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Work/Src/Gen4_R-Car_Trace32/2_Trunk/peraducm410.per
woody 6daf21a46d add
2026-06-16 12:20:14 +09:00

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; --------------------------------------------------------------------------------
; @Title: ADuCM410 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2024-07-22 KRZ
; @Manufacturer: AD
; @Doc: Generated (TRACE32, build: 171094.), based on: ADuCM410.svd (Ver. 1.0)
; @Core: Cortex-M33F
; @Chip: ADUCM410
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; ARM Limited (ARM) is supplying this software for use with Cortex-M
; processor based microcontroller, but can be equally used for other
; suitable processor architectures. This file can be freely distributed.
; Modifications to this file shall be clearly marked.
;
; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; --------------------------------------------------------------------------------
; $Id: peraducm410.per 19151 2025-03-04 13:03:16Z pegold $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main Extension"
newline
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD21=Cortex-M33"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x40068000
repeat 30. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2)++0x3
line.long 0x0 "ADCDAT[$1],ADCx Data and Flags"
hexmask.long.word 0x0 4.--19. 1. "DAT,ADCx Data"
bitfld.long 0x0 2. "RDY,Data Read Flag" "0: Data is Not Ready or Has Been Read Out,1: Data is Ready to Be Read"
newline
bitfld.long 0x0 1. "UVF,Underflow Flag" "0: Not Underflow,1: Underflow"
bitfld.long 0x0 0. "OVF,Overflow Flag" "0: Not Overflow,1: Overflow"
repeat.end
group.long 0x78++0x13
line.long 0x0 "ADCCON,ADC Configuration"
bitfld.long 0x0 20. "GPTTRIGMD,Mux Select GP Timer Trigger Mode" "0: Two Timeout Events Trigger One Conversion,1: One Timeout Events Trigger One Conversion"
hexmask.long.byte 0x0 15.--19. 1. "GPTEVENTEN,Enable GPT Event to Trigger Conversion"
newline
bitfld.long 0x0 14. "CNVIRQEN,Enable Conversion Interrupt Generation" "0,1"
bitfld.long 0x0 10.--12. "OSR,Oversampling Ratio" "0: Oversampling Disable,1: Oversampling X2,2: Oversampling X4,3: Oversampling X8,4: Oversampling X16,5: Oversampling X32,6: Oversampling Disable,7: Oversampling Disable"
newline
bitfld.long 0x0 9. "PDADC,ADC Power Down" "0: Not Power Down ADC,1: Power Down ADC"
bitfld.long 0x0 8. "VDDSEL,Select Whether Channel 29 is DVDD Channel or AVDD Channel" "0: Channel 29 is Half of DVDD Channel,1: Channel 29 is AVSS Channel"
newline
bitfld.long 0x0 7. "PDREFBUF,ADC Refbuf Power Down" "0: Normal Mode,1: Power Down Reference Mode"
bitfld.long 0x0 6. "RESTARTADC,Restart ADC Reset Analog Part of ADC" "0: Not Power Down ADC,1: Power Down ADC"
newline
bitfld.long 0x0 5. "PINMOD,PIN Conversion Mode Selection" "0: CNV is Controlled by PIN Level,1: CNV is Controlled by PIN Edge"
bitfld.long 0x0 4. "SEQDMA,DMA Request Enable for ADC Sequence Conversion" "0,1"
newline
bitfld.long 0x0 3. "CNVDMA,DMA Request Enable for ADC Non-sequence Conversion" "0,1"
bitfld.long 0x0 0.--2. "CONVTYPE,ADC Conversion Type Selection" "0: No Conversion,1: ADC Controlled by GPIO Pin,2: Software Single Conversion,3: Software Continue Conversion,4: PLA Conversion,5: GPT Triggered Conversion,?,?"
line.long 0x4 "PREBUFCON,Pre-charge Buffer Control"
bitfld.long 0x4 1. "PRGBYPN,Bypass N Channel Pre_buf" "0,1"
bitfld.long 0x4 0. "PRGBYPP,Bypass P Channel Pre_buf" "0,1"
line.long 0x8 "ADCCNVC,ADC Conversion Cycle for Positive Input Channels"
hexmask.long 0x8 0.--31. 1. "CNVC,CNV Frequency Configuration for Positive Channels"
line.long 0xC "ADCCNVCSLOW,ADC Conversion Cycle for Positive Input Channels"
hexmask.long 0xC 0.--31. 1. "CNVCSLOW,CNV Frequency Configuration for 100KSPS Channels"
line.long 0x10 "ADCCHA,ADC Channel Select"
hexmask.long.byte 0x10 5.--8. 1. "ADCCN,ADC N Channel Selection"
hexmask.long.byte 0x10 0.--4. 1. "ADCCP,ADC P Channel Selection"
rgroup.long 0x8C++0x3
line.long 0x0 "ADCIRQSTAT,ADC Interrupt Status"
bitfld.long 0x0 1. "SEQIRQSTAT,Sequence Conversion IRQ Status" "0: Interrupt Clear,1: Interrupt Set"
bitfld.long 0x0 0. "CNVIRQSTAT,Single Conversion IRQ Status" "0: Interrupt Clear,1: Interrupt Set"
group.long 0x90++0x7
line.long 0x0 "ADCSEQ,ADC Sequencer Control"
bitfld.long 0x0 3. "SEQIRQEN,Enable Sequencer Interrupt Generation" "0,1"
bitfld.long 0x0 2. "SEQSTL,Sequence Stall" "0: Running Sequence,1: Stalling Sequence"
newline
bitfld.long 0x0 1. "SEQREN,Sequence Restart" "0,1"
bitfld.long 0x0 0. "SEQEN,Sequence Enable" "0,1"
line.long 0x4 "ADCSEQC,ADC Sequencer Configuration"
hexmask.long.byte 0x4 0.--7. 1. "SEQT,Repeat Sequence Interval"
rgroup.long 0x98++0x3
line.long 0x0 "ADCSEQS,ADC Sequencer Status"
bitfld.long 0x0 2. "SEQSTAT,Sequencer Status" "0: Sequence is Idle,1: Sequence is Busy"
bitfld.long 0x0 1. "SEQSTLSTAT,Stall Sequencer Status" "0: Sequence Still Run,1: Sequence Has Stalled"
newline
bitfld.long 0x0 0. "CNVSTAT,ADC Conversion Idle/Busy Flag" "0: ADC Conversion is Idle,1: ADC Conversion is Busy"
group.long 0x9C++0x3F
line.long 0x0 "ADCSEQCH,ADC Sequencer Channel 0"
hexmask.long 0x0 0.--29. 1. "SEQCH,Sequence Channel Selection"
line.long 0x4 "ADCSEQCHMUX0,ADC Sequencer Channel 1"
bitfld.long 0x4 29. "DIF11,When AIN11 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x4 25.--28. 1. "DIF10,When AIN10 is P Ch. N Ch. Mux Selection in Sequencer Mode"
newline
bitfld.long 0x4 24. "DIF9,When AIN9 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x4 20.--23. 1. "DIF8,When AIN8 is P Ch. N Ch. Mux Selection in Sequencer Mode"
newline
bitfld.long 0x4 19. "DIF7,When AIN7 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x4 15.--18. 1. "DIF6,When AIN6 is P Ch. N Ch. Mux Selection in Sequencer Mode"
newline
bitfld.long 0x4 14. "DIF5,When AIN5 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x4 10.--13. 1. "DIF4,When AIN4 is P Ch. N Ch. Mux Selection in Sequencer Mode"
newline
bitfld.long 0x4 9. "DIF3,When AIN3 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x4 5.--8. 1. "DIF2,When AIN2 is P Ch. N Ch. Mux Selection in Sequencer Mode"
newline
bitfld.long 0x4 4. "DIF1,When AIN1 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x4 0.--3. 1. "DIF0,When AIN0 is P Ch. N Ch. Mux Selection in Sequencer Mode"
line.long 0x8 "ADCSEQCHMUX1,ADC Sequencer Channel 1"
bitfld.long 0x8 9. "DIF15,When AIN15 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x8 5.--8. 1. "DIF14,When AIN14 is P Ch. N Ch. Mux Selection in Sequencer Mode"
newline
bitfld.long 0x8 4. "DIF13,When AIN13 is N Ch. P Ch. Mux Selection in Sequencer Mode" "0: Unknown,1: Unknown"
hexmask.long.byte 0x8 0.--3. 1. "DIF12,When AIN12 is P Ch. N Ch. Mux Selection in Sequencer Mode"
line.long 0xC "ADCCMP,Digital Comparator 0 Configuration"
hexmask.long.byte 0xC 19.--23. 1. "CH,Channel Index for Data Comparison"
bitfld.long 0xC 18. "IRQEN,Enable IRQ Generation" "0,1"
newline
hexmask.long.word 0xC 2.--17. 1. "THR,Compare Threshold"
bitfld.long 0xC 1. "CMPDIR,Select Digital Comparator Direction" "0,1"
newline
bitfld.long 0xC 0. "EN,Digital Comparator Enable" "0,1"
line.long 0x10 "ADCCMPIRQSTAT,Digital Comparator Interrupt Status"
bitfld.long 0x10 11. "COMP3PLACLR,Comparator3 to PLA Clear" "0,1"
bitfld.long 0x10 10. "COMP2PLACLR,Comparator2 to PLA Clear" "0,1"
newline
bitfld.long 0x10 9. "COMP1PLACLR,Comparator1 to PLA Clear" "0,1"
bitfld.long 0x10 8. "COMP0PLACLR,Comparator0 to PLA Clear" "0,1"
newline
bitfld.long 0x10 7. "COMP3IRQCLR,Comparator3 Interrupt Clear" "0,1"
bitfld.long 0x10 6. "COMP2IRQCLR,Comparator2 Interrupt Clear" "0,1"
newline
bitfld.long 0x10 5. "COMP1IRQCLR,Comparator1 Interrupt Clear" "0,1"
bitfld.long 0x10 4. "COMP0IRQCLR,Comparator0 Interrupt Clear" "0,1"
newline
rbitfld.long 0x10 3. "COMP3IRQSTA,Comparator3 Interrupt Status" "0,1"
rbitfld.long 0x10 2. "COMP2IRQSTA,Comparator2 Interrupt Status" "0,1"
newline
rbitfld.long 0x10 1. "COMP1IRQSTA,Comparator1 Interrupt Status" "0,1"
rbitfld.long 0x10 0. "COMP0IRQSTA,Comparator0 Interrupt Status" "0,1"
line.long 0x14 "ADCOFGNDIFF,ADC Offset Gain Differential Channel Error Correction"
hexmask.long.tbyte 0x14 15.--31. 1. "OFFSET,Offset Error Correction"
hexmask.long.word 0x14 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x18 "ADCOFTEMP,ADC Offset Gain Temp Sensor Channel Error Correction"
hexmask.long.tbyte 0x18 0.--16. 1. "OFFSET,Offset Error Correction"
line.long 0x1C "ADCGNTEMP,ADC Offset Gain Temp Sensor Channel Error Correction"
hexmask.long.tbyte 0x1C 0.--19. 1. "GAIN,Gain Error Correction"
line.long 0x20 "ADCOFGNPGA0,ADC Offset Gain PGA0 Channel Error Correction"
hexmask.long.word 0x20 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x24 "ADCOFGNPGA1,ADC Offset Gain PGA1 Channel Error Correction"
hexmask.long.word 0x24 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x28 "ADCOFGNPGA2,ADC Offset Gain PGA2 Channel Error Correction"
hexmask.long.word 0x28 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x2C "ADCOFGNPGA3,ADC Offset Gain PGA3 Channel Error Correction"
hexmask.long.word 0x2C 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x30 "ADCOFGNPGA0TIA,ADC Offset Gain PGA0 Channel Error Correction"
hexmask.long.word 0x30 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x34 "ADCOFGNPGA1TIA,ADC Offset Gain PGA1 Channel Error Correction"
hexmask.long.word 0x34 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x38 "ADCOFGNPGA2TIA,ADC Offset Gain PGA2 Channel Error Correction"
hexmask.long.word 0x38 0.--14. 1. "GAIN,Gain Error Correction"
line.long 0x3C "ADCOFGNPGA3TIA,ADC Offset Gain PGA3 Channel Error Correction"
hexmask.long.word 0x3C 0.--14. 1. "GAIN,Gain Error Correction"
group.long 0x154++0xB
line.long 0x0 "ADCCMP1,Digital Comparator 1 Configuration"
hexmask.long.byte 0x0 19.--23. 1. "CH,Channel Index for Data Comparison"
bitfld.long 0x0 18. "IRQEN,Enable IRQ Generation" "0,1"
newline
hexmask.long.word 0x0 2.--17. 1. "THR,Compare Threshold"
bitfld.long 0x0 1. "CMPDIR,Select Digital Comparator Direction" "0,1"
newline
bitfld.long 0x0 0. "EN,Digital Comparator Enable" "0,1"
line.long 0x4 "ADCCMP2,Digital Comparator 2 Configuration"
hexmask.long.byte 0x4 19.--23. 1. "CH,Channel Index for Data Comparison"
bitfld.long 0x4 18. "IRQEN,Enable IRQ Generation" "0,1"
newline
hexmask.long.word 0x4 2.--17. 1. "THR,Compare Threshold"
bitfld.long 0x4 1. "CMPDIR,Select Digital Comparator Direction" "0,1"
newline
bitfld.long 0x4 0. "EN,Digital Comparator Enable" "0,1"
line.long 0x8 "ADCCMP3,Digital Comparator 3 Configuration"
hexmask.long.byte 0x8 19.--23. 1. "CH,Channel Index for Data Comparison"
bitfld.long 0x8 18. "IRQEN,Enable IRQ Generation" "0,1"
newline
hexmask.long.word 0x8 2.--17. 1. "THR,Compare Threshold"
bitfld.long 0x8 1. "CMPDIR,Select Digital Comparator Direction" "0,1"
newline
bitfld.long 0x8 0. "EN,Digital Comparator Enable" "0,1"
tree.end
tree "ALLON"
base ad:0x40005000
group.long 0x0++0xF
line.long 0x0 "PWRMOD,Power Modes"
rbitfld.long 0x0 3. "WICENACK,WIC Acknowledgment for SLEEPDEEP" "0: Unknown,1: Unknown"
bitfld.long 0x0 0.--1. "PWRMOD,Power Modes Control Bits" "0: Active Mode,1: CORE_SLEEP Mode,2: SYS_SLEEP Mode,3: Hibernate Mode"
line.long 0x4 "PWRKEY,Key Protection for PWRMOD"
hexmask.long.word 0x4 0.--15. 1. "PWRKEY,Power Control Key Register"
line.long 0x8 "RSTCFG,Reset Configuration"
bitfld.long 0x8 3. "ANA_RETAIN,Analog Block Retain Status After Watchdog or Software Reset" "0: GPIO/PLA Retain Status After Watchdog or..,1: GPIO/PLA not Retain Status After Watchdog or.."
bitfld.long 0x8 2. "LV_RETAIN,LV Die Retain Status After Watchdog or Software Reset" "0: LV Die Retain Status After Watchdog or Software..,1: LV Die not Retain Status After Watchdog or.."
newline
bitfld.long 0x8 0. "GPIO_PLA_RETAIN,GPIO/PLA Retain Their Status After WDT and Software Reset" "0: GPIO/PLA Retain Status After Watchdog or..,1: GPIO/PLA not Retain Status After Watchdog or.."
line.long 0xC "RSTKEY,Key Protection for RSTCFG"
hexmask.long.word 0xC 0.--15. 1. "RSTKEY,Reset Configuration Key Register"
group.long 0x20++0xB
line.long 0x0 "EI0CFG,External Interrupt Configuration 0"
bitfld.long 0x0 15. "IRQ3EN,External Interrupt 3 Enable Bit" "0: External Interrupt 3 Disabled,1: External Interrupt 3 Enabled"
bitfld.long 0x0 12.--14. "IRQ3MDE,External Interrupt 3 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x0 11. "IRQ2EN,External Interrupt 2 Enable Bit" "0: External Interrupt 2 Disabled,1: External Interrupt 2 Enabled"
bitfld.long 0x0 8.--10. "IRQ2MDE,External Interrupt 2 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x0 7. "IRQ1EN,External Interrupt 1 Enable Bit" "0: External Interrupt 0 Disabled,1: External Interrupt 0 Enabled"
bitfld.long 0x0 4.--6. "IRQ1MDE,External Interrupt 1 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x0 3. "IRQ0EN,External Interrupt 0 Enable Bit" "0: External Interrupt 0 Disabled,1: External Interrupt 0 Enabled"
bitfld.long 0x0 0.--2. "IRQ0MDE,External Interrupt 0 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
line.long 0x4 "EI1CFG,External Interrupt Configuration 1"
bitfld.long 0x4 15. "IRQ7EN,External Interrupt 7 Enable Bit" "0: External Interrupt 7 Disabled,1: External Interrupt 7 Enabled"
bitfld.long 0x4 12.--14. "IRQ7MDE,External Interrupt 7 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x4 11. "IRQ6EN,External Interrupt 6 Enable Bit" "0: External Interrupt 6 Disabled,1: External Interrupt 6 Enabled"
bitfld.long 0x4 8.--10. "IRQ6MDE,External Interrupt 6 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x4 7. "IRQ5EN,External Interrupt 5 Enable Bit" "0: External Interrupt 5 Disabled,1: External Interrupt 5 Enabled"
bitfld.long 0x4 4.--6. "IRQ5MDE,External Interrupt 5 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x4 3. "IRQ4EN,External Interrupt 4 Enable Bit" "0: External Interrupt 4 Disabled,1: External Interrupt 4 Enabled"
bitfld.long 0x4 0.--2. "IRQ4MDE,External Interrupt 4 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
line.long 0x8 "EI2CFG,External Interrupt Configuration 2"
bitfld.long 0x8 7. "IRQ9EN,External Interrupt 8 Enable Bit" "0: External Interrupt 8 Disabled,1: External Interrupt 8 Enabled"
bitfld.long 0x8 4.--6. "IRQ9MDE,External Interrupt 8 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
newline
bitfld.long 0x8 3. "IRQ8EN,External Interrupt 8 Enable Bit" "0: External Interrupt 8 Disabled,1: External Interrupt 8 Enabled"
bitfld.long 0x8 0.--2. "IRQ8MDE,External Interrupt 8 Mode Registers" "0: Rising Edge,1: Falling Edge,2: Rising or Falling Edge,3: High Level,4: Low Level,5: Falling Edge (same as 001),6: Rising or Falling Edge (same as 010),7: High Level (same as 011)"
group.long 0x30++0x3
line.long 0x0 "EICLR,External Interrupt Clear"
bitfld.long 0x0 9. "IRQ9,External Interrupt 9" "0: Unknown,1: Unknown"
bitfld.long 0x0 8. "IRQ8,External Interrupt 8" "0: Unknown,1: Unknown"
newline
bitfld.long 0x0 7. "IRQ7,External Interrupt 7" "0: Unknown,1: Unknown"
bitfld.long 0x0 6. "IRQ6,External Interrupt 6" "0: Unknown,1: Unknown"
newline
bitfld.long 0x0 5. "IRQ5,External Interrupt 5" "0: Unknown,1: Unknown"
bitfld.long 0x0 4. "IRQ4,External Interrupt 4" "0: Unknown,1: Unknown"
newline
bitfld.long 0x0 3. "IRQ3,External Interrupt 3" "0: Unknown,1: Unknown"
bitfld.long 0x0 2. "IRQ2,External Interrupt 2" "0: Unknown,1: Unknown"
newline
bitfld.long 0x0 1. "IRQ1,External Interrupt 1" "0: Unknown,1: Unknown"
bitfld.long 0x0 0. "IRQ0,External Interrupt 0" "0: Unknown,1: Unknown"
group.long 0x40++0x3
line.long 0x0 "RSTSTA,Reset Status"
bitfld.long 0x0 3. "SWRST,Software Reset" "0,1"
bitfld.long 0x0 2. "WDRST,Watchdog Timeout" "0,1"
newline
bitfld.long 0x0 1. "EXTRST,External Reset" "0,1"
bitfld.long 0x0 0. "POR,Power-on Reset" "0,1"
tree.end
tree "CACHE (Cache Controller)"
base ad:0x40044000
rgroup.long 0x0++0x3
line.long 0x0 "STAT,Cache Status Register"
bitfld.long 0x0 3. "CCWIPE,Code Cache Memory Wipe in Progress" "0,1"
bitfld.long 0x0 1. "CCLCK,Code Cache Lock Status" "0,1"
bitfld.long 0x0 0. "CCEN,Code Cache Enable Status" "0,1"
group.long 0x4++0x3
line.long 0x0 "SETUP,Cache Setup Register"
bitfld.long 0x0 8. "CCFLUSHDIS,Disable Automatic Cache and Buffer Flush on Any Flash Update" "0,1"
bitfld.long 0x0 0. "CCEN,Code Cache Enable" "0,1"
wgroup.long 0x8++0x7
line.long 0x0 "KEY,Cache Key Register"
hexmask.long 0x0 0.--31. 1. "KEY,Cache Key Register"
line.long 0x4 "PERFSETUP,Cache Performance Monitor Setup Register"
bitfld.long 0x4 1. "STRTCNTR,Performance Counter Start" "0,1"
bitfld.long 0x4 0. "STOPCNTR,Performance Counter Stop" "0,1"
rgroup.long 0x10++0x3
line.long 0x0 "ACCESSCNTR,Cache Miss Counter"
hexmask.long 0x0 0.--31. 1. "CNT,Cache Internal Performance Counter"
group.long 0x24++0x3
line.long 0x0 "MSTRSETUP,Cache Master Setup Register"
hexmask.long.byte 0x0 0.--7. 1. "MSTRNRA,No Read Allocate for Master"
rgroup.long 0x34++0x7
line.long 0x0 "ECCSTAT,Cache SRAM ECC Status Register"
bitfld.long 0x0 4.--6. "ECCErrorCnt,Cache SRAM ECC Error Counter" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 2.--3. "ECCHrespSta,Cache SRAM ECC Error Hresp Status" "0: No Error,1: 2 Bit Error,2: 1 Bit Error,3: Reserved"
bitfld.long 0x0 0.--1. "ECCIntSta,Cache SRAM ECC Error Interrupt Status" "0: No Error,1: 2 Bit Error,2: 1 Bit Error,3: Either 1 Bit Error or 2 Bit Error"
line.long 0x4 "ECCADDR,Cache SRAM ECC Address Register"
hexmask.long.word 0x4 0.--10. 1. "ECCAddr,Cache SRAM ECC Error Interrupt Address"
tree.end
tree "CLK (Clocking)"
base ad:0x40060000
group.long 0x0++0xB
line.long 0x0 "CLKCON0,Misc Clock Settings Register"
bitfld.long 0x0 10.--11. "ANAROOTCLKMUX,Clock Mux Select" "0: 16MHz Oscillator Clock,1: 32MHz Oscillator Clock,2: PLL Clock,3: External GPIO Clock"
bitfld.long 0x0 9. "SPLLIE,PLL Unlock and Lock Interrupt Enable" "0: PLL Interrupt Will Not Be Generated,1: PLL Interrupt Will Be Generated"
newline
bitfld.long 0x0 7.--8. "ANACLKMUX,Mux Selection Analog Clock Source" "0: Internal Oscillator is Selected (HFOSC),?,2: GPIO Clock,?"
hexmask.long.byte 0x0 2.--5. 1. "CLKOUT,GPIO CLK Out Select"
newline
bitfld.long 0x0 0.--1. "CLKMUX,Clock Mux Select" "0: High Frequency Internal Oscillator (HFOSC),1: System PLL is Selected (160 MHz),?,3: External GPIO Port is Selected (ECLKIN)"
line.long 0x4 "CLKCON1,Clock Dividers Register"
bitfld.long 0x4 9.--11. "CDADCCLK,ADCCLK Divide Bits" "0: DIV1. Divide by 1 (ADCCLK is Equal to Root Clock),1: DIV2. Divide by 2 (ADCCLK is Half the Frequency..,2: DIV4. Divide by 4 (ADCCLK is Quarter the..,3: DIV8. Divide by 8,4: DIV16. Divide by 16,5: DIV32. Divide by 32,6: DIV64. Divide by 164,7: DIV128. Divide by 128"
bitfld.long 0x4 6.--8. "CDPCLK1,APB1 PCLK Divide Bits" "0: DIV1. Divide by 1 (PCLK is Equal to Root Clock),1: DIV2. Divide by 2 (PCLK is Half the Frequency of..,2: DIV4. Divide by 4 (PCLK is Quarter the Frequency..,3: DIV8. Divide by 8,4: DIV16. Divide by 16,5: DIV32. Divide by 32,6: DIV64. Divide by 164,7: DIV128. Divide by 128"
newline
bitfld.long 0x4 3.--5. "CDPCLK0,APB0 PCLK Divide Bits" "0: DIV1. Divide by 1 (PCLK is Equal to Root Clock),1: DIV2. Divide by 2 (PCLK is Half the Frequency of..,2: DIV4. Divide by 4 (PCLK is Quarter the Frequency..,3: DIV8. Divide by 8,4: DIV16. Divide by 16,5: DIV32. Divide by 32,6: DIV64. Divide by 164,7: DIV128. Divide by 128"
bitfld.long 0x4 0.--2. "CDHCLK,HCLK Divide Bits" "0: DIV1. Divide by 1 (HCLK is Equal to Root Clock),1: DIV2. Divide by 2 (HCLK is Half the Frequency of..,2: DIV4. Divide by 4 (HCLK is Quarter the Frequency..,3: DIV8. Divide by 8,4: DIV16.Divide by 16,5: DIV32.Divide by 32,6: DIV64.Divide by 64,7: DIV128. Divide by 128"
line.long 0x8 "CLKSTAT0,Clocking Status"
rbitfld.long 0x8 4. "SPLLUNLOCK,Sticky System PLL Unlock Flag" "0: No PLL Lock Event Was Detected,1: A PLL Lock Event Was Detected"
rbitfld.long 0x8 3. "SPLLLOCK,Sticky System PLL Lock Flag" "0: No PLL Lock Event Was Detected,1: A PLL Lock Event Was Detected"
newline
bitfld.long 0x8 2. "SPLLUNLOCKCLR,System PLL Unlock" "0: No Loss of PLL Lock Was Detected,1: A PLL Loss of Lock Was Detected"
bitfld.long 0x8 1. "SPLLLOCKCLR,System PLL Lock" "0: No PLL Lock Event Was Detected,1: A PLL Lock Event Was Detected"
newline
rbitfld.long 0x8 0. "SPLLSTATUS,System PLL Status" "0: The PLL is Not Locked or Not Properly..,1: The PLL is Locked and is Ready for Use as the.."
tree.end
tree "COMP (Analog Comparators)"
base ad:0x40068A00
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "COMPCON[$1],Unknown"
bitfld.long 0x0 19.--20. "INTMODE,Interrupt Mode" "0: Generate Interrupt if Rising Edge Happens,1: Generate Interrupt if Falling Edge Happens,2: Generate Interrupt if Low Level Happens,3: Generate Interrupt if High Level Happens"
bitfld.long 0x0 18. "INTEN,Interrupt Enable" "0,1"
newline
bitfld.long 0x0 17. "EN,Enable Comparator" "0,1"
bitfld.long 0x0 13.--15. "INPOS,Select Comparator Positive Input Source" "0: All Input Switches Off,1: Enable AIN8/10/12/14 for comp 0/1/2/3,2: Enable PGA0/1/2/3 for comp 0/1/2/3,3: Enable GPIO0.6/0.7/2.0/2.1 Analog Signal Input..,?,?,?,?"
newline
bitfld.long 0x0 10.--12. "INNEG,Select Comparator Negative Input Source" "0: All Input Switches Off,1: Enable Half Avdd Input,2: Enable AIN9/11/13/15 for Comp 0/1/2/3,3: Enable VDAC8 Input,4: Enable VDAC9 Input,5: Enable VDAC10 Input,6: Enable VDAC11 Input,7: Enable 1.25V Ref Input from AIN15(BUF1)"
bitfld.long 0x0 8.--9. "OUT,Comp Interrupt Select" "0: Output to Test Pad Disable,1: Output to Test Pad Disable,2: Output to Test Pad Enable,3: Output to Test Pad Disable"
newline
bitfld.long 0x0 7. "INV,Select Output Logic State" "0: Output is High if +ve is higher than -ve input,1: Output is High if -ve is higher than +ve input"
hexmask.long.byte 0x0 0.--4. 1. "HYS,Comp Hysteresis Register"
repeat.end
rgroup.long 0x10++0x3
line.long 0x0 "COMPIRQSTAT,Unknown"
bitfld.long 0x0 3. "COMP3,Comparator 3 Interrupt Status" "0,1"
bitfld.long 0x0 2. "COMP2,Comparator 2 Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "COMP1,Comparator 1 Interrupt Status" "0,1"
bitfld.long 0x0 0. "COMP0,Comparator 0 Interrupt Status" "0,1"
tree.end
tree "CRC (Cyclic Redundancy Check)"
base ad:0x40066000
group.long 0x0++0x3
line.long 0x0 "CTL,CRC Control Register"
hexmask.long.byte 0x0 28.--31. 1. "RevID,Revision ID"
bitfld.long 0x0 4. "W16SWP,Word16 Swap" "0,1"
bitfld.long 0x0 3. "BYTMIRR,Byte Mirroring" "0,1"
bitfld.long 0x0 2. "BITMIRR,Bit Mirroring" "0,1"
bitfld.long 0x0 1. "LSBFIRST,LSB First Calculation Order" "0,1"
bitfld.long 0x0 0. "EN,CRC Peripheral Enable" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "IPDATA,Input Data Word Register"
hexmask.long 0x0 0.--31. 1. "DATA_WORD,Data Input."
group.long 0x8++0x7
line.long 0x0 "RESULT,CRC Result Register"
hexmask.long 0x0 0.--31. 1. "RESIDUE,CRC Residue"
line.long 0x4 "POLY,Programmable CRC Polynomial"
hexmask.long 0x4 0.--31. 1. "REDUCTION_POLY,CRC Reduction Polynomial"
tree.end
tree "DMA (Direct Memory Access Controller)"
base ad:0x40040000
rgroup.long 0x0++0x3
line.long 0x0 "STAT,DMA Status"
hexmask.long.byte 0x0 16.--20. 1. "CHANM1,Number of Available DMA Channels Minus 1"
bitfld.long 0x0 0. "MEN,Enable Status of the Controller" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "CFG,DMA Configuration"
bitfld.long 0x0 0. "MEN,Controller Enable" "0,1"
group.long 0x8++0x3
line.long 0x0 "PDBPTR,DMA Channel Primary Control Data Base Pointer"
hexmask.long 0x0 0.--31. 1. "ADDR,Pointer to the Base Address of the Primary Data Structure"
rgroup.long 0xC++0x3
line.long 0x0 "ADBPTR,DMA Channel Alternate Control Data Base Pointer"
hexmask.long 0x0 0.--31. 1. "ADDR,Base Address of the Alternate Data Structure"
wgroup.long 0x14++0x3
line.long 0x0 "SWREQ,DMA Channel Software Request"
hexmask.long 0x0 0.--30. 1. "CHAN,Generate Software Request"
group.long 0x20++0x3
line.long 0x0 "RMSKSET,DMA Channel Request Mask Set"
hexmask.long 0x0 0.--30. 1. "CHAN,Mask Requests from DMA Channels"
wgroup.long 0x24++0x3
line.long 0x0 "RMSKCLR,DMA Channel Request Mask Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Clear REQ_MASK_SET Bits in DMARMSKSET"
group.long 0x28++0x3
line.long 0x0 "ENSET,DMA Channel Enable Set"
hexmask.long 0x0 0.--30. 1. "CHAN,Enable DMA Channels"
wgroup.long 0x2C++0x3
line.long 0x0 "ENCLR,DMA Channel Enable Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Disable DMA Channels"
group.long 0x30++0x3
line.long 0x0 "ALTSET,DMA Channel Primary-alternate Set"
hexmask.long 0x0 0.--30. 1. "CHAN,Control Structure Status / Select Alt Structure"
wgroup.long 0x34++0xB
line.long 0x0 "ALTCLR,DMA Channel Primary-alternate Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Select Primary Data Structure"
line.long 0x4 "PRISET,DMA Channel Priority Set"
hexmask.long 0x4 0.--30. 1. "CHAN,Configure Channel for High Priority"
line.long 0x8 "PRICLR,DMA Channel Priority Clear"
hexmask.long 0x8 0.--30. 1. "CHPRICLR,Configure Channel for Default Priority Level"
group.long 0x48++0xB
line.long 0x0 "ERRCHNLCLR,DMA per Channel Error Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Per Channel Bus Error Status/ Clear"
line.long 0x4 "ERRCLR,DMA Bus Error Clear"
hexmask.long 0x4 0.--30. 1. "CHAN,Bus Error Status"
line.long 0x8 "INVALIDDESCCLR,DMA per Channel Invalid Descriptor Clear"
hexmask.long 0x8 0.--30. 1. "CHAN,Per Channel Invalid Descriptor Status"
group.long 0x800++0x3
line.long 0x0 "BSSET,DMA Channel Bytes Swap Enable Set"
hexmask.long 0x0 0.--30. 1. "CHAN,Byte Swap Status"
wgroup.long 0x804++0x3
line.long 0x0 "BSCLR,DMA Channel Bytes Swap Enable Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Disable Byte Swap"
group.long 0x810++0x3
line.long 0x0 "SRCADDRSET,DMA Channel Source Address Decrement Enable Set"
hexmask.long 0x0 0.--30. 1. "CHAN,Source Address Decrement Status / Configure"
wgroup.long 0x814++0x3
line.long 0x0 "SRCADDRCLR,DMA Channel Source Address Decrement Enable Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Disable Source Address Decrement"
group.long 0x818++0x3
line.long 0x0 "DSTADDRSET,DMA Channel Destination Address Decrement Enable Set"
hexmask.long 0x0 0.--30. 1. "CHAN,Destination Address Decrement Status"
wgroup.long 0x81C++0x3
line.long 0x0 "DSTADDRCLR,DMA Channel Destination Address Decrement Enable Clear"
hexmask.long 0x0 0.--30. 1. "CHAN,Disable Destination Address Decrement"
rgroup.long 0xFE0++0x3
line.long 0x0 "REVID,DMA Controller Revision ID"
hexmask.long.byte 0x0 0.--7. 1. "DMAREVID,DMA Controller Revision ID"
tree.end
tree "DMAREQ"
base ad:0x40007000
group.long 0x0++0x17
line.long 0x0 "REQEN,GPT/GPT32 and PLA DMA Request Enable"
bitfld.long 0x0 1. "GPLA_DMA_EN1,GPT/GPT32 and PLA DMA Request 1 Enable" "0,1"
bitfld.long 0x0 0. "GPLA_DMA_EN0,GPT/GPT32 and PLA DMA Request 0 Enable" "0,1"
line.long 0x4 "REQ0SEL,GPT/GPT32 and PLA DMA Request 0 Select"
hexmask.long.byte 0x4 0.--3. 1. "DMA_REQ0_SEL,GPT/GPT32 and PLA DMA Request 0 Source Select"
line.long 0x8 "REQ1SEL,GPT/GPT32 and PLA DMA Request 1 Select"
hexmask.long.byte 0x8 0.--3. 1. "DMA_REQ1_SEL,GPT/GPT32 and PLA DMA Request 1 Source Select"
line.long 0xC "PLAREQEN,PLA DMA Requests Enable"
bitfld.long 0xC 3. "PLA_DMA_REQ3_EN,PLA DMA Request 3 Enable" "0,1"
bitfld.long 0xC 2. "PLA_DMA_REQ2_EN,PLA DMA Request 2 Enable" "0,1"
newline
bitfld.long 0xC 1. "PLA_DMA_REQ1_EN,PLA DMA Request 1 Enable" "0,1"
bitfld.long 0xC 0. "PLA_DMA_REQ0_EN,PLA DMA Request 0 Enable" "0,1"
line.long 0x10 "GPTREQEN,GPT/GPT32 DMA Requests Enable"
bitfld.long 0x10 4. "GPTH1DMAEN,GPT32 1 DMA Request Enable" "0,1"
bitfld.long 0x10 3. "GPTH0DMAEN,GPT32 0 DMA Request Enable" "0,1"
newline
bitfld.long 0x10 2. "GPT2DMAEN,GPT 2 DMA Request Enable" "0,1"
bitfld.long 0x10 1. "GPT1DMAEN,GPT 1 DMA Request Enable" "0,1"
newline
bitfld.long 0x10 0. "GPT0DMAEN,GPT 0 DMA Request Enable" "0,1"
line.long 0x14 "GPT_REQ_TYPE,GPT and GPT32 Require Type"
bitfld.long 0x14 8.--9. "GPT32_REQ1_TYPE,GPT32 Req1 DMA Require Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and Rising Edge..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Falling Edge.."
bitfld.long 0x14 6.--7. "GPT32_REQ0_TYPE,GPT32 Req0 DMA Require Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and Rising Edge..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Falling Edge.."
newline
bitfld.long 0x14 4.--5. "GPT_REQ2_TYPE,GPT Req2 DMA Require Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and Rising Edge..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Falling Edge.."
bitfld.long 0x14 2.--3. "GPT_REQ1_TYPE,GPT Req1 DMA Require Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and Rising Edge..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Falling Edge.."
newline
bitfld.long 0x14 0.--1. "GPT_REQ0_TYPE,GPT Req0 DMA Require Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and Rising Edge..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Falling Edge.."
tree.end
tree "FLASH (Flash Controller)"
base ad:0x40048000
rgroup.long 0x0++0x3
line.long 0x0 "FEESTA,Status Register"
bitfld.long 0x0 29.--30. "ECCERRCNTD1,ECC Error Count via DMA Bus of Flash 1" "0,1,2,3"
bitfld.long 0x0 27.--28. "ECCHRESPDMA,ECC Error Response on DMA Bus" "0: No Error. Successful Read from Program Flash via..,1: During AHB Read to Flash 2 Bit Error Detected..,2: 1 Bit Error is Corrected for One Flash Location..,3: Reserved"
newline
bitfld.long 0x0 25.--26. "ECCHRESPCODE,ECC Error Response on CODE Bus" "0: No Error. Successful Read from Program Flash via..,1: During AHB Read to Flash 2 Bit Error Detected..,2: 1 Bit Error is Corrected for One Flash Location..,3: Reserved"
bitfld.long 0x0 22.--24. "ECCERRCNTC1,ECC Error Count via CODE Bus of Flash 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20.--21. "ECCERRCNTD0,ECC Error Count via DMA Bus of Flash 0" "0,1,2,3"
bitfld.long 0x0 17.--19. "ECCERRCNTC0,ECC Error Count via CODE Bus of Flash 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15.--16. "ECCERRINITSIGN,ECC Error on Initial Info Signature Check" "0: No Error Successful Flash Read Operation During..,1: During Initial Signature Check 2 Bit Error..,2: 1 Bit Error is Corrected for One Flash Location..,3: During Initial Signature Command 1 Bit Error and.."
bitfld.long 0x0 14. "INIT,Initialization Upload in Progress." "0,1"
newline
bitfld.long 0x0 13. "SIGNERR,Initial Signature Check Error on Info Space" "0,1"
bitfld.long 0x0 11.--12. "ECCREADERRFLSH1,ECC Interrupt Errors During AHB Read to Flash 1." "0: No Error. Successful Read from Data Flash via..,1: 1 Bit Error is Corrected for One Flash Location..,2: During AHB Read to Flash 2 Bit Error Detected..,3: During AHB Read It is Either ECC Error or ECC.."
newline
bitfld.long 0x0 9.--10. "ECCREADERRFLSH0,ECC Interrupt Errors During AHB Read to Flash 0." "0: No Error. Successful Read from Program Flash via..,1: During AHB Read to Flash 2 Bit Error Detected..,2: 1 Bit Error is Corrected for One Flash Location..,3: During AHB Read It is Either ECC Error or ECC.."
bitfld.long 0x0 7.--8. "ECCERRCMD,ECC Errors Produced During Signature Commands" "0: No Error Successful Flash Read Operation During..,1: During Signature Commands 2 Bit Error is..,2: 1 Bit Error is Corrected for One or More Flash..,3: During Signature Commands 1 Bit Error and 2 Bit.."
newline
bitfld.long 0x0 4.--5. "CMDFAIL,Command Failed" "0: Successful Completion of a Command or a Write,1: Attempted Signcheck write or Erase of a..,2: Read Verify Error,3: Indicates That a Command or a Write Was Aborted.."
bitfld.long 0x0 3. "WRALCOMP,Write Almost Complete - Key-hole Registers Open for Access" "0,1"
newline
bitfld.long 0x0 2. "CMDCOMP,Command Complete" "0,1"
bitfld.long 0x0 1. "WRCLOSE,Key-hole Registers Closed for Access" "0,1"
newline
bitfld.long 0x0 0. "CMDBUSY,Command Busy." "0,1"
group.long 0x4++0x1B
line.long 0x0 "FEECON0,Command Control Register - Interrupt Enable Register"
bitfld.long 0x0 2. "IENERR,Command Fail Interrupt Enable" "0,1"
bitfld.long 0x0 1. "IWRALCOMP,Write Almost Complete Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "IENCMD,Command Complete Interrupt Enable" "0,1"
line.long 0x4 "FEECMD,Command Register"
hexmask.long.byte 0x4 0.--4. 1. "CMD,Commands"
line.long 0x8 "FEEFLADR,Flash Address Key - Hole Register"
hexmask.long.tbyte 0x8 3.--20. 1. "FLAddr,Memory Mapped Address for the Flash Location"
line.long 0xC "FEEFLDATA0,Flash Data Register - Key - Hole Interface Lower 32 Bits"
hexmask.long 0xC 0.--31. 1. "FLData0,Lower 32 Bit of 64 Bit Data to Be Written to Flash"
line.long 0x10 "FEEFLDATA1,Flash Data Register - Key - Hole Interface Upper 32 Bits"
hexmask.long 0x10 0.--31. 1. "FLData1,Upper 32 Bit of 64 Bit Data to Be Written to Flash"
line.long 0x14 "FEEADR0,Lower Page Address"
hexmask.long.byte 0x14 13.--20. 1. "PageAddr0,Page Address 0"
line.long 0x18 "FEEADR1,Upper Page Address"
hexmask.long.byte 0x18 13.--20. 1. "PageAddr1,Page Address 1"
wgroup.long 0x20++0x3
line.long 0x0 "FEEKEY,Flash Key Register."
hexmask.long 0x0 0.--31. 1. "KEY,Key Register"
group.long 0x28++0x7
line.long 0x0 "FEEPRO0,Write Protection Register for Flash0"
hexmask.long 0x0 0.--31. 1. "WrProt0,Write Protection for Flash0 - 32 Bits."
line.long 0x4 "FEEPRO1,Write Protection Register for Flash1"
hexmask.long 0x4 0.--31. 1. "WrProt1,Write Protection for Flash1 - 32 Bits."
rgroup.long 0x34++0x3
line.long 0x0 "FEESIG,Flash Signature"
hexmask.long.tbyte 0x0 0.--23. 1. "Sign,Signature"
group.long 0x38++0x3
line.long 0x0 "FEECON1,User Setup Register"
rbitfld.long 0x0 8. "SwapInFlashEn,Swap Inside Flash Enable" "0,1"
bitfld.long 0x0 6. "SwapFlash1,Swap Top and Bottom Image Inside Flash 1." "0,1"
newline
bitfld.long 0x0 5. "SwapFlash0,Swap Top and Bottom Image Inside Flash 0." "0,1"
rbitfld.long 0x0 4. "MDIOmode,MDIO Mode" "0,1"
newline
bitfld.long 0x0 3. "SwapProgramCode,Swap Program Code for MDIO Mode." "0,1"
bitfld.long 0x0 2. "AutoIncrEn,Auto Address Increment for Key Hole Access." "0,1"
newline
bitfld.long 0x0 1. "KHDMAEn,Key - Hole DMA Enable." "0,1"
bitfld.long 0x0 0. "JtagDebugEn,JTAG Debug Enable" "0,1"
rgroup.long 0x40++0x3
line.long 0x0 "FEEWRADDRA,Write Abort Address Register"
hexmask.long 0x0 0.--31. 1. "WrAbortAddr,Write Abort Address"
group.long 0x48++0xB
line.long 0x0 "FEEAEN0,Lower 32 Bits of the Sys Irq Abort Enable Register."
hexmask.long 0x0 0.--31. 1. "SysIrqAbortEn,Lower 32 Bits of System Interrupt Abort Enable."
line.long 0x4 "FEEAEN1,Middle 32 Bits of the Sys Irq Abort Enable Register."
hexmask.long 0x4 0.--31. 1. "SysIrqAbortEn,Middle 32 Bits of System Interrupt Abort Enable."
line.long 0x8 "FEEAEN2,Upper 32 Bits of the Sys Irq Abort Enable Register."
hexmask.long 0x8 0.--31. 1. "SysIrqAbortEn,Upper 32 Bits of System Interrupt Abort Enable."
group.long 0x64++0x3
line.long 0x0 "FEEECCCONFIG,Configurable ECC Enable/disable. Error Response"
bitfld.long 0x0 5.--6. "ECCAddrCon,ECC Error Address Control Bit." "0: ECC Error Address Register Can't Be Cleared..,1: ECC Error Address Register Can't Be Cleared..,2: Previous ECC Error Address Register is Cleared..,3: Previous ECC Error Address Register is Cleared.."
bitfld.long 0x0 3.--4. "ECCIntrERROR,Interrupt Enable When a ECC Error Happens During an AHB Read" "0: Interrupt is Not Generated Even If There is an..,1: Interrupt is Generated Only If 2 Bit Error is..,2: Interrupt is Generated Only If 1 Bit Error..,3: Interrupt is Generated If Either 2 Bit Detected.."
newline
bitfld.long 0x0 1.--2. "ECCAHBERROR,Signifies How to Generate AHB Error on ECC" "0: AHB Error (HRESP = 1) is Not Generated Even If..,1: AHB Error (HRESP = 1) is Generated Only If 2 Bit..,2: AHB Error (HRESP = 1) is Generated Only If 1 Bit..,3: AHB Error (HRESP = 1) is Generated If Either 2.."
bitfld.long 0x0 0. "ECCDisable,ECC Disable Bit." "0,1"
rgroup.long 0x74++0x7
line.long 0x0 "FEEECCADDRC0,Flash 0 ECC Error Address via CODE Bus"
hexmask.long.tbyte 0x0 0.--20. 1. "FLECCAddrC0,Flash0 Address for Which ECC Error is Detected via CODE Bus."
line.long 0x4 "FEEECCADDRC1,Flash 1 ECC Error Address via CODE Bus"
hexmask.long.tbyte 0x4 0.--20. 1. "FLECCAddrC1,Flash1 Address for Which ECC Error is Detected via CODE Bus."
rgroup.long 0x94++0x7
line.long 0x0 "FEEECCADDRD0,Flash 0 ECC Error Address via DMA Bus"
hexmask.long.tbyte 0x0 0.--20. 1. "FLECCAddrD0,Flash0 Address for Which ECC Error is Detected via DMA Bus."
line.long 0x4 "FEEECCADDRD1,Flash 1 ECC Error Address via DMA Bus"
hexmask.long.tbyte 0x4 0.--20. 1. "FLECCAddrD1,Flash1 Address for Which ECC Error is Detected via DMA Bus."
tree.end
tree "GPIO (General-Purpose Inputs/Outputs)"
base ad:0x40050000
group.long 0x0++0xB
line.long 0x0 "GP0CON,GPIO Port 0 Configuration"
bitfld.long 0x0 14.--15. "CON7,P0.7 Configuration Bits" "0: GPIO,1: I2C2 SDA,2: Comparator Data Input 1,3: PLAO[5]"
bitfld.long 0x0 12.--13. "CON6,P0.6 Configuration Bits" "0: GPIO,1: I2C2 SCL,2: Comparator Data Input 0,3: PLAO[4]"
bitfld.long 0x0 10.--11. "CON5,P0.5 Configuration Bits" "0: GPIO,1: I2C0 SDA,2: UART0 SOUT,3: PLAO[3]"
newline
bitfld.long 0x0 8.--9. "CON4,P0.4 Configuration Bits" "0: GPIO,1: I2C0 SCL,2: UART0 SIN,3: PLAO[2]"
bitfld.long 0x0 6.--7. "CON3,P0.3 Configuration Bits" "0: GPIO/IRQ0,1: SPI0 CS,2: PLA CLK0,3: PLAI[3]"
bitfld.long 0x0 4.--5. "CON2,P0.2 Configuration Bits" "0: GPIO,1: SPI0 MOSI,2: PLA Clock 1,3: PLAI[2]"
newline
bitfld.long 0x0 2.--3. "CON1,P0.1 Configuration Bits" "0: GPIO,1: SPI0 MISO,2: Comparater Output,3: PLAI[1]"
bitfld.long 0x0 0.--1. "CON0,P0.0 Configuration Bits" "0: GPIO,1: SPI0 SCLK,2: Comparater Output,3: PLAI[0]"
line.long 0x4 "GP0OE,GPIO Port 0 Output Enable"
hexmask.long.byte 0x4 0.--7. 1. "OE,Open Drain Enable"
line.long 0x8 "GP0IE,GPIO Port 0 Input Path Enable"
hexmask.long.byte 0x8 0.--7. 1. "IE,Input Enable"
rgroup.long 0xC++0x3
line.long 0x0 "GP0IN,GPIO Port 0 Registered Data Input"
hexmask.long.byte 0x0 0.--7. 1. "Y,Data Input from Pad"
group.long 0x10++0x3
line.long 0x0 "GP0OUT,GPIO Port 0 Data Output"
hexmask.long.byte 0x0 0.--7. 1. "A,Data Output to Pad"
wgroup.long 0x14++0xB
line.long 0x0 "GP0SET,GPIO Port 0 Data Out Set"
hexmask.long.byte 0x0 0.--7. 1. "SETUP,Set the Output HIGH for the Pin"
line.long 0x4 "GP0CLR,GPIO Port 0 Data Out Clear"
hexmask.long.byte 0x4 0.--7. 1. "CLR,Set the Output Low for the Port Pin"
line.long 0x8 "GP0TGL,GPIO Port 0 Pin Toggle"
hexmask.long.byte 0x8 0.--7. 1. "TGL,Toggle the Output of the Port Pin"
group.long 0x20++0x2B
line.long 0x0 "GP0ODE,GPIO Port 0 Open Drain Enable"
hexmask.long.byte 0x0 0.--7. 1. "ODE,Open Drain Enable"
line.long 0x4 "GP0IS,GPIO Port 0 Input Select"
hexmask.long.byte 0x4 0.--7. 1. "ISEL,Input Select"
line.long 0x8 "GP0PE,GPIO Port 0 Pull Enable"
hexmask.long.byte 0x8 0.--7. 1. "PE,Pull Enable"
line.long 0xC "GP0PS,GPIO Port 0 Pull Select"
hexmask.long.byte 0xC 0.--7. 1. "PS,Pull Select"
line.long 0x10 "GP0SR,GPIO Port 0 Slew Rate"
hexmask.long.byte 0x10 0.--7. 1. "SR,Slew Rate"
line.long 0x14 "GP0DS,GPIO Port 0 Drive Select"
bitfld.long 0x14 14.--15. "DS7,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 12.--13. "DS6,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 10.--11. "DS5,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 8.--9. "DS4,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 6.--7. "DS3,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 4.--5. "DS2,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 2.--3. "DS1,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 0.--1. "DS0,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
line.long 0x18 "GP0PWR,GPIO Port 0 Power Select"
hexmask.long.byte 0x18 0.--3. 1. "PWR,Pad Power Select"
line.long 0x1C "GP0POL,GPIO Interrupt Polarity Select"
hexmask.long.byte 0x1C 0.--7. 1. "INTPOL,Parametric Output"
line.long 0x20 "GP0IENA,InterruptA Enable"
hexmask.long.byte 0x20 0.--7. 1. "INTAEN,InterruptA Enable"
line.long 0x24 "GP0IENB,InterruptB Enable"
hexmask.long.byte 0x24 0.--7. 1. "INTBEN,InterruptA Enable"
line.long 0x28 "GP0INT,Interrupt Status"
hexmask.long.byte 0x28 0.--7. 1. "INTSTATUS,Interrupt Status"
group.long 0x50++0xB
line.long 0x0 "GP1CON,GPIO Port 1 Configuration"
bitfld.long 0x0 14.--15. "CON7,P1.7 Configuration Bits" "0: GPIO/IRQ1,1: SPI1 CS,2: PWM5,3: PLAO[13]"
bitfld.long 0x0 12.--13. "CON6,P1.6 Configuration Bits" "0: GPIO,1: SPI1 MOSI,2: PWM4,3: PLAO[12]"
bitfld.long 0x0 10.--11. "CON5,P1.5 Configuration Bits" "0: GPIO,1: SPI1 MISO,2: PWM3,3: PLAO[11]"
newline
bitfld.long 0x0 8.--9. "CON4,P1.4 Configuration Bits" "0: GPIO,1: SPI1 SCLK,2: PWM2,3: PLAO[10]"
bitfld.long 0x0 6.--7. "CON3,P1.3 Configuration Bits" "0: GPIO,1: I2C1 SDA,2: PWM1,3: PLAI[7]"
bitfld.long 0x0 4.--5. "CON2,P1.2 Configuration Bits" "0: GPIO,1: I2C1 SCL,2: PWM,3: PLAI6]"
newline
bitfld.long 0x0 2.--3. "CON1,P1.1 Configuration Bits" "0: GPIO,1: UART 1 SOUT,2: Comparater Output 3,3: PLAI[5]"
bitfld.long 0x0 0.--1. "CON0,P1.0 Configuration Bits" "0: GPIO,1: UART1 SIN,2: Comparater Output 2,3: PLAI[4]"
line.long 0x4 "GP1OE,GPIO Port 1 Output Enable"
hexmask.long.byte 0x4 0.--7. 1. "OE,Output Enable"
line.long 0x8 "GP1IE,GPIO Port 1 Input Path Enable"
hexmask.long.byte 0x8 0.--7. 1. "IE,Input Enable"
rgroup.long 0x5C++0x3
line.long 0x0 "GP1IN,GPIO Port 1 Registered Data Input"
hexmask.long.byte 0x0 0.--7. 1. "Y,Data Input from Pad"
group.long 0x60++0x3
line.long 0x0 "GP1OUT,GPIO Port 1 Data Output"
hexmask.long.byte 0x0 0.--7. 1. "A,Data Output to Pad"
wgroup.long 0x64++0xB
line.long 0x0 "GP1SET,GPIO Port 1 Data Out Set"
hexmask.long.byte 0x0 0.--7. 1. "SETUP,Set the Output HIGH for the Pin"
line.long 0x4 "GP1CLR,GPIO Port 1 Data Out Clear"
hexmask.long.byte 0x4 0.--7. 1. "CLR,Set the Output Low for the Port Pin"
line.long 0x8 "GP1TGL,GPIO Port 1 Pin Toggle"
hexmask.long.byte 0x8 0.--7. 1. "TGL,Toggle the Output of the Port Pin"
group.long 0x70++0x2B
line.long 0x0 "GP1ODE,GPIO Port 1 Open Drain Enable"
hexmask.long.byte 0x0 0.--7. 1. "ODE,Open Drain Enable"
line.long 0x4 "GP1IS,GPIO Port 1 Input Select"
hexmask.long.byte 0x4 0.--7. 1. "ISEL,Input Select"
line.long 0x8 "GP1PE,GPIO Port 1 Pull Enable"
hexmask.long.byte 0x8 0.--7. 1. "PE,Pull Enable"
line.long 0xC "GP1PS,GPIO Port 1 Pull Select"
hexmask.long.byte 0xC 0.--7. 1. "PS,Pull Select"
line.long 0x10 "GP1SR,GPIO Port 1 Slew Rate"
hexmask.long.byte 0x10 0.--7. 1. "SR,Slew Rate"
line.long 0x14 "GP1DS,GPIO Port 1 Drive Select"
bitfld.long 0x14 14.--15. "DS7,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 12.--13. "DS6,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 10.--11. "DS5,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 8.--9. "DS4,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 6.--7. "DS3,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 4.--5. "DS2,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 2.--3. "DS1,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 0.--1. "DS0,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
line.long 0x18 "GP1PWR,GPIO Port 1 Power Select"
hexmask.long.byte 0x18 0.--7. 1. "PWR,Pad Power Select"
line.long 0x1C "GP1POL,GPIO Interrupt Polarity Select"
hexmask.long.byte 0x1C 0.--7. 1. "INTPOL,Parametric Output"
line.long 0x20 "GP1IENA,InterruptA Enable"
hexmask.long.byte 0x20 0.--7. 1. "INTAEN,InterruptA Enable"
line.long 0x24 "GP1IENB,InterruptB Enable"
hexmask.long.byte 0x24 0.--7. 1. "INTBEN,InterruptB Enable"
line.long 0x28 "GP1INT,Interrupt Status"
hexmask.long.byte 0x28 0.--7. 1. "INTSTATUS,Interrupt Status"
group.long 0xA0++0xB
line.long 0x0 "GP2CON,GPIO Port 2 Configuration"
bitfld.long 0x0 14.--15. "CON7,P2.7 Configuration Bits" "0: GPIO/IRQ6,1: SPI 2 CS,2: I2C1 SDA of ITLA package,3: PLAO[21]"
bitfld.long 0x0 12.--13. "CON6,P2.6 Configuration Bits" "0: GPIO/IRQ5,1: SPI 2 SCLK,2: I2C1 SCL of ITLA Package,3: PLAO[20]"
bitfld.long 0x0 10.--11. "CON5,P2.5 Configuration Bits" "0: GPIO,1: Spi2 Miso,2: UART1 TX of ITLA package,3: PLAO[19]"
newline
bitfld.long 0x0 8.--9. "CON4,P2.4 Configuration Bits" "0: GPIO/IRQ4,1: SPI2 MOSI,2: UART1 RX of ITLA package,3: PLAO[18]"
bitfld.long 0x0 6.--7. "CON3,P2.3 Configuration Bits" "0: GPIO/BM,?,?,3: PLAI[10]"
bitfld.long 0x0 4.--5. "CON2,P2.2 Configuration Bits" "0: GPIO,1: Power Reset,2: Clock Output,3: Serial Wire Output"
newline
bitfld.long 0x0 2.--3. "CON1,P2.1 Configuration Bits" "0: GPIO/IRQ2,1: External Clock in,2: Comparater Data Input,3: PLAI[9]"
bitfld.long 0x0 0.--1. "CON0,P2.0 Configuration Bits" "0: GPIO,1: ADC Convert,2: Comparator Data Input 2,3: PLA GPIO Input[8]"
line.long 0x4 "GP2OE,GPIO Port 2 Output Enable"
hexmask.long.byte 0x4 0.--7. 1. "OE,Output Enable"
line.long 0x8 "GP2IE,GPIO Port 2 Input Path Enable"
hexmask.long.byte 0x8 0.--7. 1. "IE,Input Enable"
rgroup.long 0xAC++0x3
line.long 0x0 "GP2IN,GPIO Port 2 Registered Data Input"
hexmask.long.byte 0x0 0.--7. 1. "Y,Data Input from Pad"
group.long 0xB0++0x3
line.long 0x0 "GP2OUT,GPIO Port 2 Data Output"
hexmask.long.byte 0x0 0.--7. 1. "A,Data Output to Pad"
wgroup.long 0xB4++0xB
line.long 0x0 "GP2SET,GPIO Port 2 Data Out Set"
hexmask.long.byte 0x0 0.--7. 1. "SETUP,Set the Output HIGH for the Pin"
line.long 0x4 "GP2CLR,GPIO Port 2 Data Out Clear"
hexmask.long.byte 0x4 0.--7. 1. "CLR,Set the Output Low for the Port Pin"
line.long 0x8 "GP2TGL,GPIO Port 2 Pin Toggle"
hexmask.long.byte 0x8 0.--7. 1. "TGL,Toggle the Output of the Port Pin"
group.long 0xC0++0x17
line.long 0x0 "GP2ODE,GPIO Port 2 Open Drain Enable"
hexmask.long.byte 0x0 0.--7. 1. "ODE,Open Drain Enable"
line.long 0x4 "GP2IS,GPIO Port 2 Input Select"
hexmask.long.byte 0x4 0.--7. 1. "ISEL,Input Select"
line.long 0x8 "GP2PE,GPIO Port 2 Pull Enable"
hexmask.long.byte 0x8 0.--7. 1. "PE,Pull Enable"
line.long 0xC "GP2PS,GPIO Port 2 Pull Select"
hexmask.long.byte 0xC 0.--7. 1. "PS,Pull Select"
line.long 0x10 "GP2SR,GPIO Port 2 Slew Rate"
hexmask.long.byte 0x10 0.--7. 1. "SR,Slew Rate"
line.long 0x14 "GP2DS,GPIO Port 2 Drive Select"
bitfld.long 0x14 14.--15. "DS7,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 12.--13. "DS6,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 10.--11. "DS5,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 8.--9. "DS4,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 6.--7. "DS3,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 4.--5. "DS2,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 2.--3. "DS1,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 0.--1. "DS0,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
group.long 0xDC++0xF
line.long 0x0 "GP2POL,Interrupt Polarity"
hexmask.long.byte 0x0 0.--7. 1. "INTPOL,Interrupt Polarity"
line.long 0x4 "GP2IENA,InterruptA Enable"
hexmask.long.byte 0x4 0.--7. 1. "INTAEN,InterruptA Enable"
line.long 0x8 "GP2IENB,InterruptB Enable"
hexmask.long.byte 0x8 0.--7. 1. "INTBEN,InterruptB Enable"
line.long 0xC "GP2INT,Interrupt Status"
hexmask.long.byte 0xC 0.--7. 1. "INTSTATUS,Interrupt Status"
group.long 0xF0++0xB
line.long 0x0 "GP3CON,GPIO Port 3 Configuration"
bitfld.long 0x0 14.--15. "CON7,P3.7 Configuration Bits" "0: GPIO,?,?,3: PLAO[29]"
bitfld.long 0x0 12.--13. "CON6,P3.6 Configuration Bits" "0: GPIO,1: SLAVE MDIO MDIO,2: SPI 2 Sready,3: PLA Output 30"
bitfld.long 0x0 10.--11. "CON5,P3.5 Configuration Bits" "0: GPIO,1: SLVA MDIO MCK,2: SPI 1 Sready,3: PLAO[27]"
newline
bitfld.long 0x0 8.--9. "CON4,P3.4 Configuration Bits" "0: GPIO/IRQ9,1: MDIO Port Address 4,2: Duplicate SOUT0,3: PLAO[26]"
bitfld.long 0x0 6.--7. "CON3,P3.3 Configuration Bits" "0: GPIO,1: MDIO Port Address3,2: Duplicate SIN0,3: PLAI[15]"
bitfld.long 0x0 4.--5. "CON2,P3.2 Configuration Bits" "0: GPIO,1: MDIO Port Address2,2: PWM Trip,3: PLAI[14]"
newline
bitfld.long 0x0 2.--3. "CON1,P3.1 Configuration Bits" "0: GPIO,1: MDIO PRTADDR1,2: PWM Sync,3: PLAI[13]"
bitfld.long 0x0 0.--1. "CON0,P3.0 Configuration Bits" "0: GPIO/IRQ8,1: MDIO Port Address 0,2: SPI 0 Sready,3: PLAI[12]"
line.long 0x4 "GP3OE,GPIO Port 3 Output Enable"
hexmask.long.byte 0x4 0.--7. 1. "OE,Output Enable"
line.long 0x8 "GP3IE,GPIO Port 3 Input Path Enable"
hexmask.long.byte 0x8 0.--7. 1. "IE,Input Enable"
rgroup.long 0xFC++0x3
line.long 0x0 "GP3IN,GPIO Port 3 Registered Data Input"
hexmask.long.byte 0x0 0.--7. 1. "Y,Data Input from Pad"
group.long 0x100++0x3
line.long 0x0 "GP3OUT,GPIO Port 3 Data Output"
hexmask.long.byte 0x0 0.--7. 1. "A,Data Output to Pad"
wgroup.long 0x104++0xB
line.long 0x0 "GP3SET,GPIO Port 3 Data Out Set"
hexmask.long.byte 0x0 0.--7. 1. "SETUP,Set the Output HIGH for the Pin"
line.long 0x4 "GP3CLR,GPIO Port 3 Data Out Clear"
hexmask.long.byte 0x4 0.--7. 1. "CLR,Set the Output Low for the Port Pin"
line.long 0x8 "GP3TGL,GPIO Port 3 Pin Toggle"
hexmask.long.byte 0x8 0.--7. 1. "TGL,Toggle the Output of the Port Pin"
group.long 0x110++0x17
line.long 0x0 "GP3ODE,GPIO Port 3 Open Drain Enable"
hexmask.long.byte 0x0 0.--7. 1. "ODE,Open Drain Enable"
line.long 0x4 "GP3IS,GPIO Port 3 Input Select"
hexmask.long.byte 0x4 0.--7. 1. "ISEL,Input Select"
line.long 0x8 "GP3PE,GPIO Port 3 Pull Enable"
hexmask.long.byte 0x8 0.--7. 1. "PE,Pull Enable"
line.long 0xC "GP3PS,GPIO Port 3 Pull Select"
hexmask.long.byte 0xC 0.--7. 1. "PS,Pull Select"
line.long 0x10 "GP3SR,GPIO Port 3 Slew Rate"
hexmask.long.byte 0x10 0.--7. 1. "SR,Slew Rate"
line.long 0x14 "GP3DS,GPIO Port 3 Drive Select"
bitfld.long 0x14 14.--15. "DS7,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 12.--13. "DS6,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 10.--11. "DS5,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 8.--9. "DS4,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 6.--7. "DS3,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 4.--5. "DS2,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 2.--3. "DS1,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 0.--1. "DS0,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
group.long 0x12C++0xF
line.long 0x0 "GP3POL,GPIO Interrupt Polarity Select"
hexmask.long.byte 0x0 0.--7. 1. "INTPOL,Parametric Output"
line.long 0x4 "GP3IENA,InterruptA Enable"
hexmask.long.byte 0x4 0.--7. 1. "INTAEN,InterruptA Enable"
line.long 0x8 "GP3IENB,InterruptB Enable"
hexmask.long.byte 0x8 0.--7. 1. "INTBEN,InterruptB Enable"
line.long 0xC "GP3INT,Interrupt Status"
hexmask.long.byte 0xC 0.--7. 1. "INTSTATUS,Interrupt Status"
group.long 0x140++0xB
line.long 0x0 "GP4CON,GPIO Port 4 Configuration"
bitfld.long 0x0 14.--15. "CON7,P4.7 Configuration Bits" "0: GPIO/IRQ7,?,2: PLA Clock 2,?"
bitfld.long 0x0 10.--11. "CON5,P4.5 Configuration Bits" "0: GPIO,?,?,?"
bitfld.long 0x0 8.--9. "CON4,P4.4 Configuration Bits" "0: GPIO,1: VDAC5,?,?"
newline
bitfld.long 0x0 6.--7. "CON3,P4.3 Configuration Bits" "0: GPIO,?,?,?"
bitfld.long 0x0 4.--5. "CON2,P4.2 Configuration Bits" "0: GPIO,1: VDAC7,?,?"
bitfld.long 0x0 2.--3. "CON1,P4.1 Configuration Bits" "0: GPIO,1: VDAC6,?,3: PLAO[28]"
newline
bitfld.long 0x0 0.--1. "CON0,P4.0 Configuration Bits" "0: GPIO,1: VDAC3,?,3: PLAI[11]"
line.long 0x4 "GP4OE,GPIO Port 4 Output Enable"
hexmask.long.byte 0x4 0.--7. 1. "OE,Output Enable"
line.long 0x8 "GP4IE,GPIO Port 4 Input Path Enable"
hexmask.long.byte 0x8 0.--7. 1. "IE,Input Enable"
rgroup.long 0x14C++0x3
line.long 0x0 "GP4IN,GPIO Port 4 Registered Data Input"
hexmask.long.byte 0x0 0.--7. 1. "Y,Data Input from Pad"
group.long 0x150++0x3
line.long 0x0 "GP4OUT,GPIO Port 4 Data Output"
hexmask.long.byte 0x0 0.--7. 1. "A,Data Output to Pad"
wgroup.long 0x154++0xB
line.long 0x0 "GP4SET,GPIO Port 4 Data Out Set"
hexmask.long.byte 0x0 0.--7. 1. "SETUP,Set the Output HIGH for the Pin"
line.long 0x4 "GP4CLR,GPIO Port 4 Data Out Clear"
hexmask.long.byte 0x4 0.--7. 1. "CLR,Set the Output Low for the Port Pin"
line.long 0x8 "GP4TGL,GPIO Port 4 Pin Toggle"
hexmask.long.byte 0x8 0.--7. 1. "TGL,Toggle the Output of the Port Pin"
group.long 0x160++0x17
line.long 0x0 "GP4ODE,GPIO Port 4 Open Drain Enable"
hexmask.long.byte 0x0 0.--7. 1. "ODE,Open Drain Enable"
line.long 0x4 "GP4IS,GPIO Port 4 Input Select"
hexmask.long.byte 0x4 0.--7. 1. "ISEL,Input Select"
line.long 0x8 "GP4PE,GPIO Port 4 Pull Enable"
hexmask.long.byte 0x8 0.--7. 1. "PE,Pull Enable"
line.long 0xC "GP4PS,GPIO Port 4 Pull Select"
hexmask.long.byte 0xC 0.--7. 1. "PS,Pull Select"
line.long 0x10 "GP4SR,GPIO Port 4 Slew Rate"
hexmask.long.byte 0x10 0.--7. 1. "SR,Slew Rate"
line.long 0x14 "GP4DS,GPIO Port 4 Drive Select"
bitfld.long 0x14 14.--15. "DS7,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 12.--13. "DS6,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 10.--11. "DS5,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 8.--9. "DS4,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 6.--7. "DS3,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 4.--5. "DS2,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 2.--3. "DS1,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 0.--1. "DS0,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
group.long 0x17C++0xF
line.long 0x0 "GP4POL,GPIO Interrupt Polarity Select"
hexmask.long.byte 0x0 0.--7. 1. "INTPOL,Parametric Output"
line.long 0x4 "GP4IENA,InterruptA Enable"
hexmask.long.byte 0x4 0.--7. 1. "INTAEN,InterruptA Enable"
line.long 0x8 "GP4IENB,InterruptB Enable"
hexmask.long.byte 0x8 0.--7. 1. "INTBEN,InterruptB Enable"
line.long 0xC "GP4INT,Interrupt Status"
hexmask.long.byte 0xC 0.--7. 1. "INTSTATUS,Interrupt Status"
group.long 0x190++0xB
line.long 0x0 "GP5CON,GPIO Port 6 Configuration"
bitfld.long 0x0 14.--15. "CON7,P5.7 Configuration Bits" "0: GPIO/IRQ_HV,1: Full Mux 6,?,?"
bitfld.long 0x0 12.--13. "CON6,P5.6 Configuration Bits" "0: GPIO/IRQ_HV,1: Full Mux 6,?,?"
bitfld.long 0x0 10.--11. "CON5,P5.5 Configuration Bits" "0: GPIO,1: Full Mux5,?,?"
newline
bitfld.long 0x0 8.--9. "CON4,P5.4 Configuration Bits" "0: GPIO,1: Full_mux 4,?,?"
bitfld.long 0x0 6.--7. "CON3,P5.3 Configuration Bits" "0: GPIO,1: Full Mux 3,2: VDAC11,?"
bitfld.long 0x0 4.--5. "CON2,P5.2 Configuration Bits" "0: GPIO,1: Full Mux 2,2: VDAC10,?"
newline
bitfld.long 0x0 2.--3. "CON1,P5.1 Configuration Bits" "0: GPIO,1: Full Mux 1,2: VDAC9,?"
bitfld.long 0x0 0.--1. "CON0,P5.0 Configuration Bits" "0: GPIO,1: Full Mux 0,2: VDAC8,?"
line.long 0x4 "GP5OE,GPIO Port 5 Output Enable"
hexmask.long.byte 0x4 0.--7. 1. "OE,Output Enable"
line.long 0x8 "GP5IE,GPIO Port 5 Input Path Enable"
hexmask.long.byte 0x8 0.--7. 1. "IE,Input Enable"
rgroup.long 0x19C++0x3
line.long 0x0 "GP5IN,GPIO Port 5 Registered Data Input"
hexmask.long.byte 0x0 0.--7. 1. "Y,Data Input from Pad"
group.long 0x1A0++0x3
line.long 0x0 "GP5OUT,GPIO Port 5 Data Output"
hexmask.long.byte 0x0 0.--7. 1. "A,Data Output to Pad"
wgroup.long 0x1A4++0xB
line.long 0x0 "GP5SET,GPIO Port 5 Data Out Set"
hexmask.long.byte 0x0 0.--7. 1. "SETUP,Set the Output HIGH for the Pin"
line.long 0x4 "GP5CLR,GPIO Port 5 Data Out Clear"
hexmask.long.byte 0x4 0.--7. 1. "CLR,Set the Output Low for the Port Pin"
line.long 0x8 "GP5TGL,GPIO Port 5 Pin Toggle"
hexmask.long.byte 0x8 0.--7. 1. "TGL,Toggle the Output of the Port Pin"
group.long 0x1B0++0x17
line.long 0x0 "GP5ODE,GPIO Port 5 Open Drain Enable"
hexmask.long.byte 0x0 0.--7. 1. "ODE,Open Drain Enable"
line.long 0x4 "GP5IS,GPIO Port 5 Input Select"
hexmask.long.byte 0x4 0.--7. 1. "ISEL,Input Select"
line.long 0x8 "GP5PE,GPIO Port 5 Pull Enable"
hexmask.long.byte 0x8 0.--7. 1. "PE,Pull Enable"
line.long 0xC "GP5PS,GPIO Port 5 Pull Select"
hexmask.long.byte 0xC 0.--7. 1. "PS,Pull Select"
line.long 0x10 "GP5SR,GPIO Port 5 Slew Rate"
hexmask.long.byte 0x10 0.--7. 1. "SR,Slew Rate"
line.long 0x14 "GP5DS,GPIO Port 5 Drive Select"
bitfld.long 0x14 14.--15. "DS7,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 12.--13. "DS6,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 10.--11. "DS5,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 8.--9. "DS4,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 6.--7. "DS3,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 4.--5. "DS2,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
newline
bitfld.long 0x14 2.--3. "DS1,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
bitfld.long 0x14 0.--1. "DS0,Drive Select" "0: Drive Strength 1,1: Drive Strength 2,2: Drive Strength 3,3: Drive Strength 4"
group.long 0x1CC++0xF
line.long 0x0 "GP5POL,GPIO Interrupt Polarity Select"
hexmask.long.byte 0x0 0.--7. 1. "INTPOL,Parametric Output"
line.long 0x4 "GP5IENA,InterruptA Enable"
hexmask.long.byte 0x4 0.--7. 1. "INTAEN,InterruptA Enable"
line.long 0x8 "GP5IENB,InterruptB Enable"
hexmask.long.byte 0x8 0.--7. 1. "INTBEN,InterruptB Enable"
line.long 0xC "GP5INT,Interrupt Status"
hexmask.long.byte 0xC 0.--7. 1. "INTSTATUS,Interrupt Status"
tree.end
tree "GPT (General-Purpose Timers - 16-bit)"
base ad:0x0
tree "GPT0"
base ad:0x40000000
group.long 0x0++0x3
line.long 0x0 "LD,16-bit Load Value Register"
hexmask.long.word 0x0 0.--15. 1. "LOAD,Load Value"
rgroup.long 0x4++0x3
line.long 0x0 "VAL,16-bit Timer Value Register"
hexmask.long.word 0x0 0.--15. 1. "COUNT_VAL,Current Count"
group.long 0x8++0x7
line.long 0x0 "CON,Control Register"
bitfld.long 0x0 7. "RLD,Reload Control" "0: Up/Down Counter is Only Reset on a Timeout Event,1: Resets the Up/down Counter When GPTCLRI[0] is Set"
bitfld.long 0x0 5.--6. "CLK,Clock Select" "0: PCLK.,1: ROOT_CLK,2: LFOSC. 32 KHz OSC,3: HFXTAL. 16 MHz OSC or XTAL (Dependent on.."
newline
bitfld.long 0x0 4. "ENABLE,Timer Enable" "0: DIS. Timer is Disabled (default),1: EN. Timer is Enabled"
bitfld.long 0x0 3. "MOD,Timer Mode" "0: FREERUN.Timer Runs in Free Running Mode,1: PERIODIC. Timer Runs in Periodic Mode (default)"
newline
bitfld.long 0x0 2. "UP,Count up" "0: DIS. Timer is Set to Count Down (default),1: EN. Timer is Set to Count up"
bitfld.long 0x0 0.--1. "PRE,Prescaler" "0: Source_clock / [1 or 4],1: Source_clock / 16,2: Source_clock / 256,3: Source_clock / 32 768"
line.long 0x4 "CLRI,Clear Interrupt Register"
bitfld.long 0x4 0. "TMOUT,Clear Timeout Interrupt" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STA,Status Register"
bitfld.long 0x0 7. "PDOK,GPTCLRI Synchronization" "0: CLR. the Interrupt is Cleared in the Timer Clock..,1: SET. GPTCLRI[0] is Being Updated in the Timer.."
bitfld.long 0x0 6. "BUSY,Timer Busy" "0: Timer Ready to Receive Commands to GPTCON,1: Timer Not Ready to Receive Commands to GPTCON"
newline
bitfld.long 0x0 0. "TMOUT,Timeout Event Occurred" "0: No Timeout Event Has Occurred,1: a Timeout Event Has Occurred"
tree.end
tree "GPT1"
base ad:0x40000400
group.long 0x0++0x3
line.long 0x0 "LD,16-bit Load Value Register"
hexmask.long.word 0x0 0.--15. 1. "LOAD,Load Value"
rgroup.long 0x4++0x3
line.long 0x0 "VAL,16-bit Timer Value Register"
hexmask.long.word 0x0 0.--15. 1. "COUNT_VAL,Current Count"
group.long 0x8++0x7
line.long 0x0 "CON,Control Register"
bitfld.long 0x0 7. "RLD,Reload Control" "0: Up/Down Counter is Only Reset on a Timeout Event,1: Resets the Up/down Counter When GPTCLRI[0] is Set"
bitfld.long 0x0 5.--6. "CLK,Clock Select" "0: PCLK.,1: ROOT_CLK,2: LFOSC. 32 KHz OSC,3: HFXTAL. 16 MHz OSC or XTAL (Dependent on.."
newline
bitfld.long 0x0 4. "ENABLE,Timer Enable" "0: DIS. Timer is Disabled (default),1: EN. Timer is Enabled"
bitfld.long 0x0 3. "MOD,Timer Mode" "0: FREERUN.Timer Runs in Free Running Mode,1: PERIODIC. Timer Runs in Periodic Mode (default)"
newline
bitfld.long 0x0 2. "UP,Count up" "0: DIS. Timer is Set to Count Down (default),1: EN. Timer is Set to Count up"
bitfld.long 0x0 0.--1. "PRE,Prescaler" "0: Source_clock / [1 or 4],1: Source_clock / 16,2: Source_clock / 256,3: Source_clock / 32 768"
line.long 0x4 "CLRI,Clear Interrupt Register"
bitfld.long 0x4 0. "TMOUT,Clear Timeout Interrupt" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STA,Status Register"
bitfld.long 0x0 7. "PDOK,GPTCLRI Synchronization" "0: CLR. the Interrupt is Cleared in the Timer Clock..,1: SET. GPTCLRI[0] is Being Updated in the Timer.."
bitfld.long 0x0 6. "BUSY,Timer Busy" "0: Timer Ready to Receive Commands to GPTCON,1: Timer Not Ready to Receive Commands to GPTCON"
newline
bitfld.long 0x0 0. "TMOUT,Timeout Event Occurred" "0: No Timeout Event Has Occurred,1: a Timeout Event Has Occurred"
tree.end
tree "GPT2"
base ad:0x40000800
group.long 0x0++0x3
line.long 0x0 "LD,16-bit Load Value Register"
hexmask.long.word 0x0 0.--15. 1. "LOAD,Load Value"
rgroup.long 0x4++0x3
line.long 0x0 "VAL,16-bit Timer Value Register"
hexmask.long.word 0x0 0.--15. 1. "COUNT_VAL,Current Count"
group.long 0x8++0x7
line.long 0x0 "CON,Control Register"
bitfld.long 0x0 7. "RLD,Reload Control" "0: Up/Down Counter is Only Reset on a Timeout Event,1: Resets the Up/down Counter When GPTCLRI[0] is Set"
bitfld.long 0x0 5.--6. "CLK,Clock Select" "0: PCLK.,1: ROOT_CLK,2: LFOSC. 32 KHz OSC,3: HFXTAL. 16 MHz OSC or XTAL (Dependent on.."
newline
bitfld.long 0x0 4. "ENABLE,Timer Enable" "0: DIS. Timer is Disabled (default),1: EN. Timer is Enabled"
bitfld.long 0x0 3. "MOD,Timer Mode" "0: FREERUN.Timer Runs in Free Running Mode,1: PERIODIC. Timer Runs in Periodic Mode (default)"
newline
bitfld.long 0x0 2. "UP,Count up" "0: DIS. Timer is Set to Count Down (default),1: EN. Timer is Set to Count up"
bitfld.long 0x0 0.--1. "PRE,Prescaler" "0: Source_clock / [1 or 4],1: Source_clock / 16,2: Source_clock / 256,3: Source_clock / 32 768"
line.long 0x4 "CLRI,Clear Interrupt Register"
bitfld.long 0x4 0. "TMOUT,Clear Timeout Interrupt" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "STA,Status Register"
bitfld.long 0x0 7. "PDOK,GPTCLRI Synchronization" "0: CLR. the Interrupt is Cleared in the Timer Clock..,1: SET. GPTCLRI[0] is Being Updated in the Timer.."
bitfld.long 0x0 6. "BUSY,Timer Busy" "0: Timer Ready to Receive Commands to GPTCON,1: Timer Not Ready to Receive Commands to GPTCON"
newline
bitfld.long 0x0 0. "TMOUT,Timeout Event Occurred" "0: No Timeout Event Has Occurred,1: a Timeout Event Has Occurred"
tree.end
tree.end
tree "GPTH (General-Purpose Timers - 32-bit)"
base ad:0x0
tree "GPTH0"
base ad:0x40000C00
group.long 0x0++0xB
line.long 0x0 "CTL,Timer Control"
hexmask.long.byte 0x0 4.--8. 1. "PRE,Timer Prescale"
bitfld.long 0x0 2.--3. "SEL,Clock Source Select" "0: PCLK,1: HCLK,2: High Frequency Oscillator,3: High Frequency XTALL"
bitfld.long 0x0 0. "EN,Timer Enable" "0,1"
line.long 0x4 "CNT,Count Value"
hexmask.long 0x4 0.--31. 1. "CNT,Current Counter Value."
line.long 0x8 "STATUS,Timer Status"
bitfld.long 0x8 3. "cc3_status,CC3 Status" "0,1"
bitfld.long 0x8 2. "cc2_status,CC2 Status" "0,1"
bitfld.long 0x8 1. "cc1_status,CC1 Status" "0,1"
bitfld.long 0x8 0. "cc0_status,CC0 Status" "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "CFG[$1],Capture Compare Configuration"
hexmask.long.byte 0x0 2.--5. 1. "EVENT_SEL,Capture Events Select"
bitfld.long 0x0 1. "CC_EN,Capture Compare Enabled" "0,1"
bitfld.long 0x0 0. "MODE,Capture or Compare Mode" "0: Compare,1: Capture"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "CC[$1],Compare and Capture Value"
hexmask.long 0x0 0.--31. 1. "CC,Capture or Compare Value"
repeat.end
tree.end
tree "GPTH1"
base ad:0x40001000
group.long 0x0++0xB
line.long 0x0 "CTL,Timer Control"
hexmask.long.byte 0x0 4.--8. 1. "PRE,Timer Prescale"
bitfld.long 0x0 2.--3. "SEL,Clock Source Select" "0: PCLK,1: HCLK,2: High Frequency Oscillator,3: High Frequency XTALL"
bitfld.long 0x0 0. "EN,Timer Enable" "0,1"
line.long 0x4 "CNT,Count Value"
hexmask.long 0x4 0.--31. 1. "CNT,Current Counter Value."
line.long 0x8 "STATUS,Timer Status"
bitfld.long 0x8 3. "cc3_status,CC3 Status" "0,1"
bitfld.long 0x8 2. "cc2_status,CC2 Status" "0,1"
bitfld.long 0x8 1. "cc1_status,CC1 Status" "0,1"
bitfld.long 0x8 0. "cc0_status,CC0 Status" "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "CFG[$1],Capture Compare Configuration"
hexmask.long.byte 0x0 2.--5. 1. "EVENT_SEL,Capture Events Select"
bitfld.long 0x0 1. "CC_EN,Capture Compare Enabled" "0,1"
bitfld.long 0x0 0. "MODE,Capture or Compare Mode" "0: Compare,1: Capture"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "CC[$1],Compare and Capture Value"
hexmask.long 0x0 0.--31. 1. "CC,Capture or Compare Value"
repeat.end
tree.end
tree.end
tree "I2C (I2C Serial Interface)"
base ad:0x0
tree "I2C0"
base ad:0x40020800
group.long 0x0++0x7
line.long 0x0 "MCTL,Master Control"
bitfld.long 0x0 13. "PRESTOP_BUS_CLR,Prestop Bus-Clear" "0,1"
bitfld.long 0x0 12. "BUS_CLR_EN,Bus-Clear Enable" "0,1"
newline
bitfld.long 0x0 11. "MTXDMA,Enable Master Tx DMA Request" "0,1"
bitfld.long 0x0 10. "MRXDMA,Enable Master Rx DMA Request" "0,1"
newline
bitfld.long 0x0 9. "MXMITDEC,Decrement Master TX FIFO Status When Transmitted One Byte" "0,1"
bitfld.long 0x0 8. "IENCMP,Transaction Completed (Or Stop Detected) Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "IENACK,ACK Not Received Interrupt Enable" "0,1"
bitfld.long 0x0 6. "IENALOST,Arbitration Lost Interrupt Enable" "0,1"
newline
bitfld.long 0x0 5. "IENMTX,Transmit Request Interrupt Enable." "0,1"
bitfld.long 0x0 4. "IENMRX,Receive Request Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "LOOPBACK,Internal Loopback Enable" "0,1"
bitfld.long 0x0 1. "COMPETE,Start Back-off Disable" "0,1"
newline
bitfld.long 0x0 0. "MASEN,Master Enable" "0,1"
line.long 0x4 "MSTAT,Master Status"
rbitfld.long 0x4 15. "MSTR_HS_MODE,Master High Speed Mode Flag" "0,1"
rbitfld.long 0x4 14. "SCL_FILTERED,State of SCL Line" "0,1"
newline
rbitfld.long 0x4 13. "SDA_FILTERED,State of SDA Line" "0,1"
rbitfld.long 0x4 12. "MTXUFLOW,Master Transmit Underflow" "0,1"
newline
rbitfld.long 0x4 11. "MSTOP,STOP Driven by This I2C Master" "0,1"
rbitfld.long 0x4 10. "LINEBUSY,Line is Busy" "0,1"
newline
rbitfld.long 0x4 9. "MRXOF,Master Receive FIFO Overflow" "0,1"
rbitfld.long 0x4 8. "TCOMP,Transaction Complete or Stop Detected" "0,1"
newline
rbitfld.long 0x4 7. "NACKDATA,ACK Not Received in Response to Data Write" "0,1"
rbitfld.long 0x4 6. "MBUSY,Master Busy" "0,1"
newline
rbitfld.long 0x4 5. "ALOST,Arbitration Lost" "0,1"
rbitfld.long 0x4 4. "NACKADDR,ACK Not Received in Response to an Address" "0,1"
newline
rbitfld.long 0x4 3. "MRXREQ,Master Receive Request" "0,1"
bitfld.long 0x4 2. "MTXREQ,Master Transmit Interrupt Bit" "0,1"
newline
rbitfld.long 0x4 0.--1. "MTXFSTA,Master Transmit FIFO Status" "0,1,2,3"
rgroup.long 0x8++0x3
line.long 0x0 "MRX,Master Receive Data"
hexmask.long.byte 0x0 0.--7. 1. "ICMRX,Master Receive Register"
group.long 0xC++0x7
line.long 0x0 "MTX,Master Transmit Data"
hexmask.long.byte 0x0 0.--7. 1. "I2CMRX,Master Transmit Register"
line.long 0x4 "MRXCNT,Master Receive Data Count"
bitfld.long 0x4 8. "EXTEND,Extended Read" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "COUNT,Receive Count"
rgroup.long 0x14++0x3
line.long 0x0 "MCRXCNT,Master Current Receive Data Count"
hexmask.long.byte 0x0 0.--7. 1. "COUNT,Current Receive Count"
group.long 0x18++0x17
line.long 0x0 "ADDR0,1st Master Address Byte"
hexmask.long.byte 0x0 0.--7. 1. "ADR1,Address Byte 1"
line.long 0x4 "ADDR1,2nd Master Address Byte"
hexmask.long.byte 0x4 0.--7. 1. "ADR2,Address Byte 2"
line.long 0x8 "BYT,Start Byte"
hexmask.long.byte 0x8 0.--7. 1. "SBYTE,Start Byte"
line.long 0xC "DIV,Serial Clock Period Divisor"
hexmask.long.byte 0xC 8.--15. 1. "HIGH,Serial Clock High Time"
hexmask.long.byte 0xC 0.--7. 1. "LOW,Serial Clock Low Time"
line.long 0x10 "SCTL,Slave Control"
bitfld.long 0x10 15. "ID_FIFO_EN,ID FIFO Enable" "0,1"
bitfld.long 0x10 14. "STXDMA,Enable Slave Tx DMA Request" "0,1"
newline
bitfld.long 0x10 13. "SRXDMA,Enable Slave Rx DMA Request" "0,1"
bitfld.long 0x10 12. "IENREPST,Repeated Start Interrupt Enable" "0,1"
newline
bitfld.long 0x10 11. "SXMITDEC,Decrement Slave Tx FIFO Status When Transmitted a Byte" "0,1"
bitfld.long 0x10 10. "IENSTX,Slave Transmit Request Interrupt Enable" "0,1"
newline
bitfld.long 0x10 9. "IENSRX,Slave Receive Request Interrupt Enable" "0,1"
bitfld.long 0x10 8. "IENSTOP,Stop Condition Detected Interrupt Enable" "0,1"
newline
bitfld.long 0x10 7. "NACK,NACK Next Communication" "0,1"
bitfld.long 0x10 5. "EARLYTXR,Early Transmit Request Mode" "0,1"
newline
bitfld.long 0x10 4. "GCSBCLR,General Call Status Bit Clear" "0,1"
bitfld.long 0x10 3. "HGCEN,Hardware General Call Enable" "0,1"
newline
bitfld.long 0x10 2. "GCEN,General Call Enable" "0,1"
bitfld.long 0x10 1. "ADR10EN,Enabled 10-bit Addressing" "0,1"
newline
bitfld.long 0x10 0. "SLVEN,Slave Enable" "0,1"
line.long 0x14 "SSTAT,Slave I2C Status/Error/IRQ"
rbitfld.long 0x14 15. "SLV_HS_MODE,Slave High Speed Mode Flag" "0,1"
rbitfld.long 0x14 14. "START,Start and Matching Address" "0,1"
newline
rbitfld.long 0x14 13. "REPSTART,Repeated Start and Matching Address" "0,1"
rbitfld.long 0x14 11.--12. "IDMAT,Device ID Matched" "0: Received Address Matched ID Register 0,1: Received Address Matched ID Register 1,2: Received Address Matched ID Register 2,3: Received Address Matched ID Register 3"
newline
rbitfld.long 0x14 10. "STOP,Stop After Start and Matching Address" "0,1"
rbitfld.long 0x14 8.--9. "GCID,General ID" "0: No general call,1: General call Reset and Program Address,2: General Call Program Address,3: General Call Matching Alternative ID"
newline
rbitfld.long 0x14 7. "GCINT,General Call Interrupt" "0,1"
rbitfld.long 0x14 6. "SBUSY,Slave Busy" "0,1"
newline
rbitfld.long 0x14 5. "NOACK,Ack Not Generated by the Slave" "0,1"
rbitfld.long 0x14 4. "SRXOF,Slave Receive FIFO Overflow" "0,1"
newline
rbitfld.long 0x14 3. "SRXREQ,Slave Receive Request" "0,1"
rbitfld.long 0x14 2. "STXREQ,Slave Transmit Interrupt Bit" "0,1"
newline
rbitfld.long 0x14 1. "STXUR,Slave Transmit FIFO Underflow" "0,1"
bitfld.long 0x14 0. "STXFSEREQ,Slave Tx FIFO Status or Early Request" "0,1"
rgroup.long 0x30++0x3
line.long 0x0 "SRX,Slave Receive"
hexmask.long.byte 0x0 0.--7. 1. "I2CSRX,Slave Receive Register"
group.long 0x34++0x33
line.long 0x0 "STX,Slave Transmit"
bitfld.long 0x0 8.--9. "ID_SEL,ID FIFO Selection" "0: Select Address Matched ID Register 0,1: Select Address Matched ID Register 1,2: Select Address Matched ID Register 2,3: Select Address Matched ID Register 3"
hexmask.long.byte 0x0 0.--7. 1. "I2CSTX,Slave Transmit Register"
line.long 0x4 "ALT,Hardware General Call ID"
hexmask.long.byte 0x4 0.--7. 1. "ALT,Slave Alt"
line.long 0x8 "ID0,1st Slave Address Device ID"
hexmask.long.byte 0x8 0.--7. 1. "ID0,Slave Device ID 0"
line.long 0xC "ID1,2nd Slave Address Device ID"
hexmask.long.byte 0xC 0.--7. 1. "ID1,Slave Device ID 1"
line.long 0x10 "ID2,3rd Slave Address Device ID"
hexmask.long.byte 0x10 0.--7. 1. "ID2,Slave Device ID 2"
line.long 0x14 "ID3,4th Slave Address Device ID"
hexmask.long.byte 0x14 0.--7. 1. "ID3,Slave Device ID 3"
line.long 0x18 "STAT,Master and Slave FIFO Status"
bitfld.long 0x18 10. "STX_FLUSH_ALL,Flush All the Slave Transmit ID FIFOs." "0,1"
bitfld.long 0x18 9. "MFLUSH,Flush the Master Transmit FIFO" "0,1"
newline
bitfld.long 0x18 8. "SFLUSH,Flush the Slave Transmit FIFO" "0,1"
rbitfld.long 0x18 6.--7. "MRXFSTA,Master Receive FIFO Status" "0: FIFO Empty,1: 1 Bytes In The FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x18 4.--5. "MTXSFA,Master Transmit FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x18 2.--3. "SRXFSTA,Slave Receive FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x18 0.--1. "STXFSTA,Slave Transmit FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
line.long 0x1C "SHCTL,Shared Control"
hexmask.long.byte 0x1C 12.--15. 1. "SCL_DLY,Delay Between SCLOUT and SCLOEN"
hexmask.long.byte 0x1C 8.--11. 1. "SDA_DLY,Delay Between SDAOUT and SDAOEN"
newline
rbitfld.long 0x1C 6. "ADR_BUSY,ADR Busy Flag" "0,1"
bitfld.long 0x1C 0. "RESET,Reset START STOP Detect Circuit" "0,1"
line.long 0x20 "TCTL,Timing Control Register"
hexmask.long.byte 0x20 12.--15. 1. "FILTER_TICKS,SCK & SDA Gglitch Filter Ticks."
bitfld.long 0x20 9.--11. "PRE_DIV,Presale Divide Counter for SCK DIV" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 8. "FILTEROFF,Input Filter Control" "0,1"
hexmask.long.byte 0x20 0.--5. 1. "THDATIN,Data in Hold Start"
line.long 0x24 "ASTRETCH_SCL,Automatic Stretch SCL Register"
bitfld.long 0x24 15. "clr_addr_ack_irq,Write Clear the Address ACK IRQ." "0,1"
bitfld.long 0x24 14. "sscl_irq_ien,Slave Stretch Interruption Enable" "0,1"
newline
bitfld.long 0x24 13. "addr_ack_ien,Slave ADDRESS ACK Interruption Enable" "0,1"
bitfld.long 0x24 12. "SSCL_RLS,Slave Manual Clear Stretch" "0,1"
newline
bitfld.long 0x24 11. "sscl_after_ack,Slave RX Stretch After ACK Mode" "0,1"
bitfld.long 0x24 10. "MAN_RLS_EN,Manual Release Stretch Enable" "0,1"
newline
rbitfld.long 0x24 9. "timeout_sscl_slv,Slave Automatic Stretch Timeout" "0,1"
rbitfld.long 0x24 8. "timeout_sscl_mas,Master Automatic Stretch Timeout" "0,1"
newline
hexmask.long.byte 0x24 4.--7. 1. "strecth_mode_slv,Slave Automatic Stretch Mode"
hexmask.long.byte 0x24 0.--3. 1. "stretch_mode_mas,Master Automatic Stretch Mode"
line.long 0x28 "IDFSTA,ID FIFO Status Register"
rbitfld.long 0x28 15. "STX3UR,Slave Transmit ID3 FIFO Underflow" "0,1"
rbitfld.long 0x28 14. "STX2UR,Slave Transmit ID2 FIFO Underflow" "0,1"
newline
rbitfld.long 0x28 13. "STX1UR,Slave Transmit ID1 FIFO Underflow" "0,1"
rbitfld.long 0x28 12. "STX0UR,Slave Transmit ID0 FIFO Underflow" "0,1"
newline
bitfld.long 0x28 11. "SFLUSH3,Flush the Slave Transmit ID3 FIFO" "0,1"
bitfld.long 0x28 10. "SFLUSH2,Flush the Slave Transmit ID2 FIFO" "0,1"
newline
bitfld.long 0x28 9. "SFLUSH1,Flush the Slave Transmit ID1 FIFO" "0,1"
bitfld.long 0x28 8. "SFLUSH0,Flush the Slave Transmit ID0 FIFO" "0,1"
newline
rbitfld.long 0x28 6.--7. "STX3FSTA,Slave Transmit ID3 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x28 4.--5. "STX2FSTA,Slave Transmit ID2 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x28 2.--3. "STX1FSTA,Slave Transmit ID1 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x28 0.--1. "STX0FSTA,Slave Transmit ID0 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
line.long 0x2C "SLV_ADDR1,Slave 10 Bits Address 1st Byte."
hexmask.long.byte 0x2C 0.--7. 1. "SLV_ADR1,Slave 10 Bits Address 1st Byte"
line.long 0x30 "SLV_ADDR2,Slave 10 Bits Address 2nd Byte."
hexmask.long.byte 0x30 0.--7. 1. "SLV_ADR2,Slave 10 Bit Address 2nd Byte"
rgroup.long 0x68++0x3
line.long 0x0 "SSTAT2,Slave I2C Status/IRQ 2"
bitfld.long 0x0 2. "rw_direction,Slave I2C RW Direction." "0,1"
bitfld.long 0x0 1. "addr_ack_irq,Slave ADDR ACK Interruption State." "0,1"
newline
bitfld.long 0x0 0. "sscl_irq,Stretch Interruption State." "0,1"
tree.end
tree "I2C1"
base ad:0x40020C00
group.long 0x0++0x7
line.long 0x0 "MCTL,Master Control"
bitfld.long 0x0 13. "PRESTOP_BUS_CLR,Prestop Bus-Clear" "0,1"
bitfld.long 0x0 12. "BUS_CLR_EN,Bus-Clear Enable" "0,1"
newline
bitfld.long 0x0 11. "MTXDMA,Enable Master Tx DMA Request" "0,1"
bitfld.long 0x0 10. "MRXDMA,Enable Master Rx DMA Request" "0,1"
newline
bitfld.long 0x0 9. "MXMITDEC,Decrement Master TX FIFO Status When Transmitted One Byte" "0,1"
bitfld.long 0x0 8. "IENCMP,Transaction Completed (Or Stop Detected) Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "IENACK,ACK Not Received Interrupt Enable" "0,1"
bitfld.long 0x0 6. "IENALOST,Arbitration Lost Interrupt Enable" "0,1"
newline
bitfld.long 0x0 5. "IENMTX,Transmit Request Interrupt Enable." "0,1"
bitfld.long 0x0 4. "IENMRX,Receive Request Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "LOOPBACK,Internal Loopback Enable" "0,1"
bitfld.long 0x0 1. "COMPETE,Start Back-off Disable" "0,1"
newline
bitfld.long 0x0 0. "MASEN,Master Enable" "0,1"
line.long 0x4 "MSTAT,Master Status"
rbitfld.long 0x4 15. "MSTR_HS_MODE,Master High Speed Mode Flag" "0,1"
rbitfld.long 0x4 14. "SCL_FILTERED,State of SCL Line" "0,1"
newline
rbitfld.long 0x4 13. "SDA_FILTERED,State of SDA Line" "0,1"
rbitfld.long 0x4 12. "MTXUFLOW,Master Transmit Underflow" "0,1"
newline
rbitfld.long 0x4 11. "MSTOP,STOP Driven by This I2C Master" "0,1"
rbitfld.long 0x4 10. "LINEBUSY,Line is Busy" "0,1"
newline
rbitfld.long 0x4 9. "MRXOF,Master Receive FIFO Overflow" "0,1"
rbitfld.long 0x4 8. "TCOMP,Transaction Complete or Stop Detected" "0,1"
newline
rbitfld.long 0x4 7. "NACKDATA,ACK Not Received in Response to Data Write" "0,1"
rbitfld.long 0x4 6. "MBUSY,Master Busy" "0,1"
newline
rbitfld.long 0x4 5. "ALOST,Arbitration Lost" "0,1"
rbitfld.long 0x4 4. "NACKADDR,ACK Not Received in Response to an Address" "0,1"
newline
rbitfld.long 0x4 3. "MRXREQ,Master Receive Request" "0,1"
bitfld.long 0x4 2. "MTXREQ,Master Transmit Interrupt Bit" "0,1"
newline
rbitfld.long 0x4 0.--1. "MTXFSTA,Master Transmit FIFO Status" "0,1,2,3"
rgroup.long 0x8++0x3
line.long 0x0 "MRX,Master Receive Data"
hexmask.long.byte 0x0 0.--7. 1. "ICMRX,Master Receive Register"
group.long 0xC++0x7
line.long 0x0 "MTX,Master Transmit Data"
hexmask.long.byte 0x0 0.--7. 1. "I2CMRX,Master Transmit Register"
line.long 0x4 "MRXCNT,Master Receive Data Count"
bitfld.long 0x4 8. "EXTEND,Extended Read" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "COUNT,Receive Count"
rgroup.long 0x14++0x3
line.long 0x0 "MCRXCNT,Master Current Receive Data Count"
hexmask.long.byte 0x0 0.--7. 1. "COUNT,Current Receive Count"
group.long 0x18++0x17
line.long 0x0 "ADDR0,1st Master Address Byte"
hexmask.long.byte 0x0 0.--7. 1. "ADR1,Address Byte 1"
line.long 0x4 "ADDR1,2nd Master Address Byte"
hexmask.long.byte 0x4 0.--7. 1. "ADR2,Address Byte 2"
line.long 0x8 "BYT,Start Byte"
hexmask.long.byte 0x8 0.--7. 1. "SBYTE,Start Byte"
line.long 0xC "DIV,Serial Clock Period Divisor"
hexmask.long.byte 0xC 8.--15. 1. "HIGH,Serial Clock High Time"
hexmask.long.byte 0xC 0.--7. 1. "LOW,Serial Clock Low Time"
line.long 0x10 "SCTL,Slave Control"
bitfld.long 0x10 15. "ID_FIFO_EN,ID FIFO Enable" "0,1"
bitfld.long 0x10 14. "STXDMA,Enable Slave Tx DMA Request" "0,1"
newline
bitfld.long 0x10 13. "SRXDMA,Enable Slave Rx DMA Request" "0,1"
bitfld.long 0x10 12. "IENREPST,Repeated Start Interrupt Enable" "0,1"
newline
bitfld.long 0x10 11. "SXMITDEC,Decrement Slave Tx FIFO Status When Transmitted a Byte" "0,1"
bitfld.long 0x10 10. "IENSTX,Slave Transmit Request Interrupt Enable" "0,1"
newline
bitfld.long 0x10 9. "IENSRX,Slave Receive Request Interrupt Enable" "0,1"
bitfld.long 0x10 8. "IENSTOP,Stop Condition Detected Interrupt Enable" "0,1"
newline
bitfld.long 0x10 7. "NACK,NACK Next Communication" "0,1"
bitfld.long 0x10 5. "EARLYTXR,Early Transmit Request Mode" "0,1"
newline
bitfld.long 0x10 4. "GCSBCLR,General Call Status Bit Clear" "0,1"
bitfld.long 0x10 3. "HGCEN,Hardware General Call Enable" "0,1"
newline
bitfld.long 0x10 2. "GCEN,General Call Enable" "0,1"
bitfld.long 0x10 1. "ADR10EN,Enabled 10-bit Addressing" "0,1"
newline
bitfld.long 0x10 0. "SLVEN,Slave Enable" "0,1"
line.long 0x14 "SSTAT,Slave I2C Status/Error/IRQ"
rbitfld.long 0x14 15. "SLV_HS_MODE,Slave High Speed Mode Flag" "0,1"
rbitfld.long 0x14 14. "START,Start and Matching Address" "0,1"
newline
rbitfld.long 0x14 13. "REPSTART,Repeated Start and Matching Address" "0,1"
rbitfld.long 0x14 11.--12. "IDMAT,Device ID Matched" "0: Received Address Matched ID Register 0,1: Received Address Matched ID Register 1,2: Received Address Matched ID Register 2,3: Received Address Matched ID Register 3"
newline
rbitfld.long 0x14 10. "STOP,Stop After Start and Matching Address" "0,1"
rbitfld.long 0x14 8.--9. "GCID,General ID" "0: No general call,1: General call Reset and Program Address,2: General Call Program Address,3: General Call Matching Alternative ID"
newline
rbitfld.long 0x14 7. "GCINT,General Call Interrupt" "0,1"
rbitfld.long 0x14 6. "SBUSY,Slave Busy" "0,1"
newline
rbitfld.long 0x14 5. "NOACK,Ack Not Generated by the Slave" "0,1"
rbitfld.long 0x14 4. "SRXOF,Slave Receive FIFO Overflow" "0,1"
newline
rbitfld.long 0x14 3. "SRXREQ,Slave Receive Request" "0,1"
rbitfld.long 0x14 2. "STXREQ,Slave Transmit Interrupt Bit" "0,1"
newline
rbitfld.long 0x14 1. "STXUR,Slave Transmit FIFO Underflow" "0,1"
bitfld.long 0x14 0. "STXFSEREQ,Slave Tx FIFO Status or Early Request" "0,1"
rgroup.long 0x30++0x3
line.long 0x0 "SRX,Slave Receive"
hexmask.long.byte 0x0 0.--7. 1. "I2CSRX,Slave Receive Register"
group.long 0x34++0x33
line.long 0x0 "STX,Slave Transmit"
bitfld.long 0x0 8.--9. "ID_SEL,ID FIFO Selection" "0: Select Address Matched ID Register 0,1: Select Address Matched ID Register 1,2: Select Address Matched ID Register 2,3: Select Address Matched ID Register 3"
hexmask.long.byte 0x0 0.--7. 1. "I2CSTX,Slave Transmit Register"
line.long 0x4 "ALT,Hardware General Call ID"
hexmask.long.byte 0x4 0.--7. 1. "ALT,Slave Alt"
line.long 0x8 "ID0,1st Slave Address Device ID"
hexmask.long.byte 0x8 0.--7. 1. "ID0,Slave Device ID 0"
line.long 0xC "ID1,2nd Slave Address Device ID"
hexmask.long.byte 0xC 0.--7. 1. "ID1,Slave Device ID 1"
line.long 0x10 "ID2,3rd Slave Address Device ID"
hexmask.long.byte 0x10 0.--7. 1. "ID2,Slave Device ID 2"
line.long 0x14 "ID3,4th Slave Address Device ID"
hexmask.long.byte 0x14 0.--7. 1. "ID3,Slave Device ID 3"
line.long 0x18 "STAT,Master and Slave FIFO Status"
bitfld.long 0x18 10. "STX_FLUSH_ALL,Flush All the Slave Transmit ID FIFOs." "0,1"
bitfld.long 0x18 9. "MFLUSH,Flush the Master Transmit FIFO" "0,1"
newline
bitfld.long 0x18 8. "SFLUSH,Flush the Slave Transmit FIFO" "0,1"
rbitfld.long 0x18 6.--7. "MRXFSTA,Master Receive FIFO Status" "0: FIFO Empty,1: 1 Bytes In The FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x18 4.--5. "MTXSFA,Master Transmit FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x18 2.--3. "SRXFSTA,Slave Receive FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x18 0.--1. "STXFSTA,Slave Transmit FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
line.long 0x1C "SHCTL,Shared Control"
hexmask.long.byte 0x1C 12.--15. 1. "SCL_DLY,Delay Between SCLOUT and SCLOEN"
hexmask.long.byte 0x1C 8.--11. 1. "SDA_DLY,Delay Between SDAOUT and SDAOEN"
newline
rbitfld.long 0x1C 6. "ADR_BUSY,ADR Busy Flag" "0,1"
bitfld.long 0x1C 0. "RESET,Reset START STOP Detect Circuit" "0,1"
line.long 0x20 "TCTL,Timing Control Register"
hexmask.long.byte 0x20 12.--15. 1. "FILTER_TICKS,SCK & SDA Gglitch Filter Ticks."
bitfld.long 0x20 9.--11. "PRE_DIV,Presale Divide Counter for SCK DIV" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 8. "FILTEROFF,Input Filter Control" "0,1"
hexmask.long.byte 0x20 0.--5. 1. "THDATIN,Data in Hold Start"
line.long 0x24 "ASTRETCH_SCL,Automatic Stretch SCL Register"
bitfld.long 0x24 15. "clr_addr_ack_irq,Write Clear the Address ACK IRQ." "0,1"
bitfld.long 0x24 14. "sscl_irq_ien,Slave Stretch Interruption Enable" "0,1"
newline
bitfld.long 0x24 13. "addr_ack_ien,Slave ADDRESS ACK Interruption Enable" "0,1"
bitfld.long 0x24 12. "SSCL_RLS,Slave Manual Clear Stretch" "0,1"
newline
bitfld.long 0x24 11. "sscl_after_ack,Slave RX Stretch After ACK Mode" "0,1"
bitfld.long 0x24 10. "MAN_RLS_EN,Manual Release Stretch Enable" "0,1"
newline
rbitfld.long 0x24 9. "timeout_sscl_slv,Slave Automatic Stretch Timeout" "0,1"
rbitfld.long 0x24 8. "timeout_sscl_mas,Master Automatic Stretch Timeout" "0,1"
newline
hexmask.long.byte 0x24 4.--7. 1. "strecth_mode_slv,Slave Automatic Stretch Mode"
hexmask.long.byte 0x24 0.--3. 1. "stretch_mode_mas,Master Automatic Stretch Mode"
line.long 0x28 "IDFSTA,ID FIFO Status Register"
rbitfld.long 0x28 15. "STX3UR,Slave Transmit ID3 FIFO Underflow" "0,1"
rbitfld.long 0x28 14. "STX2UR,Slave Transmit ID2 FIFO Underflow" "0,1"
newline
rbitfld.long 0x28 13. "STX1UR,Slave Transmit ID1 FIFO Underflow" "0,1"
rbitfld.long 0x28 12. "STX0UR,Slave Transmit ID0 FIFO Underflow" "0,1"
newline
bitfld.long 0x28 11. "SFLUSH3,Flush the Slave Transmit ID3 FIFO" "0,1"
bitfld.long 0x28 10. "SFLUSH2,Flush the Slave Transmit ID2 FIFO" "0,1"
newline
bitfld.long 0x28 9. "SFLUSH1,Flush the Slave Transmit ID1 FIFO" "0,1"
bitfld.long 0x28 8. "SFLUSH0,Flush the Slave Transmit ID0 FIFO" "0,1"
newline
rbitfld.long 0x28 6.--7. "STX3FSTA,Slave Transmit ID3 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x28 4.--5. "STX2FSTA,Slave Transmit ID2 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x28 2.--3. "STX1FSTA,Slave Transmit ID1 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x28 0.--1. "STX0FSTA,Slave Transmit ID0 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
line.long 0x2C "SLV_ADDR1,Slave 10 Bits Address 1st Byte."
hexmask.long.byte 0x2C 0.--7. 1. "SLV_ADR1,Slave 10 Bits Address 1st Byte"
line.long 0x30 "SLV_ADDR2,Slave 10 Bits Address 2nd Byte."
hexmask.long.byte 0x30 0.--7. 1. "SLV_ADR2,Slave 10 Bit Address 2nd Byte"
rgroup.long 0x68++0x3
line.long 0x0 "SSTAT2,Slave I2C Status/IRQ 2"
bitfld.long 0x0 2. "rw_direction,Slave I2C RW Direction." "0,1"
bitfld.long 0x0 1. "addr_ack_irq,Slave ADDR ACK Interruption State." "0,1"
newline
bitfld.long 0x0 0. "sscl_irq,Stretch Interruption State." "0,1"
tree.end
tree "I2C2"
base ad:0x40021000
group.long 0x0++0x7
line.long 0x0 "MCTL,Master Control"
bitfld.long 0x0 13. "PRESTOP_BUS_CLR,Prestop Bus-Clear" "0,1"
bitfld.long 0x0 12. "BUS_CLR_EN,Bus-Clear Enable" "0,1"
newline
bitfld.long 0x0 11. "MTXDMA,Enable Master Tx DMA Request" "0,1"
bitfld.long 0x0 10. "MRXDMA,Enable Master Rx DMA Request" "0,1"
newline
bitfld.long 0x0 9. "MXMITDEC,Decrement Master TX FIFO Status When Transmitted One Byte" "0,1"
bitfld.long 0x0 8. "IENCMP,Transaction Completed (Or Stop Detected) Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "IENACK,ACK Not Received Interrupt Enable" "0,1"
bitfld.long 0x0 6. "IENALOST,Arbitration Lost Interrupt Enable" "0,1"
newline
bitfld.long 0x0 5. "IENMTX,Transmit Request Interrupt Enable." "0,1"
bitfld.long 0x0 4. "IENMRX,Receive Request Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "LOOPBACK,Internal Loopback Enable" "0,1"
bitfld.long 0x0 1. "COMPETE,Start Back-off Disable" "0,1"
newline
bitfld.long 0x0 0. "MASEN,Master Enable" "0,1"
line.long 0x4 "MSTAT,Master Status"
rbitfld.long 0x4 15. "MSTR_HS_MODE,Master High Speed Mode Flag" "0,1"
rbitfld.long 0x4 14. "SCL_FILTERED,State of SCL Line" "0,1"
newline
rbitfld.long 0x4 13. "SDA_FILTERED,State of SDA Line" "0,1"
rbitfld.long 0x4 12. "MTXUFLOW,Master Transmit Underflow" "0,1"
newline
rbitfld.long 0x4 11. "MSTOP,STOP Driven by This I2C Master" "0,1"
rbitfld.long 0x4 10. "LINEBUSY,Line is Busy" "0,1"
newline
rbitfld.long 0x4 9. "MRXOF,Master Receive FIFO Overflow" "0,1"
rbitfld.long 0x4 8. "TCOMP,Transaction Complete or Stop Detected" "0,1"
newline
rbitfld.long 0x4 7. "NACKDATA,ACK Not Received in Response to Data Write" "0,1"
rbitfld.long 0x4 6. "MBUSY,Master Busy" "0,1"
newline
rbitfld.long 0x4 5. "ALOST,Arbitration Lost" "0,1"
rbitfld.long 0x4 4. "NACKADDR,ACK Not Received in Response to an Address" "0,1"
newline
rbitfld.long 0x4 3. "MRXREQ,Master Receive Request" "0,1"
bitfld.long 0x4 2. "MTXREQ,Master Transmit Interrupt Bit" "0,1"
newline
rbitfld.long 0x4 0.--1. "MTXFSTA,Master Transmit FIFO Status" "0,1,2,3"
rgroup.long 0x8++0x3
line.long 0x0 "MRX,Master Receive Data"
hexmask.long.byte 0x0 0.--7. 1. "ICMRX,Master Receive Register"
group.long 0xC++0x7
line.long 0x0 "MTX,Master Transmit Data"
hexmask.long.byte 0x0 0.--7. 1. "I2CMRX,Master Transmit Register"
line.long 0x4 "MRXCNT,Master Receive Data Count"
bitfld.long 0x4 8. "EXTEND,Extended Read" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "COUNT,Receive Count"
rgroup.long 0x14++0x3
line.long 0x0 "MCRXCNT,Master Current Receive Data Count"
hexmask.long.byte 0x0 0.--7. 1. "COUNT,Current Receive Count"
group.long 0x18++0x17
line.long 0x0 "ADDR0,1st Master Address Byte"
hexmask.long.byte 0x0 0.--7. 1. "ADR1,Address Byte 1"
line.long 0x4 "ADDR1,2nd Master Address Byte"
hexmask.long.byte 0x4 0.--7. 1. "ADR2,Address Byte 2"
line.long 0x8 "BYT,Start Byte"
hexmask.long.byte 0x8 0.--7. 1. "SBYTE,Start Byte"
line.long 0xC "DIV,Serial Clock Period Divisor"
hexmask.long.byte 0xC 8.--15. 1. "HIGH,Serial Clock High Time"
hexmask.long.byte 0xC 0.--7. 1. "LOW,Serial Clock Low Time"
line.long 0x10 "SCTL,Slave Control"
bitfld.long 0x10 15. "ID_FIFO_EN,ID FIFO Enable" "0,1"
bitfld.long 0x10 14. "STXDMA,Enable Slave Tx DMA Request" "0,1"
newline
bitfld.long 0x10 13. "SRXDMA,Enable Slave Rx DMA Request" "0,1"
bitfld.long 0x10 12. "IENREPST,Repeated Start Interrupt Enable" "0,1"
newline
bitfld.long 0x10 11. "SXMITDEC,Decrement Slave Tx FIFO Status When Transmitted a Byte" "0,1"
bitfld.long 0x10 10. "IENSTX,Slave Transmit Request Interrupt Enable" "0,1"
newline
bitfld.long 0x10 9. "IENSRX,Slave Receive Request Interrupt Enable" "0,1"
bitfld.long 0x10 8. "IENSTOP,Stop Condition Detected Interrupt Enable" "0,1"
newline
bitfld.long 0x10 7. "NACK,NACK Next Communication" "0,1"
bitfld.long 0x10 5. "EARLYTXR,Early Transmit Request Mode" "0,1"
newline
bitfld.long 0x10 4. "GCSBCLR,General Call Status Bit Clear" "0,1"
bitfld.long 0x10 3. "HGCEN,Hardware General Call Enable" "0,1"
newline
bitfld.long 0x10 2. "GCEN,General Call Enable" "0,1"
bitfld.long 0x10 1. "ADR10EN,Enabled 10-bit Addressing" "0,1"
newline
bitfld.long 0x10 0. "SLVEN,Slave Enable" "0,1"
line.long 0x14 "SSTAT,Slave I2C Status/Error/IRQ"
rbitfld.long 0x14 15. "SLV_HS_MODE,Slave High Speed Mode Flag" "0,1"
rbitfld.long 0x14 14. "START,Start and Matching Address" "0,1"
newline
rbitfld.long 0x14 13. "REPSTART,Repeated Start and Matching Address" "0,1"
rbitfld.long 0x14 11.--12. "IDMAT,Device ID Matched" "0: Received Address Matched ID Register 0,1: Received Address Matched ID Register 1,2: Received Address Matched ID Register 2,3: Received Address Matched ID Register 3"
newline
rbitfld.long 0x14 10. "STOP,Stop After Start and Matching Address" "0,1"
rbitfld.long 0x14 8.--9. "GCID,General ID" "0: No general call,1: General call Reset and Program Address,2: General Call Program Address,3: General Call Matching Alternative ID"
newline
rbitfld.long 0x14 7. "GCINT,General Call Interrupt" "0,1"
rbitfld.long 0x14 6. "SBUSY,Slave Busy" "0,1"
newline
rbitfld.long 0x14 5. "NOACK,Ack Not Generated by the Slave" "0,1"
rbitfld.long 0x14 4. "SRXOF,Slave Receive FIFO Overflow" "0,1"
newline
rbitfld.long 0x14 3. "SRXREQ,Slave Receive Request" "0,1"
rbitfld.long 0x14 2. "STXREQ,Slave Transmit Interrupt Bit" "0,1"
newline
rbitfld.long 0x14 1. "STXUR,Slave Transmit FIFO Underflow" "0,1"
bitfld.long 0x14 0. "STXFSEREQ,Slave Tx FIFO Status or Early Request" "0,1"
rgroup.long 0x30++0x3
line.long 0x0 "SRX,Slave Receive"
hexmask.long.byte 0x0 0.--7. 1. "I2CSRX,Slave Receive Register"
group.long 0x34++0x33
line.long 0x0 "STX,Slave Transmit"
bitfld.long 0x0 8.--9. "ID_SEL,ID FIFO Selection" "0: Select Address Matched ID Register 0,1: Select Address Matched ID Register 1,2: Select Address Matched ID Register 2,3: Select Address Matched ID Register 3"
hexmask.long.byte 0x0 0.--7. 1. "I2CSTX,Slave Transmit Register"
line.long 0x4 "ALT,Hardware General Call ID"
hexmask.long.byte 0x4 0.--7. 1. "ALT,Slave Alt"
line.long 0x8 "ID0,1st Slave Address Device ID"
hexmask.long.byte 0x8 0.--7. 1. "ID0,Slave Device ID 0"
line.long 0xC "ID1,2nd Slave Address Device ID"
hexmask.long.byte 0xC 0.--7. 1. "ID1,Slave Device ID 1"
line.long 0x10 "ID2,3rd Slave Address Device ID"
hexmask.long.byte 0x10 0.--7. 1. "ID2,Slave Device ID 2"
line.long 0x14 "ID3,4th Slave Address Device ID"
hexmask.long.byte 0x14 0.--7. 1. "ID3,Slave Device ID 3"
line.long 0x18 "STAT,Master and Slave FIFO Status"
bitfld.long 0x18 10. "STX_FLUSH_ALL,Flush All the Slave Transmit ID FIFOs." "0,1"
bitfld.long 0x18 9. "MFLUSH,Flush the Master Transmit FIFO" "0,1"
newline
bitfld.long 0x18 8. "SFLUSH,Flush the Slave Transmit FIFO" "0,1"
rbitfld.long 0x18 6.--7. "MRXFSTA,Master Receive FIFO Status" "0: FIFO Empty,1: 1 Bytes In The FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x18 4.--5. "MTXSFA,Master Transmit FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x18 2.--3. "SRXFSTA,Slave Receive FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x18 0.--1. "STXFSTA,Slave Transmit FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
line.long 0x1C "SHCTL,Shared Control"
hexmask.long.byte 0x1C 12.--15. 1. "SCL_DLY,Delay Between SCLOUT and SCLOEN"
hexmask.long.byte 0x1C 8.--11. 1. "SDA_DLY,Delay Between SDAOUT and SDAOEN"
newline
rbitfld.long 0x1C 6. "ADR_BUSY,ADR Busy Flag" "0,1"
bitfld.long 0x1C 0. "RESET,Reset START STOP Detect Circuit" "0,1"
line.long 0x20 "TCTL,Timing Control Register"
hexmask.long.byte 0x20 12.--15. 1. "FILTER_TICKS,SCK & SDA Gglitch Filter Ticks."
bitfld.long 0x20 9.--11. "PRE_DIV,Presale Divide Counter for SCK DIV" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 8. "FILTEROFF,Input Filter Control" "0,1"
hexmask.long.byte 0x20 0.--5. 1. "THDATIN,Data in Hold Start"
line.long 0x24 "ASTRETCH_SCL,Automatic Stretch SCL Register"
bitfld.long 0x24 15. "clr_addr_ack_irq,Write Clear the Address ACK IRQ." "0,1"
bitfld.long 0x24 14. "sscl_irq_ien,Slave Stretch Interruption Enable" "0,1"
newline
bitfld.long 0x24 13. "addr_ack_ien,Slave ADDRESS ACK Interruption Enable" "0,1"
bitfld.long 0x24 12. "SSCL_RLS,Slave Manual Clear Stretch" "0,1"
newline
bitfld.long 0x24 11. "sscl_after_ack,Slave RX Stretch After ACK Mode" "0,1"
bitfld.long 0x24 10. "MAN_RLS_EN,Manual Release Stretch Enable" "0,1"
newline
rbitfld.long 0x24 9. "timeout_sscl_slv,Slave Automatic Stretch Timeout" "0,1"
rbitfld.long 0x24 8. "timeout_sscl_mas,Master Automatic Stretch Timeout" "0,1"
newline
hexmask.long.byte 0x24 4.--7. 1. "strecth_mode_slv,Slave Automatic Stretch Mode"
hexmask.long.byte 0x24 0.--3. 1. "stretch_mode_mas,Master Automatic Stretch Mode"
line.long 0x28 "IDFSTA,ID FIFO Status Register"
rbitfld.long 0x28 15. "STX3UR,Slave Transmit ID3 FIFO Underflow" "0,1"
rbitfld.long 0x28 14. "STX2UR,Slave Transmit ID2 FIFO Underflow" "0,1"
newline
rbitfld.long 0x28 13. "STX1UR,Slave Transmit ID1 FIFO Underflow" "0,1"
rbitfld.long 0x28 12. "STX0UR,Slave Transmit ID0 FIFO Underflow" "0,1"
newline
bitfld.long 0x28 11. "SFLUSH3,Flush the Slave Transmit ID3 FIFO" "0,1"
bitfld.long 0x28 10. "SFLUSH2,Flush the Slave Transmit ID2 FIFO" "0,1"
newline
bitfld.long 0x28 9. "SFLUSH1,Flush the Slave Transmit ID1 FIFO" "0,1"
bitfld.long 0x28 8. "SFLUSH0,Flush the Slave Transmit ID0 FIFO" "0,1"
newline
rbitfld.long 0x28 6.--7. "STX3FSTA,Slave Transmit ID3 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x28 4.--5. "STX2FSTA,Slave Transmit ID2 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
newline
rbitfld.long 0x28 2.--3. "STX1FSTA,Slave Transmit ID1 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
rbitfld.long 0x28 0.--1. "STX0FSTA,Slave Transmit ID0 FIFO Status" "0: FIFO Empty,1: 1 Bytes in the FIFO,2: 2 Bytes in the FIFO,3: Reserved"
line.long 0x2C "SLV_ADDR1,Slave 10 Bits Address 1st Byte."
hexmask.long.byte 0x2C 0.--7. 1. "SLV_ADR1,Slave 10 Bits Address 1st Byte"
line.long 0x30 "SLV_ADDR2,Slave 10 Bits Address 2nd Byte."
hexmask.long.byte 0x30 0.--7. 1. "SLV_ADR2,Slave 10 Bit Address 2nd Byte"
rgroup.long 0x68++0x3
line.long 0x0 "SSTAT2,Slave I2C Status/IRQ 2"
bitfld.long 0x0 2. "rw_direction,Slave I2C RW Direction." "0,1"
bitfld.long 0x0 1. "addr_ack_irq,Slave ADDR ACK Interruption State." "0,1"
newline
bitfld.long 0x0 0. "sscl_irq,Stretch Interruption State." "0,1"
tree.end
tree.end
tree "MDIO"
base ad:0x40022000
group.long 0x0++0x3
line.long 0x0 "MDCON,MDIO Block Control"
bitfld.long 0x0 8. "MD_EN,MD Enable" "0,1"
bitfld.long 0x0 2. "MD_DRV,Enable Open-drain or Push-pull of MDIO Drive" "0: MDIO Drive Open Drain.,1: MDIO Drive Push-pull."
bitfld.long 0x0 1. "MD_PHM,Enable PHY Address Bit Width" "0: 5bits PHYADD is active,1: 3bits PHYADD is active two MSBS are ignored"
newline
bitfld.long 0x0 0. "MD_RST,Write 1 to Reset MDIO Block." "0: Reset MDIO,1: Reset MDIO"
rgroup.long 0x4++0xB
line.long 0x0 "MDFRM,MDIO Received Frame Control Information"
hexmask.long.byte 0x0 7.--11. 1. "MD_DEV,Received DEVADD"
hexmask.long.byte 0x0 2.--6. 1. "MD_PHY,Received PHYADR."
bitfld.long 0x0 0.--1. "MD_OP,Received OP" "0: Address Frame.,1: Write Frame.,2: PostReadIncAdd Frame.,3: Read Frame."
line.long 0x4 "MDRXD,MDIO Received Data"
hexmask.long.word 0x4 0.--15. 1. "MD_RXD,Received Data"
line.long 0x8 "MDADR,MDIO Received Address"
hexmask.long.word 0x8 0.--15. 1. "MD_ADR,Received Address"
group.long 0x10++0x7
line.long 0x0 "MDTXD,MDIO Data for Transmission"
hexmask.long.word 0x0 0.--15. 1. "MD_TXD,TX Data"
line.long 0x4 "MDPHY,MDIO PHYADDR Software Values and Selection and DEVADD"
hexmask.long.byte 0x4 10.--14. 1. "MD_DEVADD,Expected DEVADD"
hexmask.long.byte 0x4 5.--9. 1. "MD_PHYSEL,Selects Expected PHYADR Bits"
hexmask.long.byte 0x4 0.--4. 1. "MD_PHYSW,Software Provided PHYADR"
rgroup.long 0x18++0x3
line.long 0x0 "MDSTA,MDIO Progress Signaling Through Frame"
bitfld.long 0x0 7. "MD_PHYN,PHY Address Non Matching Status" "0,1"
bitfld.long 0x0 6. "MD_PHYM,PHY Address Matching Status" "0,1"
bitfld.long 0x0 5. "MD_DEVN,Device Address None Match Status" "0,1"
newline
bitfld.long 0x0 4. "MD_DEVM,Device Address Matching Status" "0,1"
bitfld.long 0x0 3. "MD_RDF,Read Frame Status" "0,1"
bitfld.long 0x0 2. "MD_INCF,Post Read Increment Address Frame Status" "0,1"
newline
bitfld.long 0x0 1. "MD_ADRF,Address Frame Status" "0,1"
bitfld.long 0x0 0. "MD_WRF,Write Frame Status" "0,1"
group.long 0x1C++0x3
line.long 0x0 "MDIEN,MDIO Interrupt Enables"
bitfld.long 0x0 7. "MD_PHYNI,Interrupt Enable for MD_PHYN" "0,1"
bitfld.long 0x0 6. "MD_PHYMI,Interrupt Enable for MD_PHYM" "0,1"
bitfld.long 0x0 5. "MD_DEVNI,Interrupt Enable for MD_DEVN" "0,1"
newline
bitfld.long 0x0 4. "MD_DEVMI,Interrupt Enable for MD_DEVM" "0,1"
bitfld.long 0x0 3. "MD_RDFI,Interrupt Enable for MD_RDF" "0,1"
bitfld.long 0x0 2. "MD_INCFI,Interrupt Enable for MD_INCF" "0,1"
newline
bitfld.long 0x0 1. "MD_ADRI,Interrupt Enable for MD_ADRF" "0,1"
bitfld.long 0x0 0. "MD_WRFI,Interrupt Enable for MD_WRF" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "MDPIN,MDIO Read PHYADDR Pins"
hexmask.long.byte 0x0 0.--4. 1. "MD_PIN,PRTADR Pins"
group.long 0x28++0x7
line.long 0x0 "DMAEN,MDIO DMA Enable"
bitfld.long 0x0 3. "WR_DATA,Write Data" "0,1"
bitfld.long 0x0 2. "WR_ADR,Write Address" "0,1"
bitfld.long 0x0 1. "INCRD_DATA,Increment Read Data" "0,1"
newline
bitfld.long 0x0 0. "RD_DATA,Read Data" "0,1"
line.long 0x4 "MDTESTCON,MDIO Test Controller Protected by Test Key"
bitfld.long 0x4 13. "En_TA_output,Enable Output Different During OP Phase" "0,1"
bitfld.long 0x4 12. "TA_1_value,Output Value During Second Bit of OP" "0,1"
bitfld.long 0x4 11. "TA_0_value,Output Value During First Bit of OP" "0,1"
tree.end
tree "MISC16 (Silicon Identification)"
base ad:0x40002000
rgroup.long 0x20++0x7
line.long 0x0 "ADIID,ADI ID"
hexmask.long.word 0x0 0.--15. 1. "ADIID,ADI ID"
line.long 0x4 "CHIPID,Chip ID"
hexmask.long.word 0x4 4.--15. 1. "PARTID,Part Identifier"
hexmask.long.byte 0x4 0.--3. 1. "REVISION,Silicon Revision Number"
wgroup.long 0x134++0x3
line.long 0x0 "USERKEY,Open to Customer to Protect Important Registers"
hexmask.long 0x0 0.--31. 1. "KEY,User Key"
tree.end
tree "PGA (PGA/TIA Input Amplifier)"
base ad:0x40069000
group.long 0x0++0x3
line.long 0x0 "PGABIASCON,PGA Bias Circuit Control Signal"
bitfld.long 0x0 5. "PD3BUF1P25,BUF1P25 Power Down" "0: BUF1p25 Enable,1: BUF1p25 Power Down"
bitfld.long 0x0 4. "PD2BUF1P25,BUF1P25 Power Down" "0: BUF1p25 Enable,1: BUF1p25 Power Down"
newline
bitfld.long 0x0 3. "PD1BUF1P25,BUF1P25 Power Down" "0: BUF1p25 Enable,1: BUF1p25 Power Down"
bitfld.long 0x0 2. "PD0BUF1P25,BUF1P25 Power Down" "0: BUF1p25 Enable,1: BUF1p25 Power Down"
newline
bitfld.long 0x0 1. "PD1BUF0P2,Buf_200mv Power Down" "0: Buf_200mV Enable,1: Buf_200mv Power Down"
bitfld.long 0x0 0. "PD0BUF0P2,Buf_200mv Power Down" "0: Buf_200mV Enable,1: Buf_200mv Power Down"
group.long 0x20++0xB
line.long 0x0 "PGA0CON,PGA0 Control Register"
bitfld.long 0x0 15. "TIASRCEN,Select Between Source Mode and Sink Mode" "0: Sink Mode,1: Source Mode"
bitfld.long 0x0 14. "DRVEN,Sink Current Ability Improve" "0: Disable Isink Ability Improvement Normal Drive,1: Enable Isink Ability Improvement"
newline
bitfld.long 0x0 11.--12. "TIAVDACSEL,TIA Vbias Selection of VDAC Channel" "0: Select VDAC8 as TIA Vbias,1: Select VDAC9 as TIA Vbias,2: Select VDAC10 as TIA Vbias,3: Select VDAC11 as TIA Vbias"
bitfld.long 0x0 8.--10. "TIAGAIN,TIA Gain Configuration" "0: TIARES=250ohm,1: TIARES=750ohm,2: TIARES=2kohm,3: TIARES=5kohm,4: TIARES=10kohm,5: TIARES=20kohm,6: TIARES=100kohm,?"
newline
bitfld.long 0x0 5.--7. "PGAGAIN,PGA Gain Configuration" "0: Gain=1,1: GAIN=2,2: GAIN=4,3: GAIN=6,4: GAIN=8,5: GAIN=10,?,?"
bitfld.long 0x0 3. "CAPBYPASS,Bypass the External Cap" "0: Select the External CAP,1: Bypass the External Cap"
newline
bitfld.long 0x0 2. "PGAMODE,PGA DC Mode or AC Couple Mode Selection" "0: PGA DC Mode Enable,1: PGA AC Coupling Mode Enable"
bitfld.long 0x0 1. "MODE,PGA or TIA Mode Selection" "0: PGA Mode Enable,1: TIA Mode Enable"
newline
bitfld.long 0x0 0. "PDPGACORE,PGA Core Power Down" "0,1"
line.long 0x4 "PGA0CHPCON,PGA0 Chop Function Ctrl"
bitfld.long 0x4 0. "CHOPOFF,Disable Chop Function" "0: Enable Chop Function,1: Disable Chop Function"
line.long 0x8 "PGA3CHPCON,PGA3 Chop Function Ctrl"
bitfld.long 0x8 0. "CHOPOFF,Disable Chop Function" "0: Enable Chop Function,1: Disable Chop Function"
group.long 0x70++0x7
line.long 0x0 "PGA1CON,PGA1 Control Register"
bitfld.long 0x0 15. "TIASRCEN,Select Between Source Mode and Sink Mode" "0: Sink Mode,1: Source Mode"
bitfld.long 0x0 14. "DRVEN,Sink Current Ability Improve" "0: Disable Isink Ability Improvement Normal Drive,1: Enable Isink Ability Improvement"
newline
bitfld.long 0x0 11.--12. "TIAVDACSEL,TIA Vbias Selection of VDAC Channel" "0: Select VDAC8 as TIA Vbias,1: Select VDAC9 as TIA Vbias,2: Select VDAC10 as TIA Vbias,3: Select VDAC11 as TIA Vbias"
bitfld.long 0x0 8.--10. "TIAGAIN,TIA Gain Configuration" "0: TIARES=250ohm,1: TIARES=750ohm,2: TIARES=2kohm,3: TIARES=5kohm,4: TIARES=10kohm,5: TIARES=20kohm,6: TIARES=100kohm,?"
newline
bitfld.long 0x0 5.--7. "PGAGAIN,PGA Gain Configuration" "0: Gain=1,1: GAIN=2,2: GAIN=4,3: GAIN=6,4: GAIN=8,5: GAIN=10,?,?"
bitfld.long 0x0 2. "PGAMODE,PGA DC Mode or AC Couple Mode Selection" "0: PGA DC Mode Enable,1: PGA AC Coupling Mode Enable"
newline
bitfld.long 0x0 1. "MODE,PGA or TIA Mode Selection" "0: PGA Mode Enable,1: TIA Mode Enable"
bitfld.long 0x0 0. "PDPGACORE,PGA Core Power Down" "0,1"
line.long 0x4 "PGA1CHPCON,PGA1 Chop Function Ctrl"
bitfld.long 0x4 0. "CHOPOFF,Disable Chop Function" "0: Enable Chop Function,1: Disable Chop Function"
group.long 0xA0++0x7
line.long 0x0 "PGA2CON,PGA2 Control Register"
bitfld.long 0x0 15. "TIASRCEN,Select Between Source Mode and Sink Mode" "0: Sink Mode,1: Source Mode"
bitfld.long 0x0 14. "DRVEN,Sink Current Ability Improve" "0: Disable Isink Ability Improvement Normal Drive,1: Enable Isink Ability Improvement"
newline
bitfld.long 0x0 11.--12. "TIAVDACSEL,TIA Vbias Selection of VDAC Channel" "0: Select VDAC8 as TIA Vbias,1: Select VDAC9 as TIA Vbias,2: Select VDAC10 as TIA Vbias,3: Select VDAC11 as TIA Vbias"
bitfld.long 0x0 8.--10. "TIAGAIN,TIA Gain Configuration" "0: TIARES=250ohm,1: TIARES=750ohm,2: TIARES=2kohm,3: TIARES=5kohm,4: TIARES=10kohm,5: TIARES=20kohm,6: TIARES=100kohm,?"
newline
bitfld.long 0x0 5.--7. "PGAGAIN,PGA Gain Configuration" "0: Gain=1,1: GAIN=2,2: GAIN=4,3: GAIN=6,4: GAIN=8,5: GAIN=10,?,?"
bitfld.long 0x0 3. "CAPBYPASS,Bypass the External Cap" "0: Select the External CAP,1: Bypass the External Cap"
newline
bitfld.long 0x0 2. "PGAMODE,PGA DC Mode or AC Couple Mode Selection" "0: PGA DC Mode Enable,1: PGA AC Coupling Mode Enable"
bitfld.long 0x0 1. "MODE,PGA or TIA Mode Selection" "0: PGA Mode Enable,1: TIA Mode Enable"
newline
bitfld.long 0x0 0. "PDPGACORE,PGA Core Power Down" "0,1"
line.long 0x4 "PGA2CHPCON,PGA2 Chop Function Ctrl"
bitfld.long 0x4 0. "CHOPOFF,Disable Chop Function" "0: Enable Chop Function,1: Disable Chop Function"
group.long 0xD0++0x3
line.long 0x0 "PGA3CON,PGA3 Control Register"
bitfld.long 0x0 15. "TIASRCEN,Select Between Source Mode and Sink Mode" "0: Sink Mode,1: Source Mode"
bitfld.long 0x0 14. "DRVEN,Sink Current Ability Improve" "0: Disable Isink Ability Improvement Normal Drive,1: Enable Isink Ability Improvement"
newline
bitfld.long 0x0 11.--12. "TIAVDACSEL,TIA Vbias Selection of VDAC Channel" "0: Select VDAC8 as TIA Vbias,1: Select VDAC9 as TIA Vbias,2: Select VDAC10 as TIA Vbias,3: Select VDAC11 as TIA Vbias"
bitfld.long 0x0 8.--10. "TIAGAIN,TIA Gain Configuration" "0: TIARES=250ohm,1: TIARES=750ohm,2: TIARES=2kohm,3: TIARES=5kohm,4: TIARES=10kohm,5: TIARES=20kohm,6: TIARES=100kohm,?"
newline
bitfld.long 0x0 5.--7. "PGAGAIN,PGA Gain Configuration" "0: Gain=1,1: GAIN=2,2: GAIN=4,3: GAIN=6,4: GAIN=8,5: GAIN=10,?,?"
bitfld.long 0x0 2. "PGAMODE,PGA DC Mode or AC Couple Mode Selection" "0: PGA DC Mode Enable,1: PGA AC Coupling Mode Enable"
newline
bitfld.long 0x0 1. "MODE,PGA or TIA Mode Selection" "0: PGA Mode Enable,1: TIA Mode Enable"
bitfld.long 0x0 0. "PDPGACORE,PGA Core Power Down" "0,1"
tree.end
tree "PLA (Programmable Logic Array)"
base ad:0x40006000
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40006000 ad:0x40006004 ad:0x40006008 ad:0x4000600C ad:0x40006010 ad:0x40006014 ad:0x40006018 ad:0x4000601C ad:0x40006020 ad:0x40006024 ad:0x40006028 ad:0x4000602C ad:0x40006030 ad:0x40006034 ad:0x40006038 ad:0x4000603C)
tree "ELMxcon[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "PLA_ELEM,ELEMx Configuration Register"
bitfld.long 0x0 10.--12. "MUX0,Mux for Even Element Feedback(in Respective Block)" "0: Feedback from Element 0 (all Except Element 0) /..,1: Feedback from Element 2,2: Feedback from Element 4,3: Feedback from Element 6,4: Feedback from Element 8,5: Feedback from Element 10,6: Feedback from Element 12,7: Feedback from Element 14"
bitfld.long 0x0 7.--9. "MUX1,Mux for Odd Element Feedback (In Respective Block)" "0: Feedback from Element 1,1: Feedback from Element 3,2: Feedback from Element 5,3: Feedback from Element 7,4: Feedback from Element 9,5: Feedback from Element 11,6: Feedback from Element 13,7: Feedback from Element 15"
bitfld.long 0x0 6. "MUX2,Mux Between PLA_DINx Register/Block0 Output or Even Feedback" "0: PLA_DINx Input,1: Even Feedback Mux"
newline
bitfld.long 0x0 5. "MUX3,Mux Between GPIO Bus Input or Odd Feedback Input" "0: Odd Feedback Mux,1: GPIO Input"
hexmask.long.byte 0x0 1.--4. 1. "TBL,Configures Output"
bitfld.long 0x0 0. "MUX4,Select or Bypass Flip-flop Output" "0: FF Output,1: Bypass Output"
tree.end
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40006040 ad:0x40006044 ad:0x40006048 ad:0x4000604C ad:0x40006050 ad:0x40006054 ad:0x40006058 ad:0x4000605C ad:0x40006060 ad:0x40006064 ad:0x40006068 ad:0x4000606C ad:0x40006070 ad:0x40006074 ad:0x40006078 ad:0x4000607C)
tree "ELMxcon[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "PLA_ELEM,ELEMx Configuration Register"
bitfld.long 0x0 10.--12. "MUX0,Mux for Even Element Feedback(in Respective Block)" "0: Feedback from Element 0 (all Except Element 0) /..,1: Feedback from Element 2,2: Feedback from Element 4,3: Feedback from Element 6,4: Feedback from Element 8,5: Feedback from Element 10,6: Feedback from Element 12,7: Feedback from Element 14"
bitfld.long 0x0 7.--9. "MUX1,Mux for Odd Element Feedback (In Respective Block)" "0: Feedback from Element 1,1: Feedback from Element 3,2: Feedback from Element 5,3: Feedback from Element 7,4: Feedback from Element 9,5: Feedback from Element 11,6: Feedback from Element 13,7: Feedback from Element 15"
bitfld.long 0x0 6. "MUX2,Mux Between PLA_DINx Register/Block0 Output or Even Feedback" "0: PLA_DINx Input,1: Even Feedback Mux"
newline
bitfld.long 0x0 5. "MUX3,Mux Between GPIO Bus Input or Odd Feedback Input" "0: Odd Feedback Mux,1: GPIO Input"
hexmask.long.byte 0x0 1.--4. 1. "TBL,Configures Output"
bitfld.long 0x0 0. "MUX4,Select or Bypass Flip-flop Output" "0: FF Output,1: Bypass Output"
tree.end
repeat.end
base ad:0x40006000
group.long 0x80++0x13
line.long 0x0 "PLA_CLK,PLA Clock Select"
bitfld.long 0x0 4.--6. "BLOCK1,Clock Select for Block 1" "0: GPIO Clock 0,1: GPIO Clock 1,2: GPIO Clock 2,3: PCLK0,4: MOSC (16 MHz),5: Timer 0,6: Timer 2,7: KOSC (32 KHz)"
bitfld.long 0x0 0.--2. "BLOCK0,Clock Select for Block 0" "0: GPIO Clock 0,1: GPIO Clock 1,2: GPIO Clock 2,3: PCLK0,4: MOSC (16 MHz),5: Timer 0,6: Timer 2,7: KOSC (32 KHz)"
line.long 0x4 "PLA_IRQ0,Interrupt Register for Block 0"
bitfld.long 0x4 12. "irq1_en,IRQ1 Enable" "0: Disable IRQ1 Interrupt,1: Enable IRQ1 Interrupt"
hexmask.long.byte 0x4 8.--11. 1. "irq1_src,IRQ1 Source Select"
newline
bitfld.long 0x4 4. "irq0_en,IRQ0 Enable" "0: Disable IRQ0 Interrupt,1: Enable IRQ0 Interrupt"
hexmask.long.byte 0x4 0.--3. 1. "irq0_src,IRQ0 Source Select"
line.long 0x8 "PLA_IRQ1,Interrupt Register for Block1"
bitfld.long 0x8 12. "irq3_en,IRQ3 Enable" "0: Disable IRQ3 Interrupt,1: Enable IRQ3 Interrupt"
hexmask.long.byte 0x8 8.--11. 1. "irq3_src,IRQ3 Source Select"
newline
bitfld.long 0x8 4. "irq2_en,IRQ2 Enable" "0: Disable IRQ2 Interrupt,1: Enable IRQ2 Interrupt"
hexmask.long.byte 0x8 0.--3. 1. "irq2_src,IRQ2 Source Select"
line.long 0xC "PLA_ADC,ADC Configuration Register"
bitfld.long 0xC 5. "convst_en,Bit to Enable ADC Start Convert from PLA" "0: Disable,1: Enable"
hexmask.long.byte 0xC 0.--4. 1. "convst_src,Element for ADC Start Convert Source"
line.long 0x10 "PLA_DIN0,AMBA Bus Data Input for Block 0"
hexmask.long.word 0x10 0.--15. 1. "DIN,Input Bit to Element 15 to Element 0."
rgroup.long 0x98++0x7
line.long 0x0 "PLA_DOUT0,AMBA Bus Data Output for Block 0"
bitfld.long 0x0 15. "E15,Output Bit from Element 15" "0,1"
bitfld.long 0x0 14. "E14,Output Bit from Element 14" "0,1"
newline
bitfld.long 0x0 13. "E13,Output Bit from Element 13" "0,1"
bitfld.long 0x0 12. "E12,Output Bit from Element 12" "0,1"
newline
bitfld.long 0x0 11. "E11,Output Bit from Element 11" "0,1"
bitfld.long 0x0 10. "E10,Output Bit from Element 10" "0,1"
newline
bitfld.long 0x0 9. "E9,Output Bit from Element 9" "0,1"
bitfld.long 0x0 8. "E8,Output Bit from Element 8" "0,1"
newline
bitfld.long 0x0 7. "E7,Output Bit from Element 7" "0,1"
bitfld.long 0x0 6. "E6,Output Bit from Element 6" "0,1"
newline
bitfld.long 0x0 5. "E5,Output Bit from Element 5" "0,1"
bitfld.long 0x0 4. "E4,Output Bit from Element 4" "0,1"
newline
bitfld.long 0x0 3. "E3,Output Bit from Element 3" "0,1"
bitfld.long 0x0 2. "E2,Output Bit from Element 2" "0,1"
newline
bitfld.long 0x0 1. "E1,Output Bit from Element 1" "0,1"
bitfld.long 0x0 0. "E0,Output Bit from Element 0" "0,1"
line.long 0x4 "PLA_DOUT1,AMBA Bus Data Output for Block1"
bitfld.long 0x4 15. "E31,Output Bit from Element 31" "0,1"
bitfld.long 0x4 14. "E30,Output Bit from Element 30" "0,1"
newline
bitfld.long 0x4 13. "E29,Output Bit from Element 29" "0,1"
bitfld.long 0x4 12. "E28,Output Bit from Element 28" "0,1"
newline
bitfld.long 0x4 11. "E27,Output Bit from Element 27" "0,1"
bitfld.long 0x4 10. "E26,Output Bit from Element 26" "0,1"
newline
bitfld.long 0x4 9. "E25,Output Bit from Element 25" "0,1"
bitfld.long 0x4 8. "E24,Output Bit from Element 24" "0,1"
newline
bitfld.long 0x4 7. "E23,Output Bit from Element 23" "0,1"
bitfld.long 0x4 6. "E22,Output Bit from Element 22" "0,1"
newline
bitfld.long 0x4 5. "E21,Output Bit from Element 21" "0,1"
bitfld.long 0x4 4. "E20,Output Bit from Element 20" "0,1"
newline
bitfld.long 0x4 3. "E19,Output Bit from Element 19" "0,1"
bitfld.long 0x4 2. "E18,Output Bit from Element 18" "0,1"
newline
bitfld.long 0x4 1. "E17,Output Bit from Element 17" "0,1"
bitfld.long 0x4 0. "E16,Output Bit from Element 16" "0,1"
group.long 0xA0++0x7
line.long 0x0 "PLA_LCK,Write Lock Register."
bitfld.long 0x0 0. "LOCKED,Set to Disable Writing to Registers" "0: Writing to Registers Allowed,1: Writing to Registers Disabled"
line.long 0x4 "PLA_IRQTYPE,PLA Interrupt Request and DMA Request Type"
bitfld.long 0x4 6.--7. "irq3_type,IRQ3 and DMA Request 3 Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and High Level..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Low Level.."
bitfld.long 0x4 4.--5. "irq2_type,IRQ2 and DMA Request 2 Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and High Level..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Low Level.."
newline
bitfld.long 0x4 2.--3. "irq1_type,IRQ1 and DMA Request 1Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and High Level..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Low Level.."
bitfld.long 0x4 0.--1. "irq0_type,IRQ0 and DMA Request 0 Type" "0: High Level Trigger Interrupt and High Level..,1: Rising Edge Trigger Interrupt and Rising Edge..,2: Low Level Trigger Interrupt and Low Level..,3: Falling Edge Trigger Interrupt and Falling Edge.."
tree.end
tree "PLL"
base ad:0x40069200
group.long 0x0++0x3
line.long 0x0 "PLLPDCTRL,Unknown"
bitfld.long 0x0 6. "TOTPDB,PDB of PLL All" "0,1"
tree.end
tree "PWM (Pulse Width Modulator)"
base ad:0x40064000
group.long 0x0++0xB
line.long 0x0 "PWMCON0,PWM Control Register"
bitfld.long 0x0 15. "SYNC,Set to Enable PWM Synchronization from the SYNC Pin" "0: Ignore Transition from the SYNC Pin,1: All PWM Counters are Reset on the Next Clock.."
bitfld.long 0x0 14. "PWM7INV,Set to Invert PWM7 Output" "0,1"
newline
bitfld.long 0x0 13. "PWM5INV,Set to Invert PWM5 Output" "0,1"
bitfld.long 0x0 12. "PWM3INV,Set to Invert PWM3 Output" "0,1"
newline
bitfld.long 0x0 11. "PWM1INV,Set to Invert PWM1 Output" "0,1"
bitfld.long 0x0 10. "PWMIEN,Set to Enable Interrupts for PWM" "0,1"
newline
bitfld.long 0x0 9. "ENA,Enable for Pair 0 and 1 When HOFF=0 and HMODE=1" "0: Disable Pair 0 and 1,1: Enable Pair 0 and 1"
bitfld.long 0x0 6.--8. "PWMCMP,PWM Clock Prescaler. Sets UCLK Divider." "0: UCLK/2,1: UCLK/4,2: UCLK/8,3: UCLK/16,4: UCLK/32,5: UCLK/64,6: UCLK/128,7: UCLK/256"
newline
bitfld.long 0x0 5. "POINV,Set to Invert PWM Outputs for Pair 0/1 in H-bridge Mode" "0,1"
bitfld.long 0x0 4. "HOFF,Set to Turn off the High-side for Pair 0/1 in H-bridge Mode" "0,1"
newline
bitfld.long 0x0 3. "LCOMP,Signal to Load a New Set of Compare Register Values" "0: Use the Values Previously Store in the Compare..,1: Load the Internal Compare Registers with Values.."
bitfld.long 0x0 2. "HDIR,Direction Control When PWM is in H-bridge Mode" "0: PWM2 and PWM3 Act as Output Signals While PWM0..,1: PWM0 and PWM1 Act as Output Signals While PWM2.."
newline
bitfld.long 0x0 1. "HMODE,Set to Enable H-bridge Mode" "0,1"
bitfld.long 0x0 0. "PWMEN,Master Enable for PWM" "0: Disable All PWM Outputs,1: Enable All PWM Outputs"
line.long 0x4 "PWMCON1,ADC Conversion Start and Trip Control Register"
hexmask.long.byte 0x4 8.--15. 1. "REVREG1,Reserved. Return 0 on Reads"
bitfld.long 0x4 6. "TRIP_EN,Set to Enable PWM Trip Functionality" "0,1"
newline
rbitfld.long 0x4 4.--5. "REVREG0,Reserved" "0,1,2,3"
line.long 0x8 "PWMICLR,Hardware Trip Configuration Register"
hexmask.long.word 0x8 5.--15. 1. "REVREG2,Reserved. Return 0 on Reads"
bitfld.long 0x8 4. "TRIP,Write a 1 to Clear Latched IRQPWMTrip Interrupt." "0,1"
newline
bitfld.long 0x8 3. "PWM3,Write a 1 to Clear Latched IRQPWM3 Interrupt." "0,1"
bitfld.long 0x8 2. "PWM2,Write a 1 to Clear Latched IRQPWM2 Interrupt." "0,1"
newline
bitfld.long 0x8 1. "PWM1,Write a 1 to Clear Latched IRQPWM1 Interrupt." "0,1"
bitfld.long 0x8 0. "PWM0,Write a 1 to Clear Latched IRQPWM0 Interrupt." "0,1"
group.long 0x10++0x3F
line.long 0x0 "PWM0COM0,Compare Register 0 for PWM0 and PWM1"
hexmask.long.word 0x0 0.--15. 1. "PWM0COM0,Compare Register 0 for PWM0 and PWM1"
line.long 0x4 "PWM0COM1,Compare Register 1 for PWM0 and PWM1"
hexmask.long.word 0x4 0.--15. 1. "PWM0COM1,Compare Register 1 for PWM0 and PWM1"
line.long 0x8 "PWM0COM2,Compare Register 2 for PWM0 and PWM1"
hexmask.long.word 0x8 0.--15. 1. "PWM0COM2,Compare Register 2 for PWM0 and PWM1"
line.long 0xC "PWM0LEN,Period Value Register for PWM0 and PWM1"
hexmask.long.word 0xC 0.--15. 1. "PWM0LEN,Period Value Register for PWM0 and PWM1"
line.long 0x10 "PWM1COM0,Compare Register 0 for PWM2 and PWM3"
hexmask.long.word 0x10 0.--15. 1. "PWM1COM0,Compare Register 0 for PWM2 and PWM3"
line.long 0x14 "PWM1COM1,Compare Register 1 for PWM2 and PWM3"
hexmask.long.word 0x14 0.--15. 1. "PWM1COM1,Compare Register 1 for PWM2 and PWM3"
line.long 0x18 "PWM1COM2,Compare Register 2 for PWM2 and PWM3"
hexmask.long.word 0x18 0.--15. 1. "PWM1COM2,Compare Register 2 for PWM2 and PWM3"
line.long 0x1C "PWM1LEN,Period Value Register for PWM2 and PWM3"
hexmask.long.word 0x1C 0.--15. 1. "PWM1LEN,Period Value Register for PWM2 and PWM3"
line.long 0x20 "PWM2COM0,Compare Register 0 for PWM4 and PWM5"
hexmask.long.word 0x20 0.--15. 1. "PWM2COM0,Compare Register 0 for PWM4 and PWM5"
line.long 0x24 "PWM2COM1,Compare Register 1 for PWM4 and PWM5"
hexmask.long.word 0x24 0.--15. 1. "PWM2COM1,Compare Register 1 for PWM4 and PWM5"
line.long 0x28 "PWM2COM2,Compare Register 2 for PWM4 and PWM5"
hexmask.long.word 0x28 0.--15. 1. "PWM2COM2,Compare Register 2 for PWM4 and PWM5"
line.long 0x2C "PWM2LEN,Period Value Register for PWM4 and PWM5"
hexmask.long.word 0x2C 0.--15. 1. "PWM2LEN,Period Value Register for PWM4 and PWM5"
line.long 0x30 "PWM3COM0,Compare Register 0 for PWM6 and PWM7"
hexmask.long.word 0x30 0.--15. 1. "PWM3COM0,Compare Register 0 for PWM6 and PWM7"
line.long 0x34 "PWM3COM1,Compare Register 1 for PWM6 and PWM7"
hexmask.long.word 0x34 0.--15. 1. "PWM3COM1,Compare Register 1 for PWM6 and PWM7"
line.long 0x38 "PWM3COM2,Compare Register 2 for PWM6 and PWM7"
hexmask.long.word 0x38 0.--15. 1. "PWM3COM2,Compare Register 2 for PWM6 and PWM7"
line.long 0x3C "PWM3LEN,Period Value Register for PWM6 and PWM7"
hexmask.long.word 0x3C 0.--15. 1. "PWM3LEN,Period Value Register for PWM6 and PWM7"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "D2D0"
base ad:0x40024000
group.long 0x0++0x3
line.long 0x0 "STAT,Status"
bitfld.long 0x0 15. "RDY,Detected an Edge on Ready Indicator for Flow-control" "0,1"
bitfld.long 0x0 14. "CSFALL,Detected a Falling Edge on CS in Slave CON Mode" "0,1"
newline
bitfld.long 0x0 13. "CSRISE,Detected a Rising Edge on CS in Slave CON Mode" "0,1"
bitfld.long 0x0 12. "CSERR,Detected a CS Error Condition in Slave Mode" "0,1"
newline
rbitfld.long 0x0 11. "CS,CS Status" "0,1"
bitfld.long 0x0 7. "RXOVR,SPI Rx FIFO Overflow" "0,1"
newline
bitfld.long 0x0 6. "RXIRQ,SPI Rx IRQ" "0,1"
bitfld.long 0x0 5. "TXIRQ,SPI Tx IRQ" "0,1"
newline
bitfld.long 0x0 4. "TXUNDR,SPI Tx FIFO Underflow" "0,1"
bitfld.long 0x0 3. "TXDONE,SPI Tx Done in Read Command Mode" "0,1"
newline
bitfld.long 0x0 2. "TXEMPTY,SPI Tx FIFO Empty Interrupt" "0,1"
bitfld.long 0x0 1. "XFRDONE,SPI Transfer Completion" "0,1"
newline
rbitfld.long 0x0 0. "IRQ,SPI Interrupt Status" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "RX,Receive"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Receive Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Receive Buffer"
wgroup.long 0x8++0x3
line.long 0x0 "TX,Transmit"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Transmit Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Transmit Buffer"
group.long 0xC++0x13
line.long 0x0 "DIV,SPI Baud Rate Selection"
bitfld.long 0x0 8. "SFR,Slave Free Run Mode" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "DIV,SPI Clock Divider"
line.long 0x4 "CTL,SPI Configuration 1"
bitfld.long 0x4 14. "CSRST,Reset Mode for CS Error Bit" "0,1"
bitfld.long 0x4 13. "TFLUSH,SPI Tx FIFO Flush Enable" "0,1"
newline
bitfld.long 0x4 12. "RFLUSH,SPI Rx FIFO Flush Enable" "0,1"
bitfld.long 0x4 11. "CON,Continuous Transfer Enable" "0,1"
newline
bitfld.long 0x4 10. "LOOPBACK,Loopback Enable" "0,1"
bitfld.long 0x4 9. "OEN,Slave MISO Output Enable" "0,1"
newline
bitfld.long 0x4 8. "RXOF,RX Overflow Overwrite Enable" "0,1"
bitfld.long 0x4 7. "ZEN,Transmit Zeros Enable" "0,1"
newline
bitfld.long 0x4 6. "TIM,SPI Transfer and Interrupt Mode" "0,1"
bitfld.long 0x4 5. "LSB,LSB First Transfer Enable" "0,1"
newline
bitfld.long 0x4 4. "WOM,SPI Wired or Mode" "0,1"
bitfld.long 0x4 3. "CPOL,Serial Clock Polarity" "0,1"
newline
bitfld.long 0x4 2. "CPHA,Serial Clock Phase Mode" "0,1"
bitfld.long 0x4 1. "MASEN,Master Mode Enable" "0,1"
newline
bitfld.long 0x4 0. "SPIEN,SPI Enable" "0,1"
line.long 0x8 "IEN,SPI Configuration 2"
bitfld.long 0x8 14. "TXEMPTY,Tx-FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x8 13. "XFRDONE,SPI Transfer Completion Interrupt Enable" "0,1"
newline
bitfld.long 0x8 12. "TXDONE,SPI Transmit Done Interrupt Enable" "0,1"
bitfld.long 0x8 11. "RDY,Ready Signal Edge Interrupt Enable" "0,1"
newline
bitfld.long 0x8 10. "RXOVR,Rx-overflow Interrupt Enable" "0,1"
bitfld.long 0x8 9. "TXUNDR,Tx-underflow Interrupt Enable" "0,1"
newline
bitfld.long 0x8 8. "CS,Enable Interrupt on Every CS Edge in Slave CON Mode" "0,1"
bitfld.long 0x8 0.--2. "IRQMODE,SPI IRQ Mode Bits" "0: Interrupt Occurs After 1 Byte is Transfered or..,1: Interrupt Occurs After 2 Byte is Transfered or..,2: Interrupt Occurs After 3 Byte is Transfered or..,3: Interrupt Occurs After 4 Byte is Transfered or..,4: Interrupt Occurs After 5 Byte is Transfered or..,5: Interrupt Occurs After 6 Byte is Transfered or..,6: Interrupt Occurs After 7 Byte is Transfered or..,7: Interrupt Occurs After 8 Byte is Transfered or.."
line.long 0xC "CNT,Transfer Byte Count"
bitfld.long 0xC 15. "FRAMECONT,Continue Frame" "0,1"
hexmask.long.word 0xC 0.--13. 1. "VALUES,Transfer Byte Count"
line.long 0x10 "DMA,SPI DMA Enable"
bitfld.long 0x10 2. "RXEN,Enable Receive DMA Request" "0,1"
bitfld.long 0x10 1. "TXEN,Enable Transmit DMA Request" "0,1"
newline
bitfld.long 0x10 0. "EN,Enable DMA for Data Transfer" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "FIFOSTAT,FIFO Status"
hexmask.long.byte 0x0 8.--11. 1. "RX,SPI Rx FIFO Status"
hexmask.long.byte 0x0 0.--3. 1. "TX,SPI Tx FIFO Status"
group.long 0x24++0xB
line.long 0x0 "RDCTL,Read Control"
bitfld.long 0x0 8. "THREEPIN,Three Pin SPI Mode" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "TXBYTES,Transmit Byte Count Minus 1 for Read Command"
newline
bitfld.long 0x0 1. "OVERLAP,Tx/Rx Overlap Mode" "0,1"
bitfld.long 0x0 0. "CMDEN,Read Command Enable" "0,1"
line.long 0x4 "FLOWCTL,Flow Control"
hexmask.long.word 0x4 6.--15. 1. "RDBURSTSZ,Read Data Burst Size Minus 1"
bitfld.long 0x4 4. "RDYPOL,Polarity of RDY/MISO Line" "0: Polarity is Active HIGH. SPI Master Waits Until..,1: Polarity is Active LOW. SPI Master Waits Until.."
newline
bitfld.long 0x4 0.--1. "MODE,Flow Control Mode" "0: Flow Control is Disabled.,1: Flow Control is Based on Timer (WAIT_TMR).,2: Flow Control is Based on RDY Signal.,3: Flow Control is Based on MISO Pin."
line.long 0x8 "WAITTMR,Wait Timer for Flow Control"
hexmask.long.word 0x8 0.--15. 1. "TRIMS,Wait Timer for Flow-control"
group.long 0x34++0x3
line.long 0x0 "CSOVERRIDE,Chip-Select Override"
bitfld.long 0x0 0.--1. "CTL,CS Override Control" "0: CS is Not Forced.,1: CS is Forced to Drive 1'b1.,2: CS is Forced to Drive 1'b0.,?"
tree.end
tree "D2D1"
base ad:0x40028000
group.long 0x0++0x3
line.long 0x0 "STAT,Status"
bitfld.long 0x0 15. "RDY,Detected an Edge on Ready Indicator for Flow-control" "0,1"
bitfld.long 0x0 14. "CSFALL,Detected a Falling Edge on CS in Slave CON Mode" "0,1"
newline
bitfld.long 0x0 13. "CSRISE,Detected a Rising Edge on CS in Slave CON Mode" "0,1"
bitfld.long 0x0 12. "CSERR,Detected a CS Error Condition in Slave Mode" "0,1"
newline
rbitfld.long 0x0 11. "CS,CS Status" "0,1"
bitfld.long 0x0 7. "RXOVR,SPI Rx FIFO Overflow" "0,1"
newline
bitfld.long 0x0 6. "RXIRQ,SPI Rx IRQ" "0,1"
bitfld.long 0x0 5. "TXIRQ,SPI Tx IRQ" "0,1"
newline
bitfld.long 0x0 4. "TXUNDR,SPI Tx FIFO Underflow" "0,1"
bitfld.long 0x0 3. "TXDONE,SPI Tx Done in Read Command Mode" "0,1"
newline
bitfld.long 0x0 2. "TXEMPTY,SPI Tx FIFO Empty Interrupt" "0,1"
bitfld.long 0x0 1. "XFRDONE,SPI Transfer Completion" "0,1"
newline
rbitfld.long 0x0 0. "IRQ,SPI Interrupt Status" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "RX,Receive"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Receive Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Receive Buffer"
wgroup.long 0x8++0x3
line.long 0x0 "TX,Transmit"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Transmit Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Transmit Buffer"
group.long 0xC++0x13
line.long 0x0 "DIV,SPI Baud Rate Selection"
bitfld.long 0x0 8. "SFR,Slave Free Run Mode" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "DIV,SPI Clock Divider"
line.long 0x4 "CTL,SPI Configuration 1"
bitfld.long 0x4 14. "CSRST,Reset Mode for CS Error Bit" "0,1"
bitfld.long 0x4 13. "TFLUSH,SPI Tx FIFO Flush Enable" "0,1"
newline
bitfld.long 0x4 12. "RFLUSH,SPI Rx FIFO Flush Enable" "0,1"
bitfld.long 0x4 11. "CON,Continuous Transfer Enable" "0,1"
newline
bitfld.long 0x4 10. "LOOPBACK,Loopback Enable" "0,1"
bitfld.long 0x4 9. "OEN,Slave MISO Output Enable" "0,1"
newline
bitfld.long 0x4 8. "RXOF,RX Overflow Overwrite Enable" "0,1"
bitfld.long 0x4 7. "ZEN,Transmit Zeros Enable" "0,1"
newline
bitfld.long 0x4 6. "TIM,SPI Transfer and Interrupt Mode" "0,1"
bitfld.long 0x4 5. "LSB,LSB First Transfer Enable" "0,1"
newline
bitfld.long 0x4 4. "WOM,SPI Wired or Mode" "0,1"
bitfld.long 0x4 3. "CPOL,Serial Clock Polarity" "0,1"
newline
bitfld.long 0x4 2. "CPHA,Serial Clock Phase Mode" "0,1"
bitfld.long 0x4 1. "MASEN,Master Mode Enable" "0,1"
newline
bitfld.long 0x4 0. "SPIEN,SPI Enable" "0,1"
line.long 0x8 "IEN,SPI Configuration 2"
bitfld.long 0x8 14. "TXEMPTY,Tx-FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x8 13. "XFRDONE,SPI Transfer Completion Interrupt Enable" "0,1"
newline
bitfld.long 0x8 12. "TXDONE,SPI Transmit Done Interrupt Enable" "0,1"
bitfld.long 0x8 11. "RDY,Ready Signal Edge Interrupt Enable" "0,1"
newline
bitfld.long 0x8 10. "RXOVR,Rx-overflow Interrupt Enable" "0,1"
bitfld.long 0x8 9. "TXUNDR,Tx-underflow Interrupt Enable" "0,1"
newline
bitfld.long 0x8 8. "CS,Enable Interrupt on Every CS Edge in Slave CON Mode" "0,1"
bitfld.long 0x8 0.--2. "IRQMODE,SPI IRQ Mode Bits" "0: Interrupt Occurs After 1 Byte is Transfered or..,1: Interrupt Occurs After 2 Byte is Transfered or..,2: Interrupt Occurs After 3 Byte is Transfered or..,3: Interrupt Occurs After 4 Byte is Transfered or..,4: Interrupt Occurs After 5 Byte is Transfered or..,5: Interrupt Occurs After 6 Byte is Transfered or..,6: Interrupt Occurs After 7 Byte is Transfered or..,7: Interrupt Occurs After 8 Byte is Transfered or.."
line.long 0xC "CNT,Transfer Byte Count"
bitfld.long 0xC 15. "FRAMECONT,Continue Frame" "0,1"
hexmask.long.word 0xC 0.--13. 1. "VALUES,Transfer Byte Count"
line.long 0x10 "DMA,SPI DMA Enable"
bitfld.long 0x10 2. "RXEN,Enable Receive DMA Request" "0,1"
bitfld.long 0x10 1. "TXEN,Enable Transmit DMA Request" "0,1"
newline
bitfld.long 0x10 0. "EN,Enable DMA for Data Transfer" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "FIFOSTAT,FIFO Status"
hexmask.long.byte 0x0 8.--11. 1. "RX,SPI Rx FIFO Status"
hexmask.long.byte 0x0 0.--3. 1. "TX,SPI Tx FIFO Status"
group.long 0x24++0xB
line.long 0x0 "RDCTL,Read Control"
bitfld.long 0x0 8. "THREEPIN,Three Pin SPI Mode" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "TXBYTES,Transmit Byte Count Minus 1 for Read Command"
newline
bitfld.long 0x0 1. "OVERLAP,Tx/Rx Overlap Mode" "0,1"
bitfld.long 0x0 0. "CMDEN,Read Command Enable" "0,1"
line.long 0x4 "FLOWCTL,Flow Control"
hexmask.long.word 0x4 6.--15. 1. "RDBURSTSZ,Read Data Burst Size Minus 1"
bitfld.long 0x4 4. "RDYPOL,Polarity of RDY/MISO Line" "0: Polarity is Active HIGH. SPI Master Waits Until..,1: Polarity is Active LOW. SPI Master Waits Until.."
newline
bitfld.long 0x4 0.--1. "MODE,Flow Control Mode" "0: Flow Control is Disabled.,1: Flow Control is Based on Timer (WAIT_TMR).,2: Flow Control is Based on RDY Signal.,3: Flow Control is Based on MISO Pin."
line.long 0x8 "WAITTMR,Wait Timer for Flow Control"
hexmask.long.word 0x8 0.--15. 1. "TRIMS,Wait Timer for Flow-control"
group.long 0x34++0x3
line.long 0x0 "CSOVERRIDE,Chip-Select Override"
bitfld.long 0x0 0.--1. "CTL,CS Override Control" "0: CS is Not Forced.,1: CS is Forced to Drive 1'b1.,2: CS is Forced to Drive 1'b0.,?"
tree.end
tree "SPI0"
base ad:0x40054000
group.long 0x0++0x3
line.long 0x0 "STAT,Status"
bitfld.long 0x0 15. "RDY,Detected an Edge on Ready Indicator for Flow-control" "0,1"
bitfld.long 0x0 14. "CSFALL,Detected a Falling Edge on CS in Slave CON Mode" "0,1"
newline
bitfld.long 0x0 13. "CSRISE,Detected a Rising Edge on CS in Slave CON Mode" "0,1"
bitfld.long 0x0 12. "CSERR,Detected a CS Error Condition in Slave Mode" "0,1"
newline
rbitfld.long 0x0 11. "CS,CS Status" "0,1"
bitfld.long 0x0 7. "RXOVR,SPI Rx FIFO Overflow" "0,1"
newline
bitfld.long 0x0 6. "RXIRQ,SPI Rx IRQ" "0,1"
bitfld.long 0x0 5. "TXIRQ,SPI Tx IRQ" "0,1"
newline
bitfld.long 0x0 4. "TXUNDR,SPI Tx FIFO Underflow" "0,1"
bitfld.long 0x0 3. "TXDONE,SPI Tx Done in Read Command Mode" "0,1"
newline
bitfld.long 0x0 2. "TXEMPTY,SPI Tx FIFO Empty Interrupt" "0,1"
bitfld.long 0x0 1. "XFRDONE,SPI Transfer Completion" "0,1"
newline
rbitfld.long 0x0 0. "IRQ,SPI Interrupt Status" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "RX,Receive"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Receive Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Receive Buffer"
wgroup.long 0x8++0x3
line.long 0x0 "TX,Transmit"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Transmit Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Transmit Buffer"
group.long 0xC++0x13
line.long 0x0 "DIV,SPI Baud Rate Selection"
bitfld.long 0x0 8. "SFR,Slave Free Run Mode" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "DIV,SPI Clock Divider"
line.long 0x4 "CTL,SPI Configuration 1"
bitfld.long 0x4 14. "CSRST,Reset Mode for CS Error Bit" "0,1"
bitfld.long 0x4 13. "TFLUSH,SPI Tx FIFO Flush Enable" "0,1"
newline
bitfld.long 0x4 12. "RFLUSH,SPI Rx FIFO Flush Enable" "0,1"
bitfld.long 0x4 11. "CON,Continuous Transfer Enable" "0,1"
newline
bitfld.long 0x4 10. "LOOPBACK,Loopback Enable" "0,1"
bitfld.long 0x4 9. "OEN,Slave MISO Output Enable" "0,1"
newline
bitfld.long 0x4 8. "RXOF,RX Overflow Overwrite Enable" "0,1"
bitfld.long 0x4 7. "ZEN,Transmit Zeros Enable" "0,1"
newline
bitfld.long 0x4 6. "TIM,SPI Transfer and Interrupt Mode" "0,1"
bitfld.long 0x4 5. "LSB,LSB First Transfer Enable" "0,1"
newline
bitfld.long 0x4 4. "WOM,SPI Wired or Mode" "0,1"
bitfld.long 0x4 3. "CPOL,Serial Clock Polarity" "0,1"
newline
bitfld.long 0x4 2. "CPHA,Serial Clock Phase Mode" "0,1"
bitfld.long 0x4 1. "MASEN,Master Mode Enable" "0,1"
newline
bitfld.long 0x4 0. "SPIEN,SPI Enable" "0,1"
line.long 0x8 "IEN,SPI Configuration 2"
bitfld.long 0x8 14. "TXEMPTY,Tx-FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x8 13. "XFRDONE,SPI Transfer Completion Interrupt Enable" "0,1"
newline
bitfld.long 0x8 12. "TXDONE,SPI Transmit Done Interrupt Enable" "0,1"
bitfld.long 0x8 11. "RDY,Ready Signal Edge Interrupt Enable" "0,1"
newline
bitfld.long 0x8 10. "RXOVR,Rx-overflow Interrupt Enable" "0,1"
bitfld.long 0x8 9. "TXUNDR,Tx-underflow Interrupt Enable" "0,1"
newline
bitfld.long 0x8 8. "CS,Enable Interrupt on Every CS Edge in Slave CON Mode" "0,1"
bitfld.long 0x8 0.--2. "IRQMODE,SPI IRQ Mode Bits" "0: Interrupt Occurs After 1 Byte is Transfered or..,1: Interrupt Occurs After 2 Byte is Transfered or..,2: Interrupt Occurs After 3 Byte is Transfered or..,3: Interrupt Occurs After 4 Byte is Transfered or..,4: Interrupt Occurs After 5 Byte is Transfered or..,5: Interrupt Occurs After 6 Byte is Transfered or..,6: Interrupt Occurs After 7 Byte is Transfered or..,7: Interrupt Occurs After 8 Byte is Transfered or.."
line.long 0xC "CNT,Transfer Byte Count"
bitfld.long 0xC 15. "FRAMECONT,Continue Frame" "0,1"
hexmask.long.word 0xC 0.--13. 1. "VALUES,Transfer Byte Count"
line.long 0x10 "DMA,SPI DMA Enable"
bitfld.long 0x10 2. "RXEN,Enable Receive DMA Request" "0,1"
bitfld.long 0x10 1. "TXEN,Enable Transmit DMA Request" "0,1"
newline
bitfld.long 0x10 0. "EN,Enable DMA for Data Transfer" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "FIFOSTAT,FIFO Status"
hexmask.long.byte 0x0 8.--11. 1. "RX,SPI Rx FIFO Status"
hexmask.long.byte 0x0 0.--3. 1. "TX,SPI Tx FIFO Status"
group.long 0x24++0xB
line.long 0x0 "RDCTL,Read Control"
bitfld.long 0x0 8. "THREEPIN,Three Pin SPI Mode" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "TXBYTES,Transmit Byte Count Minus 1 for Read Command"
newline
bitfld.long 0x0 1. "OVERLAP,Tx/Rx Overlap Mode" "0,1"
bitfld.long 0x0 0. "CMDEN,Read Command Enable" "0,1"
line.long 0x4 "FLOWCTL,Flow Control"
hexmask.long.word 0x4 6.--15. 1. "RDBURSTSZ,Read Data Burst Size Minus 1"
bitfld.long 0x4 4. "RDYPOL,Polarity of RDY/MISO Line" "0: Polarity is Active HIGH. SPI Master Waits Until..,1: Polarity is Active LOW. SPI Master Waits Until.."
newline
bitfld.long 0x4 0.--1. "MODE,Flow Control Mode" "0: Flow Control is Disabled.,1: Flow Control is Based on Timer (WAIT_TMR).,2: Flow Control is Based on RDY Signal.,3: Flow Control is Based on MISO Pin."
line.long 0x8 "WAITTMR,Wait Timer for Flow Control"
hexmask.long.word 0x8 0.--15. 1. "TRIMS,Wait Timer for Flow-control"
group.long 0x34++0x3
line.long 0x0 "CSOVERRIDE,Chip-Select Override"
bitfld.long 0x0 0.--1. "CTL,CS Override Control" "0: CS is Not Forced.,1: CS is Forced to Drive 1'b1.,2: CS is Forced to Drive 1'b0.,?"
tree.end
tree "SPI1"
base ad:0x40058000
group.long 0x0++0x3
line.long 0x0 "STAT,Status"
bitfld.long 0x0 15. "RDY,Detected an Edge on Ready Indicator for Flow-control" "0,1"
bitfld.long 0x0 14. "CSFALL,Detected a Falling Edge on CS in Slave CON Mode" "0,1"
newline
bitfld.long 0x0 13. "CSRISE,Detected a Rising Edge on CS in Slave CON Mode" "0,1"
bitfld.long 0x0 12. "CSERR,Detected a CS Error Condition in Slave Mode" "0,1"
newline
rbitfld.long 0x0 11. "CS,CS Status" "0,1"
bitfld.long 0x0 7. "RXOVR,SPI Rx FIFO Overflow" "0,1"
newline
bitfld.long 0x0 6. "RXIRQ,SPI Rx IRQ" "0,1"
bitfld.long 0x0 5. "TXIRQ,SPI Tx IRQ" "0,1"
newline
bitfld.long 0x0 4. "TXUNDR,SPI Tx FIFO Underflow" "0,1"
bitfld.long 0x0 3. "TXDONE,SPI Tx Done in Read Command Mode" "0,1"
newline
bitfld.long 0x0 2. "TXEMPTY,SPI Tx FIFO Empty Interrupt" "0,1"
bitfld.long 0x0 1. "XFRDONE,SPI Transfer Completion" "0,1"
newline
rbitfld.long 0x0 0. "IRQ,SPI Interrupt Status" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "RX,Receive"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Receive Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Receive Buffer"
wgroup.long 0x8++0x3
line.long 0x0 "TX,Transmit"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Transmit Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Transmit Buffer"
group.long 0xC++0x13
line.long 0x0 "DIV,SPI Baud Rate Selection"
bitfld.long 0x0 8. "SFR,Slave Free Run Mode" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "DIV,SPI Clock Divider"
line.long 0x4 "CTL,SPI Configuration 1"
bitfld.long 0x4 14. "CSRST,Reset Mode for CS Error Bit" "0,1"
bitfld.long 0x4 13. "TFLUSH,SPI Tx FIFO Flush Enable" "0,1"
newline
bitfld.long 0x4 12. "RFLUSH,SPI Rx FIFO Flush Enable" "0,1"
bitfld.long 0x4 11. "CON,Continuous Transfer Enable" "0,1"
newline
bitfld.long 0x4 10. "LOOPBACK,Loopback Enable" "0,1"
bitfld.long 0x4 9. "OEN,Slave MISO Output Enable" "0,1"
newline
bitfld.long 0x4 8. "RXOF,RX Overflow Overwrite Enable" "0,1"
bitfld.long 0x4 7. "ZEN,Transmit Zeros Enable" "0,1"
newline
bitfld.long 0x4 6. "TIM,SPI Transfer and Interrupt Mode" "0,1"
bitfld.long 0x4 5. "LSB,LSB First Transfer Enable" "0,1"
newline
bitfld.long 0x4 4. "WOM,SPI Wired or Mode" "0,1"
bitfld.long 0x4 3. "CPOL,Serial Clock Polarity" "0,1"
newline
bitfld.long 0x4 2. "CPHA,Serial Clock Phase Mode" "0,1"
bitfld.long 0x4 1. "MASEN,Master Mode Enable" "0,1"
newline
bitfld.long 0x4 0. "SPIEN,SPI Enable" "0,1"
line.long 0x8 "IEN,SPI Configuration 2"
bitfld.long 0x8 14. "TXEMPTY,Tx-FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x8 13. "XFRDONE,SPI Transfer Completion Interrupt Enable" "0,1"
newline
bitfld.long 0x8 12. "TXDONE,SPI Transmit Done Interrupt Enable" "0,1"
bitfld.long 0x8 11. "RDY,Ready Signal Edge Interrupt Enable" "0,1"
newline
bitfld.long 0x8 10. "RXOVR,Rx-overflow Interrupt Enable" "0,1"
bitfld.long 0x8 9. "TXUNDR,Tx-underflow Interrupt Enable" "0,1"
newline
bitfld.long 0x8 8. "CS,Enable Interrupt on Every CS Edge in Slave CON Mode" "0,1"
bitfld.long 0x8 0.--2. "IRQMODE,SPI IRQ Mode Bits" "0: Interrupt Occurs After 1 Byte is Transfered or..,1: Interrupt Occurs After 2 Byte is Transfered or..,2: Interrupt Occurs After 3 Byte is Transfered or..,3: Interrupt Occurs After 4 Byte is Transfered or..,4: Interrupt Occurs After 5 Byte is Transfered or..,5: Interrupt Occurs After 6 Byte is Transfered or..,6: Interrupt Occurs After 7 Byte is Transfered or..,7: Interrupt Occurs After 8 Byte is Transfered or.."
line.long 0xC "CNT,Transfer Byte Count"
bitfld.long 0xC 15. "FRAMECONT,Continue Frame" "0,1"
hexmask.long.word 0xC 0.--13. 1. "VALUES,Transfer Byte Count"
line.long 0x10 "DMA,SPI DMA Enable"
bitfld.long 0x10 2. "RXEN,Enable Receive DMA Request" "0,1"
bitfld.long 0x10 1. "TXEN,Enable Transmit DMA Request" "0,1"
newline
bitfld.long 0x10 0. "EN,Enable DMA for Data Transfer" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "FIFOSTAT,FIFO Status"
hexmask.long.byte 0x0 8.--11. 1. "RX,SPI Rx FIFO Status"
hexmask.long.byte 0x0 0.--3. 1. "TX,SPI Tx FIFO Status"
group.long 0x24++0xB
line.long 0x0 "RDCTL,Read Control"
bitfld.long 0x0 8. "THREEPIN,Three Pin SPI Mode" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "TXBYTES,Transmit Byte Count Minus 1 for Read Command"
newline
bitfld.long 0x0 1. "OVERLAP,Tx/Rx Overlap Mode" "0,1"
bitfld.long 0x0 0. "CMDEN,Read Command Enable" "0,1"
line.long 0x4 "FLOWCTL,Flow Control"
hexmask.long.word 0x4 6.--15. 1. "RDBURSTSZ,Read Data Burst Size Minus 1"
bitfld.long 0x4 4. "RDYPOL,Polarity of RDY/MISO Line" "0: Polarity is Active HIGH. SPI Master Waits Until..,1: Polarity is Active LOW. SPI Master Waits Until.."
newline
bitfld.long 0x4 0.--1. "MODE,Flow Control Mode" "0: Flow Control is Disabled.,1: Flow Control is Based on Timer (WAIT_TMR).,2: Flow Control is Based on RDY Signal.,3: Flow Control is Based on MISO Pin."
line.long 0x8 "WAITTMR,Wait Timer for Flow Control"
hexmask.long.word 0x8 0.--15. 1. "TRIMS,Wait Timer for Flow-control"
group.long 0x34++0x3
line.long 0x0 "CSOVERRIDE,Chip-Select Override"
bitfld.long 0x0 0.--1. "CTL,CS Override Control" "0: CS is Not Forced.,1: CS is Forced to Drive 1'b1.,2: CS is Forced to Drive 1'b0.,?"
tree.end
tree "SPI2"
base ad:0x4005C000
group.long 0x0++0x3
line.long 0x0 "STAT,Status"
bitfld.long 0x0 15. "RDY,Detected an Edge on Ready Indicator for Flow-control" "0,1"
bitfld.long 0x0 14. "CSFALL,Detected a Falling Edge on CS in Slave CON Mode" "0,1"
newline
bitfld.long 0x0 13. "CSRISE,Detected a Rising Edge on CS in Slave CON Mode" "0,1"
bitfld.long 0x0 12. "CSERR,Detected a CS Error Condition in Slave Mode" "0,1"
newline
rbitfld.long 0x0 11. "CS,CS Status" "0,1"
bitfld.long 0x0 7. "RXOVR,SPI Rx FIFO Overflow" "0,1"
newline
bitfld.long 0x0 6. "RXIRQ,SPI Rx IRQ" "0,1"
bitfld.long 0x0 5. "TXIRQ,SPI Tx IRQ" "0,1"
newline
bitfld.long 0x0 4. "TXUNDR,SPI Tx FIFO Underflow" "0,1"
bitfld.long 0x0 3. "TXDONE,SPI Tx Done in Read Command Mode" "0,1"
newline
bitfld.long 0x0 2. "TXEMPTY,SPI Tx FIFO Empty Interrupt" "0,1"
bitfld.long 0x0 1. "XFRDONE,SPI Transfer Completion" "0,1"
newline
rbitfld.long 0x0 0. "IRQ,SPI Interrupt Status" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "RX,Receive"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Receive Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Receive Buffer"
wgroup.long 0x8++0x3
line.long 0x0 "TX,Transmit"
hexmask.long.byte 0x0 8.--15. 1. "BYTE2,8-bit Transmit Buffer Used Only in DMA Modes"
hexmask.long.byte 0x0 0.--7. 1. "BYTE1,8-bit Transmit Buffer"
group.long 0xC++0x13
line.long 0x0 "DIV,SPI Baud Rate Selection"
bitfld.long 0x0 8. "SFR,Slave Free Run Mode" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "DIV,SPI Clock Divider"
line.long 0x4 "CTL,SPI Configuration 1"
bitfld.long 0x4 14. "CSRST,Reset Mode for CS Error Bit" "0,1"
bitfld.long 0x4 13. "TFLUSH,SPI Tx FIFO Flush Enable" "0,1"
newline
bitfld.long 0x4 12. "RFLUSH,SPI Rx FIFO Flush Enable" "0,1"
bitfld.long 0x4 11. "CON,Continuous Transfer Enable" "0,1"
newline
bitfld.long 0x4 10. "LOOPBACK,Loopback Enable" "0,1"
bitfld.long 0x4 9. "OEN,Slave MISO Output Enable" "0,1"
newline
bitfld.long 0x4 8. "RXOF,RX Overflow Overwrite Enable" "0,1"
bitfld.long 0x4 7. "ZEN,Transmit Zeros Enable" "0,1"
newline
bitfld.long 0x4 6. "TIM,SPI Transfer and Interrupt Mode" "0,1"
bitfld.long 0x4 5. "LSB,LSB First Transfer Enable" "0,1"
newline
bitfld.long 0x4 4. "WOM,SPI Wired or Mode" "0,1"
bitfld.long 0x4 3. "CPOL,Serial Clock Polarity" "0,1"
newline
bitfld.long 0x4 2. "CPHA,Serial Clock Phase Mode" "0,1"
bitfld.long 0x4 1. "MASEN,Master Mode Enable" "0,1"
newline
bitfld.long 0x4 0. "SPIEN,SPI Enable" "0,1"
line.long 0x8 "IEN,SPI Configuration 2"
bitfld.long 0x8 14. "TXEMPTY,Tx-FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x8 13. "XFRDONE,SPI Transfer Completion Interrupt Enable" "0,1"
newline
bitfld.long 0x8 12. "TXDONE,SPI Transmit Done Interrupt Enable" "0,1"
bitfld.long 0x8 11. "RDY,Ready Signal Edge Interrupt Enable" "0,1"
newline
bitfld.long 0x8 10. "RXOVR,Rx-overflow Interrupt Enable" "0,1"
bitfld.long 0x8 9. "TXUNDR,Tx-underflow Interrupt Enable" "0,1"
newline
bitfld.long 0x8 8. "CS,Enable Interrupt on Every CS Edge in Slave CON Mode" "0,1"
bitfld.long 0x8 0.--2. "IRQMODE,SPI IRQ Mode Bits" "0: Interrupt Occurs After 1 Byte is Transfered or..,1: Interrupt Occurs After 2 Byte is Transfered or..,2: Interrupt Occurs After 3 Byte is Transfered or..,3: Interrupt Occurs After 4 Byte is Transfered or..,4: Interrupt Occurs After 5 Byte is Transfered or..,5: Interrupt Occurs After 6 Byte is Transfered or..,6: Interrupt Occurs After 7 Byte is Transfered or..,7: Interrupt Occurs After 8 Byte is Transfered or.."
line.long 0xC "CNT,Transfer Byte Count"
bitfld.long 0xC 15. "FRAMECONT,Continue Frame" "0,1"
hexmask.long.word 0xC 0.--13. 1. "VALUES,Transfer Byte Count"
line.long 0x10 "DMA,SPI DMA Enable"
bitfld.long 0x10 2. "RXEN,Enable Receive DMA Request" "0,1"
bitfld.long 0x10 1. "TXEN,Enable Transmit DMA Request" "0,1"
newline
bitfld.long 0x10 0. "EN,Enable DMA for Data Transfer" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "FIFOSTAT,FIFO Status"
hexmask.long.byte 0x0 8.--11. 1. "RX,SPI Rx FIFO Status"
hexmask.long.byte 0x0 0.--3. 1. "TX,SPI Tx FIFO Status"
group.long 0x24++0xB
line.long 0x0 "RDCTL,Read Control"
bitfld.long 0x0 8. "THREEPIN,Three Pin SPI Mode" "0,1"
hexmask.long.byte 0x0 2.--5. 1. "TXBYTES,Transmit Byte Count Minus 1 for Read Command"
newline
bitfld.long 0x0 1. "OVERLAP,Tx/Rx Overlap Mode" "0,1"
bitfld.long 0x0 0. "CMDEN,Read Command Enable" "0,1"
line.long 0x4 "FLOWCTL,Flow Control"
hexmask.long.word 0x4 6.--15. 1. "RDBURSTSZ,Read Data Burst Size Minus 1"
bitfld.long 0x4 4. "RDYPOL,Polarity of RDY/MISO Line" "0: Polarity is Active HIGH. SPI Master Waits Until..,1: Polarity is Active LOW. SPI Master Waits Until.."
newline
bitfld.long 0x4 0.--1. "MODE,Flow Control Mode" "0: Flow Control is Disabled.,1: Flow Control is Based on Timer (WAIT_TMR).,2: Flow Control is Based on RDY Signal.,3: Flow Control is Based on MISO Pin."
line.long 0x8 "WAITTMR,Wait Timer for Flow Control"
hexmask.long.word 0x8 0.--15. 1. "TRIMS,Wait Timer for Flow-control"
group.long 0x34++0x3
line.long 0x0 "CSOVERRIDE,Chip-Select Override"
bitfld.long 0x0 0.--1. "CTL,CS Override Control" "0: CS is Not Forced.,1: CS is Forced to Drive 1'b1.,2: CS is Forced to Drive 1'b0.,?"
tree.end
tree.end
tree "SRAM (Static Random Access Memory)"
base ad:0x40065000
group.long 0x0++0x3
line.long 0x0 "SRAMCON,SRAM Control Register"
bitfld.long 0x0 1. "CSEL,Use Cache as a Part of SRAM0" "0: Cache not as SRAM,1: Cache as SRAM"
bitfld.long 0x0 0. "REMAP,Using SRAM0 as Instruction SRAM" "0: Using as Code SRAM,1: Using as System SRAM"
group.long 0xC++0x3
line.long 0x0 "SRAMECCCON,SRAM ECC Control Register"
bitfld.long 0x0 7.--8. "RECERRTYPE,ECC Error Address and Data Record Type" "0: Return Current Error Address and Data Information,1: Return Stored Error Address and Data Information,2: Return Stored Error Address and Data Information,3: Return Stored Error Address and Data Information"
bitfld.long 0x0 5.--6. "INTERRTYPE,ECC Interrupt Error Response Type" "0: No Error Report,1: 2 Bits Error Report,2: 1 Bit Error Report,3: 1 or 2 Bits Error Report"
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bitfld.long 0x0 3.--4. "BUSERRTYPE,ECC AHB Bus Error Response Type" "0: No Error Report,1: 2 Bits Error Report,2: 1 Bit Error Report,3: 1 or 2 Bits Error Report"
bitfld.long 0x0 0.--2. "EN,ECC Check Enable" "0: None SRAM ECC Enable,1: SRAM0 ECC Enable,2: SRAM1 ECC Enable,3: SRAM0 and SRAM1 ECC Enable,4: SRAM2 ECC Enable,5: SRAM0 and SRAM2 ECC Enable,6: SRAM1 and SRAM2 ECC Enable,7: SRAM0 and SRAM1 and SRAM2 ECC Enable"
rgroup.long 0x10++0x27
line.long 0x0 "SRAMECCSTA,SRAM ECC Status Register"
bitfld.long 0x0 8.--10. "ERRCNT,ECC Error Counter" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 5. "S2ERR1B,SRAM2 ECC 1 Bits Error" "0,1"
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bitfld.long 0x0 4. "S2ERR2B,SRAM2 ECC 2 Bits Error" "0,1"
bitfld.long 0x0 3. "S1ERR1B,SRAM1 ECC 1 Bit Error" "0,1"
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bitfld.long 0x0 2. "S1ERR2B,SRAM1 ECC 2 Bits Error" "0,1"
bitfld.long 0x0 1. "S0ERR1B,SRAM0 ECC 1 Bit Error" "0,1"
newline
bitfld.long 0x0 0. "S0ERR2B,SRAM0 ECC 2 Bits Error" "0,1"
line.long 0x4 "SRAMECCA0,SRAM0 ECC Error Address Register"
hexmask.long 0x4 0.--31. 1. "ADDR,ECC Error Address"
line.long 0x8 "SRAMECCD0,SRAM0 ECC Error Data Register"
hexmask.long 0x8 0.--31. 1. "DATA,ECC Error Raw Data"
line.long 0xC "SRAMECCP0,SRAM0 ECC Error Parity Register"
hexmask.long.byte 0xC 0.--6. 1. "PARITY,ECC Error Raw Parity"
line.long 0x10 "SRAMECCA1,SRAM1 ECC Error Address Register"
hexmask.long 0x10 0.--31. 1. "ADDR,ECC Error Address"
line.long 0x14 "SRAMECCD1,SRAM1 ECC Error Data Register"
hexmask.long 0x14 0.--31. 1. "DATA,ECC Error Raw Data"
line.long 0x18 "SRAMECCP1,SRAM1 ECC Error Parity Register"
hexmask.long.byte 0x18 0.--6. 1. "PARITY,ECC Error Raw Parity"
line.long 0x1C "SRAMECCA2,SRAM2 ECC Error Address Register"
hexmask.long 0x1C 0.--31. 1. "ADDR,ECC Error Address"
line.long 0x20 "SRAMECCD2,SRAM2 ECC Error Data Register"
hexmask.long 0x20 0.--31. 1. "DATA,ECC Error Raw Data"
line.long 0x24 "SRAMECCP2,SRAM2 ECC Error Parity Register"
hexmask.long.byte 0x24 0.--6. 1. "PARITY,ECC Error Raw Parity"
tree.end
tree "TMPSNS (Temperature Sensor)"
base ad:0x40069600
group.long 0x0++0xB
line.long 0x0 "TMPSNSCON,Unknown"
bitfld.long 0x0 1. "ENTMPSNS,Enable Temp Sensor" "0,1"
line.long 0x4 "TMPSNSCHPCON,Unknown"
bitfld.long 0x4 0. "CHOFFTMPSNS,Chopping Disable = 1 Enable = 0" "0,1"
line.long 0x8 "VCMREFCON,Unknown"
bitfld.long 0x8 1. "PGAREFSEL,0.2V or 0.5V Selection for PGA" "0: Select 0.2V Reference,1: Select 0.5V Reference"
group.long 0x10++0x3
line.long 0x0 "VCMBUFCON,Unknown"
bitfld.long 0x0 4. "MUXSEL1,Selection 0=2.5V 1=1.25V" "0: 2,1: 1"
bitfld.long 0x0 2. "MUXSEL0,Selection 0=2.5V 1=1.25V" "0: 2,1: 1"
bitfld.long 0x0 1. "PDBUF1,Power Down Unit Gain Buffer1" "0,1"
bitfld.long 0x0 0. "PDBUF0,Power Down Unit Gain Buffer0" "0,1"
tree.end
tree "UART (UART Serial Interface)"
base ad:0x0
tree "UART0"
base ad:0x40020000
rgroup.long 0x0++0x3
line.long 0x0 "RX,Receive/transfer Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register"
group.long 0x4++0x3
line.long 0x0 "IEN,Interrupt Enable"
bitfld.long 0x0 5. "EDMAR,DMA Requests in Receive Mode" "0: DMA Requests Disabled,1: DMA Requests Enabled"
bitfld.long 0x0 4. "EDMAT,DMA Requests in Transmit Mode" "0: DMA Requests are Disabled,1: DMA Requests are Enabled"
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bitfld.long 0x0 3. "EDSSI,Modem Status Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 2. "ELSI,Rx Status Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 1. "ETBEI,Transmit Buffer Empty Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 0. "ERBFI,Receive Buffer Full Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt ID"
bitfld.long 0x0 6.--7. "FEND,FIFO Enabled" "0: FIFO Not Enabled 16450 Mode,?,?,3: FIFO Enabled 16550 Mode"
bitfld.long 0x0 1.--3. "STAT,Interrupt Status" "0: Modem Status Interrupt (Read MSR Register to..,1: Transmit Buffer Empty Interrupt (Write to Tx..,2: Receive Buffer Full Interrupt (Read Rx Register..,3: Receive Line Status Interrupt (Read LSR Register..,?,?,6: Receive FIFO Time-out Interrupt (Read Rx..,?"
newline
bitfld.long 0x0 0. "NIRQ,Interrupt Flag" "0,1"
group.long 0xC++0x7
line.long 0x0 "LCR,Line Control"
bitfld.long 0x0 6. "BRK,Set Break" "0,1"
bitfld.long 0x0 5. "SP,Stick Parity" "0: Parity Will Not Be Forced Based on Parity Select..,1: Parity Forced Based on Parity Select and Parity.."
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bitfld.long 0x0 4. "EPS,Parity Select" "0: Odd Parity Will Be Transmitted and Checked.,1: Even Parity Will Be Transmitted and Checked."
bitfld.long 0x0 3. "PEN,Parity Enable" "0: Parity Will Not Be Transmitted or Checked.,1: Parity Will Be Transmitted and Checked."
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bitfld.long 0x0 2. "STOPPED,Stop Bit" "0: Send 1 Stop Bit Regardless of the Word Length..,1: Send a Number of Stop Bits Based on the Word.."
bitfld.long 0x0 0.--1. "WLS,Word Length Select" "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits"
line.long 0x4 "MCR,Modem Control"
bitfld.long 0x4 4. "LOOPBACK,Loop Back Mode" "0: Normal Operation - Loopback Disabled,1: Loopback Enabled"
bitfld.long 0x4 3. "OUT2,Output 2" "0: Force NOUT2 to a Logic 1,1: Force NOUT2 to a Logic 0"
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bitfld.long 0x4 2. "OUT1,Output 1" "0: Force NOUT1 to a Logic 1,1: Force NOUT1 to a Logic 0"
bitfld.long 0x4 1. "RTS,Request to Send" "0: Force NRTS to a Logic 1,1: Force NRTS to a Logic 0"
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bitfld.long 0x4 0. "DTR,Data Terminal Ready" "0: Force NDTR to a Logic 1,1: Force NDTR to a Logic 0"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status"
bitfld.long 0x0 7. "FIFOERR,FIFO Error" "0,1"
bitfld.long 0x0 6. "TEMT,Transmit and Shift Register Empty Status" "0: Tx Register Has Been Written to and Contains..,1: Tx Register and the Transmit Shift Register are.."
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bitfld.long 0x0 5. "THRE,Transmit Register Empty" "0: Tx Register Has Been Written to and Contains..,1: Tx Register is Empty and It is Safe to Write New.."
bitfld.long 0x0 4. "BI,Break Indicator" "0,1"
newline
bitfld.long 0x0 3. "FE,Framing Error" "0: No Invalid Stop Bit Was Detected.,1: An Invalid Stop Bit Was Detected on a Received.."
bitfld.long 0x0 2. "PE,Parity Error" "0: No Parity Error Was Detected.,1: A Parity Error Occurred on a Received Word."
newline
bitfld.long 0x0 1. "OE,Overrun Error" "0: Receive Data Has Not Been Overwritten.,1: Receive Data Was Overwritten by New Data Before.."
bitfld.long 0x0 0. "DR,Data Ready" "0: Rx Register Does Not Contain New Receive Data.,1: Rx Register Contains Receive Data That Should Be.."
line.long 0x4 "MSR,Modem Status"
bitfld.long 0x4 7. "DCD,Data Carrier Detect" "0: NDCD is Currently Logic High.,1: NDCD is Currently Logic Low."
bitfld.long 0x4 6. "RI,Ring Indicator" "0: NRI is Currently Logic High.,1: NRI is Currently Logic Low."
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bitfld.long 0x4 5. "DSR,Data Set Ready" "0: NDSR is Currently Logic High,1: NDSR is Currently Logic Low"
bitfld.long 0x4 4. "CTS,Clear to Send" "0: NCTS is Currently Logic High,1: NCTS is Currently Logic Low"
newline
bitfld.long 0x4 3. "DDCD,Delta DCD" "0: Data Carrier Detect Bit Has Not Changed State..,1: Data Carrier Detect Bit Changed State Since MSR.."
bitfld.long 0x4 2. "TERI,Trailing Edge RI" "0: Ring Indicator Bit Has Not Changed from 0 to 1..,1: Ring Indicator Bit Changed from 0 to 1 Since MSR.."
newline
bitfld.long 0x4 1. "DDSR,Delta DSR" "0: Data Set Ready Bit Has Not Changed State Since..,1: Data Set Ready Bit Changed State Since MSR.."
bitfld.long 0x4 0. "DCTS,Delta CTS" "0: Clear to Send Bit Has Not Changed State Since..,1: Clear to Send Bit Changed State Since MSR.."
group.long 0x1C++0x17
line.long 0x0 "SCR,Scratch Buffer"
hexmask.long.byte 0x0 0.--7. 1. "SCR,Scratch"
line.long 0x4 "FCR,FIFO Control"
bitfld.long 0x4 6.--7. "RFTRIG,RX FIFO Trig Level" "0: 1 Byte to Trig RX Interrupt,1: 4 Byte to Trig RX Interrupt,2: 8 Byte to Trig RX Interrupt,3: 14 Byte to Trig RX Interrupt"
bitfld.long 0x4 3. "FDMAMD,FIFO DMA Mode" "0: In DMA Mode 0 RX DMA Request Will Be Asserted..,1: In DMA Mode 1 RX DMA Request Will Be Asserted.."
newline
bitfld.long 0x4 2. "TFCLR,Clear TX FIFO" "0,1"
bitfld.long 0x4 1. "RFCLR,Clear RX FIFO" "0,1"
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bitfld.long 0x4 0. "FIFOEN,FIFO Enable as to Work in 16550 Mode" "0,1"
line.long 0x8 "FBR,Fractional Baud Rate"
bitfld.long 0x8 15. "FBEN,Fractional Baud Rate Generator Enable" "0,1"
bitfld.long 0x8 11.--12. "DIVM,Fractional Baud Rate M Divide Bits 1 to 3" "0,1,2,3"
newline
hexmask.long.word 0x8 0.--10. 1. "DIVN,Fractional Baud Rate N Divide Bits 0 to 2047"
line.long 0xC "DIV,Baudrate Divider"
hexmask.long.word 0xC 0.--15. 1. "DIV,Baud Rate Divider"
line.long 0x10 "LCR2,Second Line Control"
bitfld.long 0x10 0.--1. "OSR,Over Sample Rate" "0: Over Sample by 4,1: Over Sample by 8,2: Over Sample by 16,3: Over Sample by 32"
line.long 0x14 "CTL,UART Control Register"
hexmask.long.byte 0x14 8.--15. 1. "REV,UART Revision ID"
bitfld.long 0x14 4. "RXINV,Invert Receiver Line" "0: Don't Invert Receiver Line (idling High),1: Invert Receiver Line (idling Low)"
newline
bitfld.long 0x14 1. "FORCECLK,Force UCLK on" "0: UCLK Automatically Gated,1: UCLK Always Working"
rgroup.long 0x34++0x7
line.long 0x0 "RFC,RX FIFO Byte Count"
hexmask.long.byte 0x0 0.--4. 1. "RFC,Current RX FIFO Data Bytes"
line.long 0x4 "TFC,TX FIFO Byte Count"
hexmask.long.byte 0x4 0.--4. 1. "TFC,Current TX FIFO Data Bytes"
group.long 0x3C++0x7
line.long 0x0 "RSC,RS485 Half-duplex Control"
bitfld.long 0x0 3. "DISTX,Hold off TX When Receiving" "0,1"
bitfld.long 0x0 2. "DISRX,Disable RX When Transmitting" "0,1"
newline
bitfld.long 0x0 1. "OENSP,SOUT_EN De-assert Before Full Stop Bit(s)" "0: SOUT_EN De-assert Same Time as Full Stop Bit(s),1: SOUT_EN De-assert Half-bit Earlier Than Full.."
bitfld.long 0x0 0. "OENP,SOUT_EN Polarity" "0: High Active,1: Low Active"
line.long 0x4 "ACR,Auto Baud Control"
hexmask.long.byte 0x4 8.--11. 1. "EEC,Ending Edge Count"
bitfld.long 0x4 4.--6. "SEC,Starting Edge Count" "0: First Edge (always the Falling Edge of START Bit),1: Second Edge,2: Third Edge,3: Fourth Edge,4: Fifth Edge,5: Sixth Edge,6: Seventh Edge,7: Eighth Edge"
newline
bitfld.long 0x4 2. "TOIEN,Enable Time-out Interrupt" "0,1"
bitfld.long 0x4 1. "DNIEN,Enable Done Interrupt" "0,1"
newline
bitfld.long 0x4 0. "ABE,Auto Baud Enable" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "ASRL,Auto Baud Status (Low)"
hexmask.long.word 0x0 4.--15. 1. "CNT,Auto Baud Counter Value"
bitfld.long 0x0 3. "NEETO,Timed Out Due to No Valid Ending Edge Found" "0,1"
newline
bitfld.long 0x0 2. "NSETO,Timed Out Due to No Valid Start Edge Found" "0,1"
bitfld.long 0x0 1. "BRKTO,Timed Out Due to Long Time Break Condition" "0,1"
newline
bitfld.long 0x0 0. "DONE,Auto Baud Done Successfully" "0,1"
line.long 0x4 "ASRH,Auto Baud Status (High)"
hexmask.long.byte 0x4 0.--7. 1. "CNT,Auto Baud Counter Value"
tree.end
tree "UART1"
base ad:0x40020400
rgroup.long 0x0++0x3
line.long 0x0 "RX,Receive/transfer Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,Receive Buffer Register"
group.long 0x4++0x3
line.long 0x0 "IEN,Interrupt Enable"
bitfld.long 0x0 5. "EDMAR,DMA Requests in Receive Mode" "0: DMA Requests Disabled,1: DMA Requests Enabled"
bitfld.long 0x0 4. "EDMAT,DMA Requests in Transmit Mode" "0: DMA Requests are Disabled,1: DMA Requests are Enabled"
newline
bitfld.long 0x0 3. "EDSSI,Modem Status Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 2. "ELSI,Rx Status Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
newline
bitfld.long 0x0 1. "ETBEI,Transmit Buffer Empty Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x0 0. "ERBFI,Receive Buffer Full Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt ID"
bitfld.long 0x0 6.--7. "FEND,FIFO Enabled" "0: FIFO Not Enabled 16450 Mode,?,?,3: FIFO Enabled 16550 Mode"
bitfld.long 0x0 1.--3. "STAT,Interrupt Status" "0: Modem Status Interrupt (Read MSR Register to..,1: Transmit Buffer Empty Interrupt (Write to Tx..,2: Receive Buffer Full Interrupt (Read Rx Register..,3: Receive Line Status Interrupt (Read LSR Register..,?,?,6: Receive FIFO Time-out Interrupt (Read Rx..,?"
newline
bitfld.long 0x0 0. "NIRQ,Interrupt Flag" "0,1"
group.long 0xC++0x7
line.long 0x0 "LCR,Line Control"
bitfld.long 0x0 6. "BRK,Set Break" "0,1"
bitfld.long 0x0 5. "SP,Stick Parity" "0: Parity Will Not Be Forced Based on Parity Select..,1: Parity Forced Based on Parity Select and Parity.."
newline
bitfld.long 0x0 4. "EPS,Parity Select" "0: Odd Parity Will Be Transmitted and Checked.,1: Even Parity Will Be Transmitted and Checked."
bitfld.long 0x0 3. "PEN,Parity Enable" "0: Parity Will Not Be Transmitted or Checked.,1: Parity Will Be Transmitted and Checked."
newline
bitfld.long 0x0 2. "STOPPED,Stop Bit" "0: Send 1 Stop Bit Regardless of the Word Length..,1: Send a Number of Stop Bits Based on the Word.."
bitfld.long 0x0 0.--1. "WLS,Word Length Select" "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits"
line.long 0x4 "MCR,Modem Control"
bitfld.long 0x4 4. "LOOPBACK,Loop Back Mode" "0: Normal Operation - Loopback Disabled,1: Loopback Enabled"
bitfld.long 0x4 3. "OUT2,Output 2" "0: Force NOUT2 to a Logic 1,1: Force NOUT2 to a Logic 0"
newline
bitfld.long 0x4 2. "OUT1,Output 1" "0: Force NOUT1 to a Logic 1,1: Force NOUT1 to a Logic 0"
bitfld.long 0x4 1. "RTS,Request to Send" "0: Force NRTS to a Logic 1,1: Force NRTS to a Logic 0"
newline
bitfld.long 0x4 0. "DTR,Data Terminal Ready" "0: Force NDTR to a Logic 1,1: Force NDTR to a Logic 0"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status"
bitfld.long 0x0 7. "FIFOERR,FIFO Error" "0,1"
bitfld.long 0x0 6. "TEMT,Transmit and Shift Register Empty Status" "0: Tx Register Has Been Written to and Contains..,1: Tx Register and the Transmit Shift Register are.."
newline
bitfld.long 0x0 5. "THRE,Transmit Register Empty" "0: Tx Register Has Been Written to and Contains..,1: Tx Register is Empty and It is Safe to Write New.."
bitfld.long 0x0 4. "BI,Break Indicator" "0,1"
newline
bitfld.long 0x0 3. "FE,Framing Error" "0: No Invalid Stop Bit Was Detected.,1: An Invalid Stop Bit Was Detected on a Received.."
bitfld.long 0x0 2. "PE,Parity Error" "0: No Parity Error Was Detected.,1: A Parity Error Occurred on a Received Word."
newline
bitfld.long 0x0 1. "OE,Overrun Error" "0: Receive Data Has Not Been Overwritten.,1: Receive Data Was Overwritten by New Data Before.."
bitfld.long 0x0 0. "DR,Data Ready" "0: Rx Register Does Not Contain New Receive Data.,1: Rx Register Contains Receive Data That Should Be.."
line.long 0x4 "MSR,Modem Status"
bitfld.long 0x4 7. "DCD,Data Carrier Detect" "0: NDCD is Currently Logic High.,1: NDCD is Currently Logic Low."
bitfld.long 0x4 6. "RI,Ring Indicator" "0: NRI is Currently Logic High.,1: NRI is Currently Logic Low."
newline
bitfld.long 0x4 5. "DSR,Data Set Ready" "0: NDSR is Currently Logic High,1: NDSR is Currently Logic Low"
bitfld.long 0x4 4. "CTS,Clear to Send" "0: NCTS is Currently Logic High,1: NCTS is Currently Logic Low"
newline
bitfld.long 0x4 3. "DDCD,Delta DCD" "0: Data Carrier Detect Bit Has Not Changed State..,1: Data Carrier Detect Bit Changed State Since MSR.."
bitfld.long 0x4 2. "TERI,Trailing Edge RI" "0: Ring Indicator Bit Has Not Changed from 0 to 1..,1: Ring Indicator Bit Changed from 0 to 1 Since MSR.."
newline
bitfld.long 0x4 1. "DDSR,Delta DSR" "0: Data Set Ready Bit Has Not Changed State Since..,1: Data Set Ready Bit Changed State Since MSR.."
bitfld.long 0x4 0. "DCTS,Delta CTS" "0: Clear to Send Bit Has Not Changed State Since..,1: Clear to Send Bit Changed State Since MSR.."
group.long 0x1C++0x17
line.long 0x0 "SCR,Scratch Buffer"
hexmask.long.byte 0x0 0.--7. 1. "SCR,Scratch"
line.long 0x4 "FCR,FIFO Control"
bitfld.long 0x4 6.--7. "RFTRIG,RX FIFO Trig Level" "0: 1 Byte to Trig RX Interrupt,1: 4 Byte to Trig RX Interrupt,2: 8 Byte to Trig RX Interrupt,3: 14 Byte to Trig RX Interrupt"
bitfld.long 0x4 3. "FDMAMD,FIFO DMA Mode" "0: In DMA Mode 0 RX DMA Request Will Be Asserted..,1: In DMA Mode 1 RX DMA Request Will Be Asserted.."
newline
bitfld.long 0x4 2. "TFCLR,Clear TX FIFO" "0,1"
bitfld.long 0x4 1. "RFCLR,Clear RX FIFO" "0,1"
newline
bitfld.long 0x4 0. "FIFOEN,FIFO Enable as to Work in 16550 Mode" "0,1"
line.long 0x8 "FBR,Fractional Baud Rate"
bitfld.long 0x8 15. "FBEN,Fractional Baud Rate Generator Enable" "0,1"
bitfld.long 0x8 11.--12. "DIVM,Fractional Baud Rate M Divide Bits 1 to 3" "0,1,2,3"
newline
hexmask.long.word 0x8 0.--10. 1. "DIVN,Fractional Baud Rate N Divide Bits 0 to 2047"
line.long 0xC "DIV,Baudrate Divider"
hexmask.long.word 0xC 0.--15. 1. "DIV,Baud Rate Divider"
line.long 0x10 "LCR2,Second Line Control"
bitfld.long 0x10 0.--1. "OSR,Over Sample Rate" "0: Over Sample by 4,1: Over Sample by 8,2: Over Sample by 16,3: Over Sample by 32"
line.long 0x14 "CTL,UART Control Register"
hexmask.long.byte 0x14 8.--15. 1. "REV,UART Revision ID"
bitfld.long 0x14 4. "RXINV,Invert Receiver Line" "0: Don't Invert Receiver Line (idling High),1: Invert Receiver Line (idling Low)"
newline
bitfld.long 0x14 1. "FORCECLK,Force UCLK on" "0: UCLK Automatically Gated,1: UCLK Always Working"
rgroup.long 0x34++0x7
line.long 0x0 "RFC,RX FIFO Byte Count"
hexmask.long.byte 0x0 0.--4. 1. "RFC,Current RX FIFO Data Bytes"
line.long 0x4 "TFC,TX FIFO Byte Count"
hexmask.long.byte 0x4 0.--4. 1. "TFC,Current TX FIFO Data Bytes"
group.long 0x3C++0x7
line.long 0x0 "RSC,RS485 Half-duplex Control"
bitfld.long 0x0 3. "DISTX,Hold off TX When Receiving" "0,1"
bitfld.long 0x0 2. "DISRX,Disable RX When Transmitting" "0,1"
newline
bitfld.long 0x0 1. "OENSP,SOUT_EN De-assert Before Full Stop Bit(s)" "0: SOUT_EN De-assert Same Time as Full Stop Bit(s),1: SOUT_EN De-assert Half-bit Earlier Than Full.."
bitfld.long 0x0 0. "OENP,SOUT_EN Polarity" "0: High Active,1: Low Active"
line.long 0x4 "ACR,Auto Baud Control"
hexmask.long.byte 0x4 8.--11. 1. "EEC,Ending Edge Count"
bitfld.long 0x4 4.--6. "SEC,Starting Edge Count" "0: First Edge (always the Falling Edge of START Bit),1: Second Edge,2: Third Edge,3: Fourth Edge,4: Fifth Edge,5: Sixth Edge,6: Seventh Edge,7: Eighth Edge"
newline
bitfld.long 0x4 2. "TOIEN,Enable Time-out Interrupt" "0,1"
bitfld.long 0x4 1. "DNIEN,Enable Done Interrupt" "0,1"
newline
bitfld.long 0x4 0. "ABE,Auto Baud Enable" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "ASRL,Auto Baud Status (Low)"
hexmask.long.word 0x0 4.--15. 1. "CNT,Auto Baud Counter Value"
bitfld.long 0x0 3. "NEETO,Timed Out Due to No Valid Ending Edge Found" "0,1"
newline
bitfld.long 0x0 2. "NSETO,Timed Out Due to No Valid Start Edge Found" "0,1"
bitfld.long 0x0 1. "BRKTO,Timed Out Due to Long Time Break Condition" "0,1"
newline
bitfld.long 0x0 0. "DONE,Auto Baud Done Successfully" "0,1"
line.long 0x4 "ASRH,Auto Baud Status (High)"
hexmask.long.byte 0x4 0.--7. 1. "CNT,Auto Baud Counter Value"
tree.end
tree.end
tree "VDAC (Digital-to-Analog Converter)"
base ad:0x40069800
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "DACCON[$1],DAC Control Register"
bitfld.long 0x0 9. "DRV,Drive Ability Boost Enable Can Drive 10mA Load." "0: Normal Work Mode,1: Drive Ability Boost Mode"
bitfld.long 0x0 8. "PD,DAC Top Power Down" "0: DAC Top Enable,1: DAC TOP Power Down"
bitfld.long 0x0 5. "FSLVL,Select Output Full Scale" "0: Full Scale is 2.5V,1: Full Scale is 3.3V"
bitfld.long 0x0 4. "EN,DAC Input Data Clear Won't Be Controlled by Sync Mode." "0: DAC DATA Clear,1: DAC DATA Normal Input"
repeat.end
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "DACDAT[$1],DAC Data Register"
hexmask.long.word 0x0 12.--27. 1. "DATAIN,DAC Input Data"
repeat.end
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40004000
group.long 0x0++0x3
line.long 0x0 "LD,Watchdog Timer Load Value"
hexmask.long.word 0x0 0.--15. 1. "LOAD,WDT Load Value"
rgroup.long 0x4++0x3
line.long 0x0 "VALS,Current Count Value"
hexmask.long.word 0x0 0.--15. 1. "CCOUNT,Current WDT Count Value."
group.long 0x8++0x3
line.long 0x0 "CON,Watchdog Timer Control Register"
bitfld.long 0x0 10. "WDTIRQEN,WDT Interrupt Enable" "0,1"
bitfld.long 0x0 9. "MINLOADEN,Timer Window Control" "0,1"
newline
bitfld.long 0x0 8. "CLKDIV2,Clock Source" "0,1"
bitfld.long 0x0 6. "MDE,Timer Mode Select" "0: Free-running Mode,1: Periodic Mode (default)"
newline
bitfld.long 0x0 5. "EN,Timer Enable" "0,1"
bitfld.long 0x0 2.--3. "PRE,Prescaler." "0: Source Clock/1,1: Source Clock/16.,2: Source Clock/256 (default).,3: Source Clock/4096"
newline
bitfld.long 0x0 1. "IRQ,WDT Interrupt Enable" "0: Watchdog Timer Timeout Creates a Reset.,1: Watchdog Timer Timeout Creates an Interrupt.."
bitfld.long 0x0 0. "PDSTOP,Power Down Stop Enable" "0: Continue Counting When in Hibernate,1: Stop Counter When in Hibernate."
wgroup.long 0xC++0x3
line.long 0x0 "CLRI,Refresh Watchdog Register"
hexmask.long.word 0x0 0.--15. 1. "CLRWDG,Refresh Register"
rgroup.long 0x18++0x3
line.long 0x0 "STA,Timer Status"
bitfld.long 0x0 6. "TMINLD,WDTMINLD Write Status" "0,1"
bitfld.long 0x0 5. "OTPWRDONE,Reset Type Status" "0,1"
newline
bitfld.long 0x0 4. "LOCKS,Lock Status" "0: Timer Operation Not Locked,1: Timer Enabled and Locked"
bitfld.long 0x0 3. "CON,WDTCON Write Status" "0,1"
newline
bitfld.long 0x0 2. "TLD,WDTVAL Write Status" "0,1"
bitfld.long 0x0 1. "CLRI,WDTCLRI Write Status" "0,1"
newline
bitfld.long 0x0 0. "IRQ,WDT Interrupt" "0: Watchdog Timer Interrupt Not Pending,1: Watchdog Timer Interrupt Pending"
group.long 0x1C++0x3
line.long 0x0 "MINLD,Minimum Load Value"
hexmask.long.word 0x0 0.--15. 1. "MINLOAD,WDT Min Load Value"
tree.end
tree "WUT (Wake-up Timer)"
base ad:0x40003000
rgroup.long 0x0++0x7
line.long 0x0 "T4VAL0,Current Count Value - LS 16 Bits"
hexmask.long.word 0x0 0.--15. 1. "T4VALL,Current Count Low"
line.long 0x4 "T4VAL1,Current Count Value - MS 16 Bits"
hexmask.long.word 0x4 0.--15. 1. "T4VALH,Current Count High"
group.long 0x8++0x23
line.long 0x0 "T4CON,Control Register"
bitfld.long 0x0 11. "STOP_WUFA,Disables Updating Field a Register T4WUFA" "0,1"
bitfld.long 0x0 9.--10. "CLK,Clock Select" "0: PCLK: PCLK (default),1: LFOSC: 32 KHz Internal Oscillator,2: LFOSC: 32kHz Internal Oscillator,3: ECLKIN: External Clock from P1.0"
newline
bitfld.long 0x0 8. "WUEN,Wakeup Enable" "0: DIS: Cleared by User to Disable the Wake up..,1: EN: Set by User to Enable the Wake up Timer Even.."
bitfld.long 0x0 7. "ENABLE,Timer Enable" "0: DIS: Disable the Timer (default).,1: EN: Enable the Timer."
newline
bitfld.long 0x0 6. "TMODE,Timer Mode" "0: PERIODIC: Cleared by User to Operate in Periodic..,1: FREERUN: Set by User to Operate in Free Running.."
bitfld.long 0x0 3. "FREEZE,Freeze Enable" "0: DIS: Cleared by User to Disable This Feature..,1: EN: Set by User to Enable the Freeze of the High.."
newline
bitfld.long 0x0 0.--1. "PRE,Prescaler" "0: PREDIV1: Source Clock/1 (default). If the..,1: PREDIV16: Source Clock/16,2: PREDIV256: Source Clock/256,3: PREDIV32768: Source Clock/32 768"
line.long 0x4 "T4INC,12-bit Interval for Wakeup Field a"
hexmask.long.word 0x4 0.--11. 1. "INTERVAL,Interval for Wakeup Field a"
line.long 0x8 "T4WUFB0,Wakeup Field B - LS 16 Bits"
hexmask.long.word 0x8 0.--15. 1. "T4WUFBL,Wakeup Field B Low"
line.long 0xC "T4WUFB1,Wakeup Field B - MS 16 Bits"
hexmask.long.word 0xC 0.--15. 1. "T4WUFBH,Wakeup Field B High"
line.long 0x10 "T4WUFC0,Wakeup Field C - LS 16 Bits"
hexmask.long.word 0x10 0.--15. 1. "T4WUFCL,Wakeup Field C Low"
line.long 0x14 "T4WUFC1,Wakeup Field C - MS 16 Bits"
hexmask.long.word 0x14 0.--15. 1. "T4WUFCH,Wakeup Field C High"
line.long 0x18 "T4WUFD0,Wakeup Field D - LS 16 Bits"
hexmask.long.word 0x18 0.--15. 1. "T4WUFD0,Wakeup Field D Low"
line.long 0x1C "T4WUFD1,Wakeup Field D - MS 16 Bits"
hexmask.long.word 0x1C 0.--15. 1. "T4WUFDH,Wakeup Field D High"
line.long 0x20 "T4IEN,Interrupt Enable Register"
bitfld.long 0x20 4. "ROLL,Rollover Interrupt Enable" "0,1"
bitfld.long 0x20 3. "WUFD,T4WUFD Interrupt Enable" "0,1"
newline
bitfld.long 0x20 2. "WUFC,T4WUFC Interrupt Enable" "0,1"
bitfld.long 0x20 1. "WUFB,T4WUFB Interrupt Enable" "0,1"
newline
bitfld.long 0x20 0. "WUFA,T4WUFA Interrupt Enable" "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "T4STA,Status Register"
bitfld.long 0x0 8. "PDOK,Enable Bit Synchronized" "0,1"
bitfld.long 0x0 7. "FREEZE,Timer Value Freeze" "0,1"
newline
bitfld.long 0x0 6. "IRQCRY,Wakeup Status to Powerdown" "0,1"
bitfld.long 0x0 4. "ROLL,Rollover Interrupt Flag" "0,1"
newline
bitfld.long 0x0 3. "WUFD,T4WUFD Interrupt Flag" "0,1"
bitfld.long 0x0 2. "WUFC,T4WUFC Interrupt Flag" "0,1"
newline
bitfld.long 0x0 1. "WUFB,T4WUFB Interrupt Flag" "0,1"
bitfld.long 0x0 0. "WUFA,T4WUFA Interrupt Flag" "0,1"
group.long 0x30++0x3
line.long 0x0 "T4CLRI,Clear Interrupt Register"
bitfld.long 0x0 4. "ROLL,Rollover Interrupt Clear" "0,1"
bitfld.long 0x0 3. "WUFD,T4WUFD Interrupt Clear" "0,1"
newline
bitfld.long 0x0 2. "WUFC,T4WUFC Interrupt Clear" "0,1"
bitfld.long 0x0 1. "WUFB,T4WUFB Interrupt Clear" "0,1"
newline
bitfld.long 0x0 0. "WUFA,T4WUFA Interrupt Clear" "0,1"
group.long 0x3C++0x7
line.long 0x0 "T4WUFA0,Wakeup Field a - LS 16 Bits"
hexmask.long.word 0x0 0.--15. 1. "T4WUFAL,Wakeup Field a Low"
line.long 0x4 "T4WUFA1,Wakeup Field a - MS 16 Bits"
hexmask.long.word 0x4 0.--15. 1. "T4WUFAH,Wakeup Field a High"
tree.end
newline
AUTOINDENT.OFF
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