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Work/Src/Gen4_R-Car_Trace32/2_Trunk/perrw610.per
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; --------------------------------------------------------------------------------
; @Title: RW610 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2025-03-07 KRZ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: Generated (TRACE32, build: 177654.), based on:
; RW610.svd (Ver. 1.0)
; @Core: Cortex-M33F
; @Chip: RW610
; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; Copyright 2016-2021 NXP
; All rights reserved.
;
; SPDX-License-Identifier: BSD-3-Clause
; --------------------------------------------------------------------------------
; $Id: perrw610.per 19207 2025-03-11 13:52:40Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main Extension"
newline
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD21=Cortex-M33"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACOMP (Analog Comparator)"
base ad:0x40038400
group.long 0x0++0x7
line.long 0x0 "CTRL0,ACOMP0 Control Register"
bitfld.long 0x0 31. "EDGE_LEVL_SEL,ACOMP0 interrupt type select." "0: level triggered interrupt,1: edge triggered interrupt"
bitfld.long 0x0 30. "INT_ACT_HI,ACOMP0 interrupt active mode select." "0: Low level or falling edge triggered interrupt,1: High level or rising edge triggered interrupt"
newline
bitfld.long 0x0 29. "FIE,ACOMP0 enable/disable falling edge triggered edge pulse." "0: no description available,1: no description available"
bitfld.long 0x0 28. "RIE,ACOMP0 enable/disable rising edge triggered edge pulse." "0: no description available,1: no description available"
newline
bitfld.long 0x0 27. "INACT_VAL,Set output value when ACOMP0 is inactive." "0: output 0 when ACOMP0 is inactive,1: output 1 when ACOMP0 is inactive"
bitfld.long 0x0 26. "MUXEN,ACOMP0 input MUX enable bit." "0: disable input mux,1: enable input mux"
newline
hexmask.long.byte 0x0 22.--25. 1. "POS_SEL,ACOMP0 positive input select bits."
hexmask.long.byte 0x0 18.--21. 1. "NEG_SEL,ACOMP0 negative input select bits."
newline
hexmask.long.byte 0x0 12.--17. 1. "LEVEL_SEL,Scaling factor select bits for VIO reference level."
bitfld.long 0x0 10.--11. "BIAS_PROG,ACOMP0 bias current control bits or response time control bits." "0: power mode1 (slow response mode),1: power mode2 (medium response mode),2: power mode3 (fast response mode),?"
newline
bitfld.long 0x0 7.--9. "HYST_SELP,Select ACOMP0 positive hysteresis voltage level." "0: No hysteresis,1: +10 mV hysteresis,2: +20 mV hysteresis,3: +30 mV hysteresis,4: +40 mV hysteresis,5: +50 mV hysteresis,6: +60 mV hysteresis,7: +70 mV hysteresis"
bitfld.long 0x0 4.--6. "HYST_SELN,Select ACOMP0 negative hysteresis voltage level." "0: no hysteresis,1: -10 mV hysteresis,2: -20 mV hysteresis,3: -30 mV hysteresis,4: -40 mV hysteresis,5: -50 mV hysteresis,6: -60 mV hysteresis,7: -70 mV hysteresis"
newline
bitfld.long 0x0 2.--3. "WARMTIME,Set ACOMP0 Warm-Up time" "0: 1 us,1: 2 us,2: 4 us,3: 8 us"
bitfld.long 0x0 1. "GPIOINV,Enable/Disable inversion of ACOMP0 output to GPIO." "0: do not invert ACOMP0 output,1: invert ACOMP0 output"
newline
bitfld.long 0x0 0. "EN,ACOMP0 enable" "0: no description available,1: no description available"
line.long 0x4 "CTRL1,ACOMP1 Control Register"
bitfld.long 0x4 31. "EDGE_LEVL_SEL,ACOMP1 interrupt type select." "0: level triggered interrupt,1: edge triggered interrupt"
bitfld.long 0x4 30. "INT_ACT_HI,ACOMP1 interrupt active mode select." "0: Low level or falling edge triggered interrupt,1: High level or rising edge triggered interrupt"
newline
bitfld.long 0x4 29. "FIE,ACOMP1 enable/disable falling edge triggered edge pulse." "0: no description available,1: no description available"
bitfld.long 0x4 28. "RIE,ACOMP1 enable/disable rising edge triggered edge pulse." "0: no description available,1: no description available"
newline
bitfld.long 0x4 27. "INACT_VAL,Set output value when ACOMP1 is inactive." "0: output 0 when ACOMP1 is inactive,1: output 1 when ACOMP1 is inactive"
bitfld.long 0x4 26. "MUXEN,ACOMP1 input MUX enable" "0: disable input mux,1: enable input mux"
newline
hexmask.long.byte 0x4 22.--25. 1. "POS_SEL,ACOMP1 positive input select"
hexmask.long.byte 0x4 18.--21. 1. "NEG_SEL,ACOMP1 negative input select"
newline
hexmask.long.byte 0x4 12.--17. 1. "LEVEL_SEL,Scaling factor select bits for vio reference level."
bitfld.long 0x4 10.--11. "BIAS_PROG,ACOMP1 bias current control bits Or response time control bits." "0: power mode1 (Slow response mode),1: power mode2 (Medium response mode),2: power mode3 (Fast response mode),?"
newline
bitfld.long 0x4 7.--9. "HYST_SELP,Select ACOMP1 positive hysteresis voltage level." "0: No hysteresis,1: +10 mV hysteresis,2: +20 mV hysteresis,3: +30 mV hysteresis,4: +40 mV hysteresis,5: +50 mV hysteresis,6: +60 mV hysteresis,7: +70 mV hysteresis"
bitfld.long 0x4 4.--6. "HYST_SELN,Select ACOMP1 negative hysteresis voltage level." "0: No hysteresis,1: -10 mV hysteresis,2: -20 mV hysteresis,3: -30 mV hysteresis,4: -40 mV hysteresis,5: -50 mV hysteresis,6: -60 mV hysteresis,7: -70 mV hysteresis"
newline
bitfld.long 0x4 2.--3. "WARMTIME,Set ACOMP1 warm-up time." "0: 1 us,1: 2 us,2: 4 us,3: 8 us"
bitfld.long 0x4 1. "GPIOINV,Enable/disable inversion of ACOMP1 output to GPIO." "0: do not invert ACOMP1 output,1: invert ACOMP1 output"
newline
bitfld.long 0x4 0. "EN,ACOMP1 enable bit." "0: no description available,1: no description available"
rgroup.long 0x8++0x7
line.long 0x0 "STATUS0,ACOMP0 Status Register"
bitfld.long 0x0 1. "OUT,ACOMP0 comparison output value." "0,1"
bitfld.long 0x0 0. "ACT,ACOMP0 active status." "0: ACOMP0 is inactive,1: ACOMP0 is active"
line.long 0x4 "STATUS1,ACOMP1 Status Register"
bitfld.long 0x4 1. "OUT,ACOMP1 comparison output value." "0,1"
bitfld.long 0x4 0. "ACT,ACOMP1 active status." "0: ACOMP1 is inactive,1: ACOMP1 is active"
group.long 0x10++0x7
line.long 0x0 "ROUTE0,ACOMP0 Route Register"
bitfld.long 0x0 1. "PE,Enable/disable ACOMP0 output to pin." "0: no description available,1: no description available"
bitfld.long 0x0 0. "OUTSEL,Select ACOMP0 synchronous or asynchronous output to pin." "0: Synchronous output,1: Asynchronous output"
line.long 0x4 "ROUTE1,ACOMP1 Route Register"
bitfld.long 0x4 1. "PE,Enable/disable ACOMP1 output to pin" "0: no description available,1: no description available"
bitfld.long 0x4 0. "OUTSEL,Select ACOMP1 synchronous or asynchronous output to pin" "0: Synchronous output,1: Asynchronous output"
rgroup.long 0x18++0x7
line.long 0x0 "ISR0,ACOMP0 Interrupt Status Register"
bitfld.long 0x0 1. "OUTA_INT,ACOMP0 Asynchronized Output Interrupt" "0,1"
bitfld.long 0x0 0. "OUT_INT,ACOMP0 Synchronized Output Interrupt" "0,1"
line.long 0x4 "ISR1,ACOMP1 Interrupt Status Register"
bitfld.long 0x4 1. "OUTA_INT,ACOMP1 Asynchronized Output Interrupt" "0,1"
bitfld.long 0x4 0. "OUT_INT,ACOMP1 Synchronized Output Interrupt" "0,1"
group.long 0x20++0x7
line.long 0x0 "IMR0,ACOMP0 Interrupt Mask Register"
bitfld.long 0x0 1. "OUTA_INT_MASK,Mask Asynchronized Interrupt" "0,1"
bitfld.long 0x0 0. "OUT_INT_MASK,Mask Synchronized Interrupt" "0,1"
line.long 0x4 "IMR1,ACOMP1 Interrupt Mask Register"
bitfld.long 0x4 1. "OUTA_INT_MASK,Mask Asynchronized Interrupt" "0,1"
bitfld.long 0x4 0. "OUT_INT_MASK,Mask Synchronized Interrupt" "0,1"
rgroup.long 0x28++0x7
line.long 0x0 "IRSR0,ACOMP0 Interrupt Raw Status Register"
bitfld.long 0x0 1. "OUTA_INT_RAW,Raw Mask Asynchronized Interrupt" "0,1"
bitfld.long 0x0 0. "OUT_INT_RAW,Raw Mask Synchronized Interrupt" "0,1"
line.long 0x4 "IRSR1,ACOMP1 Interrupt Raw Status Register"
bitfld.long 0x4 1. "OUTA_INT_RAW,Raw Mask Asynchronized Interrupt" "0,1"
bitfld.long 0x4 0. "OUT_INT_RAW,Raw Mask Synchronized Interrupt" "0,1"
group.long 0x30++0xF
line.long 0x0 "ICR0,ACOMP0 Interrupt Clear Register"
bitfld.long 0x0 1. "OUTA_INT_CLR,ACOMP0 asyncrhonized output interrupt flag clear signal." "0,1"
bitfld.long 0x0 0. "OUT_INT_CLR,ACOMP0 syncrhonized output interrupt flag clear signal." "0,1"
line.long 0x4 "ICR1,ACOMP1 Interrupt Clear Register"
bitfld.long 0x4 1. "OUTA_INT_CLR,ACOMP1 asyncrhonized output interrupt flag clear signal." "0,1"
bitfld.long 0x4 0. "OUT_INT_CLR,ACOMP1 syncrhonized output interrupt flag clear signal." "0,1"
line.long 0x8 "RST0,ACOMP0 Soft Reset Register"
bitfld.long 0x8 0. "SOFT_RST,Soft Reset for ACOMP0 (active high)" "0: no action,1: no description available"
line.long 0xC "RST1,ACOMP1 Soft Reset Register"
bitfld.long 0xC 0. "SOFT_RST,Soft Reset for ACOMP1 (active high)" "0: no action,1: no description available"
group.long 0x48++0x3
line.long 0x0 "CLK,Clock Register"
bitfld.long 0x0 1. "SOFT_CLK_RST,soft reset for clock divider" "0: no action,1: no description available"
tree.end
tree "ADC (Analog to Digital Converter)"
base ad:0x0
tree "GAU_GPADC0"
base ad:0x40038000
group.long 0x0++0x13
line.long 0x0 "ADC_REG_CMD,ADC Command Register"
bitfld.long 0x0 2. "SOFT_CLK_RST,user reset clock" "0,1"
bitfld.long 0x0 1. "SOFT_RST,user reset the whole block" "0,1"
bitfld.long 0x0 0. "CONV_START,converaion control bit." "0,1"
line.long 0x4 "ADC_REG_GENERAL,ADC General Register"
hexmask.long.byte 0x4 8.--13. 1. "CLK_DIV_RATIO,analog 64M clock division ratio"
bitfld.long 0x4 5. "ADC_CAL_EN,calibration enable auto cleared after calibration done" "0,1"
bitfld.long 0x4 4. "CLK_ANA2M_INV,analog clock 2M inverted" "0,1"
newline
bitfld.long 0x4 3. "CLK_ANA64M_INV,analog clock 64M inverted" "0,1"
bitfld.long 0x4 2. "FORCE_CLK_ON,override the gpadc_mclk_en from outside" "0,1"
bitfld.long 0x4 1. "GLOBAL_EN,ADC enable/disable" "0,1"
newline
bitfld.long 0x4 0. "GPADC_MASTER,play as master or slave in dual mode master is the only controller of when slave start" "0,1"
line.long 0x8 "ADC_REG_CONFIG,ADC Configuration Register"
bitfld.long 0x8 20. "PWR_MODE,ADC power mode select." "0,1"
hexmask.long.byte 0x8 16.--19. 1. "SCAN_LENGTH,scan converation length actual length is scan_length+1."
bitfld.long 0x8 13.--15. "AVG_SEL,moving average length" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 12. "CAL_DATA_SEL,select calibration data source." "0,1"
bitfld.long 0x8 11. "CAL_DATA_RST,reset the self calibration data." "0,1"
bitfld.long 0x8 10. "CAL_VREF_SEL,select input reference channel for gain calibration" "0,1"
newline
bitfld.long 0x8 9. "DATA_FORMAT_SEL,set data format for the final data" "0,1"
bitfld.long 0x8 8. "CONT_CONV_EN,To enable continuous conversion" "0,1"
bitfld.long 0x8 6. "SINGLE_DUAL,work mode select" "0,1"
newline
bitfld.long 0x8 5. "DUAL_MODE,dual mode select" "0,1"
bitfld.long 0x8 4. "TRIGGER_EN,External elevel trigger enable bit support gpadc_trigger/gpadc_data_valid handshake" "0,1"
hexmask.long.byte 0x8 0.--3. 1. "TRIGGER_SEL,External trigger source select bits"
line.long 0xC "ADC_REG_INTERVAL,ADC Interval Register"
bitfld.long 0xC 5. "BYPASS_WARMUP,Bypass warmup state inside adc." "0,1"
hexmask.long.byte 0xC 0.--4. 1. "WARMUP_TIME,warmup time should be set equal to or higher than 1uS."
line.long 0x10 "ADC_REG_ANA,ADC ANA Register"
bitfld.long 0x10 17.--18. "RES_SEL,adc resolution/data rate select" "0,1,2,3"
bitfld.long 0x10 16. "BIAS_SEL,adc analog portion low power mode select. Half the biasing current for modulator when enabled." "0,1"
bitfld.long 0x10 15. "CHOP_EN,adc chopper/auto-zero(only in 12bit mode) enable" "0,1"
newline
bitfld.long 0x10 14. "INBUF_EN,gpadc input gain buffer enable bit." "0,1"
bitfld.long 0x10 13. "INBUF_CHOP_EN,Input buffer chopper enable" "0,1"
bitfld.long 0x10 11.--12. "INBUF_GAIN,adc gain control. Also select input voltage range." "0,1,2,3"
newline
bitfld.long 0x10 10. "SINGLEDIFF,Select single ended or differential input." "0,1"
bitfld.long 0x10 4.--5. "VREF_SEL,adc reference voltage select." "0,1,2,3"
bitfld.long 0x10 3. "VREF_CHOP_EN,adc voltage reference buffer chopper enable" "0,1"
newline
bitfld.long 0x10 2. "VREF_SCF_BYPASS,adc voltage reference buffer sc-filter bypass" "0,1"
bitfld.long 0x10 1. "TS_EN,temperature sensor enable only enable when channel source is temperature sensor" "0,1"
bitfld.long 0x10 0. "TSEXT_SEL,temperature sensor diode select" "0,1"
group.long 0x18++0xB
line.long 0x0 "ADC_REG_SCN1,ADC Converation Sequence 1 Register"
hexmask.long.byte 0x0 28.--31. 1. "SCAN_CH_7,amux source 7"
hexmask.long.byte 0x0 24.--27. 1. "SCAN_CH_6,amux source 6"
hexmask.long.byte 0x0 20.--23. 1. "SCAN_CH_5,amux source 5"
newline
hexmask.long.byte 0x0 16.--19. 1. "SCAN_CH_4,amux source 4"
hexmask.long.byte 0x0 12.--15. 1. "SCAN_CH_3,amux source 3"
hexmask.long.byte 0x0 8.--11. 1. "SCAN_CH_2,amux source 2"
newline
hexmask.long.byte 0x0 4.--7. 1. "SCAN_CH_1,amux source 1"
hexmask.long.byte 0x0 0.--3. 1. "SCAN_CH_0,amux source 0"
line.long 0x4 "ADC_REG_SCN2,ADC Converation Sequence 2 Register"
hexmask.long.byte 0x4 28.--31. 1. "SCAN_CH_15,amux source 15"
hexmask.long.byte 0x4 24.--27. 1. "SCAN_CH_14,amux source 14"
hexmask.long.byte 0x4 20.--23. 1. "SCAN_CH_13,amux source 13"
newline
hexmask.long.byte 0x4 16.--19. 1. "SCAN_CH_12,amux source 12"
hexmask.long.byte 0x4 12.--15. 1. "SCAN_CH_11,amux source 11"
hexmask.long.byte 0x4 8.--11. 1. "SCAN_CH_10,amux source 10"
newline
hexmask.long.byte 0x4 4.--7. 1. "SCAN_CH_9,amux source 9"
hexmask.long.byte 0x4 0.--3. 1. "SCAN_CH_8,amux source 8"
line.long 0x8 "ADC_REG_RESULT_BUF,ADC Result Buffer Register"
bitfld.long 0x8 0. "WIDTH_SEL,adc finial result fifo data packed format select must set scan_length as even when choose 32-bits" "0,1"
group.long 0x28++0x3
line.long 0x0 "ADC_REG_DMAR,ADC DMAR Register"
bitfld.long 0x0 1.--2. "FIFO_THL,fifo threshold" "0,1,2,3"
bitfld.long 0x0 0. "DMA_EN,dma enbale" "0,1"
rgroup.long 0x2C++0x7
line.long 0x0 "ADC_REG_STATUS,ADC Status Register"
hexmask.long.byte 0x0 3.--8. 1. "FIFO_DATA_COUNT,fifo data number"
bitfld.long 0x0 2. "FIFO_FULL,fifo full status" "0,1"
bitfld.long 0x0 1. "FIFO_NE,fifo not empty status" "0,1"
newline
bitfld.long 0x0 0. "ACT,adc status" "0,1"
line.long 0x4 "ADC_REG_ISR,ADC ISR Register"
bitfld.long 0x4 6. "FIFO_UNDERRUN,FIFO underrun interrupt flag" "0,1"
bitfld.long 0x4 5. "FIFO_OVERRUN,FIFO overrun interrupt flag" "0,1"
bitfld.long 0x4 4. "DATASAT_POS,ADC data positive side saturation interrupt flag" "0,1"
newline
bitfld.long 0x4 3. "DATASAT_NEG,ADC data negative side saturation interrupt flag" "0,1"
bitfld.long 0x4 2. "OFFSAT,Offset correction saturation interrupt flag" "0,1"
bitfld.long 0x4 1. "GAINSAT,Gain correction saturation interrupt flag" "0,1"
newline
bitfld.long 0x4 0. "RDY,Conversion data ready interrupt flag" "0,1"
group.long 0x34++0x3
line.long 0x0 "ADC_REG_IMR,ADC IMR Register"
bitfld.long 0x0 6. "FIFO_UNDERRUN_MASK,write 1 mask" "0,1"
bitfld.long 0x0 5. "FIFO_OVERRUN_MASK,write 1 mask" "0,1"
bitfld.long 0x0 4. "DATASAT_POS_MASK,write 1 mask" "0,1"
newline
bitfld.long 0x0 3. "DATASAT_NEG_MASK,write 1 mask" "0,1"
bitfld.long 0x0 2. "OFFSAT_MASK,write 1 mask" "0,1"
bitfld.long 0x0 1. "GAINSAT_MASK,write 1 mask" "0,1"
newline
bitfld.long 0x0 0. "RDY_MASK,write 1 mask" "0,1"
rgroup.long 0x38++0x3
line.long 0x0 "ADC_REG_IRSR,ADC IRSR Register"
bitfld.long 0x0 6. "FIFO_UNDERRUN_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 5. "FIFO_OVERRUN_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 4. "DATASAT_POS_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
newline
bitfld.long 0x0 3. "DATASAT_NEG_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 2. "OFFSAT_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 1. "GAINSAT_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
newline
bitfld.long 0x0 0. "RDY_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
group.long 0x3C++0x3
line.long 0x0 "ADC_REG_ICR,ADC ICR Register"
bitfld.long 0x0 6. "FIFO_UNDERRUN_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 5. "FIFO_OVERRUN_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 4. "DATASAT_POS_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
newline
bitfld.long 0x0 3. "DATASAT_NEG_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 2. "OFFSAT_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 1. "GAINSAT_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
newline
bitfld.long 0x0 0. "RDY_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "ADC_REG_RESULT,ADC Result Register"
hexmask.long 0x0 0.--31. 1. "DATA,ADC finial conversion result data after calibratiob and signed/unsigned process"
line.long 0x4 "ADC_REG_RAW_RESULT,ADC Raw Result Register"
hexmask.long.tbyte 0x4 0.--21. 1. "RAW_DATA,ADC Raw data in signed 22bit format"
group.long 0x4C++0x17
line.long 0x0 "ADC_REG_OFFSET_CAL,ADC Offset Calibration Register"
hexmask.long.word 0x0 16.--31. 1. "OFFSET_CAL_USR,User offset calibration data. 16-bit signed."
hexmask.long.word 0x0 0.--15. 1. "OFFSET_CAL,ADC self offset calibration value. 16-bit signed ."
line.long 0x4 "ADC_REG_GAIN_CAL,ADC Gain Calibration Register"
hexmask.long.word 0x4 16.--31. 1. "GAIN_CAL_USR,ADC user gain calibration value. 16-bit signed."
hexmask.long.word 0x4 0.--15. 1. "GAIN_CAL,ADC self gain calibration value. 16-bit signed."
line.long 0x8 "ADC_REG_TEST,ADC Test Register"
bitfld.long 0x8 1.--3. "TEST_SEL,test_sel" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 0. "TEST_EN,Analog test enable." "0,1"
line.long 0xC "ADC_REG_AUDIO,ADC Audio Register"
bitfld.long 0xC 9. "PGA_CHOP_EN,Audio PGA chopper enable." "0,1"
bitfld.long 0xC 6.--8. "PGA_CM,Audio PGA output common mode control" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 3.--5. "PGA_GAIN,Audio PGA voltage gain select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0. "EN,Audio enable." "0,1"
line.long 0x10 "ADC_REG_VOICE_DET,ADC Voice Detect Register"
bitfld.long 0x10 1.--3. "LEVEL_SEL,Voice level selection." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0. "DET_EN,Voice level detection enable select" "0,1"
line.long 0x14 "ADC_REG_RSVD,ADC Reserved Register"
hexmask.long.word 0x14 0.--15. 1. "UNUSED_RESERVED_ADC_CONTROL_BITS,unused_Reserved_ADC_control_bits"
tree.end
tree "GAU_GPADC1"
base ad:0x40038100
group.long 0x0++0x13
line.long 0x0 "ADC_REG_CMD,ADC Command Register"
bitfld.long 0x0 2. "SOFT_CLK_RST,user reset clock" "0,1"
bitfld.long 0x0 1. "SOFT_RST,user reset the whole block" "0,1"
bitfld.long 0x0 0. "CONV_START,converaion control bit." "0,1"
line.long 0x4 "ADC_REG_GENERAL,ADC General Register"
hexmask.long.byte 0x4 8.--13. 1. "CLK_DIV_RATIO,analog 64M clock division ratio"
bitfld.long 0x4 5. "ADC_CAL_EN,calibration enable auto cleared after calibration done" "0,1"
bitfld.long 0x4 4. "CLK_ANA2M_INV,analog clock 2M inverted" "0,1"
newline
bitfld.long 0x4 3. "CLK_ANA64M_INV,analog clock 64M inverted" "0,1"
bitfld.long 0x4 2. "FORCE_CLK_ON,override the gpadc_mclk_en from outside" "0,1"
bitfld.long 0x4 1. "GLOBAL_EN,ADC enable/disable" "0,1"
newline
bitfld.long 0x4 0. "GPADC_MASTER,play as master or slave in dual mode master is the only controller of when slave start" "0,1"
line.long 0x8 "ADC_REG_CONFIG,ADC Configuration Register"
bitfld.long 0x8 20. "PWR_MODE,ADC power mode select." "0,1"
hexmask.long.byte 0x8 16.--19. 1. "SCAN_LENGTH,scan converation length actual length is scan_length+1."
bitfld.long 0x8 13.--15. "AVG_SEL,moving average length" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 12. "CAL_DATA_SEL,select calibration data source." "0,1"
bitfld.long 0x8 11. "CAL_DATA_RST,reset the self calibration data." "0,1"
bitfld.long 0x8 10. "CAL_VREF_SEL,select input reference channel for gain calibration" "0,1"
newline
bitfld.long 0x8 9. "DATA_FORMAT_SEL,set data format for the final data" "0,1"
bitfld.long 0x8 8. "CONT_CONV_EN,To enable continuous conversion" "0,1"
bitfld.long 0x8 6. "SINGLE_DUAL,work mode select" "0,1"
newline
bitfld.long 0x8 5. "DUAL_MODE,dual mode select" "0,1"
bitfld.long 0x8 4. "TRIGGER_EN,External elevel trigger enable bit support gpadc_trigger/gpadc_data_valid handshake" "0,1"
hexmask.long.byte 0x8 0.--3. 1. "TRIGGER_SEL,External trigger source select bits"
line.long 0xC "ADC_REG_INTERVAL,ADC Interval Register"
bitfld.long 0xC 5. "BYPASS_WARMUP,Bypass warmup state inside adc." "0,1"
hexmask.long.byte 0xC 0.--4. 1. "WARMUP_TIME,warmup time should be set equal to or higher than 1uS."
line.long 0x10 "ADC_REG_ANA,ADC ANA Register"
bitfld.long 0x10 17.--18. "RES_SEL,adc resolution/data rate select" "0,1,2,3"
bitfld.long 0x10 16. "BIAS_SEL,adc analog portion low power mode select. Half the biasing current for modulator when enabled." "0,1"
bitfld.long 0x10 15. "CHOP_EN,adc chopper/auto-zero(only in 12bit mode) enable" "0,1"
newline
bitfld.long 0x10 14. "INBUF_EN,gpadc input gain buffer enable bit." "0,1"
bitfld.long 0x10 13. "INBUF_CHOP_EN,Input buffer chopper enable" "0,1"
bitfld.long 0x10 11.--12. "INBUF_GAIN,adc gain control. Also select input voltage range." "0,1,2,3"
newline
bitfld.long 0x10 10. "SINGLEDIFF,Select single ended or differential input." "0,1"
bitfld.long 0x10 4.--5. "VREF_SEL,adc reference voltage select." "0,1,2,3"
bitfld.long 0x10 3. "VREF_CHOP_EN,adc voltage reference buffer chopper enable" "0,1"
newline
bitfld.long 0x10 2. "VREF_SCF_BYPASS,adc voltage reference buffer sc-filter bypass" "0,1"
bitfld.long 0x10 1. "TS_EN,temperature sensor enable only enable when channel source is temperature sensor" "0,1"
bitfld.long 0x10 0. "TSEXT_SEL,temperature sensor diode select" "0,1"
group.long 0x18++0xB
line.long 0x0 "ADC_REG_SCN1,ADC Converation Sequence 1 Register"
hexmask.long.byte 0x0 28.--31. 1. "SCAN_CH_7,amux source 7"
hexmask.long.byte 0x0 24.--27. 1. "SCAN_CH_6,amux source 6"
hexmask.long.byte 0x0 20.--23. 1. "SCAN_CH_5,amux source 5"
newline
hexmask.long.byte 0x0 16.--19. 1. "SCAN_CH_4,amux source 4"
hexmask.long.byte 0x0 12.--15. 1. "SCAN_CH_3,amux source 3"
hexmask.long.byte 0x0 8.--11. 1. "SCAN_CH_2,amux source 2"
newline
hexmask.long.byte 0x0 4.--7. 1. "SCAN_CH_1,amux source 1"
hexmask.long.byte 0x0 0.--3. 1. "SCAN_CH_0,amux source 0"
line.long 0x4 "ADC_REG_SCN2,ADC Converation Sequence 2 Register"
hexmask.long.byte 0x4 28.--31. 1. "SCAN_CH_15,amux source 15"
hexmask.long.byte 0x4 24.--27. 1. "SCAN_CH_14,amux source 14"
hexmask.long.byte 0x4 20.--23. 1. "SCAN_CH_13,amux source 13"
newline
hexmask.long.byte 0x4 16.--19. 1. "SCAN_CH_12,amux source 12"
hexmask.long.byte 0x4 12.--15. 1. "SCAN_CH_11,amux source 11"
hexmask.long.byte 0x4 8.--11. 1. "SCAN_CH_10,amux source 10"
newline
hexmask.long.byte 0x4 4.--7. 1. "SCAN_CH_9,amux source 9"
hexmask.long.byte 0x4 0.--3. 1. "SCAN_CH_8,amux source 8"
line.long 0x8 "ADC_REG_RESULT_BUF,ADC Result Buffer Register"
bitfld.long 0x8 0. "WIDTH_SEL,adc finial result fifo data packed format select must set scan_length as even when choose 32-bits" "0,1"
group.long 0x28++0x3
line.long 0x0 "ADC_REG_DMAR,ADC DMAR Register"
bitfld.long 0x0 1.--2. "FIFO_THL,fifo threshold" "0,1,2,3"
bitfld.long 0x0 0. "DMA_EN,dma enbale" "0,1"
rgroup.long 0x2C++0x7
line.long 0x0 "ADC_REG_STATUS,ADC Status Register"
hexmask.long.byte 0x0 3.--8. 1. "FIFO_DATA_COUNT,fifo data number"
bitfld.long 0x0 2. "FIFO_FULL,fifo full status" "0,1"
bitfld.long 0x0 1. "FIFO_NE,fifo not empty status" "0,1"
newline
bitfld.long 0x0 0. "ACT,adc status" "0,1"
line.long 0x4 "ADC_REG_ISR,ADC ISR Register"
bitfld.long 0x4 6. "FIFO_UNDERRUN,FIFO underrun interrupt flag" "0,1"
bitfld.long 0x4 5. "FIFO_OVERRUN,FIFO overrun interrupt flag" "0,1"
bitfld.long 0x4 4. "DATASAT_POS,ADC data positive side saturation interrupt flag" "0,1"
newline
bitfld.long 0x4 3. "DATASAT_NEG,ADC data negative side saturation interrupt flag" "0,1"
bitfld.long 0x4 2. "OFFSAT,Offset correction saturation interrupt flag" "0,1"
bitfld.long 0x4 1. "GAINSAT,Gain correction saturation interrupt flag" "0,1"
newline
bitfld.long 0x4 0. "RDY,Conversion data ready interrupt flag" "0,1"
group.long 0x34++0x3
line.long 0x0 "ADC_REG_IMR,ADC IMR Register"
bitfld.long 0x0 6. "FIFO_UNDERRUN_MASK,write 1 mask" "0,1"
bitfld.long 0x0 5. "FIFO_OVERRUN_MASK,write 1 mask" "0,1"
bitfld.long 0x0 4. "DATASAT_POS_MASK,write 1 mask" "0,1"
newline
bitfld.long 0x0 3. "DATASAT_NEG_MASK,write 1 mask" "0,1"
bitfld.long 0x0 2. "OFFSAT_MASK,write 1 mask" "0,1"
bitfld.long 0x0 1. "GAINSAT_MASK,write 1 mask" "0,1"
newline
bitfld.long 0x0 0. "RDY_MASK,write 1 mask" "0,1"
rgroup.long 0x38++0x3
line.long 0x0 "ADC_REG_IRSR,ADC IRSR Register"
bitfld.long 0x0 6. "FIFO_UNDERRUN_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 5. "FIFO_OVERRUN_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 4. "DATASAT_POS_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
newline
bitfld.long 0x0 3. "DATASAT_NEG_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 2. "OFFSAT_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
bitfld.long 0x0 1. "GAINSAT_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
newline
bitfld.long 0x0 0. "RDY_RAW,The corresponding flag will be captured into this register regardless the interrupt mask. Will be cleared only when int_clr is asserted." "0,1"
group.long 0x3C++0x3
line.long 0x0 "ADC_REG_ICR,ADC ICR Register"
bitfld.long 0x0 6. "FIFO_UNDERRUN_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 5. "FIFO_OVERRUN_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 4. "DATASAT_POS_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
newline
bitfld.long 0x0 3. "DATASAT_NEG_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 2. "OFFSAT_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
bitfld.long 0x0 1. "GAINSAT_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
newline
bitfld.long 0x0 0. "RDY_CLR,Write 1 to clear both adc_reg_irsr and adc_reg_isr" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "ADC_REG_RESULT,ADC Result Register"
hexmask.long 0x0 0.--31. 1. "DATA,ADC finial conversion result data after calibratiob and signed/unsigned process"
line.long 0x4 "ADC_REG_RAW_RESULT,ADC Raw Result Register"
hexmask.long.tbyte 0x4 0.--21. 1. "RAW_DATA,ADC Raw data in signed 22bit format"
group.long 0x4C++0x17
line.long 0x0 "ADC_REG_OFFSET_CAL,ADC Offset Calibration Register"
hexmask.long.word 0x0 16.--31. 1. "OFFSET_CAL_USR,User offset calibration data. 16-bit signed."
hexmask.long.word 0x0 0.--15. 1. "OFFSET_CAL,ADC self offset calibration value. 16-bit signed ."
line.long 0x4 "ADC_REG_GAIN_CAL,ADC Gain Calibration Register"
hexmask.long.word 0x4 16.--31. 1. "GAIN_CAL_USR,ADC user gain calibration value. 16-bit signed."
hexmask.long.word 0x4 0.--15. 1. "GAIN_CAL,ADC self gain calibration value. 16-bit signed."
line.long 0x8 "ADC_REG_TEST,ADC Test Register"
bitfld.long 0x8 1.--3. "TEST_SEL,test_sel" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 0. "TEST_EN,Analog test enable." "0,1"
line.long 0xC "ADC_REG_AUDIO,ADC Audio Register"
bitfld.long 0xC 9. "PGA_CHOP_EN,Audio PGA chopper enable." "0,1"
bitfld.long 0xC 6.--8. "PGA_CM,Audio PGA output common mode control" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 3.--5. "PGA_GAIN,Audio PGA voltage gain select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0. "EN,Audio enable." "0,1"
line.long 0x10 "ADC_REG_VOICE_DET,ADC Voice Detect Register"
bitfld.long 0x10 1.--3. "LEVEL_SEL,Voice level selection." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0. "DET_EN,Voice level detection enable select" "0,1"
line.long 0x14 "ADC_REG_RSVD,ADC Reserved Register"
hexmask.long.word 0x14 0.--15. 1. "UNUSED_RESERVED_ADC_CONTROL_BITS,unused_Reserved_ADC_control_bits"
tree.end
tree.end
tree "AHB_SECURE_CTRL"
base ad:0x40148000
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "BOOTROM0_MEM_RULE[$1],0x03000000-0x0303FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40148020 ad:0x401480D0 ad:0x40148180)
tree "FLEXSPI[$1]"
base $2
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "FLEXSPI_REGION0_MEM_RULE$1,0x2 * index8rule_index00000--0x2 * index8rule_indexFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
group.long ($2+0x20)++0x3
line.long 0x0 "FLEXSPI_REGION1_MEM_RULE,0x2 * index8400000--0x2 * index87FFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long ($2+0x30)++0x3
line.long 0x0 "FLEXSPI_REGION2_MEM_RULE,0x2 * index8800000--0x2 * index8FFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long ($2+0x40)++0x3
line.long 0x0 "FLEXSPI_REGION3_MEM_RULE,0x2 * index9000000--0x2 * index9FFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long ($2+0x50)++0x3
line.long 0x0 "FLEXSPI_REGION4_MEM_RULE,0x2 * indexA000000--0x2 * indexBFFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x60)++0x3
line.long 0x0 "FLEXSPI_REGION5_MEM_RULE$1,0x2 * indexCrule_index00000--0x2 * indexCrule_indexFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
group.long ($2+0x70)++0x3
line.long 0x0 "FLEXSPI_REGION6_MEM_RULE,0x2 * indexC400000--0x2 * indexC7FFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long ($2+0x80)++0x3
line.long 0x0 "FLEXSPI_REGION7_MEM_RULE,0x2 * indexC800000--0x2 * indexCFFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long ($2+0x90)++0x3
line.long 0x0 "FLEXSPI_REGION8_MEM_RULE,0x2 * indexD000000~0x2 * indexDFFFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long ($2+0xA0)++0x3
line.long 0x0 "FLEXSPI_REGION9_MEM_RULE,0x2 * indexE000000~0x2 * indexFFFFFFF"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
tree.end
repeat.end
base ad:0x40148000
newline
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x240)++0x3
line.long 0x0 "RAM0_MEM_RULE[$1],0x20000000--0x2000FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x250)++0x3
line.long 0x0 "RAM1_MEM_RULE$1,0x20010000--0x2001FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x270)++0x3
line.long 0x0 "RAM2_MEM_RULE$1,0x20020000--0x2002FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x280)++0x3
line.long 0x0 "RAM3_MEM_RULE$1,0x20030000--0x2003FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2A0)++0x3
line.long 0x0 "RAM4_MEM_RULE$1,0x20040000--0x2004FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2B0)++0x3
line.long 0x0 "RAM5_MEM_RULE$1,0x20050000--0x2005FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2D0)++0x3
line.long 0x0 "RAM6_MEM_RULE$1,0x20060000--0x2006FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2E0)++0x3
line.long 0x0 "RAM7_MEM_RULE$1,0x20070000--0x2007FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "RAM8_MEM_RULE$1,0x20080000--0x2008FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x310)++0x3
line.long 0x0 "RAM9_MEM_RULE$1,0x20090000--0x2009FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x320)++0x3
line.long 0x0 "RAM10_MEM_RULE$1,0x200A0000--0x200AFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x330)++0x3
line.long 0x0 "RAM11_MEM_RULE$1,0x200B0000--0x200BFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x350)++0x3
line.long 0x0 "RAM12_MEM_RULE$1,0x200C0000--0x200CFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x360)++0x3
line.long 0x0 "RAM13_MEM_RULE$1,0x200D0000--0x200DFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x370)++0x3
line.long 0x0 "RAM14_MEM_RULE$1,0x200E0000--0x200EFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x380)++0x3
line.long 0x0 "RAM15_MEM_RULE$1,0x200F0000--0x200FFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x3A0)++0x3
line.long 0x0 "RAM16_MEM_RULE$1,0x20100000--0x2010FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x3B0)++0x3
line.long 0x0 "RAM17_MEM_RULE$1,0x20011000--0x20011FFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x3C0)++0x3
line.long 0x0 "RAM18_MEM_RULE$1,0x20012000--0x20012FFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
group.long 0x3E0++0x23
line.long 0x0 "APB_GRP0_MEM_RULE0,0x4000000--0x40007FFF"
bitfld.long 0x0 28.--29. "CSSV2_RULE7,0x4000 7000--0x4000 7FFF" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "PUFCTRL_RULE6,0x4000 6000--0x4000 6FFF" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "IOCON_RULE4,0x4000 4000--0x4000 4FFF" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "SYSCTL2_RULE3,0x4000 3000--0x4000 3FFF" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "SYSCTL0_RULE2,0x4000 2000--0x4000 2FFF" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "CLKCTL0_RULE1,0x4000 1000--0x4000 1FFF" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RSTCTL0_RULE0,0x4000 0000--0x4000 0FFF" "0,1,2,3"
line.long 0x4 "APB_GRP0_MEM_RULE1,0x40008000~0x4000FFFF"
bitfld.long 0x4 28.--29. "UTICK_RULE15,0x4000 F000--0x4000 FFFF" "0,1,2,3"
newline
bitfld.long 0x4 24.--25. "WWDT0_RULE14,0x4000 E000--0x4000 EFFF" "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "OCOTP_ADAP_RULE11,0x4000 A000--0x4000 AFFF" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "OCOTP_RULE10,0x4000 A000--0x4000 AFFF" "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "PKC_RULE9,0x4000 9000--0x4000 9FFF" "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "USIM_RULE8,0x4000 8000--0x4000 8FFF" "0,1,2,3"
line.long 0x8 "APB_GRP0_MEM_RULE2,0x40010000--0x40017FFF"
bitfld.long 0x8 16.--17. "TRNG_RULE20,0x4001 4000--0x4001 4FFF" "0,1,2,3"
line.long 0xC "APB_GRP0_MEM_RULE3,0x40018000--0x4001FFFF"
bitfld.long 0xC 16.--17. "C0AON_DOMAIN_TESTCON_RULE28,0x4001 C000--0x4001 CFFF" "0,1,2,3"
newline
bitfld.long 0xC 12.--13. "C0_DOMAIN_TESTCON_RULE27,0x4001 B000--0x4001 BFFF" "0,1,2,3"
line.long 0x10 "APB_GRP1_MEM_RULE0,0x40020000--0x40027FFF"
bitfld.long 0x10 24.--25. "PERIPH_INPUT_MUX_RULE6,0x4002 6000--0x4002 6FFF" "0,1,2,3"
newline
bitfld.long 0x10 20.--21. "GPIO_INTR_CTRL_RULE5,0x4002 5000--0x4002 5FFF" "0,1,2,3"
newline
bitfld.long 0x10 16.--17. "ITRC_RULE4,0x4002 4000--0x4002 4FFF" "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "SYSCTL1_RULE2,0x4002 2000--0x4002 2FFF" "0,1,2,3"
newline
bitfld.long 0x10 4.--5. "CLKCTL1_RULE1,0x4002 1000--0x4002 1FFF" "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "RSTCTL1_RULE0,0x4002 0000--0x4002 0FFF" "0,1,2,3"
line.long 0x14 "APB_GRP1_MEM_RULE1,0x40028000--0x4002FFFF"
bitfld.long 0x14 28.--29. "FREQME_RULE7,0x4002 F000--0x4002 FFFF" "0,1,2,3"
newline
bitfld.long 0x14 20.--21. "MRT_RULE5,0x4002 D000--0x4002 DFFF" "0,1,2,3"
newline
bitfld.long 0x14 12.--13. "CT32BIT3_RULE3,0x4002 B000--0x4002 BFFF" "0,1,2,3"
newline
bitfld.long 0x14 8.--9. "CT32BIT2_RULE2,0x4002 A000--0x4002 AFFF" "0,1,2,3"
newline
bitfld.long 0x14 4.--5. "CT32BIT1_RULE1,0x4002 9000--0x4002 9FFF" "0,1,2,3"
newline
bitfld.long 0x14 0.--1. "CT32BIT0_RULE0,0x4002 8000--0x4002 8FFF" "0,1,2,3"
line.long 0x18 "APB_GRP1_MEM_RULE2,0x40030000--0x40037FFF"
bitfld.long 0x18 16.--17. "FLASH_CACHE1_RULE4,0x4003 4000--0x4003 4FFF" "0,1,2,3"
newline
bitfld.long 0x18 12.--13. "FLASH_CACHE0_RULE3,0x4003 3000--0x4003 3FFF" "0,1,2,3"
newline
bitfld.long 0x18 4.--5. "PMU_RULE1,0x4003 1000--0x4003 1FFF" "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "RTC_RULE0,0x4003 0000--0x4003 0FFF" "0,1,2,3"
line.long 0x1C "APB_GRP1_MEM_RULE3,0x40038000--0x4003FFFF"
bitfld.long 0x1C 28.--29. "FREEMRT_RULE7,no description available" "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "RF_SYSCON_RULE3,0x4003 B000--0x4003 BFFF" "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "GAU_RULE0,0x4003 8000--0x4003 8FFF" "0,1,2,3"
line.long 0x20 "AHB_PERIPH0_SLAVE_RULE,0x40100000--0x4011FFFF"
bitfld.long 0x20 28.--29. "DEBUG_MAILBOX_RULE7,0x4010F000--0x4010FFFF" "0,1,2,3"
newline
bitfld.long 0x20 24.--25. "FLEXCOMM3_RULE6,0x40109000--0x40109FFF" "0,1,2,3"
newline
bitfld.long 0x20 20.--21. "FLEXCOMM2_RULE5,0x40108000--0x40108FFF" "0,1,2,3"
newline
bitfld.long 0x20 16.--17. "FLEXCOMM1_RULE4,0x40107000--0x40107FFF" "0,1,2,3"
newline
bitfld.long 0x20 12.--13. "FLEXCOMM0_RULE3,0x40106000--0x40106FFF" "0,1,2,3"
newline
bitfld.long 0x20 8.--9. "DMA1_RULE2,0x40105000--0x40105FFF" "0,1,2,3"
newline
bitfld.long 0x20 4.--5. "DMA0_RULE1,0x40104000--0x40104FFF" "0,1,2,3"
newline
bitfld.long 0x20 0.--1. "HSGPIO_RULE0,0x40100000--0x40103FFF" "0,1,2,3"
group.long 0x410++0x3
line.long 0x0 "AHB_PERIPH1_SLAVE_RULE,0x40120000--0x40127FFF"
bitfld.long 0x0 24.--25. "FLEXCOMM14_RULE6,0x40126000--0x40126FFF" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "FLEXCOMM4_RULE2,0x40122000--0x40122FFF" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "DMIC_RULE1,0x40121000--0x40121FFF" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CRC_RULE0,0x40120000--0x40120FFF" "0,1,2,3"
group.long 0x430++0x7
line.long 0x0 "AIPS_BRIDGE_MEM_RULE0,0x4013 0000 ~0x4013 7FFF"
bitfld.long 0x0 16.--17. "OSPI_AND_OTFAD_RULE4,0x4013 4000--0x4013 4FFF" "0,1,2,3"
line.long 0x4 "AIPS_BRIDGE_MEM_RULE1,0x4013 8000 ~0x4013 FFFF"
bitfld.long 0x4 28.--29. "ATX_TEST_RULE7,0x4013 F000--0x4013 FFFF" "0,1,2,3"
newline
bitfld.long 0x4 24.--25. "MTR_TEST_RULE6,0x4013 E000--0x4013 EFFF" "0,1,2,3"
newline
bitfld.long 0x4 16.--17. "ROM_CTRL_RULE4,0x4013 C000--0x4013 CFFF" "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "OSTIMER_RULE3,0x4013 B000--0x4013 BFFF" "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "ENET,0x4013 8000--0x4013 8FFF" "0,1,2,3"
group.long 0x440++0x3
line.long 0x0 "AHB_PERIPH2_SLAVE_RULE,0x40140000--0x4014BFFF"
bitfld.long 0x0 20.--21. "SECURITY_CTRL_RULE5,0x40148000--0x4014BFFF" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "SRAM_IF_REG_RULE4,0x40147000--0x40147FFF" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "SCT_RULE3,0x40146000--0x40146FFF" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "USB_HS_HOST_RULE2,0x40145000--0x40145FFF" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "USB_HS_DEV_RULE1,0x40144000--0x40144FFF" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "USB_HS_RAM_RULE0,0x40140000--0x40143FFF" "0,1,2,3"
group.long 0x450++0x3
line.long 0x0 "SECURITY_CTRL_MEM_RULE,0x40148000--0x4014BFFF"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long 0x460++0x3
line.long 0x0 "AHB_PERIPH3_SLAVE_RULE,the memory map is 0x40150000--0x40158FFF"
bitfld.long 0x0 16.--17. "PKC_RULE4,0x40158000--0x40158FFF" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "HPU_RULE3,0x40154000--0x40157FFF" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "SDIO_RULE2,0x40158000--0x40158FFF" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "SECURE_GPIO_RULE1,0x40154000--0x40157FFF" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "PQ_COPRO_RULE0,0x40150000--0x40150FFF" "0,1,2,3"
group.long 0x470++0x3
line.long 0x0 "AON_MEM_RULE,0x4015C000--0x4015FFFF"
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
group.long 0x480++0x3
line.long 0x0 "WLAN_S0_SLAVE_RULE,0x41000000-0x4137FFFF. 3.5MB"
bitfld.long 0x0 0.--1. "RULE0,0x41000000-0x4137FFFF 3.5MB" "0,1,2,3"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x490)++0x3
line.long 0x0 "WLAN_S1_MEM_RULE[$1],0x41380000-0x413FFFFF. partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
group.long 0x4A0++0x3
line.long 0x0 "BLE_S0_SLAVE_RULE,0x44000000-0x443BFFFF"
bitfld.long 0x0 0.--1. "RULE0,0x44000000-0x443BFFFF" "0,1,2,3"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4B0)++0x3
line.long 0x0 "BLE_S1_MEM_RULE[$1],0x443C0000-0x443FFFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4D0)++0x3
line.long 0x0 "SOC_TOP_MEM_RULE[$1],0x45000000-0x4500FFFF partrule_index"
bitfld.long 0x0 28.--29. "RULE7,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "RULE6,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RULE5,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "RULE4,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RULE3,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RULE2,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RULE1,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RULE0,secure control rule0. it can be set when check_reg's write_lock is '0'" "0,1,2,3"
repeat.end
repeat 18. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE00)++0x3
line.long 0x0 "SEC_VIO_ADDR[$1],most recent security violation address for AHB layer n"
hexmask.long 0x0 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
repeat.end
repeat 18. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE80)++0x3
line.long 0x0 "SEC_VIO_MISC_INFO[$1],most recent security violation miscellaneous information for AHB layer n"
hexmask.long.byte 0x0 8.--11. 1. "SEC_VIO_INFO_MASTER,security violation master number"
newline
hexmask.long.byte 0x0 4.--7. 1. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level"
newline
bitfld.long 0x0 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator 0: code 1" "0: code,?"
newline
bitfld.long 0x0 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator 0: read 1: write" "0: read,1: write"
repeat.end
group.long 0xF00++0x3
line.long 0x0 "SEC_VIO_INFO_VALID,security violation address/information registers valid flags"
bitfld.long 0x0 17. "VIO_INFO_VALID17,violation information valid flag for AHB layer 17. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 16. "VIO_INFO_VALID16,violation information valid flag for AHB layer 16. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 15. "VIO_INFO_VALID15,violation information valid flag for AHB layer 15. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 14. "VIO_INFO_VALID14,violation information valid flag for AHB layer 14. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 13. "VIO_INFO_VALID13,violation information valid flag for AHB layer 13. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 12. "VIO_INFO_VALID12,violation information valid flag for AHB layer 12. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 11. "VIO_INFO_VALID11,violation information valid flag for AHB layer 11. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 10. "VIO_INFO_VALID10,violation information valid flag for AHB layer 10. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 9. "VIO_INFO_VALID9,violation information valid flag for AHB layer 9. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 8. "VIO_INFO_VALID8,violation information valid flag for AHB layer 8. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 7. "VIO_INFO_VALID7,violation information valid flag for AHB layer 7. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 6. "VIO_INFO_VALID6,violation information valid flag for AHB layer 6. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 5. "VIO_INFO_VALID5,violation information valid flag for AHB layer 5. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 4. "VIO_INFO_VALID4,violation information valid flag for AHB layer 4. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 3. "VIO_INFO_VALID3,violation information valid flag for AHB layer 3. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 2. "VIO_INFO_VALID2,violation information valid flag for AHB layer 2. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 1. "VIO_INFO_VALID1,violation information valid flag for AHB layer 1. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
newline
bitfld.long 0x0 0. "VIO_INFO_VALID0,violation information valid flag for AHB layer 0. 0: not valid. 1: valid (violation occurred). Write 1 to clear." "0: not valid,1: valid"
group.long 0xF80++0x7
line.long 0x0 "SEC_GPIO_MASK0,Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs. I2C. UART configured as secure peripherals) pin states to non-secure world."
bitfld.long 0x0 31. "PIO0_PIN31_SEC_MASK,0 : Pin PIO0_31 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_31 state is readable by non-secure..,?"
newline
bitfld.long 0x0 30. "PIO0_PIN30_SEC_MASK,0 : Pin PIO0_30 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_30 state is readable by non-secure..,?"
newline
bitfld.long 0x0 29. "PIO0_PIN29_SEC_MASK,0 : Pin PIO0_29 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_29 state is readable by non-secure..,?"
newline
bitfld.long 0x0 28. "PIO0_PIN28_SEC_MASK,0 : Pin PIO0_28 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_28 state is readable by non-secure..,?"
newline
bitfld.long 0x0 27. "PIO0_PIN27_SEC_MASK,0 : Pin PIO0_27 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_27 state is readable by non-secure..,?"
newline
bitfld.long 0x0 26. "PIO0_PIN26_SEC_MASK,0 : Pin PIO0_26 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_26 state is readable by non-secure..,?"
newline
bitfld.long 0x0 25. "PIO0_PIN25_SEC_MASK,0 : Pin PIO0_25 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_25 state is readable by non-secure..,?"
newline
bitfld.long 0x0 24. "PIO0_PIN24_SEC_MASK,0 : Pin PIO0_24 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_24 state is readable by non-secure..,?"
newline
bitfld.long 0x0 23. "PIO0_PIN23_SEC_MASK,0 : Pin PIO0_23 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_23 state is readable by non-secure..,?"
newline
bitfld.long 0x0 22. "PIO0_PIN22_SEC_MASK,0 : Pin PIO0_22 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_22 state is readable by non-secure..,?"
newline
bitfld.long 0x0 21. "PIO0_PIN21_SEC_MASK,0 : Pin PIO0_21 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_21 state is readable by non-secure..,?"
newline
bitfld.long 0x0 20. "PIO0_PIN20_SEC_MASK,0 : Pin PIO0_20 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_20 state is readable by non-secure..,?"
newline
bitfld.long 0x0 19. "PIO0_PIN19_SEC_MASK,0 : Pin PIO0_19 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_19 state is readable by non-secure..,?"
newline
bitfld.long 0x0 18. "PIO0_PIN18_SEC_MASK,0 : Pin PIO0_18 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_18 state is readable by non-secure..,?"
newline
bitfld.long 0x0 17. "PIO0_PIN17_SEC_MASK,0 : Pin PIO0_17 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_17 state is readable by non-secure..,?"
newline
bitfld.long 0x0 16. "PIO0_PIN16_SEC_MASK,0 : Pin PIO0_16 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_16 state is readable by non-secure..,?"
newline
bitfld.long 0x0 15. "PIO0_PIN15_SEC_MASK,0 : Pin PIO0_15 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_15 state is readable by non-secure..,?"
newline
bitfld.long 0x0 14. "PIO0_PIN14_SEC_MASK,0 : Pin PIO0_14 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_14 state is readable by non-secure..,?"
newline
bitfld.long 0x0 13. "PIO0_PIN13_SEC_MASK,0 : Pin PIO0_13 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_13 state is readable by non-secure..,?"
newline
bitfld.long 0x0 12. "PIO0_PIN12_SEC_MASK,0 : Pin PIO0_12 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_12 state is readable by non-secure..,?"
newline
bitfld.long 0x0 11. "PIO0_PIN11_SEC_MASK,0 : Pin PIO0_11 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_11 state is readable by non-secure..,?"
newline
bitfld.long 0x0 10. "PIO0_PIN10_SEC_MASK,0 : Pin PIO0_10 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_10 state is readable by non-secure..,?"
newline
bitfld.long 0x0 9. "PIO0_PIN9_SEC_MASK,0 : Pin PIO0_9 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_9 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 8. "PIO0_PIN8_SEC_MASK,0 : Pin PIO0_8 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_8 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 7. "PIO0_PIN7_SEC_MASK,0 : Pin PIO0_7 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_7 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 6. "PIO0_PIN6_SEC_MASK,0 : Pin PIO0_6 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_6 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 5. "PIO0_PIN5_SEC_MASK,0 : Pin PIO0_5 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_5 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 4. "PIO0_PIN4_SEC_MASK,0 : Pin PIO0_4 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_4 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 3. "PIO0_PIN3_SEC_MASK,0 : Pin PIO0_3 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_3 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 2. "PIO0_PIN2_SEC_MASK,0 : Pin PIO0_2 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_2 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 1. "PIO0_PIN1_SEC_MASK,0 : Pin PIO0_1 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_1 state is readable by non-secure world..,?"
newline
bitfld.long 0x0 0. "PIO0_PIN0_SEC_MASK,0 : Pin PIO0_0 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO0_0 state is readable by non-secure world..,?"
line.long 0x4 "SEC_GPIO_MASK1,Secure GPIO mask for port 1 pins."
bitfld.long 0x4 31. "PIO1_PIN31_SEC_MASK,0 : Pin PIO1_31 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_31 state is readable by non-secure..,?"
newline
bitfld.long 0x4 30. "PIO1_PIN30_SEC_MASK,0 : Pin PIO1_30 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_30 state is readable by non-secure..,?"
newline
bitfld.long 0x4 29. "PIO1_PIN29_SEC_MASK,0 : Pin PIO1_29 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_29 state is readable by non-secure..,?"
newline
bitfld.long 0x4 28. "PIO1_PIN28_SEC_MASK,0 : Pin PIO1_28 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_28 state is readable by non-secure..,?"
newline
bitfld.long 0x4 27. "PIO1_PIN27_SEC_MASK,0 : Pin PIO1_27 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_27 state is readable by non-secure..,?"
newline
bitfld.long 0x4 26. "PIO1_PIN26_SEC_MASK,0 : Pin PIO1_26 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_26 state is readable by non-secure..,?"
newline
bitfld.long 0x4 25. "PIO1_PIN25_SEC_MASK,0 : Pin PIO1_25 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_25 state is readable by non-secure..,?"
newline
bitfld.long 0x4 24. "PIO1_PIN24_SEC_MASK,0 : Pin PIO1_24 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_24 state is readable by non-secure..,?"
newline
bitfld.long 0x4 23. "PIO1_PIN23_SEC_MASK,0 : Pin PIO1_23 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_23 state is readable by non-secure..,?"
newline
bitfld.long 0x4 22. "PIO1_PIN22_SEC_MASK,0 : Pin PIO1_22 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_22 state is readable by non-secure..,?"
newline
bitfld.long 0x4 21. "PIO1_PIN21_SEC_MASK,0 : Pin PIO1_21 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_21 state is readable by non-secure..,?"
newline
bitfld.long 0x4 20. "PIO1_PIN20_SEC_MASK,0 : Pin PIO1_20 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_20 state is readable by non-secure..,?"
newline
bitfld.long 0x4 19. "PIO1_PIN19_SEC_MASK,0 : Pin PIO1_19 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_19 state is readable by non-secure..,?"
newline
bitfld.long 0x4 18. "PIO1_PIN18_SEC_MASK,0 : Pin PIO1_18 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_18 state is readable by non-secure..,?"
newline
bitfld.long 0x4 17. "PIO1_PIN17_SEC_MASK,0 : Pin PIO1_17 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_17 state is readable by non-secure..,?"
newline
bitfld.long 0x4 16. "PIO1_PIN16_SEC_MASK,0 : Pin PIO1_16 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_16 state is readable by non-secure..,?"
newline
bitfld.long 0x4 15. "PIO1_PIN15_SEC_MASK,0 : Pin PIO1_15 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_15 state is readable by non-secure..,?"
newline
bitfld.long 0x4 14. "PIO1_PIN14_SEC_MASK,0 : Pin PIO1_14 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_14 state is readable by non-secure..,?"
newline
bitfld.long 0x4 13. "PIO1_PIN13_SEC_MASK,0 : Pin PIO1_13 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_13 state is readable by non-secure..,?"
newline
bitfld.long 0x4 12. "PIO1_PIN12_SEC_MASK,0 : Pin PIO1_12 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_12 state is readable by non-secure..,?"
newline
bitfld.long 0x4 11. "PIO1_PIN11_SEC_MASK,0 : Pin PIO1_11 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_11 state is readable by non-secure..,?"
newline
bitfld.long 0x4 10. "PIO1_PIN10_SEC_MASK,0 : Pin PIO1_10 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_10 state is readable by non-secure..,?"
newline
bitfld.long 0x4 9. "PIO1_PIN9_SEC_MASK,0 : Pin PIO1_9 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_9 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 8. "PIO1_PIN8_SEC_MASK,0 : Pin PIO1_8 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_8 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 7. "PIO1_PIN7_SEC_MASK,0 : Pin PIO1_7 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_7 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 6. "PIO1_PIN6_SEC_MASK,0 : Pin PIO1_6 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_6 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 5. "PIO1_PIN5_SEC_MASK,0 : Pin PIO1_5 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_5 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 4. "PIO1_PIN4_SEC_MASK,0 : Pin PIO1_4 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_4 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 3. "PIO1_PIN3_SEC_MASK,0 : Pin PIO1_3 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_3 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 2. "PIO1_PIN2_SEC_MASK,0 : Pin PIO1_2 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_2 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 1. "PIO1_PIN1_SEC_MASK,0 : Pin PIO1_1 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_1 state is readable by non-secure world..,?"
newline
bitfld.long 0x4 0. "PIO1_PIN0_SEC_MASK,0 : Pin PIO1_0 state is readable by non-secure world through non-secure GPIO port control registers" "0: Pin PIO1_0 state is readable by non-secure world..,?"
group.long 0xFBC++0x3
line.long 0x0 "SEC_GPIO_MASK_LOCK,sec_gp_reg write-lock bits"
bitfld.long 0x0 2.--3. "SEC_GP_REG1_LOCK,2'b10: sec_reg_reg1 can be written. All other values: sec_reg_reg1 can't be written." "?,?,2: sec_reg_reg1 can be written,?"
newline
bitfld.long 0x0 0.--1. "SEC_GP_REG0_LOCK,2'b10: sec_reg_reg0 can be written. All other values: sec_reg_reg0 can't be written." "?,?,2: sec_reg_reg0 can be written,?"
group.long 0xFD0++0x7
line.long 0x0 "MASTER_SEC_REG,master secure level register"
bitfld.long 0x0 30.--31. "MASTER_SEC_LEVEL_LOCK,master_sec_reg write-lock. When 2'b10 this register can be written. With any other value this register can't be written." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "GDMA,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ENET,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "SDIO,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "PKC,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "USB,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "CSS,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "DMA1,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "DMA0,master secure level control." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "POWERQUAD,master secure level control." "0,1,2,3"
line.long 0x4 "MASTER_SEC_ANTI_POL_REG,master secure level anti-pole register"
bitfld.long 0x4 30.--31. "MASTER_SEC_LEVEL_ANTIPOL_LOCK,master_sec_antipol_reg register write-lock. When 2'b10 this register can be written. With any other value this register can't be written." "0,1,2,3"
newline
bitfld.long 0x4 20.--21. "GDMA,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "ENET,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 16.--17. "SDIO,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "PKC,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "USB,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "CSS,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "DMA1,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "DMA0,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "POWERQUAD,master secure level control anti-pole value (i.e It must be written with the inverted value of the corresponding field in master_sec_reg)." "0,1,2,3"
group.long 0xFEC++0x3
line.long 0x0 "CM33_LOCK_REG,m33 lock control register"
bitfld.long 0x0 30.--31. "M33_LOCK_REG_LOCK,2'b10: this register can be written. All other values: this register can't be written" "?,?,2: this register can be written,?"
newline
bitfld.long 0x0 8.--9. "LOCK_SAU,2'b10:m33 LOCKSAU is 0. All other values: m33 LOCKSAU is 1" "?,?,2: m33 LOCKSAU is 0,?"
newline
bitfld.long 0x0 6.--7. "LOCK_S_MPU,2'b10:m33 LOCKSMPU is 0. All other values: m33 LOCKSMPU is 1" "?,?,2: m33 LOCKSMPU is 0,?"
newline
bitfld.long 0x0 4.--5. "LOCK_S_VTAIRCR,2'b10:m33 LOCKSVTAURCR is 0. All other values: m33 LOCKSVTAURCR is 1" "?,?,2: m33 LOCKSVTAURCR is 0,?"
newline
bitfld.long 0x0 2.--3. "LOCK_NS_MPU,2'b10:m33 LOCKNSMPU is 0. All other values: m33 LOCKNSMPU is 1" "?,?,2: m33 LOCKNSMPU is 0,?"
newline
bitfld.long 0x0 0.--1. "LOCK_NS_VTOR,2'b10: m33 LOCKNSVTOR is 0. All other values: m33 LOCKNSVTOR is 1" "?,?,2: m33 LOCKNSVTOR is 0,?"
group.long 0xFF8++0x7
line.long 0x0 "MISC_CTRL_DP_REG,secure control duplicate register"
bitfld.long 0x0 14.--15. "IDAU_ALL_NS,00 11 10 : IDAU is enabled" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "DISABLE_STRICT_MODE,00 11 10 = Simple master in strict mode" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "DISABLE_VIOLATION_ABORT,Disable secure violation abort" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ENABLE_NS_PRIV_CHECK,AHB bus matrix enable non-secure privilege check" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "ENABLE_S_PRIV_CHECK,AHB bus matrix enable secure privilege check" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ENABLE_SECURE_CHECKING,AHB bus matrix enable secure checking. 10: disabled. All other values: enabled (restrictive mode)" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "WRITE_LOCK,write lock" "0,1,2,3"
line.long 0x4 "MISC_CTRL_REG,secure control register"
bitfld.long 0x4 14.--15. "IDAU_ALL_NS,00 11 10 : IDAU is enabled" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "DISABLE_STRICT_MODE,00 11 10 = Simple master in strict mode" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "DISABLE_VIOLATION_ABORT,Disable secure violation abort" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "ENABLE_NS_PRIV_CHECK,AHB bus matrix enable non-secure privilege check" "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "ENABLE_S_PRIV_CHECK,AHB bus matrix enable secure privilege check" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "ENABLE_SECURE_CHECKING,AHB bus matrix enable secure checking. 10: disabled. All other values: enabled (restrictive mode)" "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "WRITE_LOCK,write lock" "0,1,2,3"
tree.end
tree "AON"
base ad:0x0
tree "AON_SOC_CIU"
base ad:0x45000800
group.long 0x0++0x3
line.long 0x0 "PAD_CONFIG0,'"
bitfld.long 0x0 31. "XOSC_ENA_PAD_SEL,xosc_ena_pads selection from CAU or mci_top" "0,1"
bitfld.long 0x0 17. "XOSC_OD_EN,Crystal Oscillator Enable Output Open-Drain Enable for GPIO[0]" "0,1"
bitfld.long 0x0 1. "PAD_PWRDOWN_LATCH,Enables the pd_sel latching" "0,1"
group.long 0x10++0x3
line.long 0x0 "PAD_PWRDOWN_CTRL2,Pad Power-down Control 2"
bitfld.long 0x0 20.--22. "GPIO27_PD_SEL,Power Down Output Value for GPIO[27] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "GPIO26_PD_SEL,Power Down Output Value for GPIO[26] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 12.--14. "GPIO25_PD_SEL,Power Down Output Value for GPIO[25] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8.--10. "GPIO24_PD_SEL,Power Down Output Value for GPIO[24] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4.--6. "GPIO23_PD_SEL,Power Down Output Value for GPIO[23] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "GPIO22_PD_SEL,Power Down Output Value for GPIO[22] Pad" "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x0 "SR_CONFIG1,GPIO Slew Rate control"
bitfld.long 0x0 22.--23. "GPIO27_SR,Slew Rate Control for GPIO[27]" "0,1,2,3"
bitfld.long 0x0 20.--21. "GPIO26_SR,Slew Rate Control for GPIO[26]" "0,1,2,3"
bitfld.long 0x0 18.--19. "GPIO25_SR,Slew Rate Control for GPIO[25]" "0,1,2,3"
bitfld.long 0x0 16.--17. "GPIO24_SR,Slew Rate Control for GPIO[24]" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "GPIO23_SR,Slew Rate Control for GPIO[23]" "0,1,2,3"
bitfld.long 0x0 12.--13. "GPIO22_SR,Slew Rate Control for GPIO[22]" "0,1,2,3"
group.long 0x74++0x3
line.long 0x0 "PAD_PU_PD_EN1,Pad Pull-up Pull-down Enable2"
bitfld.long 0x0 22.--23. "GPIO27_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[27]" "0,1,2,3"
bitfld.long 0x0 20.--21. "GPIO26_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[26]" "0,1,2,3"
bitfld.long 0x0 18.--19. "GPIO25_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[25]" "0,1,2,3"
bitfld.long 0x0 16.--17. "GPIO24_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[24]" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "GPIO23_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[23]" "0,1,2,3"
bitfld.long 0x0 12.--13. "GPIO22_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[22]" "0,1,2,3"
group.long 0x8C++0x3
line.long 0x0 "PAD_SLP_EN0,Pad Sleep Mode Enable"
bitfld.long 0x0 27. "GPIO27_SLP_EN,Enable Forcing GPIO[27] Output During Sleep" "0,1"
bitfld.long 0x0 26. "GPIO26_SLP_EN,Enable Forcing GPIO[26] Output During Sleep" "0,1"
bitfld.long 0x0 25. "GPIO25_SLP_EN,Enable Forcing GPIO[25] Output During Sleep" "0,1"
bitfld.long 0x0 24. "GPIO24_SLP_EN,Enable Forcing GPIO[24] Output During Sleep" "0,1"
newline
bitfld.long 0x0 23. "GPIO23_SLP_EN,Enable Forcing GPIO[23] Output During Sleep" "0,1"
bitfld.long 0x0 22. "GPIO22_SLP_EN,Enable Forcing GPIO[22] Output During Sleep" "0,1"
group.long 0x98++0x3
line.long 0x0 "PAD_SLP_VAL0,Pad Sleep Mode Value"
bitfld.long 0x0 27. "GPIO27_SLP_VAL,Force GPIO[27] Output During Sleep" "0,1"
bitfld.long 0x0 26. "GPIO26_SLP_VAL,Force GPIO[26] Output During Sleep" "0,1"
bitfld.long 0x0 25. "GPIO25_SLP_VAL,Force GPIO[25] Output During Sleep" "0,1"
bitfld.long 0x0 24. "GPIO24_SLP_VAL,Force GPIO[24] Output During Sleep" "0,1"
newline
bitfld.long 0x0 23. "GPIO23_SLP_VAL,Force GPIO[23] Output During Sleep" "0,1"
bitfld.long 0x0 22. "GPIO22_SLP_VAL,Force GPIO[22] Output During Sleep" "0,1"
group.long 0x10C++0x3
line.long 0x0 "RST_SW,Reset Controls for SOC_RESET_GEN"
bitfld.long 0x0 25. "AON_SOCCIU_RSTB,reset for the aon socciu registers. It gets auto clear" "0,1"
bitfld.long 0x0 24. "SOCAON_ITRC_CHIP_RSTB_EN,Default the itrc chip reset can reset SOCAON (jtag) SW can disable this if not required" "0,1"
bitfld.long 0x0 9. "BUCK_REG_RST,config reg SW reset for BUCK18 and BUCK11 active high" "0,1"
rgroup.long 0x130++0x3
line.long 0x0 "STRAP_FINISH_STATUS,SOC Strap Finish Status"
bitfld.long 0x0 0. "STRAP_FINISH,Strap Finish status from strap logic." "0,1"
group.long 0x13C++0x3
line.long 0x0 "SOC_OTP_CONTROL,Power Switch (1.8v) Control for SOC OTP"
bitfld.long 0x0 0. "SOC_OTP_PSW18_PD,Power-Down control for the 1.8V Power-Switch for OTPs on SOC side" "0,1"
group.long 0x204++0x3
line.long 0x0 "PAD_AON_VREG_VSENSOR_CTRL,AON Vsensor and Vreg Pad Control"
rbitfld.long 0x0 14. "VSENSOR_DETECT,VIO_AON_Vsensor_Detect_V18 Status" "0,1"
bitfld.long 0x0 13. "V25EN_CORE,V25EN_CORE" "0,1"
bitfld.long 0x0 12. "VSENSOR_VTHRESH,Vsensor AON Detection Threshold" "0,1"
bitfld.long 0x0 9.--11. "VSENSOR_TEST,Vsensor AON Test Point Mux Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "VSENSOR_TE,Vsensor AON Test Enable" "0,1"
bitfld.long 0x0 7. "VSENSOR_CLK_12,Vsensor AON Clock" "0,1"
bitfld.long 0x0 6. "VSENSOR_DISABLE_12,Vsensor AON disable" "0,1"
bitfld.long 0x0 5. "VSENSOR_V18EN_12_IN,Bypass Value when Vsensor_Bypass Bit Set" "0,1"
newline
bitfld.long 0x0 4. "VSENSOR_BYPASS,Active High Enable Signal for Bypass Mode" "0,1"
bitfld.long 0x0 1. "VIO_REG_CTRL_EN,VIO reg control enable function" "0,1"
bitfld.long 0x0 0. "VIO_REG_ENB,VIO_AON Pad Regulator" "0,1"
group.long 0x400++0x3
line.long 0x0 "TST_REDBIST_CTRL,Redundant BIST Control"
bitfld.long 0x0 3. "REDBIST_MODE_EN,Redundant Bist Mode Enable" "0,1"
bitfld.long 0x0 0.--2. "REDBIST_SEL,Redundant Bist Selection" "0,1,2,3,4,5,6,7"
group.long 0x40C++0x3
line.long 0x0 "TST_MBIST_CTRL,MBIST Control"
bitfld.long 0x0 2. "MBIST_EN_BYPASS_EN,CIU to Control Memory BIST (instead of JTAG)" "0,1"
bitfld.long 0x0 1. "MBIST_ROWCOL_CTRL,Small Memory Row_Cel_Switch Control" "0,1"
bitfld.long 0x0 0. "MBIST_EN_BYPASS_VAL,Small Memory and ROM BIST Logic" "0,1"
group.long 0x44C++0x3
line.long 0x0 "TST_JTAG_LOADER_BOOT_CTRL,JTAG loader and boot code interaction control"
hexmask.long.byte 0x0 8.--11. 1. "STRAP,Boot code after setting 0xB on GPIO polls for the bit[1:0] and when bit[0] is set it uses the information in [11:8] for host boot"
bitfld.long 0x0 4. "JTAG_CIU_BUSY,JTAG ciu busy for BUSY bit observation" "0,1"
rbitfld.long 0x0 3. "JTAG_CIU_REQ,JTAG ciu request" "0,1"
rbitfld.long 0x0 2. "JTAG_CIU_IRAM_2,The ATE final test signal. Boot code will poll it to know it is for final test" "0,1"
newline
rbitfld.long 0x0 1. "WARM_BOOT,warm boot" "0,1"
rbitfld.long 0x0 0. "BOOT_FLAG,Boot_flag is polled by boot code after setting 0xB on GPIO" "0,1"
rgroup.long 0x480++0x3
line.long 0x0 "STRAP_RDBK,Strap Readback"
hexmask.long.byte 0x0 20.--23. 1. "REF_CLK_RATE,CAU Reference Clock Rate"
bitfld.long 0x0 14. "QFN_BOND,Bond Strap Value" "0,1"
bitfld.long 0x0 11. "DAP_USE_JTAG,1 (Default): DAP uses JTAG" "0,1"
bitfld.long 0x0 8. "DIS_KEY_ROT_DBG,dis_key_rot_dbg" "0,1"
newline
bitfld.long 0x0 7. "VTOR_SEL,Strap bit to select secure VTOR base addr of CM33" "0,1"
bitfld.long 0x0 5.--6. "XOSC_SEL,Crystal Osc Enable" "0,1,2,3"
bitfld.long 0x0 4. "REF_CLK_DETECT,ref_clk_detect (reserved)" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "MODE,Boot Options:"
group.long 0x484++0x3
line.long 0x0 "STRAP_SW,Software Strap Override"
bitfld.long 0x0 31. "ENABLE,Software Strap Mode Enable" "0,1"
hexmask.long.byte 0x0 20.--23. 1. "REF_CLK_RATE,CAU Reference Clock Rate"
bitfld.long 0x0 14. "QFN_BOND,Bond Type" "0,1"
bitfld.long 0x0 5.--6. "XOSC_SEL,Crystal Osc Enable" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "MODE,Below are the modes selected based on the value of this field:"
group.long 0x500++0x3
line.long 0x0 "PAD_SLP_PU_PD_DIS0,Pad Sleep Pullup and Pulldown Disable1"
bitfld.long 0x0 27. "GPIO27_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[27] During Sleep Mode" "0,1"
bitfld.long 0x0 26. "GPIO26_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[26] During Sleep Mode" "0,1"
bitfld.long 0x0 25. "GPIO25_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[25] During Sleep Mode" "0,1"
bitfld.long 0x0 24. "GPIO24_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[24] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 23. "GPIO23_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[23] During Sleep Mode" "0,1"
bitfld.long 0x0 22. "GPIO22_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[22] During Sleep Mode" "0,1"
rgroup.long 0x518++0x1F
line.long 0x0 "JTAG_CIU_CMD0,JTAG ciu cmd byte 0"
hexmask.long 0x0 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [31:0]"
line.long 0x4 "JTAG_CIU_CMD1,JTAG ciu cmd byte 1"
hexmask.long 0x4 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [63:32]"
line.long 0x8 "JTAG_CIU_CMD2,JTAG ciu cmd byte 2"
hexmask.long 0x8 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [95:64]"
line.long 0xC "JTAG_CIU_CMD3,JTAG ciu cmd byte 3"
hexmask.long 0xC 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [127:96]"
line.long 0x10 "JTAG_CIU_CMD4,JTAG ciu cmd byte 4"
hexmask.long 0x10 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [159:128]"
line.long 0x14 "JTAG_CIU_CMD5,JTAG ciu cmd byte 5"
hexmask.long 0x14 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [191:160]"
line.long 0x18 "JTAG_CIU_CMD6,JTAG ciu cmd byte 6"
hexmask.long 0x18 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [223:192]"
line.long 0x1C "JTAG_CIU_CMD7,JTAG ciu cmd byte 7"
hexmask.long 0x1C 0.--31. 1. "JTAG_CIU_CMD,JTAG ciu cmd reg bit [255:224]"
group.long 0x538++0x3
line.long 0x0 "MCI_IOMUX_EN0,mci_iomux_enable control for GPIO[31:0]"
hexmask.long.byte 0x0 22.--27. 1. "EN_27_22,Bitwise enable control for mci_io_mux GPIO[27:22]"
group.long 0x550++0x3
line.long 0x0 "ECO_CTRL,Test ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0x600++0x3
line.long 0x0 "EXTRA_PORTS,EXTRA Ports"
hexmask.long.byte 0x0 8.--15. 1. "SOCCIU_MCI_EXTRA_IN,Extra Ports from MCI"
hexmask.long.byte 0x0 0.--7. 1. "SOCCIU_MCI_EXTRA_OUT,Extra Ports to MCI"
tree.end
tree "AON_TESTMUX"
base ad:0x45001C00
group.long 0x0++0x27
line.long 0x0 "CONFIG1_REG0,config1 reg for first block-1 of testmux"
bitfld.long 0x0 24.--25. "BIT_3_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x0 16.--17. "BIT_2_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x0 8.--9. "BIT_1_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x0 0.--1. "BIT_0_SEL,Config1 reg0 bit0 select" "0,1,2,3"
line.long 0x4 "CONFIG1_REG1,config1 reg for first block-1 of testmux"
bitfld.long 0x4 24.--25. "BIT_7_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x4 16.--17. "BIT_6_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x4 8.--9. "BIT_5_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x4 0.--1. "BIT_4_SEL,Same as Bit 0" "0,1,2,3"
line.long 0x8 "CONFIG1_REG2,config2 reg for block-2 of testmux"
bitfld.long 0x8 24.--25. "BIT_11_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x8 16.--17. "BIT_10_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x8 8.--9. "BIT_9_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x8 0.--1. "BIT_8_SEL,Same as Bit 0" "0,1,2,3"
line.long 0xC "CONFIG1_REG3,config2 reg for block-2 of testmux"
bitfld.long 0xC 24.--25. "BIT_15_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0xC 16.--17. "BIT_14_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0xC 8.--9. "BIT_13_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0xC 0.--1. "BIT_12_SEL,Same as Bit 0" "0,1,2,3"
line.long 0x10 "CONFIG2_REG0,config1 reg for first block-1 of testmux"
bitfld.long 0x10 24.--25. "BIT_3_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x10 16.--17. "BIT_2_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x10 8.--9. "BIT_1_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x10 0.--1. "BIT_0_SEL,Same as Bit 0" "0,1,2,3"
line.long 0x14 "CONFIG2_REG1,config1 reg for first block-1 of testmux"
bitfld.long 0x14 24.--25. "BIT_7_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x14 16.--17. "BIT_6_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x14 8.--9. "BIT_5_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x14 0.--1. "BIT_4_SEL,Same as Bit 0" "0,1,2,3"
line.long 0x18 "CONFIG2_REG2,config2 reg for block-2 of testmux"
bitfld.long 0x18 24.--25. "BIT_11_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x18 16.--17. "BIT_10_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x18 8.--9. "BIT_9_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x18 0.--1. "BIT_8_SEL,Same as Bit 0" "0,1,2,3"
line.long 0x1C "CONFIG2_REG3,config2 reg for block-2 of testmux"
bitfld.long 0x1C 24.--25. "BIT_15_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x1C 16.--17. "BIT_14_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x1C 8.--9. "BIT_13_SEL,Same as Bit 0" "0,1,2,3"
bitfld.long 0x1C 0.--1. "BIT_12_SEL,Same as Bit 0" "0,1,2,3"
line.long 0x20 "TESTMUX_CONFIG_REG,config reg for testmux"
hexmask.long.byte 0x20 27.--31. 1. "ROTATE_SEL,rotation config : 1 bit roation"
bitfld.long 0x20 1.--2. "REMAP_SEL,Remaping scheme -" "0,1,2,3"
bitfld.long 0x20 0. "BITWISE_SEL_EN,Bitwise select enable" "0,1"
line.long 0x24 "CONFIG_TEST_MODE,testmode enable disable control"
hexmask.long.byte 0x24 0.--3. 1. "EN,Config testmode enable"
tree.end
tree.end
tree "APU"
base ad:0x0
tree "APU0"
base ad:0x41258400
rgroup.long 0x0++0x3
line.long 0x0 "APU_IP_REVISION,APU IP revision"
hexmask.long.word 0x0 0.--15. 1. "IP_REV,IP revision"
group.long 0x4++0x1F
line.long 0x0 "CTRL,Control"
bitfld.long 0x0 25. "CPU1_MSG_RDY_MASK,CPU1 Message Ready Mask" "0,1"
newline
bitfld.long 0x0 24. "FW_CP15_SLEEP,FW CP15 Sleep" "0,1"
newline
bitfld.long 0x0 23. "CP_15_SLEEP_MASK,CP15 Sleep Mask" "0,1"
newline
bitfld.long 0x0 22. "FW_IPS_CP15_SLEEP,FW IPS CP15 Sleep" "0,1"
newline
bitfld.long 0x0 21. "IPS_CP15_SLEEP_MASK,IPS CP15 Sleep Mask" "0,1"
newline
bitfld.long 0x0 17. "SDU_SLP_RDY_MASK,SDU Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 15. "APU_SW_ACC_RST,APU SW ACC Reset" "0,1"
newline
bitfld.long 0x0 14. "RST_APU_SLPCLK_TIMER,Reset APU Sleep Clock Timer" "0,1"
newline
bitfld.long 0x0 13. "SW_TIMER_LD,SW Timer" "0,1"
newline
bitfld.long 0x0 12. "APU_NO_TBTT_RESET,APU No TBTT Reset" "0,1"
newline
bitfld.long 0x0 11. "APU_AUTO_CALIBRATE,APU Auto Calibrate" "0,1"
newline
bitfld.long 0x0 10. "APU_ALLOW_AUTO_LOAD,APU Allow Auto load" "0,1"
newline
bitfld.long 0x0 9. "USE_HOST_INTR_SLP,Use Host Interrupt Sleep" "0,1"
newline
bitfld.long 0x0 8. "ENTER_ALL_SLEEP_MODE,Enter All Sleep Mode" "0,1"
newline
bitfld.long 0x0 7. "APU_CAL_DONE_CLEAR_METHOD,1- use falling edge of apu_sw_acc_rst to clear the apu_cal_done after FW polls the apu_cal_done = 1" "0,1"
newline
bitfld.long 0x0 4.--6. "APU_SUBSYS1_HOST,APU Subsystem1 Host" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3. "WLCOMN_USE_NOM_PWR_BYP,WLAN comman domain uses nominal voltage" "0,1"
newline
bitfld.long 0x0 1. "FW_CPU1_PD,FW CPU1 Pd" "0,1"
newline
bitfld.long 0x0 0. "CPU1_PD_MASK,CPU1 Pd Mask" "0,1"
line.long 0x4 "TIMER_PWR_MODE,Timer Power Mode"
bitfld.long 0x4 24. "USE_HSIC_SLP_SYNC,Use HSIC Sleep Sync" "0,1"
newline
bitfld.long 0x4 23. "XOSC_ON_WHILE_SLEEP,XOSC On While Sleep" "0,1"
newline
bitfld.long 0x4 22. "GENERIC_TIMER_BYPASS,When set to 1 generic_alarm_en2 will be used for generic_alarm_en1" "0,1"
newline
bitfld.long 0x4 21. "GENERIC_TIMER_EN,Enable sleep timer to generate interrupt when value matches generic timer value. Debug only" "0,1"
newline
bitfld.long 0x4 18. "ENA_FAST_WKUP,Enable Fast Wakeup" "0,1"
newline
bitfld.long 0x4 17. "SOC_XOSC_PWR_ON,SoC XOSC Power on" "0,1"
newline
bitfld.long 0x4 13. "DIS_APU_INTR_ON_WAKEUP,Disable APU Interrupt on Wakeup" "0,1"
newline
bitfld.long 0x4 12. "XP_OPT_EN,Set to 1 to enable the sleep FSM to look for wakeup req after power shutdown and before reference clock shutdown." "0,1"
newline
bitfld.long 0x4 7. "DIS_GATED_SLP_CLK,Disable Gated Sleep Clock" "0,1"
newline
bitfld.long 0x4 6. "WL2_BCN_ALARM_TIMER_EN,WLAN2 beacon alarm timer enable" "0,1"
newline
bitfld.long 0x4 5. "WL_BCN_ALARM_TIMER_EN,WLAN beacon alarm timer enable" "0,1"
newline
bitfld.long 0x4 4. "SLP_CLK_TIMER_EN,free running sleep clock timer enable" "0,1"
newline
bitfld.long 0x4 0. "MCI_XP_REQ_MASK,MCI XP Request Mask" "0,1"
line.long 0x8 "PWR_CTRL,Power Control"
bitfld.long 0x8 15. "PCIE_P_REQ_MASK_FOR_SLPFSM,Mask pcie_p_req and pcie_xp_req for slp_fsm" "0,1"
newline
bitfld.long 0x8 14. "DLY_NON_UDR_RSTB,Delay non-UDR RSTb" "0,1"
newline
bitfld.long 0x8 13. "RFU_IN_WLAN_DOMAIN,RFU WLAN mode" "0,1"
newline
bitfld.long 0x8 12. "SOC_USE_UNSYNC_VOL_LVL,SoC Use unSync Vol Level" "0,1"
newline
bitfld.long 0x8 11. "SOC_USE_NOM_VOL_BYP,SoC Use Nominal Vol Bypass" "0,1"
newline
bitfld.long 0x8 10. "CLK_DIV_RESETB_REFCLK,CLK_DIV_RESETB Reference Clock" "0,1"
newline
bitfld.long 0x8 9. "CLK_DIV_RESETB_ENABLE,CLK_DIV_RESETB Enable" "0,1"
newline
bitfld.long 0x8 8. "SRAM_PD_EN,APU SRAM power down enable" "0,1"
newline
bitfld.long 0x8 7. "XOSC_OFF_DURING_POWER_OFF,XOSC Off During Power Off" "0,1"
newline
bitfld.long 0x8 6. "NON_UDR_RSTB_EN,APU non-UDR reset enable" "0,1"
newline
bitfld.long 0x8 5. "ISO_ENABLE_REFCK,ISO Enable Reference Clock" "0,1"
newline
bitfld.long 0x8 4. "DLY_UDR2ISO,UDR firewall_bar to isolation delay enable" "0,1"
newline
bitfld.long 0x8 3. "APU_ISO_CELL_EN,APU isolation enable" "0,1"
newline
bitfld.long 0x8 2. "APU_UDR_FIREWALL_BAR_EN,APU UDR enable" "0,1"
newline
bitfld.long 0x8 1. "APU_SW_PD_EN,APU switch power down enable" "0,1"
newline
bitfld.long 0x8 0. "APU_PD_CTRL_EN,APU power domain control enable" "0,1"
line.long 0xC "PLL_CTRL,PLL Control"
bitfld.long 0xC 9. "FW_PLL1_EN_SET,Fw sets pll_en[1] value when apu_pll_ctrl[4] = 1 " "0,1"
newline
bitfld.long 0xC 8. "FW_USE_PLL1,When set to 1 FW controls pll_en[1] value (pll0 is Tcpu in Skyhawk)" "0,1"
newline
bitfld.long 0xC 5. "FW_PLL0_EN_SET,Fw sets pll_en[0] value when apu_pll_ctrl[4] = 1 " "0,1"
newline
bitfld.long 0xC 4. "FW_USE_PLL0,When set to 1 FW controls pll_en[0] value (pll0 is Tcpu in Skyhawk)" "0,1"
newline
bitfld.long 0xC 1. "DIS_APU_PLL_EN1,When set to 1 apu_pll_en[1]=0 (pll1 is Tsoc in Skyhawk)" "0,1"
newline
bitfld.long 0xC 0. "DIS_APU_PLL_EN0,When set to 1 apu_pll_en[0]=0 (pll0 is Tcpu in Skyhawk)" "0,1"
line.long 0x10 "PLL_DIS_CNT,PLL Disable Count"
hexmask.long.word 0x10 0.--15. 1. "PLL_DIS_CNT,PLL disable count in reference clocks"
line.long 0x14 "STABLE_CNT,Stable Count"
hexmask.long.word 0x14 16.--31. 1. "PLL_STABLE_CNT,PLL stable count in sleep clocks after APU asserts pll_en"
newline
hexmask.long.word 0x14 0.--15. 1. "XOSC_STABLE_CNT,XOSC stable count in sleep clocks after APU asserts xosc_en"
line.long 0x18 "CPU1_HOST_WKUP_MASK,CPU1 Host Wakeup Mask"
hexmask.long.word 0x18 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x1C "CPU1_HOST_WKUP_POL,CPU1 Host Wakeup Polarity"
hexmask.long.word 0x1C 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
rgroup.long 0x24++0xB
line.long 0x0 "CAL_WIN_CNT,Calibration Window Count"
hexmask.long 0x0 0.--31. 1. "APU_CAL_WIN_CNT,Number of calibration clocks elapsed during calibration window"
line.long 0x4 "AUTO_10US,Auto 10us"
hexmask.long 0x4 0.--31. 1. "APU_AUTO_10US,auto alarm value loaded during auto calibration"
line.long 0x8 "ACC_CNT,Accumulation Count"
hexmask.long 0x8 0.--31. 1. "APU_ACC_CNT,number of sleep clocks elapsed during the calibration window"
group.long 0x30++0x3
line.long 0x0 "CAL_WIN_SIZE,Calibration Window Size"
hexmask.long 0x0 0.--31. 1. "APU_CAL_WIN_SIZE,calibration window size in number of calibration clocks."
rgroup.long 0x34++0x7
line.long 0x0 "SLP_CLK_TIMER,Sleep Clock Timer"
hexmask.long 0x0 0.--31. 1. "APU_SLP_CLK_TIMER,reads back the current value of the free running sleep clock counter."
line.long 0x4 "STATUS_RD,Status Read"
hexmask.long.word 0x4 16.--31. 1. "HOST_WKUP_AFTER_MASK,Host Wakeup After Mask"
newline
hexmask.long.byte 0x4 12.--15. 1. "APU_SLEEP_FSM_STATE,APU Sleep FSM State"
newline
bitfld.long 0x4 11. "APU_SOC_CLK_EN1,APU SoC Clock Enable 1" "0,1"
newline
bitfld.long 0x4 10. "APU_SOC_CLK_EN2,APU SoC Clock Enable 2" "0,1"
newline
bitfld.long 0x4 9. "APU_SOC_CLK_EN3,APU SoC Clock Enable 3" "0,1"
newline
bitfld.long 0x4 8. "APU_SYS_CLK_EN,APU System Clock Enable" "0,1"
newline
bitfld.long 0x4 7. "APU_MAC_CLK_EN1,APU MAC Clock Enable 1" "0,1"
newline
bitfld.long 0x4 6. "APU_BT_CLK_EN,APU Bluetooth Clock Enable" "0,1"
newline
bitfld.long 0x4 5. "APU_MAC_CLK_EN2,APU MAC Clock Enable 2" "0,1"
newline
bitfld.long 0x4 4. "APU_BT2_CLK_EN,APU Bluetooth2 Clock Enable" "0,1"
newline
bitfld.long 0x4 3. "APU_XOSC_STABLE,APU XOSC Stable" "0,1"
newline
bitfld.long 0x4 2. "APU_PLL_STABLE_1,APU PLL Stable[1]" "0,1"
newline
bitfld.long 0x4 1. "APU_PLL_STABLE_0,T1 PLL stable" "0,1"
newline
bitfld.long 0x4 0. "CALIBRATION_STATUS,Calibration Status" "0,1"
group.long 0x3C++0x7
line.long 0x0 "STABLE_CNT2,Stable Count 2"
hexmask.long.word 0x0 0.--15. 1. "PLL2_STBL_CNT,T3 stable count in reference clocks"
line.long 0x4 "DYN_PLL_MASK,Dynamic PLL Mask"
hexmask.long.word 0x4 16.--31. 1. "HOST_WKUP_PLL_REQ_MASK,When mask is 0 host_wkup is treated as pll_req if soc_use_ref_only = 0"
newline
bitfld.long 0x4 14. "FULL_SLP_MASK,Full Sleep Mask" "0,1"
newline
bitfld.long 0x4 13. "GEN_TIMER_WKUP_PLL_REQ_MASK,When mask is 0 gen_timer_wkup_wkup is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 12. "SD_CLK_SWITCH_OK_MASK,SD Clock Switch Ok Mask" "0,1"
newline
bitfld.long 0x4 11. "CPU2_CP15_PLL_REQ_MASK,When mask is 0 !cpu2_cp15_sleep is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 10. "BLE_SLP_RDY_PLL_REQ_MASK,When mask is 0 !ble_slp_rdy is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 9. "BT_SLP_RDY_PLL_REQ_MASK,When mask is 0 !bt_slp_rdy is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 8. "BT_CLK_REQ_PLL_REQ_MASK,When mask is 0 bt_clk_req is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 7. "BT_AES_CLK_REQ_MASK,When mask is 0 bt_aes_clk_req is treated as pll_req of bt_aes_nco_mode =0" "0,1"
newline
bitfld.long 0x4 6. "BRF_PLL_REQ_MASK,When mask =0 brf_pll_req treated as pll_req" "0,1"
newline
bitfld.long 0x4 5. "BT_PLL_REQ_MASK,When mask =0 bt_pll_req treated as pll_req" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "TESTBUS_RD1,Testbus Read 1"
hexmask.long.word 0x0 16.--31. 1. "DVFS_TIMER,DVFS timer"
newline
hexmask.long.word 0x0 0.--15. 1. "TIMER_CNTR,DVFS internal counter"
line.long 0x4 "TESTBUS_RD2,Testbus Read 2"
hexmask.long 0x4 0.--31. 1. "APU_TESTBUS_RD2,Last 8 FSM state changes are stored in the register"
group.long 0x4C++0x13
line.long 0x0 "GENERIC_TIMER_CNT,Generic Timer Count"
hexmask.long 0x0 0.--31. 1. "GENERIC_TIMER_CNT,Generic Timer Count"
line.long 0x4 "CPU1_HOST_WKUP_CTRL,CPU1 Host Wakeup Control"
hexmask.long.word 0x4 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x4 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0x8 "DYN_PLL_CLK_EXT_CTRL,Dynamic PLL Clock Ext Control"
bitfld.long 0x8 31. "BT_AES_PLL_EXT_EN,Bluetooth AES PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 30. "BT_AES_CLK_EXT_EN,BLuetooth AES Clock Ext Enable" "0,1"
newline
bitfld.long 0x8 29. "BT2_AES_PLL_EXT_EN,Bluetooth2 AES PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 28. "BT2_AES_CLK_EXT_EN,BLuetooth2 AES Clock Ext Enable" "0,1"
newline
bitfld.long 0x8 12. "CPU3_INACTIVE_EXT_EN,CPU3 Inactive Ext Enable" "0,1"
newline
bitfld.long 0x8 11. "CPU3_PLL_EXT_EN,CPU3 PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 10. "DVFS_T1_EXT_EN,DVFS T1 Ext Enable" "0,1"
newline
bitfld.long 0x8 9. "T3_EXT_EN,T3 Ext Enable" "0,1"
newline
bitfld.long 0x8 8. "T1_EXT_EN,T1 Ext Enable" "0,1"
newline
bitfld.long 0x8 7. "CPU2_INACTIVE_EXT_EN,CPU2 Inactive Ext Enable" "0,1"
newline
bitfld.long 0x8 6. "CPU2_PLL_EXT_EN,CPU2 PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 5. "CPU1_INACTIVE_EXT_EN,CPU1 Inactive Ext Enable" "0,1"
newline
bitfld.long 0x8 4. "CPU1_PLL_EXT_EN,CPU1 PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 2. "SOC_CLK3_EXT_EN,SoC Clock 3 Ext Enable" "0,1"
newline
bitfld.long 0x8 1. "SOC_CLK2_EXT_EN,SoC Clock 2 Ext Enable" "0,1"
newline
bitfld.long 0x8 0. "SOC_CLK1_EXT_EN,SoC Clock 1 Ext Enable" "0,1"
line.long 0xC "GENERIC_SLP_START_VAL,Generic Sleep Start Value"
hexmask.long 0xC 0.--31. 1. "GENERIC_SLP_START_VAL,Generic Sleep Start Value"
line.long 0x10 "DLY_HOST_CTRL,Delay Host Control"
hexmask.long.tbyte 0x10 8.--31. 1. "DLY_HOST_WKUP_CNT,Number of sleep clocks to delay host wakeup interrupt"
newline
bitfld.long 0x10 7. "RST_HOST_WKUP_CNT,Reset Host Wakeup Count" "0,1"
newline
hexmask.long.byte 0x10 3.--6. 1. "HOST_WKUP_SEL,selects which host wakeup to be delayed out of 16 hosts"
newline
bitfld.long 0x10 0. "DLY_HOST_WKUP_EN,Delay Host Wakeup Enable" "0,1"
rgroup.long 0x60++0x3
line.long 0x0 "HOST_WKUP_CNT,Host Wakeup Count"
hexmask.long.tbyte 0x0 0.--23. 1. "HOST_WKUP_DLY_CNT,Host Wakeup Delay Count"
group.long 0x64++0x13
line.long 0x0 "CPU2_HOST_WKUP_MASK,CPU2 Host Wakeup Mask"
hexmask.long.word 0x0 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x4 "CPU2_HOST_WKUP_POL,CPU2 Host Wakeup Polarity"
hexmask.long.word 0x4 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
line.long 0x8 "CPU2_HOST_WKUP_CTRL,CPU2 Host Wakeup Control"
hexmask.long.word 0x8 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x8 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0xC "CPU2_CTRL,CPU2 Control"
bitfld.long 0xC 16.--18. "APU_SUBSYS2_HOST,APU Subsystem 2 Host" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 5. "GENERIC_TIMER_EN2,Generic Timer Enable 2" "0,1"
newline
bitfld.long 0xC 4. "SOC_USE_REF_ONLY,SoC Use Ref Only" "0,1"
newline
bitfld.long 0xC 3. "CPU2_CP15_SLP_BYPASS_EN,CPU2 CP15 Sleep Bypass Enable" "0,1"
newline
bitfld.long 0xC 2. "CPU2_CP15_SLP_BYPASS_VAL,CPU2 CP15 Sleep Bypass Value" "0,1"
newline
bitfld.long 0xC 0. "CPU2_MSG_RDY_MASK,CPU2 Message Ready Mask" "0,1"
line.long 0x10 "WLAN_PWR_CTRL_DLY,Wlan domain FSM Power Control Delay"
hexmask.long 0x10 0.--31. 1. "PWR_CTRL_DLY,Wlan domain FSM Power Control Delay"
rgroup.long 0x78++0x3
line.long 0x0 "STATUS2,Status 2"
bitfld.long 0x0 31. "CPU1_APU_PD,CPU1 to APU powerdown" "0,1"
newline
bitfld.long 0x0 30. "AMU3_CP15_SLEEP,CPU3 CP15 Sleep" "0,1"
newline
bitfld.long 0x0 29. "AMU2_CP15_SLEEP,CPU2 CP15 Sleep" "0,1"
newline
bitfld.long 0x0 28. "AMU1_CP15_SLEEP,CPU1 CP15 Sleep" "0,1"
newline
bitfld.long 0x0 27. "APU_INTR_WLAN_WAKEUP1,APU wlan1 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 26. "APU_INTR_WLAN_WAKEUP2,APU wlan2 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 25. "APU_DVFS_CLK_SEL,APU DVFS Clock Select" "0,1"
newline
bitfld.long 0x0 24. "BT2_CLK_REQ,BT2 clk req" "0,1"
newline
bitfld.long 0x0 23. "BT_CLK_REQ,BT clk req" "0,1"
newline
bitfld.long 0x0 22. "BCA_SLNA_ON,BCA SLNA On" "0,1"
newline
bitfld.long 0x0 21. "BCA_CLK_EN,APU BCA Clock Enable" "0,1"
newline
bitfld.long 0x0 20. "BCA_CLK_REQ,BCA Clock Request" "0,1"
newline
bitfld.long 0x0 19. "PCIE_XP_REQ,PCIe XP req" "0,1"
newline
bitfld.long 0x0 18. "PCIE_P_REQ,PCIe P req" "0,1"
newline
bitfld.long 0x0 17. "APU_SOC_CAU_LDO_XOSC_EN,APU SoC CAU LOD XOSC Enable" "0,1"
newline
bitfld.long 0x0 16. "APU_CAU_BT_ACTIVE,APU CAU Bluetooth Active" "0,1"
newline
bitfld.long 0x0 15. "APU_WL_RF_CLK_EN2,WLAN RFU1 clk enable" "0,1"
newline
bitfld.long 0x0 14. "APU_WL_RF_CLK_EN1,WLAN RFU1 clk enable" "0,1"
newline
bitfld.long 0x0 13. "APU_BBUD_CLK_EN2,bbud1 clk enable" "0,1"
newline
bitfld.long 0x0 12. "APU_BBUD_CLK_EN1,bbud2 clk enable" "0,1"
newline
bitfld.long 0x0 11. "APU_INTR_BT2_WAKEUP,APU BT2 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 10. "APU_INTR_BT_WAKEUP,APU BT2 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 9. "APU_BRF2_CLK_EN,BRF2 clk enable" "0,1"
newline
bitfld.long 0x0 8. "APU_BRF_CLK_EN,BRF clk enable" "0,1"
newline
bitfld.long 0x0 7. "APU_BT2_AES_CLK_SEL,BT2 AES clk select" "0,1"
newline
bitfld.long 0x0 6. "APU_BT_AES_CLK_SEL,BT AES clk select" "0,1"
newline
bitfld.long 0x0 5. "APU_BT2_AES_CLK_EN,BT2 AES Clk enable" "0,1"
newline
bitfld.long 0x0 4. "APU_BT_AES_CLK_EN,BT AES Clk enable" "0,1"
newline
bitfld.long 0x0 3. "LMU_G2BIST_FINISH,LMU G2BIST finish" "0,1"
newline
bitfld.long 0x0 2. "CPU3_MSG_RDY_INT,CPU3 Message Ready" "0,1"
newline
bitfld.long 0x0 1. "CPU2_MSG_RDY_INT,CPU2 Message Ready" "0,1"
newline
bitfld.long 0x0 0. "CPU1_MSG_RDY_INT,CPU1 Message Ready" "0,1"
group.long 0x7C++0xB
line.long 0x0 "WLAN_PWR_CTRL_DLY2,Wlan domain FSM Power Control Delay 2"
hexmask.long 0x0 0.--31. 1. "PWR_CTRL_DLY2,WLAN domain FSM power control delay 2"
line.long 0x4 "WL_CTRL,WLAN Control"
bitfld.long 0x4 31. "WL_HOST_SLP_RDY,WLAN Host Sleep Ready" "0,1"
newline
bitfld.long 0x4 25. "WLAN_USE_UNSYNC_PWR_LVL,WLAN Use Unsync Power Level" "0,1"
newline
bitfld.long 0x4 24. "FW_FORCE_WL_PWRUP,FW Force WLAN Powerup" "0,1"
newline
bitfld.long 0x4 22. "APU_WLAN_RF_MUX_SEL,APU WLAN RF Mux Select" "0,1"
newline
bitfld.long 0x4 21. "APU_TSF_AUTO_UPDATE,APU TSF Auto Update" "0,1"
newline
hexmask.long.byte 0x4 16.--20. 1. "APU_TSF_UPD_CNT,APU TSF Update Count"
newline
bitfld.long 0x4 15. "APU_FW_RST_PE,APU FW Reset PE" "0,1"
newline
bitfld.long 0x4 10. "USE_WL_PWR_RDY_FOR_WLRF_CLK,Use WLAN Power Ready for WL RF Clock" "0,1"
newline
bitfld.long 0x4 9. "WL_USE_NOM_PWR_BYP,WLAN Use Nominal Power Bypass" "0,1"
newline
bitfld.long 0x4 7. "USE_WL_INTR_SLP,Use WLAN Interrupt Sleep" "0,1"
newline
bitfld.long 0x4 6. "APU_WKUP_WLRF_RX,APU Wakeup WL RF Rx" "0,1"
newline
bitfld.long 0x4 5. "IDLE2ISO_DLY_EN,Delay from idle to iso to ensure delay from bbud_non_udr_rst_b =0 to wlan_iso_en = 1" "0,1"
newline
bitfld.long 0x4 2. "WL_SLP_RDY_FW,WLAN Sleep Ready Firmware" "0,1"
newline
bitfld.long 0x4 1. "WL_SLP_RDY_MASK,WLAN Sleep Ready Mask" "0,1"
newline
bitfld.long 0x4 0. "WL_SLP_RDY,WLAN Sleep Ready" "0,1"
line.long 0x8 "WL_WKUP_MASK,WLAN Wakeup Mask"
hexmask.long.word 0x8 16.--31. 1. "WL_HOST_MAP,WLAN Host Map"
newline
bitfld.long 0x8 12. "IHB_WL_XPP_DYNPLL_REQ_MASK,When mask = 0 ihb_wl_xpp_req is treated as pll_req" "0,1"
newline
bitfld.long 0x8 11. "WL_SLP_RDY_DYNPLL_REQ_MASK,When mask = 0 !wl_slp_rdy is treated as pll_req" "0,1"
newline
bitfld.long 0x8 10. "WL_TIMER_DYNPLL_REQ_MASK,When mask = 0 wlan_timer_xpp req is treated as pll_req" "0,1"
newline
bitfld.long 0x8 9. "WL_HOST_DYNPLL_REQ_MASK,When mask = 0 wlan_host_wkup is treated as pll_req" "0,1"
newline
bitfld.long 0x8 8. "WL_RF_PLL_DYNPLL_REQ_MASK,When mask = 0 wl_rf_pll_req is treated as pll_req" "0,1"
newline
bitfld.long 0x8 3. "BCA_MWS_WKUP_XP_MASK,BCA MWS Wakeup XP Mask" "0,1"
newline
bitfld.long 0x8 2. "WL_RF_PLL_REQ_MASK,WLAN RF PLL Request Mask" "0,1"
newline
bitfld.long 0x8 1. "BBUD_T2_PLL_REQ_MASK,BBUD T2 PLL Request Mask" "0,1"
newline
bitfld.long 0x8 0. "WL_BCN_TIMER_WKUP_MASK,WLAN Beacon Timer Wakeup Mask" "0,1"
rgroup.long 0x88++0x7
line.long 0x0 "WL_STATUS,WLAN Status"
bitfld.long 0x0 31. "BCA_CLK_REQ,BCA Clock Request" "0,1"
newline
bitfld.long 0x0 30. "BBUD_T2_PLL_REQ,BBUD T2 PLL Request" "0,1"
newline
bitfld.long 0x0 29. "WLRF_PLL_REQ,WL RF PLL Request" "0,1"
newline
bitfld.long 0x0 28. "TIMER_WAKEUP,Timer Wakeup" "0,1"
newline
bitfld.long 0x0 27. "TIMER_XPP_WAKEUP,Timer XPP Wakeup" "0,1"
newline
bitfld.long 0x0 26. "WL_TIMER_INTR,WLAN Timer Interrupt" "0,1"
newline
bitfld.long 0x0 25. "WLAN_HOST_WKUP,WLAN Host Wakeup" "0,1"
newline
bitfld.long 0x0 24. "WL_HOST_INTR_REF,WLAN Host Interrupt Reference" "0,1"
newline
bitfld.long 0x0 23. "WL_PWR_RDY,WLAN Power Ready" "0,1"
newline
bitfld.long 0x0 22. "SOC_VOL_REACHED,SoC Volume Reached" "0,1"
newline
bitfld.long 0x0 21. "WLAN_VOL_REACHED,WLAN Volume Reached" "0,1"
newline
bitfld.long 0x0 20. "APU_WLAN_SRAM_PD,APU WLAN SRAM Enable" "0,1"
newline
bitfld.long 0x0 19. "APU_WLAN_ISO_EN,APU WLAN ISO Enable" "0,1"
newline
bitfld.long 0x0 18. "APU_WLAN_CLK_DIV_RSTB,APU WLAN Clock Div RSTb" "0,1"
newline
bitfld.long 0x0 17. "APU_WLAN_UDR_FIREWALL_B,APU WLAN UDR Firewall b" "0,1"
newline
bitfld.long 0x0 16. "APU_WLAN_SWITCH_PD,APU WLAN Switch Pd" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "APU_WL_ST,APU WLAN St"
newline
bitfld.long 0x0 10. "APU_BBUD_NON_UDR_RST_B,APU BBUD non-UDR RSTb" "0,1"
newline
bitfld.long 0x0 9. "APU_RTDP_WU_RSTB,APU RTDP WU RSTb" "0,1"
newline
bitfld.long 0x0 8. "BCA_MWS_WKUP_XP,BCA MWS Wakeup XP" "0,1"
newline
bitfld.long 0x0 7. "APU_PLL3_EN,APU PLL3 Enable" "0,1"
newline
bitfld.long 0x0 6. "APU_PLL1_EN,APU PLL1 Enable" "0,1"
newline
bitfld.long 0x0 4.--5. "APU_WL_RF_CTRL,APU WLAN RF Control for PE1/PE2" "0,1,2,3"
newline
bitfld.long 0x0 3. "APU_WL_SLP_RDY_AFTER_MASK,APU WLAN Sleep Ready After Mask" "0,1"
newline
bitfld.long 0x0 2. "APU_WL_RF_CLK_EN,APU WLAN Ref Clock Enable" "0,1"
newline
bitfld.long 0x0 1. "APU_BBUD_CLK_EN,APU BBUD Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_MAC_CLK_EN,APU MAC Clock Enable" "0,1"
line.long 0x4 "WL_ALARM_RD,WLAN Alarm Readback"
hexmask.long 0x4 0.--31. 1. "APU_WL_ALARM_RD,reads back current beacon timer alarm value"
group.long 0x90++0x27
line.long 0x0 "WL_BCN_XP_ALARM,WLAN Beacon Alarm"
hexmask.long 0x0 0.--31. 1. "WL_BCN_XP_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock and power"
line.long 0x4 "WL_BCN_INTR_ALARM,WLAN Beacon Interrupt Alarm"
hexmask.long 0x4 0.--31. 1. "WL_BCN_INTR_ALARM,number of ref clocks after WLAN beacon timer request to firmware wakeup"
line.long 0x8 "WL_HOST_INTR_ALARM,WLAN Host Interrupt Alarm"
hexmask.long 0x8 0.--31. 1. "WL_HOST_INTR_ALARM,number of ref clocks after WLAN host request to firmware wakeup"
line.long 0xC "WL_BCN_PLL_ALARM,WLAN Beacon PLL Alarm"
hexmask.long 0xC 0.--31. 1. "WL_BCN_PLL_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock power and PLL"
line.long 0x10 "TSF_REF_FACTOR,TSF Reference Factor"
hexmask.long.tbyte 0x10 0.--18. 1. "TSF_REF_FACTOR,number of 1us in 1 reference clock"
line.long 0x14 "TSF_SLEEP_FACTOR,TSF Sleep Factor"
hexmask.long 0x14 0.--27. 1. "TSF_SLEEP_FACTOR,number of 1us in 1 sleep clock"
line.long 0x18 "BBUD_UDR_ISO_CNT,BBUD UDR ISO Count"
hexmask.long.word 0x18 16.--28. 1. "BBUD_CLK_ASSERT_CNT,number of reference clocks before bbud_iso_en de-assertion after bbud_non_udr_rst de-asserts"
newline
hexmask.long.word 0x18 0.--12. 1. "BBUD_UDR_ASSERT_CNT,number of reference clocks before bbud_non_udr_rst de-assertion after bbud_clk_en is asserted"
line.long 0x1C "WL_DVFS_CTRL,WLAN DVFS Control"
hexmask.long.byte 0x1C 0.--6. 1. "WLAN_VOL_VAL,WLAN Vol Value"
line.long 0x20 "WL_CTRL2,WLAN Control 2"
bitfld.long 0x20 31. "WL_HOST_SLP_RDY,WLAN Host Sleep Ready" "0,1"
newline
bitfld.long 0x20 25. "WLAN_USE_UNSYNC_PWR_LVL,WLAN Use Unsync Power Level" "0,1"
newline
bitfld.long 0x20 24. "FW_FORCE_WL_PWRUP,FW Force WLAN Powerup" "0,1"
newline
bitfld.long 0x20 22. "APU_WLAN_RF_MUX_SEL,APU WLAN RF Mux Select" "0,1"
newline
bitfld.long 0x20 21. "APU_TSF_AUTO_UPDATE,APU TSF Auto Update" "0,1"
newline
hexmask.long.byte 0x20 16.--20. 1. "APU_TSF_UPD_CNT,APU TSF Update Count"
newline
bitfld.long 0x20 15. "APU_FW_RST_PE,APU FW Reset PE" "0,1"
newline
bitfld.long 0x20 10. "USE_WL_PWR_RDY_FOR_WLRF_CLK,Use WLAN Power Ready for WL RF Clock" "0,1"
newline
bitfld.long 0x20 9. "WL_USE_NOM_PWR_BYP,Use nom_pwr_lvl from dvfs for wl_pwr_lvl_reached" "0,1"
newline
bitfld.long 0x20 7. "USE_WL_INTR_SLP,Use WLAN Interrupt Sleep" "0,1"
newline
bitfld.long 0x20 6. "APU_WKUP_WLRF_RX,APU Wakeup WL RF Rx" "0,1"
newline
bitfld.long 0x20 5. "IDLE2ISO_DLY_EN,Delay from idle to iso to ensure delay from bbud_non_udr_rst_b =0 to wlan_iso_en = 1" "0,1"
newline
bitfld.long 0x20 2. "WL_SLP_RDY_FW,WLAN Sleep Ready Firmware" "0,1"
newline
bitfld.long 0x20 1. "WL_SLP_RDY_MASK,WLAN Sleep Ready Mask" "0,1"
newline
bitfld.long 0x20 0. "WL_SLP_RDY,WLAN Sleep Ready" "0,1"
line.long 0x24 "WL_WKUP_MASK2,WLAN Wakeup Mask 2"
hexmask.long.word 0x24 16.--31. 1. "WL_HOST_MAP,WLAN Host Map"
newline
bitfld.long 0x24 12. "IHB_WL_XPP_DYNPLL_REQ_MASK,When mask = 0 ihb_wl_xpp_req is treated as pll_req" "0,1"
newline
bitfld.long 0x24 11. "WL_SLP_RDY_DYNPLL_REQ_MASK,When mask = 0 !wl_slp_rdy is treated as pll_req" "0,1"
newline
bitfld.long 0x24 10. "WL_TIMER_DYNPLL_REQ_MASK,When mask = 0 wlan_timer_xpp req is treated as pll_req" "0,1"
newline
bitfld.long 0x24 9. "WL_HOST_DYNPLL_REQ_MASK,When mask = 0 wlan_host_wkup is treated as pll_req" "0,1"
newline
bitfld.long 0x24 8. "WL_RF_PLL_DYNPLL_REQ_MASK,When mask = 0 wl_rf_pll_req is treated as pll_req" "0,1"
newline
bitfld.long 0x24 3. "BCA_MWS_WKUP_XP_MASK,BCA MWS Wakeup XP Mask" "0,1"
newline
bitfld.long 0x24 2. "WL_RF_PLL_REQ_MASK,WLAN RF PLL Request Mask" "0,1"
newline
bitfld.long 0x24 1. "BBUD_T2_PLL_REQ_MASK,BBUD T2 PLL Request Mask" "0,1"
newline
bitfld.long 0x24 0. "WL_BCN_TIMER_WKUP_MASK,WLAN Beacon Timer Wakeup Mask" "0,1"
rgroup.long 0xB8++0x7
line.long 0x0 "WL_STATUS2,WLAN Status 2"
bitfld.long 0x0 31. "BCA_CLK_REQ,BCA Clock Request" "0,1"
newline
bitfld.long 0x0 30. "BBUD_T2_PLL_REQ,BBUD T2 PLL Request" "0,1"
newline
bitfld.long 0x0 29. "WLRF_PLL_REQ,WLAN RF PLL Request" "0,1"
newline
bitfld.long 0x0 28. "TIMER_WAKEUP,Timer Wakeup" "0,1"
newline
bitfld.long 0x0 27. "TIMER_XPP_WAKEUP,Timer XPP Wakeup" "0,1"
newline
bitfld.long 0x0 26. "WL_TIMER_INTR,WLAN Timer Interrupt" "0,1"
newline
bitfld.long 0x0 25. "WLAN_HOST_WKUP,WLAN Host Wakeup" "0,1"
newline
bitfld.long 0x0 24. "WL_HOST_INTR_REF,WLAN Host Interrupt Reference" "0,1"
newline
bitfld.long 0x0 23. "WL_PWR_RDY,WLAN Power Ready" "0,1"
newline
bitfld.long 0x0 22. "SOC_VOL_REACHED,SoC Volume Reached" "0,1"
newline
bitfld.long 0x0 21. "WLAN_VOL_REACHED,WLAN Volume Reached" "0,1"
newline
bitfld.long 0x0 20. "APU_WLAN_SRAM_PD,APU WLAN SRAM Pd" "0,1"
newline
bitfld.long 0x0 19. "APU_WLAN_ISO_EN,APU WLAN ISO Enable" "0,1"
newline
bitfld.long 0x0 18. "APU_WLAN_CLK_DIV_RSTB,APU WLAN Clock Div RSTb" "0,1"
newline
bitfld.long 0x0 17. "APU_WLAN_UDR_FIREWALL_B,APU WLAN UDR Firewall b" "0,1"
newline
bitfld.long 0x0 16. "APU_WLAN_SWITCH_PD,APU WLAN Switch Pd" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "APU_WL_ST,APU WLAN St"
newline
bitfld.long 0x0 10. "APU_BBUD_NON_UDR_RST_B,APU BBUD non-UDR RSTb" "0,1"
newline
bitfld.long 0x0 9. "APU_RTDP_WU_RSTB,APU RTDP WU RSTb" "0,1"
newline
bitfld.long 0x0 8. "BCA_MWS_WKUP_XP,BCA MWS Wakeup XP" "0,1"
newline
bitfld.long 0x0 7. "APU_PLL3_EN,APU PLL3 Enable" "0,1"
newline
bitfld.long 0x0 6. "APU_PLL1_EN,APU PLL1 Enable" "0,1"
newline
bitfld.long 0x0 4.--5. "APU_WL_RF_CTRL,APU WLAN RF Control" "0,1,2,3"
newline
bitfld.long 0x0 3. "APU_WL_SLP_RDY_AFTER_MASK,APU WLAN Sleep Ready After Mask" "0,1"
newline
bitfld.long 0x0 2. "APU_WL_RF_CLK_EN,APU WLAN Ref Clock Enable" "0,1"
newline
bitfld.long 0x0 1. "APU_BBUD_CLK_EN,APU BBUD Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_MAC_CLK_EN,APU MAC Clock Enable" "0,1"
line.long 0x4 "WL_ALARM_RD2,WLAN Alarm Readback 2"
hexmask.long 0x4 0.--31. 1. "APU_WL_ALARM_RD,reads back current beacon timer alarm value"
group.long 0xC0++0x13
line.long 0x0 "WL_BCN_XP_ALARM2,WLAN Beacon XP Alarm 2"
hexmask.long 0x0 0.--31. 1. "WL_BCN_XP_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock and power"
line.long 0x4 "WL_BCN_INTR_ALARM2,WLAN Beacon Interrupt Alarm 2"
hexmask.long 0x4 0.--31. 1. "WL_BCN_INTR_ALARM,number of ref clocks after WLAN beacon timer request to firmware wakeup"
line.long 0x8 "WL_HOST_INTR_ALARM2,WLAN Host Interrupt Alarm 2"
hexmask.long 0x8 0.--31. 1. "WL_HOST_INTR_ALARM,number of ref clocks after WLAN host request to firmware wakeup"
line.long 0xC "WL_BCN_PLL_ALARM2,WLAN Beacon PLL Alarm 2"
hexmask.long 0xC 0.--31. 1. "WL_BCN_PLL_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock power and PLL"
line.long 0x10 "WLCOMN_PWR_CTRL,WLAN Comm Powerup Control"
hexmask.long.word 0x10 16.--31. 1. "WLCOMN_PWRUP_CNT,number of reference clocks after soc_pwr_rdy to push wlcomn power up"
newline
bitfld.long 0x10 15. "CPU_VINITHI,CPU to CPU Delay" "0,1"
newline
bitfld.long 0x10 10. "IDLE2ISO_DLY_EN,wlcomn FSM state delay enable. When 1 use wlcomn_pwr_ctrl_dly and wlcomn_pwr_ctrl_dly2. When 0 no delay." "0,1"
newline
bitfld.long 0x10 9. "USE_DEEPSLEEP_FOR_SYS_CLK_EN,Use Deep Sleep for SYS_CLK Enable" "0,1"
newline
bitfld.long 0x10 8. "USE_WLCOMN_PWR_RDY_FOR_WL,Use WL COMM Power Ready fro WLAN" "0,1"
newline
hexmask.long.byte 0x10 0.--7. 1. "WLCOMN_UDR_ASSERT_CNT,WL COMM UDR Assert Count"
rgroup.long 0xD4++0x3
line.long 0x0 "WLCOMN_STATUS,WLAN Comm Status"
bitfld.long 0x0 19. "APU_WLCOMN_ISO_EN,APU WLAN COMN ISO Enable" "0,1"
newline
bitfld.long 0x0 18. "APU_WLCOMN_CLK_DIV_RSTB,APU WLAN COMN Clock Div RSTb" "0,1"
newline
bitfld.long 0x0 17. "APU_WLCOMN_UDR_FIREWALL_B,APU WLAN COMN UDR Firewall b" "0,1"
newline
bitfld.long 0x0 16. "APU_WLCOMN_SWITCH_PD,APU WLAN COMN Switch Pd" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "APU_WLCOMN_ST,APU WLAN COMN St"
newline
bitfld.long 0x0 11. "ENTER_CPU1_SUB_DSLP_REFCK,WLCOMN FSM enter ip power down" "0,1"
newline
bitfld.long 0x0 10. "START_WLCOMN_WKUP_REFCK,WLCOMN FSM start ip wake up" "0,1"
group.long 0xE0++0x7
line.long 0x0 "BT_CTRL,Bluetooth Control"
bitfld.long 0x0 31. "BT_HOST_SLP_RDY,Bluetooth Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 30. "BT_PLL_SYNC_MODE_SEL,Bluetooth PLL Sync Mode Select" "0,1"
newline
bitfld.long 0x0 29. "BT_CLK_SYNC_MODE_SEL0,Bluetooth Clock Sync Mode Select 0" "0,1"
newline
bitfld.long 0x0 28. "BRF_CLK_SYNC_MODE_SEL,BRF Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x0 27. "USE_GLITCH_FREE_BT_CLK_REQ,Use Glitch-Free Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x0 26. "BT_CLK_SYNC_MODE_SEL1,Bluetooth Clock Sync Mode Select 1" "0,1"
newline
bitfld.long 0x0 7. "USE_BT_INTR_SLP,Use Bluetooth interrupt Sleep" "0,1"
newline
bitfld.long 0x0 3. "BTU_CLK_NCO_MODE_SEL_EN,0- disable the btu_clk_nco_mode from CIU2 keep the bt_clk_req as XP wakeup source" "0,1"
newline
bitfld.long 0x0 2. "BT_SLP_RDY_FW,Bluetooth Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "BT_SLP_RDY_MASK,Bluetoot Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "BT_SLP_RDY,Bluetooth Sleep Ready" "0,1"
line.long 0x4 "BT_WKUP_MASK,Bluetooth Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "BT_HOST_MAP,Bluetooth Host Map"
newline
bitfld.long 0x4 5. "BRF_PLL_REQ_MASK,BRF PLL Request Mask" "0,1"
newline
bitfld.long 0x4 4. "BT_PLL_REQ_MASK,Bluetooth PLL Request Mask" "0,1"
newline
bitfld.long 0x4 3. "BT_INTR_MASK,Bluetooth Interrupt Mask" "0,1"
newline
bitfld.long 0x4 2. "BT_WB_ACTIVE_REQ_MASK,Bluetooth WB Active Request Mask" "0,1"
newline
bitfld.long 0x4 1. "BT_CLK_REQ_MASK,Bluetooth Clock Request Mask" "0,1"
newline
bitfld.long 0x4 0. "BCA_CLK_REQ_MASK,BCA Clock Request Mask" "0,1"
rgroup.long 0xE8++0x3
line.long 0x0 "BT_STATUS,Bluetooth Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup In"
newline
bitfld.long 0x0 9. "BT_WIDEBAND_ACTIVE,Bluetooth Wideband Active" "0,1"
newline
bitfld.long 0x0 8. "BRF_PLL_REQ,BRF PLL Request" "0,1"
newline
bitfld.long 0x0 7. "BT_CLK_REQ,Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x0 6. "BT_PLL_REQ,Bluetooth PLL Request" "0,1"
newline
bitfld.long 0x0 5. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 4. "BT_HOST_WKUP,Bluetooth Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "BT_ACTIVE_SLPCK,Bluetooth Active Sleep Clock" "0,1"
newline
bitfld.long 0x0 1. "APU_BRF_CLK_EN,APU BRF Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_CLK_EN,APU Bluetooth Clock Enable" "0,1"
group.long 0xEC++0xB
line.long 0x0 "BT_CKEN_CTRL,Bluetooth Clock Enable Control"
bitfld.long 0x0 5. "BT_CLK_EN_SEL,selection for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "BT_CLK_EN_VAL,control value for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "BT_CLK_EN_SEL_XOSC,selection for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "BT_CLK_EN_VAL_XOSC,control value for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "BL_CLK_EN_SEL_PWR,selection for bt_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "BT_CLK_EN_VAL_PWR,control value for bt_clk_en when power ready" "0,1"
line.long 0x4 "BT_RESRC_CTRL,Bluetooth RESRC Control"
bitfld.long 0x4 11. "FW_ALLWAKE_REQ_VAL,firmware override value when apu_bt_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FW_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FW_IPWAKE_REQ_VAL,override value when apu_bt_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FW_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FW_SB_REQ_VAL,override value when apu_bt_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FW_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FW_XP_REQ_VAL,override value when apu_bt_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FW_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FW_XOSC_REQ_VAL,override value when apu_bt_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FW_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FW_PWR_REQ_VAL,override value when apu_bt_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FW_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "BT_DVFS_CTRL,Bluetooth DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "BT_VOL_VAL,Blueooth Vol Value"
group.long 0x100++0x7
line.long 0x0 "FM_CTRL,FM Control"
bitfld.long 0x0 31. "FM_HOST_SLP_RDY,FM Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 7. "USE_FM_INTR_SLP,Use FM Interrupt Sleep" "0,1"
newline
bitfld.long 0x0 5. "FM_CLK_SYNC_MODE_SEL,FM Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x0 4. "FM_DYN_VOL_EN,FM Dynamic Vol Enable" "0,1"
newline
bitfld.long 0x0 3. "FM_PRESENT,FM Present" "0,1"
newline
bitfld.long 0x0 2. "FM_SLP_RDY_FW,FM Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "FM_SLP_RDY_MASK,FM Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "FM_SLP_RDY,FM Sleep Delay" "0,1"
line.long 0x4 "FM_WKUP_MASK,FM Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "FM_HOST_MAP,FM to host-HOST Delay"
newline
bitfld.long 0x4 2. "FM_PRESENT_MASK,FM Present Mask" "0,1"
newline
bitfld.long 0x4 1. "FM_INTR_MASK,FM Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "FM_CLK_REQ_MASK,FM Clock Request Mask" "0,1"
rgroup.long 0x108++0x3
line.long 0x0 "FM_STATUS,FM Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup Interrupt"
newline
bitfld.long 0x0 7. "FM_PRESENT,FM Present" "0,1"
newline
bitfld.long 0x0 6. "FM_CLK_REQ,FM Clock Request" "0,1"
newline
bitfld.long 0x0 5. "FM_INTR,FM Interrupt" "0,1"
newline
bitfld.long 0x0 4. "FM_HOST_WKUP,FM Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "XOSC_STABLE_REFCK,XOSC Stable Ref Clock" "0,1"
newline
bitfld.long 0x0 1. "SOC_CLK_EN2,SoC Clock Enable 2" "0,1"
newline
bitfld.long 0x0 0. "APU_FM_CLK_EN,APU FM Clock Enable" "0,1"
group.long 0x10C++0xB
line.long 0x0 "FM_CKEN_CTRL,FM Clock Enable Control"
bitfld.long 0x0 5. "FM_CLK_EN_PLL_SEL,selection for fm_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "FM_CLK_EN_PLL_VAL,control value for fm_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "FM_CLK_EN_XOSC_SEL,selection for fm_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "FM_CLK_EN_XOSC_VAL,control value for fm_clk_en when xosc is ready" "0,1"
newline
bitfld.long 0x0 1. "FM_CLK_EN_PWR_SEL,selection for fm_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "FM_CLK_EN_PWR_VAL,control value for fm_clk_en when power ready" "0,1"
line.long 0x4 "FM_RESRC_CTRL,FM RESRC Control"
bitfld.long 0x4 11. "FM_ALLWAKE_REQ_VAL,firmware override value when apu_fm_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FM_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FM_IPWAKE_REQ_VAL,override value when apu_fm_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FM_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FM_SB_REQ_VAL,override value when apu_fm_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FM_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FM_XP_REQ_VAL,override value when apu_fm_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FM_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FM_XOSC_REQ_VAL,override value when apu_fm_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FM_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FM_PWR_REQ_VAL,override value when apu_fm_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FM_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "FM_DVFS_CTRL,FM DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "FM_VOL_VAL,FM Vol Value"
group.long 0x120++0xF
line.long 0x0 "USB_PWR_CTRL_DLY,USB FSM Power Control Delay"
hexmask.long 0x0 0.--31. 1. "PWR_CTRL_DLY,USB FSM Power Control Delay"
line.long 0x4 "USB_PWR_CTRL_DLY2,USB FSM Power Control Delay 2"
hexmask.long 0x4 0.--31. 1. "PWR_CTRL_DLY2,USB FSM Power Control Delay 2"
line.long 0x8 "WLCOMN_PWR_CTRL_DLY,Wlan common domain FSM Power Control Delay"
hexmask.long 0x8 0.--31. 1. "PWR_CTRL_DLY,WLAN COMN FSM power control delay"
line.long 0xC "WLCOMN_PWR_CTRL_DLY2,Wlan common domain FSM Power Control Delay 2"
hexmask.long 0xC 0.--31. 1. "PWR_CTRL_DLY2,WLAN COMN FSM power control delay"
group.long 0x140++0x7
line.long 0x0 "BLE_CTRL,BLE Control"
bitfld.long 0x0 31. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0x0 15. "BT_AES_NCO_MODE,Bluetooth AES NCO Mode" "0,1"
newline
bitfld.long 0x0 3. "BLE_MODE_EN,BLE Mode Enable" "0,1"
newline
bitfld.long 0x0 2. "BLE_SLP_RDY_FW,BLE Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "BLE_SLP_RDY_MASK,BLE Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "BLE_SLP_RDY,BLE Sleep Ready" "0,1"
line.long 0x4 "BLE_WKUP_MASK,BLE Wakeup Mask"
bitfld.long 0x4 4. "LBC_XP_REQ_MASK,LBC XP Request Mask" "0,1"
newline
bitfld.long 0x4 3. "BT_AES_CLK_REQ_MASK,Bluetooth AES Clock Request Mask" "0,1"
rgroup.long 0x148++0x3
line.long 0x0 "BLE_STATUS,BLE Status"
bitfld.long 0x0 9. "BT_AES_CLK_REQ,Bluetooth AES Clock Request Mask" "0,1"
newline
bitfld.long 0x0 8. "LBC_XP_REQ,LBC XP Request" "0,1"
newline
bitfld.long 0x0 6. "BT_AES_NCO_MODE,Blueooth AES NCO Mode" "0,1"
newline
bitfld.long 0x0 5. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0x0 4. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 3. "T1_STABLE,T1 Delay" "0,1"
newline
bitfld.long 0x0 2. "XOSC_STABLE_REFCK,XOSC Stable Ref Clock" "0,1"
newline
bitfld.long 0x0 1. "BT_AES_CLK_SEL,Bluetooth AES Clock Select" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_AES_CLK_EN,APU Bluetooth AES Clock Enable" "0,1"
group.long 0x160++0x7
line.long 0x0 "NFC_CTRL,NFC Control"
bitfld.long 0x0 31. "NFC_HOST_SLP_RDY,NFC Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 25. "NFC_USE_UNSYNC_PWR_LVL,NFC Use Unsync Power Level" "0,1"
newline
bitfld.long 0x0 24. "FW_FORCE_NFC_PWRUP,FW Force NFC Powerup" "0,1"
newline
bitfld.long 0x0 9. "NFC_USE_NOM_PWR_BYP,Use nom_pwr_lvl from dvfs for nfc_pwr_lvl_reached" "0,1"
newline
bitfld.long 0x0 8. "NFC_USE_CPU2_SUBSLP,Use CPU2 subsystem sleep for NFC power down" "0,1"
newline
bitfld.long 0x0 7. "FW_CLR_NFC_INTR,FW Clear NFC Interrupt" "0,1"
newline
bitfld.long 0x0 5. "NFC_USE_SOC_PWR_SEQ,Use SoC power sequence for NFC as well" "0,1"
newline
bitfld.long 0x0 4. "USE_NFC_INTR_SLP,Use NFC Interrupt Sleep" "0,1"
newline
bitfld.long 0x0 3. "USE_NFC_REF_ONLY,Use NFC Reference Only" "0,1"
newline
bitfld.long 0x0 2. "NFC_SLP_RDY_FW,NFC Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "NFC_SLP_RDY_MASK,NFC Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "NFC_SLP_RDY,NFC Sleep Ready" "0,1"
line.long 0x4 "NFC_WKUP_MASK,NFC Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "NFC_HOST_MAP,NFC Host Map"
newline
bitfld.long 0x4 2. "NFC_INT_WKUP_MASK,NFC Interrupt Wakeup Mask" "0,1"
newline
bitfld.long 0x4 1. "NFC_XP_WKUP_MASK,NFC XP Wakeup Mask" "0,1"
newline
bitfld.long 0x4 0. "NFC_P_WKUP_MASK,NFC P Wakeup Mask" "0,1"
rgroup.long 0x168++0x3
line.long 0x0 "NFC_STATUS,NFC Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup Interrupt"
newline
bitfld.long 0x0 12.--14. "APU_NFC_ST,APU NFC St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "NFC_PWR_RDY,NFC Power ready" "0,1"
newline
bitfld.long 0x0 10. "SOC_VOL_REACHED,SoC Vol Reached" "0,1"
newline
bitfld.long 0x0 9. "NFC_VOL_REACHED,NFC Vol Reached" "0,1"
newline
bitfld.long 0x0 8. "APU_NFC_SRAM_PD_AON,APU NFC SRAM PD AON" "0,1"
newline
bitfld.long 0x0 7. "APU_NFC_ISO_EN_AON,APU NFC ISO Enable AON" "0,1"
newline
bitfld.long 0x0 6. "APU_NFC_CLK_DIV_RSTB_AON,APU NFC Clock Divider RSTb AON" "0,1"
newline
bitfld.long 0x0 5. "APU_NFC_UDR_FIREWALL_B_AON,APU NFC UDR Firewall B AON" "0,1"
newline
bitfld.long 0x0 4. "APU_NFC_SWITCH_PD_AON,APU NFC Switch PD AON" "0,1"
newline
bitfld.long 0x0 3. "NFC_P_REQ,NFC P Req" "0,1"
newline
bitfld.long 0x0 2. "NFC_XP_REQ,NFC XP Req" "0,1"
newline
bitfld.long 0x0 1. "NFC_INT,NFC Interrupt" "0,1"
newline
bitfld.long 0x0 0. "APU_NFC_AHBCLK_EN,APU NFC AHB Clock Enable" "0,1"
group.long 0x16C++0xB
line.long 0x0 "NFC_CKEN_CTRL,NFC Clock Enable Control"
bitfld.long 0x0 5. "NFC_CLK_EN_PLL_SEL,selection for nfc_cm3_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "NFC_CLK_EN_PLL_VAL,NFC Clock Enable PLL Value" "0,1"
newline
bitfld.long 0x0 3. "NFC_CLK_EN_XOSC_SEL,selection for nfc_cm3_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "NFC_CLK_EN_XOSC_VAL,Control value for nfc_cm3_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "NFC_CLK_EN_PWR_SEL,selection for nfc_cm3_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "NFC_CLK_EN_PWR_VAL,control value for nfc_clk_en when power ready" "0,1"
line.long 0x4 "NFC_RESRC_CTRL,NFC RESRC Control"
bitfld.long 0x4 11. "NFC_ALLWAKE_REQ_VAL,firmware override value when apu_nfc_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "NFC_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "NFC_IPWAKE_REQ_VAL,override value when apu_nfc_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "NFC_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "NFC_SB_REQ_VAL,override value when apu_nfc_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "NFC_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "NFC_XP_REQ_VAL,override value when apu_nfc_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "NFC_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "NFC_XOSC_REQ_VAL,override value when apu_nfc_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "NFC_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "NFC_PWR_REQ_VAL,override value when apu_nfc_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "NFC_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "NFC_DVFS_CTRL,NFC DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "NFC_VOL_VAL,NFC Vol Value"
group.long 0x180++0x7
line.long 0x0 "FP4_CTRL,FP4(15.4) Control"
bitfld.long 0x0 31. "FP4_HOST_SLP_RDY,FP4 Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 30. "FRF_PLL_SYNC_MODE_SEL,FRF PLL Sync Mode Select" "0,1"
newline
bitfld.long 0x0 29. "FP4_CLK_SYNC_MODE_SEL0,FP4 Clock Sync Mode Select 0" "0,1"
newline
bitfld.long 0x0 28. "FRF_CLK_SYNC_MODE_SEL,FRF Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x0 27. "USE_GLITCH_FREE_FP4_CLK_REQ,Use Glitch-Free FP4 Clock Request" "0,1"
newline
bitfld.long 0x0 26. "FP4_CLK_SYNC_MODE_SEL1,FP4 Clock Sync Mode Select 1" "0,1"
newline
bitfld.long 0x0 7. "USE_FP4_INTR_SLP,Use 15.4 interrupt Sleep" "0,1"
newline
bitfld.long 0x0 2. "FP4_SLP_RDY_FW,Bluetooth Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "FP4_SLP_RDY_MASK,FP4 Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "FP4_SLP_RDY,FP4 Sleep Ready" "0,1"
line.long 0x4 "FP4_WKUP_MASK,FP4 Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "FP4_HOST_MAP,15.4 Host Map"
newline
bitfld.long 0x4 3. "FP4_PLL_REQ_MASK,15.4 PLL Request Mask" "0,1"
newline
bitfld.long 0x4 2. "FRF_PLL_REQ_MASK,FRF PLL Request Mask" "0,1"
newline
bitfld.long 0x4 1. "FP4_INTERRUPT_MASK,FP4 Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "FP4_CLK_REQ_MASK,FP4 Clock Request Mask" "0,1"
rgroup.long 0x188++0x3
line.long 0x0 "FP4_STATUS,FP4 Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup In"
newline
bitfld.long 0x0 7. "FRF_PLL_REQ,FRF PLL Request" "0,1"
newline
bitfld.long 0x0 6. "FP4_CLK_REQ,FP4 Clock Request" "0,1"
newline
bitfld.long 0x0 5. "FP4_PLL_REQ,FP4 PLL Request" "0,1"
newline
bitfld.long 0x0 4. "FP4_INTERRUPT,FP4 Interrupt" "0,1"
newline
bitfld.long 0x0 3. "BT_HOST_WKUP,Bluetooth Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "FP4_ACTIVE_SLPCK,FP4 Active Sleep Clock" "0,1"
newline
bitfld.long 0x0 1. "APU_FRF_CLK_EN,APU FRF Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_FP4_CLK_EN,APU FP4 Clock Enable" "0,1"
group.long 0x18C++0x2F
line.long 0x0 "FP4_CKEN_CTRL,FP4 Clock Enable Control"
bitfld.long 0x0 5. "FP4_CLK_EN_SEL,selection for fp4_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "FP4_CLK_EN_VAL,control value for fp4_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "FP4_CLK_EN_SEL_XOSC,selection for fp4_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "FP4_CLK_EN_VAL_XOSC,control value for fp4_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "FP4_CLK_EN_SEL_PWR,selection for fp4_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "FP4_CLK_EN_VAL_PWR,control value for fp4_clk_en when power ready" "0,1"
line.long 0x4 "FP4_RESRC_CTRL,FP4 RESRC Control"
bitfld.long 0x4 11. "FW_ALLWAKE_REQ_VAL,firmware override value when apu_fp4_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FW_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FW_IPWAKE_REQ_VAL,override value when apu_fp4_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FW_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FW_SB_REQ_VAL,override value when apu_fp4_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FW_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FW_XP_REQ_VAL,override value when apu_fp4_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FW_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FW_XOSC_REQ_VAL,override value when apu_fp4_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FW_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FW_PWR_REQ_VAL,override value when apu_fp4_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FW_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "FP4_DVFS_CTRL,FP4 DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "FP4_VOL_VAL,FP4 Vol Value"
line.long 0xC "CPU2_FP4_HOST_WKUP_MASK,CPU2 15.4 Host Wakeup Mask"
hexmask.long.word 0xC 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x10 "CPU2_FP4_HOST_WKUP_POL,CPU2 15.4 Host Wakeup Polarity"
hexmask.long.word 0x10 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
line.long 0x14 "CPU2_FP4_HOST_WKUP_CTRL,CPU2 15.4 Host Wakeup Control"
hexmask.long.word 0x14 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x14 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0x18 "HW_IP_ACTIVE_INDEX_CTRL,HW IP active index Control"
hexmask.long 0x18 0.--31. 1. "MASTERX_ACTIVE_INDEX,master0-7 Active Index[3:0]"
line.long 0x1C "HW_IP_INACTIVE_INDEX_CTRL,HW IP inactive Control"
hexmask.long 0x1C 0.--31. 1. "MASTERX_INACTIVE_INDEX,master0-7 inactive Index[3:0]"
line.long 0x20 "HW_IP_DYNAMIC_CLK_SWITCH_CTRL,HW IP dynamic clock switching contrl"
hexmask.long.byte 0x20 16.--23. 1. "MASTERX_ACTIVE_INDEX_BYPASS_EN,1- use masterx_active-index from register hw_ip_active_index_ctrl; 0-use active index from HW latched version"
newline
hexmask.long.byte 0x20 8.--15. 1. "MASTERX_APU_IDLE_BYPASS_VAL,idle bypass val"
newline
hexmask.long.byte 0x20 0.--7. 1. "MASTERX_APU_IDLE_BYPASS_EN,1-FW bypasses hw_ip_idle; 0 - use hw_ip_idle"
line.long 0x24 "IHB_CTRL,IHB Control"
hexmask.long.byte 0x24 16.--22. 1. "IHB_VOL_VAL,Voltage value needed for Bluetooth function"
newline
bitfld.long 0x24 3. "IHB_CLK_REQ_AS_XPP_REQ,IHB Clock Request as XPP Request" "0,1"
newline
bitfld.long 0x24 2. "IHB_CLK_REQ_AS_XP_REQ,IHB Clock Request as XP Request" "0,1"
newline
bitfld.long 0x24 1. "IHB_VOL_REQ_AS_XP_REQ,IHB Vol Request as XP Request" "0,1"
newline
bitfld.long 0x24 0. "IHB_VOL_REQ_AS_P_REQ,IHB Vol Request as P Request" "0,1"
line.long 0x28 "IHB_WKUP_MASK,IHB Wakeup Mask"
bitfld.long 0x28 4. "CPU1_IHB_PMU_WKUP_MASK,CPU1 IHB PMU Wakeup Mask" "0,1"
newline
bitfld.long 0x28 3. "IHB_WL_WKUP_REQ_MASK,IHB WLAN Wakeup Request Mask" "0,1"
newline
bitfld.long 0x28 2. "IHB_CLK_REQ_MASK,IHB Clock Request Mask" "0,1"
newline
bitfld.long 0x28 1. "IHB_LO_VOL_REQ_MASK,IHB Low Vol Request Mask" "0,1"
newline
bitfld.long 0x28 0. "IHB_HI_VOL_REQ_MASK,IHB High Vol Request Mask" "0,1"
line.long 0x2C "CPU2_IHB_WKUP_MASK,CPU2 IHB Wakeup Mask"
bitfld.long 0x2C 0. "CPU2_IHB_PMU_WKUP_MASK,CPU2 IHB PMU Wakeup Mask" "0,1"
rgroup.long 0x1BC++0x3
line.long 0x0 "IHB_STATUS,IHB Status"
hexmask.long 0x0 0.--31. 1. "IHB_STATUS,IHB Status"
group.long 0x1C0++0x7
line.long 0x0 "USB_CTRL,USB Control"
bitfld.long 0x0 31. "USB_CLK_SEL_ACK_EXT_EN,USB Clock Select Ack Ext Enable" "0,1"
newline
bitfld.long 0x0 25. "USB_USE_UNSYNC_VOL_LVL,USB Use Unsync Vol Level" "0,1"
newline
bitfld.long 0x0 24. "FW_FORCE_USB_PWRUP,FW Force USB Powerup" "0,1"
newline
bitfld.long 0x0 9. "USB_USE_NOM_PWR_BYP,USB Use Nominal Power Bypass" "0,1"
newline
bitfld.long 0x0 5. "IDLE2ISO_DLY_EN,USB FSM state counter enable. When set to 1 use usb_pwr_ctrl_dly and usb_pwr_ctrl_dly2. When set to 0 no delay" "0,1"
newline
bitfld.long 0x0 4. "USE_CLK_SEL_ACK_AS_USB_PWR_DWN,Use Clock Select Ack as USB Power Down" "0,1"
newline
bitfld.long 0x0 0. "USB_PWR_DWN_MASK,USB Power Down Mask" "0,1"
line.long 0x4 "USB_WKUP_MASK,USB Wakeup Mask"
bitfld.long 0x4 2. "USB_CLK_SEL_REQ_MASK,USB Clock Select Request Mask" "0,1"
newline
bitfld.long 0x4 1. "USB_AXI_CLK_REQ_MASK,USB AXI Clock Request Mask" "0,1"
newline
bitfld.long 0x4 0. "USB_P_REQ_MASK,USB P Request Mask" "0,1"
rgroup.long 0x1C8++0x3
line.long 0x0 "USB_STATUS,USB Status"
hexmask.long.byte 0x0 16.--19. 1. "APU_USB_ST,APU USB St"
newline
bitfld.long 0x0 15. "USB_PWR_DWN,USB Power Down" "0,1"
newline
bitfld.long 0x0 14. "DVFS_USB_VOL_LVL_REACHED,DVFS USB Vol Level Reached" "0,1"
newline
bitfld.long 0x0 13. "DVFS_NOM_VOL_LVL_REACHED,DVFS Nominal Vol Level Reached" "0,1"
newline
bitfld.long 0x0 12. "USB_VOL_LVL_REACHED,USB Vol Level Reached" "0,1"
newline
bitfld.long 0x0 11. "APU_USB_CLK_SEL,APU USB Clock Select" "0,1"
newline
bitfld.long 0x0 10. "XOSC_STABLE_REFCK,OSC clock stable on ref clock domain" "0,1"
newline
bitfld.long 0x0 9. "APU_USB_AXI_CLK_EN,APU USB AXI Clock Enable" "0,1"
newline
bitfld.long 0x0 8. "USB_CLK_SEL_ACK_EXT_EN,extension enable for the usb_clk_sel_ack" "0,1"
newline
bitfld.long 0x0 7. "APU_USB_SWITCH_PD,APU USB Switch Power Down" "0,1"
newline
bitfld.long 0x0 6. "SOC_PWR_RDY,SOC Power Ready" "0,1"
newline
bitfld.long 0x0 5. "APU_USB_AXI_CLK_ACK,APU USB AXI Clock Ack" "0,1"
newline
bitfld.long 0x0 4. "USB_AXI_CLK_REQ,USB AXI Clock Request" "0,1"
newline
bitfld.long 0x0 3. "APU_USB_CLK_SEL_ACK,APU USB Clock Select Ack" "0,1"
newline
bitfld.long 0x0 2. "USB_CLK_SEL_REQ,USB Clock Select Request" "0,1"
newline
bitfld.long 0x0 1. "APU_USB_P_ACK,APU USB P Ack" "0,1"
newline
bitfld.long 0x0 0. "USB_P_REQ,USB P Request" "0,1"
group.long 0x200++0x67
line.long 0x0 "CPU1_DVFS_CTRL,CPU1 DVFS Control"
bitfld.long 0x0 31. "PCIE_VOL_HOST_SLP_DEP,PCIe Vol Host Sleep Dep" "0,1"
newline
bitfld.long 0x0 30. "PCIE_VOL_FLR_DEP,PCIe Vol Flr Dep" "0,1"
newline
bitfld.long 0x0 29. "PCIE_VOL_HOST_WKUP_DEP,PCIe Vol Host Wakeup Dep" "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "CPU1_INACTIVE_AHB1_INDEX,CPU1 Inactive AHB1 Index"
newline
hexmask.long.byte 0x0 16.--19. 1. "CPU1_ACTIVE_AHB1_INDEX,CPU1 Active AHB1 Index"
newline
hexmask.long.byte 0x0 12.--15. 1. "CPU1_INACTIVE_SYS_INDEX,CPU1 Inactive System Index"
newline
hexmask.long.byte 0x0 8.--11. 1. "CPU1_ACTIVE_SYS_INDEX,CPU1 Active System Index"
newline
hexmask.long.byte 0x0 4.--7. 1. "CPU1_INACTIVE_INDEX,CPU1 Inactive Index"
newline
hexmask.long.byte 0x0 0.--3. 1. "CPU1_ACTIVE_INDEX,CPU1 Active Index"
line.long 0x4 "CPU1_FREQ_REG1,CPU1 Frequency 1"
hexmask.long 0x4 0.--31. 1. "CPU1_FREQ_REG1,CPU1 Frequency 1"
line.long 0x8 "CPU1_FREQ_REG2,CPU1 Frequency 2"
hexmask.long 0x8 0.--31. 1. "CPU1_FREQ_REG2,CPU1 Frequency 2"
line.long 0xC "CPU1_PLL_EN_REG,CPU1 PLL Enable"
hexmask.long 0xC 0.--31. 1. "CPU1_PLL_EN_REG,CPU1 PLL Enable"
line.long 0x10 "CPU1_VOL_REG1,CPU1 Voltage 1"
hexmask.long 0x10 0.--31. 1. "CPU1_VOL_REG1,CPU1 Voltage 1"
line.long 0x14 "CPU1_VOL_REG2,CPU1 Voltage 2"
hexmask.long 0x14 0.--31. 1. "CPU1_VOL_REG2,CPU1 Voltage 2"
line.long 0x18 "CPU1_VOL_REG3,CPU1 Voltage 3"
hexmask.long 0x18 0.--31. 1. "CPU1_VOL_REG3,CPU1 Voltage 3"
line.long 0x1C "CPU1_VOL_REG4,CPU1 Voltage 4"
hexmask.long 0x1C 0.--31. 1. "CPU1_VOL_REG4,CPU1 Voltage 4"
line.long 0x20 "CPU2_DVFS_CTRL,CPU2 DVFS Control"
hexmask.long.byte 0x20 25.--31. 1. "UART_VOL_VAL,UART Vol Value"
newline
bitfld.long 0x20 24. "CPU2_AHB1_INDEX_SEL_METHOD,CPU2 AHB1 index select method" "0,1"
newline
hexmask.long.byte 0x20 20.--23. 1. "CPU2_INACTIVE_AHB1_INDEX,CPU2 Inactive AHB1 Index"
newline
hexmask.long.byte 0x20 16.--19. 1. "CPU2_ACTIVE_AHB1_INDEX,CPU2 Active AHB1 Index"
newline
hexmask.long.byte 0x20 12.--15. 1. "CPU2_INACTIVE_SYS_INDEX,CPU2 Inactive System Index"
newline
hexmask.long.byte 0x20 8.--11. 1. "CPU2_ACTIVE_SYS_INDEX,CPU2 Active System Index"
newline
hexmask.long.byte 0x20 4.--7. 1. "CPU2_INACTIVE_INDEX,CPU2 Inactive Index"
newline
hexmask.long.byte 0x20 0.--3. 1. "CPU2_ACTIVE_INDEX,CPU2 Active Index"
line.long 0x24 "CPU2_FREQ_REG1,CPU2 Frequency 1"
hexmask.long 0x24 0.--31. 1. "CPU2_FREQ_REG1,CPU2 Frequency 1"
line.long 0x28 "CPU2_FREQ_REG2,CPU2 Frequency 2"
hexmask.long 0x28 0.--31. 1. "CPU2_FREQ_REG2,CPU2Frequency 2"
line.long 0x2C "CPU2_PLL_EN_REG,CPU2 PLL Enable"
hexmask.long 0x2C 0.--31. 1. "CPU2_PLL_EN_REG,CPU2 PLL Enable"
line.long 0x30 "CPU2_VOL_REG1,CPU2 Voltage 1"
hexmask.long 0x30 0.--31. 1. "CPU2_VOL_REG1,CPU2 Voltage 1"
line.long 0x34 "CPU2_VOL_REG2,CPU2 Voltage 2"
hexmask.long 0x34 0.--31. 1. "CPU2_VOL_REG2,CPU2 Voltage 2"
line.long 0x38 "CPU2_VOL_REG3,CPU2 Voltage 3"
hexmask.long 0x38 0.--31. 1. "CPU2_VOL_REG3,CPU2 Voltage 3"
line.long 0x3C "CPU2_VOL_REG4,CPU2 Voltage 4"
hexmask.long 0x3C 0.--31. 1. "CPU2_VOL_REG4,CPU2 Voltage 4"
line.long 0x40 "SYS_FREQ_REG1,System Frequency 1"
hexmask.long 0x40 0.--31. 1. "SYS_FREQ_REG1,System Frequency 1"
line.long 0x44 "SYS_FREQ_REG2,System Frequency 2"
hexmask.long 0x44 0.--31. 1. "SYS_FREQ_REG2,System Frequency 2"
line.long 0x48 "SYS_PLL_EN_REG,System PLL Enable"
hexmask.long 0x48 0.--31. 1. "SYS_PLL_EN_REG,System PLL Enable"
line.long 0x4C "SYS_VOL_REG1,System Voltage 1"
hexmask.long 0x4C 0.--31. 1. "SYS_VOL_REG1,System Voltage 1"
line.long 0x50 "SYS_VOL_REG2,System Voltage 2"
hexmask.long 0x50 0.--31. 1. "SYS_VOL_REG2,System Voltage 2"
line.long 0x54 "SYS_VOL_REG3,System Voltage 3"
hexmask.long 0x54 0.--31. 1. "SYS_VOL_REG3,System Voltage 3"
line.long 0x58 "SYS_VOL_REG4,System Voltage 4"
hexmask.long 0x58 0.--31. 1. "SYS_VOL_REG4,System Voltage 4"
line.long 0x5C "DVFS_CTRL,DVFS Control"
hexmask.long.byte 0x5C 25.--31. 1. "SDIO_VOL_VAL,SDIO Vol Value"
newline
bitfld.long 0x5C 24. "INACTIVE_ACK_EXT_EN,Inactive Ack Ext Enable" "0,1"
newline
bitfld.long 0x5C 21. "UPDATE_BUCK_EN,to enable the forcing buck value when the resolution is not aligned" "0,1"
newline
bitfld.long 0x5C 20. "EN_FASTER_DVFS,Enable Faster DVFS" "0,1"
newline
bitfld.long 0x5C 19. "SW_LOCK_GUARD_DIS,SW Lock Guard Disable" "0,1"
newline
bitfld.long 0x5C 18. "DVFS_EAS_VOL_DIS,DVFS EAS Vol Disable" "0,1"
newline
bitfld.long 0x5C 17. "EN_FASTER_DYN_CLK,Enable Faster Dynamic Clock" "0,1"
newline
bitfld.long 0x5C 16. "DVFS_MODE,DVFS Mode 0: only use partial_dvfs_vol(default)" "0: only use partial_dvfs_vol,?"
newline
bitfld.long 0x5C 15. "DVFS_DYN_CLK_EN,DVFS Dynamic Clock Enable" "0,1"
newline
bitfld.long 0x5C 14. "DVFS_CLK_SWITCH_EN,DVFS Clock Switch Enable" "0,1"
newline
hexmask.long.byte 0x5C 7.--13. 1. "DVFS_EAS_VOL,DVFS EAS Vol"
newline
hexmask.long.byte 0x5C 0.--6. 1. "DVFS_HOST_VOL_VAL,DVFS Host Vol Value"
line.long 0x60 "PARTIAL_DVFS_CTRL,Partial DVFS Control"
bitfld.long 0x60 31. "BYPASS_DVFS_FSM,Bypass DVFS FSM" "0,1"
newline
hexmask.long.byte 0x60 21.--25. 1. "VOL_RESOLUTION_SLP,Vol Resolution Sleep"
newline
hexmask.long.byte 0x60 16.--20. 1. "VOL_RESOLUTION_REF,Vol Resolution Ref"
newline
hexmask.long.byte 0x60 8.--11. 1. "STATIC_DVFS_FREQ,Static DVFS Frequency"
newline
bitfld.long 0x60 7. "STATIC_PLL_EN,Static PLL Enable" "0,1"
newline
hexmask.long.byte 0x60 0.--6. 1. "PARTIAL_DVFS_VOL,Partial DVFS Vol"
line.long 0x64 "DVFS_TIMER,DVFS Timer"
hexmask.long.word 0x64 16.--31. 1. "REF_CNT,Reference Count"
newline
hexmask.long.word 0x64 0.--15. 1. "SLP_CNT,Sleep Count"
group.long 0x270++0x1B
line.long 0x0 "AHB1_FREQ_REG1,AHB1 Frequency 1"
hexmask.long 0x0 0.--31. 1. "AHB1_FREQ_REG1,AHB1 Frequency 1"
line.long 0x4 "AHB1_FREQ_REG2,AHB1 Frequency 2"
hexmask.long 0x4 0.--31. 1. "AHB1_FREQ_REG2,AHB1 Frequency 2"
line.long 0x8 "AHB1_PLL_EN_REG,AHB1 PLL Enable"
hexmask.long 0x8 0.--31. 1. "AHB1_PLL_EN_REG,AHB1 PLL Enable"
line.long 0xC "AHB1_VOL_REG1,AHB1 Voltage 1"
hexmask.long 0xC 0.--31. 1. "AHB1_VOL_REG1,AHB1 Voltage 1"
line.long 0x10 "AHB1_VOL_REG2,AHB1 Voltage 2"
hexmask.long 0x10 0.--31. 1. "AHB1_VOL_REG2,AHB1 Voltage 2"
line.long 0x14 "AHB1_VOL_REG3,AHB1 Voltage 3"
hexmask.long 0x14 0.--31. 1. "AHB1_VOL_REG3,AHB1 Voltage 3"
line.long 0x18 "AHB1_VOL_REG4,AHB1 Voltage 4"
hexmask.long 0x18 0.--31. 1. "AHB1_VOL_REG4,AHB1 Voltage 4"
rgroup.long 0x298++0x3
line.long 0x0 "DVFS_STATUS,DVFS Status"
bitfld.long 0x0 31. "SW_LOCK_GAURD,SW Lock Guard" "0,1"
newline
bitfld.long 0x0 30. "SW_FREQ_GAURD,SW Frequency Guard" "0,1"
newline
hexmask.long.byte 0x0 23.--29. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
bitfld.long 0x0 22. "PCIE_VOL_LVL_REACHED,PCIe Vol Level Reached" "0,1"
newline
bitfld.long 0x0 21. "USB_VOL_LVL_REACHED,USB Vol Level Reached" "0,1"
newline
bitfld.long 0x0 20. "SOC_POWER_LVL_REACHED,SoC Power Level Reached" "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x0 12.--15. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x0 8.--11. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
bitfld.long 0x0 7. "LOCK_VOL_REQ,Lock Vol Request" "0,1"
newline
bitfld.long 0x0 6. "CPU1_LOCK_VOL,CPU1 Lock Vol" "0,1"
newline
bitfld.long 0x0 5. "CPU2_LOCK_VOL,CPU2 Lock Vol" "0,1"
newline
bitfld.long 0x0 4. "SYS_LOCK_VOL,System Lock Vol" "0,1"
newline
bitfld.long 0x0 3. "LOCK_FREQ_REQ,Lock Frequency Request" "0,1"
newline
bitfld.long 0x0 2. "CPU1_LOCK_FREQ,CPU1 Lock Frequency" "0,1"
newline
bitfld.long 0x0 1. "CPU2_LOCK_FREQ,CPU2 Lock Frequency" "0,1"
newline
bitfld.long 0x0 0. "SYS_LOCK_FREQ,System Lock Frequency" "0,1"
group.long 0x29C++0x7
line.long 0x0 "DVFS_DBG_CTRL,DVFS Debug Control"
bitfld.long 0x0 16. "SD_CLK_SWITCH_OK_MASK,SD Clock Switch Ok Mask" "0,1"
newline
bitfld.long 0x0 15. "BUCK_EFF_MODE_FIX,BUCK Efficiency Mode Fix" "0,1"
newline
bitfld.long 0x0 13. "DVFS_CLK_SEL_FW_VAL,DVFS Clock Select FW Value" "0,1"
newline
bitfld.long 0x0 12. "DVFS_CLK_SEL_FW_BYPASS,DVFS Clock Select FW Bypass" "0,1"
newline
bitfld.long 0x0 8.--9. "DBG_SLP_TIMER_SEL,Debug Sleep Timer Select" "0,1,2,3"
newline
bitfld.long 0x0 4.--6. "DBG_VOL_SEL,Debug Vol Select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "END_TRIGGER,End Trigger" "0,1"
newline
bitfld.long 0x0 1. "START_TRIGGER,Start Trigger" "0,1"
newline
bitfld.long 0x0 0. "DVFS_DBG_MODE,DVFS Debug Mode" "0,1"
line.long 0x4 "DVFS_DBG_PATTERN_DATA,DVFS Debug Pattern Data"
hexmask.long.byte 0x4 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x4 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x4 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x4 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x4 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x4 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x4 0.--4. 1. "VOL_REQ,Vol Request"
rgroup.long 0x2A4++0x1B
line.long 0x0 "DVFS_DBG_REG0,DVFS Debug 0"
hexmask.long.byte 0x0 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x0 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x0 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x0 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x0 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x0 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x0 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x4 "DVFS_DBG_REG1,DVFS Debug 1"
hexmask.long.byte 0x4 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x4 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x4 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x4 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x4 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x4 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x4 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x8 "DVFS_DBG_REG2,DVFS Debug 2"
hexmask.long.byte 0x8 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x8 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x8 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x8 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x8 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x8 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x8 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0xC "DVFS_DBG_REG3,DVFS Debug 3"
hexmask.long.byte 0xC 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0xC 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0xC 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0xC 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0xC 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0xC 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0xC 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x10 "DVFS_DBG_REG4,DVFS Debug 4"
hexmask.long.byte 0x10 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x10 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x10 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x10 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x10 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x10 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x10 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x14 "DVFS_DBG_REG5,DVFS Debug 5"
hexmask.long.byte 0x14 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x14 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x14 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x14 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x14 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x14 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x14 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x18 "DVFS_DBG_STATUS,DVFS Debug Status"
hexmask.long.byte 0x18 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x18 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x18 18.--21. 1. "VOL_REQ,Vol Request"
newline
bitfld.long 0x18 17. "NOM_VOL_LVL_REACHED,Nominal Vol Level Reached" "0,1"
newline
bitfld.long 0x18 16. "NFC_VOL_LVL_REACHED,NFC Vol Level Reached" "0,1"
newline
bitfld.long 0x18 15. "WLAN_VOL_LVL_REACHED,WLAN Vol Level Reached" "0,1"
newline
bitfld.long 0x18 12. "PMIC_TIMER_DONE_REG,PMIC Timer Done" "0,1"
newline
bitfld.long 0x18 11. "SW_FREQ_GAURD_EN,SW Frequency Guard Enable" "0,1"
newline
bitfld.long 0x18 10. "EAS_SEL,EAS Select" "0,1"
newline
bitfld.long 0x18 9. "DVFS_CLK_SEL_DVFSCK,DVFS Clock Select DVFSCK" "0,1"
newline
bitfld.long 0x18 8. "SW_LOCK_GAURD_EN,SW Lock Guard Enable" "0,1"
newline
bitfld.long 0x18 7. "RESET_COUNTER_SYNCED,voltage corresponding to PMIC code 0x3" "0,1"
newline
bitfld.long 0x18 6. "KEEP_DVFS_LVL_ACTIVE,Keep DVFS Level Active" "0,1"
newline
hexmask.long.byte 0x18 1.--5. 1. "BUCK_LVL_REACHED,voltage corresponding to PMIC code 0x2"
newline
bitfld.long 0x18 0. "DVFS_DBG_LOG_DONE,DVFS Debug Log Done" "0,1"
group.long 0x2C0++0x3
line.long 0x0 "DVFS_DBG_PATTERN_MASK,DVFS Debug Patter Mask"
hexmask.long 0x0 0.--31. 1. "MASK,Mask to Delay"
group.long 0x2F8++0x13
line.long 0x0 "DVFS_PMIC_TIMER,DVFS PMIC Timer"
hexmask.long.word 0x0 20.--31. 1. "ACTIVE_CNT,Active Count"
newline
hexmask.long.byte 0x0 16.--19. 1. "SLP_CNT,Sleep Counts"
newline
hexmask.long.word 0x0 0.--15. 1. "REF_CNT,Reference Count"
line.long 0x4 "DVFS_PMIC_MAP,DVFS PMIC Map"
bitfld.long 0x4 31. "USE_PMIC_TIMER,Use PMIC Timer" "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "DVFS_VOL_FOR_PMIC3,DVFS Vol for PMIC 3"
newline
hexmask.long.byte 0x4 16.--22. 1. "DVFS_VOL_FOR_PMIC2,DVFS Vol for PMIC 2"
newline
hexmask.long.byte 0x4 8.--14. 1. "DVFS_VOL_FOR_PMIC1,DVFS Vol for PMIC 1"
newline
hexmask.long.byte 0x4 0.--6. 1. "DVFS_VOL_FOR_PMIC0,DVFS Vol for PMIC 0"
line.long 0x8 "LDO_CTRL,LDO Control"
bitfld.long 0x8 31. "KEEP_LDO_MAIN_WHILE_SLP,Keep LDO Main While Sleep" "0,1"
newline
bitfld.long 0x8 30. "USE_XOSC_EN_AS_SEL,Use XOSC Enable as Select" "0,1"
newline
hexmask.long.byte 0x8 8.--15. 1. "BACKUP_DELAY_COUNTER_VAL,Backup Delay Counter Value"
newline
bitfld.long 0x8 4.--5. "MAIN_DELAY_COUNTER_VAL,Main Delay Counter Value" "0,1,2,3"
newline
bitfld.long 0x8 1. "BACKUP_DELAY_CNT_EN,Backup Delay Count Enable" "0,1"
newline
bitfld.long 0x8 0. "MAIN_DELAY_CNT_EN,Main Delay Count Enable" "0,1"
line.long 0xC "LDO_BACKUP_LVL_MAP1,LDO Backup Level Map 1"
hexmask.long 0xC 0.--31. 1. "LDO_BACKUP_LVL_MAP1,LDO Backup Level Map 1"
line.long 0x10 "LDO_BACKUP_LVL_MAP2,LDO Backup Level Map 2"
hexmask.long 0x10 0.--31. 1. "LDO_BACKUP_LVL_MAP2,LDO Backup Level Map 2"
rgroup.long 0x30C++0x3
line.long 0x0 "LDO_STATUS,LDO Status"
bitfld.long 0x0 25. "BKUP_LVL1_SEL,Backup Level 1 Select" "0,1"
newline
bitfld.long 0x0 24. "BKUP_LVL2_SEL,Backup Level 2 Select" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "BACKUP_DELAY_CNT,Backup Delay Count (to check testbus)"
newline
bitfld.long 0x0 15. "LDO_BACKUP_EN,LDO Backup Enable" "0,1"
newline
bitfld.long 0x0 14. "D_LDO_BACKUP_EN,D LDO Backup Enable" "0,1"
newline
bitfld.long 0x0 13. "BACK_DELAY_CNT_MET,Back Delay Count Met" "0,1"
newline
bitfld.long 0x0 12. "ACTIVE_SEL,Active Select" "0,1"
newline
bitfld.long 0x0 11. "LDO_MAIN_PD,LDO Main Powerdown" "0,1"
newline
bitfld.long 0x0 10. "MAIN_PD_DELAY_CNT_MET,Main Powerdown Delay Count Met" "0,1"
newline
bitfld.long 0x0 8.--9. "MAIN_PD_DELAY_CNT,Main Powerdown Delay Count" "0,1,2,3"
newline
hexmask.long.byte 0x0 4.--7. 1. "LDO_MAIN_LVL,LDO Main Level"
newline
bitfld.long 0x0 0.--2. "LDO_BACKUP_LVL,LDO Backup Level" "0,1,2,3,4,5,6,7"
group.long 0x310++0x7
line.long 0x0 "RC32_CAL_CTRL,RC32 Calibration Control"
hexmask.long.byte 0x0 4.--10. 1. "RC32_CAL_VOL_VAL,RC32 Calibration Vol Value"
newline
bitfld.long 0x0 3. "USE_RC32_CAL_DONE,Use RC32 Calibration Done" "0,1"
newline
bitfld.long 0x0 2. "RC32_PARTIAL_CAL_EN_ON_BT_WKUP,RC32 Partial Calibration Enable on Bluetooth Wakeup" "0,1"
newline
bitfld.long 0x0 1. "RC32_PARTIAL_CAL_EN,RC32 Partial Calibration Enable" "0,1"
newline
bitfld.long 0x0 0. "RC32_FULL_CAL_EN,RC32 Full Calibration Enable" "0,1"
line.long 0x4 "RC32_CAL_SLPCLK_TIMER,RC32 Calibration Sleep Clock Timer"
hexmask.long 0x4 0.--31. 1. "RC32_CAL_SLPCLK_TIMER,RC32 Calibration Sleep Clock Timer"
rgroup.long 0x318++0x3
line.long 0x0 "RC32CAL_SLPCLK_CNT_RD,RC32 Calibration Sleep Clock Count Read"
hexmask.long 0x0 0.--31. 1. "RC32CAL_SLPCLK_CNT_RD,RC32 Calibration Sleep Clock Count Read"
group.long 0x338++0x1F
line.long 0x0 "TSTBUS_DATA,Testbus Data"
hexmask.long 0x0 0.--31. 1. "TSTBUS_DATA,Testbus Data"
line.long 0x4 "TST_CTRL,Test Control"
bitfld.long 0x4 28.--30. "CPU1_HOST_TST_CTRL,CPU1 Host Test Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24.--25. "HOST_TST_CTRL,Host Test Control" "0,1,2,3"
newline
bitfld.long 0x4 23. "USE_SOC_APU_SUBTEST,Use SoC APU Subtest" "0,1"
newline
bitfld.long 0x4 21.--22. "APU_REG_SUBTEST_SEL,APU Reg Subtest Select" "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--20. 1. "APU_TESTBUS_SEL,APU Testbus Select"
newline
hexmask.long.byte 0x4 12.--15. 1. "TEST_MUX_SEL_SHIFT_BIT,Test MUX Select Shift"
newline
hexmask.long.byte 0x4 7.--11. 1. "CPU2_HOST_TST_CTRL,CPU2 Host Test Control"
newline
bitfld.long 0x4 5. "CPU1_CP15_SLP_CTRL,CPU1 CP15 Sleep Control" "0,1"
newline
bitfld.long 0x4 4. "WLAN_TST_CTRL,WLAN Test Control" "0,1"
newline
bitfld.long 0x4 3. "CPU2_CP15_SLP_CTRL,CPU2 CP15 Sleep Control" "0,1"
newline
bitfld.long 0x4 2. "NFC_TST_CTRL,NFC Test Control" "0,1"
newline
bitfld.long 0x4 1. "FM_TST_CTRL,FM Test Control" "0,1"
newline
bitfld.long 0x4 0. "BT_BLE_TST_CTRL,Bluetooth BLE Test Control" "0,1"
line.long 0x8 "BCA_LTE_CTRL,BCA LTE Control"
bitfld.long 0x8 31. "BCA_CLK_FW_EN,BCA Clock FW Enable" "0,1"
newline
bitfld.long 0x8 30. "BCA_FORCE_ON_WHILE_BT,BCA Force on While Bluetooth" "0,1"
newline
bitfld.long 0x8 20. "USE_SLNA_WHILE_BT,Use sLNA While Bluetooth" "0,1"
newline
bitfld.long 0x8 16. "BCA_BT_LTE_COEX_EN,BCA Bluetooth LTE Coexistence Enable" "0,1"
newline
bitfld.long 0x8 15. "BCA_WL_LTE_COEX_EN,BCA WLAN LTE Coexistence Enable" "0,1"
newline
bitfld.long 0x8 7. "BCA_LTE_CLK_BYP,BCA LTE Clock Bypass" "0,1"
newline
bitfld.long 0x8 4. "LTE_TMR2_CNT_FREEZE,LTE TMR2 Count Freeze" "0,1"
newline
bitfld.long 0x8 3. "LTE_TMR1_CNT_FREEZE,LTE TMR1 Count Freeze" "0,1"
newline
bitfld.long 0x8 2. "LTE_TMR2_INT,LTE TMR2 Interrupt" "0,1"
newline
bitfld.long 0x8 1. "LTE_TMR1_INT,LTE TMR1 Interrupt" "0,1"
newline
bitfld.long 0x8 0. "LTE_CNT_START,LTE Count Start" "0,1"
line.long 0xC "BCA_LTE_TIMER1,BCA LTE Timer 1"
hexmask.long 0xC 0.--31. 1. "BCA_LTE_TIMER1,BCA LTE Timer 1"
line.long 0x10 "BCA_LTE_TIMER2,BCA LTE Timer 2"
hexmask.long 0x10 0.--31. 1. "BCA_LTE_TIMER2,BCA LTE Timer 2"
line.long 0x14 "BCA_MWS_WKUP_TIMER,BCA MWS Wakeup Timer"
hexmask.long.byte 0x14 28.--31. 1. "BCA_BCN_WKUP_CNT,BCA Beacon Wakeup Count"
newline
hexmask.long.word 0x14 0.--15. 1. "BCA_MWS_TIMER,BCA MWS Timer"
line.long 0x18 "BT2_CTRL,Bluetooth 2 Control"
bitfld.long 0x18 31. "BT_HOST_SLP_RDY,Bluetooth Host Sleep Ready" "0,1"
newline
bitfld.long 0x18 30. "BT_PLL_SYNC_MODE_SEL,Bluetooth PLL Sync Mode Select" "0,1"
newline
bitfld.long 0x18 29. "BT_CLK_SYNC_MODE_SEL0,Bluetooth Clock Sync Mode Select 0" "0,1"
newline
bitfld.long 0x18 28. "BRF_CLK_SYNC_MODE_SEL,BRF Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x18 27. "USE_GLITCH_FREE_BT_CLK_REQ,Use Glitch-Free Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x18 26. "BT_CLK_SYNC_MODE_SEL1,Bluetooth Clock Sync Mode Select 1" "0,1"
newline
bitfld.long 0x18 7. "USE_BT_INTR_SLP,Use Bluetooth interrupt Sleep" "0,1"
newline
bitfld.long 0x18 3. "BTU_CLK_NCO_MODE_SEL_EN,1- ignore the btu_clk_nco_mode from CIU2 keep the bt_clk_req as XP wakeup source" "0,1"
newline
bitfld.long 0x18 2. "BT_SLP_RDY_FW,Bluetooth Sleep Ready FW" "0,1"
newline
bitfld.long 0x18 1. "BT_SLP_RDY_MASK,Bluetoot Sleep Ready Mask" "0,1"
newline
bitfld.long 0x18 0. "BT_SLP_RDY,Bluetooth Sleep Ready" "0,1"
line.long 0x1C "BT2_WKUP_MASK,Bluetooth 2 Wakeup Mask"
hexmask.long.word 0x1C 16.--31. 1. "BT_HOST_MAP,Bluetooth Host Map"
newline
bitfld.long 0x1C 5. "BRF_PLL_REQ_MASK,BRF PLL Request Mask" "0,1"
newline
bitfld.long 0x1C 4. "BT_PLL_REQ_MASK,Bluetooth PLL Request Mask" "0,1"
newline
bitfld.long 0x1C 3. "BT_INTR_MASK,Bluetooth Interrupt Mask" "0,1"
newline
bitfld.long 0x1C 2. "BT_WB_ACTIVE_REQ_MASK,Bluetooth WB Active Request Mask" "0,1"
newline
bitfld.long 0x1C 1. "BT_CLK_REQ_MASK,Bluetooth Clock Request Mask" "0,1"
newline
bitfld.long 0x1C 0. "BCA_CLK_REQ_MASK,BCA Clock Request Mask" "0,1"
rgroup.long 0x358++0x3
line.long 0x0 "BT2_STATUS,Bluetooth 2 Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup In"
newline
bitfld.long 0x0 9. "BT_WIDEBAND_ACTIVE,Bluetooth Wideband Active" "0,1"
newline
bitfld.long 0x0 8. "BRF_PLL_REQ,BRF PLL Request" "0,1"
newline
bitfld.long 0x0 7. "BT_CLK_REQ,Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x0 6. "BT_PLL_REQ,Bluetooth PLL Request" "0,1"
newline
bitfld.long 0x0 5. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 4. "BT_HOST_WKUP,Bluetooth Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "BT_ACTIVE_SLPCK,Bluetooth Active Sleep Clock" "0,1"
newline
bitfld.long 0x0 1. "APU_BRF_CLK_EN,APU BRF Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_CLK_EN,APU Bluetooth Clock Enable" "0,1"
group.long 0x35C++0x13
line.long 0x0 "BT2_CKEN_CTRL,Bluetooth 2 Clock Enable Control"
bitfld.long 0x0 5. "BT_CLK_EN_SEL,selection for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "BT_CLK_EN_VAL,control value for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "BT_CLK_EN_SEL_XOSC,selection for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "BT_CLK_EN_VAL_XOSC,control value for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "BL_CLK_EN_SEL_PWR,selection for bt_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "BT_CLK_EN_VAL_PWR,control value for bt_clk_en when power ready" "0,1"
line.long 0x4 "BT2_RESRC_CTRL,Bluetooth 2 RESRC Control"
bitfld.long 0x4 11. "FW_ALLWAKE_REQ_VAL,firmware override value when apu_bt_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FW_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FW_IPWAKE_REQ_VAL,override value when apu_bt_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FW_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FW_SB_REQ_VAL,override value when apu_bt_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FW_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FW_XP_REQ_VAL,override value when apu_bt_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FW_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FW_XOSC_REQ_VAL,override value when apu_bt_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FW_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FW_PWR_REQ_VAL,override value when apu_bt_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FW_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "BT2_DVFS_CTRL,Bluetooth 2 DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "BT_VOL_VAL,Blueooth Vol Value"
line.long 0xC "BLE2_CTRL,BLE 2 Control"
bitfld.long 0xC 31. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0xC 15. "BT_AES_NCO_MODE,Bluetooth AES NCO Mode" "0,1"
newline
bitfld.long 0xC 3. "BLE_MODE_EN,BLE Mode Enable" "0,1"
newline
bitfld.long 0xC 2. "BLE_SLP_RDY_FW,BLE Sleep Ready FW" "0,1"
newline
bitfld.long 0xC 1. "BLE_SLP_RDY_MASK,BLE Sleep Ready Mask" "0,1"
newline
bitfld.long 0xC 0. "BLE_SLP_RDY,BLE Sleep Ready" "0,1"
line.long 0x10 "BLE2_WKUP_MASK,BLE 2 Wakeup Mask"
bitfld.long 0x10 4. "LBC_XP_REQ_MASK,LBC XP Request Mask" "0,1"
newline
bitfld.long 0x10 3. "BT_AES_CLK_REQ_MASK,Bluetooth AES Clock Request Mask" "0,1"
rgroup.long 0x370++0x3
line.long 0x0 "BLE2_STATUS,BLE 2 Status"
bitfld.long 0x0 9. "BT_AES_CLK_REQ,Bluetooth AES Clock Request Mask" "0,1"
newline
bitfld.long 0x0 8. "LBC_XP_REQ,LBC XP Request" "0,1"
newline
bitfld.long 0x0 6. "BT_AES_NCO_MODE,Blueooth AES NCO Mode" "0,1"
newline
bitfld.long 0x0 5. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0x0 4. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 3. "T1_STABLE,T1 Delay" "0,1"
newline
bitfld.long 0x0 2. "XOSC_STABLE_REFCK,XOSC Stable Ref Clock" "0,1"
newline
bitfld.long 0x0 1. "BT_AES_CLK_SEL,Bluetooth AES Clock Select" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_AES_CLK_EN,APU Bluetooth AES Clock Enable" "0,1"
rgroup.long 0x380++0x3
line.long 0x0 "LMU_IP_REVISION,LMU IP Revision"
hexmask.long.word 0x0 0.--15. 1. "IP_REV,IP Revision"
group.long 0x384++0x3
line.long 0x0 "LMU_CPU1_STA_CFG,LMU CPU1 STA Configuration"
bitfld.long 0x0 31. "RESERVED0,Reserved 0" "0,1"
newline
bitfld.long 0x0 30. "BANK15_STA_OFF_EN,Bank15 STA Off Enable" "0,1"
newline
bitfld.long 0x0 29. "RESERVED1,Reserved 1" "0,1"
newline
bitfld.long 0x0 28. "BANK14_STA_OFF_EN,Bank14 STA Off Enable" "0,1"
newline
bitfld.long 0x0 27. "RESERVED2,Reserved 2" "0,1"
newline
bitfld.long 0x0 26. "BANK13_STA_OFF_EN,Bank13 STA Off Enable" "0,1"
newline
bitfld.long 0x0 25. "RESERVED3,Reserved 3" "0,1"
newline
bitfld.long 0x0 24. "BANK12_STA_OFF_EN,Bank12 STA Off Enable" "0,1"
newline
bitfld.long 0x0 23. "RESERVED4,Reserved 4" "0,1"
newline
bitfld.long 0x0 22. "BANK11_STA_OFF_EN,Bank11 STA Off Enable" "0,1"
newline
bitfld.long 0x0 21. "RESERVED5,Reserved 5" "0,1"
newline
bitfld.long 0x0 20. "BANK10_STA_OFF_EN,Bank10 STA Off Enable" "0,1"
newline
bitfld.long 0x0 19. "RESERVED6,Reserved 6" "0,1"
newline
bitfld.long 0x0 18. "BANK9_STA_OFF_EN,Bank9 STA Off Enable" "0,1"
newline
bitfld.long 0x0 17. "RESERVED7,Reserved 7" "0,1"
newline
bitfld.long 0x0 16. "BANK8_STA_OFF_EN,Bank8 STA Off Enable" "0,1"
newline
bitfld.long 0x0 15. "RESERVED8,Reserved 8" "0,1"
newline
bitfld.long 0x0 14. "BANK7_STA_OFF_EN,Bank7 STA Off Enable" "0,1"
newline
bitfld.long 0x0 13. "RESERVED9,Reserved 9" "0,1"
newline
bitfld.long 0x0 12. "BANK6_STA_OFF_EN,Bank6 STA Off Enable" "0,1"
newline
bitfld.long 0x0 11. "RESERVED10,Reserved 10" "0,1"
newline
bitfld.long 0x0 10. "BANK5_STA_OFF_EN,Bank5 STA Off Enable" "0,1"
newline
bitfld.long 0x0 9. "RESERVED11,Reserved 11" "0,1"
newline
bitfld.long 0x0 8. "BANK4_STA_OFF_EN,Bank4 STA Off Enable" "0,1"
newline
bitfld.long 0x0 7. "RESERVED12,Reserved 12" "0,1"
newline
bitfld.long 0x0 6. "BANK3_STA_OFF_EN,Bank3 STA Off Enable" "0,1"
newline
bitfld.long 0x0 5. "RESERVED13,Reserved 13" "0,1"
newline
bitfld.long 0x0 4. "BANK2_STA_OFF_EN,Bank2 STA Off Enable" "0,1"
newline
bitfld.long 0x0 3. "RESERVED14,Reserved 14" "0,1"
newline
bitfld.long 0x0 2. "BANK1_STA_OFF_EN,Bank1 STA Off Enable" "0,1"
newline
bitfld.long 0x0 1. "RESERVED15,Reserved 15" "0,1"
newline
bitfld.long 0x0 0. "BANK0_STA_OFF_EN,Bank0 STA Off Enable" "0,1"
rgroup.long 0x388++0x7
line.long 0x0 "LMU_CPU1_STA_STATUS1,LMU CPU1 STA Status 1"
bitfld.long 0x0 29.--31. "BANK7_FSM_ST,Bank7 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK7_FSM_ST_REP_DONE,Bank7 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK6_FSM_ST,Bank6 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK6_FSM_ST_REP_DONE,Bank6 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK5_FSM_ST,Bank5 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK5_FSM_ST_REP_DONE,Bank5 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK4_FSM_ST,Bank4 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK4_FSM_ST_REP_DONE,Bank4 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK3_FSM_ST_REP_DONE,Bank3 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK2_FSM_ST,Bank2 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK2_FSM_ST_REP_DONE,Bank2 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK1_FSM_ST_REP_DONE,Bank1FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK0_FSM_ST_REP_DONE,Bank0 FSM St Rep Done" "0,1"
line.long 0x4 "LMU_CPU1_STA_STATUS2,LMU CPU1 STA Status 2"
bitfld.long 0x4 29.--31. "BANK15_FSM_ST,Bank15 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 28. "BANK15_FSM_ST_REP_DONE,Bank15 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 25.--27. "BANK14_FSM_ST,Bank14 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "BANK14_FSM_ST_REP_DONE,Bank14 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 21.--23. "BANK13_FSM_ST,Bank13 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "BANK13_FSM_ST_REP_DONE,Bank13 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 17.--19. "BANK12_FSM_ST,Bank12 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "BANK12_FSM_ST_REP_DONE,Bank12 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 13.--15. "BANK11_FSM_ST,Bank11 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "BANK11_FSM_ST_REP_DONE,Bank11 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 9.--11. "BANK10_FSM_ST,Bank10 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 8. "BANK10_FSM_ST_REP_DONE,Bank10 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 5.--7. "BANK9_FSM_ST,Bank9 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "BANK9_FSM_ST_REP_DONE,Bank9 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 1.--3. "BANK8_FSM_ST,Bank8 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "BANK8_FSM_ST_REP_DONE,Bank8 FSM St Rep Done" "0,1"
group.long 0x398++0x3
line.long 0x0 "LMU_CPU1_DYN_CTRL,LMU CPU1 Dynamic Control"
hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED0,Reserved 0"
newline
bitfld.long 0x0 13. "BANK3_DYN_PD,Bank3 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 12. "BANK3_DYN_MODE_EN,Bank3 Dynamic Mode Enable" "0,1"
newline
bitfld.long 0x0 10.--11. "RESERVED1,Reserved 1" "0,1,2,3"
newline
bitfld.long 0x0 9. "BANK2_DYN_PD,Bank2 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 8. "BANK2_DYN_MODE_EN,Bank2 Dynamic Mode Enable" "0,1"
newline
bitfld.long 0x0 6.--7. "RESERVED2,Reserved 2" "0,1,2,3"
newline
bitfld.long 0x0 5. "BANK1_DYN_PD,Bank1 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 4. "BANK1_DYN_MODE_EN,Bank1 Dynamic Mode Enable" "0,1"
newline
bitfld.long 0x0 2.--3. "RESERVED3,Reserved 3" "0,1,2,3"
newline
bitfld.long 0x0 1. "BANK0_DYN_PD,Bank0 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 0. "BANK0_DYN_MODE_EN,Bank0 Dynamic Mode Enable" "0,1"
rgroup.long 0x39C++0x3
line.long 0x0 "LMU_CPU1_DYN_STATUS,LMU CPU1 Dynamic Status"
bitfld.long 0x0 14.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 13. "BANK3_DYN_REP,Bank3 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 12. "BANK3_DYN_REP_REQ,Bank3 Dynamic Rep Request" "0,1"
newline
bitfld.long 0x0 10.--11. "BANK2_FSM_ST,Bank2 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 9. "BANK2_DYN_REP,Bank2 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 8. "BANK2_DYN_REP_REQ,Bank2 Dynamic Rep Request" "0,1"
newline
bitfld.long 0x0 6.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 5. "BANK1_DYN_REP,Bank1 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 4. "BANK1_DYN_REP_REQ,Bank1 Dynamic Rep Request" "0,1"
newline
bitfld.long 0x0 2.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 1. "BANK0_DYN_REP,Bank0 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 0. "BANK0_DYN_REP_REQ,Bank0 Dynamic Rep Request" "0,1"
group.long 0x3A8++0x3
line.long 0x0 "LMU_CPU2_STA_CFG,LMU CPU2 STA Configuration"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED0,Reserved 0"
newline
bitfld.long 0x0 14. "BANK7_STA_OFF_EN,Bank7 STA Off Enable" "0,1"
newline
bitfld.long 0x0 13. "RESERVED1,Reserved 1" "0,1"
newline
bitfld.long 0x0 12. "BANK6_STA_OFF_EN,Bank6 STA Off Enable" "0,1"
newline
bitfld.long 0x0 11. "RESERVED2,Reserved 2" "0,1"
newline
bitfld.long 0x0 10. "BANK5_STA_OFF_EN,Bank5 STA Off Enable" "0,1"
newline
bitfld.long 0x0 9. "RESERVED3,Reserved 3" "0,1"
newline
bitfld.long 0x0 8. "BANK4_STA_OFF_EN,Bank4 STA Off Enable" "0,1"
newline
bitfld.long 0x0 7. "RESERVED4,Reserved 4" "0,1"
newline
bitfld.long 0x0 6. "BANK3_STA_OFF_EN,Bank3 STA Off Enable" "0,1"
newline
bitfld.long 0x0 5. "RESERVED5,Reserved 5" "0,1"
newline
bitfld.long 0x0 4. "BANK2_STA_OFF_EN,Bank2 STA Off Enable" "0,1"
newline
bitfld.long 0x0 3. "RESERVED6,Reserved 6" "0,1"
newline
bitfld.long 0x0 2. "BANK1_STA_OFF_EN,Bank1 STA Off Enable" "0,1"
newline
bitfld.long 0x0 1. "RESERVED7,Reserved 7" "0,1"
newline
bitfld.long 0x0 0. "BANK0_STA_OFF_EN,Bank0 STA Off Enable" "0,1"
rgroup.long 0x3AC++0x3
line.long 0x0 "LMU_CPU2_STA_STATUS1,LMU CPU2 STA Status 1"
bitfld.long 0x0 29.--31. "BANK7_FSM_ST,Bank7 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK7_FSM_ST_REP_DONE,Bank7 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK6_FSM_ST,Bank6 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK6_FSM_ST_REP_DONE,Bank6 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK5_FSM_ST,Bank5 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK5_FSM_ST_REP_DONE,Bank5 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK4_FSM_ST,Bank4 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK4_FSM_ST_REP_DONE,Bank4 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK3_FSM_ST_REP_DONE,Bank3 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK2_FSM_ST,Bank2FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK2_FSM_ST_REP_DONE,Bank2 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK1_FSM_ST_REP_DONE,Bank1 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK0_FSM_ST_REP_DONE,Bank0 FSM St Rep Done" "0,1"
group.long 0x3B0++0x3
line.long 0x0 "LMU_CPU3_STA_CFG,LMU CPU3 STA Configuration"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED0,Reserved 0"
newline
bitfld.long 0x0 14. "BANK7_STA_OFF_EN,Bank7 STA Off Enable" "0,1"
newline
bitfld.long 0x0 13. "RESERVED1,Reserved 1" "0,1"
newline
bitfld.long 0x0 12. "BANK6_STA_OFF_EN,Bank6 STA Off Enable" "0,1"
newline
bitfld.long 0x0 11. "RESERVED2,Reserved 2" "0,1"
newline
bitfld.long 0x0 10. "BANK5_STA_OFF_EN,Bank5 STA Off Enable" "0,1"
newline
bitfld.long 0x0 9. "RESERVED3,Reserved 3" "0,1"
newline
bitfld.long 0x0 8. "BANK4_STA_OFF_EN,Bank4 STA Off Enable" "0,1"
newline
bitfld.long 0x0 7. "RESERVED4,Reserved 4" "0,1"
newline
bitfld.long 0x0 6. "BANK3_STA_OFF_EN,Bank3 STA Off Enable" "0,1"
newline
bitfld.long 0x0 5. "RESERVED5,Reserved 5" "0,1"
newline
bitfld.long 0x0 4. "BANK2_STA_OFF_EN,Bank2 STA Off Enable" "0,1"
newline
bitfld.long 0x0 3. "RESERVED6,Reserved 6" "0,1"
newline
bitfld.long 0x0 2. "BANK1_STA_OFF_EN,Bank1 STA Off Enable" "0,1"
newline
bitfld.long 0x0 1. "RESERVED7,Reserved 7" "0,1"
newline
bitfld.long 0x0 0. "BANK0_STA_OFF_EN,Bank0 STA Off Enable" "0,1"
rgroup.long 0x3B4++0x3
line.long 0x0 "LMU_CPU3_STA_STATUS1,LMU CPU3 STA Status 1"
bitfld.long 0x0 29.--31. "BANK7_FSM_ST,Bank7 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK7_FSM_ST_REP_DONE,Bank7 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK6_FSM_ST,Bank6 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK6_FSM_ST_REP_DONE,Bank6 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK5_FSM_ST,Bank5 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK5_FSM_ST_REP_DONE,Bank5 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK4_FSM_ST,Bank4 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK4_FSM_ST_REP_DONE,Bank4 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK3_FSM_ST_REP_DONE,Bank3 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK2_FSM_ST,Bank2FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK2_FSM_ST_REP_DONE,Bank2 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK1_FSM_ST_REP_DONE,Bank1 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK0_FSM_ST_REP_DONE,Bank0 FSM St Rep Done" "0,1"
group.long 0x3B8++0x3
line.long 0x0 "LMU_G2BIST_CTRL,LMU G2BIST Control"
bitfld.long 0x0 30. "DISABLE_DYN_REPAIR,1= disable dynamic memory repair" "?,1: disable dynamic memory repair"
newline
bitfld.long 0x0 29. "DISABLE_STA_REPAIR,1= disable static memory repair" "?,1: disable static memory repair"
newline
hexmask.long.byte 0x0 0.--4. 1. "LMU_G2BIST_MODE,1 = fuse load mode default mode when powered up. All repairable memories will be repaired by g2bist engine"
rgroup.long 0x3BC++0x3
line.long 0x0 "LMU_STATUS,LMU Status"
bitfld.long 0x0 20. "LMU_G2BIST_START,LMU_g to BIST Start" "0,1"
newline
hexmask.long.byte 0x0 12.--19. 1. "LMU_G2BIST_PWRDMN_RPR_REQ,LMU_g to BIST Powerdown RPR Request"
newline
hexmask.long.byte 0x0 8.--11. 1. "LMU_G2BIST_MODE,LMU_g to BIST Mode"
newline
hexmask.long.byte 0x0 4.--7. 1. "NXT_ST,NXT St"
newline
hexmask.long.byte 0x0 0.--3. 1. "REPAIR_FSM_ST,Repair FSM St"
group.long 0x3C0++0x3
line.long 0x0 "LMU_STA_CFG_MASK,LMU STA Configuration Mask"
hexmask.long.byte 0x0 0.--7. 1. "STA_CFG_MASK,STA Configuration Mask"
rgroup.long 0x3C4++0x7
line.long 0x0 "LMU_CPU2_STA_STATUS2,LMU CPU2 STA Status 2"
bitfld.long 0x0 29.--31. "BANK15_FSM_ST,Bank15 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK15_FSM_ST_REP_DONE,Bank15 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK14_FSM_ST,Bank14 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK14_FSM_ST_REP_DONE,Bank14 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK13_FSM_ST,Bank13 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK13_FSM_ST_REP_DONE,Bank13 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK12_FSM_ST,Bank12 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK12_FSM_ST_REP_DONE,Bank12 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK11_FSM_ST,Bank11 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK11_FSM_ST_REP_DONE,Bank11 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK10_FSM_ST,Bank10 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK10_FSM_ST_REP_DONE,Bank10 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK9_FSM_ST,Bank9 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK9_FSM_ST_REP_DONE,Bank9 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK8_FSM_ST,Bank8 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK8_FSM_ST_REP_DONE,Bank8 FSM St Rep Done" "0,1"
line.long 0x4 "LMU_CPU3_STA_STATUS2,LMU CPU3 STA Status 2"
bitfld.long 0x4 29.--31. "BANK15_FSM_ST,Bank15 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 28. "BANK15_FSM_ST_REP_DONE,Bank15 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 25.--27. "BANK14_FSM_ST,Bank14 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "BANK14_FSM_ST_REP_DONE,Bank14 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 21.--23. "BANK13_FSM_ST,Bank13 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "BANK13_FSM_ST_REP_DONE,Bank13 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 17.--19. "BANK12_FSM_ST,Bank12 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "BANK12_FSM_ST_REP_DONE,Bank12 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 13.--15. "BANK11_FSM_ST,Bank11 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "BANK11_FSM_ST_REP_DONE,Bank11 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 9.--11. "BANK10_FSM_ST,Bank10 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 8. "BANK10_FSM_ST_REP_DONE,Bank10 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 5.--7. "BANK9_FSM_ST,Bank9 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "BANK9_FSM_ST_REP_DONE,Bank9 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 1.--3. "BANK8_FSM_ST,Bank8 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "BANK8_FSM_ST_REP_DONE,Bank8 FSM St Rep Done" "0,1"
group.long 0x3D0++0x2F
line.long 0x0 "CPU3_HOST_WKUP_MASK,CPU3 Host Wakeup Mask"
hexmask.long.word 0x0 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x4 "CPU3_HOST_WKUP_POL,CPU3 Host Wakeup Polarity"
hexmask.long.word 0x4 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
line.long 0x8 "CPU3_HOST_WKUP_CTRL,CPU3 Host Wakeup Control"
hexmask.long.word 0x8 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x8 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0xC "CPU3_CTRL,CPU3 Control"
bitfld.long 0xC 16.--18. "APU_SUBSYS3_HOST,APU Subsystem 2 Host" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 5. "GENERIC_TIMER_EN2,Generic Timer Enable 2" "0,1"
newline
bitfld.long 0xC 4. "SOC_USE_REF_ONLY,SoC Use Ref Only" "0,1"
newline
bitfld.long 0xC 3. "CPU3_CP15_SLP_BYPASS_EN,CPU3 CP15 Sleep Bypass Enable" "0,1"
newline
bitfld.long 0xC 2. "CPU3_CP15_SLP_BYPASS_VAL,CPU3 CP15 Sleep Bypass Value" "0,1"
newline
bitfld.long 0xC 0. "CPU3_MSG_RDY_MASK,CPU3 Message Ready Mask" "0,1"
line.long 0x10 "CPU3_DVFS_CTRL,CPU3 DVFS Control"
hexmask.long.byte 0x10 25.--31. 1. "UART_VOL_VAL,UART Vol Value"
newline
bitfld.long 0x10 24. "CPU3_AHB1_INDEX_SEL_METHOD,CPU3 AHB1 index select method" "0,1"
newline
hexmask.long.byte 0x10 20.--23. 1. "CPU3_INACTIVE_AHB1_INDEX,CPU3 Inactive AHB1 Index"
newline
hexmask.long.byte 0x10 16.--19. 1. "CPU3_ACTIVE_AHB1_INDEX,CPU3 Active AHB1 Index"
newline
hexmask.long.byte 0x10 12.--15. 1. "CPU3_INACTIVE_SYS_INDEX,CPU3 Inactive System Index"
newline
hexmask.long.byte 0x10 8.--11. 1. "CPU3_ACTIVE_SYS_INDEX,CPU3 Active System Index"
newline
hexmask.long.byte 0x10 4.--7. 1. "CPU3_INACTIVE_INDEX,CPU3 Inactive Index"
newline
hexmask.long.byte 0x10 0.--3. 1. "CPU3_ACTIVE_INDEX,CPU3 Active Index"
line.long 0x14 "CPU3_FREQ_REG1,CPU3 Frequency 1"
hexmask.long 0x14 0.--31. 1. "CPU3_FREQ_REG1,CPU3 Frequency 1"
line.long 0x18 "CPU3_FREQ_REG2,CPU3 Frequency 2"
hexmask.long 0x18 0.--31. 1. "CPU3_FREQ_REG2,CPU3Frequency 2"
line.long 0x1C "CPU3_PLL_EN_REG,CPU3 PLL Enable"
hexmask.long 0x1C 0.--31. 1. "CPU3_PLL_EN_REG,CPU3 PLL Enable"
line.long 0x20 "CPU3_VOL_REG1,CPU3 Voltage 1"
hexmask.long 0x20 0.--31. 1. "CPU3_VOL_REG1,CPU3 Voltage 1"
line.long 0x24 "CPU3_VOL_REG2,CPU3 Voltage 2"
hexmask.long 0x24 0.--31. 1. "CPU3_VOL_REG2,CPU3 Voltage 2"
line.long 0x28 "CPU3_VOL_REG3,CPU3 Voltage 3"
hexmask.long 0x28 0.--31. 1. "CPU3_VOL_REG3,CPU3 Voltage 3"
line.long 0x2C "CPU3_VOL_REG4,CPU3 Voltage 4"
hexmask.long 0x2C 0.--31. 1. "CPU3_VOL_REG4,CPU3 Voltage 4"
tree.end
tree "APU1"
base ad:0x44258400
rgroup.long 0x0++0x3
line.long 0x0 "APU_IP_REVISION,APU IP revision"
hexmask.long.word 0x0 0.--15. 1. "IP_REV,IP revision"
group.long 0x4++0x1F
line.long 0x0 "CTRL,Control"
bitfld.long 0x0 25. "CPU1_MSG_RDY_MASK,CPU1 Message Ready Mask" "0,1"
newline
bitfld.long 0x0 24. "FW_CP15_SLEEP,FW CP15 Sleep" "0,1"
newline
bitfld.long 0x0 23. "CP_15_SLEEP_MASK,CP15 Sleep Mask" "0,1"
newline
bitfld.long 0x0 22. "FW_IPS_CP15_SLEEP,FW IPS CP15 Sleep" "0,1"
newline
bitfld.long 0x0 21. "IPS_CP15_SLEEP_MASK,IPS CP15 Sleep Mask" "0,1"
newline
bitfld.long 0x0 17. "SDU_SLP_RDY_MASK,SDU Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 15. "APU_SW_ACC_RST,APU SW ACC Reset" "0,1"
newline
bitfld.long 0x0 14. "RST_APU_SLPCLK_TIMER,Reset APU Sleep Clock Timer" "0,1"
newline
bitfld.long 0x0 13. "SW_TIMER_LD,SW Timer" "0,1"
newline
bitfld.long 0x0 12. "APU_NO_TBTT_RESET,APU No TBTT Reset" "0,1"
newline
bitfld.long 0x0 11. "APU_AUTO_CALIBRATE,APU Auto Calibrate" "0,1"
newline
bitfld.long 0x0 10. "APU_ALLOW_AUTO_LOAD,APU Allow Auto load" "0,1"
newline
bitfld.long 0x0 9. "USE_HOST_INTR_SLP,Use Host Interrupt Sleep" "0,1"
newline
bitfld.long 0x0 8. "ENTER_ALL_SLEEP_MODE,Enter All Sleep Mode" "0,1"
newline
bitfld.long 0x0 7. "APU_CAL_DONE_CLEAR_METHOD,1- use falling edge of apu_sw_acc_rst to clear the apu_cal_done after FW polls the apu_cal_done = 1" "0,1"
newline
bitfld.long 0x0 4.--6. "APU_SUBSYS1_HOST,APU Subsystem1 Host" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3. "WLCOMN_USE_NOM_PWR_BYP,WLAN comman domain uses nominal voltage" "0,1"
newline
bitfld.long 0x0 1. "FW_CPU1_PD,FW CPU1 Pd" "0,1"
newline
bitfld.long 0x0 0. "CPU1_PD_MASK,CPU1 Pd Mask" "0,1"
line.long 0x4 "TIMER_PWR_MODE,Timer Power Mode"
bitfld.long 0x4 24. "USE_HSIC_SLP_SYNC,Use HSIC Sleep Sync" "0,1"
newline
bitfld.long 0x4 23. "XOSC_ON_WHILE_SLEEP,XOSC On While Sleep" "0,1"
newline
bitfld.long 0x4 22. "GENERIC_TIMER_BYPASS,When set to 1 generic_alarm_en2 will be used for generic_alarm_en1" "0,1"
newline
bitfld.long 0x4 21. "GENERIC_TIMER_EN,Enable sleep timer to generate interrupt when value matches generic timer value. Debug only" "0,1"
newline
bitfld.long 0x4 18. "ENA_FAST_WKUP,Enable Fast Wakeup" "0,1"
newline
bitfld.long 0x4 17. "SOC_XOSC_PWR_ON,SoC XOSC Power on" "0,1"
newline
bitfld.long 0x4 13. "DIS_APU_INTR_ON_WAKEUP,Disable APU Interrupt on Wakeup" "0,1"
newline
bitfld.long 0x4 12. "XP_OPT_EN,Set to 1 to enable the sleep FSM to look for wakeup req after power shutdown and before reference clock shutdown." "0,1"
newline
bitfld.long 0x4 7. "DIS_GATED_SLP_CLK,Disable Gated Sleep Clock" "0,1"
newline
bitfld.long 0x4 6. "WL2_BCN_ALARM_TIMER_EN,WLAN2 beacon alarm timer enable" "0,1"
newline
bitfld.long 0x4 5. "WL_BCN_ALARM_TIMER_EN,WLAN beacon alarm timer enable" "0,1"
newline
bitfld.long 0x4 4. "SLP_CLK_TIMER_EN,free running sleep clock timer enable" "0,1"
newline
bitfld.long 0x4 0. "MCI_XP_REQ_MASK,MCI XP Request Mask" "0,1"
line.long 0x8 "PWR_CTRL,Power Control"
bitfld.long 0x8 15. "PCIE_P_REQ_MASK_FOR_SLPFSM,Mask pcie_p_req and pcie_xp_req for slp_fsm" "0,1"
newline
bitfld.long 0x8 14. "DLY_NON_UDR_RSTB,Delay non-UDR RSTb" "0,1"
newline
bitfld.long 0x8 13. "RFU_IN_WLAN_DOMAIN,RFU WLAN mode" "0,1"
newline
bitfld.long 0x8 12. "SOC_USE_UNSYNC_VOL_LVL,SoC Use unSync Vol Level" "0,1"
newline
bitfld.long 0x8 11. "SOC_USE_NOM_VOL_BYP,SoC Use Nominal Vol Bypass" "0,1"
newline
bitfld.long 0x8 10. "CLK_DIV_RESETB_REFCLK,CLK_DIV_RESETB Reference Clock" "0,1"
newline
bitfld.long 0x8 9. "CLK_DIV_RESETB_ENABLE,CLK_DIV_RESETB Enable" "0,1"
newline
bitfld.long 0x8 8. "SRAM_PD_EN,APU SRAM power down enable" "0,1"
newline
bitfld.long 0x8 7. "XOSC_OFF_DURING_POWER_OFF,XOSC Off During Power Off" "0,1"
newline
bitfld.long 0x8 6. "NON_UDR_RSTB_EN,APU non-UDR reset enable" "0,1"
newline
bitfld.long 0x8 5. "ISO_ENABLE_REFCK,ISO Enable Reference Clock" "0,1"
newline
bitfld.long 0x8 4. "DLY_UDR2ISO,UDR firewall_bar to isolation delay enable" "0,1"
newline
bitfld.long 0x8 3. "APU_ISO_CELL_EN,APU isolation enable" "0,1"
newline
bitfld.long 0x8 2. "APU_UDR_FIREWALL_BAR_EN,APU UDR enable" "0,1"
newline
bitfld.long 0x8 1. "APU_SW_PD_EN,APU switch power down enable" "0,1"
newline
bitfld.long 0x8 0. "APU_PD_CTRL_EN,APU power domain control enable" "0,1"
line.long 0xC "PLL_CTRL,PLL Control"
bitfld.long 0xC 9. "FW_PLL1_EN_SET,Fw sets pll_en[1] value when apu_pll_ctrl[4] = 1 " "0,1"
newline
bitfld.long 0xC 8. "FW_USE_PLL1,When set to 1 FW controls pll_en[1] value (pll0 is Tcpu in Skyhawk)" "0,1"
newline
bitfld.long 0xC 5. "FW_PLL0_EN_SET,Fw sets pll_en[0] value when apu_pll_ctrl[4] = 1 " "0,1"
newline
bitfld.long 0xC 4. "FW_USE_PLL0,When set to 1 FW controls pll_en[0] value (pll0 is Tcpu in Skyhawk)" "0,1"
newline
bitfld.long 0xC 1. "DIS_APU_PLL_EN1,When set to 1 apu_pll_en[1]=0 (pll1 is Tsoc in Skyhawk)" "0,1"
newline
bitfld.long 0xC 0. "DIS_APU_PLL_EN0,When set to 1 apu_pll_en[0]=0 (pll0 is Tcpu in Skyhawk)" "0,1"
line.long 0x10 "PLL_DIS_CNT,PLL Disable Count"
hexmask.long.word 0x10 0.--15. 1. "PLL_DIS_CNT,PLL disable count in reference clocks"
line.long 0x14 "STABLE_CNT,Stable Count"
hexmask.long.word 0x14 16.--31. 1. "PLL_STABLE_CNT,PLL stable count in sleep clocks after APU asserts pll_en"
newline
hexmask.long.word 0x14 0.--15. 1. "XOSC_STABLE_CNT,XOSC stable count in sleep clocks after APU asserts xosc_en"
line.long 0x18 "CPU1_HOST_WKUP_MASK,CPU1 Host Wakeup Mask"
hexmask.long.word 0x18 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x1C "CPU1_HOST_WKUP_POL,CPU1 Host Wakeup Polarity"
hexmask.long.word 0x1C 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
rgroup.long 0x24++0xB
line.long 0x0 "CAL_WIN_CNT,Calibration Window Count"
hexmask.long 0x0 0.--31. 1. "APU_CAL_WIN_CNT,Number of calibration clocks elapsed during calibration window"
line.long 0x4 "AUTO_10US,Auto 10us"
hexmask.long 0x4 0.--31. 1. "APU_AUTO_10US,auto alarm value loaded during auto calibration"
line.long 0x8 "ACC_CNT,Accumulation Count"
hexmask.long 0x8 0.--31. 1. "APU_ACC_CNT,number of sleep clocks elapsed during the calibration window"
group.long 0x30++0x3
line.long 0x0 "CAL_WIN_SIZE,Calibration Window Size"
hexmask.long 0x0 0.--31. 1. "APU_CAL_WIN_SIZE,calibration window size in number of calibration clocks."
rgroup.long 0x34++0x7
line.long 0x0 "SLP_CLK_TIMER,Sleep Clock Timer"
hexmask.long 0x0 0.--31. 1. "APU_SLP_CLK_TIMER,reads back the current value of the free running sleep clock counter."
line.long 0x4 "STATUS_RD,Status Read"
hexmask.long.word 0x4 16.--31. 1. "HOST_WKUP_AFTER_MASK,Host Wakeup After Mask"
newline
hexmask.long.byte 0x4 12.--15. 1. "APU_SLEEP_FSM_STATE,APU Sleep FSM State"
newline
bitfld.long 0x4 11. "APU_SOC_CLK_EN1,APU SoC Clock Enable 1" "0,1"
newline
bitfld.long 0x4 10. "APU_SOC_CLK_EN2,APU SoC Clock Enable 2" "0,1"
newline
bitfld.long 0x4 9. "APU_SOC_CLK_EN3,APU SoC Clock Enable 3" "0,1"
newline
bitfld.long 0x4 8. "APU_SYS_CLK_EN,APU System Clock Enable" "0,1"
newline
bitfld.long 0x4 7. "APU_MAC_CLK_EN1,APU MAC Clock Enable 1" "0,1"
newline
bitfld.long 0x4 6. "APU_BT_CLK_EN,APU Bluetooth Clock Enable" "0,1"
newline
bitfld.long 0x4 5. "APU_MAC_CLK_EN2,APU MAC Clock Enable 2" "0,1"
newline
bitfld.long 0x4 4. "APU_BT2_CLK_EN,APU Bluetooth2 Clock Enable" "0,1"
newline
bitfld.long 0x4 3. "APU_XOSC_STABLE,APU XOSC Stable" "0,1"
newline
bitfld.long 0x4 2. "APU_PLL_STABLE_1,APU PLL Stable[1]" "0,1"
newline
bitfld.long 0x4 1. "APU_PLL_STABLE_0,T1 PLL stable" "0,1"
newline
bitfld.long 0x4 0. "CALIBRATION_STATUS,Calibration Status" "0,1"
group.long 0x3C++0x7
line.long 0x0 "STABLE_CNT2,Stable Count 2"
hexmask.long.word 0x0 0.--15. 1. "PLL2_STBL_CNT,T3 stable count in reference clocks"
line.long 0x4 "DYN_PLL_MASK,Dynamic PLL Mask"
hexmask.long.word 0x4 16.--31. 1. "HOST_WKUP_PLL_REQ_MASK,When mask is 0 host_wkup is treated as pll_req if soc_use_ref_only = 0"
newline
bitfld.long 0x4 14. "FULL_SLP_MASK,Full Sleep Mask" "0,1"
newline
bitfld.long 0x4 13. "GEN_TIMER_WKUP_PLL_REQ_MASK,When mask is 0 gen_timer_wkup_wkup is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 12. "SD_CLK_SWITCH_OK_MASK,SD Clock Switch Ok Mask" "0,1"
newline
bitfld.long 0x4 11. "CPU2_CP15_PLL_REQ_MASK,When mask is 0 !cpu2_cp15_sleep is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 10. "BLE_SLP_RDY_PLL_REQ_MASK,When mask is 0 !ble_slp_rdy is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 9. "BT_SLP_RDY_PLL_REQ_MASK,When mask is 0 !bt_slp_rdy is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 8. "BT_CLK_REQ_PLL_REQ_MASK,When mask is 0 bt_clk_req is treated as pll_req if soc_use_ref_only = 0" "0,1"
newline
bitfld.long 0x4 7. "BT_AES_CLK_REQ_MASK,When mask is 0 bt_aes_clk_req is treated as pll_req of bt_aes_nco_mode =0" "0,1"
newline
bitfld.long 0x4 6. "BRF_PLL_REQ_MASK,When mask =0 brf_pll_req treated as pll_req" "0,1"
newline
bitfld.long 0x4 5. "BT_PLL_REQ_MASK,When mask =0 bt_pll_req treated as pll_req" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "TESTBUS_RD1,Testbus Read 1"
hexmask.long.word 0x0 16.--31. 1. "DVFS_TIMER,DVFS timer"
newline
hexmask.long.word 0x0 0.--15. 1. "TIMER_CNTR,DVFS internal counter"
line.long 0x4 "TESTBUS_RD2,Testbus Read 2"
hexmask.long 0x4 0.--31. 1. "APU_TESTBUS_RD2,Last 8 FSM state changes are stored in the register"
group.long 0x4C++0x13
line.long 0x0 "GENERIC_TIMER_CNT,Generic Timer Count"
hexmask.long 0x0 0.--31. 1. "GENERIC_TIMER_CNT,Generic Timer Count"
line.long 0x4 "CPU1_HOST_WKUP_CTRL,CPU1 Host Wakeup Control"
hexmask.long.word 0x4 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x4 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0x8 "DYN_PLL_CLK_EXT_CTRL,Dynamic PLL Clock Ext Control"
bitfld.long 0x8 31. "BT_AES_PLL_EXT_EN,Bluetooth AES PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 30. "BT_AES_CLK_EXT_EN,BLuetooth AES Clock Ext Enable" "0,1"
newline
bitfld.long 0x8 29. "BT2_AES_PLL_EXT_EN,Bluetooth2 AES PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 28. "BT2_AES_CLK_EXT_EN,BLuetooth2 AES Clock Ext Enable" "0,1"
newline
bitfld.long 0x8 12. "CPU3_INACTIVE_EXT_EN,CPU3 Inactive Ext Enable" "0,1"
newline
bitfld.long 0x8 11. "CPU3_PLL_EXT_EN,CPU3 PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 10. "DVFS_T1_EXT_EN,DVFS T1 Ext Enable" "0,1"
newline
bitfld.long 0x8 9. "T3_EXT_EN,T3 Ext Enable" "0,1"
newline
bitfld.long 0x8 8. "T1_EXT_EN,T1 Ext Enable" "0,1"
newline
bitfld.long 0x8 7. "CPU2_INACTIVE_EXT_EN,CPU2 Inactive Ext Enable" "0,1"
newline
bitfld.long 0x8 6. "CPU2_PLL_EXT_EN,CPU2 PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 5. "CPU1_INACTIVE_EXT_EN,CPU1 Inactive Ext Enable" "0,1"
newline
bitfld.long 0x8 4. "CPU1_PLL_EXT_EN,CPU1 PLL Ext Enable" "0,1"
newline
bitfld.long 0x8 2. "SOC_CLK3_EXT_EN,SoC Clock 3 Ext Enable" "0,1"
newline
bitfld.long 0x8 1. "SOC_CLK2_EXT_EN,SoC Clock 2 Ext Enable" "0,1"
newline
bitfld.long 0x8 0. "SOC_CLK1_EXT_EN,SoC Clock 1 Ext Enable" "0,1"
line.long 0xC "GENERIC_SLP_START_VAL,Generic Sleep Start Value"
hexmask.long 0xC 0.--31. 1. "GENERIC_SLP_START_VAL,Generic Sleep Start Value"
line.long 0x10 "DLY_HOST_CTRL,Delay Host Control"
hexmask.long.tbyte 0x10 8.--31. 1. "DLY_HOST_WKUP_CNT,Number of sleep clocks to delay host wakeup interrupt"
newline
bitfld.long 0x10 7. "RST_HOST_WKUP_CNT,Reset Host Wakeup Count" "0,1"
newline
hexmask.long.byte 0x10 3.--6. 1. "HOST_WKUP_SEL,selects which host wakeup to be delayed out of 16 hosts"
newline
bitfld.long 0x10 0. "DLY_HOST_WKUP_EN,Delay Host Wakeup Enable" "0,1"
rgroup.long 0x60++0x3
line.long 0x0 "HOST_WKUP_CNT,Host Wakeup Count"
hexmask.long.tbyte 0x0 0.--23. 1. "HOST_WKUP_DLY_CNT,Host Wakeup Delay Count"
group.long 0x64++0x13
line.long 0x0 "CPU2_HOST_WKUP_MASK,CPU2 Host Wakeup Mask"
hexmask.long.word 0x0 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x4 "CPU2_HOST_WKUP_POL,CPU2 Host Wakeup Polarity"
hexmask.long.word 0x4 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
line.long 0x8 "CPU2_HOST_WKUP_CTRL,CPU2 Host Wakeup Control"
hexmask.long.word 0x8 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x8 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0xC "CPU2_CTRL,CPU2 Control"
bitfld.long 0xC 16.--18. "APU_SUBSYS2_HOST,APU Subsystem 2 Host" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 5. "GENERIC_TIMER_EN2,Generic Timer Enable 2" "0,1"
newline
bitfld.long 0xC 4. "SOC_USE_REF_ONLY,SoC Use Ref Only" "0,1"
newline
bitfld.long 0xC 3. "CPU2_CP15_SLP_BYPASS_EN,CPU2 CP15 Sleep Bypass Enable" "0,1"
newline
bitfld.long 0xC 2. "CPU2_CP15_SLP_BYPASS_VAL,CPU2 CP15 Sleep Bypass Value" "0,1"
newline
bitfld.long 0xC 0. "CPU2_MSG_RDY_MASK,CPU2 Message Ready Mask" "0,1"
line.long 0x10 "WLAN_PWR_CTRL_DLY,Wlan domain FSM Power Control Delay"
hexmask.long 0x10 0.--31. 1. "PWR_CTRL_DLY,Wlan domain FSM Power Control Delay"
rgroup.long 0x78++0x3
line.long 0x0 "STATUS2,Status 2"
bitfld.long 0x0 31. "CPU1_APU_PD,CPU1 to APU powerdown" "0,1"
newline
bitfld.long 0x0 30. "AMU3_CP15_SLEEP,CPU3 CP15 Sleep" "0,1"
newline
bitfld.long 0x0 29. "AMU2_CP15_SLEEP,CPU2 CP15 Sleep" "0,1"
newline
bitfld.long 0x0 28. "AMU1_CP15_SLEEP,CPU1 CP15 Sleep" "0,1"
newline
bitfld.long 0x0 27. "APU_INTR_WLAN_WAKEUP1,APU wlan1 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 26. "APU_INTR_WLAN_WAKEUP2,APU wlan2 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 25. "APU_DVFS_CLK_SEL,APU DVFS Clock Select" "0,1"
newline
bitfld.long 0x0 24. "BT2_CLK_REQ,BT2 clk req" "0,1"
newline
bitfld.long 0x0 23. "BT_CLK_REQ,BT clk req" "0,1"
newline
bitfld.long 0x0 22. "BCA_SLNA_ON,BCA SLNA On" "0,1"
newline
bitfld.long 0x0 21. "BCA_CLK_EN,APU BCA Clock Enable" "0,1"
newline
bitfld.long 0x0 20. "BCA_CLK_REQ,BCA Clock Request" "0,1"
newline
bitfld.long 0x0 19. "PCIE_XP_REQ,PCIe XP req" "0,1"
newline
bitfld.long 0x0 18. "PCIE_P_REQ,PCIe P req" "0,1"
newline
bitfld.long 0x0 17. "APU_SOC_CAU_LDO_XOSC_EN,APU SoC CAU LOD XOSC Enable" "0,1"
newline
bitfld.long 0x0 16. "APU_CAU_BT_ACTIVE,APU CAU Bluetooth Active" "0,1"
newline
bitfld.long 0x0 15. "APU_WL_RF_CLK_EN2,WLAN RFU1 clk enable" "0,1"
newline
bitfld.long 0x0 14. "APU_WL_RF_CLK_EN1,WLAN RFU1 clk enable" "0,1"
newline
bitfld.long 0x0 13. "APU_BBUD_CLK_EN2,bbud1 clk enable" "0,1"
newline
bitfld.long 0x0 12. "APU_BBUD_CLK_EN1,bbud2 clk enable" "0,1"
newline
bitfld.long 0x0 11. "APU_INTR_BT2_WAKEUP,APU BT2 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 10. "APU_INTR_BT_WAKEUP,APU BT2 wakeup interrupt" "0,1"
newline
bitfld.long 0x0 9. "APU_BRF2_CLK_EN,BRF2 clk enable" "0,1"
newline
bitfld.long 0x0 8. "APU_BRF_CLK_EN,BRF clk enable" "0,1"
newline
bitfld.long 0x0 7. "APU_BT2_AES_CLK_SEL,BT2 AES clk select" "0,1"
newline
bitfld.long 0x0 6. "APU_BT_AES_CLK_SEL,BT AES clk select" "0,1"
newline
bitfld.long 0x0 5. "APU_BT2_AES_CLK_EN,BT2 AES Clk enable" "0,1"
newline
bitfld.long 0x0 4. "APU_BT_AES_CLK_EN,BT AES Clk enable" "0,1"
newline
bitfld.long 0x0 3. "LMU_G2BIST_FINISH,LMU G2BIST finish" "0,1"
newline
bitfld.long 0x0 2. "CPU3_MSG_RDY_INT,CPU3 Message Ready" "0,1"
newline
bitfld.long 0x0 1. "CPU2_MSG_RDY_INT,CPU2 Message Ready" "0,1"
newline
bitfld.long 0x0 0. "CPU1_MSG_RDY_INT,CPU1 Message Ready" "0,1"
group.long 0x7C++0xB
line.long 0x0 "WLAN_PWR_CTRL_DLY2,Wlan domain FSM Power Control Delay 2"
hexmask.long 0x0 0.--31. 1. "PWR_CTRL_DLY2,WLAN domain FSM power control delay 2"
line.long 0x4 "WL_CTRL,WLAN Control"
bitfld.long 0x4 31. "WL_HOST_SLP_RDY,WLAN Host Sleep Ready" "0,1"
newline
bitfld.long 0x4 25. "WLAN_USE_UNSYNC_PWR_LVL,WLAN Use Unsync Power Level" "0,1"
newline
bitfld.long 0x4 24. "FW_FORCE_WL_PWRUP,FW Force WLAN Powerup" "0,1"
newline
bitfld.long 0x4 22. "APU_WLAN_RF_MUX_SEL,APU WLAN RF Mux Select" "0,1"
newline
bitfld.long 0x4 21. "APU_TSF_AUTO_UPDATE,APU TSF Auto Update" "0,1"
newline
hexmask.long.byte 0x4 16.--20. 1. "APU_TSF_UPD_CNT,APU TSF Update Count"
newline
bitfld.long 0x4 15. "APU_FW_RST_PE,APU FW Reset PE" "0,1"
newline
bitfld.long 0x4 10. "USE_WL_PWR_RDY_FOR_WLRF_CLK,Use WLAN Power Ready for WL RF Clock" "0,1"
newline
bitfld.long 0x4 9. "WL_USE_NOM_PWR_BYP,WLAN Use Nominal Power Bypass" "0,1"
newline
bitfld.long 0x4 7. "USE_WL_INTR_SLP,Use WLAN Interrupt Sleep" "0,1"
newline
bitfld.long 0x4 6. "APU_WKUP_WLRF_RX,APU Wakeup WL RF Rx" "0,1"
newline
bitfld.long 0x4 5. "IDLE2ISO_DLY_EN,Delay from idle to iso to ensure delay from bbud_non_udr_rst_b =0 to wlan_iso_en = 1" "0,1"
newline
bitfld.long 0x4 2. "WL_SLP_RDY_FW,WLAN Sleep Ready Firmware" "0,1"
newline
bitfld.long 0x4 1. "WL_SLP_RDY_MASK,WLAN Sleep Ready Mask" "0,1"
newline
bitfld.long 0x4 0. "WL_SLP_RDY,WLAN Sleep Ready" "0,1"
line.long 0x8 "WL_WKUP_MASK,WLAN Wakeup Mask"
hexmask.long.word 0x8 16.--31. 1. "WL_HOST_MAP,WLAN Host Map"
newline
bitfld.long 0x8 12. "IHB_WL_XPP_DYNPLL_REQ_MASK,When mask = 0 ihb_wl_xpp_req is treated as pll_req" "0,1"
newline
bitfld.long 0x8 11. "WL_SLP_RDY_DYNPLL_REQ_MASK,When mask = 0 !wl_slp_rdy is treated as pll_req" "0,1"
newline
bitfld.long 0x8 10. "WL_TIMER_DYNPLL_REQ_MASK,When mask = 0 wlan_timer_xpp req is treated as pll_req" "0,1"
newline
bitfld.long 0x8 9. "WL_HOST_DYNPLL_REQ_MASK,When mask = 0 wlan_host_wkup is treated as pll_req" "0,1"
newline
bitfld.long 0x8 8. "WL_RF_PLL_DYNPLL_REQ_MASK,When mask = 0 wl_rf_pll_req is treated as pll_req" "0,1"
newline
bitfld.long 0x8 3. "BCA_MWS_WKUP_XP_MASK,BCA MWS Wakeup XP Mask" "0,1"
newline
bitfld.long 0x8 2. "WL_RF_PLL_REQ_MASK,WLAN RF PLL Request Mask" "0,1"
newline
bitfld.long 0x8 1. "BBUD_T2_PLL_REQ_MASK,BBUD T2 PLL Request Mask" "0,1"
newline
bitfld.long 0x8 0. "WL_BCN_TIMER_WKUP_MASK,WLAN Beacon Timer Wakeup Mask" "0,1"
rgroup.long 0x88++0x7
line.long 0x0 "WL_STATUS,WLAN Status"
bitfld.long 0x0 31. "BCA_CLK_REQ,BCA Clock Request" "0,1"
newline
bitfld.long 0x0 30. "BBUD_T2_PLL_REQ,BBUD T2 PLL Request" "0,1"
newline
bitfld.long 0x0 29. "WLRF_PLL_REQ,WL RF PLL Request" "0,1"
newline
bitfld.long 0x0 28. "TIMER_WAKEUP,Timer Wakeup" "0,1"
newline
bitfld.long 0x0 27. "TIMER_XPP_WAKEUP,Timer XPP Wakeup" "0,1"
newline
bitfld.long 0x0 26. "WL_TIMER_INTR,WLAN Timer Interrupt" "0,1"
newline
bitfld.long 0x0 25. "WLAN_HOST_WKUP,WLAN Host Wakeup" "0,1"
newline
bitfld.long 0x0 24. "WL_HOST_INTR_REF,WLAN Host Interrupt Reference" "0,1"
newline
bitfld.long 0x0 23. "WL_PWR_RDY,WLAN Power Ready" "0,1"
newline
bitfld.long 0x0 22. "SOC_VOL_REACHED,SoC Volume Reached" "0,1"
newline
bitfld.long 0x0 21. "WLAN_VOL_REACHED,WLAN Volume Reached" "0,1"
newline
bitfld.long 0x0 20. "APU_WLAN_SRAM_PD,APU WLAN SRAM Enable" "0,1"
newline
bitfld.long 0x0 19. "APU_WLAN_ISO_EN,APU WLAN ISO Enable" "0,1"
newline
bitfld.long 0x0 18. "APU_WLAN_CLK_DIV_RSTB,APU WLAN Clock Div RSTb" "0,1"
newline
bitfld.long 0x0 17. "APU_WLAN_UDR_FIREWALL_B,APU WLAN UDR Firewall b" "0,1"
newline
bitfld.long 0x0 16. "APU_WLAN_SWITCH_PD,APU WLAN Switch Pd" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "APU_WL_ST,APU WLAN St"
newline
bitfld.long 0x0 10. "APU_BBUD_NON_UDR_RST_B,APU BBUD non-UDR RSTb" "0,1"
newline
bitfld.long 0x0 9. "APU_RTDP_WU_RSTB,APU RTDP WU RSTb" "0,1"
newline
bitfld.long 0x0 8. "BCA_MWS_WKUP_XP,BCA MWS Wakeup XP" "0,1"
newline
bitfld.long 0x0 7. "APU_PLL3_EN,APU PLL3 Enable" "0,1"
newline
bitfld.long 0x0 6. "APU_PLL1_EN,APU PLL1 Enable" "0,1"
newline
bitfld.long 0x0 4.--5. "APU_WL_RF_CTRL,APU WLAN RF Control for PE1/PE2" "0,1,2,3"
newline
bitfld.long 0x0 3. "APU_WL_SLP_RDY_AFTER_MASK,APU WLAN Sleep Ready After Mask" "0,1"
newline
bitfld.long 0x0 2. "APU_WL_RF_CLK_EN,APU WLAN Ref Clock Enable" "0,1"
newline
bitfld.long 0x0 1. "APU_BBUD_CLK_EN,APU BBUD Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_MAC_CLK_EN,APU MAC Clock Enable" "0,1"
line.long 0x4 "WL_ALARM_RD,WLAN Alarm Readback"
hexmask.long 0x4 0.--31. 1. "APU_WL_ALARM_RD,reads back current beacon timer alarm value"
group.long 0x90++0x27
line.long 0x0 "WL_BCN_XP_ALARM,WLAN Beacon Alarm"
hexmask.long 0x0 0.--31. 1. "WL_BCN_XP_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock and power"
line.long 0x4 "WL_BCN_INTR_ALARM,WLAN Beacon Interrupt Alarm"
hexmask.long 0x4 0.--31. 1. "WL_BCN_INTR_ALARM,number of ref clocks after WLAN beacon timer request to firmware wakeup"
line.long 0x8 "WL_HOST_INTR_ALARM,WLAN Host Interrupt Alarm"
hexmask.long 0x8 0.--31. 1. "WL_HOST_INTR_ALARM,number of ref clocks after WLAN host request to firmware wakeup"
line.long 0xC "WL_BCN_PLL_ALARM,WLAN Beacon PLL Alarm"
hexmask.long 0xC 0.--31. 1. "WL_BCN_PLL_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock power and PLL"
line.long 0x10 "TSF_REF_FACTOR,TSF Reference Factor"
hexmask.long.tbyte 0x10 0.--18. 1. "TSF_REF_FACTOR,number of 1us in 1 reference clock"
line.long 0x14 "TSF_SLEEP_FACTOR,TSF Sleep Factor"
hexmask.long 0x14 0.--27. 1. "TSF_SLEEP_FACTOR,number of 1us in 1 sleep clock"
line.long 0x18 "BBUD_UDR_ISO_CNT,BBUD UDR ISO Count"
hexmask.long.word 0x18 16.--28. 1. "BBUD_CLK_ASSERT_CNT,number of reference clocks before bbud_iso_en de-assertion after bbud_non_udr_rst de-asserts"
newline
hexmask.long.word 0x18 0.--12. 1. "BBUD_UDR_ASSERT_CNT,number of reference clocks before bbud_non_udr_rst de-assertion after bbud_clk_en is asserted"
line.long 0x1C "WL_DVFS_CTRL,WLAN DVFS Control"
hexmask.long.byte 0x1C 0.--6. 1. "WLAN_VOL_VAL,WLAN Vol Value"
line.long 0x20 "WL_CTRL2,WLAN Control 2"
bitfld.long 0x20 31. "WL_HOST_SLP_RDY,WLAN Host Sleep Ready" "0,1"
newline
bitfld.long 0x20 25. "WLAN_USE_UNSYNC_PWR_LVL,WLAN Use Unsync Power Level" "0,1"
newline
bitfld.long 0x20 24. "FW_FORCE_WL_PWRUP,FW Force WLAN Powerup" "0,1"
newline
bitfld.long 0x20 22. "APU_WLAN_RF_MUX_SEL,APU WLAN RF Mux Select" "0,1"
newline
bitfld.long 0x20 21. "APU_TSF_AUTO_UPDATE,APU TSF Auto Update" "0,1"
newline
hexmask.long.byte 0x20 16.--20. 1. "APU_TSF_UPD_CNT,APU TSF Update Count"
newline
bitfld.long 0x20 15. "APU_FW_RST_PE,APU FW Reset PE" "0,1"
newline
bitfld.long 0x20 10. "USE_WL_PWR_RDY_FOR_WLRF_CLK,Use WLAN Power Ready for WL RF Clock" "0,1"
newline
bitfld.long 0x20 9. "WL_USE_NOM_PWR_BYP,Use nom_pwr_lvl from dvfs for wl_pwr_lvl_reached" "0,1"
newline
bitfld.long 0x20 7. "USE_WL_INTR_SLP,Use WLAN Interrupt Sleep" "0,1"
newline
bitfld.long 0x20 6. "APU_WKUP_WLRF_RX,APU Wakeup WL RF Rx" "0,1"
newline
bitfld.long 0x20 5. "IDLE2ISO_DLY_EN,Delay from idle to iso to ensure delay from bbud_non_udr_rst_b =0 to wlan_iso_en = 1" "0,1"
newline
bitfld.long 0x20 2. "WL_SLP_RDY_FW,WLAN Sleep Ready Firmware" "0,1"
newline
bitfld.long 0x20 1. "WL_SLP_RDY_MASK,WLAN Sleep Ready Mask" "0,1"
newline
bitfld.long 0x20 0. "WL_SLP_RDY,WLAN Sleep Ready" "0,1"
line.long 0x24 "WL_WKUP_MASK2,WLAN Wakeup Mask 2"
hexmask.long.word 0x24 16.--31. 1. "WL_HOST_MAP,WLAN Host Map"
newline
bitfld.long 0x24 12. "IHB_WL_XPP_DYNPLL_REQ_MASK,When mask = 0 ihb_wl_xpp_req is treated as pll_req" "0,1"
newline
bitfld.long 0x24 11. "WL_SLP_RDY_DYNPLL_REQ_MASK,When mask = 0 !wl_slp_rdy is treated as pll_req" "0,1"
newline
bitfld.long 0x24 10. "WL_TIMER_DYNPLL_REQ_MASK,When mask = 0 wlan_timer_xpp req is treated as pll_req" "0,1"
newline
bitfld.long 0x24 9. "WL_HOST_DYNPLL_REQ_MASK,When mask = 0 wlan_host_wkup is treated as pll_req" "0,1"
newline
bitfld.long 0x24 8. "WL_RF_PLL_DYNPLL_REQ_MASK,When mask = 0 wl_rf_pll_req is treated as pll_req" "0,1"
newline
bitfld.long 0x24 3. "BCA_MWS_WKUP_XP_MASK,BCA MWS Wakeup XP Mask" "0,1"
newline
bitfld.long 0x24 2. "WL_RF_PLL_REQ_MASK,WLAN RF PLL Request Mask" "0,1"
newline
bitfld.long 0x24 1. "BBUD_T2_PLL_REQ_MASK,BBUD T2 PLL Request Mask" "0,1"
newline
bitfld.long 0x24 0. "WL_BCN_TIMER_WKUP_MASK,WLAN Beacon Timer Wakeup Mask" "0,1"
rgroup.long 0xB8++0x7
line.long 0x0 "WL_STATUS2,WLAN Status 2"
bitfld.long 0x0 31. "BCA_CLK_REQ,BCA Clock Request" "0,1"
newline
bitfld.long 0x0 30. "BBUD_T2_PLL_REQ,BBUD T2 PLL Request" "0,1"
newline
bitfld.long 0x0 29. "WLRF_PLL_REQ,WLAN RF PLL Request" "0,1"
newline
bitfld.long 0x0 28. "TIMER_WAKEUP,Timer Wakeup" "0,1"
newline
bitfld.long 0x0 27. "TIMER_XPP_WAKEUP,Timer XPP Wakeup" "0,1"
newline
bitfld.long 0x0 26. "WL_TIMER_INTR,WLAN Timer Interrupt" "0,1"
newline
bitfld.long 0x0 25. "WLAN_HOST_WKUP,WLAN Host Wakeup" "0,1"
newline
bitfld.long 0x0 24. "WL_HOST_INTR_REF,WLAN Host Interrupt Reference" "0,1"
newline
bitfld.long 0x0 23. "WL_PWR_RDY,WLAN Power Ready" "0,1"
newline
bitfld.long 0x0 22. "SOC_VOL_REACHED,SoC Volume Reached" "0,1"
newline
bitfld.long 0x0 21. "WLAN_VOL_REACHED,WLAN Volume Reached" "0,1"
newline
bitfld.long 0x0 20. "APU_WLAN_SRAM_PD,APU WLAN SRAM Pd" "0,1"
newline
bitfld.long 0x0 19. "APU_WLAN_ISO_EN,APU WLAN ISO Enable" "0,1"
newline
bitfld.long 0x0 18. "APU_WLAN_CLK_DIV_RSTB,APU WLAN Clock Div RSTb" "0,1"
newline
bitfld.long 0x0 17. "APU_WLAN_UDR_FIREWALL_B,APU WLAN UDR Firewall b" "0,1"
newline
bitfld.long 0x0 16. "APU_WLAN_SWITCH_PD,APU WLAN Switch Pd" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "APU_WL_ST,APU WLAN St"
newline
bitfld.long 0x0 10. "APU_BBUD_NON_UDR_RST_B,APU BBUD non-UDR RSTb" "0,1"
newline
bitfld.long 0x0 9. "APU_RTDP_WU_RSTB,APU RTDP WU RSTb" "0,1"
newline
bitfld.long 0x0 8. "BCA_MWS_WKUP_XP,BCA MWS Wakeup XP" "0,1"
newline
bitfld.long 0x0 7. "APU_PLL3_EN,APU PLL3 Enable" "0,1"
newline
bitfld.long 0x0 6. "APU_PLL1_EN,APU PLL1 Enable" "0,1"
newline
bitfld.long 0x0 4.--5. "APU_WL_RF_CTRL,APU WLAN RF Control" "0,1,2,3"
newline
bitfld.long 0x0 3. "APU_WL_SLP_RDY_AFTER_MASK,APU WLAN Sleep Ready After Mask" "0,1"
newline
bitfld.long 0x0 2. "APU_WL_RF_CLK_EN,APU WLAN Ref Clock Enable" "0,1"
newline
bitfld.long 0x0 1. "APU_BBUD_CLK_EN,APU BBUD Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_MAC_CLK_EN,APU MAC Clock Enable" "0,1"
line.long 0x4 "WL_ALARM_RD2,WLAN Alarm Readback 2"
hexmask.long 0x4 0.--31. 1. "APU_WL_ALARM_RD,reads back current beacon timer alarm value"
group.long 0xC0++0x13
line.long 0x0 "WL_BCN_XP_ALARM2,WLAN Beacon XP Alarm 2"
hexmask.long 0x0 0.--31. 1. "WL_BCN_XP_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock and power"
line.long 0x4 "WL_BCN_INTR_ALARM2,WLAN Beacon Interrupt Alarm 2"
hexmask.long 0x4 0.--31. 1. "WL_BCN_INTR_ALARM,number of ref clocks after WLAN beacon timer request to firmware wakeup"
line.long 0x8 "WL_HOST_INTR_ALARM2,WLAN Host Interrupt Alarm 2"
hexmask.long 0x8 0.--31. 1. "WL_HOST_INTR_ALARM,number of ref clocks after WLAN host request to firmware wakeup"
line.long 0xC "WL_BCN_PLL_ALARM2,WLAN Beacon PLL Alarm 2"
hexmask.long 0xC 0.--31. 1. "WL_BCN_PLL_ALARM,number of sleep clocks until WLAN beacon timer requests for reference clock power and PLL"
line.long 0x10 "WLCOMN_PWR_CTRL,WLAN Comm Powerup Control"
hexmask.long.word 0x10 16.--31. 1. "WLCOMN_PWRUP_CNT,number of reference clocks after soc_pwr_rdy to push wlcomn power up"
newline
bitfld.long 0x10 15. "CPU_VINITHI,CPU to CPU Delay" "0,1"
newline
bitfld.long 0x10 10. "IDLE2ISO_DLY_EN,wlcomn FSM state delay enable. When 1 use wlcomn_pwr_ctrl_dly and wlcomn_pwr_ctrl_dly2. When 0 no delay." "0,1"
newline
bitfld.long 0x10 9. "USE_DEEPSLEEP_FOR_SYS_CLK_EN,Use Deep Sleep for SYS_CLK Enable" "0,1"
newline
bitfld.long 0x10 8. "USE_WLCOMN_PWR_RDY_FOR_WL,Use WL COMM Power Ready fro WLAN" "0,1"
newline
hexmask.long.byte 0x10 0.--7. 1. "WLCOMN_UDR_ASSERT_CNT,WL COMM UDR Assert Count"
rgroup.long 0xD4++0x3
line.long 0x0 "WLCOMN_STATUS,WLAN Comm Status"
bitfld.long 0x0 19. "APU_WLCOMN_ISO_EN,APU WLAN COMN ISO Enable" "0,1"
newline
bitfld.long 0x0 18. "APU_WLCOMN_CLK_DIV_RSTB,APU WLAN COMN Clock Div RSTb" "0,1"
newline
bitfld.long 0x0 17. "APU_WLCOMN_UDR_FIREWALL_B,APU WLAN COMN UDR Firewall b" "0,1"
newline
bitfld.long 0x0 16. "APU_WLCOMN_SWITCH_PD,APU WLAN COMN Switch Pd" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "APU_WLCOMN_ST,APU WLAN COMN St"
newline
bitfld.long 0x0 11. "ENTER_CPU1_SUB_DSLP_REFCK,WLCOMN FSM enter ip power down" "0,1"
newline
bitfld.long 0x0 10. "START_WLCOMN_WKUP_REFCK,WLCOMN FSM start ip wake up" "0,1"
group.long 0xE0++0x7
line.long 0x0 "BT_CTRL,Bluetooth Control"
bitfld.long 0x0 31. "BT_HOST_SLP_RDY,Bluetooth Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 30. "BT_PLL_SYNC_MODE_SEL,Bluetooth PLL Sync Mode Select" "0,1"
newline
bitfld.long 0x0 29. "BT_CLK_SYNC_MODE_SEL0,Bluetooth Clock Sync Mode Select 0" "0,1"
newline
bitfld.long 0x0 28. "BRF_CLK_SYNC_MODE_SEL,BRF Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x0 27. "USE_GLITCH_FREE_BT_CLK_REQ,Use Glitch-Free Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x0 26. "BT_CLK_SYNC_MODE_SEL1,Bluetooth Clock Sync Mode Select 1" "0,1"
newline
bitfld.long 0x0 7. "USE_BT_INTR_SLP,Use Bluetooth interrupt Sleep" "0,1"
newline
bitfld.long 0x0 3. "BTU_CLK_NCO_MODE_SEL_EN,0- disable the btu_clk_nco_mode from CIU2 keep the bt_clk_req as XP wakeup source" "0,1"
newline
bitfld.long 0x0 2. "BT_SLP_RDY_FW,Bluetooth Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "BT_SLP_RDY_MASK,Bluetoot Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "BT_SLP_RDY,Bluetooth Sleep Ready" "0,1"
line.long 0x4 "BT_WKUP_MASK,Bluetooth Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "BT_HOST_MAP,Bluetooth Host Map"
newline
bitfld.long 0x4 5. "BRF_PLL_REQ_MASK,BRF PLL Request Mask" "0,1"
newline
bitfld.long 0x4 4. "BT_PLL_REQ_MASK,Bluetooth PLL Request Mask" "0,1"
newline
bitfld.long 0x4 3. "BT_INTR_MASK,Bluetooth Interrupt Mask" "0,1"
newline
bitfld.long 0x4 2. "BT_WB_ACTIVE_REQ_MASK,Bluetooth WB Active Request Mask" "0,1"
newline
bitfld.long 0x4 1. "BT_CLK_REQ_MASK,Bluetooth Clock Request Mask" "0,1"
newline
bitfld.long 0x4 0. "BCA_CLK_REQ_MASK,BCA Clock Request Mask" "0,1"
rgroup.long 0xE8++0x3
line.long 0x0 "BT_STATUS,Bluetooth Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup In"
newline
bitfld.long 0x0 9. "BT_WIDEBAND_ACTIVE,Bluetooth Wideband Active" "0,1"
newline
bitfld.long 0x0 8. "BRF_PLL_REQ,BRF PLL Request" "0,1"
newline
bitfld.long 0x0 7. "BT_CLK_REQ,Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x0 6. "BT_PLL_REQ,Bluetooth PLL Request" "0,1"
newline
bitfld.long 0x0 5. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 4. "BT_HOST_WKUP,Bluetooth Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "BT_ACTIVE_SLPCK,Bluetooth Active Sleep Clock" "0,1"
newline
bitfld.long 0x0 1. "APU_BRF_CLK_EN,APU BRF Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_CLK_EN,APU Bluetooth Clock Enable" "0,1"
group.long 0xEC++0xB
line.long 0x0 "BT_CKEN_CTRL,Bluetooth Clock Enable Control"
bitfld.long 0x0 5. "BT_CLK_EN_SEL,selection for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "BT_CLK_EN_VAL,control value for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "BT_CLK_EN_SEL_XOSC,selection for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "BT_CLK_EN_VAL_XOSC,control value for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "BL_CLK_EN_SEL_PWR,selection for bt_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "BT_CLK_EN_VAL_PWR,control value for bt_clk_en when power ready" "0,1"
line.long 0x4 "BT_RESRC_CTRL,Bluetooth RESRC Control"
bitfld.long 0x4 11. "FW_ALLWAKE_REQ_VAL,firmware override value when apu_bt_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FW_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FW_IPWAKE_REQ_VAL,override value when apu_bt_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FW_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FW_SB_REQ_VAL,override value when apu_bt_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FW_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FW_XP_REQ_VAL,override value when apu_bt_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FW_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FW_XOSC_REQ_VAL,override value when apu_bt_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FW_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FW_PWR_REQ_VAL,override value when apu_bt_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FW_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "BT_DVFS_CTRL,Bluetooth DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "BT_VOL_VAL,Blueooth Vol Value"
group.long 0x100++0x7
line.long 0x0 "FM_CTRL,FM Control"
bitfld.long 0x0 31. "FM_HOST_SLP_RDY,FM Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 7. "USE_FM_INTR_SLP,Use FM Interrupt Sleep" "0,1"
newline
bitfld.long 0x0 5. "FM_CLK_SYNC_MODE_SEL,FM Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x0 4. "FM_DYN_VOL_EN,FM Dynamic Vol Enable" "0,1"
newline
bitfld.long 0x0 3. "FM_PRESENT,FM Present" "0,1"
newline
bitfld.long 0x0 2. "FM_SLP_RDY_FW,FM Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "FM_SLP_RDY_MASK,FM Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "FM_SLP_RDY,FM Sleep Delay" "0,1"
line.long 0x4 "FM_WKUP_MASK,FM Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "FM_HOST_MAP,FM to host-HOST Delay"
newline
bitfld.long 0x4 2. "FM_PRESENT_MASK,FM Present Mask" "0,1"
newline
bitfld.long 0x4 1. "FM_INTR_MASK,FM Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "FM_CLK_REQ_MASK,FM Clock Request Mask" "0,1"
rgroup.long 0x108++0x3
line.long 0x0 "FM_STATUS,FM Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup Interrupt"
newline
bitfld.long 0x0 7. "FM_PRESENT,FM Present" "0,1"
newline
bitfld.long 0x0 6. "FM_CLK_REQ,FM Clock Request" "0,1"
newline
bitfld.long 0x0 5. "FM_INTR,FM Interrupt" "0,1"
newline
bitfld.long 0x0 4. "FM_HOST_WKUP,FM Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "XOSC_STABLE_REFCK,XOSC Stable Ref Clock" "0,1"
newline
bitfld.long 0x0 1. "SOC_CLK_EN2,SoC Clock Enable 2" "0,1"
newline
bitfld.long 0x0 0. "APU_FM_CLK_EN,APU FM Clock Enable" "0,1"
group.long 0x10C++0xB
line.long 0x0 "FM_CKEN_CTRL,FM Clock Enable Control"
bitfld.long 0x0 5. "FM_CLK_EN_PLL_SEL,selection for fm_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "FM_CLK_EN_PLL_VAL,control value for fm_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "FM_CLK_EN_XOSC_SEL,selection for fm_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "FM_CLK_EN_XOSC_VAL,control value for fm_clk_en when xosc is ready" "0,1"
newline
bitfld.long 0x0 1. "FM_CLK_EN_PWR_SEL,selection for fm_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "FM_CLK_EN_PWR_VAL,control value for fm_clk_en when power ready" "0,1"
line.long 0x4 "FM_RESRC_CTRL,FM RESRC Control"
bitfld.long 0x4 11. "FM_ALLWAKE_REQ_VAL,firmware override value when apu_fm_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FM_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FM_IPWAKE_REQ_VAL,override value when apu_fm_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FM_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FM_SB_REQ_VAL,override value when apu_fm_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FM_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FM_XP_REQ_VAL,override value when apu_fm_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FM_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FM_XOSC_REQ_VAL,override value when apu_fm_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FM_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FM_PWR_REQ_VAL,override value when apu_fm_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FM_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "FM_DVFS_CTRL,FM DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "FM_VOL_VAL,FM Vol Value"
group.long 0x120++0xF
line.long 0x0 "USB_PWR_CTRL_DLY,USB FSM Power Control Delay"
hexmask.long 0x0 0.--31. 1. "PWR_CTRL_DLY,USB FSM Power Control Delay"
line.long 0x4 "USB_PWR_CTRL_DLY2,USB FSM Power Control Delay 2"
hexmask.long 0x4 0.--31. 1. "PWR_CTRL_DLY2,USB FSM Power Control Delay 2"
line.long 0x8 "WLCOMN_PWR_CTRL_DLY,Wlan common domain FSM Power Control Delay"
hexmask.long 0x8 0.--31. 1. "PWR_CTRL_DLY,WLAN COMN FSM power control delay"
line.long 0xC "WLCOMN_PWR_CTRL_DLY2,Wlan common domain FSM Power Control Delay 2"
hexmask.long 0xC 0.--31. 1. "PWR_CTRL_DLY2,WLAN COMN FSM power control delay"
group.long 0x140++0x7
line.long 0x0 "BLE_CTRL,BLE Control"
bitfld.long 0x0 31. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0x0 15. "BT_AES_NCO_MODE,Bluetooth AES NCO Mode" "0,1"
newline
bitfld.long 0x0 3. "BLE_MODE_EN,BLE Mode Enable" "0,1"
newline
bitfld.long 0x0 2. "BLE_SLP_RDY_FW,BLE Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "BLE_SLP_RDY_MASK,BLE Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "BLE_SLP_RDY,BLE Sleep Ready" "0,1"
line.long 0x4 "BLE_WKUP_MASK,BLE Wakeup Mask"
bitfld.long 0x4 4. "LBC_XP_REQ_MASK,LBC XP Request Mask" "0,1"
newline
bitfld.long 0x4 3. "BT_AES_CLK_REQ_MASK,Bluetooth AES Clock Request Mask" "0,1"
rgroup.long 0x148++0x3
line.long 0x0 "BLE_STATUS,BLE Status"
bitfld.long 0x0 9. "BT_AES_CLK_REQ,Bluetooth AES Clock Request Mask" "0,1"
newline
bitfld.long 0x0 8. "LBC_XP_REQ,LBC XP Request" "0,1"
newline
bitfld.long 0x0 6. "BT_AES_NCO_MODE,Blueooth AES NCO Mode" "0,1"
newline
bitfld.long 0x0 5. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0x0 4. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 3. "T1_STABLE,T1 Delay" "0,1"
newline
bitfld.long 0x0 2. "XOSC_STABLE_REFCK,XOSC Stable Ref Clock" "0,1"
newline
bitfld.long 0x0 1. "BT_AES_CLK_SEL,Bluetooth AES Clock Select" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_AES_CLK_EN,APU Bluetooth AES Clock Enable" "0,1"
group.long 0x160++0x7
line.long 0x0 "NFC_CTRL,NFC Control"
bitfld.long 0x0 31. "NFC_HOST_SLP_RDY,NFC Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 25. "NFC_USE_UNSYNC_PWR_LVL,NFC Use Unsync Power Level" "0,1"
newline
bitfld.long 0x0 24. "FW_FORCE_NFC_PWRUP,FW Force NFC Powerup" "0,1"
newline
bitfld.long 0x0 9. "NFC_USE_NOM_PWR_BYP,Use nom_pwr_lvl from dvfs for nfc_pwr_lvl_reached" "0,1"
newline
bitfld.long 0x0 8. "NFC_USE_CPU2_SUBSLP,Use CPU2 subsystem sleep for NFC power down" "0,1"
newline
bitfld.long 0x0 7. "FW_CLR_NFC_INTR,FW Clear NFC Interrupt" "0,1"
newline
bitfld.long 0x0 5. "NFC_USE_SOC_PWR_SEQ,Use SoC power sequence for NFC as well" "0,1"
newline
bitfld.long 0x0 4. "USE_NFC_INTR_SLP,Use NFC Interrupt Sleep" "0,1"
newline
bitfld.long 0x0 3. "USE_NFC_REF_ONLY,Use NFC Reference Only" "0,1"
newline
bitfld.long 0x0 2. "NFC_SLP_RDY_FW,NFC Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "NFC_SLP_RDY_MASK,NFC Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "NFC_SLP_RDY,NFC Sleep Ready" "0,1"
line.long 0x4 "NFC_WKUP_MASK,NFC Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "NFC_HOST_MAP,NFC Host Map"
newline
bitfld.long 0x4 2. "NFC_INT_WKUP_MASK,NFC Interrupt Wakeup Mask" "0,1"
newline
bitfld.long 0x4 1. "NFC_XP_WKUP_MASK,NFC XP Wakeup Mask" "0,1"
newline
bitfld.long 0x4 0. "NFC_P_WKUP_MASK,NFC P Wakeup Mask" "0,1"
rgroup.long 0x168++0x3
line.long 0x0 "NFC_STATUS,NFC Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup Interrupt"
newline
bitfld.long 0x0 12.--14. "APU_NFC_ST,APU NFC St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "NFC_PWR_RDY,NFC Power ready" "0,1"
newline
bitfld.long 0x0 10. "SOC_VOL_REACHED,SoC Vol Reached" "0,1"
newline
bitfld.long 0x0 9. "NFC_VOL_REACHED,NFC Vol Reached" "0,1"
newline
bitfld.long 0x0 8. "APU_NFC_SRAM_PD_AON,APU NFC SRAM PD AON" "0,1"
newline
bitfld.long 0x0 7. "APU_NFC_ISO_EN_AON,APU NFC ISO Enable AON" "0,1"
newline
bitfld.long 0x0 6. "APU_NFC_CLK_DIV_RSTB_AON,APU NFC Clock Divider RSTb AON" "0,1"
newline
bitfld.long 0x0 5. "APU_NFC_UDR_FIREWALL_B_AON,APU NFC UDR Firewall B AON" "0,1"
newline
bitfld.long 0x0 4. "APU_NFC_SWITCH_PD_AON,APU NFC Switch PD AON" "0,1"
newline
bitfld.long 0x0 3. "NFC_P_REQ,NFC P Req" "0,1"
newline
bitfld.long 0x0 2. "NFC_XP_REQ,NFC XP Req" "0,1"
newline
bitfld.long 0x0 1. "NFC_INT,NFC Interrupt" "0,1"
newline
bitfld.long 0x0 0. "APU_NFC_AHBCLK_EN,APU NFC AHB Clock Enable" "0,1"
group.long 0x16C++0xB
line.long 0x0 "NFC_CKEN_CTRL,NFC Clock Enable Control"
bitfld.long 0x0 5. "NFC_CLK_EN_PLL_SEL,selection for nfc_cm3_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "NFC_CLK_EN_PLL_VAL,NFC Clock Enable PLL Value" "0,1"
newline
bitfld.long 0x0 3. "NFC_CLK_EN_XOSC_SEL,selection for nfc_cm3_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "NFC_CLK_EN_XOSC_VAL,Control value for nfc_cm3_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "NFC_CLK_EN_PWR_SEL,selection for nfc_cm3_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "NFC_CLK_EN_PWR_VAL,control value for nfc_clk_en when power ready" "0,1"
line.long 0x4 "NFC_RESRC_CTRL,NFC RESRC Control"
bitfld.long 0x4 11. "NFC_ALLWAKE_REQ_VAL,firmware override value when apu_nfc_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "NFC_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "NFC_IPWAKE_REQ_VAL,override value when apu_nfc_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "NFC_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "NFC_SB_REQ_VAL,override value when apu_nfc_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "NFC_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "NFC_XP_REQ_VAL,override value when apu_nfc_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "NFC_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "NFC_XOSC_REQ_VAL,override value when apu_nfc_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "NFC_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "NFC_PWR_REQ_VAL,override value when apu_nfc_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "NFC_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "NFC_DVFS_CTRL,NFC DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "NFC_VOL_VAL,NFC Vol Value"
group.long 0x180++0x7
line.long 0x0 "FP4_CTRL,FP4(15.4) Control"
bitfld.long 0x0 31. "FP4_HOST_SLP_RDY,FP4 Host Sleep Ready" "0,1"
newline
bitfld.long 0x0 30. "FRF_PLL_SYNC_MODE_SEL,FRF PLL Sync Mode Select" "0,1"
newline
bitfld.long 0x0 29. "FP4_CLK_SYNC_MODE_SEL0,FP4 Clock Sync Mode Select 0" "0,1"
newline
bitfld.long 0x0 28. "FRF_CLK_SYNC_MODE_SEL,FRF Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x0 27. "USE_GLITCH_FREE_FP4_CLK_REQ,Use Glitch-Free FP4 Clock Request" "0,1"
newline
bitfld.long 0x0 26. "FP4_CLK_SYNC_MODE_SEL1,FP4 Clock Sync Mode Select 1" "0,1"
newline
bitfld.long 0x0 7. "USE_FP4_INTR_SLP,Use 15.4 interrupt Sleep" "0,1"
newline
bitfld.long 0x0 2. "FP4_SLP_RDY_FW,Bluetooth Sleep Ready FW" "0,1"
newline
bitfld.long 0x0 1. "FP4_SLP_RDY_MASK,FP4 Sleep Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "FP4_SLP_RDY,FP4 Sleep Ready" "0,1"
line.long 0x4 "FP4_WKUP_MASK,FP4 Wakeup Mask"
hexmask.long.word 0x4 16.--31. 1. "FP4_HOST_MAP,15.4 Host Map"
newline
bitfld.long 0x4 3. "FP4_PLL_REQ_MASK,15.4 PLL Request Mask" "0,1"
newline
bitfld.long 0x4 2. "FRF_PLL_REQ_MASK,FRF PLL Request Mask" "0,1"
newline
bitfld.long 0x4 1. "FP4_INTERRUPT_MASK,FP4 Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "FP4_CLK_REQ_MASK,FP4 Clock Request Mask" "0,1"
rgroup.long 0x188++0x3
line.long 0x0 "FP4_STATUS,FP4 Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup In"
newline
bitfld.long 0x0 7. "FRF_PLL_REQ,FRF PLL Request" "0,1"
newline
bitfld.long 0x0 6. "FP4_CLK_REQ,FP4 Clock Request" "0,1"
newline
bitfld.long 0x0 5. "FP4_PLL_REQ,FP4 PLL Request" "0,1"
newline
bitfld.long 0x0 4. "FP4_INTERRUPT,FP4 Interrupt" "0,1"
newline
bitfld.long 0x0 3. "BT_HOST_WKUP,Bluetooth Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "FP4_ACTIVE_SLPCK,FP4 Active Sleep Clock" "0,1"
newline
bitfld.long 0x0 1. "APU_FRF_CLK_EN,APU FRF Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_FP4_CLK_EN,APU FP4 Clock Enable" "0,1"
group.long 0x18C++0x2F
line.long 0x0 "FP4_CKEN_CTRL,FP4 Clock Enable Control"
bitfld.long 0x0 5. "FP4_CLK_EN_SEL,selection for fp4_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "FP4_CLK_EN_VAL,control value for fp4_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "FP4_CLK_EN_SEL_XOSC,selection for fp4_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "FP4_CLK_EN_VAL_XOSC,control value for fp4_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "FP4_CLK_EN_SEL_PWR,selection for fp4_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "FP4_CLK_EN_VAL_PWR,control value for fp4_clk_en when power ready" "0,1"
line.long 0x4 "FP4_RESRC_CTRL,FP4 RESRC Control"
bitfld.long 0x4 11. "FW_ALLWAKE_REQ_VAL,firmware override value when apu_fp4_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FW_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FW_IPWAKE_REQ_VAL,override value when apu_fp4_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FW_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FW_SB_REQ_VAL,override value when apu_fp4_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FW_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FW_XP_REQ_VAL,override value when apu_fp4_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FW_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FW_XOSC_REQ_VAL,override value when apu_fp4_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FW_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FW_PWR_REQ_VAL,override value when apu_fp4_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FW_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "FP4_DVFS_CTRL,FP4 DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "FP4_VOL_VAL,FP4 Vol Value"
line.long 0xC "CPU2_FP4_HOST_WKUP_MASK,CPU2 15.4 Host Wakeup Mask"
hexmask.long.word 0xC 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x10 "CPU2_FP4_HOST_WKUP_POL,CPU2 15.4 Host Wakeup Polarity"
hexmask.long.word 0x10 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
line.long 0x14 "CPU2_FP4_HOST_WKUP_CTRL,CPU2 15.4 Host Wakeup Control"
hexmask.long.word 0x14 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x14 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0x18 "HW_IP_ACTIVE_INDEX_CTRL,HW IP active index Control"
hexmask.long 0x18 0.--31. 1. "MASTERX_ACTIVE_INDEX,master0-7 Active Index[3:0]"
line.long 0x1C "HW_IP_INACTIVE_INDEX_CTRL,HW IP inactive Control"
hexmask.long 0x1C 0.--31. 1. "MASTERX_INACTIVE_INDEX,master0-7 inactive Index[3:0]"
line.long 0x20 "HW_IP_DYNAMIC_CLK_SWITCH_CTRL,HW IP dynamic clock switching contrl"
hexmask.long.byte 0x20 16.--23. 1. "MASTERX_ACTIVE_INDEX_BYPASS_EN,1- use masterx_active-index from register hw_ip_active_index_ctrl; 0-use active index from HW latched version"
newline
hexmask.long.byte 0x20 8.--15. 1. "MASTERX_APU_IDLE_BYPASS_VAL,idle bypass val"
newline
hexmask.long.byte 0x20 0.--7. 1. "MASTERX_APU_IDLE_BYPASS_EN,1-FW bypasses hw_ip_idle; 0 - use hw_ip_idle"
line.long 0x24 "IHB_CTRL,IHB Control"
hexmask.long.byte 0x24 16.--22. 1. "IHB_VOL_VAL,Voltage value needed for Bluetooth function"
newline
bitfld.long 0x24 3. "IHB_CLK_REQ_AS_XPP_REQ,IHB Clock Request as XPP Request" "0,1"
newline
bitfld.long 0x24 2. "IHB_CLK_REQ_AS_XP_REQ,IHB Clock Request as XP Request" "0,1"
newline
bitfld.long 0x24 1. "IHB_VOL_REQ_AS_XP_REQ,IHB Vol Request as XP Request" "0,1"
newline
bitfld.long 0x24 0. "IHB_VOL_REQ_AS_P_REQ,IHB Vol Request as P Request" "0,1"
line.long 0x28 "IHB_WKUP_MASK,IHB Wakeup Mask"
bitfld.long 0x28 4. "CPU1_IHB_PMU_WKUP_MASK,CPU1 IHB PMU Wakeup Mask" "0,1"
newline
bitfld.long 0x28 3. "IHB_WL_WKUP_REQ_MASK,IHB WLAN Wakeup Request Mask" "0,1"
newline
bitfld.long 0x28 2. "IHB_CLK_REQ_MASK,IHB Clock Request Mask" "0,1"
newline
bitfld.long 0x28 1. "IHB_LO_VOL_REQ_MASK,IHB Low Vol Request Mask" "0,1"
newline
bitfld.long 0x28 0. "IHB_HI_VOL_REQ_MASK,IHB High Vol Request Mask" "0,1"
line.long 0x2C "CPU2_IHB_WKUP_MASK,CPU2 IHB Wakeup Mask"
bitfld.long 0x2C 0. "CPU2_IHB_PMU_WKUP_MASK,CPU2 IHB PMU Wakeup Mask" "0,1"
rgroup.long 0x1BC++0x3
line.long 0x0 "IHB_STATUS,IHB Status"
hexmask.long 0x0 0.--31. 1. "IHB_STATUS,IHB Status"
group.long 0x1C0++0x7
line.long 0x0 "USB_CTRL,USB Control"
bitfld.long 0x0 31. "USB_CLK_SEL_ACK_EXT_EN,USB Clock Select Ack Ext Enable" "0,1"
newline
bitfld.long 0x0 25. "USB_USE_UNSYNC_VOL_LVL,USB Use Unsync Vol Level" "0,1"
newline
bitfld.long 0x0 24. "FW_FORCE_USB_PWRUP,FW Force USB Powerup" "0,1"
newline
bitfld.long 0x0 9. "USB_USE_NOM_PWR_BYP,USB Use Nominal Power Bypass" "0,1"
newline
bitfld.long 0x0 5. "IDLE2ISO_DLY_EN,USB FSM state counter enable. When set to 1 use usb_pwr_ctrl_dly and usb_pwr_ctrl_dly2. When set to 0 no delay" "0,1"
newline
bitfld.long 0x0 4. "USE_CLK_SEL_ACK_AS_USB_PWR_DWN,Use Clock Select Ack as USB Power Down" "0,1"
newline
bitfld.long 0x0 0. "USB_PWR_DWN_MASK,USB Power Down Mask" "0,1"
line.long 0x4 "USB_WKUP_MASK,USB Wakeup Mask"
bitfld.long 0x4 2. "USB_CLK_SEL_REQ_MASK,USB Clock Select Request Mask" "0,1"
newline
bitfld.long 0x4 1. "USB_AXI_CLK_REQ_MASK,USB AXI Clock Request Mask" "0,1"
newline
bitfld.long 0x4 0. "USB_P_REQ_MASK,USB P Request Mask" "0,1"
rgroup.long 0x1C8++0x3
line.long 0x0 "USB_STATUS,USB Status"
hexmask.long.byte 0x0 16.--19. 1. "APU_USB_ST,APU USB St"
newline
bitfld.long 0x0 15. "USB_PWR_DWN,USB Power Down" "0,1"
newline
bitfld.long 0x0 14. "DVFS_USB_VOL_LVL_REACHED,DVFS USB Vol Level Reached" "0,1"
newline
bitfld.long 0x0 13. "DVFS_NOM_VOL_LVL_REACHED,DVFS Nominal Vol Level Reached" "0,1"
newline
bitfld.long 0x0 12. "USB_VOL_LVL_REACHED,USB Vol Level Reached" "0,1"
newline
bitfld.long 0x0 11. "APU_USB_CLK_SEL,APU USB Clock Select" "0,1"
newline
bitfld.long 0x0 10. "XOSC_STABLE_REFCK,OSC clock stable on ref clock domain" "0,1"
newline
bitfld.long 0x0 9. "APU_USB_AXI_CLK_EN,APU USB AXI Clock Enable" "0,1"
newline
bitfld.long 0x0 8. "USB_CLK_SEL_ACK_EXT_EN,extension enable for the usb_clk_sel_ack" "0,1"
newline
bitfld.long 0x0 7. "APU_USB_SWITCH_PD,APU USB Switch Power Down" "0,1"
newline
bitfld.long 0x0 6. "SOC_PWR_RDY,SOC Power Ready" "0,1"
newline
bitfld.long 0x0 5. "APU_USB_AXI_CLK_ACK,APU USB AXI Clock Ack" "0,1"
newline
bitfld.long 0x0 4. "USB_AXI_CLK_REQ,USB AXI Clock Request" "0,1"
newline
bitfld.long 0x0 3. "APU_USB_CLK_SEL_ACK,APU USB Clock Select Ack" "0,1"
newline
bitfld.long 0x0 2. "USB_CLK_SEL_REQ,USB Clock Select Request" "0,1"
newline
bitfld.long 0x0 1. "APU_USB_P_ACK,APU USB P Ack" "0,1"
newline
bitfld.long 0x0 0. "USB_P_REQ,USB P Request" "0,1"
group.long 0x200++0x67
line.long 0x0 "CPU1_DVFS_CTRL,CPU1 DVFS Control"
bitfld.long 0x0 31. "PCIE_VOL_HOST_SLP_DEP,PCIe Vol Host Sleep Dep" "0,1"
newline
bitfld.long 0x0 30. "PCIE_VOL_FLR_DEP,PCIe Vol Flr Dep" "0,1"
newline
bitfld.long 0x0 29. "PCIE_VOL_HOST_WKUP_DEP,PCIe Vol Host Wakeup Dep" "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "CPU1_INACTIVE_AHB1_INDEX,CPU1 Inactive AHB1 Index"
newline
hexmask.long.byte 0x0 16.--19. 1. "CPU1_ACTIVE_AHB1_INDEX,CPU1 Active AHB1 Index"
newline
hexmask.long.byte 0x0 12.--15. 1. "CPU1_INACTIVE_SYS_INDEX,CPU1 Inactive System Index"
newline
hexmask.long.byte 0x0 8.--11. 1. "CPU1_ACTIVE_SYS_INDEX,CPU1 Active System Index"
newline
hexmask.long.byte 0x0 4.--7. 1. "CPU1_INACTIVE_INDEX,CPU1 Inactive Index"
newline
hexmask.long.byte 0x0 0.--3. 1. "CPU1_ACTIVE_INDEX,CPU1 Active Index"
line.long 0x4 "CPU1_FREQ_REG1,CPU1 Frequency 1"
hexmask.long 0x4 0.--31. 1. "CPU1_FREQ_REG1,CPU1 Frequency 1"
line.long 0x8 "CPU1_FREQ_REG2,CPU1 Frequency 2"
hexmask.long 0x8 0.--31. 1. "CPU1_FREQ_REG2,CPU1 Frequency 2"
line.long 0xC "CPU1_PLL_EN_REG,CPU1 PLL Enable"
hexmask.long 0xC 0.--31. 1. "CPU1_PLL_EN_REG,CPU1 PLL Enable"
line.long 0x10 "CPU1_VOL_REG1,CPU1 Voltage 1"
hexmask.long 0x10 0.--31. 1. "CPU1_VOL_REG1,CPU1 Voltage 1"
line.long 0x14 "CPU1_VOL_REG2,CPU1 Voltage 2"
hexmask.long 0x14 0.--31. 1. "CPU1_VOL_REG2,CPU1 Voltage 2"
line.long 0x18 "CPU1_VOL_REG3,CPU1 Voltage 3"
hexmask.long 0x18 0.--31. 1. "CPU1_VOL_REG3,CPU1 Voltage 3"
line.long 0x1C "CPU1_VOL_REG4,CPU1 Voltage 4"
hexmask.long 0x1C 0.--31. 1. "CPU1_VOL_REG4,CPU1 Voltage 4"
line.long 0x20 "CPU2_DVFS_CTRL,CPU2 DVFS Control"
hexmask.long.byte 0x20 25.--31. 1. "UART_VOL_VAL,UART Vol Value"
newline
bitfld.long 0x20 24. "CPU2_AHB1_INDEX_SEL_METHOD,CPU2 AHB1 index select method" "0,1"
newline
hexmask.long.byte 0x20 20.--23. 1. "CPU2_INACTIVE_AHB1_INDEX,CPU2 Inactive AHB1 Index"
newline
hexmask.long.byte 0x20 16.--19. 1. "CPU2_ACTIVE_AHB1_INDEX,CPU2 Active AHB1 Index"
newline
hexmask.long.byte 0x20 12.--15. 1. "CPU2_INACTIVE_SYS_INDEX,CPU2 Inactive System Index"
newline
hexmask.long.byte 0x20 8.--11. 1. "CPU2_ACTIVE_SYS_INDEX,CPU2 Active System Index"
newline
hexmask.long.byte 0x20 4.--7. 1. "CPU2_INACTIVE_INDEX,CPU2 Inactive Index"
newline
hexmask.long.byte 0x20 0.--3. 1. "CPU2_ACTIVE_INDEX,CPU2 Active Index"
line.long 0x24 "CPU2_FREQ_REG1,CPU2 Frequency 1"
hexmask.long 0x24 0.--31. 1. "CPU2_FREQ_REG1,CPU2 Frequency 1"
line.long 0x28 "CPU2_FREQ_REG2,CPU2 Frequency 2"
hexmask.long 0x28 0.--31. 1. "CPU2_FREQ_REG2,CPU2Frequency 2"
line.long 0x2C "CPU2_PLL_EN_REG,CPU2 PLL Enable"
hexmask.long 0x2C 0.--31. 1. "CPU2_PLL_EN_REG,CPU2 PLL Enable"
line.long 0x30 "CPU2_VOL_REG1,CPU2 Voltage 1"
hexmask.long 0x30 0.--31. 1. "CPU2_VOL_REG1,CPU2 Voltage 1"
line.long 0x34 "CPU2_VOL_REG2,CPU2 Voltage 2"
hexmask.long 0x34 0.--31. 1. "CPU2_VOL_REG2,CPU2 Voltage 2"
line.long 0x38 "CPU2_VOL_REG3,CPU2 Voltage 3"
hexmask.long 0x38 0.--31. 1. "CPU2_VOL_REG3,CPU2 Voltage 3"
line.long 0x3C "CPU2_VOL_REG4,CPU2 Voltage 4"
hexmask.long 0x3C 0.--31. 1. "CPU2_VOL_REG4,CPU2 Voltage 4"
line.long 0x40 "SYS_FREQ_REG1,System Frequency 1"
hexmask.long 0x40 0.--31. 1. "SYS_FREQ_REG1,System Frequency 1"
line.long 0x44 "SYS_FREQ_REG2,System Frequency 2"
hexmask.long 0x44 0.--31. 1. "SYS_FREQ_REG2,System Frequency 2"
line.long 0x48 "SYS_PLL_EN_REG,System PLL Enable"
hexmask.long 0x48 0.--31. 1. "SYS_PLL_EN_REG,System PLL Enable"
line.long 0x4C "SYS_VOL_REG1,System Voltage 1"
hexmask.long 0x4C 0.--31. 1. "SYS_VOL_REG1,System Voltage 1"
line.long 0x50 "SYS_VOL_REG2,System Voltage 2"
hexmask.long 0x50 0.--31. 1. "SYS_VOL_REG2,System Voltage 2"
line.long 0x54 "SYS_VOL_REG3,System Voltage 3"
hexmask.long 0x54 0.--31. 1. "SYS_VOL_REG3,System Voltage 3"
line.long 0x58 "SYS_VOL_REG4,System Voltage 4"
hexmask.long 0x58 0.--31. 1. "SYS_VOL_REG4,System Voltage 4"
line.long 0x5C "DVFS_CTRL,DVFS Control"
hexmask.long.byte 0x5C 25.--31. 1. "SDIO_VOL_VAL,SDIO Vol Value"
newline
bitfld.long 0x5C 24. "INACTIVE_ACK_EXT_EN,Inactive Ack Ext Enable" "0,1"
newline
bitfld.long 0x5C 21. "UPDATE_BUCK_EN,to enable the forcing buck value when the resolution is not aligned" "0,1"
newline
bitfld.long 0x5C 20. "EN_FASTER_DVFS,Enable Faster DVFS" "0,1"
newline
bitfld.long 0x5C 19. "SW_LOCK_GUARD_DIS,SW Lock Guard Disable" "0,1"
newline
bitfld.long 0x5C 18. "DVFS_EAS_VOL_DIS,DVFS EAS Vol Disable" "0,1"
newline
bitfld.long 0x5C 17. "EN_FASTER_DYN_CLK,Enable Faster Dynamic Clock" "0,1"
newline
bitfld.long 0x5C 16. "DVFS_MODE,DVFS Mode 0: only use partial_dvfs_vol(default)" "0: only use partial_dvfs_vol,?"
newline
bitfld.long 0x5C 15. "DVFS_DYN_CLK_EN,DVFS Dynamic Clock Enable" "0,1"
newline
bitfld.long 0x5C 14. "DVFS_CLK_SWITCH_EN,DVFS Clock Switch Enable" "0,1"
newline
hexmask.long.byte 0x5C 7.--13. 1. "DVFS_EAS_VOL,DVFS EAS Vol"
newline
hexmask.long.byte 0x5C 0.--6. 1. "DVFS_HOST_VOL_VAL,DVFS Host Vol Value"
line.long 0x60 "PARTIAL_DVFS_CTRL,Partial DVFS Control"
bitfld.long 0x60 31. "BYPASS_DVFS_FSM,Bypass DVFS FSM" "0,1"
newline
hexmask.long.byte 0x60 21.--25. 1. "VOL_RESOLUTION_SLP,Vol Resolution Sleep"
newline
hexmask.long.byte 0x60 16.--20. 1. "VOL_RESOLUTION_REF,Vol Resolution Ref"
newline
hexmask.long.byte 0x60 8.--11. 1. "STATIC_DVFS_FREQ,Static DVFS Frequency"
newline
bitfld.long 0x60 7. "STATIC_PLL_EN,Static PLL Enable" "0,1"
newline
hexmask.long.byte 0x60 0.--6. 1. "PARTIAL_DVFS_VOL,Partial DVFS Vol"
line.long 0x64 "DVFS_TIMER,DVFS Timer"
hexmask.long.word 0x64 16.--31. 1. "REF_CNT,Reference Count"
newline
hexmask.long.word 0x64 0.--15. 1. "SLP_CNT,Sleep Count"
group.long 0x270++0x1B
line.long 0x0 "AHB1_FREQ_REG1,AHB1 Frequency 1"
hexmask.long 0x0 0.--31. 1. "AHB1_FREQ_REG1,AHB1 Frequency 1"
line.long 0x4 "AHB1_FREQ_REG2,AHB1 Frequency 2"
hexmask.long 0x4 0.--31. 1. "AHB1_FREQ_REG2,AHB1 Frequency 2"
line.long 0x8 "AHB1_PLL_EN_REG,AHB1 PLL Enable"
hexmask.long 0x8 0.--31. 1. "AHB1_PLL_EN_REG,AHB1 PLL Enable"
line.long 0xC "AHB1_VOL_REG1,AHB1 Voltage 1"
hexmask.long 0xC 0.--31. 1. "AHB1_VOL_REG1,AHB1 Voltage 1"
line.long 0x10 "AHB1_VOL_REG2,AHB1 Voltage 2"
hexmask.long 0x10 0.--31. 1. "AHB1_VOL_REG2,AHB1 Voltage 2"
line.long 0x14 "AHB1_VOL_REG3,AHB1 Voltage 3"
hexmask.long 0x14 0.--31. 1. "AHB1_VOL_REG3,AHB1 Voltage 3"
line.long 0x18 "AHB1_VOL_REG4,AHB1 Voltage 4"
hexmask.long 0x18 0.--31. 1. "AHB1_VOL_REG4,AHB1 Voltage 4"
rgroup.long 0x298++0x3
line.long 0x0 "DVFS_STATUS,DVFS Status"
bitfld.long 0x0 31. "SW_LOCK_GAURD,SW Lock Guard" "0,1"
newline
bitfld.long 0x0 30. "SW_FREQ_GAURD,SW Frequency Guard" "0,1"
newline
hexmask.long.byte 0x0 23.--29. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
bitfld.long 0x0 22. "PCIE_VOL_LVL_REACHED,PCIe Vol Level Reached" "0,1"
newline
bitfld.long 0x0 21. "USB_VOL_LVL_REACHED,USB Vol Level Reached" "0,1"
newline
bitfld.long 0x0 20. "SOC_POWER_LVL_REACHED,SoC Power Level Reached" "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x0 12.--15. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x0 8.--11. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
bitfld.long 0x0 7. "LOCK_VOL_REQ,Lock Vol Request" "0,1"
newline
bitfld.long 0x0 6. "CPU1_LOCK_VOL,CPU1 Lock Vol" "0,1"
newline
bitfld.long 0x0 5. "CPU2_LOCK_VOL,CPU2 Lock Vol" "0,1"
newline
bitfld.long 0x0 4. "SYS_LOCK_VOL,System Lock Vol" "0,1"
newline
bitfld.long 0x0 3. "LOCK_FREQ_REQ,Lock Frequency Request" "0,1"
newline
bitfld.long 0x0 2. "CPU1_LOCK_FREQ,CPU1 Lock Frequency" "0,1"
newline
bitfld.long 0x0 1. "CPU2_LOCK_FREQ,CPU2 Lock Frequency" "0,1"
newline
bitfld.long 0x0 0. "SYS_LOCK_FREQ,System Lock Frequency" "0,1"
group.long 0x29C++0x7
line.long 0x0 "DVFS_DBG_CTRL,DVFS Debug Control"
bitfld.long 0x0 16. "SD_CLK_SWITCH_OK_MASK,SD Clock Switch Ok Mask" "0,1"
newline
bitfld.long 0x0 15. "BUCK_EFF_MODE_FIX,BUCK Efficiency Mode Fix" "0,1"
newline
bitfld.long 0x0 13. "DVFS_CLK_SEL_FW_VAL,DVFS Clock Select FW Value" "0,1"
newline
bitfld.long 0x0 12. "DVFS_CLK_SEL_FW_BYPASS,DVFS Clock Select FW Bypass" "0,1"
newline
bitfld.long 0x0 8.--9. "DBG_SLP_TIMER_SEL,Debug Sleep Timer Select" "0,1,2,3"
newline
bitfld.long 0x0 4.--6. "DBG_VOL_SEL,Debug Vol Select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "END_TRIGGER,End Trigger" "0,1"
newline
bitfld.long 0x0 1. "START_TRIGGER,Start Trigger" "0,1"
newline
bitfld.long 0x0 0. "DVFS_DBG_MODE,DVFS Debug Mode" "0,1"
line.long 0x4 "DVFS_DBG_PATTERN_DATA,DVFS Debug Pattern Data"
hexmask.long.byte 0x4 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x4 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x4 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x4 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x4 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x4 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x4 0.--4. 1. "VOL_REQ,Vol Request"
rgroup.long 0x2A4++0x1B
line.long 0x0 "DVFS_DBG_REG0,DVFS Debug 0"
hexmask.long.byte 0x0 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x0 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x0 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x0 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x0 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x0 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x0 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x4 "DVFS_DBG_REG1,DVFS Debug 1"
hexmask.long.byte 0x4 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x4 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x4 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x4 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x4 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x4 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x4 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x8 "DVFS_DBG_REG2,DVFS Debug 2"
hexmask.long.byte 0x8 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x8 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x8 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x8 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x8 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x8 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x8 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0xC "DVFS_DBG_REG3,DVFS Debug 3"
hexmask.long.byte 0xC 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0xC 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0xC 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0xC 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0xC 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0xC 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0xC 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x10 "DVFS_DBG_REG4,DVFS Debug 4"
hexmask.long.byte 0x10 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x10 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x10 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x10 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x10 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x10 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x10 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x14 "DVFS_DBG_REG5,DVFS Debug 5"
hexmask.long.byte 0x14 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x14 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x14 17.--21. 1. "APU_BUCK_LVL_CTRL,APU BUCK Level Control"
newline
hexmask.long.byte 0x14 13.--16. 1. "CPU1_FREQ_CTRL,CPU1 Frequency Control"
newline
hexmask.long.byte 0x14 9.--12. 1. "CPU2_FREQ_CTRL,CPU2 Frequency Control"
newline
hexmask.long.byte 0x14 5.--8. 1. "SYS_FREQ_CTRL,System Frequency Control"
newline
hexmask.long.byte 0x14 0.--4. 1. "VOL_REQ,Vol Request"
line.long 0x18 "DVFS_DBG_STATUS,DVFS Debug Status"
hexmask.long.byte 0x18 27.--31. 1. "HW_VOL_REQ,HW Vol Request"
newline
hexmask.long.byte 0x18 22.--26. 1. "SW_VOL_REQ,SW Vol Request"
newline
hexmask.long.byte 0x18 18.--21. 1. "VOL_REQ,Vol Request"
newline
bitfld.long 0x18 17. "NOM_VOL_LVL_REACHED,Nominal Vol Level Reached" "0,1"
newline
bitfld.long 0x18 16. "NFC_VOL_LVL_REACHED,NFC Vol Level Reached" "0,1"
newline
bitfld.long 0x18 15. "WLAN_VOL_LVL_REACHED,WLAN Vol Level Reached" "0,1"
newline
bitfld.long 0x18 12. "PMIC_TIMER_DONE_REG,PMIC Timer Done" "0,1"
newline
bitfld.long 0x18 11. "SW_FREQ_GAURD_EN,SW Frequency Guard Enable" "0,1"
newline
bitfld.long 0x18 10. "EAS_SEL,EAS Select" "0,1"
newline
bitfld.long 0x18 9. "DVFS_CLK_SEL_DVFSCK,DVFS Clock Select DVFSCK" "0,1"
newline
bitfld.long 0x18 8. "SW_LOCK_GAURD_EN,SW Lock Guard Enable" "0,1"
newline
bitfld.long 0x18 7. "RESET_COUNTER_SYNCED,voltage corresponding to PMIC code 0x3" "0,1"
newline
bitfld.long 0x18 6. "KEEP_DVFS_LVL_ACTIVE,Keep DVFS Level Active" "0,1"
newline
hexmask.long.byte 0x18 1.--5. 1. "BUCK_LVL_REACHED,voltage corresponding to PMIC code 0x2"
newline
bitfld.long 0x18 0. "DVFS_DBG_LOG_DONE,DVFS Debug Log Done" "0,1"
group.long 0x2C0++0x3
line.long 0x0 "DVFS_DBG_PATTERN_MASK,DVFS Debug Patter Mask"
hexmask.long 0x0 0.--31. 1. "MASK,Mask to Delay"
group.long 0x2F8++0x13
line.long 0x0 "DVFS_PMIC_TIMER,DVFS PMIC Timer"
hexmask.long.word 0x0 20.--31. 1. "ACTIVE_CNT,Active Count"
newline
hexmask.long.byte 0x0 16.--19. 1. "SLP_CNT,Sleep Counts"
newline
hexmask.long.word 0x0 0.--15. 1. "REF_CNT,Reference Count"
line.long 0x4 "DVFS_PMIC_MAP,DVFS PMIC Map"
bitfld.long 0x4 31. "USE_PMIC_TIMER,Use PMIC Timer" "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "DVFS_VOL_FOR_PMIC3,DVFS Vol for PMIC 3"
newline
hexmask.long.byte 0x4 16.--22. 1. "DVFS_VOL_FOR_PMIC2,DVFS Vol for PMIC 2"
newline
hexmask.long.byte 0x4 8.--14. 1. "DVFS_VOL_FOR_PMIC1,DVFS Vol for PMIC 1"
newline
hexmask.long.byte 0x4 0.--6. 1. "DVFS_VOL_FOR_PMIC0,DVFS Vol for PMIC 0"
line.long 0x8 "LDO_CTRL,LDO Control"
bitfld.long 0x8 31. "KEEP_LDO_MAIN_WHILE_SLP,Keep LDO Main While Sleep" "0,1"
newline
bitfld.long 0x8 30. "USE_XOSC_EN_AS_SEL,Use XOSC Enable as Select" "0,1"
newline
hexmask.long.byte 0x8 8.--15. 1. "BACKUP_DELAY_COUNTER_VAL,Backup Delay Counter Value"
newline
bitfld.long 0x8 4.--5. "MAIN_DELAY_COUNTER_VAL,Main Delay Counter Value" "0,1,2,3"
newline
bitfld.long 0x8 1. "BACKUP_DELAY_CNT_EN,Backup Delay Count Enable" "0,1"
newline
bitfld.long 0x8 0. "MAIN_DELAY_CNT_EN,Main Delay Count Enable" "0,1"
line.long 0xC "LDO_BACKUP_LVL_MAP1,LDO Backup Level Map 1"
hexmask.long 0xC 0.--31. 1. "LDO_BACKUP_LVL_MAP1,LDO Backup Level Map 1"
line.long 0x10 "LDO_BACKUP_LVL_MAP2,LDO Backup Level Map 2"
hexmask.long 0x10 0.--31. 1. "LDO_BACKUP_LVL_MAP2,LDO Backup Level Map 2"
rgroup.long 0x30C++0x3
line.long 0x0 "LDO_STATUS,LDO Status"
bitfld.long 0x0 25. "BKUP_LVL1_SEL,Backup Level 1 Select" "0,1"
newline
bitfld.long 0x0 24. "BKUP_LVL2_SEL,Backup Level 2 Select" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "BACKUP_DELAY_CNT,Backup Delay Count (to check testbus)"
newline
bitfld.long 0x0 15. "LDO_BACKUP_EN,LDO Backup Enable" "0,1"
newline
bitfld.long 0x0 14. "D_LDO_BACKUP_EN,D LDO Backup Enable" "0,1"
newline
bitfld.long 0x0 13. "BACK_DELAY_CNT_MET,Back Delay Count Met" "0,1"
newline
bitfld.long 0x0 12. "ACTIVE_SEL,Active Select" "0,1"
newline
bitfld.long 0x0 11. "LDO_MAIN_PD,LDO Main Powerdown" "0,1"
newline
bitfld.long 0x0 10. "MAIN_PD_DELAY_CNT_MET,Main Powerdown Delay Count Met" "0,1"
newline
bitfld.long 0x0 8.--9. "MAIN_PD_DELAY_CNT,Main Powerdown Delay Count" "0,1,2,3"
newline
hexmask.long.byte 0x0 4.--7. 1. "LDO_MAIN_LVL,LDO Main Level"
newline
bitfld.long 0x0 0.--2. "LDO_BACKUP_LVL,LDO Backup Level" "0,1,2,3,4,5,6,7"
group.long 0x310++0x7
line.long 0x0 "RC32_CAL_CTRL,RC32 Calibration Control"
hexmask.long.byte 0x0 4.--10. 1. "RC32_CAL_VOL_VAL,RC32 Calibration Vol Value"
newline
bitfld.long 0x0 3. "USE_RC32_CAL_DONE,Use RC32 Calibration Done" "0,1"
newline
bitfld.long 0x0 2. "RC32_PARTIAL_CAL_EN_ON_BT_WKUP,RC32 Partial Calibration Enable on Bluetooth Wakeup" "0,1"
newline
bitfld.long 0x0 1. "RC32_PARTIAL_CAL_EN,RC32 Partial Calibration Enable" "0,1"
newline
bitfld.long 0x0 0. "RC32_FULL_CAL_EN,RC32 Full Calibration Enable" "0,1"
line.long 0x4 "RC32_CAL_SLPCLK_TIMER,RC32 Calibration Sleep Clock Timer"
hexmask.long 0x4 0.--31. 1. "RC32_CAL_SLPCLK_TIMER,RC32 Calibration Sleep Clock Timer"
rgroup.long 0x318++0x3
line.long 0x0 "RC32CAL_SLPCLK_CNT_RD,RC32 Calibration Sleep Clock Count Read"
hexmask.long 0x0 0.--31. 1. "RC32CAL_SLPCLK_CNT_RD,RC32 Calibration Sleep Clock Count Read"
group.long 0x338++0x1F
line.long 0x0 "TSTBUS_DATA,Testbus Data"
hexmask.long 0x0 0.--31. 1. "TSTBUS_DATA,Testbus Data"
line.long 0x4 "TST_CTRL,Test Control"
bitfld.long 0x4 28.--30. "CPU1_HOST_TST_CTRL,CPU1 Host Test Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24.--25. "HOST_TST_CTRL,Host Test Control" "0,1,2,3"
newline
bitfld.long 0x4 23. "USE_SOC_APU_SUBTEST,Use SoC APU Subtest" "0,1"
newline
bitfld.long 0x4 21.--22. "APU_REG_SUBTEST_SEL,APU Reg Subtest Select" "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--20. 1. "APU_TESTBUS_SEL,APU Testbus Select"
newline
hexmask.long.byte 0x4 12.--15. 1. "TEST_MUX_SEL_SHIFT_BIT,Test MUX Select Shift"
newline
hexmask.long.byte 0x4 7.--11. 1. "CPU2_HOST_TST_CTRL,CPU2 Host Test Control"
newline
bitfld.long 0x4 5. "CPU1_CP15_SLP_CTRL,CPU1 CP15 Sleep Control" "0,1"
newline
bitfld.long 0x4 4. "WLAN_TST_CTRL,WLAN Test Control" "0,1"
newline
bitfld.long 0x4 3. "CPU2_CP15_SLP_CTRL,CPU2 CP15 Sleep Control" "0,1"
newline
bitfld.long 0x4 2. "NFC_TST_CTRL,NFC Test Control" "0,1"
newline
bitfld.long 0x4 1. "FM_TST_CTRL,FM Test Control" "0,1"
newline
bitfld.long 0x4 0. "BT_BLE_TST_CTRL,Bluetooth BLE Test Control" "0,1"
line.long 0x8 "BCA_LTE_CTRL,BCA LTE Control"
bitfld.long 0x8 31. "BCA_CLK_FW_EN,BCA Clock FW Enable" "0,1"
newline
bitfld.long 0x8 30. "BCA_FORCE_ON_WHILE_BT,BCA Force on While Bluetooth" "0,1"
newline
bitfld.long 0x8 20. "USE_SLNA_WHILE_BT,Use sLNA While Bluetooth" "0,1"
newline
bitfld.long 0x8 16. "BCA_BT_LTE_COEX_EN,BCA Bluetooth LTE Coexistence Enable" "0,1"
newline
bitfld.long 0x8 15. "BCA_WL_LTE_COEX_EN,BCA WLAN LTE Coexistence Enable" "0,1"
newline
bitfld.long 0x8 7. "BCA_LTE_CLK_BYP,BCA LTE Clock Bypass" "0,1"
newline
bitfld.long 0x8 4. "LTE_TMR2_CNT_FREEZE,LTE TMR2 Count Freeze" "0,1"
newline
bitfld.long 0x8 3. "LTE_TMR1_CNT_FREEZE,LTE TMR1 Count Freeze" "0,1"
newline
bitfld.long 0x8 2. "LTE_TMR2_INT,LTE TMR2 Interrupt" "0,1"
newline
bitfld.long 0x8 1. "LTE_TMR1_INT,LTE TMR1 Interrupt" "0,1"
newline
bitfld.long 0x8 0. "LTE_CNT_START,LTE Count Start" "0,1"
line.long 0xC "BCA_LTE_TIMER1,BCA LTE Timer 1"
hexmask.long 0xC 0.--31. 1. "BCA_LTE_TIMER1,BCA LTE Timer 1"
line.long 0x10 "BCA_LTE_TIMER2,BCA LTE Timer 2"
hexmask.long 0x10 0.--31. 1. "BCA_LTE_TIMER2,BCA LTE Timer 2"
line.long 0x14 "BCA_MWS_WKUP_TIMER,BCA MWS Wakeup Timer"
hexmask.long.byte 0x14 28.--31. 1. "BCA_BCN_WKUP_CNT,BCA Beacon Wakeup Count"
newline
hexmask.long.word 0x14 0.--15. 1. "BCA_MWS_TIMER,BCA MWS Timer"
line.long 0x18 "BT2_CTRL,Bluetooth 2 Control"
bitfld.long 0x18 31. "BT_HOST_SLP_RDY,Bluetooth Host Sleep Ready" "0,1"
newline
bitfld.long 0x18 30. "BT_PLL_SYNC_MODE_SEL,Bluetooth PLL Sync Mode Select" "0,1"
newline
bitfld.long 0x18 29. "BT_CLK_SYNC_MODE_SEL0,Bluetooth Clock Sync Mode Select 0" "0,1"
newline
bitfld.long 0x18 28. "BRF_CLK_SYNC_MODE_SEL,BRF Clock Sync Mode Select" "0,1"
newline
bitfld.long 0x18 27. "USE_GLITCH_FREE_BT_CLK_REQ,Use Glitch-Free Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x18 26. "BT_CLK_SYNC_MODE_SEL1,Bluetooth Clock Sync Mode Select 1" "0,1"
newline
bitfld.long 0x18 7. "USE_BT_INTR_SLP,Use Bluetooth interrupt Sleep" "0,1"
newline
bitfld.long 0x18 3. "BTU_CLK_NCO_MODE_SEL_EN,1- ignore the btu_clk_nco_mode from CIU2 keep the bt_clk_req as XP wakeup source" "0,1"
newline
bitfld.long 0x18 2. "BT_SLP_RDY_FW,Bluetooth Sleep Ready FW" "0,1"
newline
bitfld.long 0x18 1. "BT_SLP_RDY_MASK,Bluetoot Sleep Ready Mask" "0,1"
newline
bitfld.long 0x18 0. "BT_SLP_RDY,Bluetooth Sleep Ready" "0,1"
line.long 0x1C "BT2_WKUP_MASK,Bluetooth 2 Wakeup Mask"
hexmask.long.word 0x1C 16.--31. 1. "BT_HOST_MAP,Bluetooth Host Map"
newline
bitfld.long 0x1C 5. "BRF_PLL_REQ_MASK,BRF PLL Request Mask" "0,1"
newline
bitfld.long 0x1C 4. "BT_PLL_REQ_MASK,Bluetooth PLL Request Mask" "0,1"
newline
bitfld.long 0x1C 3. "BT_INTR_MASK,Bluetooth Interrupt Mask" "0,1"
newline
bitfld.long 0x1C 2. "BT_WB_ACTIVE_REQ_MASK,Bluetooth WB Active Request Mask" "0,1"
newline
bitfld.long 0x1C 1. "BT_CLK_REQ_MASK,Bluetooth Clock Request Mask" "0,1"
newline
bitfld.long 0x1C 0. "BCA_CLK_REQ_MASK,BCA Clock Request Mask" "0,1"
rgroup.long 0x358++0x3
line.long 0x0 "BT2_STATUS,Bluetooth 2 Status"
hexmask.long.word 0x0 16.--31. 1. "HOST_WKUP_IN,Host Wakeup In"
newline
bitfld.long 0x0 9. "BT_WIDEBAND_ACTIVE,Bluetooth Wideband Active" "0,1"
newline
bitfld.long 0x0 8. "BRF_PLL_REQ,BRF PLL Request" "0,1"
newline
bitfld.long 0x0 7. "BT_CLK_REQ,Bluetooth Clock Request" "0,1"
newline
bitfld.long 0x0 6. "BT_PLL_REQ,Bluetooth PLL Request" "0,1"
newline
bitfld.long 0x0 5. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 4. "BT_HOST_WKUP,Bluetooth Host Wakeup" "0,1"
newline
bitfld.long 0x0 2. "BT_ACTIVE_SLPCK,Bluetooth Active Sleep Clock" "0,1"
newline
bitfld.long 0x0 1. "APU_BRF_CLK_EN,APU BRF Clock Enable" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_CLK_EN,APU Bluetooth Clock Enable" "0,1"
group.long 0x35C++0x13
line.long 0x0 "BT2_CKEN_CTRL,Bluetooth 2 Clock Enable Control"
bitfld.long 0x0 5. "BT_CLK_EN_SEL,selection for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 4. "BT_CLK_EN_VAL,control value for bt_clk_en when PLL ready" "0,1"
newline
bitfld.long 0x0 3. "BT_CLK_EN_SEL_XOSC,selection for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 2. "BT_CLK_EN_VAL_XOSC,control value for bt_clk_en when XOSC ready" "0,1"
newline
bitfld.long 0x0 1. "BL_CLK_EN_SEL_PWR,selection for bt_clk_en when power ready" "0,1"
newline
bitfld.long 0x0 0. "BT_CLK_EN_VAL_PWR,control value for bt_clk_en when power ready" "0,1"
line.long 0x4 "BT2_RESRC_CTRL,Bluetooth 2 RESRC Control"
bitfld.long 0x4 11. "FW_ALLWAKE_REQ_VAL,firmware override value when apu_bt_resrc_ctrl[10] is set" "0,1"
newline
bitfld.long 0x4 10. "FW_ALLWAKE_REQ,firmware override hw xosc + pwr + pll allwake request" "0,1"
newline
bitfld.long 0x4 9. "FW_IPWAKE_REQ_VAL,override value when apu_bt_resrc_ctrl[8] is set" "0,1"
newline
bitfld.long 0x4 8. "FW_IPWAKE_REQ,override hw xosc + pwr + pll ipwake request" "0,1"
newline
bitfld.long 0x4 7. "FW_SB_REQ_VAL,override value when apu_bt_resrc_ctrl[6] is set" "0,1"
newline
bitfld.long 0x4 6. "FW_SB_REQ,override hw xosc + pwr + pll sb request" "0,1"
newline
bitfld.long 0x4 5. "FW_XP_REQ_VAL,override value when apu_bt_resrc_ctrl[4] is set" "0,1"
newline
bitfld.long 0x4 4. "FW_XP_REQ,override hw xosc + pwr request" "0,1"
newline
bitfld.long 0x4 3. "FW_XOSC_REQ_VAL,override value when apu_bt_resrc_ctrl[2] is set" "0,1"
newline
bitfld.long 0x4 2. "FW_XOSC_REQ,override hw xosc request" "0,1"
newline
bitfld.long 0x4 1. "FW_PWR_REQ_VAL,override value when apu_bt_resrc_ctrl[0] is set" "0,1"
newline
bitfld.long 0x4 0. "FW_PWR_REQ,override hw power request" "0,1"
line.long 0x8 "BT2_DVFS_CTRL,Bluetooth 2 DVFS Control"
hexmask.long.byte 0x8 0.--6. 1. "BT_VOL_VAL,Blueooth Vol Value"
line.long 0xC "BLE2_CTRL,BLE 2 Control"
bitfld.long 0xC 31. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0xC 15. "BT_AES_NCO_MODE,Bluetooth AES NCO Mode" "0,1"
newline
bitfld.long 0xC 3. "BLE_MODE_EN,BLE Mode Enable" "0,1"
newline
bitfld.long 0xC 2. "BLE_SLP_RDY_FW,BLE Sleep Ready FW" "0,1"
newline
bitfld.long 0xC 1. "BLE_SLP_RDY_MASK,BLE Sleep Ready Mask" "0,1"
newline
bitfld.long 0xC 0. "BLE_SLP_RDY,BLE Sleep Ready" "0,1"
line.long 0x10 "BLE2_WKUP_MASK,BLE 2 Wakeup Mask"
bitfld.long 0x10 4. "LBC_XP_REQ_MASK,LBC XP Request Mask" "0,1"
newline
bitfld.long 0x10 3. "BT_AES_CLK_REQ_MASK,Bluetooth AES Clock Request Mask" "0,1"
rgroup.long 0x370++0x3
line.long 0x0 "BLE2_STATUS,BLE 2 Status"
bitfld.long 0x0 9. "BT_AES_CLK_REQ,Bluetooth AES Clock Request Mask" "0,1"
newline
bitfld.long 0x0 8. "LBC_XP_REQ,LBC XP Request" "0,1"
newline
bitfld.long 0x0 6. "BT_AES_NCO_MODE,Blueooth AES NCO Mode" "0,1"
newline
bitfld.long 0x0 5. "BLE_XP_REQ,BLE XP Request" "0,1"
newline
bitfld.long 0x0 4. "BT_INTERRUPT,Bluetooth Interrupt" "0,1"
newline
bitfld.long 0x0 3. "T1_STABLE,T1 Delay" "0,1"
newline
bitfld.long 0x0 2. "XOSC_STABLE_REFCK,XOSC Stable Ref Clock" "0,1"
newline
bitfld.long 0x0 1. "BT_AES_CLK_SEL,Bluetooth AES Clock Select" "0,1"
newline
bitfld.long 0x0 0. "APU_BT_AES_CLK_EN,APU Bluetooth AES Clock Enable" "0,1"
rgroup.long 0x380++0x3
line.long 0x0 "LMU_IP_REVISION,LMU IP Revision"
hexmask.long.word 0x0 0.--15. 1. "IP_REV,IP Revision"
group.long 0x384++0x3
line.long 0x0 "LMU_CPU1_STA_CFG,LMU CPU1 STA Configuration"
bitfld.long 0x0 31. "RESERVED0,Reserved 0" "0,1"
newline
bitfld.long 0x0 30. "BANK15_STA_OFF_EN,Bank15 STA Off Enable" "0,1"
newline
bitfld.long 0x0 29. "RESERVED1,Reserved 1" "0,1"
newline
bitfld.long 0x0 28. "BANK14_STA_OFF_EN,Bank14 STA Off Enable" "0,1"
newline
bitfld.long 0x0 27. "RESERVED2,Reserved 2" "0,1"
newline
bitfld.long 0x0 26. "BANK13_STA_OFF_EN,Bank13 STA Off Enable" "0,1"
newline
bitfld.long 0x0 25. "RESERVED3,Reserved 3" "0,1"
newline
bitfld.long 0x0 24. "BANK12_STA_OFF_EN,Bank12 STA Off Enable" "0,1"
newline
bitfld.long 0x0 23. "RESERVED4,Reserved 4" "0,1"
newline
bitfld.long 0x0 22. "BANK11_STA_OFF_EN,Bank11 STA Off Enable" "0,1"
newline
bitfld.long 0x0 21. "RESERVED5,Reserved 5" "0,1"
newline
bitfld.long 0x0 20. "BANK10_STA_OFF_EN,Bank10 STA Off Enable" "0,1"
newline
bitfld.long 0x0 19. "RESERVED6,Reserved 6" "0,1"
newline
bitfld.long 0x0 18. "BANK9_STA_OFF_EN,Bank9 STA Off Enable" "0,1"
newline
bitfld.long 0x0 17. "RESERVED7,Reserved 7" "0,1"
newline
bitfld.long 0x0 16. "BANK8_STA_OFF_EN,Bank8 STA Off Enable" "0,1"
newline
bitfld.long 0x0 15. "RESERVED8,Reserved 8" "0,1"
newline
bitfld.long 0x0 14. "BANK7_STA_OFF_EN,Bank7 STA Off Enable" "0,1"
newline
bitfld.long 0x0 13. "RESERVED9,Reserved 9" "0,1"
newline
bitfld.long 0x0 12. "BANK6_STA_OFF_EN,Bank6 STA Off Enable" "0,1"
newline
bitfld.long 0x0 11. "RESERVED10,Reserved 10" "0,1"
newline
bitfld.long 0x0 10. "BANK5_STA_OFF_EN,Bank5 STA Off Enable" "0,1"
newline
bitfld.long 0x0 9. "RESERVED11,Reserved 11" "0,1"
newline
bitfld.long 0x0 8. "BANK4_STA_OFF_EN,Bank4 STA Off Enable" "0,1"
newline
bitfld.long 0x0 7. "RESERVED12,Reserved 12" "0,1"
newline
bitfld.long 0x0 6. "BANK3_STA_OFF_EN,Bank3 STA Off Enable" "0,1"
newline
bitfld.long 0x0 5. "RESERVED13,Reserved 13" "0,1"
newline
bitfld.long 0x0 4. "BANK2_STA_OFF_EN,Bank2 STA Off Enable" "0,1"
newline
bitfld.long 0x0 3. "RESERVED14,Reserved 14" "0,1"
newline
bitfld.long 0x0 2. "BANK1_STA_OFF_EN,Bank1 STA Off Enable" "0,1"
newline
bitfld.long 0x0 1. "RESERVED15,Reserved 15" "0,1"
newline
bitfld.long 0x0 0. "BANK0_STA_OFF_EN,Bank0 STA Off Enable" "0,1"
rgroup.long 0x388++0x7
line.long 0x0 "LMU_CPU1_STA_STATUS1,LMU CPU1 STA Status 1"
bitfld.long 0x0 29.--31. "BANK7_FSM_ST,Bank7 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK7_FSM_ST_REP_DONE,Bank7 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK6_FSM_ST,Bank6 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK6_FSM_ST_REP_DONE,Bank6 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK5_FSM_ST,Bank5 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK5_FSM_ST_REP_DONE,Bank5 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK4_FSM_ST,Bank4 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK4_FSM_ST_REP_DONE,Bank4 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK3_FSM_ST_REP_DONE,Bank3 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK2_FSM_ST,Bank2 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK2_FSM_ST_REP_DONE,Bank2 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK1_FSM_ST_REP_DONE,Bank1FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK0_FSM_ST_REP_DONE,Bank0 FSM St Rep Done" "0,1"
line.long 0x4 "LMU_CPU1_STA_STATUS2,LMU CPU1 STA Status 2"
bitfld.long 0x4 29.--31. "BANK15_FSM_ST,Bank15 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 28. "BANK15_FSM_ST_REP_DONE,Bank15 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 25.--27. "BANK14_FSM_ST,Bank14 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "BANK14_FSM_ST_REP_DONE,Bank14 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 21.--23. "BANK13_FSM_ST,Bank13 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "BANK13_FSM_ST_REP_DONE,Bank13 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 17.--19. "BANK12_FSM_ST,Bank12 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "BANK12_FSM_ST_REP_DONE,Bank12 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 13.--15. "BANK11_FSM_ST,Bank11 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "BANK11_FSM_ST_REP_DONE,Bank11 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 9.--11. "BANK10_FSM_ST,Bank10 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 8. "BANK10_FSM_ST_REP_DONE,Bank10 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 5.--7. "BANK9_FSM_ST,Bank9 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "BANK9_FSM_ST_REP_DONE,Bank9 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 1.--3. "BANK8_FSM_ST,Bank8 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "BANK8_FSM_ST_REP_DONE,Bank8 FSM St Rep Done" "0,1"
group.long 0x398++0x3
line.long 0x0 "LMU_CPU1_DYN_CTRL,LMU CPU1 Dynamic Control"
hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED0,Reserved 0"
newline
bitfld.long 0x0 13. "BANK3_DYN_PD,Bank3 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 12. "BANK3_DYN_MODE_EN,Bank3 Dynamic Mode Enable" "0,1"
newline
bitfld.long 0x0 10.--11. "RESERVED1,Reserved 1" "0,1,2,3"
newline
bitfld.long 0x0 9. "BANK2_DYN_PD,Bank2 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 8. "BANK2_DYN_MODE_EN,Bank2 Dynamic Mode Enable" "0,1"
newline
bitfld.long 0x0 6.--7. "RESERVED2,Reserved 2" "0,1,2,3"
newline
bitfld.long 0x0 5. "BANK1_DYN_PD,Bank1 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 4. "BANK1_DYN_MODE_EN,Bank1 Dynamic Mode Enable" "0,1"
newline
bitfld.long 0x0 2.--3. "RESERVED3,Reserved 3" "0,1,2,3"
newline
bitfld.long 0x0 1. "BANK0_DYN_PD,Bank0 Dynamic Powerdown" "0,1"
newline
bitfld.long 0x0 0. "BANK0_DYN_MODE_EN,Bank0 Dynamic Mode Enable" "0,1"
rgroup.long 0x39C++0x3
line.long 0x0 "LMU_CPU1_DYN_STATUS,LMU CPU1 Dynamic Status"
bitfld.long 0x0 14.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 13. "BANK3_DYN_REP,Bank3 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 12. "BANK3_DYN_REP_REQ,Bank3 Dynamic Rep Request" "0,1"
newline
bitfld.long 0x0 10.--11. "BANK2_FSM_ST,Bank2 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 9. "BANK2_DYN_REP,Bank2 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 8. "BANK2_DYN_REP_REQ,Bank2 Dynamic Rep Request" "0,1"
newline
bitfld.long 0x0 6.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 5. "BANK1_DYN_REP,Bank1 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 4. "BANK1_DYN_REP_REQ,Bank1 Dynamic Rep Request" "0,1"
newline
bitfld.long 0x0 2.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3"
newline
bitfld.long 0x0 1. "BANK0_DYN_REP,Bank0 Dynamic Rep" "0,1"
newline
bitfld.long 0x0 0. "BANK0_DYN_REP_REQ,Bank0 Dynamic Rep Request" "0,1"
group.long 0x3A8++0x3
line.long 0x0 "LMU_CPU2_STA_CFG,LMU CPU2 STA Configuration"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED0,Reserved 0"
newline
bitfld.long 0x0 14. "BANK7_STA_OFF_EN,Bank7 STA Off Enable" "0,1"
newline
bitfld.long 0x0 13. "RESERVED1,Reserved 1" "0,1"
newline
bitfld.long 0x0 12. "BANK6_STA_OFF_EN,Bank6 STA Off Enable" "0,1"
newline
bitfld.long 0x0 11. "RESERVED2,Reserved 2" "0,1"
newline
bitfld.long 0x0 10. "BANK5_STA_OFF_EN,Bank5 STA Off Enable" "0,1"
newline
bitfld.long 0x0 9. "RESERVED3,Reserved 3" "0,1"
newline
bitfld.long 0x0 8. "BANK4_STA_OFF_EN,Bank4 STA Off Enable" "0,1"
newline
bitfld.long 0x0 7. "RESERVED4,Reserved 4" "0,1"
newline
bitfld.long 0x0 6. "BANK3_STA_OFF_EN,Bank3 STA Off Enable" "0,1"
newline
bitfld.long 0x0 5. "RESERVED5,Reserved 5" "0,1"
newline
bitfld.long 0x0 4. "BANK2_STA_OFF_EN,Bank2 STA Off Enable" "0,1"
newline
bitfld.long 0x0 3. "RESERVED6,Reserved 6" "0,1"
newline
bitfld.long 0x0 2. "BANK1_STA_OFF_EN,Bank1 STA Off Enable" "0,1"
newline
bitfld.long 0x0 1. "RESERVED7,Reserved 7" "0,1"
newline
bitfld.long 0x0 0. "BANK0_STA_OFF_EN,Bank0 STA Off Enable" "0,1"
rgroup.long 0x3AC++0x3
line.long 0x0 "LMU_CPU2_STA_STATUS1,LMU CPU2 STA Status 1"
bitfld.long 0x0 29.--31. "BANK7_FSM_ST,Bank7 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK7_FSM_ST_REP_DONE,Bank7 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK6_FSM_ST,Bank6 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK6_FSM_ST_REP_DONE,Bank6 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK5_FSM_ST,Bank5 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK5_FSM_ST_REP_DONE,Bank5 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK4_FSM_ST,Bank4 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK4_FSM_ST_REP_DONE,Bank4 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK3_FSM_ST_REP_DONE,Bank3 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK2_FSM_ST,Bank2FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK2_FSM_ST_REP_DONE,Bank2 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK1_FSM_ST_REP_DONE,Bank1 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK0_FSM_ST_REP_DONE,Bank0 FSM St Rep Done" "0,1"
group.long 0x3B0++0x3
line.long 0x0 "LMU_CPU3_STA_CFG,LMU CPU3 STA Configuration"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED0,Reserved 0"
newline
bitfld.long 0x0 14. "BANK7_STA_OFF_EN,Bank7 STA Off Enable" "0,1"
newline
bitfld.long 0x0 13. "RESERVED1,Reserved 1" "0,1"
newline
bitfld.long 0x0 12. "BANK6_STA_OFF_EN,Bank6 STA Off Enable" "0,1"
newline
bitfld.long 0x0 11. "RESERVED2,Reserved 2" "0,1"
newline
bitfld.long 0x0 10. "BANK5_STA_OFF_EN,Bank5 STA Off Enable" "0,1"
newline
bitfld.long 0x0 9. "RESERVED3,Reserved 3" "0,1"
newline
bitfld.long 0x0 8. "BANK4_STA_OFF_EN,Bank4 STA Off Enable" "0,1"
newline
bitfld.long 0x0 7. "RESERVED4,Reserved 4" "0,1"
newline
bitfld.long 0x0 6. "BANK3_STA_OFF_EN,Bank3 STA Off Enable" "0,1"
newline
bitfld.long 0x0 5. "RESERVED5,Reserved 5" "0,1"
newline
bitfld.long 0x0 4. "BANK2_STA_OFF_EN,Bank2 STA Off Enable" "0,1"
newline
bitfld.long 0x0 3. "RESERVED6,Reserved 6" "0,1"
newline
bitfld.long 0x0 2. "BANK1_STA_OFF_EN,Bank1 STA Off Enable" "0,1"
newline
bitfld.long 0x0 1. "RESERVED7,Reserved 7" "0,1"
newline
bitfld.long 0x0 0. "BANK0_STA_OFF_EN,Bank0 STA Off Enable" "0,1"
rgroup.long 0x3B4++0x3
line.long 0x0 "LMU_CPU3_STA_STATUS1,LMU CPU3 STA Status 1"
bitfld.long 0x0 29.--31. "BANK7_FSM_ST,Bank7 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK7_FSM_ST_REP_DONE,Bank7 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK6_FSM_ST,Bank6 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK6_FSM_ST_REP_DONE,Bank6 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK5_FSM_ST,Bank5 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK5_FSM_ST_REP_DONE,Bank5 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK4_FSM_ST,Bank4 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK4_FSM_ST_REP_DONE,Bank4 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK3_FSM_ST,Bank3 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK3_FSM_ST_REP_DONE,Bank3 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK2_FSM_ST,Bank2FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK2_FSM_ST_REP_DONE,Bank2 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK1_FSM_ST,Bank1 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK1_FSM_ST_REP_DONE,Bank1 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK0_FSM_ST,Bank0 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK0_FSM_ST_REP_DONE,Bank0 FSM St Rep Done" "0,1"
group.long 0x3B8++0x3
line.long 0x0 "LMU_G2BIST_CTRL,LMU G2BIST Control"
bitfld.long 0x0 30. "DISABLE_DYN_REPAIR,1= disable dynamic memory repair" "?,1: disable dynamic memory repair"
newline
bitfld.long 0x0 29. "DISABLE_STA_REPAIR,1= disable static memory repair" "?,1: disable static memory repair"
newline
hexmask.long.byte 0x0 0.--4. 1. "LMU_G2BIST_MODE,1 = fuse load mode default mode when powered up. All repairable memories will be repaired by g2bist engine"
rgroup.long 0x3BC++0x3
line.long 0x0 "LMU_STATUS,LMU Status"
bitfld.long 0x0 20. "LMU_G2BIST_START,LMU_g to BIST Start" "0,1"
newline
hexmask.long.byte 0x0 12.--19. 1. "LMU_G2BIST_PWRDMN_RPR_REQ,LMU_g to BIST Powerdown RPR Request"
newline
hexmask.long.byte 0x0 8.--11. 1. "LMU_G2BIST_MODE,LMU_g to BIST Mode"
newline
hexmask.long.byte 0x0 4.--7. 1. "NXT_ST,NXT St"
newline
hexmask.long.byte 0x0 0.--3. 1. "REPAIR_FSM_ST,Repair FSM St"
group.long 0x3C0++0x3
line.long 0x0 "LMU_STA_CFG_MASK,LMU STA Configuration Mask"
hexmask.long.byte 0x0 0.--7. 1. "STA_CFG_MASK,STA Configuration Mask"
rgroup.long 0x3C4++0x7
line.long 0x0 "LMU_CPU2_STA_STATUS2,LMU CPU2 STA Status 2"
bitfld.long 0x0 29.--31. "BANK15_FSM_ST,Bank15 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "BANK15_FSM_ST_REP_DONE,Bank15 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 25.--27. "BANK14_FSM_ST,Bank14 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "BANK14_FSM_ST_REP_DONE,Bank14 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 21.--23. "BANK13_FSM_ST,Bank13 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "BANK13_FSM_ST_REP_DONE,Bank13 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 17.--19. "BANK12_FSM_ST,Bank12 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "BANK12_FSM_ST_REP_DONE,Bank12 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 13.--15. "BANK11_FSM_ST,Bank11 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "BANK11_FSM_ST_REP_DONE,Bank11 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 9.--11. "BANK10_FSM_ST,Bank10 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "BANK10_FSM_ST_REP_DONE,Bank10 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 5.--7. "BANK9_FSM_ST,Bank9 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "BANK9_FSM_ST_REP_DONE,Bank9 FSM St Rep Done" "0,1"
newline
bitfld.long 0x0 1.--3. "BANK8_FSM_ST,Bank8 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "BANK8_FSM_ST_REP_DONE,Bank8 FSM St Rep Done" "0,1"
line.long 0x4 "LMU_CPU3_STA_STATUS2,LMU CPU3 STA Status 2"
bitfld.long 0x4 29.--31. "BANK15_FSM_ST,Bank15 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 28. "BANK15_FSM_ST_REP_DONE,Bank15 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 25.--27. "BANK14_FSM_ST,Bank14 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "BANK14_FSM_ST_REP_DONE,Bank14 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 21.--23. "BANK13_FSM_ST,Bank13 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "BANK13_FSM_ST_REP_DONE,Bank13 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 17.--19. "BANK12_FSM_ST,Bank12 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "BANK12_FSM_ST_REP_DONE,Bank12 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 13.--15. "BANK11_FSM_ST,Bank11 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "BANK11_FSM_ST_REP_DONE,Bank11 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 9.--11. "BANK10_FSM_ST,Bank10 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 8. "BANK10_FSM_ST_REP_DONE,Bank10 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 5.--7. "BANK9_FSM_ST,Bank9 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "BANK9_FSM_ST_REP_DONE,Bank9 FSM St Rep Done" "0,1"
newline
bitfld.long 0x4 1.--3. "BANK8_FSM_ST,Bank8 FSM St" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "BANK8_FSM_ST_REP_DONE,Bank8 FSM St Rep Done" "0,1"
group.long 0x3D0++0x2F
line.long 0x0 "CPU3_HOST_WKUP_MASK,CPU3 Host Wakeup Mask"
hexmask.long.word 0x0 0.--15. 1. "HOST_WKUP_MASK,Host Wakeup Mask"
line.long 0x4 "CPU3_HOST_WKUP_POL,CPU3 Host Wakeup Polarity"
hexmask.long.word 0x4 0.--15. 1. "HOST_WKUP_POL,Host Wakeup Polarity"
line.long 0x8 "CPU3_HOST_WKUP_CTRL,CPU3 Host Wakeup Control"
hexmask.long.word 0x8 16.--31. 1. "HOST_INTR_MASK,Host Interrupt Mask"
newline
hexmask.long.word 0x8 0.--15. 1. "HOST_WKUP_CTRL,Host Wakeup Control"
line.long 0xC "CPU3_CTRL,CPU3 Control"
bitfld.long 0xC 16.--18. "APU_SUBSYS3_HOST,APU Subsystem 2 Host" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 5. "GENERIC_TIMER_EN2,Generic Timer Enable 2" "0,1"
newline
bitfld.long 0xC 4. "SOC_USE_REF_ONLY,SoC Use Ref Only" "0,1"
newline
bitfld.long 0xC 3. "CPU3_CP15_SLP_BYPASS_EN,CPU3 CP15 Sleep Bypass Enable" "0,1"
newline
bitfld.long 0xC 2. "CPU3_CP15_SLP_BYPASS_VAL,CPU3 CP15 Sleep Bypass Value" "0,1"
newline
bitfld.long 0xC 0. "CPU3_MSG_RDY_MASK,CPU3 Message Ready Mask" "0,1"
line.long 0x10 "CPU3_DVFS_CTRL,CPU3 DVFS Control"
hexmask.long.byte 0x10 25.--31. 1. "UART_VOL_VAL,UART Vol Value"
newline
bitfld.long 0x10 24. "CPU3_AHB1_INDEX_SEL_METHOD,CPU3 AHB1 index select method" "0,1"
newline
hexmask.long.byte 0x10 20.--23. 1. "CPU3_INACTIVE_AHB1_INDEX,CPU3 Inactive AHB1 Index"
newline
hexmask.long.byte 0x10 16.--19. 1. "CPU3_ACTIVE_AHB1_INDEX,CPU3 Active AHB1 Index"
newline
hexmask.long.byte 0x10 12.--15. 1. "CPU3_INACTIVE_SYS_INDEX,CPU3 Inactive System Index"
newline
hexmask.long.byte 0x10 8.--11. 1. "CPU3_ACTIVE_SYS_INDEX,CPU3 Active System Index"
newline
hexmask.long.byte 0x10 4.--7. 1. "CPU3_INACTIVE_INDEX,CPU3 Inactive Index"
newline
hexmask.long.byte 0x10 0.--3. 1. "CPU3_ACTIVE_INDEX,CPU3 Active Index"
line.long 0x14 "CPU3_FREQ_REG1,CPU3 Frequency 1"
hexmask.long 0x14 0.--31. 1. "CPU3_FREQ_REG1,CPU3 Frequency 1"
line.long 0x18 "CPU3_FREQ_REG2,CPU3 Frequency 2"
hexmask.long 0x18 0.--31. 1. "CPU3_FREQ_REG2,CPU3Frequency 2"
line.long 0x1C "CPU3_PLL_EN_REG,CPU3 PLL Enable"
hexmask.long 0x1C 0.--31. 1. "CPU3_PLL_EN_REG,CPU3 PLL Enable"
line.long 0x20 "CPU3_VOL_REG1,CPU3 Voltage 1"
hexmask.long 0x20 0.--31. 1. "CPU3_VOL_REG1,CPU3 Voltage 1"
line.long 0x24 "CPU3_VOL_REG2,CPU3 Voltage 2"
hexmask.long 0x24 0.--31. 1. "CPU3_VOL_REG2,CPU3 Voltage 2"
line.long 0x28 "CPU3_VOL_REG3,CPU3 Voltage 3"
hexmask.long 0x28 0.--31. 1. "CPU3_VOL_REG3,CPU3 Voltage 3"
line.long 0x2C "CPU3_VOL_REG4,CPU3 Voltage 4"
hexmask.long 0x2C 0.--31. 1. "CPU3_VOL_REG4,CPU3 Voltage 4"
tree.end
tree.end
tree "BG"
base ad:0x40038700
group.long 0x0++0x3
line.long 0x0 "CTRL,Control Register"
hexmask.long.byte 0x0 4.--7. 1. "RES_TRIM,1.2V voltage reference resistor trim."
bitfld.long 0x0 0. "PD,Bandgap power down." "0: Power up,1: Power down"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Status Register"
bitfld.long 0x0 0. "RDY,1'b1 indicates BG ready flag." "0,1"
tree.end
tree "BLE (Bluetooth Low Energy)"
base ad:0x0
tree "BLEAPU"
base ad:0x44258000
group.long 0x8++0x7
line.long 0x0 "SOCBTAPU_APU_BYPASS0,APU Bypass0"
bitfld.long 0x0 31. "RFU_PA_PE_G_BYPASS_VAL,RFU PA_PE_G Bypass Value" "0,1"
newline
bitfld.long 0x0 30. "RFU_PA_PE_A_BYPASS_VAL,RFU PA_PE_A Bypass Value" "0,1"
newline
bitfld.long 0x0 29. "RFU_PE2_BYPASS_VAL,RFU PE2 Bypass Value" "0,1"
newline
bitfld.long 0x0 28. "RFU_PE1_BYPASS_VAL,RFU PE1 Bypass Value" "0,1"
newline
bitfld.long 0x0 27. "RX_PE_BYPASS_VAL,Rx_Pe Bypass Value" "0,1"
newline
bitfld.long 0x0 26. "TX_PE_BYPASS_VAL,Tx_Pe Bypass Value" "0,1"
newline
bitfld.long 0x0 23. "TBG_MAC2_CLK_EN_BYPASS_VAL,TBG512_320_176_MAC2_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 22. "TBG_BBU2_CLK_EN_BYPASS_VAL,TBG512_320_176_BBU2_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 21. "TBG_SOC_CLK_EN_BYPASS_VAL,TBG512_320_176_SoC_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 20. "TBG_MAC1_CLK_EN_BYPASS_VAL,TBG512_320_176_MAC1_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 19. "TBG_T2_PDB_BYPASS_VAL,TBF176_Pdb Bypass Value" "0,1"
newline
bitfld.long 0x0 18. "TBG_BBU1_CLK_EN_BYPASS_VAL,TBG512_320_176_BBU1_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 17. "TBG_TCPU_PDB_BYPASS_VAL,TCPU_Pdb Bypass Value" "0,1"
newline
bitfld.long 0x0 16. "C2P_XOSC_EN_BYPASS_VAL,C2p_Xosc_En Bypass Value" "0,1"
newline
bitfld.long 0x0 15. "RFU_PA_PE_G_BYPASS_EN,RFU_PA_PE_G_Bypass Enable" "0,1"
newline
bitfld.long 0x0 14. "RFU_PA_PE_A_BYPASS_EN,RFU_PA_PE_A_Bypass Enable" "0,1"
newline
bitfld.long 0x0 13. "RFU_PE2_BYPASS_EN,RFU_PE2_Bypass Enable" "0,1"
newline
bitfld.long 0x0 12. "RFU_PE1_BYPASS_EN,RFU_PE1_Bypass Enable" "0,1"
newline
bitfld.long 0x0 11. "RX_PE_BYPASS_EN,BBU_Rx_Pe_Bypass Enable" "0,1"
newline
bitfld.long 0x0 10. "TX_PE_BYPASS_EN,BBU_Rx_Pe_Bypass Enable" "0,1"
newline
bitfld.long 0x0 7. "TBG_MAC2_CLK_EN_BYPASS_EN,TBG512_320_176_MAC2_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 6. "TBG_BBU2_CLK_EN_BYPASS_EN,TBG512_320_176_BBU2_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 5. "TBG_SOC_CLK_EN_BYPASS_EN,TBG512_320_176_SoC_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 4. "TBG_MAC1_CLK_EN_BYPASS_EN,TBG512_320_176_MAC1_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 3. "TBG_T2_PDB_BYPASS_EN,tbg t2_Pdb_Bypass" "0,1"
newline
bitfld.long 0x0 2. "TBG_BBU1_CLK_EN_BYPASS_EN,TBG512_320_176_BBU1_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 1. "TBG_TCPU_PDB_BYPASS_EN,TCPU_Pdb_Bypass" "0,1"
newline
bitfld.long 0x0 0. "C2P_XOSC_EN_BYPASS_EN,C2p_Xosc_En_Bypass" "0,1"
line.long 0x4 "SOCBTAPU_APU_PWR_CTRL_BYPASS0,APU power control Bypass Register 0"
bitfld.long 0x4 9. "SOC_NON_UDR_RST_BYPASS_EN,Firmware Bypass SoC non udr rst from APU (used for brf sif only in KF2)" "0,1"
newline
bitfld.long 0x4 8. "SOC_NON_UDR_RST_BYPASS_VAL,Firmware Bypass Value for SoC non udr rst (active low signal)" "0,1"
newline
bitfld.long 0x4 7. "SOC_CLK_DIV_RSTB_BYPASS_EN,Firmware Bypass SoC Clk_Div_Rstb from APU" "0,1"
newline
bitfld.long 0x4 6. "SOC_CLK_DIV_RSTB_BYPASS_VAL,Firmware Bypass Value for SoC Dlk_Div_Rstb (active low signal)" "0,1"
newline
bitfld.long 0x4 5. "SOC_ISO_EN_BYPASS_EN,SoC Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0x4 4. "SOC_ISO_EN_BYPASS_VAL,SoC Isolation Cell Control" "0,1"
newline
bitfld.long 0x4 3. "SOC_FWBAR_BYPASS_EN,SoC Firewallbar Control Enable" "0,1"
newline
bitfld.long 0x4 2. "SOC_FWBAR_BYPASS_VAL,SoC Firewallbar Control" "0,1"
newline
bitfld.long 0x4 1. "SOC_PSW_BYPASS_EN,SoC Power Switch Control Enable" "0,1"
newline
bitfld.long 0x4 0. "SOC_PSW_BYPASS_VAL,SoC Power Switch Control" "0,1"
group.long 0x1C++0xF
line.long 0x0 "SOCBTAPU_APU_BYPASS1,APU Bypass Register 1"
bitfld.long 0x0 27. "SLNA_CLK_EN_BYPASS_VAL,Firmware Bypass Value for SLNA_Clk_En (active high signal)" "0,1"
newline
bitfld.long 0x0 26. "SLNA_CLK_EN_BYPASS_EN,Firmware Bypass for SLNA_Clk_En" "0,1"
newline
bitfld.long 0x0 19. "BCA_CLK_EN_BYPASS_VAL,Firmware Bypass Value for BCA_Clk_En (active high signal)" "0,1"
newline
bitfld.long 0x0 18. "BCA_CLK_EN_BYPASS_EN,Firmware Bypass BCA_Clk_En" "0,1"
newline
bitfld.long 0x0 10. "PLL_OVERRIDE_BYPASS,PLL Override Bypass" "0,1"
newline
bitfld.long 0x0 9. "PE1_DYN_BYPASS,PE1_Dyn_Bypass" "0,1"
newline
bitfld.long 0x0 8. "RXPE_DYN_BYPASS,Rxpe_Dyn_Bypass" "0,1"
newline
bitfld.long 0x0 7. "SOC_CAU_XOSC_EN_BP_VAL,Firmware Bypass Xosc_En Value for SoC_CAU_Xosc_En_Bp_En" "0,1"
newline
bitfld.long 0x0 6. "SOC_CAU_XOSC_EN_BP_EN,Firmware Bypass Xosc_En to CAU and other parts of the chip including pads" "0,1"
line.long 0x4 "SOCBTAPU_APU_BYPASS2,APU Bypass Register 2"
bitfld.long 0x4 28.--29. "PMIC_DVSC_CTRL_BYPASS_VAL,Firmware Bypass value for pmic dvsc ctrl from APU (default high power WLAN ode)" "0,1,2,3"
newline
bitfld.long 0x4 27. "PMIC_DVSC_CTRL_BYPASS_EN,Firmware Bypass enable for pmic dvsc ctrl from APU" "0,1"
newline
bitfld.long 0x4 26. "TBG_T1_STABLE_BYPASS_VAL,Firmware Bypass value for T1 pll_stable signal from APU" "0,1"
newline
bitfld.long 0x4 25. "TBG_T1_STABLE_BYPASS_EN,Firmware Bypass enable for T1 pll_stable signal from APU" "0,1"
newline
bitfld.long 0x4 13. "T3_PI2_PDB_BYPASS_VAL,Firmware Bypass Value for TBG256 aiu_pi2" "0,1"
newline
bitfld.long 0x4 12. "T3_PI2_PDB_BYPASS_EN,Firmware Bypass for TBG256 aiu_pi2" "0,1"
newline
bitfld.long 0x4 11. "T3_PI1_PDB_BYPASS_VAL,Firmware Bypass Value for TBG256 aiu pi1" "0,1"
newline
bitfld.long 0x4 10. "T3_PI1_PDB_BYPASS_EN,Firmware Bypass for TBG256 aiu_pi1" "0,1"
newline
bitfld.long 0x4 9. "TBG_T3_PDB_BYPASS_VAL,T3_Pdb Bypass Value" "0,1"
newline
bitfld.long 0x4 8. "TBG_T3_PDB_BYPASS_EN,Firmware Bypass for T3_pdb pll" "0,1"
line.long 0x8 "SOCBTAPU_APU_BYPASS3,APU Bypass Register 3"
bitfld.long 0x8 17. "SLNA_BBUD_BRF_BYPASS_VAL,Firmware Bypass Value for apu mux control of SLNA gain from bbud/brf" "0,1"
newline
bitfld.long 0x8 16. "SLNA_BBUD_BRF_BYPASS_EN,Firmware Bypass for apu mux control of SLNA gain from bbud/brf" "0,1"
newline
bitfld.long 0x8 15. "SPSRAM_RST_BYPASS_VAL,Firmware Bypass Value for single power sram reset(active low signal)" "0,1"
newline
bitfld.long 0x8 14. "SPSRAM_RST_BYPASS_EN,Firmware Bypass for Single power SRAM reset enable" "0,1"
newline
bitfld.long 0x8 5. "SYS_CLK_EN_BYPASS_VAL,Firmware Bypass Value for sys clock domain clock enable(active high signal)" "0,1"
newline
bitfld.long 0x8 4. "SYS_CLK_EN_BYPASS_EN,Firmware Bypass for sys clock domain clock enable" "0,1"
line.long 0xC "SOCBTAPU_APU_CTRL,APU Control"
bitfld.long 0xC 20. "FORCE_BTU2_WAKEUP,Force BTU2 Wakeup" "0,1"
newline
bitfld.long 0xC 19. "APU_HOST_WKUP_CPU3,APU Wakeup triggered by CPU3" "0,1"
newline
bitfld.long 0xC 18. "APU_HOST_WKUP_CPU1,APU Wakeup triggered by CPU1" "0,1"
newline
bitfld.long 0xC 17. "RFU_5G_SRAM_PD_METHOD_SEL,Choose apu signal to use for SRAM PD of RFU 5G memories" "0,1"
newline
bitfld.long 0xC 16. "SOC_PA_PE_EN_MAC2,PA_PE control from MAC2 to RFU SoC_PA_PE Input" "0,1"
newline
bitfld.long 0xC 15. "LMU_BYPASS,LMU global bypass bit" "0,1"
newline
bitfld.long 0xC 13. "BRF_SRAM_PD_METHOD_SEL,Choose apu signal to use for SRAM PD of BRF memories" "0,1"
newline
bitfld.long 0xC 12. "RFU_2G_SRAM_PD_METHOD_SEL,Choose apu signal to use for SRAM PD of RFU 2G memories" "0,1"
newline
bitfld.long 0xC 11. "SOC_PA_PE_G_EN,PA_PE_G control from SoC to Pad" "0,1"
newline
bitfld.long 0xC 10. "SOC_PA_PE_A_EN,PA_PE_A control from SoC to Pad" "0,1"
newline
bitfld.long 0xC 9. "SOC_PA_PE_EN,PA_PE control from SoC to RFU SoC_PA_PE Input" "0,1"
newline
bitfld.long 0xC 8. "BRF_INT_WAKEUP,APU Wakeup" "0,1"
newline
bitfld.long 0xC 7. "APU_HOST_WKUP,APU Wakeup triggered by CPU2" "0,1"
newline
bitfld.long 0xC 6. "ISU_WKUP_IN_USE,APU Wakeup" "0,1"
newline
bitfld.long 0xC 4. "FORCE_BTU_WAKEUP,Force BTU Wakeup" "0,1"
newline
hexmask.long.byte 0xC 0.--3. 1. "APU_REFCLK_DIV_SEL,APU Reference Clock Divider Select"
rgroup.long 0x2C++0x3
line.long 0x0 "SOCBTAPU_APU_STATUS,APU Status Register"
bitfld.long 0x0 3. "SOC_CLK_TBG_SEL,Monitor SoC_Clk_TBG_Sel" "0,1"
newline
bitfld.long 0x0 2. "SOC_CLK_T3_REF_SEL,Monitor SoC_Clk_T3_Ref_Sel" "0,1"
newline
bitfld.long 0x0 1. "BTU_CLK_TBG_SEL,Monitor BTU_Clk_TBG_Sel" "0,1"
newline
bitfld.long 0x0 0. "BRF_CLK_TBG_SEL,Monitor BRF_Clk_TBG_Sel" "0,1"
group.long 0x30++0x13
line.long 0x0 "SOCBTAPU_CPU1_LMU_STA_BYPASS0,LMU static bank control byapss0 Register"
hexmask.long.byte 0x0 24.--31. 1. "LMU_STA_BANKS_PSW_EN_BP_VAL,Firmware Bypass value for lmu static banks psw_en"
newline
hexmask.long.byte 0x0 16.--23. 1. "LMU_STA_BANKS_PSW_EN_BP_EN,Firmware Bypass enable for lmu static banks psw_en"
newline
hexmask.long.byte 0x0 8.--15. 1. "LMU_STA_BANKS_ISO_EN_BP_VAL,Firmware Bypass value for lmu static banks iso_en"
newline
hexmask.long.byte 0x0 0.--7. 1. "LMU_STA_BANKS_ISO_EN_BP_EN,Firmware Bypass enable for lmu static banks iso_en"
line.long 0x4 "SOCBTAPU_CPU1_LMU_STA_BYPASS1,LMU static bank control byapss1 Register"
hexmask.long.byte 0x4 24.--31. 1. "LMU_STA_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu static banks fnrst"
newline
hexmask.long.byte 0x4 16.--23. 1. "LMU_STA_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu static banks fnrst"
newline
hexmask.long.byte 0x4 8.--15. 1. "LMU_STA_BANKS_SRAM_PD_BP_VAL,Firmware Bypass value for lmu static banks sram_pd"
newline
hexmask.long.byte 0x4 0.--7. 1. "LMU_STA_BANKS_SRAM_PD_BP_EN,Firmware Bypass enable for lmu static banks sram_pd"
line.long 0x8 "SOCBTAPU_CPU1_LMU_STA_BYPASS2,LMU static bank byapss2 Register"
hexmask.long.byte 0x8 8.--15. 1. "LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl"
newline
hexmask.long.byte 0x8 0.--7. 1. "LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl"
line.long 0xC "SOCBTAPU_LMU_DYN_BYPASS0,LMU dynamic bank control byapss0 Register"
bitfld.long 0xC 31. "LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST,1: By default WLAN_SRAM_FNRST is used for SMU off domain banks" "?,1: By default WLAN_SRAM_FNRST is used for SMU off.."
newline
bitfld.long 0xC 24.--26. "LMU_DYN_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu dynamic banks fnrst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 16.--18. "LMU_DYN_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu dynamic banks fnrst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 8.--10. "LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu dynamic banks vddmc_sw_pd_ctrl" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0.--2. "LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu dynamic banks vddmc_sw_pd_ctrl" "0,1,2,3,4,5,6,7"
line.long 0x10 "SOCBTAPU_LMU_G2BIST_CTRL_BYPASS,LMU G2Bist control bypass Register"
hexmask.long.byte 0x10 28.--31. 1. "G2BIST_STATUS,g2bist status"
newline
bitfld.long 0x10 27. "LMU_G2BIST_CLK_EN_BP_VAL,Firmware Bypass value for lmu g2bist clock en" "0,1"
newline
bitfld.long 0x10 26. "LMU_G2BIST_CLK_EN_BP_EN,Firmware Bypass enable for lmu g2bist clock en" "0,1"
newline
bitfld.long 0x10 25. "LMU_G2BIST_START_BP_VAL,Firmware Bypass value for lmu g2bist start" "0,1"
newline
bitfld.long 0x10 24. "LMU_G2BIST_START_BP_EN,Firmware Bypass enable for lmu g2bist start" "0,1"
newline
hexmask.long.byte 0x10 1.--5. 1. "LMU_G2BIST_MODE_BYPASS_VAL,Firmware Bypass value for lmu g2bist mode"
newline
bitfld.long 0x10 0. "LMU_G2BIST_MODE_BYPASS_EN,Firmware Bypass enable for lmu g2bist mode" "0,1"
group.long 0x50++0x3
line.long 0x0 "SOCBTAPU_CPU1_LMU_G2BIST_CTRL_BYPASS,LMU G2Bist control bypass Register for CPU1"
hexmask.long.byte 0x0 24.--27. 1. "LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL,Firmware Bypass value for SMU1 dynamic banks lmu powerdomain repair request"
newline
bitfld.long 0x0 20. "LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN,Firmware Bypass enable for SMU1 dynamic banks lmu powerdomain repair request" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL,Firmware Bypass value for CPU1 static banks lmu powerdomain repair request"
newline
bitfld.long 0x0 0. "LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN,Firmware Bypass enable for CPU1 static banks lmu powerdomain repair request" "0,1"
group.long 0x5C++0x3
line.long 0x0 "SOCBTAPU_APU_PWR_CTRL_BYPASS5,'"
bitfld.long 0x0 13. "CPU1_VINITHI_BYPASS_EN,Firmware Bypass enable for CPU1 Vinithi" "0,1"
newline
bitfld.long 0x0 12. "CPU1_VINITHI_BYPASS_VAL,Firmware Bypass Value for CPU1 Vinithi (default boot from ROM)" "0,1"
group.long 0x68++0xB
line.long 0x0 "SOCBTAPU_SMU1_HYBRID_LMU_BYPASS0,LMU static bank control byapss0 Register for smu1 hybrid banks mem"
hexmask.long.byte 0x0 24.--31. 1. "LMU_HYBRID_BANKS_PSW_EN_BP_VAL,Firmware Bypass value for lmu static banks psw_en"
newline
hexmask.long.byte 0x0 16.--23. 1. "LMU_HYBRID_BANKS_PSW_EN_BP_EN,Firmware Bypass enable for lmu static banks psw_en"
newline
hexmask.long.byte 0x0 8.--15. 1. "LMU_HYBRID_BANKS_ISO_EN_BP_VAL,Firmware Bypass value for lmu static banks iso_en"
newline
hexmask.long.byte 0x0 0.--7. 1. "LMU_HYBRID_BANKS_ISO_EN_BP_EN,Firmware Bypass enable for lmu static banks iso_en"
line.long 0x4 "SOCBTAPU_SMU1_HYBRID_LMU_BYPASS1,LMU static bank control byapss1 Register for smu1 hybrid banks mem"
hexmask.long.byte 0x4 24.--31. 1. "LMU_HYBRID_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu static banks fnrst"
newline
hexmask.long.byte 0x4 16.--23. 1. "LMU_HYBRID_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu static banks fnrst"
newline
hexmask.long.byte 0x4 8.--15. 1. "LMU_HYBRID_BANKS_SRAM_PD_BP_VAL,Firmware Bypass value for lmu static banks sram_pd"
newline
hexmask.long.byte 0x4 0.--7. 1. "LMU_HYBRID_BANKS_SRAM_PD_BP_EN,Firmware Bypass enable for lmu static banks sram_pd"
line.long 0x8 "SOCBTAPU_SMU1_HYBRID_LMU_BYPASS2,LMU static bank control byapss2 Register for smu1 hybrid banks mem"
hexmask.long.byte 0x8 8.--15. 1. "LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl"
newline
hexmask.long.byte 0x8 0.--7. 1. "LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl"
group.long 0x7C++0x23
line.long 0x0 "SOCBTAPU_APU_ECO_CTRL,APU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "SOCBTAPU_GPIO_WKUP_CTRL0,'"
hexmask.long 0x4 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [0]"
line.long 0x8 "SOCBTAPU_GPIO_WKUP_CTRL1,'"
hexmask.long 0x8 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [4]"
line.long 0xC "SOCBTAPU_GPIO_WKUP_CTRL2,'"
hexmask.long 0xC 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [8]"
line.long 0x10 "SOCBTAPU_GPIO_WKUP_CTRL3,'"
hexmask.long 0x10 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [12]"
line.long 0x14 "SOCBTAPU_HOST_WKUP_MODE,'"
hexmask.long.word 0x14 0.--15. 1. "GPIO_SEL,GPIO select"
line.long 0x18 "SOCBTAPU_T3_CLK_DIV_EN_BYPASS,'"
bitfld.long 0x18 19. "TCPU_CPU_CLK_DIV_EN_BYPASS_VAL,bypass value for tcpu cpu_clk_en" "0,1"
newline
bitfld.long 0x18 18. "TCPU_CPU_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 17. "T3_BBUD_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 16. "T3_BBUD_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 15. "T3_MAC2_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 14. "T3_MAC2_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 13. "T3_MAC1_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 12. "T3_MAC1_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 11. "T3_213P3_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 10. "T3_213P3_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 9. "T3_SOC_512_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 8. "T3_SOC_512_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 7. "T3_SOC_426_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 6. "T3_SOC_426_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 5. "T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 4. "T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 3. "T3_SOC_320_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 2. "T3_SOC_320_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 1. "T3_SOC_256_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 0. "T3_SOC_256_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
line.long 0x1C "SOCBTAPU_LDO_LV_CTRL2,LV LDO Control 2"
bitfld.long 0x1C 5. "LDO_GLU_XOSC_BYPASS_EN,XOSC_EN control bypass for ldo control logic" "0,1"
newline
bitfld.long 0x1C 4. "LDO_GLU_XOSC_VAL,XOSC_EN value for ldo control logic set by FW" "0,1"
line.long 0x20 "SOCBTAPU_CAU_BYPASS,CAU Bypass"
bitfld.long 0x20 7. "BRF_CLK_BYPASS_EN,bypass enable for brf clk" "0,1"
newline
bitfld.long 0x20 6. "BRF_CLK_BYPASS_VAL,bypass value for brf clk" "0,1"
newline
bitfld.long 0x20 3. "BT_CLK_BYPASS_EN,bypass enable for bt clk enable" "0,1"
newline
bitfld.long 0x20 2. "BT_CLK_BYPASS_VAL,bypass value for bt clk enable" "0,1"
newline
bitfld.long 0x20 1. "PHY_REF_CLK_BYPASS_EN,bypass enable for phy ref clk enable" "0,1"
newline
bitfld.long 0x20 0. "PHY_REF_CLK_BYPASS_VAL,bypass value for phy ref clk enable" "0,1"
group.long 0xA4++0x3
line.long 0x0 "SOCBTAPU_MEM_PWDN2,Memory Powerdown Control"
bitfld.long 0x0 17. "OTP_BYPASS_EN,Firmware Bypass Enable for OTP Power Down" "0,1"
newline
bitfld.long 0x0 1. "OTP_BYPASS_VAL,Firmware Bypass Value for OTP Power Down" "0,1"
group.long 0xB0++0x3
line.long 0x0 "SOCBTAPU_HOST_WKUP_SOURCE,Host Wakeup Source Control"
hexmask.long.word 0x0 0.--15. 1. "ENABLE,Enable/ disable value:"
tree.end
tree "BLECTRL"
base ad:0x44240000
group.long 0x0++0x43
line.long 0x0 "CIU2_CLK_ENABLE,Clock enable"
bitfld.long 0x0 31. "SOC_AHB_CLK_SEL,Clock selection for soc_ahb_clk. 0: AHB2_CLK 1: CPU1_CLK_DIV" "0: AHB2_CLK,1: CPU1_CLK_DIV"
newline
bitfld.long 0x0 30. "CPU1_DIV_CLK_ENABLE,Clock cpu1_div_clk enable signal. cpu1_div_clk enable. 1: enable 0: disable" "0: disable,1: enable"
newline
bitfld.long 0x0 29. "AHB2_CLK_ENABLE,Clock ahb2_clk enable signal. Ahb2_clk enable. 1: enable 0: disable" "0: disable,1: enable"
newline
bitfld.long 0x0 28. "CIU_BTAPU_REF_CLK_EN,APU Reference Clock Enable" "0,1"
newline
bitfld.long 0x0 27. "CIU_BTAPU_CAL_CLK_EN,APU Calibration Clock Enable" "0,1"
newline
bitfld.long 0x0 26. "CIU_BTAPU_SLPCLK_EN,APU Sleep Clock Enable" "0,1"
newline
bitfld.long 0x0 25. "CIU_BTAPU_AHB_CLK_EN,APU AHB Clock Enable" "0,1"
newline
bitfld.long 0x0 24. "CIU_BTAPU_DVFS_CLK_EN,APU DVFS Clock Enable" "0,1"
newline
bitfld.long 0x0 23. "CIU_MSC_A2A_CLK_EN,Enable AHB2 Clock to A2A in MSC" "0,1"
newline
bitfld.long 0x0 22. "CIU_SOCCIU_A2A_CLK_EN,Enable AHB2 Clock to A2A in SOCCIU" "0,1"
newline
bitfld.long 0x0 21. "CIU2_FFU_OSC_CLK_EN,Enable FFU Oscillator Clock" "0,1"
newline
bitfld.long 0x0 20. "CIU2_FP4_SLP_CLK_EN,Enable FFU Sleep Clock" "0,1"
newline
bitfld.long 0x0 19. "CIU2_MCI_A2A_CLK_EN,Enable AHB2 Clock to A2A in MCI" "0,1"
newline
bitfld.long 0x0 18. "CIU2_AHB2APB_CLK_EN,Enable AHB2APB HCLK" "0,1"
line.long 0x4 "CIU2_ECO_0,ECO Register 0"
hexmask.long 0x4 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x8 "CIU2_ECO_1,ECO Register 1"
hexmask.long 0x8 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0xC "CIU2_ECO_2,ECO Register 2"
hexmask.long 0xC 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x10 "CIU2_ECO_3,ECO Register 3"
hexmask.long 0x10 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x14 "CIU2_ECO_4,ECO Register 4"
hexmask.long 0x14 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x18 "CIU2_ECO_5,ECO Register 5"
hexmask.long 0x18 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x1C "CIU2_ECO_6,ECO Register 6"
hexmask.long 0x1C 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x20 "CIU2_ECO_7,ECO Register 7"
hexmask.long 0x20 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x24 "CIU2_ECO_8,ECO Register 8"
hexmask.long 0x24 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x28 "CIU2_ECO_9,ECO Register 9"
hexmask.long 0x28 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x2C "CIU2_ECO_10,ECO Register 10"
hexmask.long 0x2C 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x30 "CIU2_ECO_11,ECO Register 11"
hexmask.long 0x30 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x34 "CIU2_ECO_12,ECO Register 12"
hexmask.long 0x34 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x38 "CIU2_ECO_13,ECO Register 13"
hexmask.long 0x38 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x3C "CIU2_ECO_14,ECO Register 14"
hexmask.long 0x3C 0.--31. 1. "SPARE,Eco Reserve Register"
line.long 0x40 "CIU2_ECO_15,ECO Register 15"
hexmask.long 0x40 0.--31. 1. "SPARE,Eco Reserve Register"
group.long 0x100++0x13
line.long 0x0 "CIU2_CLK_ENABLE4,Clock Enable 4"
bitfld.long 0x0 30. "BTRTU1_CLK_EN,BT RTU1 clock enable" "0,1"
newline
bitfld.long 0x0 29. "SIU_AHB2_CLK_EN,BT SIU (UART) AHB clock enable" "0,1"
newline
bitfld.long 0x0 24. "DBUS_CLK_EN,BLE DBUS Clock Enable" "0,1"
newline
bitfld.long 0x0 23. "BT_16M_CLK_EN,BT 16MHz Clock Enable" "0,1"
newline
bitfld.long 0x0 22. "BLE_AEU_CLK_EN,BT/BLE AEU Clock Enable" "0,1"
newline
bitfld.long 0x0 21. "BLE_SYS_CLK_EN,BLE SYS Clock Enable" "0,1"
newline
bitfld.long 0x0 20. "BLE_AHB_CLK_EN,BLE ARM Clock Enable" "0,1"
newline
bitfld.long 0x0 19. "HPU2_CIU_CLK_EN,HPU2 CIU Clock Enable" "0,1"
newline
bitfld.long 0x0 16. "SMU2_AHB_CLK_EN,SMU2 AHB Clock Enable" "0,1"
newline
bitfld.long 0x0 14. "SIU_CLK_EN,BT SIU (UART) clock enable" "0,1"
newline
bitfld.long 0x0 13. "BTU_AHB_CLK_EN,BTU AHB Clock Enable" "0,1"
newline
bitfld.long 0x0 10. "BT_4MCLK_EN,BTU 4 MHz Clock Enable" "0,1"
newline
bitfld.long 0x0 9. "BT_ECLK_EN,BTU EBC Clock Enable" "0,1"
newline
bitfld.long 0x0 8. "EBRAM_BIST_CLK_EN,EBRAM BIST Clock Enable" "0,1"
newline
bitfld.long 0x0 5. "SMU2_DYN_CLK_GATING_DIS,SMU2 Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0x0 4. "BRU_AHB2_DYN_CLK_GATING_DIS,CPU2 ROM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0x0 3. "DTCM_AHB2_DYN_CLK_GATING_DIS,CPU2 DTCM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0x0 2. "ITCM_AHB2_DYN_CLK_GATING_DIS,CPU2 ITCM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0x0 1. "BRU_AHB2_ADDR_MASK_DIS,CPU2 ROM Address Mask Selection" "0,1"
newline
bitfld.long 0x0 0. "BIST_AHB2_CLK_GATING_EN,CPU2 bist Clock for IMEM/DMEM/SMU2/EBRAM/ROM" "0,1"
line.long 0x4 "CIU2_CLK_ENABLE5,Clock Enable 5"
bitfld.long 0x4 31. "SIF_AHB2_CLK_EN,SIF ahb2 Clock Enable" "0,1"
newline
bitfld.long 0x4 30. "CPU2_MEM_SLV_CLK_EN,CPU2 Memory Slave Clock Control Feature" "0,1"
newline
bitfld.long 0x4 29. "CPU2_FABRIC_CLK_EN,CPU2 Fabric Clock Control Feature" "0,1"
newline
bitfld.long 0x4 28. "CPU2_GATEHCLK_EN,CPU2gate HCLK Feature" "0,1"
newline
bitfld.long 0x4 27. "SIF_CLK_SEL,SIF Clock Select" "0,1"
newline
bitfld.long 0x4 26. "BTRTU1_AHB_CLK_EN,SW enable for btrtu ahb clock" "0,1"
newline
bitfld.long 0x4 24.--25. "SMU2_BANK_CLK_EN,SMU2 bank Clock Enable" "0,1,2,3"
newline
bitfld.long 0x4 23. "BTU_MCLK_EN,BTU MCLK Enable" "0,1"
newline
hexmask.long.word 0x4 8.--22. 1. "BR_AHB2_CLK_EN,CPU2 BROM AHB Clock Enable"
newline
bitfld.long 0x4 7. "CIU2_REG_CLK_EN,CIU2 Reg Clock Enable" "0,1"
newline
bitfld.long 0x4 6. "CIU2_FFU_AHB_CLK_EN,Enable for AHB Clock to FFU" "0,1"
newline
bitfld.long 0x4 0.--2. "ITCM_AHB2_CLK_EN,Enable CPU2 ITCM Banks 1-2" "0,1,2,3,4,5,6,7"
line.long 0x8 "CIU2_CLK_CPU2CLK_CTRL,CPU2_AHB2 Clock Control"
hexmask.long.byte 0x8 0.--3. 1. "T1_FREQ_SEL,AHB2 Clock Frequency Select"
line.long 0xC "CIU2_CLK_UARTCLK_CTRL,UART Clock Control"
hexmask.long 0xC 7.--31. 1. "NCO_STEP_SIZE,Programmable UART Clock Frequency"
newline
bitfld.long 0xC 0. "REFCLK_SEL,Reference Clock Select" "0,1"
line.long 0x10 "CIU2_CLK_LBU2_BTRTU1_CTRL,LBU2 BT_RTU1 Clock Control"
bitfld.long 0x10 15. "BTRTU1_DBG_CLK_CTRL,BTRTU1 Debug Clock Control Feature" "0,1"
newline
bitfld.long 0x10 12. "BTRTU1_USE_REF_CLK,Static bit set by FW. If it is required that timers need not be programmed with dynamic switching of T1/Reference the BT_RTU1 source clock is set on reference clock so that the timer are not disturbed." "0,1"
newline
bitfld.long 0x10 11. "BTRTU1_TIMER1_USE_SLP_CLK,Timer 1 BT_RTU1 Clock" "0,1"
newline
bitfld.long 0x10 1. "LBU2_USE_REFCLK,Static bit set by FW based on Reference Clock Frequency. If reference clock frequency is lower and LBU can not support high baud rate of UART then FW will set soc_use_ref_mode = 0. This is an indication for Bluetooth subsystem that there.." "0,1"
group.long 0x118++0x13
line.long 0x0 "CIU2_CLK_CP15_DIS3,Clock Auto Shut-off Enable3"
bitfld.long 0x0 31. "BLE_AHB_CLK,BLE Shut Off" "0,1"
newline
bitfld.long 0x0 30. "BTU_AHB_CLK,BTU Shut Off" "0,1"
newline
bitfld.long 0x0 28. "BLE_HCLK,BLE ahb Arbiter/Decoder Shut Off" "0,1"
newline
bitfld.long 0x0 25.--26. "DMEM_AHB2_CLK,DMEM_AHB2 Shut Off" "0,1,2,3"
newline
hexmask.long.byte 0x0 21.--24. 1. "IMEM_AHB2_CLK,IMEM_AHB2 Shut Off"
newline
bitfld.long 0x0 20. "FFU_AHB2_CLK,FFU_AHB Shut Off" "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "BR_AHB2_CLK,BRU_AHB2 Shut Off"
line.long 0x4 "CIU2_RST_SW3,Software Module Reset"
bitfld.long 0x4 30. "BT_16M_CLK_,Bt 16M clock reset" "0,1"
newline
bitfld.long 0x4 29. "WD2_CPU2_RST_DISABLE,WD2 CPU2 Reset Control" "0,1"
newline
bitfld.long 0x4 28. "WD2_CHIP_RST_DISABLE,WD2 Chip Reset Control" "0,1"
newline
bitfld.long 0x4 26. "BRF_PR_,BRF_PR Reset" "0,1"
newline
bitfld.long 0x4 22. "CIU2_AHB_CLK_,CIU2 AHB Soft Reset" "0,1"
newline
bitfld.long 0x4 20. "HPU2_,HPU2 Reset" "0,1"
newline
bitfld.long 0x4 19. "SIF_AHB2_CLK_,sif ahb2 Clock Soft Reset" "0,1"
newline
bitfld.long 0x4 18. "SIF_,sif clock Soft Reset" "0,1"
newline
bitfld.long 0x4 16. "SMU2_AHB_CLK_,SMU2 (AHB_Clk) Soft Reset" "0,1"
newline
bitfld.long 0x4 11. "SIU_AHB2_CLK_N,BT SIU (UART) AHB soft reset" "0,1"
newline
bitfld.long 0x4 10. "BT_UART_N,BT UART soft reset" "0,1"
newline
bitfld.long 0x4 9. "BRU_AHB2_CLK_,BRU_AHB2 Soft Reset" "0,1"
newline
bitfld.long 0x4 8. "DEC_AHB2_CLK_,AHB2 Decoder Mux Soft Reset" "0,1"
newline
bitfld.long 0x4 7. "ARB_AHB2_CLK_,AHB2 Arbiter Soft Reset" "0,1"
newline
bitfld.long 0x4 5. "CPU2_TCM_,CPU2 TCM/DMA/Arbiter reset" "0,1"
newline
bitfld.long 0x4 4. "CPU2_CORE_,CPU2 core reset" "0,1"
newline
bitfld.long 0x4 2. "BT_COMMON_,BT Common Soft Rest" "0,1"
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bitfld.long 0x4 1. "BLE_SOC_,BLE SoC Soft Reset" "0,1"
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bitfld.long 0x4 0. "BTU_AHB_CLK_,BTU (ARM_Clk) Soft Reset" "0,1"
line.long 0x8 "CIU2_MEM_WRTC3,Memory WRTC Control 3"
bitfld.long 0x8 20.--21. "R1P_WTC,WTC for small memory for UART in AHB2_TOP" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "R1P_RTC,RTC for small memory for UART in AHB2_TOP" "0,1,2,3"
newline
bitfld.long 0x8 12.--13. "BLE_ROM_RTC_REF,BLE ROM RTC_REF" "0,1,2,3"
newline
bitfld.long 0x8 8.--10. "BLE_ROM_RTC,BLE ROM RTC" "0,1,2,3,4,5,6,7"
line.long 0xC "CIU2_MEM_WRTC4,Memory WRTC Control 4"
bitfld.long 0xC 28.--29. "BLE_WTC,ble WTC" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "BLE_RTC,ble RTC" "0,1,2,3"
newline
bitfld.long 0xC 20.--21. "BTU_WTC,BTU EBRAM WTC" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "BTU_RTC,BTU EBRAM RTC" "0,1,2,3"
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bitfld.long 0xC 16.--17. "CPU2_BRU_RTC_REF,CPU2 BROM RTC_REF" "0,1,2,3"
newline
bitfld.long 0xC 12.--14. "CPU2_BRU_RTC,CPU2 BROM RTC" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 10.--11. "SMU2_WTC,SMU2 WTC" "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "SMU2_RTC,SMU2 RTC" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "CPU2_DTCM_WTC,CPU2 DTCM WTC" "0,1,2,3"
newline
bitfld.long 0xC 4.--5. "CPU2_DTCM_RTC,CPU2 DTCM RTC" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "CPU2_ITCM_WTC,CPU2 ITCM WTC" "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "CPU2_ITCM_RTC,CPU2 ITCM RTC" "0,1,2,3"
line.long 0x10 "CIU2_MEM_PWDN3,Memory Power down Control"
bitfld.long 0x10 25. "BT_ADMA_BYPASS_EN,Firmware Bypass Enable for BT ADMA Memories Power Down" "0,1"
newline
bitfld.long 0x10 22. "BTU_BYPASS_EN,Firmware Bypass Enable for BTU Memories Power Down" "0,1"
newline
bitfld.long 0x10 21. "SIU_BYPASS_EN,Firmware Bypass Enable for UART Memories Power Down" "0,1"
newline
bitfld.long 0x10 20. "SMU2_BYPASS_EN,Firmware Bypass Enable for SMU2 Memories Power Down" "0,1"
newline
bitfld.long 0x10 18. "CPU2_ITCM_BYPASS_EN,Firmware Bypass Enable for CPU2 ITCM Memories Power Down" "0,1"
newline
bitfld.long 0x10 17. "CPU2_DTCM_BYPASS_EN,Firmware Bypass Enable for CPU2 DTCM Memories Power Down" "0,1"
newline
bitfld.long 0x10 16. "CPU2_BRU_BYPASS_EN,Firmware Bypass Enable for CPU2 Boot ROM Memories Power Down" "0,1"
newline
bitfld.long 0x10 9. "BT_ADMA_BYPASS_VAL,Firmware Bypass value for BT ADMA Memories Power Down" "0,1"
newline
bitfld.long 0x10 6. "BTU_BYPASS_VAL,Firmware Bypass value for BTU Memories Power Down" "0,1"
newline
bitfld.long 0x10 5. "SIU_BYPASS_VAL,Firmware Bypass value for UART Memories Power Down" "0,1"
newline
bitfld.long 0x10 4. "SMU2_BYPASS_VAL,Firmware Bypass value for SMU2 Memories Power Down" "0,1"
newline
bitfld.long 0x10 2. "CPU2_ITCM_BYPASS_VAL,Firmware Bypass value for CPU2 ITCM Memories Power Down" "0,1"
newline
bitfld.long 0x10 1. "CPU2_DTCM_BYPASS_VAL,Firmware Bypass value for CPU2 DTCM Memories Power Down" "0,1"
newline
bitfld.long 0x10 0. "CPU2_BRU_BYPASS_VAL,Firmware Bypass value for CPU2 Boot ROM Memories Power Down" "0,1"
rgroup.long 0x12C++0x3
line.long 0x0 "CIU2_SOC_AHB2APB_STATUS,SOC AHB2APB Status"
bitfld.long 0x0 0. "CMD_FIFO_AFULL,soc_io_top ahb2apb command fifo almost full status" "0,1"
group.long 0x140++0x3
line.long 0x0 "CIU2_BLE_CTRL,BLE Control and Status"
bitfld.long 0x0 8. "BT_AES_CLK_FREQ_SEL,btu_aes_clk Frequency Select" "0,1"
rgroup.long 0x144++0x7
line.long 0x0 "CIU2_AHB2_TO_LAST_ADDR,AHB2 Timeout Last Address"
hexmask.long 0x0 0.--31. 1. "ADDRESS,Last AHB2 Address Right Before the Current Timeout"
line.long 0x4 "CIU2_AHB2_TO_CUR_ADDR,AHB2 Current Timeout Address"
hexmask.long 0x4 0.--31. 1. "ADDRESS,Current_TO_Addr"
group.long 0x14C++0xB
line.long 0x0 "CIU2_AHB2_TO_CTRL,AHB2 ARB Control"
bitfld.long 0x0 30.--31. "AHB2_TIMEOUT_MODE,AHB2_TimeoutMode[1:0]" "0,1,2,3"
newline
bitfld.long 0x0 18. "AHB2_CPU2_DMEM_PROT_DIS,1 = Disable CPU2 Dmem Memory Protection from AHB2 side and allow AHB2 to read/write Dmem" "?,1: Disable CPU2 Dmem Memory Protection from AHB2.."
newline
bitfld.long 0x0 17. "AHB2_CPU2_IMEM_PROT_DIS,1 = Disable CPU2 Imem Memory Protection from AHB2 side and allow AHB2 to read/write Imem" "?,1: Disable CPU2 Imem Memory Protection from AHB2.."
newline
bitfld.long 0x0 16. "AHB2_SMU1_MEM_PROT_DIS,Disable SMU1 Memory Protection from AHB2 side" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "LAST_TO_MASTER_ID,AHB2 Last_TO_Master_ID"
newline
hexmask.long.byte 0x0 8.--11. 1. "CURRENT_TO_MASTER_ID,AHB2 Current_TO_Master_ID"
newline
hexmask.long.byte 0x0 4.--7. 1. "LAST_TO_SLAVE_ID,Last_TO_Slave_ID"
newline
hexmask.long.byte 0x0 0.--3. 1. "CURRENT_TO_SLAVE_ID,Current_TO_Slave_ID"
line.long 0x4 "CIU2_AHB2_SMU1_ACCESS_ADDR,AHB2 to SMU1 Accessible Address"
hexmask.long 0x4 0.--31. 1. "AHB2_SMU1_ACCESS_ADDR,SMU1 Accessible Memory Address from AHB2 side"
line.long 0x8 "CIU2_AHB2_SMU1_ACCESS_MASK,AHB2 to SMU1 Accessible Mask"
hexmask.long 0x8 0.--31. 1. "AHB2_SMU1_ACCESS_MASK,SMU1 Accessible Memory Mask from AHB2 side"
group.long 0x15C++0x3
line.long 0x0 "CIU2_CPU2_ICODE_INV_ADDR_CTRL,CPU2 Icode invalid address access control"
bitfld.long 0x0 30.--31. "HADDR_ICOD_SEL,There are 3 haddr which can be observed by selecting this:" "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "CUR_INV_ADDR_SLAVE_ID,Cur_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 4.--7. 1. "LAST_INV_ADDR_SLAVE_ID,Last_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 0.--3. 1. "LAST2_INV_ADDR_SLAVE_ID,Last2_inv_addr_Slave_ID"
rgroup.long 0x160++0x3
line.long 0x0 "CIU2_CPU2_ICODE_INV_ADDR,CPU2 Icode invalid address"
hexmask.long 0x0 0.--31. 1. "HADDR_INV_ADDR,based on CIU_CPU2_ICODE_INV_ADDR_CTRL[31:30] the address status is observed in this register"
group.long 0x164++0x3
line.long 0x0 "CIU2_CPU2_DCODE_INV_ADDR_CTRL,CPU2 Dcode invalid address access control"
bitfld.long 0x0 30.--31. "HADDR_ICOD_SEL,There are 3 haddr which can be observed by selecting this:" "0,1,2,3"
newline
hexmask.long.byte 0x0 20.--23. 1. "CUR_INV_ADDR_MASTER_ID,Cur_inv_addr_master_ID"
newline
hexmask.long.byte 0x0 16.--19. 1. "LAST_INV_ADDR_MASTER_ID,Last_inv_addr_master_ID"
newline
hexmask.long.byte 0x0 12.--15. 1. "LAST2_INV_ADDR_MASTER_ID,Last2_inv_addr_master_ID"
newline
hexmask.long.byte 0x0 8.--11. 1. "CUR_INV_ADDR_SLAVE_ID,Cur_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 4.--7. 1. "LAST_INV_ADDR_SLAVE_ID,Last_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 0.--3. 1. "LAST2_INV_ADDR_SLAVE_ID,Last2_inv_addr_Slave_ID"
rgroup.long 0x168++0x3
line.long 0x0 "CIU2_CPU2_DCODE_INV_ADDR,CPU2 Dcode invalid address"
hexmask.long 0x0 0.--31. 1. "HADDR_INV_ADDR,based on CIU_CPU2_DCODE_INV_ADDR_CTRL[31:30] the address status is observed in this register"
group.long 0x16C++0xB
line.long 0x0 "CIU2_CPU_CPU2_CTRL,CPU2 control register"
bitfld.long 0x0 31. "CPU1_RESET_INT,CPU2 fw resets cpu1( or cpu3 fw resets cpu1 if this register is used by cpu3)" "0,1"
newline
bitfld.long 0x0 30. "DSR_WKUP_IN_USE,dsr wkup when dsr_wkup_in_use = 1'b1" "0,1"
newline
bitfld.long 0x0 29. "CPU3_RESET_INT,CPU2 fw resets cpu3(or cpu3 fw resets CPU2 if this register is used by cpu3)" "0,1"
newline
bitfld.long 0x0 28. "MCI_AHB2_MSG_SCHEME,IMU Scheme Select for Communication between AHB2 & MCI" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "CPU2_DBG_CTRL,cpu2 debug control"
newline
bitfld.long 0x0 5. "CPU2_BOOT_DMEM_MUX_EN,CPU2 DMEM mux Enable" "0,1"
newline
bitfld.long 0x0 4. "CPU2_BOOT_IMEM_MUX_EN,CPU2 Boot IMEM mux Enable" "0,1"
newline
bitfld.long 0x0 2. "CPU2_JTAG_CHAIN_BYPASS,CPU2 JTAG Chain Bypass Control" "0,1"
newline
bitfld.long 0x0 0. "VINITHI,Boot Address Control" "0,1"
line.long 0x4 "CIU2_BRF_CTRL,BRF Control and Status"
rbitfld.long 0x4 31. "BRF_CHIP_RDY,BRF Chip_Rdy Status" "0,1"
newline
bitfld.long 0x4 11. "FFU_USE_BRF_RX_PATH,This bit is connected to FRF_15P4_USE_BRF_RX_PATH input of BRF as recommended by Sridhar." "0,1"
newline
bitfld.long 0x4 10. "BRF_SQU_DUMP_EN,Enable SQU data dump from BRF" "0,1"
newline
bitfld.long 0x4 9. "CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL,1. brf ref clk 1x is enabled" "0,1"
newline
bitfld.long 0x4 8. "CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN,BRF REF1X Clock Control Bypass Enable" "0,1"
newline
bitfld.long 0x4 0. "AHB_SLV_BRF_SER_EN,When set to 1 BRF serial interface will be accessed thru AHB slave memory mapped from 0xA800A000 to 0xA8011FFF" "0,1"
line.long 0x8 "CIU2_BRF_EXTRA_PORT,BRF Extra Port Connection"
hexmask.long.byte 0x8 0.--3. 1. "SOC_BRF_EXTRA,SOC_BRF_EXTRA[3:0]"
group.long 0x17C++0x13
line.long 0x0 "CIU2_BRF_ECO_CTRL,BRF ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved"
line.long 0x4 "CIU2_BTU_CTRL,BTU Control and Status"
rbitfld.long 0x4 31. "BTU_MC_WAKEUP,BTU MC_Wakeup Status" "0,1"
newline
bitfld.long 0x4 8.--10. "BT_IP_SER_SEL,bt_ip_ser_sel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 2.--3. "BT_CLK_SEL,Bluetooth sys Clock Select" "0,1,2,3"
newline
bitfld.long 0x4 1. "DBUS_HIGH_SPEED_SEL,Dbus High Speed Select Signal for Greater than 4 MHz" "0,1"
newline
bitfld.long 0x4 0. "BTU_CIPHER_EN,Bluetooth Cipher Logic" "0,1"
line.long 0x8 "CIU2_BT_PS,BT Clock Power Save"
bitfld.long 0x8 28. "BT_MCLK_FROM_SOC_SEL,BT_MCLK" "0,1"
newline
bitfld.long 0x8 27. "BT_MCLK_TBG_NCO_SEL,BT_4M_PCM_CLK" "0,1"
newline
bitfld.long 0x8 26. "BT_MCLK_NCO_EN,BT_MCLK_NCO logic to count" "0,1"
newline
hexmask.long 0x8 0.--25. 1. "BT_MCLK_NCO_MVAL,BT_MCLK NCO Module Step Control (default 0x0)"
line.long 0xC "CIU2_BT_PS2,BT Clock Power Save 2"
bitfld.long 0xC 27. "BT_PCM_CLK_TBG_NCO_SEL,BT_4M_PCM_CLK" "0,1"
newline
bitfld.long 0xC 26. "BT_PCM_CLK_NCO_EN,BT_PCM_CLK_NCO logic to count" "0,1"
newline
hexmask.long 0xC 0.--25. 1. "BT_PCM_CLK_NCO_MVAL,BT_PCM_CLK NCO Module Step Control (default 0x0)"
line.long 0x10 "CIU2_BT_REF_CTRL,BT Ref Control"
bitfld.long 0x10 20. "BT_CLK_NCO_REFCLK_SEL,BT clk (bt sys clk) selection" "0,1"
newline
hexmask.long.word 0x10 2.--17. 1. "NCO_GEN,Bluetooth Reference Clock NCO Gen Value"
newline
bitfld.long 0x10 1. "NCO_SEL,Bluetooth Reference Clock NCO Select Value" "0,1"
newline
bitfld.long 0x10 0. "NCO_EN,Bluetooth Reference Clock NCO Enable information to APU." "0,1"
group.long 0x194++0x7
line.long 0x0 "CIU2_BT_PS3,BT Clock Power Save 3"
bitfld.long 0x0 29. "BTU_CLK_NCO_MODE,BTU Clock source from ref clock (nco mode)" "0,1"
newline
bitfld.long 0x0 27. "BTU_16M_CLK_NCO_SEL,BTU 16M clock NCO Select Value" "0,1"
newline
bitfld.long 0x0 26. "BTU_16M_CLK_NCO_EN,BTU 16M Clock NCO Enable" "0,1"
newline
hexmask.long 0x0 0.--25. 1. "BTU_16M_CLK_NCO_STEP_CTRL,BT_16M_CLK NCO Module Step Control"
line.long 0x4 "CIU2_BTU_ECO_CTRL,BTU ECO Control"
hexmask.long 0x4 0.--31. 1. "ECO_BITS,Reserved"
group.long 0x1A0++0xB
line.long 0x0 "CIU2_INT_MASK,CIU2 Interrupt Mask"
hexmask.long 0x0 0.--31. 1. "MASK,Interrupt Mask for CIU2 Interrupts"
line.long 0x4 "CIU2_INT_SELECT,CIU2 Interrupt Select"
hexmask.long 0x4 0.--31. 1. "SEL,Interrupt Read/Write Clear for CIU2 Interrupts"
line.long 0x8 "CIU2_INT_EVENT_MASK,CIU2 Interrupt Event Mask"
hexmask.long 0x8 0.--31. 1. "MASK,Interrupt Event Mask for CIU2 Interrupts"
rgroup.long 0x1AC++0x3
line.long 0x0 "CIU2_INT_STATUS,CIU2 Interrupt Status"
hexmask.long 0x0 0.--31. 1. "CIU_ISR,CIU2 Interrupt Status (ISR)"
group.long 0x1B0++0xB
line.long 0x0 "CPU2_ERR_INT_MASK,CPU2 ERR Interrupt Mask"
hexmask.long 0x0 0.--31. 1. "MASK,Interrupt Mask for CPU2 ERR Interrupts"
line.long 0x4 "CPU2_ERR_INT_SELECT,CPU2 ERR Interrupt Clear Select"
hexmask.long 0x4 0.--31. 1. "SEL,Interrupt Read/Write Clear for CPU2 ERR Interrupts"
line.long 0x8 "CPU2_ERR_INT_EVENT_MASK,CPU2 ERR Interrupt Event Mask"
hexmask.long 0x8 0.--31. 1. "MASK,Interrupt Event Mask for CPU2 ERR Interrupts"
rgroup.long 0x1BC++0x3
line.long 0x0 "CPU2_ERR_INT_STATUS,CPU2 ERR Interrupt Status"
hexmask.long 0x0 0.--31. 1. "ERR_ISR,CPU2 ERR Interrupt Status (ISR)"
group.long 0x200++0xB
line.long 0x0 "CIU2_BCA1_CPU2_INT_MASK,BCA1 to CPU2 Interrupt Mask"
hexmask.long 0x0 0.--31. 1. "IMR,Interrupt Mask for BCA1 to CPU2 Interrupts"
line.long 0x4 "CIU2_BCA1_CPU2_INT_SELECT,BCA1 to CPU2 Interrupt Select"
hexmask.long 0x4 0.--31. 1. "RSR,Interrupt Read/Write Clear for BCA1 to CPU2 Interrupts"
line.long 0x8 "CIU2_BCA1_CPU2_INT_EVENT_MASK,BCA1 to CPU2 Interrupt Event Mask"
hexmask.long 0x8 0.--31. 1. "SMR,Interrupt Event Mask for BCA1 to CPU2 Interrupts"
rgroup.long 0x20C++0x3
line.long 0x0 "CIU2_BCA1_CPU2_INT_STATUS,BCA1 to CPU2 Interrupt Status"
hexmask.long 0x0 0.--31. 1. "ISR,BCA1 to CPU2 Interrupt Status"
group.long 0x210++0x13
line.long 0x0 "CIU2_APU_BYPASS1,CIU2 APU Bypass Register 1"
bitfld.long 0x0 10. "TBG_BTU_CLK_EN_BYPASS_VAL,TBG512_320_176_BTU_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 9. "BT_AES_CLK_SEL_BYPASS_VAL,Firmware Bypass Value for Btu_Aes_Clk_Sel" "0,1"
newline
bitfld.long 0x0 8. "BT_AES_CLK_SEL_BYPASS_EN,Firmware Bypass for Btu_Aes_Clk_Sel" "0,1"
newline
bitfld.long 0x0 6.--7. "TBG_BTU_CLK_EN_BYPASS_SEL,TBG512_320_176_BTU_Clk_En_Sel to TBG512_320_176 of CAU" "0,1,2,3"
newline
bitfld.long 0x0 5. "SOC_CLK_EN2_T1_BYPASS_VAL,Firmware Bypass Value for SoC_Clk_En2(active high signal)" "0,1"
newline
bitfld.long 0x0 4. "SOC_CLK_EN2_T1_BYPASS_EN,Firmware Bypass for SoC_Clk_En2" "0,1"
newline
bitfld.long 0x0 3. "BT_AES_CLK_EN_BYPASS_VAL,Firmware Bypass Value for Btu_Aes_Clk" "0,1"
newline
bitfld.long 0x0 2. "BT_AES_CLK_EN_BYPASS_EN,Firmware Bypass for Btu_Aes_Clk" "0,1"
newline
bitfld.long 0x0 1. "BRF_CLK_EN_BYPASS_VAL,Firmware Bypass Value for BRF_Clk_En (active high signal)" "0,1"
newline
bitfld.long 0x0 0. "BRF_CLK_EN_BYPASS_EN,Firmware Bypass BRF_Clk_En" "0,1"
line.long 0x4 "CIU2_CPU2_LMU_STA_BYPASS0,LMU static bank control byapss0 Register for CPU2 mem"
hexmask.long.byte 0x4 24.--31. 1. "LMU_STA_BANKS_PSW_EN_BP_VAL,Firmware Bypass value for lmu static banks psw_en"
newline
hexmask.long.byte 0x4 16.--23. 1. "LMU_STA_BANKS_PSW_EN_BP_EN,Firmware Bypass enable for lmu static banks psw_en"
newline
hexmask.long.byte 0x4 8.--15. 1. "LMU_STA_BANKS_ISO_EN_BP_VAL,Firmware Bypass value for lmu static banks iso_en"
newline
hexmask.long.byte 0x4 0.--7. 1. "LMU_STA_BANKS_ISO_EN_BP_EN,Firmware Bypass enable for lmu static banks iso_en"
line.long 0x8 "CIU2_CPU2_LMU_STA_BYPASS1,LMU static bank control byapss1 Register for CPU2"
hexmask.long.byte 0x8 24.--31. 1. "LMU_STA_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu static banks fnrst"
newline
hexmask.long.byte 0x8 16.--23. 1. "LMU_STA_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu static banks fnrst"
newline
hexmask.long.byte 0x8 8.--15. 1. "LMU_STA_BANKS_SRAM_PD_BP_VAL,Firmware Bypass value for lmu static banks sram_pd"
newline
hexmask.long.byte 0x8 0.--7. 1. "LMU_STA_BANKS_SRAM_PD_BP_EN,Firmware Bypass enable for lmu static banks sram_pd"
line.long 0xC "CIU2_CPU2_LMU_STA_BYPASS2,LMU static bank byapss2 Register for CPU2"
hexmask.long.byte 0xC 8.--15. 1. "LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl"
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hexmask.long.byte 0xC 0.--7. 1. "LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl"
line.long 0x10 "CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS,LMU G2Bist control bypass Register for CPU2"
hexmask.long.byte 0x10 1.--7. 1. "LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL,Firmware Bypass value for CPU2 static banks lmu power domain repair request"
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bitfld.long 0x10 0. "LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN,Firmware Bypass enable for CPU2 static banks lmu power domain repair request" "0,1"
group.long 0x22C++0x1B
line.long 0x0 "CIU2_APU_PWR_CTRL_BYPASS1,APU power control Bypass Register 1"
bitfld.long 0x0 9. "BRF_SRAM_PD_BYPASS_EN,Firmware Bypass SRAM_PD from APU" "0,1"
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bitfld.long 0x0 8. "BRF_SRAM_PD_BYPASS_VAL,Firmware Bypass Value for SRAM_PD (active high signal)" "0,1"
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bitfld.long 0x0 7. "BRF_CLK_DIV_RSTB_BYPASS_EN,Firmware Bypass brf Clk_Div_Rstb from APU" "0,1"
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bitfld.long 0x0 6. "BRF_CLK_DIV_RSTB_BYPASS_VAL,Firmware Bypass Value for brf Clk_Div_Rstb (active low signal)" "0,1"
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bitfld.long 0x0 5. "BRF_ISO_EN_BYPASS_EN,brf Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0x0 4. "BRF_ISO_EN_BYPASS_VAL,brf Isolation Cell Control" "0,1"
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bitfld.long 0x0 3. "BRF_FWBAR_BYPASS_EN,brf Firewallbar Control Enable" "0,1"
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bitfld.long 0x0 2. "BRF_FWBAR_BYPASS_VAL,brf Firewallbar Control" "0,1"
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bitfld.long 0x0 1. "BRF_PSW_BYPASS_EN,brf Power Switch Control Enable" "0,1"
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bitfld.long 0x0 0. "BRF_PSW_BYPASS_VAL,brf Power Switch Control" "0,1"
line.long 0x4 "CIU2_AHB2AHB_BRIDGE_CTRL,AHB2AHB Bridge Control Register"
bitfld.long 0x4 1. "MCI_AHB2_A2A_PREFETCH_EN,MCI-AHB2 ahb2ahb bridge pre-fetch hsel enable" "0,1"
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bitfld.long 0x4 0. "PREFETCH_HSEL_EN,ahb2ahb bridge pre-fetch hsel enable" "0,1"
line.long 0x8 "CIU2_CLK_CP15_DIS1,Clock Auto Shut-off Enable1"
bitfld.long 0x8 20. "CIU_BTAPU_AHB_CLK_DIS_ON_SLP,APU Shut Off" "0,1"
line.long 0xC "CIU_CLK_RTU_NCO_CTRL,RTU NCO Clock Control"
hexmask.long.word 0xC 16.--31. 1. "CIU_BTRTU_NCO_STEP,Step size for RTU clock NCO (Reference Clock Based)"
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bitfld.long 0xC 2. "CIU_BTRTU_NCO_ENABLE,RTU NCO Enable (Reference Clock Based)" "0,1"
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bitfld.long 0xC 1. "CIU_BTRTU_NCO_OUT_SEL,RTU NCO Mode Select (Reference Clock Based)" "0,1"
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bitfld.long 0xC 0. "CIU_BTRTU_REF_CLK_SEL,RTU Reference Clock from UART reference clock tree" "0,1"
line.long 0x10 "CIU_CLK_SOCCLK_CTRL,SOC Clock Control"
hexmask.long.byte 0x10 28.--31. 1. "AHB2_AHB2APB_WAIT_CYCLES,AH2 AHB2APB Wait Cycles between each APB transaction"
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hexmask.long.byte 0x10 16.--19. 1. "AHB2_AHB2APB_PCLK_DIV_SEL,AHB2 AHB2APB PCLK Divider Select"
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bitfld.long 0x10 15. "BT_AES_CLK_32_64_SEL,BT AES Clock Select 32 MHz or 64 MHz select" "0,1"
newline
bitfld.long 0x10 14. "CIU_USE_REFCLK,SoC_Clk Clock" "0,1"
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bitfld.long 0x10 13. "PM_CLK_TBG_SEL,PM Clock" "0,1"
newline
bitfld.long 0x10 12. "PM_CLK_SEL,PM Clock source select" "0,1"
newline
bitfld.long 0x10 11. "CIU_BTAPU_CAL_CLK_SEL,PMU Calibration Clock" "0,1"
newline
bitfld.long 0x10 10. "CIU_BTAPU_CONST_CAL_CLK_SEL,PMU Constant Calibration Clock Select" "0,1"
newline
bitfld.long 0x10 9. "BTU_MCLK_T3_512_DIV125_CLK_SEL,T3_512 DIV125 Clock Select" "0,1"
newline
bitfld.long 0x10 8. "BTU_MCLK_T3_512_DIV125_EN,T3_512 DIV125 Enable" "0,1"
newline
bitfld.long 0x10 7. "BTU_PCM_CLK_T3_256_DIV125_CLK_SEL,T3_256 DIV125 Clock Select" "0,1"
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bitfld.long 0x10 6. "BTU_PCM_CLK_T3_256_DIV125_EN,T3_256 DIV125 Enable" "0,1"
line.long 0x14 "CIU_CLK_SLEEPCLK_CTRL,Sleep Clock Control"
bitfld.long 0x14 30. "CIU_PCIE_SLP_CLK_SEL,PCIE Sleep Clock Select" "0,1"
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bitfld.long 0x14 28. "CIU_REFCLK_SLEEP_CLK_SEL,Reference Clock Sleep Clock Select" "0,1"
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bitfld.long 0x14 25. "CIU_NCO_SLEEP_CLK_SEL,NCO Sleep Clock Select" "0,1"
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hexmask.long.tbyte 0x14 0.--23. 1. "CIU_SLEEP_CLK_NCO_MVAL,Sleep Clock NCO"
line.long 0x18 "CIU_CLK_SLEEPCLK_CTRL2,Sleep Clock Control 2"
bitfld.long 0x18 24. "CIU_SLEEP_CLK_NCO_MVAL_BYPASS,Sleep Clock NCO mval Bypass" "0,1"
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hexmask.long.tbyte 0x18 0.--23. 1. "CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP,Sleep Clock NCO value for the sleep mode"
group.long 0x250++0x7
line.long 0x0 "CIU2_IOMUX_MODE_CTRL,Test Bus Select"
bitfld.long 0x0 2. "CIU2_EXT_FRF_MODE,0: On Chip BRF is used for 15." "0: On Chip BRF is used for 15,?"
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bitfld.long 0x0 1. "CIU2_BRF_STANDALONE_DATA_MODE,'" "0,1"
newline
bitfld.long 0x0 0. "CIU2_EXT_BRF_BIDI_MODE,'" "0,1"
line.long 0x4 "CIU2_RST_SW2,Software Module Reset"
bitfld.long 0x4 22. "CIU2_CFG_RST_,CIU config reset for IMU RTU CIU debug sync" "0,1"
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bitfld.long 0x4 21. "MCI_BLE_A2A_MHRESETN,SW Reset for mci_wl_a2a_mhresetn" "0,1"
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bitfld.long 0x4 20. "CIU2_BTU_SLP_RST_,Soft Reset to BTU Sleep Clock Domain Logic" "0,1"
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bitfld.long 0x4 19. "BLE_AHB_RST_,SW reset for ble ahb arb/dec/ciu" "0,1"
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bitfld.long 0x4 18. "ABH2_SUB_G2BIST_RSTB,SW reset for ble abh2-system g2bist controller" "0,1"
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bitfld.long 0x4 17. "CIU2_FFU_SLP_RST_,Soft Reset to FFU Sleep Clock Domain Logic" "0,1"
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bitfld.long 0x4 16. "CIU2_FFU_AHB_RST_,Soft Reset to FFU AHB I/F logic" "0,1"
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bitfld.long 0x4 10. "CIU2_AHB2APB_SW_RESETN,SW reset to the ahb2apb hresetn" "0,1"
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bitfld.long 0x4 9. "CIU2_FFU_RST_,Soft Reset to FFU" "0,1"
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bitfld.long 0x4 8. "SOCCIU_A2A_RST_,Soft Reset to A2A in SOCCIU" "0,1"
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bitfld.long 0x4 7. "MSC_A2A_,Soft Reset to A2A in MSC" "0,1"
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bitfld.long 0x4 6. "SMU2_TM_,Test Mode Reset for SMU2" "0,1"
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bitfld.long 0x4 5. "CIU2_REGISTER_RST_,CIU_Reg Module Soft Reset" "0,1"
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bitfld.long 0x4 4. "BTAPU_SLP_CLK_,Sleep Clock Logic reset for BTAPU" "0,1"
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bitfld.long 0x4 3. "BTAPU_REF_CLK_,Ref Clock Logic reset for BTAPU" "0,1"
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bitfld.long 0x4 2. "BTAPU_AHB_CLK_,AHB Clock Logic reset for BTAPU" "0,1"
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bitfld.long 0x4 1. "DRO_,DRO Clock Reset" "0,1"
group.long 0x260++0x7
line.long 0x0 "CIU2_AHB2_TO_CLEAR,AHB2 timeout logic clear register"
bitfld.long 0x0 10. "CPU2_ICODE_INV_ADDR_CLR,After the invalid address int happened on CPU2 icode bus the cpu2 will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the CPU2 Icode invalid addr logic to start recording next.." "0,1"
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bitfld.long 0x0 9. "CPU2_DCODE_INV_ADDR_CLR,After the invalid address int happened on CPU2 dcode bus the cpu2 will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the CPU2 Dcode invalid addr logic to start recording next.." "0,1"
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bitfld.long 0x0 8. "AHB2_TIMEOUT_CLEAR,After the timeout happened on AHB2 bus the cpu will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the AHB2 timeout logic to start recording next transaction. This is self clearing.." "0,1"
line.long 0x4 "CIU2_CPU_DYN_CLK_CTRL,Dynamic CPU Clock Control"
bitfld.long 0x4 30. "DYN_CPU2_CTRL_DIS,Disable Dynamic CPU2 Clock Control Feature" "0,1"
rgroup.long 0x268++0x7
line.long 0x0 "CPU2_DBG_STAT,CPU2 debug register"
hexmask.long 0x0 0.--31. 1. "CPU2_STATUS,cpu2 debug output"
line.long 0x4 "BTSS_MBIST_STAT,no description available"
hexmask.long.word 0x4 16.--24. 1. "BLESS_MBIST_READY,BIST Ready from memories in BT Sub System"
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hexmask.long.word 0x4 0.--8. 1. "BLESS_MBIST_FAIL,BIST Fail Indication from memories in BT Sub System"
group.long 0x274++0x3
line.long 0x0 "CIU2_TEST_MODE,'"
bitfld.long 0x0 0. "BT_UART_MODE,Indicates UART Mode for I/O muxing" "0,1"
group.long 0x27C++0x3
line.long 0x0 "CIU2_APU_BYPASS2,CIU2 APU Bypass Register 2"
bitfld.long 0x0 20. "TBG_FFU_CLK_EN_BYPASS_VAL,TBG FFU clock enable bypass value" "0,1"
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bitfld.long 0x0 18.--19. "TBG_FFU_CLK_EN_BYPASS_SEL,TBG FFU clock enable bypass select" "0,1,2,3"
rgroup.long 0x280++0x3
line.long 0x0 "CIU2_TST_G2BIST_STATUS,WL G2BIST Status"
bitfld.long 0x0 8. "AHB2_G2B_FINIH,AHB2 Bist Done" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "AHB2_G2B_STATUS,Redundant Bist Selection"
group.long 0x284++0x3
line.long 0x0 "CIU2_LPO_CLK_GEN_CTRL,BLE LPO CLK GEN Control"
bitfld.long 0x0 8.--9. "LPO_CLK_SEL,Selects the source of 4 MHz clock input to BLE LPO Clock Generator" "0,1,2,3"
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bitfld.long 0x0 7. "REF_4M_RST_,Soft Reset to LPO Clock Generator for 4M Clock Domain Logic" "0,1"
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bitfld.long 0x0 6. "SLP_CLK_RST_,Soft Reset to LPO Clock Generator for NCO Sleep Clock Domain Logic" "0,1"
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bitfld.long 0x0 4.--5. "LBC_DEBUG_CTRL,LBC Debug Control Signal" "0,1,2,3"
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bitfld.long 0x0 3. "SLP_CLK_NCO_EN,Enable NCO Counter in ble_lpoClk_gen" "0,1"
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bitfld.long 0x0 2. "MAN_SEL_NCO,Manually Switch back to NCO Version" "0,1"
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bitfld.long 0x0 1. "DEJIT_EN,Enable De-jitter block" "0,1"
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bitfld.long 0x0 0. "AUTO_DEJIT,Enable Auto Dejitter" "0,1"
rgroup.long 0x288++0x3
line.long 0x0 "CIU2_LPO_CLK_GEN_STATUS,BLE LPO CLK GEN Status"
bitfld.long 0x0 11. "NCO_LPO_RAMP_DN_LV,'" "0,1"
newline
bitfld.long 0x0 10. "REF_LPO_CLK_GOOD,'" "0,1"
newline
bitfld.long 0x0 9. "REF_LPO_RAMP_DN,'" "0,1"
newline
bitfld.long 0x0 8. "LPO_CLK_SEL_FSM,'" "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "LPO_CLK_3K2_CNT,'"
group.long 0x28C++0x7
line.long 0x0 "CIU2_LPO_SLP_CLK_GEN_CTRL,'"
hexmask.long 0x0 0.--31. 1. "SLP_CLK_NCO_STEP,'"
line.long 0x4 "CPU2_INT_CTRL,'"
hexmask.long.byte 0x4 0.--3. 1. "CPU2_CPU3_GP_INT,General Purpose Interrupt in Secure Region"
rgroup.long 0x294++0x7
line.long 0x0 "CIU2_BRF_EXTRA_PORT_STATUS,'"
bitfld.long 0x0 8. "BRF_ERR_FLAG,Error Flag Output from BRF is reported here." "0,1"
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bitfld.long 0x0 0.--1. "BRF_CIU2_EXTRA_STATUS,[1:0] of BRF_SOC_EXTRA output of BRF are made available as status register bits." "0,1,2,3"
line.long 0x4 "CIU2_DEBUG,'"
bitfld.long 0x4 0. "P2C_UART_SIN,Status of UART SIN (p2c_uart_sin) net is captured here." "0,1"
group.long 0x300++0xB
line.long 0x0 "CIU2_MCI_EXTRA,MCI EXTRA Ports"
hexmask.long.byte 0x0 4.--7. 1. "CIU2_MCI_EXTRA_IN,Extra Ports from MCI"
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hexmask.long.byte 0x0 0.--3. 1. "CIU2_MCI_EXTRA_OUT,Extra Ports to MCI"
line.long 0x4 "CIU2_TSTBUS_SEL,Test Bus Select"
bitfld.long 0x4 4. "SMU2_TSTBUS_SEL,Selects between following 2 Test Buses in SMU2" "0,1"
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bitfld.long 0x4 0. "AHB2_TSTBUS_SEL,Select between 2 groups of signals; The output of the mux is driven to BLE Test Mux Logic so that it can be observed on GPIOs." "0,1"
line.long 0x8 "FFU_CTRL,FFU Specific Control Register"
bitfld.long 0x8 0. "USE_TX_EN_EXTEND,Selects tx_en_extend port of FFU & drives it on c2p_soc_zigbee_tx_en." "0,1"
group.long 0x380++0x7
line.long 0x0 "BLE_RAACS_CTRL,RAACS control registers"
hexmask.long.word 0x0 19.--31. 1. "RAACS_IDLE_COUNTER_VALUE,IDLE time for which RAACS-FSM waits before shifting to next successive scaled clock."
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hexmask.long.word 0x0 5.--18. 1. "RAACS_WAIT_COUNTER_VALUE,initial IDLE-time for which RAACS FSM waits before starting to scale down the clock."
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bitfld.long 0x0 2.--4. "RAACS_CLK_SEL,defines the lowest clock to which RAACS will go down to during IDLE period (x/2; x/4; x/8; ... ;x/128) for the given test." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 1. "USE_RAACS_CLK_FOR_CPU,SW write 0 to use RAACS clock for CPU. SW write 1 to select clock gating based alternate implementation of RAACS clocking for CM3 CPU." "0,1"
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bitfld.long 0x0 0. "RAACS_EN,raacs en . S/W Write 1 to enable raacs block." "0,1"
line.long 0x4 "BLE_RAACS_PERFORMANCE_STATISTICS,RAACS performance statistics counter."
hexmask.long 0x4 1.--27. 1. "RAACS_PERFORMANCE_STATISTICS,This counter is maintaining RAACS performance count. This counter will increment by one after every 1 us(1MHZ) when RAACS is in scaled clk state."
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bitfld.long 0x4 0. "PERFORMANCE_STATISTICS_CNT_EN,performance counter en. S/W write 1 to enable performance counter." "0,1"
group.long 0x1BF800++0x7
line.long 0x0 "CIU2_CPU_CPU2_MSG_CTRL,CPU2 message register"
bitfld.long 0x0 9. "CPU3_TO_CPU2_MSG_PROCESS_DONE,CPU3 Message for CPU2 has been read by CPU2 and executed. This is self clearing bit. The CPU2 writes 1 to indicate that message send by CPU3 is executed. This generates an Interrupt to CPU3 via CIU1." "0,1"
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bitfld.long 0x0 8. "CPU2_TO_CPU3_MSG_PROCESS_DONE,CPU2 Message for CPU3 has been read by CPU3 and executed. This is self clearing bit. The CPU3 writes 1 to indicate that message send by CPU2 is executed. This generates an Interrupt to CPU2 via CIU1." "0,1"
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bitfld.long 0x0 1. "CPU3_TO_CPU2_MSG_RDY,CPU3 Message for CPU2 is ready. This is self clearing bit. The CPU3 writes 1 to indicate that message for CPU2 is ready. This generates an Interrupt to CPU2 via APU. This is old scheme and we should use IMU based scheme." "0,1"
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bitfld.long 0x0 0. "CPU2_TO_CPU3_MSG_RDY,CPU2 Message for CPU3 is ready. This is self clearing bit. The CPU2 writes 1 to indicate that message for CPU3is ready. This generates an Interrupt to CPU3 via APU. This is old scheme and we should use IMU based scheme." "0,1"
line.long 0x4 "CIU2_IMU_CPU3_WR_MSG_TO_CPU2,CPU3 write message to CPU2"
hexmask.long 0x4 0.--31. 1. "CPU3_WR_MSG_CPU2,Write CPU3 message data to CPU2 (push to FIFO)"
rgroup.long 0x1BF808++0x7
line.long 0x0 "CIU2_IMU_CPU3_RD_MSG_FROM_CPU2,CPU3 read message from CPU2"
hexmask.long 0x0 0.--31. 1. "CPU3_RD_MSG_CPU2,CPU3 read message data from CPU2 (pop from FIFO)"
line.long 0x4 "CIU2_IMU_CPU3_CPU2_MSG_FIFO_STATUS,CPU3 to CPU2 message FIFO status"
hexmask.long.byte 0x4 20.--23. 1. "CPU3_TO_CPU2_MSG_FIFO_RD_PTR,cpu3 to cpu2 msg fifo read pointer for debug"
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hexmask.long.byte 0x4 16.--19. 1. "CPU3_TO_CPU2_MSG_FIFO_WR_PTR,cpu3 to cpu2 msg fifo write pointer for debug"
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hexmask.long.byte 0x4 4.--8. 1. "CPU3_TO_CPU2_MSG_COUNT,cpu3_to_cpu2_msg_count"
newline
bitfld.long 0x4 3. "CPU3_TO_CPU2_MSG_FIFO_EMPTY,cpu3_to_cpu2_msg_fifo_empty" "0,1"
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bitfld.long 0x4 2. "CPU3_TO_CPU2_MSG_FIFO_FULL,cpu3_to_cpu2_msg_fifo_full (based upon FIFO depth)" "0,1"
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bitfld.long 0x4 1. "CPU3_TO_CPU2_MSG_FIFO_ALMOST_FULL,cpu3_to_cpu2_msg_fifo_almost_full (based upon FIFO watermark)" "0,1"
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bitfld.long 0x4 0. "CPU3_TO_CPU2_MSG_FIFO_LOCKED,cpu3_to_cpu2_msg_fifo_locked" "0,1"
group.long 0x1BF810++0x3
line.long 0x0 "CIU2_IMU_CPU3_CPU2_MSG_FIFO_CNTL,CPU3 to CPU2 message FIFO control"
hexmask.long.byte 0x0 20.--23. 1. "CPU3_CPU2_MSG_FIFO_FULL_WATERMARK,cpu3_to_cpu2 message fifo full watermark (space avail intr based upon it)"
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bitfld.long 0x0 17. "CPU3_WAIT_FOR_ACK,CPU3 wait for Acknowledgment" "0,1"
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bitfld.long 0x0 16. "CPU3_TO_CPU2_MSG_FIFO_FLUSH,Writing 1 to this bit will flush cpu3_to_cpu2 message fifo" "0,1"
newline
bitfld.long 0x0 8. "CPU3_MSG_SP_AV_INT_CLR,Writing 1 to this bit will clear message space available interrupt to CPU3 (self clear bit)" "0,1"
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bitfld.long 0x0 0. "CPU3_MSG_RDY_INT_CLR,Writing 1 to this bit will clear message ready interrupt to CPU3 (self clear bit)" "0,1"
rgroup.long 0x1BF814++0x3
line.long 0x0 "CIU2_IMU_CPU2_RD_MSG_FROM_CPU3_VAL_DBG,CPU2 last message read (from cpu3)"
hexmask.long 0x0 0.--31. 1. "CPU2_RD_MSG,CPU2 last message read (from cpu3)"
group.long 0x1BF818++0x3
line.long 0x0 "CIU2_IMU_CPU2_WR_MSG_TO_CPU3,CPU2 write message to CPU3"
hexmask.long 0x0 0.--31. 1. "CPU2_WR_MSG_CPU3,Write CPU2 message data to CPU3 (push to FIFO)"
rgroup.long 0x1BF81C++0x7
line.long 0x0 "CIU2_IMU_CPU2_RD_MSG_FROM_CPU3,CPU2 read message from CPU3"
hexmask.long 0x0 0.--31. 1. "CPU2_RD_MSG_CPU3,CPU2 read message data from CPU3 (pop from FIFO)"
line.long 0x4 "CIU2_IMU_CPU2_CPU3_MSG_FIFO_STATUS,CPU2 to CPU3 message FIFO status"
hexmask.long.byte 0x4 20.--23. 1. "CPU2_TO_CPU3_MSG_FIFO_RD_PTR,cpu3 to cpu2 msg fifo read pointer for debug"
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hexmask.long.byte 0x4 16.--19. 1. "CPU2_TO_CPU3_MSG_FIFO_WR_PTR,cpu3 to cpu2 msg fifo write pointer for debug"
newline
hexmask.long.byte 0x4 4.--8. 1. "CPU2_TO_CPU3_MSG_COUNT,cpu2_to_cpu3_msg_count"
newline
bitfld.long 0x4 3. "CPU2_TO_CPU3_MSG_FIFO_EMPTY,cpu2_to_cpu3_msg_fifo_empty" "0,1"
newline
bitfld.long 0x4 2. "CPU2_TO_CPU3_MSG_FIFO_FULL,cpu2_to_cpu3_msg_fifo_full (based upon FIFO depth)" "0,1"
newline
bitfld.long 0x4 1. "CPU2_TO_CPU3_MSG_FIFO_ALMOST_FULL,cpu2_to_cpu3_msg_fifo_almost_full (based upon FIFO watermark)" "0,1"
newline
bitfld.long 0x4 0. "CPU2_TO_CPU3_MSG_FIFO_LOCKED,cpu2_to_cpu3_msg_fifo_locked" "0,1"
group.long 0x1BF824++0x3
line.long 0x0 "CIU2_IMU_CPU2_CPU3_MSG_FIFO_CNTL,CPU2 to CPU3 message FIFO control"
hexmask.long.byte 0x0 20.--23. 1. "CPU2_CPU3_MSG_FIFO_FULL_WATERMARK,cpu2_to_cpu3 message fifo full watermark (space avail intr based upon it)"
newline
bitfld.long 0x0 17. "CPU2_WAIT_FOR_ACK,CPU2 wait for Acknowledgment" "0,1"
newline
bitfld.long 0x0 16. "CPU2_TO_CPU3_MSG_FIFO_FLUSH,Writing 1 to this bit will flush cpu2_to_cpu3 message fifo" "0,1"
newline
bitfld.long 0x0 8. "CPU2_MSG_SP_AV_INT_CLR,Writing 1 to this bit will clear message space available interrupt to CPU2 (self clear bit)" "0,1"
newline
bitfld.long 0x0 0. "CPU2_MSG_RDY_INT_CLR,Writing 1 to this bit will clear message ready interrupt to CPU2 (self clear bit)" "0,1"
rgroup.long 0x1BF828++0x3
line.long 0x0 "CIU2_IMU_CPU3_RD_MSG_FROM_CPU2_VAL_DBG,CPU3 last message read (from cpu2)"
hexmask.long 0x0 0.--31. 1. "CPU3_RD_MSG,CPU3 last message read (from cpu2)"
group.long 0x1BF82C++0xF
line.long 0x0 "CIU2_CPU3_WAKEUP_CTRL,CIU2 register to wakeup CPU3"
bitfld.long 0x0 0. "CPU3_WAKE_UP,CPU3 Wakeup Control Register. S/W Write 1 to generate a wake up interrupt to CPU3.Clear by S/W once mci_wl_wakeup_done[1] interrupt is received from CPU3." "0,1"
line.long 0x4 "CIU2_CPU2_WAKEUP_DONE,Wakeup done Control Register to CPU3"
hexmask.long.byte 0x4 0.--7. 1. "CPU2_WAKEUP_DONE,CPU2 Wakeup is done . This bit is set to 1 by S/W when CPU3 wakesup CPU2.This is self clearing bit. This generates an interrupt to CPU3 via wl_mci_wakeup_done[7:0] signal."
line.long 0x8 "CIU2_CPU3_NS_GP_INT,Non Secure region GP interrupt to CPU3"
bitfld.long 0x8 0.--1. "CPU2_CPU3_GP_NS_INT,General Purpose interrupt to CPU3 from non secure registers" "0,1,2,3"
line.long 0xC "CIU2_IMU_ECO_BITS,IMU ECO Control"
hexmask.long.word 0xC 0.--15. 1. "IMU_ECO_BITS,Reserved for ECOs"
tree.end
tree.end
tree "BUCK"
base ad:0x0
tree "BUCK11"
base ad:0x45002000
rgroup.byte 0x40++0x5
line.byte 0x0 "BUCK_BYPASS_SOC_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "BUCK_BYPASS_SOC_CTRL_ONE_RO,BUCK_BYPASS_SOC_CTRL_ONE_RO"
line.byte 0x1 "BUCK_BYPASS_SOC_CTRL_TWO_RO_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "BUCK_BYPASS_SOC_CTRL_TWO_RO,BUCK_BYPASS_SOC_CTRL_TWO_RO"
line.byte 0x2 "REG_RO_ONE_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "REG_RO_ONE,REG_RO_ONE"
line.byte 0x3 "REG_RO_TWO_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_RO_TWO,REG_RO_TWO"
line.byte 0x4 "REG_RO_THREE_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_RO_THREE,REG_RO_THREE"
line.byte 0x5 "REG_RO_FOUR_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "REG_RO_FOUR,REG_RO_FOUR"
group.byte 0x46++0x16
line.byte 0x0 "SYS_CTRL_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "REG_SYS_CTRL,REG_SYS_CTRL"
line.byte 0x1 "BUCK_BYPASS_SOC_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "REG_BUCK_BYPASS_SOC_CTRL_ONE_RW,REG_BUCK_BYPASS_SOC_CTRL_ONE_RW"
line.byte 0x2 "BUCK_BYPASS_SOC_CTRL_TWO_RW_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "REG_BUCK_BYPASS_SOC_CTRL_TWO_RW,REG_BUCK_BYPASS_SOC_CTRL_TWO_RW"
line.byte 0x3 "BUCK_CTRL_ONE_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_BUCK_CTRL_ONE,REG_BUCK_CTRL_ONE"
line.byte 0x4 "BUCK_CTRL_TWO_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_BUCK_CTRL_TWO,REG_BUCK_CTRL_TWO"
line.byte 0x5 "BUCK_CTRL_THREE_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "REG_BUCK_CTRL_THREE,REG_BUCK_CTRL_THREE"
line.byte 0x6 "BUCK_CTRL_FOUR_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "REG_BUCK_CTRL_FOUR,REG_BUCK_CTRL_FOUR"
line.byte 0x7 "BUCK_CTRL_FIVE_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "REG_BUCK_CTRL_FIVE,REG_BUCK_CTRL_FIVE"
line.byte 0x8 "BUCK_CTRL_SIX_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "REG_BUCK_CTRL_SIX,REG_BUCK_CTRL_SIX"
line.byte 0x9 "BUCK_CTRL_SEVEN_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "REG_BUCK_CTRL_SEVEN,REG_BUCK_CTRL_SEVEN"
line.byte 0xA "BUCK_CTRL_EIGHT_REG,no description available"
hexmask.byte 0xA 0.--7. 1. "REG_BUCK_CTRL_EIGHT,REG_BUCK_CTRL_EIGHT"
line.byte 0xB "BUCK_CTRL_NINE_REG,no description available"
hexmask.byte 0xB 0.--7. 1. "REG_BUCK_CTRL_NINE,REG_BUCK_CTRL_NINE"
line.byte 0xC "BUCK_CTRL_TEN_REG,no description available"
hexmask.byte 0xC 0.--7. 1. "REG_BUCK_CTRL_TEN,REG_BUCK_CTRL_TEN"
line.byte 0xD "BUCK_CTRL_ELEVEN_REG,no description available"
hexmask.byte 0xD 0.--7. 1. "REG_BUCK_CTRL_ELEVEN,REG_BUCK_CTRL_ELEVEN"
line.byte 0xE "BUCK_CTRL_TWELVE_REG,no description available"
hexmask.byte 0xE 0.--7. 1. "REG_BUCK_CTRL_TWELVE,REG_BUCK_CTRL_TWELVE"
line.byte 0xF "BUCK_CTRL_THIRTEEN_REG,no description available"
hexmask.byte 0xF 0.--7. 1. "REG_BUCK_CTRL_THIRTEEN,REG_BUCK_CTRL_THIRTEEN"
line.byte 0x10 "BUCK_CTRL_FOURTEEN_REG,no description available"
hexmask.byte 0x10 0.--7. 1. "REG_BUCK_CTRL_FOURTEEN,REG_BUCK_CTRL_FOURTEEN"
line.byte 0x11 "BUCK_CTRL_FIFTEEN_REG,no description available"
hexmask.byte 0x11 0.--7. 1. "REG_BUCK_CTRL_FIFTEEN,REG_BUCK_CTRL_FIFTEEN"
line.byte 0x12 "BUCK_CTRL_SIXTEEN_REG,no description available"
hexmask.byte 0x12 0.--7. 1. "REG_BUCK_CTRL_SIXTEEN,REG_BUCK_CTRL_SIXTEEN"
line.byte 0x13 "BUCK_CTRL_SEVENTEEN_REG,no description available"
hexmask.byte 0x13 0.--7. 1. "REG_BUCK_CTRL_SEVENTEEN,REG_BUCK_CTRL_SEVENTEEN"
line.byte 0x14 "BUCK_CTRL_EIGHTEEN_REG,no description available"
hexmask.byte 0x14 0.--7. 1. "REG_BUCK_CTRL_EIGHTEEN,REG_BUCK_CTRL_EIGHTEEN"
line.byte 0x15 "BUCK_CTRL_NINTEEN_REG,no description available"
hexmask.byte 0x15 0.--7. 1. "REG_BUCK_CTRL_NINTEEN,REG_BUCK_CTRL_NINTEEN"
line.byte 0x16 "BUCK_CTRL_TWENTY_REG,no description available"
hexmask.byte 0x16 0.--7. 1. "REG_BUCK_CTRL_TWENTY,REG_BUCK_CTRL_TWENTY"
tree.end
tree "BUCK18"
base ad:0x45002000
rgroup.byte 0x60++0x5
line.byte 0x0 "BUCK_BYPASS_SOC_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "BUCK_BYPASS_SOC_CTRL_ONE_RO,BUCK_BYPASS_SOC_CTRL_ONE_RO"
line.byte 0x1 "BUCK_BYPASS_SOC_CTRL_TWO_RO_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "BUCK_BYPASS_SOC_CTRL_TWO_RO,BUCK_BYPASS_SOC_CTRL_TWO_RO"
line.byte 0x2 "REG_RO_ONE_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "REG_RO_ONE,REG_RO_ONE"
line.byte 0x3 "REG_RO_TWO_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_RO_TWO,REG_RO_TWO"
line.byte 0x4 "REG_RO_THREE_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_RO_THREE,REG_RO_THREE"
line.byte 0x5 "REG_RO_FOUR_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "REG_RO_FOUR,REG_RO_FOUR"
group.byte 0x66++0x16
line.byte 0x0 "SYS_CTRL_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "REG_SYS_CTRL,REG_SYS_CTRL"
line.byte 0x1 "BUCK_BYPASS_SOC_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "REG_BUCK_BYPASS_SOC_CTRL_ONE_RW,REG_BUCK_BYPASS_SOC_CTRL_ONE_RW"
line.byte 0x2 "BUCK_BYPASS_SOC_CTRL_TWO_RW_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "REG_BUCK_BYPASS_SOC_CTRL_TWO_RW,REG_BUCK_BYPASS_SOC_CTRL_TWO_RW"
line.byte 0x3 "BUCK_CTRL_ONE_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_BUCK_CTRL_ONE,REG_BUCK_CTRL_ONE"
line.byte 0x4 "BUCK_CTRL_TWO_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_BUCK_CTRL_TWO,REG_BUCK_CTRL_TWO"
line.byte 0x5 "BUCK_CTRL_THREE_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "REG_BUCK_CTRL_THREE,REG_BUCK_CTRL_THREE"
line.byte 0x6 "BUCK_CTRL_FOUR_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "REG_BUCK_CTRL_FOUR,REG_BUCK_CTRL_FOUR"
line.byte 0x7 "BUCK_CTRL_FIVE_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "REG_BUCK_CTRL_FIVE,REG_BUCK_CTRL_FIVE"
line.byte 0x8 "BUCK_CTRL_SIX_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "REG_BUCK_CTRL_SIX,REG_BUCK_CTRL_SIX"
line.byte 0x9 "BUCK_CTRL_SEVEN_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "REG_BUCK_CTRL_SEVEN,REG_BUCK_CTRL_SEVEN"
line.byte 0xA "BUCK_CTRL_EIGHT_REG,no description available"
hexmask.byte 0xA 0.--7. 1. "REG_BUCK_CTRL_EIGHT,REG_BUCK_CTRL_EIGHT"
line.byte 0xB "BUCK_CTRL_NINE_REG,no description available"
hexmask.byte 0xB 0.--7. 1. "REG_BUCK_CTRL_NINE,REG_BUCK_CTRL_NINE"
line.byte 0xC "BUCK_CTRL_TEN_REG,no description available"
hexmask.byte 0xC 0.--7. 1. "REG_BUCK_CTRL_TEN,REG_BUCK_CTRL_TEN"
line.byte 0xD "BUCK_CTRL_ELEVEN_REG,no description available"
hexmask.byte 0xD 0.--7. 1. "REG_BUCK_CTRL_ELEVEN,REG_BUCK_CTRL_ELEVEN"
line.byte 0xE "BUCK_CTRL_TWELVE_REG,no description available"
hexmask.byte 0xE 0.--7. 1. "REG_BUCK_CTRL_TWELVE,REG_BUCK_CTRL_TWELVE"
line.byte 0xF "BUCK_CTRL_THIRTEEN_REG,no description available"
hexmask.byte 0xF 0.--7. 1. "REG_BUCK_CTRL_THIRTEEN,REG_BUCK_CTRL_THIRTEEN"
line.byte 0x10 "BUCK_CTRL_FOURTEEN_REG,no description available"
hexmask.byte 0x10 0.--7. 1. "REG_BUCK_CTRL_FOURTEEN,REG_BUCK_CTRL_FOURTEEN"
line.byte 0x11 "BUCK_CTRL_FIFTEEN_REG,no description available"
hexmask.byte 0x11 0.--7. 1. "REG_BUCK_CTRL_FIFTEEN,REG_BUCK_CTRL_FIFTEEN"
line.byte 0x12 "BUCK_CTRL_SIXTEEN_REG,no description available"
hexmask.byte 0x12 0.--7. 1. "REG_BUCK_CTRL_SIXTEEN,REG_BUCK_CTRL_SIXTEEN"
line.byte 0x13 "BUCK_CTRL_SEVENTEEN_REG,no description available"
hexmask.byte 0x13 0.--7. 1. "REG_BUCK_CTRL_SEVENTEEN,REG_BUCK_CTRL_SEVENTEEN"
line.byte 0x14 "BUCK_CTRL_EIGHTEEN_REG,no description available"
hexmask.byte 0x14 0.--7. 1. "REG_BUCK_CTRL_EIGHTEEN,REG_BUCK_CTRL_EIGHTEEN"
line.byte 0x15 "BUCK_CTRL_NINTEEN_REG,no description available"
hexmask.byte 0x15 0.--7. 1. "REG_BUCK_CTRL_NINTEEN,REG_BUCK_CTRL_NINTEEN"
line.byte 0x16 "BUCK_CTRL_TWENTY_REG,no description available"
hexmask.byte 0x16 0.--7. 1. "REG_BUCK_CTRL_TWENTY,REG_BUCK_CTRL_TWENTY"
tree.end
tree.end
tree "CACHE64_POLSEL"
base ad:0x0
tree "CACHE64_POLSEL0"
base ad:0x40033000
group.long 0x14++0xB
line.long 0x0 "REG0_TOP,Region 0 Top Boundary"
hexmask.long.tbyte 0x0 10.--26. 1. "REG0_TOP,Upper limit of Region 0"
line.long 0x4 "REG1_TOP,Region 1 Top Boundary"
hexmask.long.tbyte 0x4 10.--26. 1. "REG1_TOP,Upper limit of Region 1"
line.long 0x8 "POLSEL,Policy Select"
bitfld.long 0x8 4.--5. "REG02_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: Invalid"
bitfld.long 0x8 2.--3. "REG1_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: Invalid"
bitfld.long 0x8 0.--1. "REG0_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: Invalid"
tree.end
tree "CACHE64_POLSEL1"
base ad:0x40034000
group.long 0x14++0xB
line.long 0x0 "REG0_TOP,Region 0 Top Boundary"
hexmask.long.tbyte 0x0 10.--26. 1. "REG0_TOP,Upper limit of Region 0"
line.long 0x4 "REG1_TOP,Region 1 Top Boundary"
hexmask.long.tbyte 0x4 10.--26. 1. "REG1_TOP,Upper limit of Region 1"
line.long 0x8 "POLSEL,Policy Select"
bitfld.long 0x8 4.--5. "REG02_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: Invalid"
bitfld.long 0x8 2.--3. "REG1_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: Invalid"
bitfld.long 0x8 0.--1. "REG0_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: Invalid"
tree.end
tree.end
tree "CAU_TOP (Cryptographic Acceleration Unit)"
base ad:0x45002000
rgroup.byte 0x0++0x9
line.byte 0x0 "BYPASS_SOC_PD_CTRL_RO_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "BYPASS_SOC_PD_CTRL_RO,BYPASS_SOC_PD_CTRL_RO"
line.byte 0x1 "BYPASS_SOC_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "BYPASS_SOC_CTRL_ONE_RO,BYPASS_SOC_CTRL_ONE_RO"
line.byte 0x2 "BYPASS_SOC_CTRL_TWO_RO_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "BYPASS_SOC_CTRL_TWO_RO,BYPASS_SOC_CTRL_TWO_RO"
line.byte 0x3 "BYPASS_RFU_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "BYPASS_RFU_CTRL_ONE_RO,BYPASS_RFU_CTRL_ONE_RO"
line.byte 0x4 "REG_RO_ONE_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_RO_ONE,REG_RO_ONE"
line.byte 0x5 "REG_RO_TWO_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "REG_RO_TWO,REG_RO_TWO"
line.byte 0x6 "REG_RO_THREE_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "REG_RO_THREE,REG_RO_THREE"
line.byte 0x7 "REG_RO_FOUR_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "REG_RO_FOUR,REG_RO_FOUR"
line.byte 0x8 "REG_RO_FIVE_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "REG_RO_FIVE,REG_RO_FIVE"
line.byte 0x9 "REG_RO_SIX_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "REG_RO_SIX,REG_RO_SIX"
group.byte 0xA++0x32
line.byte 0x0 "SW_RESET_B_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "SW_RESET_B,SW_RESET_B"
line.byte 0x1 "SYS_CTRL_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "SYS_CTRL,SYS_CTRL"
line.byte 0x2 "SYS_CTRL_PWR_OPT_SEL_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "SYS_CTRL_PWR_OPT_SEL,SYS_CTRL_PWR_OPT_SEL"
line.byte 0x3 "BYPASS_SOC_PD_CTRL_RW_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "BYPASS_SOC_PD_CTRL_RW,BYPASS_SOC_PD_CTRL_RW"
line.byte 0x4 "BYPASS_SOC_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "BYPASS_SOC_CTRL_ONE_RW,BYPASS_SOC_CTRL_ONE_RW"
line.byte 0x5 "BYPASS_SOC_CTRL_TWO_RW_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "BYPASS_SOC_CTRL_TWO_RW,BYPASS_SOC_CTRL_TWO_RW"
line.byte 0x6 "BYPASS_RFU_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "BYPASS_RFU_CTRL_ONE_RW,BYPASS_RFU_CTRL_ONE_RW"
line.byte 0x7 "PD_CTRL_ONE_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "PD_CTRL_ONE,PD_CTRL_ONE"
line.byte 0x8 "PD_CTRL_TWO_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "PD_CTRL_TWO,PD_CTRL_TWO"
line.byte 0x9 "SLP_CTRL_ONE_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "SLP_CTRL_ONE,SLP_CTRL_ONE"
line.byte 0xA "SLP_CTRL_TWO_REG,no description available"
hexmask.byte 0xA 0.--7. 1. "SLP_CTRL_TWO,SLP_CTRL_TWO"
line.byte 0xB "BG_CTRL_REG,no description available"
hexmask.byte 0xB 0.--7. 1. "BG_CTRL,BG_CTRL"
line.byte 0xC "CPREG_CTRL_ONE_REG,no description available"
hexmask.byte 0xC 0.--7. 1. "CPREG_CTRL_ONE,CPREG_CTRL_ONE"
line.byte 0xD "CPREG_CTRL_TWO_REG,no description available"
hexmask.byte 0xD 0.--7. 1. "CPREG_CTRL_TWO,CPREG_CTRL_TWO"
line.byte 0xE "CPREG_CTRL_THREE_REG,no description available"
hexmask.byte 0xE 0.--7. 1. "CPREG_CTRL_THREE,CPREG_CTRL_THREE"
line.byte 0xF "PSEN_CTRL_ONE_REG,no description available"
hexmask.byte 0xF 0.--7. 1. "PSEN_CTRL_ONE,PSEN_CTRL_ONE"
line.byte 0x10 "PSEN_CTRL_TWO_REG,no description available"
hexmask.byte 0x10 0.--7. 1. "PSEN_CTRL_TWO,PSEN_CTRL_TWO"
line.byte 0x11 "TSEN_CTRL_ONE_REG,no description available"
hexmask.byte 0x11 0.--7. 1. "TSEN_CTRL_ONE,TSEN_CTRL_ONE"
line.byte 0x12 "TSEN_CTRL_THREE_REG,no description available"
hexmask.byte 0x12 0.--7. 1. "TSEN_CTRL_TWO,TSEN_CTRL_TWO"
line.byte 0x13 "ADC_CTRL_ONE_REG,no description available"
hexmask.byte 0x13 0.--7. 1. "ADC_CTRL,ADC_CTRL"
line.byte 0x14 "RCAL_CTRL_ONE_REG,no description available"
hexmask.byte 0x14 0.--7. 1. "RCAL_CTRL_ONE,RCAL_CTRL_ONE"
line.byte 0x15 "RCAL_CTRL_TWO_REG,no description available"
hexmask.byte 0x15 0.--7. 1. "RCAL_CTRL_TWO,RCAL_CTRL_TWO"
line.byte 0x16 "XTAL_CTRL_ONE_REG,no description available"
hexmask.byte 0x16 0.--7. 1. "XTAL_CTRL_ONE,XTAL_CTRL_ONE"
line.byte 0x17 "XTAL_CTRL_TWO_REG,no description available"
hexmask.byte 0x17 0.--7. 1. "XTAL_CTRL_TWO,XTAL_CTRL_TWO"
line.byte 0x18 "XTAL_CTRL_THREE_REG,no description available"
hexmask.byte 0x18 0.--7. 1. "XTAL_CTRL_THREE,XTAL_CTRL_THREE"
line.byte 0x19 "XTAL_CTRL_FOUR_REG,no description available"
hexmask.byte 0x19 0.--7. 1. "XTAL_CTRL_FOUR,XTAL_CTRL_FOUR"
line.byte 0x1A "XTAL_CTRL_FIVE_REG,no description available"
hexmask.byte 0x1A 0.--7. 1. "XTAL_CTRL_FIVE,XTAL_CTRL_FIVE"
line.byte 0x1B "XTAL_CTRL_SIX_REG,no description available"
hexmask.byte 0x1B 0.--7. 1. "XTAL_CTRL_SIX,XTAL_CTRL_SIX"
line.byte 0x1C "XTAL_CTRL_SEVEN_REG,no description available"
hexmask.byte 0x1C 0.--7. 1. "XTAL_CTRL_SEVEN,XTAL_CTRL_SEVEN"
line.byte 0x1D "XTAL_CTRL_EIGHT_REG,no description available"
hexmask.byte 0x1D 0.--7. 1. "XTAL_CTRL_EIGHT,XTAL_CTRL_EIGHT"
line.byte 0x1E "XTAL_CTRL_NINE_REG,no description available"
hexmask.byte 0x1E 0.--7. 1. "XTAL_CTRL_NINE,XTAL_CTRL_NINE"
line.byte 0x1F "XTAL_CTRL_TEN_REG,no description available"
hexmask.byte 0x1F 0.--7. 1. "XTAL_CTRL_TEN,XTAL_CTRL_TEN"
line.byte 0x20 "XTAL_CTRL_ELEVEN_REG,no description available"
hexmask.byte 0x20 0.--7. 1. "XTAL_CTRL_ELEVEN,XTAL_CTRL_ELEVEN"
line.byte 0x21 "XTAL_CTRL_TWELVE_REG,no description available"
hexmask.byte 0x21 0.--7. 1. "XTAL_CTRL_TWELVE,XTAL_CTRL_TWELVE"
line.byte 0x22 "XTAL_CTRL_THIRTEEN_REG,no description available"
hexmask.byte 0x22 0.--7. 1. "XTAL_CTRL_THIRTEEN,XTAL_CTRL_THIRTEEN"
line.byte 0x23 "XTAL_CTRL_FOURTEEN_REG,no description available"
hexmask.byte 0x23 0.--7. 1. "XTAL_CTRL_FOURTEEN,XTAL_CTRL_FOURTEEN"
line.byte 0x24 "XTAL_CTRL_FIFTEEN_REG,no description available"
hexmask.byte 0x24 0.--7. 1. "XTAL_CTRL_FIFTEEN,XTAL_CTRL_FIFTEEN"
line.byte 0x25 "T1_CTRL_RSVD_HI_REG,no description available"
hexmask.byte 0x25 0.--7. 1. "XTAL_CTRL_RSVD_HI,XTAL_CTRL_RSVD_HI"
line.byte 0x26 "T1_CTRL_RSVD_LO_REG,no description available"
hexmask.byte 0x26 0.--7. 1. "XTAL_CTRL_RSVD_LO,XTAL_CTRL_RSVD_LO"
line.byte 0x27 "GPIO_CTRL_REG,no description available"
hexmask.byte 0x27 0.--7. 1. "GPIO_CTRL,GPIO_CTRL"
line.byte 0x28 "ATEST_CTRL_ONE_REG,no description available"
hexmask.byte 0x28 0.--7. 1. "ATEST_CTRL_ONE,ATEST_CTRL_ONE"
line.byte 0x29 "ATEST_CTRL_TWO_REG,no description available"
hexmask.byte 0x29 0.--7. 1. "ATEST_CTRL_TWO,ATEST_CTRL_TWO"
line.byte 0x2A "ATEST_CTRL_THREE_REG,no description available"
hexmask.byte 0x2A 0.--7. 1. "ATEST_CTRL_THREE,ATEST_CTRL_THREE"
line.byte 0x2B "ATEST_CTRL_FOUR_REG,no description available"
hexmask.byte 0x2B 0.--7. 1. "ATEST_CTRL_FOUR,ATEST_CTRL_FOUR"
line.byte 0x2C "ATEST_CTRL_FIVE_REG,no description available"
hexmask.byte 0x2C 0.--7. 1. "ATEST_CTRL_FIVE,ATEST_CTRL_FIVE"
line.byte 0x2D "ATEST_CTRL_SIX_REG,no description available"
hexmask.byte 0x2D 0.--7. 1. "ATEST_CTRL_SIX,ATEST_CTRL_SIX"
line.byte 0x2E "ATEST_CTRL_SEVEN_REG,no description available"
hexmask.byte 0x2E 0.--7. 1. "ATEST_CTRL_SEVEN,ATEST_CTRL_SEVEN"
line.byte 0x2F "RESERVED_LO_ONE_REG,no description available"
hexmask.byte 0x2F 0.--7. 1. "RESERVED_LO_ONE,RESERVED_LO_ONE"
line.byte 0x30 "RESERVED_LO_TWO_REG,no description available"
hexmask.byte 0x30 0.--7. 1. "RESERVED_LO_TWO,RESERVED_LO_TWO"
line.byte 0x31 "RESERVED_HI_ONE_REG,no description available"
hexmask.byte 0x31 0.--7. 1. "RESERVED_HI_ONE,RESERVED_HI_ONE"
line.byte 0x32 "RESERVED_HI_TWO_REG,no description available"
hexmask.byte 0x32 0.--7. 1. "RESERVED_HI_TWO,RESERVED_HI_TWO"
tree.end
tree "CDOG (Code Watchdog Timer)"
base ad:0x4014C000
group.long 0x0++0xF
line.long 0x0 "CONTROL,Control"
bitfld.long 0x0 30.--31. "DEBUG_HALT_CTRL,DEBUG_HALT control" "?,1: Keep the timer running,2: Stop the timer,?"
bitfld.long 0x0 28.--29. "IRQ_PAUSE,IRQ pause control" "?,1: Keep the timer running,2: Stop the timer,?"
newline
bitfld.long 0x0 17.--19. "ADDRESS_CTRL,ADDRESS fault control" "?,1: Enable reset,2: Enable interrupt,?,4: Disable both reset and interrupt,?,?,?"
bitfld.long 0x0 14.--16. "STATE_CTRL,STATE fault control" "?,1: Enable reset,2: Enable interrupt,?,4: Disable both reset and interrupt,?,?,?"
newline
bitfld.long 0x0 11.--13. "CONTROL_CTRL,CONTROL fault control" "?,1: Enable reset,?,?,4: Disable reset,?,?,?"
bitfld.long 0x0 8.--10. "SEQUENCE_CTRL,SEQUENCE fault control" "?,1: Enable reset,2: Enable interrupt,?,4: Disable both reset and interrupt,?,?,?"
newline
bitfld.long 0x0 5.--7. "MISCOMPARE_CTRL,MISCOMPARE fault control" "?,1: Enable reset,2: Enable interrupt,?,4: Disable both reset and interrupt,?,?,?"
bitfld.long 0x0 2.--4. "TIMEOUT_CTRL,TIMEOUT fault control" "?,1: Enable reset,2: Enable interrupt,?,4: Disable both reset and interrupt,?,?,?"
newline
bitfld.long 0x0 0.--1. "LOCK_CTRL,Lock control" "?,1: Locked,2: Unlocked,?"
line.long 0x4 "RELOAD,Instruction Timer reload"
hexmask.long 0x4 0.--31. 1. "RLOAD,Instruction Timer reload value"
line.long 0x8 "INSTRUCTION_TIMER,Instruction Timer"
hexmask.long 0x8 0.--31. 1. "INSTIM,Current value of the Instruction Timer"
line.long 0xC "SECURE_COUNTER,Secure Counter"
hexmask.long 0xC 0.--31. 1. "SECCNT,Secure Counter"
rgroup.long 0x10++0x7
line.long 0x0 "STATUS,Status 1"
hexmask.long.byte 0x0 24.--27. 1. "CURST,Current State"
hexmask.long.byte 0x0 16.--23. 1. "NUMILSEQF,Number of SEQUENCE faults since the last POR"
newline
hexmask.long.byte 0x0 8.--15. 1. "NUMMISCOMPF,Number of MISCOMPARE faults since the last POR"
hexmask.long.byte 0x0 0.--7. 1. "NUMTOF,Number of TIMEOUT faults since the last POR"
line.long 0x4 "STATUS2,Status 2"
hexmask.long.byte 0x4 16.--23. 1. "NUMILLA,Number of ADDRESS faults since the last POR"
hexmask.long.byte 0x4 8.--15. 1. "NUMILLSTF,Number of STATE faults since the last POR"
newline
hexmask.long.byte 0x4 0.--7. 1. "NUMCNTF,Number of CONTROL faults since the last POR"
group.long 0x18++0x7
line.long 0x0 "FLAGS,Flags"
bitfld.long 0x0 16. "POR_FLAG,Power-on reset flag" "0: A Power-on reset event has not occurred,1: A Power-on reset event has occurred"
bitfld.long 0x0 5. "ADDR_FLAG,ADDRESS fault flag" "0: An ADDRESS fault has not occurred,1: An ADDRESS fault has occurred"
newline
bitfld.long 0x0 4. "STATE_FLAG,STATE fault flag" "0: A STATE fault has not occurred,1: A STATE fault has occurred"
bitfld.long 0x0 3. "CNT_FLAG,CONTROL fault flag" "0: A CONTROL fault has not occurred,1: A CONTROL fault has occurred"
newline
bitfld.long 0x0 2. "SEQ_FLAG,SEQUENCE fault flag" "0: A SEQUENCE fault has not occurred,1: A SEQUENCE fault has occurred"
bitfld.long 0x0 1. "MISCOM_FLAG,MISCOMPARE fault flag" "0: A MISCOMPARE fault has not occurred,1: A MISCOMPARE fault has occurred"
newline
bitfld.long 0x0 0. "TO_FLAG,TIMEOUT fault flag" "0: A TIMEOUT fault has not occurred,1: A TIMEOUT fault has occurred"
line.long 0x4 "PERSISTENT,Persistent Data Storage"
hexmask.long 0x4 0.--31. 1. "PERSIS,Persistent Storage"
wgroup.long 0x20++0x2B
line.long 0x0 "START,START Command"
hexmask.long 0x0 0.--31. 1. "STRT,Start command"
line.long 0x4 "STOP,STOP Command"
hexmask.long 0x4 0.--31. 1. "STP,Stop command"
line.long 0x8 "RESTART,RESTART Command"
hexmask.long 0x8 0.--31. 1. "RSTRT,Restart command"
line.long 0xC "ADD,ADD Command"
hexmask.long 0xC 0.--31. 1. "AD,ADD Write Value"
line.long 0x10 "ADD1,ADD1 Command"
hexmask.long 0x10 0.--31. 1. "AD1,ADD 1"
line.long 0x14 "ADD16,ADD16 Command"
hexmask.long 0x14 0.--31. 1. "AD16,ADD 16"
line.long 0x18 "ADD256,ADD256 Command"
hexmask.long 0x18 0.--31. 1. "AD256,ADD 256"
line.long 0x1C "SUB,SUB Command"
hexmask.long 0x1C 0.--31. 1. "S0B,Subtract Write Value"
line.long 0x20 "SUB1,SUB1 Command"
hexmask.long 0x20 0.--31. 1. "S1B,Subtract 1"
line.long 0x24 "SUB16,SUB16 Command"
hexmask.long 0x24 0.--31. 1. "SB16,Subtract 16"
line.long 0x28 "SUB256,SUB256 Command"
hexmask.long 0x28 0.--31. 1. "SB256,Subtract 256"
tree.end
tree "CLKCTL"
base ad:0x0
tree "CLKCTL0"
base ad:0x40001000
group.long 0x10++0xB
line.long 0x0 "PSCCTL0,clock control 0"
bitfld.long 0x0 31. "SDIO,sdio clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 30. "DMA1,dma1 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 29. "DMA0,dma0 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 28. "GDMA,gdma clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 25. "AON_MEM,aon_mem clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 24. "SCT,sct clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 22. "USB,usb clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 20. "HPU,hpu clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 16. "FLEXSPI0,flexspi0 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 11. "PUF,puf clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 10. "CSS,css clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 9. "PKC,pkc clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 8. "PQ,pq clock control" "0: Disable clock,1: Enable clock"
line.long 0x4 "PSCCTL1,clock control 1"
bitfld.long 0x4 27. "TRNG,trng clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x4 26. "ENET_IPG_S,enet_ipg_s clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x4 25. "ENET_IPG,enet_ipg clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x4 24. "SECURE_GPIO,secure_gpio clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x4 17. "OTP,otp clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x4 16. "GAU,gau clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x4 2. "SDIO_SLV,sdio_slv clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x4 0. "CSS_APB,css_apb clock control" "0: Disable clock,1: Enable clock"
line.long 0x8 "PSCCTL2,clock control 2"
bitfld.long 0x8 31. "AON_DOMAIN_TEST_MON,aon_domain_test_mon clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 30. "C0_DOMAIN_TEST_MON,c0_domain_test_mon clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 27. "LCDIC,lcdic clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 26. "FREEMRT,freemrt clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 3. "ITRC,itrc clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 2. "USIM,usim clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 1. "WWDT0,wwdt0 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 0. "UTICK,utick clock control" "0: Disable clock,1: Enable clock"
wgroup.long 0x40++0xB
line.long 0x0 "PSCCTL0_SET,Peripheral clock set 0"
bitfld.long 0x0 31. "SDIO,sdio clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 30. "DMA1,dma1 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 29. "DMA0,dma0 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 28. "GDMA,gdma clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 25. "AON_MEM,aon_mem clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 24. "SCT,sct clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 22. "USB,usb clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 20. "HPU,hpu clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 16. "FLEXSPI0,flexspi0 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 11. "PUF,puf clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 10. "CSS,css clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 9. "PKC,pkc clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 8. "PQ,pq clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
line.long 0x4 "PSCCTL1_SET,Peripheral clock set 1"
bitfld.long 0x4 27. "TRNG,trng clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
bitfld.long 0x4 26. "ENET_IPG_S,enet_ipg_s clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
newline
bitfld.long 0x4 25. "ENET_IPG,enet_ipg clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
bitfld.long 0x4 24. "SECURE_GPIO,secure_gpio clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
newline
bitfld.long 0x4 17. "OTP,otp clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x4 16. "GAU,gau clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
newline
bitfld.long 0x4 2. "SDIO_SLV,sdio_slv clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
bitfld.long 0x4 0. "CSS_APB,css_apb clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
line.long 0x8 "PSCCTL2_SET,Peripheral clock set 2"
bitfld.long 0x8 31. "AON_DOMAIN_TEST_MON,aon_domain_test_mon clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 30. "C0_DOMAIN_TEST_MON,c0_domain_test_mon clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 27. "LCDIC,lcdic clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 26. "FREEMRT,freemrt clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 3. "ITRC,itrc clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 2. "USIM,usim clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 1. "WWDT0,wwdt0 clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 0. "UTICK,utick clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
wgroup.long 0x70++0xB
line.long 0x0 "PSCCTL0_CLR,Peripheral clock clear 0"
bitfld.long 0x0 31. "SDIO,sdio clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 30. "DMA1,dma1 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 29. "DMA0,dma0 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 28. "GDMA,gdma clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 25. "AON_MEM,aon_mem clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 24. "SCT,sct clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 22. "USB,usb clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 20. "HPU,hpu clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 16. "FLEXSPI0,flexspi0 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 11. "PUF,puf clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 10. "CSS,css clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 9. "PKC,pkc clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 8. "PQ,pq clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
line.long 0x4 "PSCCTL1_CLR,Peripheral clock clear 1"
bitfld.long 0x4 27. "TRNG,trng clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
bitfld.long 0x4 26. "ENET_IPG_S,enet_ipg_s clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
newline
bitfld.long 0x4 25. "ENET_IPG,enet_ipg clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
bitfld.long 0x4 24. "SECURE_GPIO,secure_gpio clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
newline
bitfld.long 0x4 17. "OTP,otp clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x4 16. "GAU,gau clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
newline
bitfld.long 0x4 2. "SDIO_SLV,sdio_slv clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
bitfld.long 0x4 0. "CSS_APB,css_apb clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
line.long 0x8 "PSCCTL2_CLR,Peripheral clock clear 2"
bitfld.long 0x8 31. "AON_DOMAIN_TEST_MON,aon_domain_test_mon clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 30. "C0_DOMAIN_TEST_MON,c0_domain_test_mon clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 27. "LCDIC,lcdic clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 26. "FREEMRT,freemrt clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 3. "ITRC,itrc clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 2. "USIM,usim clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 1. "WWDT0,wwdt0 clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 0. "UTICK,utick clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
group.long 0x168++0x3
line.long 0x0 "SYSOSCBYPASS,System oscillator bypass"
bitfld.long 0x0 0.--2. "SEL,External clock source selection" "0: Output of the external crystal oscillator,1: External clock input (CLKIN function from a pin..,?,?,?,?,?,7: NONE.this may be selected in order to reduce.."
group.long 0x1C0++0x3
line.long 0x0 "CLK32KHZCTL0,32k control 0"
bitfld.long 0x0 0. "ENA_32KHZ,32 kHz Enable" "0: Disable,1: Enable"
group.long 0x240++0x3
line.long 0x0 "MAINPLLCLKDIV,Main PLL clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x248++0x7
line.long 0x0 "AUX0PLLCLKDIV,AUX0 PLL clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0x4 "AUX1PLLCLKDIV,AUX1 PLL clock divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x400++0x3
line.long 0x0 "SYSCPUAHBCLKDIV,System CPU AHB clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x430++0x7
line.long 0x0 "MAINCLKSELA,Main clock selection A"
bitfld.long 0x0 0.--1. "SEL,Control Main 1st Stage Control Clock Source" "0: External clock (clk_in) or REFCLK_SYS,1: FFRO Clock (48/60m_irc) divided by 4,2: 1m_lposc,3: FFRO Clock"
line.long 0x4 "MAINCLKSELB,Main clock selection B"
bitfld.long 0x4 0.--1. "SEL,Control Main 2nd Stage Control Clock Source" "0: MAINCLKSELA 1st Stage Clock,1: SFRO Clock,2: Main PLL Clock (main_pll_clk).,3: 32 kHz Clock"
group.long 0x620++0x7
line.long 0x0 "FLEXSPIFCLKSEL,FlexSPI FCLK selection"
bitfld.long 0x0 0.--2. "SEL,FlexSPI Functional Clock Source Selection" "0: Main Clock,1: t3pll_mci_flexspi_clk(365M),2: AUX0 PLL clock (aux0_pll_clk).,3: tcpu_mci_flexspi_clk(373M),4: AUX1 PLL clock (aux1_pll_clk).,5: tddr_mci_flexspi_clk(320/355/400M),6: t3pll_mci_256m,7: None this may be selected in order to reduce.."
line.long 0x4 "FLEXSPIFCLKDIV,FlexSPI FCLK divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x640++0x7
line.long 0x0 "SCTFCLKSEL,SCT FCLK selection"
bitfld.long 0x0 0.--2. "SEL,SCT Functional Clock Source Selection" "0: Main Clock,1: Main PLL Clock (main_pll_clk).,2: AUX0 PLL clock (aux0_pll_clk).,3: FFRO Clock (48/60m_irc).,4: AUX1 PLL clock (aux1_pll_clk).,5: Audio PLL Clock (audio_pll_clk).,?,7: None this may be selected in order to reduce.."
line.long 0x4 "SCTFCLKDIV,SCT FCLK divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x700++0x3
line.long 0x0 "UTICKFCLKSEL,UTICK FCLK selection"
bitfld.long 0x0 0.--2. "SEL,UTICK Functional Clock Source Selection" "0: 1m_lposc,1: Main Clock,?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x720++0x3
line.long 0x0 "WDT0FCLKSEL,WDT clock selection"
bitfld.long 0x0 0.--2. "SEL,WDT0 Functional Clock Source Selection" "0: 1m_lposc,1: Main Clock,?,?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x760++0x23
line.long 0x0 "SYSTICKFCLKSEL,System tick FCLK selection"
bitfld.long 0x0 0.--2. "SEL,SYSTICK Functional Clock Source Selection" "0: Systick Divider Output Clock,1: 1m_lposc,2: 32 kHz Clock,3: SFRO Clock (16m_irc).,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "SYSTICKFCLKDIV,System tick FCLK divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0x8 "LCDFCLKDIV,Lcd FCLK divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0xC "GAUFCLKDIV,Gau FCLK divider"
bitfld.long 0xC 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0xC 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0xC 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0x10 "USIMFCLKDIV,Usim FCLK divider"
bitfld.long 0x10 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x10 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x10 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0x14 "USIMFCLKSEL,USIM FCLK selection"
bitfld.long 0x14 0.--2. "SEL,USIM Functional Clock Source Selection" "0: Main Clock,1: Audio PLL Clock (audio_pll_clk).,2: FFRO clock,?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x18 "LCDFCLKSEL,LCD FCLK selection"
bitfld.long 0x18 0.--2. "SEL,LCD Functional Clock Source Selection" "0: Main Clock,1: t3pll_mci_flexspi_clk,2: tcpu_mci_flexspi_clk,3: tddr_mci_flexspi_clk,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x1C "GAUFCLKSEL,GAU FCLK selection"
bitfld.long 0x1C 0.--1. "SEL,GAU Functional Clock Source Selection" "0: Main Clock,1: t3pll_mci_256m,2: avpll_ch2_CLKOUT--64MHz,3: None this may be selected in order to reduce.."
line.long 0x20 "PMUFCLKDIV,Pmu FCLK divider"
bitfld.long 0x20 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x20 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x20 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x790++0x3
line.long 0x0 "BRG_CLK_EN,wl/ble/soc bridge clock enable signal"
bitfld.long 0x0 2. "SOC,1:enable clock running 0:disable clock gated" "0: disable,1: enable"
bitfld.long 0x0 1. "BLE,1:enable clock running 0:disable clock gated" "0: disable,1: enable"
newline
bitfld.long 0x0 0. "WL,1:enable clock running 0:disable clock gated" "0: disable,1: enable"
group.long 0x7A0++0xB
line.long 0x0 "G2BIST_CLK_EN,g2bist clock enable signal"
bitfld.long 0x0 0. "VALUE,1:enable g2bist_clk running 0:disable g2bist_clk gated" "0: disable,1: enable"
line.long 0x4 "MAIN_RAM_CLK_EN,main ram clock enable signal"
bitfld.long 0x4 18. "ARRAY18,1:enable main ram array18 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 17. "ARRAY17,1:enable main ram array17 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 16. "ARRAY16,1:enable main ram array16 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 15. "ARRAY15,1:enable main ram array15 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 14. "ARRAY14,1:enable main ram array14 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 13. "ARRAY13,1:enable main ram array13 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 12. "ARRAY12,1:enable main ram array12 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 11. "ARRAY11,1:enable main ram array11 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 10. "ARRAY10,1:enable main ram array10 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 9. "ARRAY9,1:enable main ram array9 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 8. "ARRAY8,1:enable main ram array8 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 7. "ARRAY7,1:enable main ram array7 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 6. "ARRAY6,1:enable main ram array6 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 5. "ARRAY5,1:enable main ram array5 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 4. "ARRAY4,1:enable main ram array4 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 3. "ARRAY3,1:enable main ram array3 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 2. "ARRAY2,1:enable main ram array2 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
bitfld.long 0x4 1. "ARRAY1,1:enable main ram array1 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
newline
bitfld.long 0x4 0. "ARRAY0,1:enable main ram array0 clock running 0:disable main ram array0 clock gated" "0: disable,1: enable"
line.long 0x8 "CSS_GDET_CLK_SEL,CSS GDET CLK selection"
bitfld.long 0x8 0.--2. "SEL,CSS GDET Clock Source Selection" "0: t3pll_mci_256m:256Mhz,1: t3pll_mci_256m/2:128Mhz,2: t3pll_mci_256m/4:64Mhz,3: t3pll_mci_256m/8:32Mhz,?,?,?,7: None this may be selected in order to reduce.."
tree.end
tree "CLKCTL1"
base ad:0x40021000
group.long 0x10++0xB
line.long 0x0 "PSCCTL0,Peripheral clock control 0"
bitfld.long 0x0 27. "OSEVENTTIMER,oseventtimer clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 24. "DMIC0,dmic0 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 22. "FC14,fc14 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 11. "FC3,fc3 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 10. "FC2,fc2 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x0 9. "FC1,fc1 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x0 8. "FC0,fc0 clock control" "0: Disable clock,1: Enable clock"
line.long 0x4 "PSCCTL1,Peripheral clock control 1"
bitfld.long 0x4 31. "FREQME,freqme clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x4 16. "CRC,crc clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x4 1. "HSGPIO1,hsgpio1 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x4 0. "HSGPIO0,hsgpio0 clock control" "0: Disable clock,1: Enable clock"
line.long 0x8 "PSCCTL2,Peripheral clock control 2"
bitfld.long 0x8 31. "PMUX,pmux clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 30. "GPIO_INT,gpio_int clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 8. "MRT,mrt clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 7. "RTC_LITE,rtc_lite clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 6. "PMU,pmu clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 4. "CT32B4,ct32b4 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 3. "CT32B3,ct32b3 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 2. "CT32B2,ct32b2 clock control" "0: Disable clock,1: Enable clock"
newline
bitfld.long 0x8 1. "CT32B1,ct32b1 clock control" "0: Disable clock,1: Enable clock"
bitfld.long 0x8 0. "CT32B0,ct32b0 clock control" "0: Disable clock,1: Enable clock"
wgroup.long 0x40++0xB
line.long 0x0 "PSCCTL0_SET,Peripheral clock set 0"
bitfld.long 0x0 27. "OSEVENTTIMER,oseventtimer clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 24. "DMIC0,dmic0 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 22. "FC14,fc14 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 11. "FC3,fc3 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 10. "FC2,fc2 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
bitfld.long 0x0 9. "FC1,fc1 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
newline
bitfld.long 0x0 8. "FC0,fc0 clock set" "0: No effect,1: Sets the PSCCTL0 Bit"
line.long 0x4 "PSCCTL1_SET,Peripheral clock set 1"
bitfld.long 0x4 31. "FREQME,freqme clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
bitfld.long 0x4 16. "CRC,crc clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
newline
bitfld.long 0x4 1. "HSGPIO1,hsgpio1 clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
bitfld.long 0x4 0. "HSGPIO0,hsgpio0 clock set" "0: No effect,1: Sets the PSCCTL1 Bit"
line.long 0x8 "PSCCTL2_SET,Peripheral clock set 2"
bitfld.long 0x8 31. "PMUX,pmux clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 30. "GPIO_INT,gpio_int clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 8. "MRT,mrt clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 7. "RTC_LITE,rtc_lite clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 6. "PMU,pmu clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 4. "CT32B4,ct32b4 clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 3. "CT32B3,ct32b3 clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 2. "CT32B2,ct32b2 clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
newline
bitfld.long 0x8 1. "CT32B1,ct32b1 clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
bitfld.long 0x8 0. "CT32B0,ct32b0 clock set" "0: No effect,1: Sets the PSCCTL2 Bit"
wgroup.long 0x70++0xB
line.long 0x0 "PSCCTL0_CLR,Peripheral clock clear 0"
bitfld.long 0x0 27. "OSEVENTTIMER,oseventtimer clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 24. "DMIC0,dmic0 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 22. "FC14,fc14 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 11. "FC3,fc3 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 10. "FC2,fc2 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
bitfld.long 0x0 9. "FC1,fc1 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
newline
bitfld.long 0x0 8. "FC0,fc0 clock clear" "0: No effect,1: Clears the PSCCTL0 Bit"
line.long 0x4 "PSCCTL1_CLR,Peripheral clock clear 1"
bitfld.long 0x4 31. "FREQME,freqme clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
bitfld.long 0x4 16. "CRC,crc clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
newline
bitfld.long 0x4 1. "HSGPIO1,hsgpio1 clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
bitfld.long 0x4 0. "HSGPIO0,hsgpio0 clock clear" "0: No effect,1: Clears the PSCCTL1 Bit"
line.long 0x8 "PSCCTL2_CLR,Peripheral clock clear 2"
bitfld.long 0x8 31. "PMUX,pmux clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 30. "GPIO_INT,gpio_int clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 8. "MRT,mrt clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 7. "RTC_LITE,rtc_lite clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 6. "PMU,pmu clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 4. "CT32B4,ct32b4 clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 3. "CT32B3,ct32b3 clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 2. "CT32B2,ct32b2 clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
newline
bitfld.long 0x8 1. "CT32B1,ct32b1 clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
bitfld.long 0x8 0. "CT32B0,ct32b0 clock clear" "0: No effect,1: Clears the PSCCTL2 Bit"
group.long 0x240++0x3
line.long 0x0 "AUDIOPLLCLKDIV,Audio PLL0 clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x480++0x3
line.long 0x0 "OSEVENTFCLKSEL,OS EVENT clock selection"
bitfld.long 0x0 0.--2. "SEL,OS Event Timer Functional Clock Source Selection" "0: 1m_lposc,1: 32 kHz Clock,2: Cortex-M33 clock (hclk),?,?,?,?,7: None this may be selected in order to reduce.."
group.long 0x500++0xB
line.long 0x0 "FRG0CLKSEL,FRG clock selection 0"
bitfld.long 0x0 0.--2. "SEL,Fractional Gen. Clock Source Selection" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock (16m_irc).,3: FFRO Clock (48/60m_irc).,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "FRG0CTL,FRG clock controller 0"
hexmask.long.byte 0x4 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is not minus 1 encoded so the numerator value is simply the value in this field."
hexmask.long.byte 0x4 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is minus 1 encoded the denominator value is the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional baud rate generator."
line.long 0x8 "FC0FCLKSEL,Flexcomm Interface clock selection 0"
bitfld.long 0x8 0.--2. "SEL,Flexcomm Functional Clock Source Selection" "0: SFRO Clock (16m_irc),1: FFRO Clock (48/60m_irc).,2: Audio PLL Clock (audio_pll_clk).,3: Master Clock In (mclk_in).,4: FCn FRG Clock (frg_clk n).,?,?,7: None this may be selected in order to reduce.."
group.long 0x520++0xB
line.long 0x0 "FRG1CLKSEL,FRG clock selection 1"
bitfld.long 0x0 0.--2. "SEL,Fractional Gen. Clock Source Selection" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock (16m_irc).,3: FFRO Clock (48/60m_irc).,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "FRG1CTL,FRG clock controller 1"
hexmask.long.byte 0x4 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is not minus 1 encoded so the numerator value is simply the value in this field."
hexmask.long.byte 0x4 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is minus 1 encoded the denominator value is the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional baud rate generator."
line.long 0x8 "FC1FCLKSEL,Flexcomm Interface clock selection 1"
bitfld.long 0x8 0.--2. "SEL,Flexcomm Functional Clock Source Selection" "0: SFRO Clock (16m_irc),1: FFRO Clock (48/60m_irc).,2: Audio PLL Clock (audio_pll_clk).,3: Master Clock In (mclk_in).,4: FCn FRG Clock (frg_clk n).,?,?,7: None this may be selected in order to reduce.."
group.long 0x540++0xB
line.long 0x0 "FRG2CLKSEL,FRG clock selection 2"
bitfld.long 0x0 0.--2. "SEL,Fractional Gen. Clock Source Selection" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock (16m_irc).,3: FFRO Clock (48/60m_irc).,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "FRG2CTL,FRG clock controller 2"
hexmask.long.byte 0x4 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is not minus 1 encoded so the numerator value is simply the value in this field."
hexmask.long.byte 0x4 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is minus 1 encoded the denominator value is the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional baud rate generator."
line.long 0x8 "FC2FCLKSEL,Flexcomm Interface clock selection 2"
bitfld.long 0x8 0.--2. "SEL,Flexcomm Functional Clock Source Selection" "0: SFRO Clock (16m_irc),1: FFRO Clock (48/60m_irc).,2: Audio PLL Clock (audio_pll_clk).,3: Master Clock In (mclk_in).,4: FCn FRG Clock (frg_clk n).,?,?,7: None this may be selected in order to reduce.."
group.long 0x560++0xB
line.long 0x0 "FRG3CLKSEL,FRG clock selection 3"
bitfld.long 0x0 0.--2. "SEL,Fractional Gen. Clock Source Selection" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock (16m_irc).,3: FFRO Clock (48/60m_irc).,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "FRG3CTL,FRG clock controller 3"
hexmask.long.byte 0x4 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is not minus 1 encoded so the numerator value is simply the value in this field."
hexmask.long.byte 0x4 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is minus 1 encoded the denominator value is the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional baud rate generator."
line.long 0x8 "FC3FCLKSEL,Flexcomm Interface clock selection 3"
bitfld.long 0x8 0.--2. "SEL,Flexcomm Functional Clock Source Selection" "0: SFRO Clock (16m_irc),1: FFRO Clock (48/60m_irc).,2: Audio PLL Clock (audio_pll_clk).,3: Master Clock In (mclk_in).,4: FCn FRG Clock (frg_clk n).,?,?,7: None this may be selected in order to reduce.."
group.long 0x6C0++0xB
line.long 0x0 "FRG14CLKSEL,FRG clock selection 14"
bitfld.long 0x0 0.--2. "SEL,Fractional Gen. Clock Source Selection" "0: Main Clock,1: FRG PLL Clock,2: SFRO Clock (16m_irc).,3: FFRO Clock (48/60m_irc).,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "FRG14CTL,FRG clock controller 14"
hexmask.long.byte 0x4 8.--15. 1. "MULT,Numerator of the fractional divider. MULT is not minus 1 encoded so the numerator value is simply the value in this field."
hexmask.long.byte 0x4 0.--7. 1. "DIV,Denominator of the fractional divider. DIV is minus 1 encoded the denominator value is the value of this field + 1. Always set to 0xFF (denominator = 256) to use with the fractional baud rate generator."
line.long 0x8 "FC14FCLKSEL,Flexcomm Interface clock selection 14"
bitfld.long 0x8 0.--2. "SEL,Flexcomm Functional Clock Source Selection" "0: SFRO Clock (16m_irc),1: FFRO Clock (48/60m_irc).,2: Audio PLL Clock (audio_pll_clk).,3: Master Clock In (mclk_in).,4: FCn FRG Clock (frg_clk n).,?,?,7: None this may be selected in order to reduce.."
group.long 0x6FC++0xB
line.long 0x0 "FRGPLLCLKDIV,FRG PLL clock divider"
bitfld.long 0x0 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x0 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x0 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0x4 "DMIC0FCLKSEL,DMIC0 clock selection"
bitfld.long 0x4 0.--2. "SEL,DMIC Functional Clock Source Selection" "0: SFRO Clock (16m_irc),1: FFRO Clock (48/60m_irc).,2: Audio PLL Clock (audio_pll_clk).,3: Master Clock In (mclk_in).,4: 1m_lposc,5: 32 kHz Wake Clk,?,7: None this may be selected in order to reduce.."
line.long 0x8 "DMIC0CLKDIV,DMIC clock divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x720++0xF
line.long 0x0 "CT32BIT0FCLKSEL,Ct32bit timer 0 clock selection"
bitfld.long 0x0 0.--2. "SEL,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock (16m_irc).,2: FFRO Clock (48/60m_irc).,3: Audio PLL Clock (audio_pll_clk).,4: Master Clock In (mclk_in).,5: 1m_lposc,?,7: None this may be selected in order to reduce.."
line.long 0x4 "CT32BIT1FCLKSEL,Ct32bit timer 1 clock selection"
bitfld.long 0x4 0.--2. "SEL,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock (16m_irc).,2: FFRO Clock (48/60m_irc).,3: Audio PLL Clock (audio_pll_clk).,4: Master Clock In (mclk_in).,5: 1m_lposc,?,7: None this may be selected in order to reduce.."
line.long 0x8 "CT32BIT2FCLKSEL,Ct32bit timer 2 clock selection"
bitfld.long 0x8 0.--2. "SEL,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock (16m_irc).,2: FFRO Clock (48/60m_irc).,3: Audio PLL Clock (audio_pll_clk).,4: Master Clock In (mclk_in).,5: 1m_lposc,?,7: None this may be selected in order to reduce.."
line.long 0xC "CT32BIT3FCLKSEL,Ct32bit timer 3 clock selection"
bitfld.long 0xC 0.--2. "SEL,CT32Bit Functional Clock Source Selection" "0: Main Clock,1: SFRO Clock (16m_irc).,2: FFRO Clock (48/60m_irc).,3: Audio PLL Clock (audio_pll_clk).,4: Master Clock In (mclk_in).,5: 1m_lposc,?,7: None this may be selected in order to reduce.."
group.long 0x740++0x7
line.long 0x0 "AUDIOMCLKSEL,Audio MCLK selection"
bitfld.long 0x0 0.--2. "SEL,Audio MCLK Clock Source Selection" "0: FFRO Clock (48/60m_irc).,1: Audio PLL Clock (audio_pll_clk).,2: main_clk,?,?,?,?,7: None this may be selected in order to reduce.."
line.long 0x4 "AUDIOMCLKDIV,Audio MCLK divider"
bitfld.long 0x4 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x4 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x4 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
group.long 0x760++0xF
line.long 0x0 "CLKOUTSEL0,Clock out selection 0"
bitfld.long 0x0 0.--2. "SEL,Clock Output Select 1st Stage" "0: SFRO Clock,1: External clock (clk_in).,2: 1m_lposc,3: FFRO Clock,4: Main Clock (main_clk).,5: refclk_sys(38.4M).,6: avpll_ch2_CLKOUT(64M),7: None this may be selected in order to reduce.."
line.long 0x4 "CLKOUTSEL1,Clock out selection 1"
bitfld.long 0x4 0.--2. "SEL,Clock Output Select 2nd Stage" "0: CLKOUTSEL0 Multiplexed Output,1: Main PLL Clock (main_pll_clk).,2: AUX0 PLL clock (aux0_pll_clk).,?,4: AUX1 PLL clock (aux1_pll_clk),5: Audio PLL Clock (audio_pll_clk).,6: 32 kHz RTC Clock.,7: None this may be selected in order to reduce.."
line.long 0x8 "CLKOUTDIV,Clock out divider"
bitfld.long 0x8 31. "REQFLAG,Divider status flag. Set when a change is made to the divider value cleared when the change is complete. The clock being divided must be running for this status to change" "0,1"
bitfld.long 0x8 30. "HALT,Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output" "0,1"
newline
bitfld.long 0x8 29. "RESET,Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count" "0,1"
hexmask.long.byte 0x8 0.--7. 1. "DIV,Clock Divider Value Selection: 0: Divide by 1... 255: Divide by 256"
line.long 0xC "CLKOUTSEL2,Clock out selection 2"
bitfld.long 0xC 0.--2. "SEL,Clock Output Select 3rd Stage" "0: CLKOUTSEL1 Multiplexed Output,1: tcpu_mci_flexspi_clk,2: tddr_mci_flexspi_clk,3: t3pll_mci_flexspi_clk,4: t3pll_mci_256m,5: cau_slp_ref_clk,6: tddr_mci_enet_clk,7: None this may be selected in order to reduce.."
tree.end
tree.end
tree "CRC (Cyclic Redundancy Check)"
base ad:0x40120000
group.long 0x0++0x7
line.long 0x0 "MODE,CRC mode register"
bitfld.long 0x0 5. "CMPL_SUM,CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM" "0: No 1's complement for CRC_SUM,1: 1's complement for CRC_SUM"
bitfld.long 0x0 4. "BIT_RVS_SUM,CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM" "0: No bit order reverse for CRC_SUM,1: Bit order reverse for CRC_SUM"
newline
bitfld.long 0x0 3. "CMPL_WR,Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA" "0: No 1's complement for CRC_WR_DATA,1: 1's complement for CRC_WR_DATA"
bitfld.long 0x0 2. "BIT_RVS_WR,Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)" "0: No bit order reverse for CRC_WR_DATA,1: Bit order reverse for CRC_WR_DATA"
newline
bitfld.long 0x0 0.--1. "CRC_POLY,CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial" "0: CRC-CCITT polynomial,1: CRC-16 polynomial,?,?"
line.long 0x4 "SEED,CRC seed register"
hexmask.long 0x4 0.--31. 1. "CRC_SEED,A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses."
rgroup.long 0x8++0x3
line.long 0x0 "SUM,CRC checksum register"
hexmask.long 0x0 0.--31. 1. "CRC_SUM,The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes."
wgroup.long 0x8++0x3
line.long 0x0 "WR_DATA,CRC data register"
hexmask.long 0x0 0.--31. 1. "CRC_WR_DATA,Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8 16 or 32-bit are allowed and accept back-to-back transactions."
tree.end
tree "CSSV2"
base ad:0x40007000
rgroup.long 0x0++0x3
line.long 0x0 "CSS_STATUS,Status register"
hexmask.long.tbyte 0x0 13.--31. 1. "STATUS_RSVD,no description available"
newline
bitfld.long 0x0 12. "GDET_IRQ_NEG,IRQ for GDET has detected a positive glitch: active high irq" "0,1"
newline
bitfld.long 0x0 11. "GDET_IRQ_POS,IRQ for GDET has detected a negative glitch: active high irq" "0,1"
newline
bitfld.long 0x0 10. "DTRNG_BUSY,When set it indicates the DTRNG is gathering entropy" "0,1"
newline
bitfld.long 0x0 8.--9. "DRBG_ENT_LVL,Entropy quality of the current DRBG instance." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PPROT,Current command privilege level" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "ECDSA_VFY_STATUS,Signature Verify Result Status; 0 == No Verify Run; 1 == Signature Verify Failed; 2 == Signature Verify Passed; 3 == Invalid Error" "0: = No Verify Run,1: = Signature Verify Failed,2: = Signature Verify Passed,3: = Invalid"
newline
bitfld.long 0x0 3. "PRNG_RDY,High to indicate the internal PRNG is ready." "0,1"
newline
bitfld.long 0x0 2. "CSS_ERR,High to indicate the CSS has detected an internal error" "0,1"
newline
bitfld.long 0x0 1. "CSS_IRQ,High to indicate the CSS has an active interrupt" "0,1"
newline
bitfld.long 0x0 0. "CSS_BUSY,High to indicate the CSS is executing a Crypto Sequence" "0,1"
group.long 0x4++0x17
line.long 0x0 "CSS_CTRL,CSS Control register"
hexmask.long.tbyte 0x0 9.--31. 1. "CTRL_RFU,reserved"
newline
bitfld.long 0x0 8. "BYTE_ORDER,Defines Endianness - 1: BigEndian 0: Little Endian" "0: Little Endian,1: BigEndian"
newline
hexmask.long.byte 0x0 3.--7. 1. "CSS_CMD,CSS Command Field: List of Valid commands:; CIPHER; AUTH_CIPHER; ECSIGN; ECVFY; ECKXCH; KEYGEN; KEYIN; KEYOUT; KDELETE; KEYPROV; CKDF; HKDF; TLS_INIT; HASH; HMAC; CMAC; DRBG_REQ; DRBG_TEST; DTRNG_CFG_LOAD; DTRNG_EVAL; GDET_CFG_LOAD; GDET_TRIM"
newline
bitfld.long 0x0 2. "CSS_RESET,Write to 1 to perform a CSS synchronous Reset" "0,1"
newline
bitfld.long 0x0 1. "CSS_START,Write to 1 to start a CSS Operation" "0,1"
newline
bitfld.long 0x0 0. "CSS_EN,CSS enable 0=CSS disabled 1= CSS is enabled" "0: CSS disabled,1: CSS is enabled"
line.long 0x4 "CSS_CMDCFG0,CSS command configuration register"
hexmask.long 0x4 0.--31. 1. "CMDCFG0,refer to reference manual for assignment of this field"
line.long 0x8 "CSS_CFG,CSS configuration register"
bitfld.long 0x8 31. "SHA2_DIRECT,1=enable sha2 direct mode: direct access from external; bus to css internal sha" "?,1: enable sha2 direct mode: direct access from.."
newline
hexmask.long.byte 0x8 26.--30. 1. "CFG_RSVD1,reserved"
newline
hexmask.long.word 0x8 16.--25. 1. "ADCTRL,maximum aes start delay"
newline
hexmask.long.word 0x8 0.--15. 1. "CFG_RSVD0,reserved"
line.long 0xC "CSS_KIDX0,Keystore index 0 - for commands that access a single key"
hexmask.long.byte 0xC 0.--6. 1. "KIDX0,keystore is indexed as an array of 128 bit key slots"
line.long 0x10 "CSS_KIDX1,Keystore index 1 - for commands that access 2 keys"
hexmask.long.byte 0x10 0.--6. 1. "KIDX1,keystore is indexed as an array of 128 bit key slots"
line.long 0x14 "CSS_KPROPIN,key properties request"
hexmask.long 0x14 0.--31. 1. "KPROPIN,for commands that create a key - requested properties; of the key that is being created"
group.long 0x20++0xB
line.long 0x0 "CSS_DMA_SRC0,CSS DMA Source 0"
hexmask.long 0x0 0.--31. 1. "ADDR_SRC0,defines the System address of the start of the; data to be transferred to the CSS via DMA"
line.long 0x4 "CSS_DMA_SRC0_LEN,CSS DMA Source 0 length"
hexmask.long 0x4 0.--31. 1. "SIZE_SRC0_LEN,Size in bytes of the data to be transferred from; the target defined in SFR CSS_DMA_SRC0"
line.long 0x8 "CSS_DMA_SRC1,CSS DMA Source 1"
hexmask.long 0x8 0.--31. 1. "ADDR_SRC1,defines the System address of the start of the; data to be transferred to the CSS via DMA"
group.long 0x30++0x13
line.long 0x0 "CSS_DMA_SRC2,CSS DMA Source 2"
hexmask.long 0x0 0.--31. 1. "ADDR_SRC2,defines the System address of the start of the; data to be transferred to the CSS via DMA"
line.long 0x4 "CSS_DMA_SRC2_LEN,CSS DMA Source 2 length"
hexmask.long 0x4 0.--31. 1. "SIZE_SRC2_LEN,Size in bytes of the data to be transferred from; the target defined in SFR CSS_DMA_SRC2"
line.long 0x8 "CSS_DMA_RES0,CSS DMA Result 0"
hexmask.long 0x8 0.--31. 1. "ADDR_RES0,defines the System Start address of where the result; of the CSS operation will be transferred via DMA"
line.long 0xC "CSS_DMA_RES0_LEN,CSS DMA Result 0 Size"
hexmask.long 0xC 0.--31. 1. "SIZE_RES0_LEN,Size in bytes of the data to be transferred to"
line.long 0x10 "CSS_INT_ENABLE,Interrupt enable"
hexmask.long 0x10 2.--31. 1. "INT_ENA_RSVD,reserved"
newline
bitfld.long 0x10 1. "GDET_INT_EN,GDET Interrupt enable bit" "0,1"
newline
bitfld.long 0x10 0. "INT_EN,Interrupt enable bit" "0,1"
wgroup.long 0x44++0x7
line.long 0x0 "CSS_INT_STATUS_CLR,Interrupt status clear"
hexmask.long 0x0 2.--31. 1. "INT_STSC_RSVD,reserved"
newline
bitfld.long 0x0 1. "GDET_INT_CLR,GDET Interrupt status clear" "0,1"
newline
bitfld.long 0x0 0. "INT_CLR,Interrupt status clear" "0,1"
line.long 0x4 "CSS_INT_STATUS_SET,Interrupt status set"
hexmask.long 0x4 3.--31. 1. "INT_STSS_RSVD,reserved"
newline
bitfld.long 0x4 2. "GDET_INT_POS_SET,Set GDET interrupt by software" "0,1"
newline
bitfld.long 0x4 1. "GDET_INT_NEG_SET,Set GDET interrupt by software" "0,1"
newline
bitfld.long 0x4 0. "INT_SET,Set interrupt by software" "0,1"
rgroup.long 0x4C++0x3
line.long 0x0 "CSS_ERR_STATUS,Status register"
hexmask.long.tbyte 0x0 9.--31. 1. "ERR_STAT_RSVD,no description available"
newline
bitfld.long 0x0 8. "DTRNG_ERR,DTRNG unable to gather entropy with the current; configuration." "0,1"
newline
bitfld.long 0x0 6.--7. "ERR_LVL,Indicates Error Level which has been triggerer." "0,1,2,3"
newline
bitfld.long 0x0 5. "PRNG_ERR,User Read of CSS_PRNG_DATOUT when CSS_STATUS." "0,1"
newline
bitfld.long 0x0 4. "FLT_ERR,Hardware fault error: Attempt to change the value; of an internal register" "0,1"
newline
bitfld.long 0x0 3. "ITG_ERR,Data integrity error:; Internal data integrity check failed" "0,1"
newline
bitfld.long 0x0 2. "ALG_ERR,Algorithm error: An internal algorithm has; produced an unexpected result." "0,1"
newline
bitfld.long 0x0 1. "OPN_ERR,Operational error:; CSS has been incorrectly operated" "0,1"
newline
bitfld.long 0x0 0. "BUS_ERR,Bus access error: public or private bus" "0,1"
wgroup.long 0x50++0x3
line.long 0x0 "CSS_ERR_STATUS_CLR,Interrupt status clear"
hexmask.long 0x0 1.--31. 1. "ERR_STSC_RSVD,reserved"
newline
bitfld.long 0x0 0. "ERR_CLR,1=clear CSS error status bits and exit CSS error state" "?,1: clear CSS error status bits and exit CSS error.."
rgroup.long 0x54++0xF
line.long 0x0 "CSS_VERSION,CSS Version"
hexmask.long.byte 0x0 28.--31. 1. "SW_X,software major release version: possible values 1-9"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_Y1,software minor release version digit1: possible values 0-9"
newline
hexmask.long.byte 0x0 20.--23. 1. "SW_Y2,software minor release version digit0: possible values 0-9"
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_Z,software extended revision version: possible values 0-9"
newline
hexmask.long.byte 0x0 12.--15. 1. "X,major release version: possible values 1-9"
newline
hexmask.long.byte 0x0 8.--11. 1. "Y1,minor release version digit1: possible values 0-9"
newline
hexmask.long.byte 0x0 4.--7. 1. "Y2,minor release version digit0: possible values 0-9"
newline
hexmask.long.byte 0x0 0.--3. 1. "Z,extended revision version: possible values 0-9"
line.long 0x4 "CSS_CONFIG,CSS Config"
hexmask.long.word 0x4 22.--31. 1. "CONFIG_RSVD,reserved"
newline
bitfld.long 0x4 21. "GDET_TRIM_SUP,gdet_trim command is supported" "0,1"
newline
bitfld.long 0x4 20. "GDET_CFG_LOAD_SUP,gdet_cfg_load command is supported" "0,1"
newline
bitfld.long 0x4 19. "DTRNG_EVAL_SUP,dtrng_eval command is supported" "0,1"
newline
bitfld.long 0x4 18. "DTRNG_CFG_LOAD_SUP,dtrng_cfg_load command is supported" "0,1"
newline
bitfld.long 0x4 17. "DRBG_TEST_SUP,drbg_test command is supported" "0,1"
newline
bitfld.long 0x4 16. "DRBG_REQ_SUP,drbg_req command is supported" "0,1"
newline
bitfld.long 0x4 15. "CMAC_SUP,cmac command is supported" "0,1"
newline
bitfld.long 0x4 14. "HMAC_SUP,hmac command is supported" "0,1"
newline
bitfld.long 0x4 13. "HASH_SUP,hash command is supported" "0,1"
newline
bitfld.long 0x4 12. "TLS_INIT_SUP,tls_init command is supported" "0,1"
newline
bitfld.long 0x4 11. "HKDF_SUP,hkdf command is supported" "0,1"
newline
bitfld.long 0x4 10. "CKDF_SUP,ckdf command is supported" "0,1"
newline
bitfld.long 0x4 9. "KEYPROV_SUP,keyprov command is supported" "0,1"
newline
bitfld.long 0x4 8. "KDELETE_SUP,kdelete command is supported" "0,1"
newline
bitfld.long 0x4 7. "KEYOUT_SUP,keyout command is supported" "0,1"
newline
bitfld.long 0x4 6. "KEYIN_SUP,keyin command is supported" "0,1"
newline
bitfld.long 0x4 5. "KEYGEN_SUP,keygen command is supported" "0,1"
newline
bitfld.long 0x4 4. "ECKXCH_SUP,dhkey_xch command is supported" "0,1"
newline
bitfld.long 0x4 3. "ECVFY_SUP,ecvfy command is supported" "0,1"
newline
bitfld.long 0x4 2. "ECSIGN_SUP,ecsign command is supported" "0,1"
newline
bitfld.long 0x4 1. "AUTH_CIPHER_SUP,auth_cipher command is supported" "0,1"
newline
bitfld.long 0x4 0. "CIPHER_SUP,cipher command is supported" "0,1"
line.long 0x8 "CSS_PRNG_DATOUT,PRNG SW read out register"
hexmask.long 0x8 0.--31. 1. "PRNG_DATOUT,32-bit wide pseudo-random number"
line.long 0xC "CSS_GDET_EVTCNT,CSS GDET Event Counter"
hexmask.long.tbyte 0xC 9.--31. 1. "GDET_EVTCNT_RSVD,reserved"
newline
bitfld.long 0xC 8. "GDET_EVTCNT_CLR_DONE,The GDET event counter has been cleared" "0,1"
newline
hexmask.long.byte 0xC 0.--7. 1. "GDET_EVTCNT,Number of glitch event recorded"
wgroup.long 0x64++0x3
line.long 0x0 "CSS_GDET_EVTCNT_CLR,CSS GDET Event Counter Clear"
hexmask.long 0x0 1.--31. 1. "GDET_EVTCNT_CLR_RSVD,reserved"
newline
bitfld.long 0x0 0. "GDET_EVTCNT_CLR,1=clear GDET event counter clear" "?,1: clear GDET event counter clear"
rgroup.long 0x100++0x3
line.long 0x0 "CSS_SHA2_STATUS,CSS SHA2 Status Register"
hexmask.long 0x0 1.--31. 1. "STATUS_RSVD1,reserved"
newline
bitfld.long 0x0 0. "SHA2_BUSY,no description available" "0,1"
group.long 0x104++0x7
line.long 0x0 "CSS_SHA2_CTRL,SHA2 Control register"
hexmask.long.tbyte 0x0 10.--31. 1. "CTRL_RSVD,r-eserved"
newline
bitfld.long 0x0 9. "SHA2_BYTE_ORDER,Write to 1 to Reverse byte endianess" "0,1"
newline
rbitfld.long 0x0 6.--8. "CTRL_RSVD1,r-eserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4.--5. "SHA2_MODE,SHA2 MODE:; 2'b11 - SHA512; 2'b10 - SHA384; 2'b01 - SHA224; 2'b00 - SHA256" "0,1,2,3"
newline
bitfld.long 0x0 3. "SHA2_LOAD,Write to 1 to Load the SHA2 Kernel" "0,1"
newline
bitfld.long 0x0 2. "SHA2_INIT,Write to 1 to Init the SHA2 Kernel" "0,1"
newline
bitfld.long 0x0 1. "SHA2_RST,Write to 1 to Reset a SHA2 operation" "0,1"
newline
bitfld.long 0x0 0. "SHA2_START,Write to 1 to Init the SHA2 Module" "0,1"
line.long 0x4 "CSS_SHA2_DIN,CSS SHA_DATA IN Register 0"
hexmask.long 0x4 0.--31. 1. "SHA_DATIN,Output CSS_SHA_DATIN from CSS Application being executed"
rgroup.long 0x10C++0x3F
line.long 0x0 "CSS_SHA2_DOUT0,CSS CSS_SHA_DATA Out Register 0"
hexmask.long 0x0 0.--31. 1. "SHA_DATA0,Output SHA_DATA from CSS Application being executed"
line.long 0x4 "CSS_SHA2_DOUT1,CSS SHA_DATA Out Register 1"
hexmask.long 0x4 0.--31. 1. "SHA_DATA1,Output SHA_DATA from CSS Application being executed"
line.long 0x8 "CSS_SHA2_DOUT2,CSS SHA_DATA Out Register 2"
hexmask.long 0x8 0.--31. 1. "SHA_DATA2,Output SHA_DATA from CSS Application being executed"
line.long 0xC "CSS_SHA2_DOUT3,CSS SHA_DATA Out Register 3"
hexmask.long 0xC 0.--31. 1. "SHA_DATA3,Output SHA_DATA from CSS Application being executed"
line.long 0x10 "CSS_SHA2_DOUT4,CSS SHA_DATA Out Register 4"
hexmask.long 0x10 0.--31. 1. "SHA_DATA4,Output SHA_DATA from CSS Application being executed"
line.long 0x14 "CSS_SHA2_DOUT5,CSS SHA_DATA Out Register 5"
hexmask.long 0x14 0.--31. 1. "SHA_DATA5,Output SHA_DATA from CSS Application being executed"
line.long 0x18 "CSS_SHA2_DOUT6,CSS SHA_DATA Out Register 6"
hexmask.long 0x18 0.--31. 1. "SHA_DATA6,Output SHA_DATA from CSS Application being executed"
line.long 0x1C "CSS_SHA2_DOUT7,CSS SHA_DATA Out Register 7"
hexmask.long 0x1C 0.--31. 1. "SHA_DATA7,Output SHA_DATA from CSS Application being executed"
line.long 0x20 "CSS_SHA2_DOUT8,CSS CSS_SHA_DATA Out Register 8"
hexmask.long 0x20 0.--31. 1. "SHA_DATA8,Output SHA_DATA from CSS Application being executed"
line.long 0x24 "CSS_SHA2_DOUT9,CSS SHA_DATA Out Register 9"
hexmask.long 0x24 0.--31. 1. "SHA_DATA9,Output SHA_DATA from CSS Application being executed"
line.long 0x28 "CSS_SHA2_DOUT10,CSS SHA_DATA Out Register 10"
hexmask.long 0x28 0.--31. 1. "SHA_DATA10,Output SHA_DATA from CSS Application being executed"
line.long 0x2C "CSS_SHA2_DOUT11,CSS SHA_DATA Out Register 11"
hexmask.long 0x2C 0.--31. 1. "SHA_DATA11,Output SHA_DATA from CSS Application being executed"
line.long 0x30 "CSS_SHA2_DOUT12,CSS SHA_DATA Out Register 12"
hexmask.long 0x30 0.--31. 1. "SHA_DATA12,Output SHA_DATA from CSS Application being executed"
line.long 0x34 "CSS_SHA2_DOUT13,CSS SHA_DATA Out Register 13"
hexmask.long 0x34 0.--31. 1. "SHA_DATA13,Output SHA_DATA from CSS Application being executed"
line.long 0x38 "CSS_SHA2_DOUT14,CSS SHA_DATA Out Register 14"
hexmask.long 0x38 0.--31. 1. "SHA_DATA14,Output SHA_DATA from CSS Application being executed"
line.long 0x3C "CSS_SHA2_DOUT15,CSS SHA_DATA Out Register 15"
hexmask.long 0x3C 0.--31. 1. "SHA_DATA15,Output SHA_DATA from CSS Application being executed"
rgroup.long 0x150++0x4F
line.long 0x0 "CSS_KS0,Status register"
bitfld.long 0x0 30.--31. "KS0_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x0 29. "KS0_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x0 28. "KS0_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x0 27. "KS0_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x0 26. "KS0_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x0 25. "KS0_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x0 24. "KS0_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x0 23. "KS0_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x0 22. "KS0_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x0 21. "KS0_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x0 20. "KS0_UAES,Aes key" "0,1"
newline
bitfld.long 0x0 19. "KS0_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x0 18. "KS0_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x0 17. "KS0_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x0 16. "KS0_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x0 15. "KS0_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x0 14. "KS0_UKSK,KSK key" "0,1"
newline
bitfld.long 0x0 13. "KS0_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x0 10.--12. "KS0_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 9. "KS0_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x0 8. "KS0_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x0 7. "KS0_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x0 6. "KS0_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x0 5. "KS0_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x0 1.--4. 1. "KS0_RSVD0,Reserved 0"
newline
bitfld.long 0x0 0. "KS0_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x4 "CSS_KS1,Status register"
bitfld.long 0x4 30.--31. "KS1_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x4 29. "KS1_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x4 28. "KS1_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x4 27. "KS1_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x4 26. "KS1_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x4 25. "KS1_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x4 24. "KS1_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x4 23. "KS1_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x4 22. "KS1_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x4 21. "KS1_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x4 20. "KS1_UAES,Aes key" "0,1"
newline
bitfld.long 0x4 19. "KS1_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x4 18. "KS1_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x4 17. "KS1_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x4 16. "KS1_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x4 15. "KS1_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x4 14. "KS1_UKSK,KSK key" "0,1"
newline
bitfld.long 0x4 13. "KS1_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x4 10.--12. "KS1_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 9. "KS1_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x4 8. "KS1_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x4 7. "KS1_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x4 6. "KS1_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x4 5. "KS1_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x4 1.--4. 1. "KS1_RSVD0,Reserved 0"
newline
bitfld.long 0x4 0. "KS1_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x8 "CSS_KS2,Status register"
bitfld.long 0x8 30.--31. "KS2_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x8 29. "KS2_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x8 28. "KS2_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x8 27. "KS2_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x8 26. "KS2_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x8 25. "KS2_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x8 24. "KS2_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x8 23. "KS2_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x8 22. "KS2_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x8 21. "KS2_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x8 20. "KS2_UAES,Aes key" "0,1"
newline
bitfld.long 0x8 19. "KS2_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x8 18. "KS2_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x8 17. "KS2_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x8 16. "KS2_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x8 15. "KS2_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x8 14. "KS2_UKSK,KSK key" "0,1"
newline
bitfld.long 0x8 13. "KS2_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x8 10.--12. "KS2_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 9. "KS2_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x8 8. "KS2_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x8 7. "KS2_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x8 6. "KS2_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x8 5. "KS2_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x8 1.--4. 1. "KS2_RSVD0,Reserved 0"
newline
bitfld.long 0x8 0. "KS2_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0xC "CSS_KS3,Status register"
bitfld.long 0xC 30.--31. "KS3_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0xC 29. "KS3_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0xC 28. "KS3_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0xC 27. "KS3_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0xC 26. "KS3_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0xC 25. "KS3_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0xC 24. "KS3_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0xC 23. "KS3_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0xC 22. "KS3_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0xC 21. "KS3_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0xC 20. "KS3_UAES,Aes key" "0,1"
newline
bitfld.long 0xC 19. "KS3_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0xC 18. "KS3_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0xC 17. "KS3_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0xC 16. "KS3_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0xC 15. "KS3_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0xC 14. "KS3_UKSK,KSK key" "0,1"
newline
bitfld.long 0xC 13. "KS3_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0xC 10.--12. "KS3_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 9. "KS3_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0xC 8. "KS3_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0xC 7. "KS3_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0xC 6. "KS3_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0xC 5. "KS3_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0xC 1.--4. 1. "KS3_RSVD0,Reserved 0"
newline
bitfld.long 0xC 0. "KS3_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x10 "CSS_KS4,Status register"
bitfld.long 0x10 30.--31. "KS4_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x10 29. "KS4_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x10 28. "KS4_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x10 27. "KS4_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x10 26. "KS4_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x10 25. "KS4_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x10 24. "KS4_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x10 23. "KS4_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x10 22. "KS4_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x10 21. "KS4_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x10 20. "KS4_UAES,Aes key" "0,1"
newline
bitfld.long 0x10 19. "KS4_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x10 18. "KS4_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x10 17. "KS4_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x10 16. "KS4_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x10 15. "KS4_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x10 14. "KS4_UKSK,KSK key" "0,1"
newline
bitfld.long 0x10 13. "KS4_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x10 10.--12. "KS4_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 9. "KS4_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x10 8. "KS4_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x10 7. "KS4_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x10 6. "KS4_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x10 5. "KS4_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x10 1.--4. 1. "KS4_RSVD0,Reserved 0"
newline
bitfld.long 0x10 0. "KS4_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x14 "CSS_KS5,Status register"
bitfld.long 0x14 30.--31. "KS5_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x14 29. "KS5_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x14 28. "KS5_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x14 27. "KS5_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x14 26. "KS5_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x14 25. "KS5_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x14 24. "KS5_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x14 23. "KS5_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x14 22. "KS5_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x14 21. "KS5_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x14 20. "KS5_UAES,Aes key" "0,1"
newline
bitfld.long 0x14 19. "KS5_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x14 18. "KS5_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x14 17. "KS5_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x14 16. "KS5_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x14 15. "KS5_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x14 14. "KS5_UKSK,KSK key" "0,1"
newline
bitfld.long 0x14 13. "KS5_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x14 10.--12. "KS5_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 9. "KS5_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x14 8. "KS5_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x14 7. "KS5_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x14 6. "KS5_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x14 5. "KS5_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x14 1.--4. 1. "KS5_RSVD0,Reserved 0"
newline
bitfld.long 0x14 0. "KS5_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x18 "CSS_KS6,Status register"
bitfld.long 0x18 30.--31. "KS6_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x18 29. "KS6_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x18 28. "KS6_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x18 27. "KS6_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x18 26. "KS6_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x18 25. "KS6_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x18 24. "KS6_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x18 23. "KS6_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x18 22. "KS6_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x18 21. "KS6_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x18 20. "KS6_UAES,Aes key" "0,1"
newline
bitfld.long 0x18 19. "KS6_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x18 18. "KS6_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x18 17. "KS6_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x18 16. "KS6_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x18 15. "KS6_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x18 14. "KS6_UKSK,KSK key" "0,1"
newline
bitfld.long 0x18 13. "KS6_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x18 10.--12. "KS6_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 9. "KS6_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x18 8. "KS6_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x18 7. "KS6_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x18 6. "KS6_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x18 5. "KS6_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x18 1.--4. 1. "KS6_RSVD0,Reserved 0"
newline
bitfld.long 0x18 0. "KS6_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x1C "CSS_KS7,Status register"
bitfld.long 0x1C 30.--31. "KS7_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x1C 29. "KS7_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x1C 28. "KS7_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x1C 27. "KS7_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x1C 26. "KS7_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x1C 25. "KS7_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x1C 24. "KS7_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x1C 23. "KS7_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x1C 22. "KS7_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x1C 21. "KS7_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x1C 20. "KS7_UAES,Aes key" "0,1"
newline
bitfld.long 0x1C 19. "KS7_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x1C 18. "KS7_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x1C 17. "KS7_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x1C 16. "KS7_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x1C 15. "KS7_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x1C 14. "KS7_UKSK,KSK key" "0,1"
newline
bitfld.long 0x1C 13. "KS7_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x1C 10.--12. "KS7_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 9. "KS7_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x1C 8. "KS7_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x1C 7. "KS7_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x1C 6. "KS7_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x1C 5. "KS7_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x1C 1.--4. 1. "KS7_RSVD0,Reserved 0"
newline
bitfld.long 0x1C 0. "KS7_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x20 "CSS_KS8,Status register"
bitfld.long 0x20 30.--31. "KS8_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x20 29. "KS8_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x20 28. "KS8_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x20 27. "KS8_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x20 26. "KS8_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x20 25. "KS8_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x20 24. "KS8_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x20 23. "KS8_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x20 22. "KS8_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x20 21. "KS8_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x20 20. "KS8_UAES,Aes key" "0,1"
newline
bitfld.long 0x20 19. "KS8_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x20 18. "KS8_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x20 17. "KS8_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x20 16. "KS8_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x20 15. "KS8_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x20 14. "KS8_UKSK,KSK key" "0,1"
newline
bitfld.long 0x20 13. "KS8_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x20 10.--12. "KS8_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 9. "KS8_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x20 8. "KS8_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x20 7. "KS8_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x20 6. "KS8_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x20 5. "KS8_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x20 1.--4. 1. "KS8_RSVD0,Reserved 0"
newline
bitfld.long 0x20 0. "KS8_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x24 "CSS_KS9,Status register"
bitfld.long 0x24 30.--31. "KS9_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x24 29. "KS9_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x24 28. "KS9_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x24 27. "KS9_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x24 26. "KS9_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x24 25. "KS9_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x24 24. "KS9_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x24 23. "KS9_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x24 22. "KS9_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x24 21. "KS9_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x24 20. "KS9_UAES,Aes key" "0,1"
newline
bitfld.long 0x24 19. "KS9_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x24 18. "KS9_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x24 17. "KS9_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x24 16. "KS9_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x24 15. "KS9_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x24 14. "KS9_UKSK,KSK key" "0,1"
newline
bitfld.long 0x24 13. "KS9_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x24 10.--12. "KS9_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 9. "KS9_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x24 8. "KS9_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x24 7. "KS9_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x24 6. "KS9_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x24 5. "KS9_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x24 1.--4. 1. "KS9_RSVD0,Reserved 0"
newline
bitfld.long 0x24 0. "KS9_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x28 "CSS_KS10,Status register"
bitfld.long 0x28 30.--31. "KS10_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x28 29. "KS10_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x28 28. "KS10_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x28 27. "KS10_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x28 26. "KS10_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x28 25. "KS10_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x28 24. "KS10_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x28 23. "KS10_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x28 22. "KS10_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x28 21. "KS10_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x28 20. "KS10_UAES,Aes key" "0,1"
newline
bitfld.long 0x28 19. "KS10_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x28 18. "KS10_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x28 17. "KS10_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x28 16. "KS10_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x28 15. "KS10_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x28 14. "KS10_UKSK,KSK key" "0,1"
newline
bitfld.long 0x28 13. "KS10_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x28 10.--12. "KS10_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 9. "KS10_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x28 8. "KS10_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x28 7. "KS10_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x28 6. "KS10_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x28 5. "KS10_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x28 1.--4. 1. "KS10_RSVD0,Reserved 0"
newline
bitfld.long 0x28 0. "KS10_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x2C "CSS_KS11,Status register"
bitfld.long 0x2C 30.--31. "KS11_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x2C 29. "KS11_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x2C 28. "KS11_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x2C 27. "KS11_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x2C 26. "KS11_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x2C 25. "KS11_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x2C 24. "KS11_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x2C 23. "KS11_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x2C 22. "KS11_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x2C 21. "KS11_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x2C 20. "KS11_UAES,Aes key" "0,1"
newline
bitfld.long 0x2C 19. "KS11_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x2C 18. "KS11_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x2C 17. "KS11_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x2C 16. "KS11_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x2C 15. "KS11_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x2C 14. "KS11_UKSK,KSK key" "0,1"
newline
bitfld.long 0x2C 13. "KS11_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x2C 10.--12. "KS11_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 9. "KS11_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x2C 8. "KS11_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x2C 7. "KS11_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x2C 6. "KS11_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x2C 5. "KS11_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x2C 1.--4. 1. "KS11_RSVD0,Reserved 0"
newline
bitfld.long 0x2C 0. "KS11_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x30 "CSS_KS12,Status register"
bitfld.long 0x30 30.--31. "KS12_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x30 29. "KS12_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x30 28. "KS12_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x30 27. "KS12_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x30 26. "KS12_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x30 25. "KS12_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x30 24. "KS12_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x30 23. "KS12_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x30 22. "KS12_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x30 21. "KS12_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x30 20. "KS12_UAES,Aes key" "0,1"
newline
bitfld.long 0x30 19. "KS12_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x30 18. "KS12_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x30 17. "KS12_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x30 16. "KS12_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x30 15. "KS12_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x30 14. "KS12_UKSK,KSK key" "0,1"
newline
bitfld.long 0x30 13. "KS12_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x30 10.--12. "KS12_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 9. "KS12_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x30 8. "KS12_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x30 7. "KS12_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x30 6. "KS12_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x30 5. "KS12_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x30 1.--4. 1. "KS12_RSVD0,Reserved 0"
newline
bitfld.long 0x30 0. "KS12_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x34 "CSS_KS13,Status register"
bitfld.long 0x34 30.--31. "KS13_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x34 29. "KS13_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x34 28. "KS13_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x34 27. "KS13_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x34 26. "KS13_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x34 25. "KS13_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x34 24. "KS13_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x34 23. "KS13_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x34 22. "KS13_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x34 21. "KS13_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x34 20. "KS13_UAES,Aes key" "0,1"
newline
bitfld.long 0x34 19. "KS13_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x34 18. "KS13_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x34 17. "KS13_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x34 16. "KS13_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x34 15. "KS13_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x34 14. "KS13_UKSK,KSK key" "0,1"
newline
bitfld.long 0x34 13. "KS13_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x34 10.--12. "KS13_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 9. "KS13_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x34 8. "KS13_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x34 7. "KS13_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x34 6. "KS13_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x34 5. "KS13_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x34 1.--4. 1. "KS13_RSVD0,Reserved 0"
newline
bitfld.long 0x34 0. "KS13_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x38 "CSS_KS14,Status register"
bitfld.long 0x38 30.--31. "KS14_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x38 29. "KS14_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x38 28. "KS14_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x38 27. "KS14_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x38 26. "KS14_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x38 25. "KS14_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x38 24. "KS14_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x38 23. "KS14_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x38 22. "KS14_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x38 21. "KS14_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x38 20. "KS14_UAES,Aes key" "0,1"
newline
bitfld.long 0x38 19. "KS14_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x38 18. "KS14_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x38 17. "KS14_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x38 16. "KS14_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x38 15. "KS14_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x38 14. "KS14_UKSK,KSK key" "0,1"
newline
bitfld.long 0x38 13. "KS14_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x38 10.--12. "KS14_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 9. "KS14_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x38 8. "KS14_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x38 7. "KS14_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x38 6. "KS14_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x38 5. "KS14_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x38 1.--4. 1. "KS14_RSVD0,Reserved 0"
newline
bitfld.long 0x38 0. "KS14_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x3C "CSS_KS15,Status register"
bitfld.long 0x3C 30.--31. "KS15_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x3C 29. "KS15_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x3C 28. "KS15_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x3C 27. "KS15_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x3C 26. "KS15_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x3C 25. "KS15_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x3C 24. "KS15_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x3C 23. "KS15_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x3C 22. "KS15_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x3C 21. "KS15_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x3C 20. "KS15_UAES,Aes key" "0,1"
newline
bitfld.long 0x3C 19. "KS15_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x3C 18. "KS15_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x3C 17. "KS15_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x3C 16. "KS15_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x3C 15. "KS15_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x3C 14. "KS15_UKSK,KSK key" "0,1"
newline
bitfld.long 0x3C 13. "KS15_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x3C 10.--12. "KS15_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 9. "KS15_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x3C 8. "KS15_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x3C 7. "KS15_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x3C 6. "KS15_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x3C 5. "KS15_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x3C 1.--4. 1. "KS15_RSVD0,Reserved 0"
newline
bitfld.long 0x3C 0. "KS15_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x40 "CSS_KS16,Status register"
bitfld.long 0x40 30.--31. "KS16_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x40 29. "KS16_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x40 28. "KS16_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x40 27. "KS16_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x40 26. "KS16_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x40 25. "KS16_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x40 24. "KS16_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x40 23. "KS16_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x40 22. "KS16_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x40 21. "KS16_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x40 20. "KS16_UAES,Aes key" "0,1"
newline
bitfld.long 0x40 19. "KS16_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x40 18. "KS16_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x40 17. "KS16_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x40 16. "KS16_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x40 15. "KS16_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x40 14. "KS16_UKSK,KSK key" "0,1"
newline
bitfld.long 0x40 13. "KS16_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x40 10.--12. "KS16_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 9. "KS16_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x40 8. "KS16_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x40 7. "KS16_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x40 6. "KS16_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x40 5. "KS16_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x40 1.--4. 1. "KS16_RSVD0,Reserved 0"
newline
bitfld.long 0x40 0. "KS16_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x44 "CSS_KS17,Status register"
bitfld.long 0x44 30.--31. "KS17_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x44 29. "KS17_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x44 28. "KS17_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x44 27. "KS17_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x44 26. "KS17_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x44 25. "KS17_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x44 24. "KS17_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x44 23. "KS17_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x44 22. "KS17_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x44 21. "KS17_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x44 20. "KS17_UAES,Aes key" "0,1"
newline
bitfld.long 0x44 19. "KS17_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x44 18. "KS17_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x44 17. "KS17_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x44 16. "KS17_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x44 15. "KS17_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x44 14. "KS17_UKSK,KSK key" "0,1"
newline
bitfld.long 0x44 13. "KS17_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x44 10.--12. "KS17_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 9. "KS17_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x44 8. "KS17_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x44 7. "KS17_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x44 6. "KS17_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x44 5. "KS17_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x44 1.--4. 1. "KS17_RSVD0,Reserved 0"
newline
bitfld.long 0x44 0. "KS17_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x48 "CSS_KS18,Status register"
bitfld.long 0x48 30.--31. "KS18_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x48 29. "KS18_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x48 28. "KS18_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x48 27. "KS18_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x48 26. "KS18_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x48 25. "KS18_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x48 24. "KS18_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x48 23. "KS18_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x48 22. "KS18_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x48 21. "KS18_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x48 20. "KS18_UAES,Aes key" "0,1"
newline
bitfld.long 0x48 19. "KS18_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x48 18. "KS18_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x48 17. "KS18_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x48 16. "KS18_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x48 15. "KS18_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x48 14. "KS18_UKSK,KSK key" "0,1"
newline
bitfld.long 0x48 13. "KS18_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x48 10.--12. "KS18_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 9. "KS18_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x48 8. "KS18_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x48 7. "KS18_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x48 6. "KS18_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x48 5. "KS18_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x48 1.--4. 1. "KS18_RSVD0,Reserved 0"
newline
bitfld.long 0x48 0. "KS18_KSIZE,Key size: 0-128 1-256" "0,1"
line.long 0x4C "CSS_KS19,Status register"
bitfld.long 0x4C 30.--31. "KS19_UPPROT,Priviledge level" "0,1,2,3"
newline
bitfld.long 0x4C 29. "KS19_UDUK,Device Unique Key" "0,1"
newline
bitfld.long 0x4C 28. "KS19_UWRPOK,Ok to wrap key" "0,1"
newline
bitfld.long 0x4C 27. "KS19_UHWO,Hardware out key" "0,1"
newline
bitfld.long 0x4C 26. "KS19_UKGSRC,Supply KEYGEN source" "0,1"
newline
bitfld.long 0x4C 25. "KS19_UTLSMS,TLS Master Secret" "0,1"
newline
bitfld.long 0x4C 24. "KS19_UTLSPMS,TLS Pre Master Secret" "0,1"
newline
bitfld.long 0x4C 23. "KS19_UKUOK,Key unwrapping key" "0,1"
newline
bitfld.long 0x4C 22. "KS19_UKWK,Key wrapping key" "0,1"
newline
bitfld.long 0x4C 21. "KS19_UHMAC,Hmac key" "0,1"
newline
bitfld.long 0x4C 20. "KS19_UAES,Aes key" "0,1"
newline
bitfld.long 0x4C 19. "KS19_UECDH,Ecc diffie hellman key" "0,1"
newline
bitfld.long 0x4C 18. "KS19_UECSG,Ecc signing key" "0,1"
newline
bitfld.long 0x4C 17. "KS19_UHKDF,Derivation key for HKDF command" "0,1"
newline
bitfld.long 0x4C 16. "KS19_UCKDF,Derivation key for CKDF command" "0,1"
newline
bitfld.long 0x4C 15. "KS19_URTF,Real Time Fingerprint key" "0,1"
newline
bitfld.long 0x4C 14. "KS19_UKSK,KSK key" "0,1"
newline
bitfld.long 0x4C 13. "KS19_UCMAC,CMAC key" "0,1"
newline
bitfld.long 0x4C 10.--12. "KS19_RSVD1,Reserved 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 9. "KS19_FHWO,Hardware Feature Output" "0,1"
newline
bitfld.long 0x4C 8. "KS19_FRTN,Hardware Feature Retention" "0,1"
newline
bitfld.long 0x4C 7. "KS19_FGP,Hardware Feature General Purpose" "0,1"
newline
bitfld.long 0x4C 6. "KS19_KBASE,First slot in a multislot key" "0,1"
newline
bitfld.long 0x4C 5. "KS19_KACT,Key is active" "0,1"
newline
hexmask.long.byte 0x4C 1.--4. 1. "KS19_RSVD0,Reserved 0"
newline
bitfld.long 0x4C 0. "KS19_KSIZE,Key size: 0-128 1-256" "0,1"
group.long 0x1A4++0x7
line.long 0x0 "CSS_BOOT_ADDR,SW control for the CSS boot addr"
hexmask.long 0x0 0.--31. 1. "BOOT_ADDR,32-bit wide boot offset"
line.long 0x4 "CSS_DBG_CFG,CSS Debug Config SFR"
hexmask.long 0x4 6.--31. 1. "DBG_CFG_RFU,reserved"
newline
bitfld.long 0x4 3.--5. "DBG_CFG1,Debug Config 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0.--2. "DBG_CFG0,Debug Config 0" "0,1,2,3,4,5,6,7"
tree.end
tree "CTIMER (Standard Counter/Timers)"
base ad:0x0
tree "CTIMER0"
base ad:0x40028000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3" "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2" "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1" "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0" "0,1"
line.long 0x4 "TCR,Timer Control Register"
bitfld.long 0x4 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take effect"
bitfld.long 0x4 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take effect"
newline
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled"
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled. The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale reload value."
line.long 0x10 "PC,Prescale Counter."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value"
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "MR2RL,Reload MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "MR0RL,Reload MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register"
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value"
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register"
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 1 then 0 causes CR1 to be loaded.."
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 0 then 1 causes CR1 to be loaded.."
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC." "0: a sequence of 1 then 0 causes CR0 to be loaded..,1: Enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC." "0: a sequence of 0 then 1 causes CR0 to be loaded..,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register"
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register"
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1" "0: Do Nothing,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3" "0,1"
bitfld.long 0x0 2. "EM2,External Match 2" "0,1"
newline
bitfld.long 0x0 1. "EM1,External Match 1" "0,1"
bitfld.long 0x0 0. "EM0,External Match 0" "0,1"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register"
bitfld.long 0x0 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select" "0: Channel 0. CAPn.0 for CTIMERn,1: Channel 1. CAPn.1 for CTIMERn,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
line.long 0x4 "PWMC,PWM Control Register"
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER1"
base ad:0x40029000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3" "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2" "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1" "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0" "0,1"
line.long 0x4 "TCR,Timer Control Register"
bitfld.long 0x4 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take effect"
bitfld.long 0x4 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take effect"
newline
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled"
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled. The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale reload value."
line.long 0x10 "PC,Prescale Counter."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value"
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "MR2RL,Reload MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "MR0RL,Reload MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register"
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value"
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register"
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 1 then 0 causes CR1 to be loaded.."
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 0 then 1 causes CR1 to be loaded.."
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC." "0: a sequence of 1 then 0 causes CR0 to be loaded..,1: Enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC." "0: a sequence of 0 then 1 causes CR0 to be loaded..,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register"
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register"
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1" "0: Do Nothing,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3" "0,1"
bitfld.long 0x0 2. "EM2,External Match 2" "0,1"
newline
bitfld.long 0x0 1. "EM1,External Match 1" "0,1"
bitfld.long 0x0 0. "EM0,External Match 0" "0,1"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register"
bitfld.long 0x0 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select" "0: Channel 0. CAPn.0 for CTIMERn,1: Channel 1. CAPn.1 for CTIMERn,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
line.long 0x4 "PWMC,PWM Control Register"
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER2"
base ad:0x4002A000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3" "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2" "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1" "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0" "0,1"
line.long 0x4 "TCR,Timer Control Register"
bitfld.long 0x4 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take effect"
bitfld.long 0x4 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take effect"
newline
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled"
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled. The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale reload value."
line.long 0x10 "PC,Prescale Counter."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value"
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "MR2RL,Reload MR2" "0: Disabled,1: Enabled"
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bitfld.long 0x14 25. "MR1RL,Reload MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "MR0RL,Reload MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register"
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value"
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register"
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
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bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 1 then 0 causes CR1 to be loaded.."
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 0 then 1 causes CR1 to be loaded.."
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC." "0: a sequence of 1 then 0 causes CR0 to be loaded..,1: Enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC." "0: a sequence of 0 then 1 causes CR0 to be loaded..,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register"
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register"
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
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bitfld.long 0x0 6.--7. "EMC1,External Match Control 1" "0: Do Nothing,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3" "0,1"
bitfld.long 0x0 2. "EM2,External Match 2" "0,1"
newline
bitfld.long 0x0 1. "EM1,External Match 1" "0,1"
bitfld.long 0x0 0. "EM0,External Match 0" "0,1"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register"
bitfld.long 0x0 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select" "0: Channel 0. CAPn.0 for CTIMERn,1: Channel 1. CAPn.1 for CTIMERn,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
line.long 0x4 "PWMC,PWM Control Register"
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value."
repeat.end
tree.end
tree "CTIMER3"
base ad:0x4002B000
group.long 0x0++0x17
line.long 0x0 "IR,Interrupt Register."
bitfld.long 0x0 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1"
bitfld.long 0x0 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1"
newline
bitfld.long 0x0 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1"
bitfld.long 0x0 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1"
newline
bitfld.long 0x0 3. "MR3INT,Interrupt flag for match channel 3" "0,1"
bitfld.long 0x0 2. "MR2INT,Interrupt flag for match channel 2" "0,1"
newline
bitfld.long 0x0 1. "MR1INT,Interrupt flag for match channel 1" "0,1"
bitfld.long 0x0 0. "MR0INT,Interrupt flag for match channel 0" "0,1"
line.long 0x4 "TCR,Timer Control Register"
bitfld.long 0x4 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take effect"
bitfld.long 0x4 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take effect"
newline
bitfld.long 0x4 1. "CRST,Counter reset." "0: Disabled. Do nothing.,1: Enabled"
bitfld.long 0x4 0. "CEN,Counter enable." "0: Disabled. The counters are disabled.,1: Enabled. The Timer Counter and Prescale Counter.."
line.long 0x8 "TC,Timer Counter"
hexmask.long 0x8 0.--31. 1. "TCVAL,Timer counter value."
line.long 0xC "PR,Prescale Register"
hexmask.long 0xC 0.--31. 1. "PRVAL,Prescale reload value."
line.long 0x10 "PC,Prescale Counter."
hexmask.long 0x10 0.--31. 1. "PCVAL,Prescale counter value"
line.long 0x14 "MCR,Match Control Register"
bitfld.long 0x14 27. "MR3RL,Reload MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 26. "MR2RL,Reload MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 25. "MR1RL,Reload MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 24. "MR0RL,Reload MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled"
bitfld.long 0x14 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled"
bitfld.long 0x14 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled"
bitfld.long 0x14 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled"
newline
bitfld.long 0x14 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled"
bitfld.long 0x14 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x18)++0x3
line.long 0x0 "MR[$1],Match Register"
hexmask.long 0x0 0.--31. 1. "MATCH,Timer counter match value"
repeat.end
group.long 0x28++0x3
line.long 0x0 "CCR,Capture Control Register"
bitfld.long 0x0 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt." "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 1 then 0 causes CR1 to be loaded.."
newline
bitfld.long 0x0 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC." "0: Disabled,1: a sequence of 0 then 1 causes CR1 to be loaded.."
bitfld.long 0x0 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC." "0: a sequence of 1 then 0 causes CR0 to be loaded..,1: Enabled"
bitfld.long 0x0 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC." "0: a sequence of 0 then 1 causes CR0 to be loaded..,1: Enabled"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x2C)++0x3
line.long 0x0 "CR[$1],Capture Register"
hexmask.long 0x0 0.--31. 1. "CAP,Timer counter capture value."
repeat.end
group.long 0x3C++0x3
line.long 0x0 "EMR,External Match Register"
bitfld.long 0x0 10.--11. "EMC3,External Match Control 3" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 8.--9. "EMC2,External Match Control 2" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 6.--7. "EMC1,External Match Control 1" "0: Do Nothing,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
bitfld.long 0x0 4.--5. "EMC0,External Match Control 0" "0: Do Nothing.,1: Clear. Clear the corresponding External Match..,2: Set. Set the corresponding External Match..,3: Toggle. Toggle the corresponding External Match.."
newline
bitfld.long 0x0 3. "EM3,External Match 3" "0,1"
bitfld.long 0x0 2. "EM2,External Match 2" "0,1"
newline
bitfld.long 0x0 1. "EM1,External Match 1" "0,1"
bitfld.long 0x0 0. "EM0,External Match 0" "0,1"
group.long 0x70++0x7
line.long 0x0 "CTCR,Count Control Register"
bitfld.long 0x0 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge. Rising edge of the signal..,1: Channel 0 Falling Edge. Falling edge of the..,2: Channel 1 Rising Edge. Rising edge of the signal..,3: Channel 1 Falling Edge. Falling edge of the..,4: Channel 2 Rising Edge. Rising edge of the signal..,5: Channel 2 Falling Edge. Falling edge of the..,?,?"
bitfld.long 0x0 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1"
newline
bitfld.long 0x0 2.--3. "CINSEL,Count Input Select" "0: Channel 0. CAPn.0 for CTIMERn,1: Channel 1. CAPn.1 for CTIMERn,2: Channel 2. CAPn.2 for CTIMERn,3: Channel 3. CAPn.3 for CTIMERn"
bitfld.long 0x0 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting." "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
line.long 0x4 "PWMC,PWM Control Register"
bitfld.long 0x4 3. "PWMEN3,PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle." "0: Match. CTIMERn_MAT3 is controlled by EM3.,1: PWM. PWM mode is enabled for CT132Bn_MAT3."
bitfld.long 0x4 2. "PWMEN2,PWM mode enable for channel2." "0: Match. CTIMERn_MAT2 is controlled by EM2.,1: PWM. PWM mode is enabled for CTIMERn_MAT2."
newline
bitfld.long 0x4 1. "PWMEN1,PWM mode enable for channel1." "0: Match. CTIMERn_MAT01 is controlled by EM1.,1: PWM. PWM mode is enabled for CTIMERn_MAT1."
bitfld.long 0x4 0. "PWMEN0,PWM mode enable for channel0." "0: Match. CTIMERn_MAT0 is controlled by EM0.,1: PWM. PWM mode is enabled for CTIMERn_MAT0."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x78)++0x3
line.long 0x0 "MSR[$1],Match Shadow Register"
hexmask.long 0x0 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value."
repeat.end
tree.end
tree.end
tree "DAC (Digital to Analog Converter)"
base ad:0x40038200
group.long 0x0++0x3
line.long 0x0 "CTRL,DAC Control Register"
bitfld.long 0x0 0. "REF_SEL,Reference selector" "0: internal reference,1: external reference"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,DAC Status Register"
bitfld.long 0x0 1. "B_DV,DACB conversion status" "0: channel B conversion is not done,1: channel B conversion complete"
bitfld.long 0x0 0. "A_DV,DACA conversion status." "0: channel A conversion is not done,1: channel A conversion complete"
group.long 0x8++0xF
line.long 0x0 "ACTRL,Channel A Control Register"
bitfld.long 0x0 18.--19. "A_RANGE,Output voltage range control with Internal/External reference" "0: 0.16+(0.64*input code/1023) with..,1: 0.19+(1.01*input code /1023) with..,2: 0.19+(1.01*input code /1023) with..,3: 0.18+(1.42*input code /1023) with.."
bitfld.long 0x0 16.--17. "A_WAVE,Channel A wave type select." "0: no description available,1: triangle wave,2: sine wave,3: no description available"
newline
bitfld.long 0x0 14.--15. "A_TRIA_STEP_SEL,Channel A triangle wave step selector." "0: 1,1: 3,2: 15,3: 511"
hexmask.long.byte 0x0 10.--13. 1. "A_TRIA_MAMP_SEL,Channel A triangle wave max amplitude selector."
newline
bitfld.long 0x0 9. "A_TRIA_HALF,Channel A triangle wave type selector." "0: full triangle,1: half triangle"
bitfld.long 0x0 8. "A_TIME_MODE,Channel A Mode" "0: non-timing related,1: timing related"
newline
bitfld.long 0x0 7. "A_DEN,Channel A DMA enable" "0: DMA data transfer disabled,1: DMA data transfer enabled"
bitfld.long 0x0 5.--6. "A_TRIG_TYP,Channel A trigger type" "?,1: rising edge trigger,2: falling edge trigger,3: both rising and falling edge trigger"
newline
bitfld.long 0x0 3.--4. "A_TRIG_SEL,Channel A trigger selector" "0,1,2,3"
bitfld.long 0x0 2. "A_TRIG_EN,Channel A trigger enable" "0: Channel A conversion triggered by external event..,1: Channel A conversion triggered by external event.."
newline
bitfld.long 0x0 1. "A_IO_EN,Channel A conversion output to pad enable" "0: disable channel A conversion result to GPIO,1: enable channel A conversion result to GPIO"
bitfld.long 0x0 0. "A_EN,Channel A Enable/Disable signal" "0: disable channel A conversion,1: enable channel A conversion"
line.long 0x4 "BCTRL,Channel B Control Register"
bitfld.long 0x4 9.--10. "B_WAVE,Channel B wave type select." "0: no description available,?,?,3: differential mode with channel A"
bitfld.long 0x4 8. "B_TIME_MODE,Channel B Mode" "0: non-timing related,1: timing related"
newline
bitfld.long 0x4 7. "B_DEN,Channel B DMA enable" "0: DMA data transfer disabled,1: DMA data transfer enabled"
bitfld.long 0x4 5.--6. "B_TRIG_TYP,Channel B trigger type" "?,1: rising edge trigger,2: falling edge trigger,3: both rising and falling edge trigger"
newline
bitfld.long 0x4 3.--4. "B_TRIG_SEL,Channel B trigger selector" "0,1,2,3"
bitfld.long 0x4 2. "B_TRIG_EN,Channel B trigger enable" "0: Channel B conversion triggered by external event..,1: Channel B conversion triggered by external event.."
newline
bitfld.long 0x4 1. "B_IO_EN,Channel B conversion output to pad enable" "0: disable channel B conversion result to GPIO,1: enable channel B conversion result to GPIO"
bitfld.long 0x4 0. "B_EN,Channel B Enable/Disable signal" "0: disable channel B conversion,1: enable channel B conversion"
line.long 0x8 "ADATA,Channel A Data Register"
hexmask.long.word 0x8 0.--9. 1. "A_DATA,Channel A Data input"
line.long 0xC "BDATA,Channel B Data Register"
hexmask.long.word 0xC 0.--9. 1. "B_DATA,Channel B Data input"
rgroup.long 0x18++0x3
line.long 0x0 "ISR,Interrupt Status Register"
bitfld.long 0x0 4. "TRIA_OVFL_INT,Triangle Overflow" "0,1"
bitfld.long 0x0 3. "B_TO_INT,Channel B Timeout" "0,1"
newline
bitfld.long 0x0 2. "A_TO_INT,Channel A Timeout" "0,1"
bitfld.long 0x0 1. "B_RDY_INT,Channel B Data Ready" "0,1"
newline
bitfld.long 0x0 0. "A_RDY_INT,Channel A Data Ready" "0,1"
group.long 0x1C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
bitfld.long 0x0 4. "TRIA_OVFL_INT_MSK,Triangle Overflow Mask" "0,1"
bitfld.long 0x0 3. "B_TO_INT_MSK,Channel B Timeout Mask" "0,1"
newline
bitfld.long 0x0 2. "A_TO_INT_MSK,Channel A Timeout Mask" "0,1"
bitfld.long 0x0 1. "B_RDY_INT_MSK,Channel B Data Ready Mask" "0,1"
newline
bitfld.long 0x0 0. "A_RDY_INT_MSK,Channel A Data Ready Mask" "0,1"
rgroup.long 0x20++0x3
line.long 0x0 "IRSR,Interrupt Raw Status Register"
bitfld.long 0x0 4. "TRIA_OVFL_INT_RAW,Triangle Overflow Raw" "0,1"
bitfld.long 0x0 3. "B_TO_INT_RAW,Channel B Timeout Raw" "0,1"
newline
bitfld.long 0x0 2. "A_TO_INT_RAW,Channel A Timeout Raw" "0,1"
bitfld.long 0x0 1. "B_RDY_INT_RAW,Channel B Data Ready Raw" "0,1"
newline
bitfld.long 0x0 0. "A_RDY_INT_RAW,Channel A Data Ready Raw" "0,1"
group.long 0x24++0xB
line.long 0x0 "ICR,Interrupt Clear Register"
bitfld.long 0x0 4. "TRIA_OVFL_INT_CLR,Triangle Overflow Clear" "0,1"
bitfld.long 0x0 3. "B_TO_INT_CLR,Channel B Timeout Clear" "0,1"
newline
bitfld.long 0x0 2. "A_TO_INT_CLR,Channel A Timeout Clear" "0,1"
bitfld.long 0x0 1. "B_RDY_INT_CLR,Channel B Data Ready Clear" "0,1"
newline
bitfld.long 0x0 0. "A_RDY_INT_CLR,Channel A Data Ready Clear" "0,1"
line.long 0x4 "CLK,Clock Register"
bitfld.long 0x4 4. "SOFT_CLK_RST,Soft reset for clock divider" "0: no description available,1: no description available"
bitfld.long 0x4 1.--2. "CLK_CTRL,DAC conversion rate selector." "0: 62.5K,1: 125K,2: 250K,3: 500K"
line.long 0x8 "RST,Soft Reset Register"
bitfld.long 0x8 1. "B_SOFT_RST,Soft reset for DAC channel B active high" "0: no action,1: no description available"
bitfld.long 0x8 0. "A_SOFT_RST,Soft reset for DAC channel A active high" "0: no action,1: no description available"
tree.end
tree "DBGMAILBOX"
base ad:0x4010F000
group.long 0x0++0xB
line.long 0x0 "CSW,Command and status word"
bitfld.long 0x0 5. "CHIP_RESET_REQ,Chip Reset Request" "0,1"
bitfld.long 0x0 4. "SOFT_RESET,Soft Reset" "0,1"
newline
bitfld.long 0x0 3. "AHB_OR_ERR,AHB Overrun Error" "0: No AHB Overrun Error,1: AHB Overrun Error. An AHB overrun occurred."
bitfld.long 0x0 2. "DBG_OR_ERR,Debug Overrun Error" "0: No Debug Overrun error,1: Debug Overrun Error. A debug overrun occurred."
newline
bitfld.long 0x0 1. "REQ_PENDING,Request Pending" "0: No Request Pending,1: Request for Re-synchronization Pending"
bitfld.long 0x0 0. "RESYNCH_REQ,Re-synchronization Request" "0: No Request,1: Request for re-synchronization"
line.long 0x4 "REQUEST,Request Value"
hexmask.long 0x4 0.--31. 1. "REQUEST,Request Value"
line.long 0x8 "RETURN,Return Value"
hexmask.long 0x8 0.--31. 1. "RET,Return Value"
rgroup.long 0xFC++0x3
line.long 0x0 "ID,Identification"
hexmask.long 0x0 0.--31. 1. "ID,Identification Value"
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x0
tree "DMA0"
base ad:0x40104000
group.long 0x0++0x3
line.long 0x0 "CTRL,DMA control"
bitfld.long 0x0 0. "ENABLE,DMA controller master enable." "0: DMA controller is disabled.,1: Enabled."
rgroup.long 0x4++0x3
line.long 0x0 "INTSTAT,Interrupt status"
bitfld.long 0x0 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending." "0: No error interrupts are pending.,1: At least one error interrupt is pending."
bitfld.long 0x0 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending." "0: No enabled interrupts are pending.,1: At least one enabled interrupt is pending."
group.long 0x8++0x3
line.long 0x0 "SRAMBASE,SRAM address of the channel configuration table"
hexmask.long.tbyte 0x0 9.--31. 1. "OFFSET,Offset"
group.long 0x20++0xF
line.long 0x0 "ENABLESET0,Channel Enable read and set for all DMA channels"
bitfld.long 0x0 31. "ENABLE31,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 30. "ENABLE30,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 29. "ENABLE29,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 28. "ENABLE28,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 27. "ENABLE27,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 26. "ENABLE26,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 25. "ENABLE25,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 24. "ENABLE24,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 23. "ENABLE23,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 22. "ENABLE22,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 21. "ENABLE21,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 20. "ENABLE20,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 19. "ENABLE19,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 18. "ENABLE18,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 17. "ENABLE17,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 16. "ENABLE16,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
line.long 0x4 "ENABLESET1,Channel Enable read and set for all DMA channels"
bitfld.long 0x4 0. "ENABLE32,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
line.long 0x8 "ENABLECLR0,Channel Enable Clear for all DMA channels"
eventfld.long 0x8 31. "CLR31,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 30. "CLR30,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 29. "CLR29,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 28. "CLR28,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 27. "CLR27,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 26. "CLR26,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 25. "CLR25,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 24. "CLR24,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 23. "CLR23,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 22. "CLR22,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 21. "CLR21,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 20. "CLR20,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 19. "CLR19,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 18. "CLR18,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 17. "CLR17,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 16. "CLR16,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
line.long 0xC "ENABLECLR1,Channel Enable Clear for all DMA channels"
eventfld.long 0xC 0. "CLR32,Writing ones to this register clears the corresponding bits in ENABLESET1." "0: No effect.,1: DMA channel is cleared."
rgroup.long 0x30++0xF
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels"
bitfld.long 0x0 31. "ACTIVE31,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 30. "ACTIVE30,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 29. "ACTIVE29,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 28. "ACTIVE28,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
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bitfld.long 0x0 27. "ACTIVE27,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 26. "ACTIVE26,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 25. "ACTIVE25,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 24. "ACTIVE24,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 23. "ACTIVE23,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 22. "ACTIVE22,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 21. "ACTIVE21,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 20. "ACTIVE20,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 19. "ACTIVE19,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 18. "ACTIVE18,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 17. "ACTIVE17,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 16. "ACTIVE16,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 15. "ACTIVE15,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 14. "ACTIVE14,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 13. "ACTIVE13,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 12. "ACTIVE12,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 11. "ACTIVE11,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 10. "ACTIVE10,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 9. "ACTIVE9,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 8. "ACTIVE8,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 7. "ACTIVE7,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 6. "ACTIVE6,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 5. "ACTIVE5,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 4. "ACTIVE4,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 3. "ACTIVE3,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 2. "ACTIVE2,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 1. "ACTIVE1,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 0. "ACTIVE0,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
line.long 0x4 "ACTIVE1,Channel Active status for all DMA channels"
bitfld.long 0x4 0. "ACTIVE32,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
line.long 0x8 "BUSY0,Channel Busy status for all DMA channels"
bitfld.long 0x8 31. "BUSY31,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 30. "BUSY30,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 29. "BUSY29,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 28. "BUSY28,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 27. "BUSY27,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 26. "BUSY26,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 25. "BUSY25,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 24. "BUSY24,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 23. "BUSY23,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 22. "BUSY22,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 21. "BUSY21,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 20. "BUSY20,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 19. "BUSY19,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 18. "BUSY18,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 17. "BUSY17,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 16. "BUSY16,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 15. "BUSY15,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 14. "BUSY14,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 13. "BUSY13,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 12. "BUSY12,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 11. "BUSY11,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 10. "BUSY10,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 9. "BUSY9,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 8. "BUSY8,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 7. "BUSY7,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 6. "BUSY6,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 5. "BUSY5,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 4. "BUSY4,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 3. "BUSY3,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 2. "BUSY2,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 1. "BUSY1,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 0. "BUSY0,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
line.long 0xC "BUSY1,Channel Busy status for all DMA channels"
bitfld.long 0xC 0. "BUSY32,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
group.long 0x40++0xF
line.long 0x0 "ERRINT0,Error Interrupt status for all DMA channels"
bitfld.long 0x0 31. "ERR31,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 30. "ERR30,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 29. "ERR29,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 28. "ERR28,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 27. "ERR27,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 26. "ERR26,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 25. "ERR25,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 24. "ERR24,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 23. "ERR23,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 22. "ERR22,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 21. "ERR21,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 20. "ERR20,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 19. "ERR19,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 18. "ERR18,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 17. "ERR17,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 16. "ERR16,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 15. "ERR15,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 14. "ERR14,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 13. "ERR13,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 12. "ERR12,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 11. "ERR11,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 10. "ERR10,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 9. "ERR9,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 8. "ERR8,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 7. "ERR7,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 6. "ERR6,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 5. "ERR5,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 4. "ERR4,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 3. "ERR3,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 2. "ERR2,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 1. "ERR1,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 0. "ERR0,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
line.long 0x4 "ERRINT1,Error Interrupt status for all DMA channels"
bitfld.long 0x4 0. "ERR32,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
line.long 0x8 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
bitfld.long 0x8 31. "INTEN31,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 30. "INTEN30,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 29. "INTEN29,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 28. "INTEN28,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 27. "INTEN27,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 26. "INTEN26,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 25. "INTEN25,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 24. "INTEN24,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 23. "INTEN23,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 22. "INTEN22,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 21. "INTEN21,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 20. "INTEN20,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 19. "INTEN19,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 18. "INTEN18,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 17. "INTEN17,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 16. "INTEN16,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 15. "INTEN15,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 14. "INTEN14,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 13. "INTEN13,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 12. "INTEN12,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 11. "INTEN11,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 10. "INTEN10,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 9. "INTEN9,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 8. "INTEN8,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 7. "INTEN7,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 6. "INTEN6,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 5. "INTEN5,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 4. "INTEN4,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 3. "INTEN3,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 2. "INTEN2,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 1. "INTEN1,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 0. "INTEN0,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
line.long 0xC "INTENSET1,Interrupt Enable read and Set for all DMA channels"
bitfld.long 0xC 0. "INTEN32,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
wgroup.long 0x50++0x7
line.long 0x0 "INTENCLR0,Interrupt Enable Clear for all DMA channels"
bitfld.long 0x0 31. "CLR31,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 30. "CLR30,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 29. "CLR29,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 28. "CLR28,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 27. "CLR27,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 26. "CLR26,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 25. "CLR25,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 24. "CLR24,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 23. "CLR23,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 22. "CLR22,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 21. "CLR21,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 20. "CLR20,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 19. "CLR19,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 18. "CLR18,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 17. "CLR17,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 16. "CLR16,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
line.long 0x4 "INTENCLR1,Interrupt Enable Clear for all DMA channels"
bitfld.long 0x4 0. "CLR32,Writing ones to this register clears corresponding bits in the DMAIntEnSet1." "0,1"
group.long 0x58++0xF
line.long 0x0 "INTA0,Interrupt A status for all DMA channels"
bitfld.long 0x0 31. "INTA31,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 30. "INTA30,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 29. "INTA29,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 28. "INTA28,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 27. "INTA27,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 26. "INTA26,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 25. "INTA25,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 24. "INTA24,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 23. "INTA23,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 22. "INTA22,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 21. "INTA21,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 20. "INTA20,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 19. "INTA19,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 18. "INTA18,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 17. "INTA17,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 16. "INTA16,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 15. "INTA15,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 14. "INTA14,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 13. "INTA13,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 12. "INTA12,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 11. "INTA11,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 10. "INTA10,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 9. "INTA9,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 8. "INTA8,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 7. "INTA7,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 6. "INTA6,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 5. "INTA5,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 4. "INTA4,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 3. "INTA3,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 2. "INTA2,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 1. "INTA1,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 0. "INTA0,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
line.long 0x4 "INTA1,Interrupt A status for all DMA channels"
bitfld.long 0x4 0. "INTA32,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
line.long 0x8 "INTB0,Interrupt B status for all DMA channels"
bitfld.long 0x8 31. "INTB31,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 30. "INTB30,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 29. "INTB29,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 28. "INTB28,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 27. "INTB27,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 26. "INTB26,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 25. "INTB25,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 24. "INTB24,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 23. "INTB23,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 22. "INTB22,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 21. "INTB21,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 20. "INTB20,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 19. "INTB19,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 18. "INTB18,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 17. "INTB17,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 16. "INTB16,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 15. "INTB15,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 14. "INTB14,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 13. "INTB13,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 12. "INTB12,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 11. "INTB11,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 10. "INTB10,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 9. "INTB9,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 8. "INTB8,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 7. "INTB7,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 6. "INTB6,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 5. "INTB5,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 4. "INTB4,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 3. "INTB3,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 2. "INTB2,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 1. "INTB1,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 0. "INTB0,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
line.long 0xC "INTB1,Interrupt B status for all DMA channels"
bitfld.long 0xC 0. "INTB0,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
wgroup.long 0x68++0x17
line.long 0x0 "SETVALID0,Set ValidPending control bits for all DMA channels"
bitfld.long 0x0 31. "SETVALID31,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 30. "SETVALID30,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 29. "SETVALID29,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 28. "SETVALID28,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 27. "SETVALID27,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 26. "SETVALID26,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 25. "SETVALID25,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 24. "SETVALID24,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 23. "SETVALID23,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 22. "SETVALID22,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 21. "SETVALID21,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 20. "SETVALID20,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 19. "SETVALID19,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 18. "SETVALID18,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 17. "SETVALID17,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 16. "SETVALID16,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 15. "SETVALID15,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 14. "SETVALID14,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 13. "SETVALID13,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 12. "SETVALID12,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 11. "SETVALID11,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 10. "SETVALID10,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 9. "SETVALID9,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 8. "SETVALID8,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 7. "SETVALID7,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 6. "SETVALID6,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 5. "SETVALID5,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 4. "SETVALID4,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 3. "SETVALID3,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 2. "SETVALID2,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 1. "SETVALID1,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 0. "SETVALID0,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
line.long 0x4 "SETVALID1,Set ValidPending control bits for all DMA channels"
bitfld.long 0x4 0. "SETVALID32,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
line.long 0x8 "SETTRIG0,Set Trigger control bits for all DMA channels"
bitfld.long 0x8 31. "SETTRIG31,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 30. "SETTRIG30,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 29. "SETTRIG29,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 28. "SETTRIG28,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 27. "SETTRIG27,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 26. "SETTRIG26,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 25. "SETTRIG25,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 24. "SETTRIG24,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 23. "SETTRIG23,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 22. "SETTRIG22,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 21. "SETTRIG21,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 20. "SETTRIG20,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 19. "SETTRIG19,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 18. "SETTRIG18,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 17. "SETTRIG17,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 16. "SETTRIG16,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 15. "SETTRIG15,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 14. "SETTRIG14,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 13. "SETTRIG13,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 12. "SETTRIG12,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 11. "SETTRIG11,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 10. "SETTRIG10,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 9. "SETTRIG9,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 8. "SETTRIG8,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 7. "SETTRIG7,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 6. "SETTRIG6,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 5. "SETTRIG5,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 4. "SETTRIG4,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 3. "SETTRIG3,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 2. "SETTRIG2,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 1. "SETTRIG1,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 0. "SETTRIG0,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
line.long 0xC "SETTRIG1,Set Trigger control bits for all DMA channels"
bitfld.long 0xC 0. "SETTRIG32,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
line.long 0x10 "ABORT0,Channel Abort control for all DMA channels"
bitfld.long 0x10 31. "ABORT31,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 30. "ABORT30,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 29. "ABORT29,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 28. "ABORT28,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 27. "ABORT27,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 26. "ABORT26,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 25. "ABORT25,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 24. "ABORT24,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 23. "ABORT23,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 22. "ABORT22,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 21. "ABORT21,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 20. "ABORT20,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 19. "ABORT19,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 18. "ABORT18,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 17. "ABORT17,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 16. "ABORT16,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 15. "ABORT15,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 14. "ABORT14,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 13. "ABORT13,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 12. "ABORT12,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 11. "ABORT11,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 10. "ABORT10,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 9. "ABORT9,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 8. "ABORT8,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 7. "ABORT7,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 6. "ABORT6,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 5. "ABORT5,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 4. "ABORT4,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 3. "ABORT3,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 2. "ABORT2,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 1. "ABORT1,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 0. "ABORT0,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
line.long 0x14 "ABORT1,Channel Abort control for all DMA channels"
bitfld.long 0x14 0. "ABORT32,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40104400 ad:0x40104410 ad:0x40104420 ad:0x40104430 ad:0x40104440 ad:0x40104450 ad:0x40104460 ad:0x40104470 ad:0x40104480 ad:0x40104490 ad:0x401044A0 ad:0x401044B0 ad:0x401044C0 ad:0x401044D0 ad:0x401044E0 ad:0x401044F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel"
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap." "0: Disabled.,1: Enabled."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst." "0: Single transfer.,1: Burst transfer."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type." "0: Edge. Hardware trigger is edge triggered.,1: Level."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for channel." "0: Hardware triggering not used for channel.,1: Hardware triggering used for channel."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable." "0: Peripheral DMA requests disabled.,1: Peripheral DMA requests enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x0 2. "TRIG,Trigger flag." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel." "0: No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded."
bitfld.long 0x0 14.--15. "DSTINC,Destination address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
newline
bitfld.long 0x0 12.--13. "SRCINC,Source address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit.,1: 16-bit.,2: 32-bit.,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for channel." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for channel." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared.,1: Cleared."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set.,1: Set."
newline
bitfld.long 0x0 1. "RELOAD,Reload." "0: Disabled. The channels' control structure should..,1: Enabled. The channels' control structure should.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag." "0: Not valid.,1: Valid."
tree.end
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40104500 ad:0x40104510 ad:0x40104520 ad:0x40104530 ad:0x40104540 ad:0x40104550 ad:0x40104560 ad:0x40104570 ad:0x40104580 ad:0x40104590 ad:0x401045A0 ad:0x401045B0 ad:0x401045C0 ad:0x401045D0 ad:0x401045E0 ad:0x401045F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel"
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap." "0: Disabled.,1: Enabled."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst." "0: Single transfer.,1: Burst transfer."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type." "0: Edge. Hardware trigger is edge triggered.,1: Level."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for channel." "0: Hardware triggering not used for channel.,1: Hardware triggering used for channel."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable." "0: Peripheral DMA requests disabled.,1: Peripheral DMA requests enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x0 2. "TRIG,Trigger flag." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel." "0: No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded."
bitfld.long 0x0 14.--15. "DSTINC,Destination address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
newline
bitfld.long 0x0 12.--13. "SRCINC,Source address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit.,1: 16-bit.,2: 32-bit.,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for channel." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for channel." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared.,1: Cleared."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set.,1: Set."
newline
bitfld.long 0x0 1. "RELOAD,Reload." "0: Disabled. The channels' control structure should..,1: Enabled. The channels' control structure should.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag." "0: Not valid.,1: Valid."
tree.end
repeat.end
tree "CHANNEL[32] (no description available)"
base ad:0x40104600
group.long 0x0++0x3
line.long 0x0 "CFG,Configuration register for DMA channel"
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap." "0: Disabled.,1: Enabled."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst." "0: Single transfer.,1: Burst transfer."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type." "0: Edge. Hardware trigger is edge triggered.,1: Level."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for channel." "0: Hardware triggering not used for channel.,1: Hardware triggering used for channel."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable." "0: Peripheral DMA requests disabled.,1: Peripheral DMA requests enabled."
rgroup.long 0x4++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x0 2. "TRIG,Trigger flag." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel." "0: No effect on DMA operation.,1: Valid pending."
group.long 0x8++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded."
bitfld.long 0x0 14.--15. "DSTINC,Destination address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
newline
bitfld.long 0x0 12.--13. "SRCINC,Source address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit.,1: 16-bit.,2: 32-bit.,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for channel." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for channel." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared.,1: Cleared."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set.,1: Set."
newline
bitfld.long 0x0 1. "RELOAD,Reload." "0: Disabled. The channels' control structure should..,1: Enabled. The channels' control structure should.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag." "0: Not valid.,1: Valid."
tree.end
tree.end
tree "DMA1"
base ad:0x40105000
group.long 0x0++0x3
line.long 0x0 "CTRL,DMA control"
bitfld.long 0x0 0. "ENABLE,DMA controller master enable." "0: DMA controller is disabled.,1: Enabled."
rgroup.long 0x4++0x3
line.long 0x0 "INTSTAT,Interrupt status"
bitfld.long 0x0 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending." "0: No error interrupts are pending.,1: At least one error interrupt is pending."
bitfld.long 0x0 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending." "0: No enabled interrupts are pending.,1: At least one enabled interrupt is pending."
group.long 0x8++0x3
line.long 0x0 "SRAMBASE,SRAM address of the channel configuration table"
hexmask.long.tbyte 0x0 9.--31. 1. "OFFSET,Offset"
group.long 0x20++0xF
line.long 0x0 "ENABLESET0,Channel Enable read and set for all DMA channels"
bitfld.long 0x0 31. "ENABLE31,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 30. "ENABLE30,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 29. "ENABLE29,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 28. "ENABLE28,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 27. "ENABLE27,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 26. "ENABLE26,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 25. "ENABLE25,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 24. "ENABLE24,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 23. "ENABLE23,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 22. "ENABLE22,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 21. "ENABLE21,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 20. "ENABLE20,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 19. "ENABLE19,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 18. "ENABLE18,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 17. "ENABLE17,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 16. "ENABLE16,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
newline
bitfld.long 0x0 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
bitfld.long 0x0 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
line.long 0x4 "ENABLESET1,Channel Enable read and set for all DMA channels"
bitfld.long 0x4 0. "ENABLE32,Enable for DMA channel" "0: DMA channel is disabled.,1: DMA channel is enabled."
line.long 0x8 "ENABLECLR0,Channel Enable Clear for all DMA channels"
eventfld.long 0x8 31. "CLR31,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 30. "CLR30,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 29. "CLR29,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 28. "CLR28,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 27. "CLR27,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 26. "CLR26,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 25. "CLR25,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 24. "CLR24,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 23. "CLR23,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 22. "CLR22,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 21. "CLR21,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 20. "CLR20,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 19. "CLR19,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 18. "CLR18,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 17. "CLR17,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 16. "CLR16,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
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eventfld.long 0x8 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
newline
eventfld.long 0x8 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
eventfld.long 0x8 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0." "0: No effect.,1: DMA channel is cleared."
line.long 0xC "ENABLECLR1,Channel Enable Clear for all DMA channels"
eventfld.long 0xC 0. "CLR32,Writing ones to this register clears the corresponding bits in ENABLESET1." "0: No effect.,1: DMA channel is cleared."
rgroup.long 0x30++0xF
line.long 0x0 "ACTIVE0,Channel Active status for all DMA channels"
bitfld.long 0x0 31. "ACTIVE31,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 30. "ACTIVE30,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 29. "ACTIVE29,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 28. "ACTIVE28,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 27. "ACTIVE27,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 26. "ACTIVE26,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 25. "ACTIVE25,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 24. "ACTIVE24,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
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bitfld.long 0x0 23. "ACTIVE23,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 22. "ACTIVE22,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 21. "ACTIVE21,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 20. "ACTIVE20,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
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bitfld.long 0x0 19. "ACTIVE19,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 18. "ACTIVE18,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 17. "ACTIVE17,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 16. "ACTIVE16,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 15. "ACTIVE15,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 14. "ACTIVE14,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 13. "ACTIVE13,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 12. "ACTIVE12,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 11. "ACTIVE11,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 10. "ACTIVE10,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 9. "ACTIVE9,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 8. "ACTIVE8,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 7. "ACTIVE7,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 6. "ACTIVE6,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 5. "ACTIVE5,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 4. "ACTIVE4,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
newline
bitfld.long 0x0 3. "ACTIVE3,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 2. "ACTIVE2,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
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bitfld.long 0x0 1. "ACTIVE1,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
bitfld.long 0x0 0. "ACTIVE0,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
line.long 0x4 "ACTIVE1,Channel Active status for all DMA channels"
bitfld.long 0x4 0. "ACTIVE32,Active flag for DMA channel." "0: DMA channel is not active.,1: DMA channel is active."
line.long 0x8 "BUSY0,Channel Busy status for all DMA channels"
bitfld.long 0x8 31. "BUSY31,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 30. "BUSY30,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 29. "BUSY29,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 28. "BUSY28,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 27. "BUSY27,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 26. "BUSY26,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 25. "BUSY25,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 24. "BUSY24,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 23. "BUSY23,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 22. "BUSY22,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 21. "BUSY21,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 20. "BUSY20,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 19. "BUSY19,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 18. "BUSY18,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 17. "BUSY17,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 16. "BUSY16,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 15. "BUSY15,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 14. "BUSY14,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 13. "BUSY13,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 12. "BUSY12,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 11. "BUSY11,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 10. "BUSY10,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 9. "BUSY9,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 8. "BUSY8,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 7. "BUSY7,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 6. "BUSY6,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 5. "BUSY5,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 4. "BUSY4,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 3. "BUSY3,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 2. "BUSY2,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
newline
bitfld.long 0x8 1. "BUSY1,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
bitfld.long 0x8 0. "BUSY0,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
line.long 0xC "BUSY1,Channel Busy status for all DMA channels"
bitfld.long 0xC 0. "BUSY32,Busy flag for DMA channel." "0: DMA channel is not busy.,1: DMA channel is busy."
group.long 0x40++0xF
line.long 0x0 "ERRINT0,Error Interrupt status for all DMA channels"
bitfld.long 0x0 31. "ERR31,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 30. "ERR30,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 29. "ERR29,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 28. "ERR28,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 27. "ERR27,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 26. "ERR26,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 25. "ERR25,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 24. "ERR24,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 23. "ERR23,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 22. "ERR22,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 21. "ERR21,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 20. "ERR20,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 19. "ERR19,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 18. "ERR18,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 17. "ERR17,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 16. "ERR16,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 15. "ERR15,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 14. "ERR14,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 13. "ERR13,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 12. "ERR12,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 11. "ERR11,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 10. "ERR10,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 9. "ERR9,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 8. "ERR8,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 7. "ERR7,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 6. "ERR6,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 5. "ERR5,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 4. "ERR4,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 3. "ERR3,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 2. "ERR2,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
newline
bitfld.long 0x0 1. "ERR1,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
bitfld.long 0x0 0. "ERR0,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
line.long 0x4 "ERRINT1,Error Interrupt status for all DMA channels"
bitfld.long 0x4 0. "ERR32,Error Interrupt flag for DMA channel." "0: The Error Interrupt is not active for DMA channel.,1: The Error Interrupt is pending for DMA channel."
line.long 0x8 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
bitfld.long 0x8 31. "INTEN31,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 30. "INTEN30,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 29. "INTEN29,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 28. "INTEN28,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 27. "INTEN27,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 26. "INTEN26,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 25. "INTEN25,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 24. "INTEN24,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 23. "INTEN23,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 22. "INTEN22,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 21. "INTEN21,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 20. "INTEN20,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 19. "INTEN19,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 18. "INTEN18,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 17. "INTEN17,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 16. "INTEN16,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 15. "INTEN15,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 14. "INTEN14,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 13. "INTEN13,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 12. "INTEN12,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 11. "INTEN11,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 10. "INTEN10,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 9. "INTEN9,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 8. "INTEN8,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 7. "INTEN7,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 6. "INTEN6,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 5. "INTEN5,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 4. "INTEN4,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 3. "INTEN3,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 2. "INTEN2,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
newline
bitfld.long 0x8 1. "INTEN1,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
bitfld.long 0x8 0. "INTEN0,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
line.long 0xC "INTENSET1,Interrupt Enable read and Set for all DMA channels"
bitfld.long 0xC 0. "INTEN32,Interrupt Enable read and set for DMA channel." "0: The Interrupt for DMA channel is disabled.,1: The Interrupt for DMA channel is enabled."
wgroup.long 0x50++0x7
line.long 0x0 "INTENCLR0,Interrupt Enable Clear for all DMA channels"
bitfld.long 0x0 31. "CLR31,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 30. "CLR30,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 29. "CLR29,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 28. "CLR28,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 27. "CLR27,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 26. "CLR26,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
newline
bitfld.long 0x0 25. "CLR25,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 24. "CLR24,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 23. "CLR23,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 22. "CLR22,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 21. "CLR21,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 20. "CLR20,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 19. "CLR19,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 18. "CLR18,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 17. "CLR17,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 16. "CLR16,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
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bitfld.long 0x0 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
bitfld.long 0x0 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0." "0,1"
line.long 0x4 "INTENCLR1,Interrupt Enable Clear for all DMA channels"
bitfld.long 0x4 0. "CLR32,Writing ones to this register clears corresponding bits in the DMAIntEnSet1." "0,1"
group.long 0x58++0xF
line.long 0x0 "INTA0,Interrupt A status for all DMA channels"
bitfld.long 0x0 31. "INTA31,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 30. "INTA30,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 29. "INTA29,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 28. "INTA28,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 27. "INTA27,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 26. "INTA26,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
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bitfld.long 0x0 25. "INTA25,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 24. "INTA24,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 23. "INTA23,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 22. "INTA22,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 21. "INTA21,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 20. "INTA20,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 19. "INTA19,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 18. "INTA18,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 17. "INTA17,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 16. "INTA16,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 15. "INTA15,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 14. "INTA14,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 13. "INTA13,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 12. "INTA12,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 11. "INTA11,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 10. "INTA10,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 9. "INTA9,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 8. "INTA8,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 7. "INTA7,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 6. "INTA6,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 5. "INTA5,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 4. "INTA4,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 3. "INTA3,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 2. "INTA2,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
newline
bitfld.long 0x0 1. "INTA1,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
bitfld.long 0x0 0. "INTA0,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
line.long 0x4 "INTA1,Interrupt A status for all DMA channels"
bitfld.long 0x4 0. "INTA32,Interrupt A status for DMA channel." "0: The DMA channel interrupt A is not active.,1: The DMA channel interrupt A is active."
line.long 0x8 "INTB0,Interrupt B status for all DMA channels"
bitfld.long 0x8 31. "INTB31,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 30. "INTB30,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 29. "INTB29,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 28. "INTB28,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 27. "INTB27,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 26. "INTB26,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 25. "INTB25,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 24. "INTB24,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 23. "INTB23,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 22. "INTB22,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 21. "INTB21,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 20. "INTB20,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 19. "INTB19,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 18. "INTB18,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 17. "INTB17,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 16. "INTB16,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 15. "INTB15,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 14. "INTB14,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 13. "INTB13,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 12. "INTB12,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 11. "INTB11,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 10. "INTB10,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 9. "INTB9,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 8. "INTB8,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 7. "INTB7,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 6. "INTB6,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 5. "INTB5,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 4. "INTB4,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 3. "INTB3,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 2. "INTB2,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
newline
bitfld.long 0x8 1. "INTB1,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
bitfld.long 0x8 0. "INTB0,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
line.long 0xC "INTB1,Interrupt B status for all DMA channels"
bitfld.long 0xC 0. "INTB0,Interrupt B status for DMA channel." "0: The DMA channel interrupt B is not active.,1: The DMA channel interrupt B is active."
wgroup.long 0x68++0x17
line.long 0x0 "SETVALID0,Set ValidPending control bits for all DMA channels"
bitfld.long 0x0 31. "SETVALID31,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 30. "SETVALID30,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 29. "SETVALID29,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 28. "SETVALID28,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 27. "SETVALID27,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 26. "SETVALID26,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 25. "SETVALID25,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 24. "SETVALID24,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 23. "SETVALID23,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 22. "SETVALID22,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 21. "SETVALID21,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 20. "SETVALID20,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 19. "SETVALID19,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 18. "SETVALID18,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 17. "SETVALID17,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 16. "SETVALID16,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 15. "SETVALID15,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 14. "SETVALID14,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 13. "SETVALID13,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 12. "SETVALID12,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 11. "SETVALID11,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 10. "SETVALID10,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 9. "SETVALID9,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 8. "SETVALID8,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 7. "SETVALID7,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 6. "SETVALID6,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 5. "SETVALID5,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 4. "SETVALID4,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 3. "SETVALID3,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 2. "SETVALID2,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
newline
bitfld.long 0x0 1. "SETVALID1,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
bitfld.long 0x0 0. "SETVALID0,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
line.long 0x4 "SETVALID1,Set ValidPending control bits for all DMA channels"
bitfld.long 0x4 0. "SETVALID32,SetValid control for DMA channel." "0: No effect.,1: Sets the ValidPending control bit for DMA channel."
line.long 0x8 "SETTRIG0,Set Trigger control bits for all DMA channels"
bitfld.long 0x8 31. "SETTRIG31,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 30. "SETTRIG30,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 29. "SETTRIG29,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 28. "SETTRIG28,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 27. "SETTRIG27,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 26. "SETTRIG26,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 25. "SETTRIG25,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 24. "SETTRIG24,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 23. "SETTRIG23,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 22. "SETTRIG22,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 21. "SETTRIG21,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 20. "SETTRIG20,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 19. "SETTRIG19,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 18. "SETTRIG18,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 17. "SETTRIG17,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 16. "SETTRIG16,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 15. "SETTRIG15,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 14. "SETTRIG14,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 13. "SETTRIG13,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 12. "SETTRIG12,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 11. "SETTRIG11,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 10. "SETTRIG10,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 9. "SETTRIG9,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 8. "SETTRIG8,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 7. "SETTRIG7,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 6. "SETTRIG6,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 5. "SETTRIG5,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 4. "SETTRIG4,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 3. "SETTRIG3,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 2. "SETTRIG2,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
newline
bitfld.long 0x8 1. "SETTRIG1,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
bitfld.long 0x8 0. "SETTRIG0,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
line.long 0xC "SETTRIG1,Set Trigger control bits for all DMA channels"
bitfld.long 0xC 0. "SETTRIG32,Set Trigger control bit for DMA channel." "0: No effect.,1: Sets the Trig bit for DMA channel."
line.long 0x10 "ABORT0,Channel Abort control for all DMA channels"
bitfld.long 0x10 31. "ABORT31,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 30. "ABORT30,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 29. "ABORT29,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 28. "ABORT28,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 27. "ABORT27,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 26. "ABORT26,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 25. "ABORT25,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 24. "ABORT24,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 23. "ABORT23,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 22. "ABORT22,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 21. "ABORT21,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 20. "ABORT20,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 19. "ABORT19,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 18. "ABORT18,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 17. "ABORT17,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 16. "ABORT16,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 15. "ABORT15,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 14. "ABORT14,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 13. "ABORT13,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 12. "ABORT12,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 11. "ABORT11,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 10. "ABORT10,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 9. "ABORT9,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 8. "ABORT8,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 7. "ABORT7,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 6. "ABORT6,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 5. "ABORT5,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 4. "ABORT4,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 3. "ABORT3,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 2. "ABORT2,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
newline
bitfld.long 0x10 1. "ABORT1,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
bitfld.long 0x10 0. "ABORT0,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
line.long 0x14 "ABORT1,Channel Abort control for all DMA channels"
bitfld.long 0x14 0. "ABORT32,Abort control for DMA channel." "0: No effect.,1: Aborts DMA operations on channel."
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40105400 ad:0x40105410 ad:0x40105420 ad:0x40105430 ad:0x40105440 ad:0x40105450 ad:0x40105460 ad:0x40105470 ad:0x40105480 ad:0x40105490 ad:0x401054A0 ad:0x401054B0 ad:0x401054C0 ad:0x401054D0 ad:0x401054E0 ad:0x401054F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel"
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap." "0: Disabled.,1: Enabled."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst." "0: Single transfer.,1: Burst transfer."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type." "0: Edge. Hardware trigger is edge triggered.,1: Level."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for channel." "0: Hardware triggering not used for channel.,1: Hardware triggering used for channel."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable." "0: Peripheral DMA requests disabled.,1: Peripheral DMA requests enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x0 2. "TRIG,Trigger flag." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel." "0: No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded."
bitfld.long 0x0 14.--15. "DSTINC,Destination address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
newline
bitfld.long 0x0 12.--13. "SRCINC,Source address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit.,1: 16-bit.,2: 32-bit.,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for channel." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for channel." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared.,1: Cleared."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set.,1: Set."
newline
bitfld.long 0x0 1. "RELOAD,Reload." "0: Disabled. The channels' control structure should..,1: Enabled. The channels' control structure should.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag." "0: Not valid.,1: Valid."
tree.end
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40105500 ad:0x40105510 ad:0x40105520 ad:0x40105530 ad:0x40105540 ad:0x40105550 ad:0x40105560 ad:0x40105570 ad:0x40105580 ad:0x40105590 ad:0x401055A0 ad:0x401055B0 ad:0x401055C0 ad:0x401055D0 ad:0x401055E0 ad:0x401055F0)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CFG,Configuration register for DMA channel"
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap." "0: Disabled.,1: Enabled."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst." "0: Single transfer.,1: Burst transfer."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type." "0: Edge. Hardware trigger is edge triggered.,1: Level."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for channel." "0: Hardware triggering not used for channel.,1: Hardware triggering used for channel."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable." "0: Peripheral DMA requests disabled.,1: Peripheral DMA requests enabled."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x0 2. "TRIG,Trigger flag." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel." "0: No effect on DMA operation.,1: Valid pending."
group.long ($2+0x8)++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded."
bitfld.long 0x0 14.--15. "DSTINC,Destination address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
newline
bitfld.long 0x0 12.--13. "SRCINC,Source address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit.,1: 16-bit.,2: 32-bit.,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for channel." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for channel." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared.,1: Cleared."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set.,1: Set."
newline
bitfld.long 0x0 1. "RELOAD,Reload." "0: Disabled. The channels' control structure should..,1: Enabled. The channels' control structure should.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag." "0: Not valid.,1: Valid."
tree.end
repeat.end
tree "CHANNEL[32] (no description available)"
base ad:0x40105000
group.long 0x0++0x3
line.long 0x0 "CFG,Configuration register for DMA channel"
bitfld.long 0x0 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 15. "DSTBURSTWRAP,Destination Burst Wrap." "0: Disabled. Destination burst wrapping is not..,1: Enabled. Destination burst wrapping is enabled.."
newline
bitfld.long 0x0 14. "SRCBURSTWRAP,Source Burst Wrap." "0: Disabled.,1: Enabled."
hexmask.long.byte 0x0 8.--11. 1. "BURSTPOWER,Burst Power."
newline
bitfld.long 0x0 6. "TRIGBURST,Trigger Burst." "0: Single transfer.,1: Burst transfer."
bitfld.long 0x0 5. "TRIGTYPE,Trigger Type." "0: Edge. Hardware trigger is edge triggered.,1: Level."
newline
bitfld.long 0x0 4. "TRIGPOL,Trigger Polarity." "0: Active low - falling edge. Hardware trigger is..,1: Active high - rising edge. Hardware trigger is.."
bitfld.long 0x0 1. "HWTRIGEN,Hardware Triggering Enable for channel." "0: Hardware triggering not used for channel.,1: Hardware triggering used for channel."
newline
bitfld.long 0x0 0. "PERIPHREQEN,Peripheral request Enable." "0: Peripheral DMA requests disabled.,1: Peripheral DMA requests enabled."
rgroup.long 0x4++0x3
line.long 0x0 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x0 2. "TRIG,Trigger flag." "0: Not triggered. The trigger for this DMA channel..,1: Triggered. The trigger for this DMA channel is.."
bitfld.long 0x0 0. "VALIDPENDING,Valid pending flag for this channel." "0: No effect on DMA operation.,1: Valid pending."
group.long 0x8++0x3
line.long 0x0 "XFERCFG,Transfer configuration register for DMA channel"
hexmask.long.word 0x0 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded."
bitfld.long 0x0 14.--15. "DSTINC,Destination address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
newline
bitfld.long 0x0 12.--13. "SRCINC,Source address increment" "0: No increment.,1: 1 x width.,2: 2 x width.,3: 4 x width."
bitfld.long 0x0 8.--9. "WIDTH,Transfer width used for this DMA channel." "0: 8-bit.,1: 16-bit.,2: 32-bit.,?"
newline
bitfld.long 0x0 5. "SETINTB,Set Interrupt flag B for channel." "0: No effect.,1: Set. The INTB flag for this channel will be set.."
bitfld.long 0x0 4. "SETINTA,Set Interrupt flag A for channel." "0: No effect.,1: Set. The INTA flag for this channel will be set.."
newline
bitfld.long 0x0 3. "CLRTRIG,Clear Trigger." "0: Not cleared.,1: Cleared."
bitfld.long 0x0 2. "SWTRIG,Software Trigger." "0: Not set.,1: Set."
newline
bitfld.long 0x0 1. "RELOAD,Reload." "0: Disabled. The channels' control structure should..,1: Enabled. The channels' control structure should.."
bitfld.long 0x0 0. "CFGVALID,Configuration Valid flag." "0: Not valid.,1: Valid."
tree.end
tree.end
tree.end
tree "DMIC (Digital Microphone Interface)"
base ad:0x40121000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40121000 ad:0x40121100 ad:0x40121200 ad:0x40121300)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x13
line.long 0x0 "OSR,Oversample Rate"
hexmask.long.byte 0x0 0.--7. 1. "OSR,Oversample Rate"
line.long 0x4 "DIVHFCLK,DMIC Clock"
hexmask.long.byte 0x4 0.--3. 1. "PDMDIV,PDM Clock Divider Value"
line.long 0x8 "PREAC2FSCOEF,Compensation Filter for 2 FS"
bitfld.long 0x8 0.--1. "COMP,Compensation value" "0: Compensation = 0. This is the recommended setting.,1: Compensation = -0.16,2: Compensation = -0.15,3: Compensation = -0.13"
line.long 0xC "PREAC4FSCOEF,Compensation Filter for 4 FS"
bitfld.long 0xC 0.--1. "COMP,Compensation value" "0: Compensation = 0. This is the recommended setting.,1: Compensation = -0.16,2: Compensation = -0.15,3: Compensation = -0.13"
line.long 0x10 "GAINSHIFT,Decimator Gain Shift"
hexmask.long.byte 0x10 0.--5. 1. "GAIN,Gain"
group.long ($2+0x80)++0x7
line.long 0x0 "FIFO_CTRL,FIFO Control"
hexmask.long.byte 0x0 16.--20. 1. "TRIGLVL,FIFO Trigger Level for Interrupt"
bitfld.long 0x0 3. "DMAEN,DMA Enable" "0: DMA requests are not enabled.,1: DMA requests based on FIFO level are enabled."
newline
bitfld.long 0x0 2. "INTEN,Interrupt Enable." "0: FIFO level interrupts are not enabled.,1: FIFO level interrupts are enabled."
bitfld.long 0x0 1. "RESETN,FIFO Reset" "0: Reset the FIFO. This must be cleared before..,1: Normal operation"
newline
bitfld.long 0x0 0. "ENABLE,FIFO Enable." "0: FIFO is not enabled. Enabling a DMIC channel..,1: FIFO is enabled. The FIFO must be enabled in.."
line.long 0x4 "FIFO_STATUS,FIFO Status"
eventfld.long 0x4 2. "UNDERRUN,Underrun Detected (write 1 to clear)" "0,1"
eventfld.long 0x4 1. "OVERRUN,Overrun Detected (write 1 to clear)" "0,1"
newline
eventfld.long 0x4 0. "INT,Status of Interrupt (write 1 to clear)" "0,1"
rgroup.long ($2+0x88)++0x3
line.long 0x0 "FIFO_DATA,FIFO Data"
hexmask.long.tbyte 0x0 0.--23. 1. "DATA,PCM Data"
group.long ($2+0x8C)++0x7
line.long 0x0 "PHY_CTRL,Physical Control"
bitfld.long 0x0 1. "PHY_HALF,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling. The clock to the..,1: Use half rate sampling. The clock to the DMIC is.."
bitfld.long 0x0 0. "PHY_FALL,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK.,1: Capture PDM_DATA on the falling edge of PDM_CLK."
line.long 0x4 "DC_CTRL,DC Filter Control"
bitfld.long 0x4 9. "SIGNEXTEND,Sign Extend" "0: The top byte of the FIFODATA register is always 0.,1: The top byte of the FIFODATA register is sign.."
bitfld.long 0x4 8. "SATURATEAT16BIT,Saturate at 16 Bit" "0: Do not Saturate. Results roll over if out range..,1: Saturate. If the result overflows it saturates.."
newline
hexmask.long.byte 0x4 4.--7. 1. "DCGAIN,DC Gain"
bitfld.long 0x4 0.--1. "DCPOLE,DC Block Filter" "0: Flat Response no filter,1: 155 Hz,2: 78 Hz,3: 39 Hz"
tree.end
repeat.end
base ad:0x40121000
newline
group.long 0xF00++0x3
line.long 0x0 "CHANEN,Channel Enable"
bitfld.long 0x0 3. "EN_CH3,Enable Channel n" "0: PDM channel n is disabled.,1: PDM channel n is enabled."
bitfld.long 0x0 2. "EN_CH2,Enable Channel n" "0: PDM channel n is disabled.,1: PDM channel n is enabled."
newline
bitfld.long 0x0 1. "EN_CH1,Enable Channel n" "0: PDM channel n is disabled.,1: PDM channel n is enabled."
bitfld.long 0x0 0. "EN_CH0,Enable Channel n" "0: PDM channel n is disabled.,1: PDM channel n is enabled."
group.long 0xF10++0xF
line.long 0x0 "USE2FS,Use 2 FS register"
bitfld.long 0x0 0. "USE2FS,Use 2FS register" "0: Use 1 FS output for PCM data.,1: Use 2 FS output for PCM data."
line.long 0x4 "GLOBAL_SYCN_EN,Global Channel Synchronization Enable"
hexmask.long.byte 0x4 0.--3. 1. "CH_SYNC_EN,Channel synch enable"
line.long 0x8 "GLOBAL_COUNT_VAL,Global channel synchronization counter value"
hexmask.long 0x8 0.--31. 1. "CCOUNTVAL,Channel Counter Value"
line.long 0xC "DECRESET,DMIC decimator reset"
hexmask.long.byte 0xC 0.--3. 1. "DECRESET,Decimator reset"
group.long 0xF80++0x17
line.long 0x0 "HWVADGAIN,HWVAD Input Gain"
hexmask.long.byte 0x0 0.--3. 1. "INPUTGAIN,Shift value for input bits"
line.long 0x4 "HWVADHPFS,HWVAD Filter Control"
bitfld.long 0x4 0.--1. "HPFS,The HPFS field chooses the High Pass filter in first part of HWVAD." "0: BYPASS. First filter by-pass.,1: HIGH_PASS_1750HZ. High pass filter with -3dB..,2: HIGH_PASS_215HZ. High pass filter with -3dB..,?"
line.long 0x8 "HWVADST10,HWVAD Control"
bitfld.long 0x8 0. "ST10,STAGE 1" "0: Normal operation waiting for HWVAD trigger event..,1: Reset internal interrupt flag by writing a '1'.."
line.long 0xC "HWVADRSTT,HWVAD Filter Reset"
bitfld.long 0xC 0. "RSST,Reset HWVAD" "0,1"
line.long 0x10 "HWVADTHGN,HWVAD Noise Estimator Gain"
hexmask.long.byte 0x10 0.--3. 1. "THGN,Gain Factor for Noise Estimator"
line.long 0x14 "HWVADTHGS,HWVAD Signal Estimator Gain"
hexmask.long.byte 0x14 0.--3. 1. "THGS,Signal Gain Factor"
rgroup.long 0xF98++0x3
line.long 0x0 "HWVADLOWZ,HWVAD Noise Envelope Estimator"
hexmask.long.word 0x0 0.--15. 1. "LOWZ,Average Noise-floor Value"
tree.end
tree "ENET (Ethernet)"
base ad:0x40138000
group.long 0x4++0x7
line.long 0x0 "EIR,Interrupt Event Register"
eventfld.long 0x0 30. "BABR,Babbling Receive Error" "0,1"
newline
eventfld.long 0x0 29. "BABT,Babbling Transmit Error" "0,1"
newline
eventfld.long 0x0 28. "GRA,Graceful Stop Complete" "0,1"
newline
eventfld.long 0x0 27. "TXF,Transmit Frame Interrupt" "0,1"
newline
eventfld.long 0x0 26. "TXB,Transmit Buffer Interrupt" "0,1"
newline
eventfld.long 0x0 25. "RXF,Receive Frame Interrupt" "0,1"
newline
eventfld.long 0x0 24. "RXB,Receive Buffer Interrupt" "0,1"
newline
eventfld.long 0x0 23. "MII,MII Interrupt." "0,1"
newline
eventfld.long 0x0 22. "EBERR,Ethernet Bus Error" "0,1"
newline
eventfld.long 0x0 21. "LC,Late Collision" "0,1"
newline
eventfld.long 0x0 20. "RL,Collision Retry Limit" "0,1"
newline
eventfld.long 0x0 19. "UN,Transmit FIFO Underrun" "0,1"
newline
eventfld.long 0x0 18. "PLR,Payload Receive Error" "0,1"
newline
eventfld.long 0x0 17. "WAKEUP,Node Wakeup Request Indication" "0,1"
newline
eventfld.long 0x0 16. "TS_AVAIL,Transmit Timestamp Available" "0,1"
newline
eventfld.long 0x0 15. "TS_TIMER,Timestamp Timer" "0,1"
line.long 0x4 "EIMR,Interrupt Mask Register"
bitfld.long 0x4 30. "BABR,BABR Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 29. "BABT,BABT Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 28. "GRA,GRA Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 27. "TXF,TXF Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 26. "TXB,TXB Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 25. "RXF,RXF Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 24. "RXB,RXB Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 23. "MII,MII Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 22. "EBERR,EBERR Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 21. "LC,LC Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 20. "RL,RL Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 19. "UN,UN Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 18. "PLR,PLR Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 17. "WAKEUP,WAKEUP Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 16. "TS_AVAIL,TS_AVAIL Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
newline
bitfld.long 0x4 15. "TS_TIMER,TS_TIMER Interrupt Mask" "0: The corresponding interrupt source is masked.,1: The corresponding interrupt source is not masked."
group.long 0x10++0x7
line.long 0x0 "RDAR,Receive Descriptor Active Register - Ring 0"
bitfld.long 0x0 24. "RDAR,Receive Descriptor Active" "0,1"
line.long 0x4 "TDAR,Transmit Descriptor Active Register - Ring 0"
bitfld.long 0x4 24. "TDAR,Transmit Descriptor Active" "0,1"
group.long 0x24++0x3
line.long 0x0 "ECR,Ethernet Control Register"
bitfld.long 0x0 8. "DBSWP,Descriptor Byte Swapping Enable" "0: The buffer descriptor bytes are not swapped to..,1: The buffer descriptor bytes are swapped to.."
newline
bitfld.long 0x0 6. "DBGEN,Debug Enable" "0: MAC continues operation in debug mode.,1: MAC enters hardware freeze mode when the.."
newline
bitfld.long 0x0 4. "EN1588,EN1588 Enable" "0: Legacy FEC buffer descriptors and functions..,1: Enhanced frame time-stamping functions enabled."
newline
bitfld.long 0x0 3. "SLEEP,Sleep Mode Enable" "0: Normal operating mode.,1: Sleep mode."
newline
bitfld.long 0x0 2. "MAGICEN,Magic Packet Detection Enable" "0: Magic detection logic disabled.,1: The MAC core detects magic packets and asserts.."
newline
bitfld.long 0x0 1. "ETHEREN,Ethernet Enable" "0: Reception immediately stops and transmission..,1: MAC is enabled and reception and transmission.."
newline
bitfld.long 0x0 0. "RESET,Ethernet MAC Reset" "0,1"
group.long 0x40++0x7
line.long 0x0 "MMFR,MII Management Frame Register"
bitfld.long 0x0 30.--31. "ST,Start Of Frame Delimiter" "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "OP,Operation Code" "0,1,2,3"
newline
hexmask.long.byte 0x0 23.--27. 1. "PA,PHY Address"
newline
hexmask.long.byte 0x0 18.--22. 1. "RA,Register Address"
newline
bitfld.long 0x0 16.--17. "TA,Turn Around" "0,1,2,3"
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hexmask.long.word 0x0 0.--15. 1. "DATA,Management Frame Data"
line.long 0x4 "MSCR,MII Speed Control Register"
bitfld.long 0x4 8.--10. "HOLDTIME,Hold time On MDIO Output" "0: 1 internal module clock cycle,1: 2 internal module clock cycles,2: 3 internal module clock cycles,?,?,?,?,7: 8 internal module clock cycles"
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bitfld.long 0x4 7. "DIS_PRE,Disable Preamble" "0: Preamble enabled.,1: Preamble (32 ones) is not prepended to the MII.."
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hexmask.long.byte 0x4 1.--6. 1. "MII_SPEED,MII Speed"
group.long 0x64++0x3
line.long 0x0 "MIBC,MIB Control Register"
bitfld.long 0x0 31. "MIB_DIS,Disable MIB Logic" "0: MIB logic is enabled.,1: MIB logic is disabled. The MIB logic halts and.."
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rbitfld.long 0x0 30. "MIB_IDLE,MIB Idle" "0: The MIB block is updating MIB counters.,1: The MIB block is not currently updating any MIB.."
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bitfld.long 0x0 29. "MIB_CLEAR,MIB Clear" "0: See note above.,1: All statistics counters are reset to 0."
group.long 0x84++0x3
line.long 0x0 "RCR,Receive Control Register"
rbitfld.long 0x0 31. "GRS,Graceful Receive Stopped" "0: Receive not stopped,1: Receive stopped"
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bitfld.long 0x0 30. "NLC,Payload Length Check Disable" "0: The payload length check is disabled.,1: The core checks the frame's payload length with.."
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hexmask.long.word 0x0 16.--29. 1. "MAX_FL,Maximum Frame Length"
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bitfld.long 0x0 15. "CFEN,MAC Control Frame Enable" "0: MAC control frames with any opcode other than..,1: MAC control frames with any opcode other than.."
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bitfld.long 0x0 14. "CRCFWD,Terminate/Forward Received CRC" "0: The CRC field of received frames is transmitted..,1: The CRC field is stripped from the frame."
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bitfld.long 0x0 13. "PAUFWD,Terminate/Forward Pause Frames" "0: Pause frames are terminated and discarded in the..,1: Pause frames are forwarded to the user.."
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bitfld.long 0x0 12. "PADEN,Enable Frame Padding Remove On Receive" "0: No padding is removed on receive by the MAC.,1: Padding is removed from received frames."
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bitfld.long 0x0 9. "RMII_10T,Enables 10-Mbit/s mode of the RMII ." "0: 100-Mbit/s operation.,1: 10-Mbit/s operation."
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bitfld.long 0x0 8. "RMII_MODE,RMII Mode Enable" "0: MAC configured for MII mode.,1: MAC configured for RMII operation."
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bitfld.long 0x0 5. "FCE,Flow Control Enable" "0: Disable flow control,1: Enable flow control"
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bitfld.long 0x0 4. "BC_REJ,Broadcast Frame Reject" "0: Will not reject frames as described above,1: Will reject frames as described above"
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bitfld.long 0x0 3. "PROM,Promiscuous Mode" "0: Disabled.,1: Enabled."
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bitfld.long 0x0 2. "MII_MODE,Media Independent Interface Mode" "?,1: MII or RMII mode as indicated by the RMII_MODE.."
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bitfld.long 0x0 1. "DRT,Disable Receive On Transmit" "0: Receive path operates independently of transmit..,1: Disable reception of frames while transmitting."
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bitfld.long 0x0 0. "LOOP,Internal Loopback" "0: Loopback disabled.,1: Transmitted frames are looped back internal to.."
group.long 0xC4++0x3
line.long 0x0 "TCR,Transmit Control Register"
bitfld.long 0x0 9. "CRCFWD,Forward Frame From Application With CRC" "0: TxBD[TC] controls whether the frame has a CRC..,1: The transmitter does not append any CRC to.."
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bitfld.long 0x0 8. "ADDINS,Set MAC Address On Transmit" "0: The source MAC address is not modified by the MAC.,1: The MAC overwrites the source MAC address with.."
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bitfld.long 0x0 5.--7. "ADDSEL,Source MAC Address Select On Transmit" "0: Node MAC address programmed on PADDR1/2 registers.,?,?,?,?,?,?,?"
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rbitfld.long 0x0 4. "RFC_PAUSE,Receive Frame Control Pause" "0,1"
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bitfld.long 0x0 3. "TFC_PAUSE,Transmit Frame Control Pause" "0: No PAUSE frame transmitted.,1: The MAC stops transmission of data frames after.."
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bitfld.long 0x0 2. "FDEN,Full-Duplex Enable" "0: Disable full-duplex,1: Enable full-duplex"
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bitfld.long 0x0 0. "GTS,Graceful Transmit Stop" "0: Disable graceful transmit stop,1: Enable graceful transmit stop"
group.long 0xE4++0xF
line.long 0x0 "PALR,Physical Address Lower Register"
hexmask.long 0x0 0.--31. 1. "PADDR1,Pause Address"
line.long 0x4 "PAUR,Physical Address Upper Register"
hexmask.long.word 0x4 16.--31. 1. "PADDR2,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match and the source address field in PAUSE frames"
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hexmask.long.word 0x4 0.--15. 1. "TYPE,Type Field In PAUSE Frames"
line.long 0x8 "OPD,Opcode/Pause Duration Register"
hexmask.long.word 0x8 16.--31. 1. "OPCODE,Opcode Field In PAUSE Frames"
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hexmask.long.word 0x8 0.--15. 1. "PAUSE_DUR,Pause Duration"
line.long 0xC "TXIC0,Transmit Interrupt Coalescing Register"
bitfld.long 0xC 31. "ICEN,Interrupt Coalescing Enable" "0: Disable Interrupt coalescing.,1: Enable Interrupt coalescing."
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bitfld.long 0xC 30. "ICCS,Interrupt Coalescing Timer Clock Source Select" "0: Use MII/GMII TX clocks.,1: Use ENET system clock."
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hexmask.long.byte 0xC 20.--27. 1. "ICFT,Interrupt coalescing frame count threshold"
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hexmask.long.word 0xC 0.--15. 1. "ICTT,Interrupt coalescing timer threshold"
group.long 0x100++0x3
line.long 0x0 "RXIC0,Receive Interrupt Coalescing Register"
bitfld.long 0x0 31. "ICEN,Interrupt Coalescing Enable" "0: Disable Interrupt coalescing.,1: Enable Interrupt coalescing."
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bitfld.long 0x0 30. "ICCS,Interrupt Coalescing Timer Clock Source Select" "0: Use MII/GMII TX clocks.,1: Use ENET system clock."
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hexmask.long.byte 0x0 20.--27. 1. "ICFT,Interrupt coalescing frame count threshold"
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hexmask.long.word 0x0 0.--15. 1. "ICTT,Interrupt coalescing timer threshold"
group.long 0x118++0xF
line.long 0x0 "IAUR,Descriptor Individual Upper Address Register"
hexmask.long 0x0 0.--31. 1. "IADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
line.long 0x4 "IALR,Descriptor Individual Lower Address Register"
hexmask.long 0x4 0.--31. 1. "IADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
line.long 0x8 "GAUR,Descriptor Group Upper Address Register"
hexmask.long 0x8 0.--31. 1. "GADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
line.long 0xC "GALR,Descriptor Group Lower Address Register"
hexmask.long 0xC 0.--31. 1. "GADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
group.long 0x144++0x3
line.long 0x0 "TFWR,Transmit FIFO Watermark Register"
bitfld.long 0x0 8. "STRFWD,Store And Forward Enable" "0: Reset. The transmission start threshold is..,1: Enabled."
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hexmask.long.byte 0x0 0.--5. 1. "TFWR,Transmit FIFO Write"
group.long 0x180++0xB
line.long 0x0 "RDSR,Receive Descriptor Ring 0 Start Register"
hexmask.long 0x0 3.--31. 1. "R_DES_START,Pointer to the beginning of the receive buffer descriptor queue."
line.long 0x4 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register"
hexmask.long 0x4 3.--31. 1. "X_DES_START,Pointer to the beginning of the transmit buffer descriptor queue."
line.long 0x8 "MRBR,Maximum Receive Buffer Size Register - Ring 0"
hexmask.long.word 0x8 4.--13. 1. "R_BUF_SIZE,Receive buffer size in bytes"
group.long 0x190++0x23
line.long 0x0 "RSFL,Receive FIFO Section Full Threshold"
hexmask.long.byte 0x0 0.--7. 1. "RX_SECTION_FULL,Value Of Receive FIFO Section Full Threshold"
line.long 0x4 "RSEM,Receive FIFO Section Empty Threshold"
hexmask.long.byte 0x4 16.--20. 1. "STAT_SECTION_EMPTY,RX Status FIFO Section Empty Threshold"
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hexmask.long.byte 0x4 0.--7. 1. "RX_SECTION_EMPTY,Value Of The Receive FIFO Section Empty Threshold"
line.long 0x8 "RAEM,Receive FIFO Almost Empty Threshold"
hexmask.long.byte 0x8 0.--7. 1. "RX_ALMOST_EMPTY,Value Of The Receive FIFO Almost Empty Threshold"
line.long 0xC "RAFL,Receive FIFO Almost Full Threshold"
hexmask.long.byte 0xC 0.--7. 1. "RX_ALMOST_FULL,Value Of The Receive FIFO Almost Full Threshold"
line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold"
hexmask.long.byte 0x10 0.--7. 1. "TX_SECTION_EMPTY,Value Of The Transmit FIFO Section Empty Threshold"
line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold"
hexmask.long.byte 0x14 0.--7. 1. "TX_ALMOST_EMPTY,Value of Transmit FIFO Almost Empty Threshold"
line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold"
hexmask.long.byte 0x18 0.--7. 1. "TX_ALMOST_FULL,Value Of The Transmit FIFO Almost Full Threshold"
line.long 0x1C "TIPG,Transmit Inter-Packet Gap"
hexmask.long.byte 0x1C 0.--4. 1. "IPG,Transmit Inter-Packet Gap"
line.long 0x20 "FTRL,Frame Truncation Length"
hexmask.long.word 0x20 0.--13. 1. "TRUNC_FL,Frame Truncation Length"
group.long 0x1C0++0x7
line.long 0x0 "TACC,Transmit Accelerator Function Configuration"
bitfld.long 0x0 4. "PROCHK,Enables insertion of protocol checksum." "0: Checksum not inserted.,1: If an IP frame with a known protocol is.."
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bitfld.long 0x0 3. "IPCHK,Enables insertion of IP header checksum." "0: Checksum is not inserted.,1: If an IP frame is transmitted the checksum is.."
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bitfld.long 0x0 0. "SHIFT16,TX FIFO Shift-16" "0: Disabled.,1: Indicates to the transmit data FIFO that the.."
line.long 0x4 "RACC,Receive Accelerator Function Configuration"
bitfld.long 0x4 7. "SHIFT16,RX FIFO Shift-16" "0: Disabled.,1: Instructs the MAC to write two additional bytes.."
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bitfld.long 0x4 6. "LINEDIS,Enable Discard Of Frames With MAC Layer Errors" "0: Frames with errors are not discarded.,1: Any frame received with a CRC length or PHY.."
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bitfld.long 0x4 2. "PRODIS,Enable Discard Of Frames With Wrong Protocol Checksum" "0: Frames with wrong checksum are not discarded.,1: If a TCP/IP UDP/IP or ICMP/IP frame is received.."
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bitfld.long 0x4 1. "IPDIS,Enable Discard Of Frames With Wrong IPv4 Header Checksum" "0: Frames with wrong IPv4 header checksum are not..,1: If an IPv4 frame is received with a mismatching.."
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bitfld.long 0x4 0. "PADREM,Enable Padding Removal For Short IP Frames" "0: Padding not removed.,1: Any bytes following the IP payload section of.."
rgroup.long 0x204++0x73
line.long 0x0 "RMON_T_PACKETS,Tx Packet Count Statistic Register"
hexmask.long.word 0x0 0.--15. 1. "TXPKTS,Packet count"
line.long 0x4 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register"
hexmask.long.word 0x4 0.--15. 1. "TXPKTS,Broadcast packets"
line.long 0x8 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register"
hexmask.long.word 0x8 0.--15. 1. "TXPKTS,Multicast packets"
line.long 0xC "RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register"
hexmask.long.word 0xC 0.--15. 1. "TXPKTS,Packets with CRC/align error"
line.long 0x10 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register"
hexmask.long.word 0x10 0.--15. 1. "TXPKTS,Number of transmit packets less than 64 bytes with good CRC"
line.long 0x14 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"
hexmask.long.word 0x14 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes with good CRC"
line.long 0x18 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
hexmask.long.word 0x18 0.--15. 1. "TXPKTS,Number of packets less than 64 bytes with bad CRC"
line.long 0x1C "RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"
hexmask.long.word 0x1C 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes and bad CRC"
line.long 0x20 "RMON_T_COL,Tx Collision Count Statistic Register"
hexmask.long.word 0x20 0.--15. 1. "TXPKTS,Number of transmit collisions"
line.long 0x24 "RMON_T_P64,Tx 64-Byte Packets Statistic Register"
hexmask.long.word 0x24 0.--15. 1. "TXPKTS,Number of 64-byte transmit packets"
line.long 0x28 "RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register"
hexmask.long.word 0x28 0.--15. 1. "TXPKTS,Number of 65- to 127-byte transmit packets"
line.long 0x2C "RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register"
hexmask.long.word 0x2C 0.--15. 1. "TXPKTS,Number of 128- to 255-byte transmit packets"
line.long 0x30 "RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register"
hexmask.long.word 0x30 0.--15. 1. "TXPKTS,Number of 256- to 511-byte transmit packets"
line.long 0x34 "RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register"
hexmask.long.word 0x34 0.--15. 1. "TXPKTS,Number of 512- to 1023-byte transmit packets"
line.long 0x38 "RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register"
hexmask.long.word 0x38 0.--15. 1. "TXPKTS,Number of 1024- to 2047-byte transmit packets"
line.long 0x3C "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register"
hexmask.long.word 0x3C 0.--15. 1. "TXPKTS,Number of transmit packets greater than 2048 bytes"
line.long 0x40 "RMON_T_OCTETS,Tx Octets Statistic Register"
hexmask.long 0x40 0.--31. 1. "TXOCTS,Number of transmit octets"
line.long 0x44 "IEEE_T_DROP,Reserved Statistic Register"
line.long 0x48 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register"
hexmask.long.word 0x48 0.--15. 1. "COUNT,Number of frames transmitted OK"
line.long 0x4C "IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register"
hexmask.long.word 0x4C 0.--15. 1. "COUNT,Number of frames transmitted with one collision"
line.long 0x50 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register"
hexmask.long.word 0x50 0.--15. 1. "COUNT,Number of frames transmitted with multiple collisions"
line.long 0x54 "IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register"
hexmask.long.word 0x54 0.--15. 1. "COUNT,Number of frames transmitted with deferral delay"
line.long 0x58 "IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register"
hexmask.long.word 0x58 0.--15. 1. "COUNT,Number of frames transmitted with late collision"
line.long 0x5C "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register"
hexmask.long.word 0x5C 0.--15. 1. "COUNT,Number of frames transmitted with excessive collisions"
line.long 0x60 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register"
hexmask.long.word 0x60 0.--15. 1. "COUNT,Number of frames transmitted with transmit FIFO underrun"
line.long 0x64 "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register"
hexmask.long.word 0x64 0.--15. 1. "COUNT,Number of frames transmitted with carrier sense error"
line.long 0x68 "IEEE_T_SQE,Reserved Statistic Register"
hexmask.long.word 0x68 0.--15. 1. "COUNT,This read-only field is reserved and always has the value 0"
line.long 0x6C "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register"
hexmask.long.word 0x6C 0.--15. 1. "COUNT,Number of flow-control pause frames transmitted"
line.long 0x70 "IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register"
hexmask.long 0x70 0.--31. 1. "COUNT,Octet count for frames transmitted without error Counts total octets (includes header and FCS fields)."
rgroup.long 0x284++0x1F
line.long 0x0 "RMON_R_PACKETS,Rx Packet Count Statistic Register"
hexmask.long.word 0x0 0.--15. 1. "COUNT,Number of packets received"
line.long 0x4 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register"
hexmask.long.word 0x4 0.--15. 1. "COUNT,Number of receive broadcast packets"
line.long 0x8 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register"
hexmask.long.word 0x8 0.--15. 1. "COUNT,Number of receive multicast packets"
line.long 0xC "RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register"
hexmask.long.word 0xC 0.--15. 1. "COUNT,Number of receive packets with CRC or align error"
line.long 0x10 "RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"
hexmask.long.word 0x10 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and good CRC"
line.long 0x14 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"
hexmask.long.word 0x14 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and good CRC"
line.long 0x18 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
hexmask.long.word 0x18 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and bad CRC"
line.long 0x1C "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"
hexmask.long.word 0x1C 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and bad CRC"
rgroup.long 0x2A8++0x3B
line.long 0x0 "RMON_R_P64,Rx 64-Byte Packets Statistic Register"
hexmask.long.word 0x0 0.--15. 1. "COUNT,Number of 64-byte receive packets"
line.long 0x4 "RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register"
hexmask.long.word 0x4 0.--15. 1. "COUNT,Number of 65- to 127-byte recieve packets"
line.long 0x8 "RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register"
hexmask.long.word 0x8 0.--15. 1. "COUNT,Number of 128- to 255-byte recieve packets"
line.long 0xC "RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register"
hexmask.long.word 0xC 0.--15. 1. "COUNT,Number of 256- to 511-byte recieve packets"
line.long 0x10 "RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register"
hexmask.long.word 0x10 0.--15. 1. "COUNT,Number of 512- to 1023-byte recieve packets"
line.long 0x14 "RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register"
hexmask.long.word 0x14 0.--15. 1. "COUNT,Number of 1024- to 2047-byte recieve packets"
line.long 0x18 "RMON_R_P_GTE2048,Rx Packets Greater than 2048 Bytes Statistic Register"
hexmask.long.word 0x18 0.--15. 1. "COUNT,Number of greater-than-2048-byte recieve packets"
line.long 0x1C "RMON_R_OCTETS,Rx Octets Statistic Register"
hexmask.long 0x1C 0.--31. 1. "COUNT,Number of receive octets"
line.long 0x20 "IEEE_R_DROP,Frames not Counted Correctly Statistic Register"
hexmask.long.word 0x20 0.--15. 1. "COUNT,Frame count"
line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register"
hexmask.long.word 0x24 0.--15. 1. "COUNT,Number of frames received OK"
line.long 0x28 "IEEE_R_CRC,Frames Received with CRC Error Statistic Register"
hexmask.long.word 0x28 0.--15. 1. "COUNT,Number of frames received with CRC error"
line.long 0x2C "IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register"
hexmask.long.word 0x2C 0.--15. 1. "COUNT,Number of frames received with alignment error"
line.long 0x30 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register"
hexmask.long.word 0x30 0.--15. 1. "COUNT,Receive FIFO overflow count"
line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register"
hexmask.long.word 0x34 0.--15. 1. "COUNT,Number of flow-control pause frames received"
line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic Register"
hexmask.long 0x38 0.--31. 1. "COUNT,Number of octets for frames received without error"
group.long 0x400++0x17
line.long 0x0 "ATCR,Adjustable Timer Control Register"
bitfld.long 0x0 13. "SLAVE,Enable Timer Slave Mode" "0: The timer is active and all configuration fields..,1: The internal timer is disabled and the.."
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bitfld.long 0x0 11. "CAPTURE,Capture Timer Value" "0: No effect.,1: The current time is captured and can be read.."
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bitfld.long 0x0 9. "RESTART,Reset Timer" "0,1"
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bitfld.long 0x0 7. "PINPER,Enables event signal output external pin frc_evt_period assertion on period event" "0: Disable.,1: Enable."
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bitfld.long 0x0 4. "PEREN,Enable Periodical Event" "0: Disable.,1: A period event interrupt can be generated.."
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bitfld.long 0x0 3. "OFFRST,Reset Timer On Offset Event" "0: The timer is not affected and no action occurs..,1: If OFFEN is set the timer resets to zero when.."
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bitfld.long 0x0 2. "OFFEN,Enable One-Shot Offset Event" "0: Disable.,1: The timer can be reset to zero when the given.."
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bitfld.long 0x0 0. "EN,Enable Timer" "0: The timer stops at the current value.,1: The timer starts incrementing."
line.long 0x4 "ATVR,Timer Value Register"
hexmask.long 0x4 0.--31. 1. "ATIME,A write sets the timer"
line.long 0x8 "ATOFF,Timer Offset Register"
hexmask.long 0x8 0.--31. 1. "OFFSET,Offset value for one-shot event generation"
line.long 0xC "ATPER,Timer Period Register"
hexmask.long 0xC 0.--31. 1. "PERIOD,Value for generating periodic events"
line.long 0x10 "ATCOR,Timer Correction Register"
hexmask.long 0x10 0.--30. 1. "COR,Correction Counter Wrap-Around Value"
line.long 0x14 "ATINC,Time-Stamping Clock Period Register"
hexmask.long.byte 0x14 8.--14. 1. "INC_CORR,Correction Increment Value"
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hexmask.long.byte 0x14 0.--6. 1. "INC,Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds"
rgroup.long 0x418++0x3
line.long 0x0 "ATSTMP,Timestamp of Last Transmitted Frame"
hexmask.long 0x0 0.--31. 1. "TIMESTAMP,Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application"
group.long 0x604++0x23
line.long 0x0 "TGSR,Timer Global Status Register"
eventfld.long 0x0 3. "TF3,Copy Of Timer Flag For Channel 3" "0: Timer Flag for Channel 3 is clear,1: Timer Flag for Channel 3 is set"
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eventfld.long 0x0 2. "TF2,Copy Of Timer Flag For Channel 2" "0: Timer Flag for Channel 2 is clear,1: Timer Flag for Channel 2 is set"
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eventfld.long 0x0 1. "TF1,Copy Of Timer Flag For Channel 1" "0: Timer Flag for Channel 1 is clear,1: Timer Flag for Channel 1 is set"
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eventfld.long 0x0 0. "TF0,Copy Of Timer Flag For Channel 0" "0: Timer Flag for Channel 0 is clear,1: Timer Flag for Channel 0 is set"
line.long 0x4 "TCSR0,Timer Control Status Register"
hexmask.long.byte 0x4 11.--15. 1. "TPWC,Timer PulseWidth Control"
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eventfld.long 0x4 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not occurred.,1: Input Capture or Output Compare has occurred."
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bitfld.long 0x4 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
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hexmask.long.byte 0x4 2.--5. 1. "TMODE,Timer Mode"
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bitfld.long 0x4 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
line.long 0x8 "TCCR0,Timer Compare Capture Register"
hexmask.long 0x8 0.--31. 1. "TCC,Timer Capture Compare"
line.long 0xC "TCSR1,Timer Control Status Register"
hexmask.long.byte 0xC 11.--15. 1. "TPWC,Timer PulseWidth Control"
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eventfld.long 0xC 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not occurred.,1: Input Capture or Output Compare has occurred."
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bitfld.long 0xC 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
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hexmask.long.byte 0xC 2.--5. 1. "TMODE,Timer Mode"
newline
bitfld.long 0xC 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
line.long 0x10 "TCCR1,Timer Compare Capture Register"
hexmask.long 0x10 0.--31. 1. "TCC,Timer Capture Compare"
line.long 0x14 "TCSR2,Timer Control Status Register"
hexmask.long.byte 0x14 11.--15. 1. "TPWC,Timer PulseWidth Control"
newline
eventfld.long 0x14 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not occurred.,1: Input Capture or Output Compare has occurred."
newline
bitfld.long 0x14 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
hexmask.long.byte 0x14 2.--5. 1. "TMODE,Timer Mode"
newline
bitfld.long 0x14 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
line.long 0x18 "TCCR2,Timer Compare Capture Register"
hexmask.long 0x18 0.--31. 1. "TCC,Timer Capture Compare"
line.long 0x1C "TCSR3,Timer Control Status Register"
hexmask.long.byte 0x1C 11.--15. 1. "TPWC,Timer PulseWidth Control"
newline
eventfld.long 0x1C 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not occurred.,1: Input Capture or Output Compare has occurred."
newline
bitfld.long 0x1C 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
hexmask.long.byte 0x1C 2.--5. 1. "TMODE,Timer Mode"
newline
bitfld.long 0x1C 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
line.long 0x20 "TCCR3,Timer Compare Capture Register"
hexmask.long 0x20 0.--31. 1. "TCC,Timer Capture Compare"
tree.end
tree "FLEXCOMM (Flexible Communications Interface)"
base ad:0x0
tree "FLEXCOMM0"
base ad:0x40106000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x0 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the USART..,1: This Flexcomm module includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected.,1: USART function selected,2: SPI function selected,3: I2C,4: I2S Transmit,5: I2S Receive,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
tree.end
tree "FLEXCOMM1"
base ad:0x40107000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x0 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the USART..,1: This Flexcomm module includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected.,1: USART function selected,2: SPI function selected,3: I2C,4: I2S Transmit,5: I2S Receive,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
tree.end
tree "FLEXCOMM2"
base ad:0x40108000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x0 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the USART..,1: This Flexcomm module includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected.,1: USART function selected,2: SPI function selected,3: I2C,4: I2S Transmit,5: I2S Receive,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
tree.end
tree "FLEXCOMM3"
base ad:0x40109000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x0 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the USART..,1: This Flexcomm module includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected.,1: USART function selected,2: SPI function selected,3: I2C,4: I2S Transmit,5: I2S Receive,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
tree.end
tree "FLEXCOMM14"
base ad:0x40126000
group.long 0xFF8++0x3
line.long 0x0 "PSELID,Peripheral Select and Flexcomm module ID"
hexmask.long.tbyte 0x0 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x0 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present"
newline
rbitfld.long 0x0 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present"
rbitfld.long 0x0 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function."
newline
rbitfld.long 0x0 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the USART..,1: This Flexcomm module includes the USART function."
bitfld.long 0x0 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software.,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x0 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected.,1: USART function selected,2: SPI function selected,3: I2C,4: I2S Transmit,5: I2S Receive,?,?"
rgroup.long 0xFFC++0x3
line.long 0x0 "PID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
tree.end
tree.end
tree "FLEXSPI (Flexible Serial Peripheral Interface)"
base ad:0x40134000
group.long 0x0++0x3F
line.long 0x0 "MCR0,Module Control Register 0"
hexmask.long.byte 0x0 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant."
newline
hexmask.long.byte 0x0 16.--23. 1. "IPGRANTWAIT,Time out wait cycle for IP command grant."
newline
bitfld.long 0x0 15. "LEARNEN,This bit is used to enable/disable data learning feature. When data learning is disabled the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction is correctly executed." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running. For FPGA applications external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled data sampling with loopback clock from SCLK pad is not supported.." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 13. "COMBINATIONEN,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]) when Port A and Port B are of 4 bit data width." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled. AHB clock and serial..,1: Doze mode support enabled. AHB clock and serial.."
newline
bitfld.long 0x0 11. "HSEN,Half Speed Serial Flash access Enable." "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.."
newline
bitfld.long 0x0 8.--10. "SERCLKDIV,Serial root clock" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
newline
bitfld.long 0x0 7. "ATDFEN,Enable AHB bus Write Access to IP TX FIFO." "0: IP TX FIFO should be written by IP Bus. AHB Bus..,1: IP TX FIFO should be written by AHB Bus. IP Bus.."
newline
bitfld.long 0x0 6. "ARDFEN,Enable AHB bus Read Access to IP RX FIFO." "0: IP RX FIFO should be read by IP Bus. AHB Bus..,1: IP RX FIFO should be read by AHB Bus. IP Bus.."
newline
bitfld.long 0x0 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,?,3: Flash provided Read strobe and input from DQS pad"
newline
bitfld.long 0x0 1. "MDIS,Module Disable" "0,1"
newline
bitfld.long 0x0 0. "SWRESET,Software Reset" "0,1"
line.long 0x4 "MCR1,Module Control Register 1"
hexmask.long.word 0x4 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
newline
hexmask.long.word 0x4 0.--15. 1. "AHBBUSWAIT,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles AHB Bus will get an error response"
line.long 0x8 "MCR2,Module Control Register 2"
hexmask.long.byte 0x8 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."
newline
bitfld.long 0x8 23. "RX_CLK_SRC_DIFF,Sample Clock source or source_b selection for Flash Reading" "0,1"
newline
bitfld.long 0x8 21.--22. "RXCLKSRC_B,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,2: SCLK output clock and loopback from SCLK..,3: Flash provided Read strobe and input from DQS pad"
newline
bitfld.long 0x8 19. "SCKBDIFFOPT,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case port B flash access is not available. After changing the value of this field MCR0[SWRESET] should be set." "0: B_SCLK pad is used as port B SCLK clock output.,1: B_SCLK pad is used as port A SCLK inverted clock.."
newline
bitfld.long 0x8 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2." "0: In Individual mode..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings.."
newline
bitfld.long 0x8 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately." "0,1"
newline
bitfld.long 0x8 11. "CLRAHBBUFOPT,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read.." "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned automatically.."
line.long 0xC "AHBCR,AHB Bus Control Register"
bitfld.long 0xC 10. "READSZALIGN,AHB Read Size Alignment" "0: AHB read size will be decided by other register..,1: AHB read size to up size to 8 bytes aligned no.."
newline
bitfld.long 0xC 6. "READADDROPT,AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation." "0: There is AHB read burst start address alignment..,1: There is no AHB read burst start address.."
newline
bitfld.long 0xC 5. "PREFETCHEN,AHB Read Prefetch Enable." "0,1"
newline
bitfld.long 0xC 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support." "0: Disabled. For all AHB write access (no matter..,1: Enabled. For AHB bufferable write access FlexSPI.."
newline
bitfld.long 0xC 3. "CACHABLEEN,Enable AHB bus cachable read access support." "0: Disabled. When there is AHB bus cachable read..,1: Enabled. When there is AHB bus cachable read.."
newline
bitfld.long 0xC 1. "CLRAHBRXBUF,Clear the status/pointers of AHB RX Buffer. Auto-cleared." "0,1"
newline
bitfld.long 0xC 0. "APAREN,Parallel mode enabled for AHB triggered Command (both read and write) ." "0: Flash will be accessed in Individual mode.,1: Flash will be accessed in Parallel mode."
line.long 0x10 "INTEN,Interrupt Enable Register"
bitfld.long 0x10 17. "AHBGCMERREN,AHB read gcm error interrupt enable." "0,1"
newline
bitfld.long 0x10 16. "IPCMDSECUREVIOEN,IP command security violation interrupt enable." "0,1"
newline
bitfld.long 0x10 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable." "0,1"
newline
bitfld.long 0x10 10. "AHBBUSTIMEOUTEN,AHB Bus timeout interrupt." "0,1"
newline
bitfld.long 0x10 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable." "0,1"
newline
bitfld.long 0x10 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable." "0,1"
newline
bitfld.long 0x10 7. "DATALEARNFAILEN,Data Learning failed interrupt enable." "0,1"
newline
bitfld.long 0x10 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable." "0,1"
newline
bitfld.long 0x10 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable." "0,1"
newline
bitfld.long 0x10 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable." "0,1"
newline
bitfld.long 0x10 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable." "0,1"
newline
bitfld.long 0x10 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable." "0,1"
newline
bitfld.long 0x10 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable." "0,1"
newline
bitfld.long 0x10 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable." "0,1"
line.long 0x14 "INTR,Interrupt Register"
eventfld.long 0x14 17. "AHBGCMERR,AHB read gcm error interrupt." "0,1"
newline
eventfld.long 0x14 16. "IPCMDSECUREVIO,IP command security violation interrupt." "0,1"
newline
eventfld.long 0x14 11. "SEQTIMEOUT,Sequence execution timeout interrupt." "0,1"
newline
eventfld.long 0x14 10. "AHBBUSTIMEOUT,AHB Bus timeout interrupt." "0,1"
newline
eventfld.long 0x14 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt." "0,1"
newline
eventfld.long 0x14 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt." "0,1"
newline
eventfld.long 0x14 7. "DATALEARNFAIL,Data Learning failed interrupt." "0,1"
newline
eventfld.long 0x14 6. "IPTXWE,IP TX FIFO watermark empty interrupt." "0,1"
newline
eventfld.long 0x14 5. "IPRXWA,IP RX FIFO watermark available interrupt." "0,1"
newline
eventfld.long 0x14 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command this command will be ignored and not executed at all." "0,1"
newline
eventfld.long 0x14 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command this command will be ignored and not executed at all." "0,1"
newline
eventfld.long 0x14 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt." "0,1"
newline
eventfld.long 0x14 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt." "0,1"
newline
eventfld.long 0x14 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated." "0,1"
line.long 0x18 "LUTKEY,LUT Key Register"
hexmask.long 0x18 0.--31. 1. "KEY,The Key to lock or unlock LUT."
line.long 0x1C "LUTCR,LUT Control Register"
bitfld.long 0x1C 2. "PROTECT,LUT protection" "0,1"
newline
bitfld.long 0x1C 1. "UNLOCK,Unlock LUT" "0,1"
newline
bitfld.long 0x1C 0. "LOCK,Lock LUT" "0,1"
line.long 0x20 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
bitfld.long 0x20 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x20 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x20 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x20 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x24 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
bitfld.long 0x24 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x24 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x24 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x24 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x24 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x28 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
bitfld.long 0x28 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x28 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x28 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x28 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x2C "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
bitfld.long 0x2C 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x2C 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x2C 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x2C 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x2C 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x30 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0"
bitfld.long 0x30 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x30 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x30 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x30 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x30 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x34 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0"
bitfld.long 0x34 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x34 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x34 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x34 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x34 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x38 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0"
bitfld.long 0x38 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x38 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x38 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x38 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x38 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
line.long 0x3C "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0"
bitfld.long 0x3C 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master." "0,1"
newline
bitfld.long 0x3C 30. "REGIONEN,AHB RX Buffer address region funciton enable" "0,1"
newline
bitfld.long 0x3C 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority 0 the lowest." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x3C 16.--19. 1. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."
newline
hexmask.long.byte 0x3C 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits."
group.long 0x60++0xF
line.long 0x0 "FLSHA1CR0,Flash Control Register 0"
bitfld.long 0x0 31. "SPLITRDEN,AHB read access split function control." "0,1"
newline
bitfld.long 0x0 30. "SPLITWREN,AHB write access split function control." "0,1"
newline
hexmask.long.tbyte 0x0 0.--22. 1. "FLSHSZ,Flash Size in KByte."
line.long 0x4 "FLSHA2CR0,Flash Control Register 0"
bitfld.long 0x4 31. "SPLITRDEN,AHB read access split function control." "0,1"
newline
bitfld.long 0x4 30. "SPLITWREN,AHB write access split function control." "0,1"
newline
hexmask.long.tbyte 0x4 0.--22. 1. "FLSHSZ,Flash Size in KByte."
line.long 0x8 "FLSHB1CR0,Flash Control Register 0"
bitfld.long 0x8 31. "SPLITRDEN,AHB read access split function control." "0,1"
newline
bitfld.long 0x8 30. "SPLITWREN,AHB write access split function control." "0,1"
newline
hexmask.long.tbyte 0x8 0.--22. 1. "FLSHSZ,Flash Size in KByte."
line.long 0xC "FLSHB2CR0,Flash Control Register 0"
bitfld.long 0xC 31. "SPLITRDEN,AHB read access split function control." "0,1"
newline
bitfld.long 0xC 30. "SPLITWREN,AHB write access split function control." "0,1"
newline
hexmask.long.tbyte 0xC 0.--22. 1. "FLSHSZ,Flash Size in KByte."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x70)++0x3
line.long 0x0 "FLSHCR1$1,Flash Control Register 1"
hexmask.long.word 0x0 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences this field should be set.."
newline
bitfld.long 0x0 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
newline
hexmask.long.byte 0x0 11.--14. 1. "CAS,Column Address Size."
newline
bitfld.long 0x0 10. "WA,Word Addressable." "0,1"
newline
hexmask.long.byte 0x0 5.--9. 1. "TCSH,Serial Flash CS Hold time."
newline
hexmask.long.byte 0x0 0.--4. 1. "TCSS,Serial Flash CS setup time."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x80)++0x3
line.long 0x0 "FLSHCR2$1,Flash Control Register 2"
bitfld.long 0x0 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS." "0,1"
newline
bitfld.long 0x0 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
newline
hexmask.long.word 0x0 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
newline
bitfld.long 0x0 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "AWRSEQID,Sequence Index for AHB Write triggered Command."
newline
bitfld.long 0x0 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT."
repeat.end
group.long 0x94++0x3
line.long 0x0 "FLSHCR4,Flash Control Register 4"
bitfld.long 0x0 11. "PAR_ADDR_ADJ_DIS,Disable the address shift logic for lower density of 16 bit PSRAM." "0,1"
newline
bitfld.long 0x0 9.--10. "PAR_WM,Enable APMEM 16 bit write mask function bit 9 for A1-B1 pair bit 10 for A2-B2 pair." "0,1,2,3"
newline
bitfld.long 0x0 3. "WMENB,Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B this bit must be set." "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
newline
bitfld.long 0x0 2. "WMENA,Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A this bit must be set." "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
newline
bitfld.long 0x0 1. "WMOPT2,Write mask option bit 2. When using AP memory This option bit could be used to remove AHB write burst minimal length limitation. When using this bit WMOPT1 should also be set." "0: DQS pin will be used as Write Mask when writing..,1: DQS pin will not be used as Write Mask when.."
newline
bitfld.long 0x0 0. "WMOPT1,Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation." "0: DQS pin will be used as Write Mask when writing..,1: DQS pin will not be used as Write Mask when.."
group.long 0xA0++0x7
line.long 0x0 "IPCR0,IP Control Register 0"
hexmask.long 0x0 0.--31. 1. "SFAR,Serial Flash Address for IP command."
line.long 0x4 "IPCR1,IP Control Register 1"
bitfld.long 0x4 31. "IPAREN,Parallel mode Enabled for IP command." "0: Flash will be accessed in Individual mode.,1: Flash will be accessed in Parallel mode."
newline
bitfld.long 0x4 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 16.--19. 1. "ISEQID,Sequence Index in LUT for IP command."
newline
hexmask.long.word 0x4 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command."
group.long 0xB0++0xF
line.long 0x0 "IPCMD,IP Command Register"
bitfld.long 0x0 0. "TRG,Setting this bit will trigger an IP Command." "0,1"
line.long 0x4 "DLPR,Data Learn Pattern Register"
hexmask.long 0x4 0.--31. 1. "DLP,Data Learning Pattern."
line.long 0x8 "IPRXFCR,IP RX FIFO Control Register"
hexmask.long.byte 0x8 2.--8. 1. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits."
newline
bitfld.long 0x8 1. "RXDMAEN,IP RX FIFO reading by DMA enabled." "0: IP RX FIFO would be read by processor.,1: IP RX FIFO would be read by DMA."
newline
bitfld.long 0x8 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO." "0,1"
line.long 0xC "IPTXFCR,IP TX FIFO Control Register"
hexmask.long.byte 0xC 2.--8. 1. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits."
newline
bitfld.long 0xC 1. "TXDMAEN,IP TX FIFO filling by DMA enabled." "0: IP TX FIFO would be filled by processor.,1: IP TX FIFO would be filled by DMA."
newline
bitfld.long 0xC 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO." "0,1"
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xC0)++0x3
line.long 0x0 "DLLCR$1,DLL Control Register 0"
hexmask.long.byte 0x0 9.--14. 1. "OVRDVAL,Slave clock delay line delay cell number selection override value."
newline
bitfld.long 0x0 8. "OVRDEN,Slave clock delay line delay cell number selection override enable." "0,1"
newline
hexmask.long.byte 0x0 3.--6. 1. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended."
newline
bitfld.long 0x0 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered so software need to clear this bit after.." "0,1"
newline
bitfld.long 0x0 0. "DLLEN,DLL calibration enable." "0,1"
repeat.end
rgroup.long 0xE0++0x1B
line.long 0x0 "STS0,Status Register 0"
hexmask.long.byte 0x0 8.--11. 1. "DATALEARNPHASEB,Indicate the sampling clock phase selection on Port B after Data Learning."
newline
hexmask.long.byte 0x0 4.--7. 1. "DATALEARNPHASEA,Indicate the sampling clock phase selection on Port A after Data Learning."
newline
bitfld.long 0x0 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1)." "0: Triggered by AHB read command (triggered by AHB..,1: Triggered by AHB write command (triggered by AHB..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)."
newline
bitfld.long 0x0 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle there will be no transaction on FlexSPI.." "0,1"
newline
bitfld.long 0x0 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface." "0,1"
line.long 0x4 "STS1,Status Register 1"
hexmask.long.byte 0x4 24.--27. 1. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c)."
newline
hexmask.long.byte 0x4 16.--19. 1. "IPCMDERRID,Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c)."
newline
hexmask.long.byte 0x4 8.--11. 1. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c)."
newline
hexmask.long.byte 0x4 0.--3. 1. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c)."
line.long 0x8 "STS2,Status Register 2"
hexmask.long.byte 0x8 24.--29. 1. "BREFSEL,Flash B sample clock reference delay line delay cell number selection."
newline
hexmask.long.byte 0x8 18.--23. 1. "BSLVSEL,Flash B sample clock slave delay line delay cell number selection."
newline
bitfld.long 0x8 17. "BREFLOCK,Flash B sample clock reference delay line locked." "0,1"
newline
bitfld.long 0x8 16. "BSLVLOCK,Flash B sample clock slave delay line locked." "0,1"
newline
hexmask.long.byte 0x8 8.--13. 1. "AREFSEL,Flash A sample clock reference delay line delay cell number selection."
newline
hexmask.long.byte 0x8 2.--7. 1. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection ."
newline
bitfld.long 0x8 1. "AREFLOCK,Flash A sample clock reference delay line locked." "0,1"
newline
bitfld.long 0x8 0. "ASLVLOCK,Flash A sample clock slave delay line locked." "0,1"
line.long 0xC "AHBSPNDSTS,AHB Suspend Status Register"
hexmask.long.word 0xC 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)."
newline
bitfld.long 0xC 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended." "0,1"
line.long 0x10 "IPRXFSTS,IP RX FIFO Status Register"
hexmask.long.word 0x10 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits."
newline
hexmask.long.byte 0x10 0.--7. 1. "FILL,Fill level of IP RX FIFO."
line.long 0x14 "IPTXFSTS,IP TX FIFO Status Register"
hexmask.long.word 0x14 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits."
newline
hexmask.long.byte 0x14 0.--7. 1. "FILL,Fill level of IP TX FIFO."
line.long 0x18 "VERID,IP Version ID Register"
hexmask.long.byte 0x18 24.--31. 1. "MAJOR,MSB 8bit of Version ID of design version."
newline
hexmask.long.byte 0x18 16.--23. 1. "MINOR,LSB 8bit of Version ID of design version."
newline
hexmask.long.word 0x18 0.--15. 1. "FEATURE,Feature of design version."
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x100)++0x3
line.long 0x0 "RFDR[$1],IP RX FIFO Data Register x"
hexmask.long 0x0 0.--31. 1. "RXDATA,RX Data"
repeat.end
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x180)++0x3
line.long 0x0 "TFDR[$1],IP TX FIFO Data Register x"
hexmask.long 0x0 0.--31. 1. "TXDATA,TX Data"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "LUT[$1],LUT x"
hexmask.long.byte 0x0 26.--31. 1. "OPCODE1,OPCODE1"
newline
bitfld.long 0x0 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--23. 1. "OPERAND1,OPERAND1"
newline
hexmask.long.byte 0x0 10.--15. 1. "OPCODE0,OPCODE"
newline
bitfld.long 0x0 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--7. 1. "OPERAND0,OPERAND0"
repeat.end
group.long 0x420++0xF
line.long 0x0 "HADDRSTART,HADDR REMAP START ADDR"
hexmask.long.tbyte 0x0 12.--31. 1. "ADDRSTART,HADDR remap range's start addr 4K aligned"
newline
bitfld.long 0x0 0. "REMAPEN,AHB Bus address remap function enable" "0: HADDR REMAP Disabled,1: HADDR REMAP Enabled"
line.long 0x4 "HADDREND,HADDR REMAP END ADDR"
hexmask.long.tbyte 0x4 12.--31. 1. "ENDSTART,HADDR remap range's end addr 4K aligned"
line.long 0x8 "HADDROFFSET,HADDR REMAP OFFSET"
hexmask.long.tbyte 0x8 12.--31. 1. "ADDROFFSET,HADDR offset field remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET"
line.long 0xC "IPEDCTRL,IPED function control"
bitfld.long 0xC 8. "AHBGCMRD,AHB read IPED GCM mode decryption enable" "0,1"
newline
bitfld.long 0xC 7. "AHGCMWR,AHB write IPED GCM mode encryption enable" "0,1"
newline
bitfld.long 0xC 6. "IPGCMWR,IP write GCM mode enable" "0,1"
newline
bitfld.long 0xC 5. "IPWROTA,IP GCM mode command write OTA region" "0,1"
newline
bitfld.long 0xC 4. "AHBRD_EN,AHB read IPED CTR mode decryption enable" "0,1"
newline
bitfld.long 0xC 3. "AHBWR_EN,AHB write IPED CTR mode encryption enable" "0,1"
newline
bitfld.long 0xC 2. "IPWR_EN,IP write IPED CTR mode encryption enable" "0,1"
newline
bitfld.long 0xC 1. "IPED_EN,Drive IPED interface i_enable" "0,1"
newline
bitfld.long 0xC 0. "CONFIG,Drive IPED interface i_config." "0,1"
group.long 0x440++0x1F
line.long 0x0 "AHBBUFREGIONSTART0,RX BUF Start address of region 0"
hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS,Start address of region 0. Minimal 4K Bytes aligned. It is system address."
line.long 0x4 "AHBBUFREGIONEND0,RX BUF region End address of region 0"
hexmask.long.tbyte 0x4 12.--31. 1. "END_ADDRESS,End address of region 0. Minimal 4K Bytes aligned. It is system address."
line.long 0x8 "AHBBUFREGIONSTART1,RX BUF Start address of region 1"
hexmask.long.tbyte 0x8 12.--31. 1. "START_ADDRESS,Start address of region 1. Minimal 4K Bytes aligned. It is system address."
line.long 0xC "AHBBUFREGIONEND1,RX BUF region End address of region 1"
hexmask.long.tbyte 0xC 12.--31. 1. "END_ADDRESS,End address of region 1. Minimal 4K Bytes aligned. It is system address."
line.long 0x10 "AHBBUFREGIONSTART2,RX BUF Start address of region 2"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS,Start address of region 2. Minimal 4K Bytes aligned. It is system address."
line.long 0x14 "AHBBUFREGIONEND2,RX BUF region End address of region 2"
hexmask.long.tbyte 0x14 12.--31. 1. "END_ADDRESS,End address of region 2. Minimal 4K Bytes aligned. It is system address."
line.long 0x18 "AHBBUFREGIONSTART3,RX BUF Start address of region 3"
hexmask.long.tbyte 0x18 12.--31. 1. "START_ADDRESS,Start address of region 3. Minimal 4K Bytes aligned. It is system address."
line.long 0x1C "AHBBUFREGIONEND3,RX BUF region End address of region 3"
hexmask.long.tbyte 0x1C 12.--31. 1. "END_ADDRESS,End address of region 3. Minimal 4K Bytes aligned. It is system address."
group.long 0x500++0x7
line.long 0x0 "IPEDCTXCTRL0,IPED context control 0"
bitfld.long 0x0 30.--31. "CTX15_FREEZE0,Controls the RW properties of this field and region 15 context registers (CTX15_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "CTX14_FREEZE0,Controls the RW properties of this field and region 14 context registers (CTX14_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "CTX13_FREEZE0,Controls the RW properties of this field and region 13 context registers (CTX13_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "CTX12_FREEZE0,Controls the RW properties of this field and region 12 context registers (CTX12_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "CTX11_FREEZE0,Controls the RW properties of this field and region 11 context registers (CTX11_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "CTX10_FREEZE0,Controls the RW properties of this field and region 10 context registers (CTX10_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "CTX9_FREEZE0,Controls the RW properties of this field and region 9 context registers (CTX9_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "CTX8_FREEZE0,Controls the RW properties of this field and region 8 context registers (CTX8_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "CTX7_FREEZE0,Controls the RW properties of this field and region 7 context registers (CTX7_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "CTX6_FREEZE0,Controls the RW properties of this field and region 6 context registers (CTX6_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "CTX5_FREEZE0,Controls the RW properties of this field and region 5 context registers (CTX5_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CTX4_FREEZE0,Controls the RW properties of this field and region 4 context registers (CTX4_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "CTX3_FREEZE0,Controls the RW properties of this field and region 3 context registers (CTX3_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "CTX2_FREEZE0,Controls the RW properties of this field and region 2 context registers (CTX2_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "CTX1_FREEZE0,Controls the RW properties of this field and region 1 context registers (CTX1_xxxx)." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CTX0_FREEZE0,Controls the RW properties of this field and region 0 context registers (CTX0_xxxx)." "0,1,2,3"
line.long 0x4 "IPEDCTXCTRL1,IPED context control 1"
bitfld.long 0x4 30.--31. "CTX15_FREEZE1,Controls the RW properties of this field and region 15 context registers (CTX15_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 28.--29. "CTX14_FREEZE1,Controls the RW properties of this field and region 14 context registers (CTX14_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "CTX13_FREEZE1,Controls the RW properties of this field and region 13 context registers (CTX13_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 24.--25. "CTX12_FREEZE1,Controls the RW properties of this field and region 12 context registers (CTX12_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "CTX11_FREEZE1,Controls the RW properties of this field and region 11 context registers (CTX11_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 20.--21. "CTX10_FREEZE1,Controls the RW properties of this field and region 10 context registers (CTX10_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "CTX9_FREEZE1,Controls the RW properties of this field and region 9 context registers (CTX9_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 16.--17. "CTX8_FREEZE1,Controls the RW properties of this field and region 8 context registers (CTX8_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "CTX7_FREEZE1,Controls the RW properties of this field and region 7 context registers (CTX7_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "CTX6_FREEZE1,Controls the RW properties of this field and region 6 context registers (CTX6_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "CTX5_FREEZE1,Controls the RW properties of this field and region 5 context registers (CTX5_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "CTX4_FREEZE1,Controls the RW properties of this field and region 4 context registers (CTX4_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "CTX3_FREEZE1,Controls the RW properties of this field and region 3 context registers (CTX3_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "CTX2_FREEZE1,Controls the RW properties of this field and region 2 context registers (CTX2_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "CTX1_FREEZE1,Controls the RW properties of this field and region 1 context registers (CTX1_xxxx)." "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "CTX0_FREEZE1,Controls the RW properties of this field and region 0 context registers (CTX0_xxxx)." "0,1,2,3"
group.long 0x520++0x17
line.long 0x0 "IPEDCTX0IV0,IPED context0 IV0"
hexmask.long 0x0 0.--31. 1. "CTX0_IV0,Lowest 32 bits of IV for region 0."
line.long 0x4 "IPEDCTX0IV1,IPED context0 IV1"
hexmask.long 0x4 0.--31. 1. "CTX0_IV1,Highest 32 bits of IV for region 0."
line.long 0x8 "IPEDCTX0START,Start address of region 0"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 0. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX0END,End address of region 0"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 0. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX0AAD0,IPED context0 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX0_AAD0,Lowest 32 bits of AAD for region 0."
line.long 0x14 "IPEDCTX0AAD1,IPED context0 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX0_AAD1,Highest 32 bits of AAD for region 0."
group.long 0x540++0x17
line.long 0x0 "IPEDCTX1IV0,IPED context1 IV0"
hexmask.long 0x0 0.--31. 1. "CTX1_IV0,Lowest 32 bits of IV for region 1."
line.long 0x4 "IPEDCTX1IV1,IPED context1 IV1"
hexmask.long 0x4 0.--31. 1. "CTX1_IV1,Highest 32 bits of IV for region 1."
line.long 0x8 "IPEDCTX1START,Start address of region 1"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 1. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX1END,End address of region 1"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 1. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX1AAD0,IPED context1 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX1_AAD0,Lowest 32 bits of AAD for region 1."
line.long 0x14 "IPEDCTX1AAD1,IPED context1 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX1_AAD1,Highest 32 bits of AAD for region 1."
group.long 0x560++0x17
line.long 0x0 "IPEDCTX2IV0,IPED context2 IV0"
hexmask.long 0x0 0.--31. 1. "CTX2_IV0,Lowest 32 bits of IV for region 2."
line.long 0x4 "IPEDCTX2IV1,IPED context2 IV1"
hexmask.long 0x4 0.--31. 1. "CTX2_IV1,Highest 32 bits of IV for region 2."
line.long 0x8 "IPEDCTX2START,Start address of region 2"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 2. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX2END,End address of region 2"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 2. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX2AAD0,IPED context2 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX2_AAD0,Lowest 32 bits of AAD for region 2."
line.long 0x14 "IPEDCTX2AAD1,IPED context2 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX2_AAD1,Highest 32 bits of AAD for region 2."
group.long 0x580++0x17
line.long 0x0 "IPEDCTX3IV0,IPED context3 IV0"
hexmask.long 0x0 0.--31. 1. "CTX3_IV0,Lowest 32 bits of IV for region 3."
line.long 0x4 "IPEDCTX3IV1,IPED context3 IV1"
hexmask.long 0x4 0.--31. 1. "CTX3_IV1,Highest 32 bits of IV for region 3."
line.long 0x8 "IPEDCTX3START,Start address of region 3"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 3. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX3END,End address of region 3"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 3. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX3AAD0,IPED context3 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX3_AAD0,Lowest 32 bits of AAD for region 3."
line.long 0x14 "IPEDCTX3AAD1,IPED context3 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX3_AAD1,Highest 32 bits of AAD for region 3."
group.long 0x5A0++0x17
line.long 0x0 "IPEDCTX4IV0,IPED context4 IV0"
hexmask.long 0x0 0.--31. 1. "CTX4_IV0,Lowest 32 bits of IV for region 4."
line.long 0x4 "IPEDCTX4IV1,IPED context4 IV1"
hexmask.long 0x4 0.--31. 1. "CTX4_IV1,Highest 32 bits of IV for region 4."
line.long 0x8 "IPEDCTX4START,Start address of region 4"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 4. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX4END,End address of region 4"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 4. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX4AAD0,IPED context4 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX4_AAD0,Lowest 32 bits of AAD for region 4."
line.long 0x14 "IPEDCTX4AAD1,IPED context4 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX4_AAD1,Highest 32 bits of AAD for region 4."
group.long 0x5C0++0x17
line.long 0x0 "IPEDCTX5IV0,IPED context5 IV0"
hexmask.long 0x0 0.--31. 1. "CTX5_IV0,Lowest 32 bits of IV for region 5."
line.long 0x4 "IPEDCTX5IV1,IPED context5 IV1"
hexmask.long 0x4 0.--31. 1. "CTX5_IV1,Highest 32 bits of IV for region 5."
line.long 0x8 "IPEDCTX5START,Start address of region 5"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 5. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX5END,End address of region 5"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 5. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX5AAD0,IPED context5 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX5_AAD0,Lowest 32 bits of AAD for region 5."
line.long 0x14 "IPEDCTX5AAD1,IPED context5 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX5_AAD1,Highest 32 bits of AAD for region 5."
group.long 0x5E0++0x17
line.long 0x0 "IPEDCTX6IV0,IPED context6 IV0"
hexmask.long 0x0 0.--31. 1. "CTX6_IV0,Lowest 32 bits of IV for region 6."
line.long 0x4 "IPEDCTX6IV1,IPED context6 IV1"
hexmask.long 0x4 0.--31. 1. "CTX6_IV1,Highest 32 bits of IV for region 6."
line.long 0x8 "IPEDCTX6START,Start address of region 6"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 6. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX6END,End address of region 6"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 6. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX6AAD0,IPED context6 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX6_AAD0,Lowest 32 bits of AAD for region 6."
line.long 0x14 "IPEDCTX6AAD1,IPED context6 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX6_AAD1,Highest 32 bits of AAD for region 6."
group.long 0x600++0x17
line.long 0x0 "IPEDCTX7IV0,IPED context7 IV0"
hexmask.long 0x0 0.--31. 1. "CTX7_IV0,Lowest 32 bits of IV for region 7."
line.long 0x4 "IPEDCTX7IV1,IPED context7 IV1"
hexmask.long 0x4 0.--31. 1. "CTX7_IV1,Highest 32 bits of IV for region 7."
line.long 0x8 "IPEDCTX7START,Start address of region 7"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 7. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX7END,End address of region 7"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 7. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX7AAD0,IPED context7 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX7_AAD0,Lowest 32 bits of AAD for region 7."
line.long 0x14 "IPEDCTX7AAD1,IPED context7 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX7_AAD1,Highest 32 bits of AAD for region 7."
group.long 0x620++0x17
line.long 0x0 "IPEDCTX8IV0,IPED context8 IV0"
hexmask.long 0x0 0.--31. 1. "CTX8_IV0,Lowest 32 bits of IV for region 8."
line.long 0x4 "IPEDCTX8IV1,IPED context8 IV1"
hexmask.long 0x4 0.--31. 1. "CTX8_IV1,Highest 32 bits of IV for region 8."
line.long 0x8 "IPEDCTX8START,Start address of region 8"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 8. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX8END,End address of region 8"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 8. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX8AAD0,IPED context8 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX8_AAD0,Lowest 32 bits of AAD for region 8."
line.long 0x14 "IPEDCTX8AAD1,IPED context8 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX8_AAD1,Highest 32 bits of AAD for region 8."
group.long 0x640++0x17
line.long 0x0 "IPEDCTX9IV0,IPED context9 IV0"
hexmask.long 0x0 0.--31. 1. "CTX9_IV0,Lowest 32 bits of IV for region 9."
line.long 0x4 "IPEDCTX9IV1,IPED context9 IV1"
hexmask.long 0x4 0.--31. 1. "CTX9_IV1,Highest 32 bits of IV for region 9."
line.long 0x8 "IPEDCTX9START,Start address of region 9"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 9. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX9END,End address of region 9"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 9. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX9AAD0,IPED context9 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX9_AAD0,Lowest 32 bits of AAD for region 9."
line.long 0x14 "IPEDCTX9AAD1,IPED context9 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX9_AAD1,Highest 32 bits of AAD for region 9."
group.long 0x660++0x17
line.long 0x0 "IPEDCTX10IV0,IPED context10 IV0"
hexmask.long 0x0 0.--31. 1. "CTX10_IV0,Lowest 32 bits of IV for region 10."
line.long 0x4 "IPEDCTX10IV1,IPED context10 IV1"
hexmask.long 0x4 0.--31. 1. "CTX10_IV1,Highest 32 bits of IV for region 10."
line.long 0x8 "IPEDCTX10START,Start address of region 10"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 10. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX10END,End address of region 10"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 10. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX10AAD0,IPED context10 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX10_AAD0,Lowest 32 bits of AAD for region 10."
line.long 0x14 "IPEDCTX10AAD1,IPED context10 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX10_AAD1,Highest 32 bits of AAD for region 10."
group.long 0x680++0x17
line.long 0x0 "IPEDCTX11IV0,IPED context11 IV0"
hexmask.long 0x0 0.--31. 1. "CTX11_IV0,Lowest 32 bits of IV for region 11."
line.long 0x4 "IPEDCTX11IV1,IPED context11 IV1"
hexmask.long 0x4 0.--31. 1. "CTX11_IV1,Highest 32 bits of IV for region 11."
line.long 0x8 "IPEDCTX11START,Start address of region 11"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 11. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX11END,End address of region 11"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 11. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX11AAD0,IPED context11 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX11_AAD0,Lowest 32 bits of AAD for region 11."
line.long 0x14 "IPEDCTX11AAD1,IPED context11 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX11_AAD1,Highest 32 bits of AAD for region 11."
group.long 0x6A0++0x17
line.long 0x0 "IPEDCTX12IV0,IPED context12 IV0"
hexmask.long 0x0 0.--31. 1. "CTX12_IV0,Lowest 32 bits of IV for region 12."
line.long 0x4 "IPEDCTX12IV1,IPED context12 IV1"
hexmask.long 0x4 0.--31. 1. "CTX12_IV1,Highest 32 bits of IV for region 12."
line.long 0x8 "IPEDCTX12START,Start address of region 12"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 12. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX12END,End address of region 12"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 12. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX12AAD0,IPED context12 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX12_AAD0,Lowest 32 bits of AAD for region 12."
line.long 0x14 "IPEDCTX12AAD1,IPED context12 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX12_AAD1,Highest 32 bits of AAD for region 12."
group.long 0x6C0++0x17
line.long 0x0 "IPEDCTX13IV0,IPED context13 IV0"
hexmask.long 0x0 0.--31. 1. "CTX13_IV0,Lowest 32 bits of IV for region 13."
line.long 0x4 "IPEDCTX13IV1,IPED context13 IV1"
hexmask.long 0x4 0.--31. 1. "CTX13_IV1,Highest 32 bits of IV for region 13."
line.long 0x8 "IPEDCTX13START,Start address of region 13"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 13. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX13END,End address of region 13"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 13. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX13AAD0,IPED context13 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX13_AAD0,Lowest 32 bits of AAD for region 13."
line.long 0x14 "IPEDCTX13AAD1,IPED context13 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX13_AAD1,Highest 32 bits of AAD for region 13."
group.long 0x6E0++0x17
line.long 0x0 "IPEDCTX14IV0,IPED context14 IV0"
hexmask.long 0x0 0.--31. 1. "CTX14_IV0,Lowest 32 bits of IV for region 14."
line.long 0x4 "IPEDCTX14IV1,IPED context14 IV1"
hexmask.long 0x4 0.--31. 1. "CTX14_IV1,Highest 32 bits of IV for region 14."
line.long 0x8 "IPEDCTX14START,Start address of region 14"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 14. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX14END,End address of region 14"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 14. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX14AAD0,IPED context14 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX14_AAD0,Lowest 32 bits of AAD for region 14."
line.long 0x14 "IPEDCTX14AAD1,IPED context14 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX14_AAD1,Highest 32 bits of AAD for region 14."
group.long 0x700++0x17
line.long 0x0 "IPEDCTX15IV0,IPED context15 IV0"
hexmask.long 0x0 0.--31. 1. "CTX15_IV0,Lowest 32 bits of IV for region 15."
line.long 0x4 "IPEDCTX15IV1,IPED context15 IV1"
hexmask.long 0x4 0.--31. 1. "CTX15_IV1,Highest 32 bits of IV for region 15."
line.long 0x8 "IPEDCTX15START,Start address of region 15"
hexmask.long.tbyte 0x8 8.--31. 1. "START_ADDRESS,Start address of region 15. Minimal 256 Bytes aligned. It is system address."
newline
bitfld.long 0x8 1. "AHBBUSERROR_DIS,If this bit is 1 ahb bus error is disable." "0,1"
newline
bitfld.long 0x8 0. "GCM,If this bit is 1 current region is GCM mode region." "0,1"
line.long 0xC "IPEDCTX15END,End address of region 15"
hexmask.long.tbyte 0xC 8.--31. 1. "END_ADDRESS,End address of region 15. Minimal 256 Bytes aligned. It is system address."
line.long 0x10 "IPEDCTX15AAD0,IPED context15 AAD0"
hexmask.long 0x10 0.--31. 1. "CTX15_AAD0,Lowest 32 bits of AAD for region 15."
line.long 0x14 "IPEDCTX15AAD1,IPED context15 AAD1"
hexmask.long 0x14 0.--31. 1. "CTX15_AAD1,Highest 32 bits of AAD for region 15."
tree.end
tree "FLEXSPI_CACHE"
base ad:0x0
tree "CACHE64_CTRL0"
base ad:0x40033000
group.long 0x800++0xF
line.long 0x0 "CCR,Cache control register"
bitfld.long 0x0 31. "GO,Initiate Cache Command" "0: Write: no effect. Read: no cache command active.,1: Write: initiate command indicated by bits 27-24."
bitfld.long 0x0 27. "PUSHW1,Push Way 1" "0: No operation,1: When setting the GO bit push all modified lines.."
newline
bitfld.long 0x0 26. "INVW1,Invalidate Way 1" "0: No operation,1: When setting the GO bit invalidate all lines in.."
bitfld.long 0x0 25. "PUSHW0,Push Way 0" "0: No operation,1: When setting the GO bit push all modified lines.."
newline
bitfld.long 0x0 24. "INVW0,Invalidate Way 0" "0: No operation,1: When setting the GO bit invalidate all lines in.."
bitfld.long 0x0 1. "ENWRBUF,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled"
newline
bitfld.long 0x0 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled"
line.long 0x4 "CLCR,Cache line control register"
bitfld.long 0x4 27. "LACC,Line access type" "0: Read,1: Write"
bitfld.long 0x4 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address"
newline
bitfld.long 0x4 24.--25. "LCMD,Line Command" "0: Search and read or write,1: Invalidate,2: Push,3: Clear"
bitfld.long 0x4 22. "LCWAY,Line Command Way" "0,1"
newline
bitfld.long 0x4 21. "LCIMB,Line Command Initial Modified Bit" "0,1"
bitfld.long 0x4 20. "LCIVB,Line Command Initial Valid Bit" "0,1"
newline
bitfld.long 0x4 16. "TDSEL,Tag/Data Select" "0: Data,1: Tag"
bitfld.long 0x4 14. "WSEL,Way select" "0: Way 0,1: Way 1"
newline
hexmask.long.word 0x4 2.--13. 1. "CACHEADDR,Cache address"
bitfld.long 0x4 0. "LGO,Initiate Cache Line Command" "0: Write: no effect. Read: no line command active.,1: Write: initiate line command indicated by bits.."
line.long 0x8 "CSAR,Cache search address register"
hexmask.long 0x8 1.--31. 1. "PHYADDR,Physical Address"
bitfld.long 0x8 0. "LGO,Initiate Cache Line Command" "0: Write: no effect. Read: no line command active.,1: Write: initiate line command indicated by bits.."
line.long 0xC "CCVR,Cache read/write value register"
hexmask.long 0xC 0.--31. 1. "DATA,Cache read/write Data"
tree.end
tree "CACHE64_CTRL1"
base ad:0x40034000
group.long 0x800++0xF
line.long 0x0 "CCR,Cache control register"
bitfld.long 0x0 31. "GO,Initiate Cache Command" "0: Write: no effect. Read: no cache command active.,1: Write: initiate command indicated by bits 27-24."
bitfld.long 0x0 27. "PUSHW1,Push Way 1" "0: No operation,1: When setting the GO bit push all modified lines.."
newline
bitfld.long 0x0 26. "INVW1,Invalidate Way 1" "0: No operation,1: When setting the GO bit invalidate all lines in.."
bitfld.long 0x0 25. "PUSHW0,Push Way 0" "0: No operation,1: When setting the GO bit push all modified lines.."
newline
bitfld.long 0x0 24. "INVW0,Invalidate Way 0" "0: No operation,1: When setting the GO bit invalidate all lines in.."
bitfld.long 0x0 1. "ENWRBUF,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled"
newline
bitfld.long 0x0 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled"
line.long 0x4 "CLCR,Cache line control register"
bitfld.long 0x4 27. "LACC,Line access type" "0: Read,1: Write"
bitfld.long 0x4 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address"
newline
bitfld.long 0x4 24.--25. "LCMD,Line Command" "0: Search and read or write,1: Invalidate,2: Push,3: Clear"
bitfld.long 0x4 22. "LCWAY,Line Command Way" "0,1"
newline
bitfld.long 0x4 21. "LCIMB,Line Command Initial Modified Bit" "0,1"
bitfld.long 0x4 20. "LCIVB,Line Command Initial Valid Bit" "0,1"
newline
bitfld.long 0x4 16. "TDSEL,Tag/Data Select" "0: Data,1: Tag"
bitfld.long 0x4 14. "WSEL,Way select" "0: Way 0,1: Way 1"
newline
hexmask.long.word 0x4 2.--13. 1. "CACHEADDR,Cache address"
bitfld.long 0x4 0. "LGO,Initiate Cache Line Command" "0: Write: no effect. Read: no line command active.,1: Write: initiate line command indicated by bits.."
line.long 0x8 "CSAR,Cache search address register"
hexmask.long 0x8 1.--31. 1. "PHYADDR,Physical Address"
bitfld.long 0x8 0. "LGO,Initiate Cache Line Command" "0: Write: no effect. Read: no line command active.,1: Write: initiate line command indicated by bits.."
line.long 0xC "CCVR,Cache read/write value register"
hexmask.long 0xC 0.--31. 1. "DATA,Cache read/write Data"
tree.end
tree.end
tree "FREQME (Frequency Measurement)"
base ad:0x4002F000
group.long 0x0++0x3
line.long 0x0 "FREQMECTRL,freqeuncy measurement register when read"
bitfld.long 0x0 31. "MEASURE_IN_PROG,Initiates a frequency measurement cycle" "0: when write 0 Force to terminate currently in..,1: when wrtie 1 Initiates a frequency measurement.."
bitfld.long 0x0 9. "PULSE_POL,high or low period of reference clock is measured in pulse width measurement mode" "0: High period of reference clock is measured in..,1: Low period of reference clock is measured in.."
newline
bitfld.long 0x0 8. "PULSE_MODE,pulse width measurement mode" "0: It works as frequency measurement mode.,1: It works as pulse width measurement mode. It.."
hexmask.long.byte 0x0 0.--4. 1. "REF_SCALE,Select reference clock counter scaling factor (measurement period). The count cycle is 2^ref_scale. This field is valid only in frequency measurement mode."
tree.end
tree "GDMA"
base ad:0x4014E000
group.long 0x40++0x27
line.long 0x0 "SADR1,DMA SOURCE ADDRESS REGISTERS"
hexmask.long 0x0 0.--31. 1. "SRCADDR,SOURCE ADDRESS"
line.long 0x4 "DADR1,DMA DESTINATION ADDRESS REGISTERS"
hexmask.long 0x4 0.--31. 1. "DESTADDR,DESTINATION ADDRESS"
line.long 0x8 "LLI1,DMA CHANNEL LINKED LIST ITEM REGISTERS"
hexmask.long 0x8 4.--31. 1. "LLI,LINKED LIST ITEM ADDRESS"
bitfld.long 0x8 1. "DESC_INT_EN,the interrupt enable for descriptor finish" "0,1"
bitfld.long 0x8 0. "STOP,STOP the channel after transaction is finished" "0,1"
line.long 0xC "CTRL1,DMA CONTROL REGISTERS"
bitfld.long 0xC 29.--31. "PROT,Protection info for AHB master bus" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 28. "SRCADDRINC,Source address increment" "0,1"
bitfld.long 0xC 27. "DESTADDRINC,destination address increment" "0,1"
bitfld.long 0xC 25.--26. "SRCWIDTH,Source peripheral/memory transfer width" "0,1,2,3"
newline
bitfld.long 0xC 23.--24. "DESTWIDTH,Destination peripheral/memory transfer width" "0,1,2,3"
bitfld.long 0xC 20.--22. "SRCBSIZE,Source peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 17.--19. "DESTBSIZE,Destination peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
hexmask.long.word 0xC 0.--12. 1. "LEN,Length of the transfer in bytes"
line.long 0x10 "CONFIG1,DMA CONFIGURE REGISTERS"
rbitfld.long 0x10 31. "FIFO_EMPTY,FIFO status of current channel" "0,1"
bitfld.long 0x10 30. "HW_EN,Hardware enable configuration of current channel" "0,1"
bitfld.long 0x10 27.--29. "HW_EN_SRC,hardware enable trigger source" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--25. "DMA_CRC_MODE,crc input data source select" "0,1,2,3"
newline
bitfld.long 0x10 20. "CRC_DATAIN_FORMAT_SEL,CRC input data format select if the dma_crc_mode is not configured to 2'b11 this field can only be confiured to 1" "0,1"
bitfld.long 0x10 16.--18. "CRC_MODE,CRC mode select if this filed is not configured to to 3'b011 the crc_ini_value[31:16]=16'b0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 13.--15. "FLOWCNTL,flow controller and transfer type" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 7.--12. 1. "SRC_PER,peripheral number"
newline
hexmask.long.byte 0x10 1.--6. 1. "DEST_PER,peripheral number"
bitfld.long 0x10 0. "LLE,Link List Enable" "0,1"
line.long 0x14 "CHL_EN1,DMA CHANNEL ENABLE REGISTERS"
bitfld.long 0x14 31. "CHL_EN,Enable/Disable the channel" "0,1"
hexmask.long.byte 0x14 4.--7. 1. "TEST_BUS_SIGNAL_SEL,TEST_BUS_SIGNAL_SEL"
hexmask.long.byte 0x14 0.--3. 1. "CHL_PRIORITY_WEIGHT,DMA Channel Priority Weight"
line.long 0x18 "CHL_STOP1,DMA CHANNEL STOP REGISTERS"
bitfld.long 0x18 31. "CHL_STOP,Stop the running channel" "0,1"
line.long 0x1C "CHNL_INT1,DMA INT REGISTERS"
bitfld.long 0x1C 31. "CRC_INT_STATUS,CRC calculation interrupt status" "0,1"
bitfld.long 0x1C 30. "CRC_INT_MASK,Mask of crc_done interrupt" "0,1"
bitfld.long 0x1C 10. "DESC_STATUS_TFRINT,configurable descriptor transfer interrupt bit" "0,1"
bitfld.long 0x1C 9. "MASK_DESC_TFRINT,descriptor transfer interrupt mask bit" "0,1"
newline
rbitfld.long 0x1C 8. "STATUS_CHLINT,DMA channel interrupt" "0,1"
bitfld.long 0x1C 7. "STATUS_ADDRERRINT,DMA Channel source/destination address alignment error interrupt bit" "0,1"
bitfld.long 0x1C 6. "MASK_ADDRERRINT,DMA Channel source/destination address alignment error interrupt mask bit" "0,1"
bitfld.long 0x1C 5. "STATUS_BUSERRINT,DMA channel bus error interrupt bit" "0,1"
newline
bitfld.long 0x1C 4. "MASK_BUSERRINT,DMA channel bus error interrupt mask bit" "0,1"
bitfld.long 0x1C 3. "STATUS_TFRINT,transfer interrupt bit" "0,1"
bitfld.long 0x1C 2. "MASK_TFRINT,transfer interrupt mask bit" "0,1"
bitfld.long 0x1C 1. "STATUS_BLOCKINT,DMA channel block transfer interrupt bit" "0,1"
newline
bitfld.long 0x1C 0. "MASK_BLOCKINT,DMA channel block transfer interrupt mask bit" "0,1"
line.long 0x20 "CRC_CPU_DATA_IN1,Stream Input Register"
hexmask.long 0x20 0.--31. 1. "DATA,Stream input data register"
line.long 0x24 "CRC_INI_VALUE1,CRC Calculation initial value"
hexmask.long 0x24 0.--31. 1. "DATA,CRC calculation initial value"
rgroup.long 0x68++0x3
line.long 0x0 "CRC_RESULT1,CRC Calculation Result"
hexmask.long 0x0 0.--31. 1. "DATA,CRC calculation result"
group.long 0x6C++0x7
line.long 0x0 "CRC_LEN1,Stream Input length"
hexmask.long 0x0 0.--31. 1. "DATA,crc Stream input data length it should be equal to the CONFIG.len when it's normal work. but in linklist it should be the total length for crc calculation"
line.long 0x4 "NUM_OF_DESCRIPTOR1,the number of descriptor"
hexmask.long 0x4 0.--31. 1. "DATA,the number of descriptor"
group.long 0x80++0x27
line.long 0x0 "SADR2,DMA SOURCE ADDRESS REGISTERS"
hexmask.long 0x0 0.--31. 1. "SRCADDR,SOURCE ADDRESS"
line.long 0x4 "DADR2,DMA DESTINATION ADDRESS REGISTERS"
hexmask.long 0x4 0.--31. 1. "DESTADDR,DESTINATION ADDRESS"
line.long 0x8 "LLI2,DMA CHANNEL LINKED LIST ITEM REGISTERS"
hexmask.long 0x8 4.--31. 1. "LLI,LINKED LIST ITEM ADDRESS"
bitfld.long 0x8 1. "DESC_INT_EN,the interrupt enable for descriptor finish" "0,1"
bitfld.long 0x8 0. "STOP,STOP the channel after transaction is finished" "0,1"
line.long 0xC "CTRL2,DMA CONTROL REGISTERS"
bitfld.long 0xC 29.--31. "PROT,Protection info for AHB master bus" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 28. "SRCADDRINC,Source address increment" "0,1"
bitfld.long 0xC 27. "DESTADDRINC,destination address increment" "0,1"
bitfld.long 0xC 25.--26. "SRCWIDTH,Source peripheral/memory transfer width" "0,1,2,3"
newline
bitfld.long 0xC 23.--24. "DESTWIDTH,Destination peripheral/memory transfer width" "0,1,2,3"
bitfld.long 0xC 20.--22. "SRCBSIZE,Source peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 17.--19. "DESTBSIZE,Destination peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
hexmask.long.word 0xC 0.--12. 1. "LEN,Length of the transfer in bytes"
line.long 0x10 "CONFIG2,DMA CONFIGURE REGISTERS"
rbitfld.long 0x10 31. "FIFO_EMPTY,FIFO status of current channel" "0,1"
bitfld.long 0x10 30. "HW_EN,Hardware enable configuration of current channel" "0,1"
bitfld.long 0x10 27.--29. "HW_EN_SRC,hardware enable trigger source" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--25. "DMA_CRC_MODE,crc input data source select" "0,1,2,3"
newline
bitfld.long 0x10 20. "CRC_DATAIN_FORMAT_SEL,CRC input data format select if the dma_crc_mode is not configured to 2'b11 this field can only be confiured to 1" "0,1"
bitfld.long 0x10 16.--18. "CRC_MODE,CRC mode select if this filed is not configured to to 3'b011 the crc_ini_value[31:16]=16'b0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 13.--15. "FLOWCNTL,flow controller and transfer type" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 7.--12. 1. "SRC_PER,peripheral number"
newline
hexmask.long.byte 0x10 1.--6. 1. "DEST_PER,peripheral number"
bitfld.long 0x10 0. "LLE,Link List Enable" "0,1"
line.long 0x14 "CHL_EN2,DMA CHANNEL ENABLE REGISTERS"
bitfld.long 0x14 31. "CHL_EN,Enable/Disable the channel" "0,1"
hexmask.long.byte 0x14 4.--7. 1. "TEST_BUS_SIGNAL_SEL,TEST_BUS_SIGNAL_SEL"
hexmask.long.byte 0x14 0.--3. 1. "CHL_PRIORITY_WEIGHT,DMA Channel Priority Weight"
line.long 0x18 "CHL_STOP2,DMA CHANNEL STOP REGISTERS"
bitfld.long 0x18 31. "CHL_STOP,Stop the running channel" "0,1"
line.long 0x1C "CHNL_INT2,DMA INT REGISTERS"
bitfld.long 0x1C 31. "CRC_INT_STATUS,CRC calculation interrupt status" "0,1"
bitfld.long 0x1C 30. "CRC_INT_MASK,Mask of crc_done interrupt" "0,1"
bitfld.long 0x1C 10. "DESC_STATUS_TFRINT,configurable descriptor transfer interrupt bit" "0,1"
bitfld.long 0x1C 9. "MASK_DESC_TFRINT,descriptor transfer interrupt mask bit" "0,1"
newline
rbitfld.long 0x1C 8. "STATUS_CHLINT,DMA channel interrupt" "0,1"
bitfld.long 0x1C 7. "STATUS_ADDRERRINT,DMA Channel source/destination address alignment error interrupt bit" "0,1"
bitfld.long 0x1C 6. "MASK_ADDRERRINT,DMA Channel source/destination address alignment error interrupt mask bit" "0,1"
bitfld.long 0x1C 5. "STATUS_BUSERRINT,DMA channel bus error interrupt bit" "0,1"
newline
bitfld.long 0x1C 4. "MASK_BUSERRINT,DMA channel bus error interrupt mask bit" "0,1"
bitfld.long 0x1C 3. "STATUS_TFRINT,transfer interrupt bit" "0,1"
bitfld.long 0x1C 2. "MASK_TFRINT,transfer interrupt mask bit" "0,1"
bitfld.long 0x1C 1. "STATUS_BLOCKINT,DMA channel block transfer interrupt bit" "0,1"
newline
bitfld.long 0x1C 0. "MASK_BLOCKINT,DMA channel block transfer interrupt mask bit" "0,1"
line.long 0x20 "CRC_CPU_DATA_IN2,Stream Input Register"
hexmask.long 0x20 0.--31. 1. "DATA,Stream input data register"
line.long 0x24 "CRC_INI_VALUE2,CRC Calculation initial value"
hexmask.long 0x24 0.--31. 1. "DATA,CRC calculation initial value"
rgroup.long 0xA8++0x3
line.long 0x0 "CRC_RESULT2,CRC Calculation Result"
hexmask.long 0x0 0.--31. 1. "DATA,CRC calculation result"
group.long 0xAC++0x7
line.long 0x0 "CRC_LEN2,Stream Input length"
hexmask.long 0x0 0.--31. 1. "DATA,crc Stream input data length it should be equal to the CONFIG.len when it's normal work. but in linklist it should be the total length for crc calculation"
line.long 0x4 "NUM_OF_DESCRIPTOR2,the number of descriptor"
hexmask.long 0x4 0.--31. 1. "DATA,the number of descriptor"
group.long 0xC0++0x27
line.long 0x0 "SADR3,DMA SOURCE ADDRESS REGISTERS"
hexmask.long 0x0 0.--31. 1. "SRCADDR,SOURCE ADDRESS"
line.long 0x4 "DADR3,DMA DESTINATION ADDRESS REGISTERS"
hexmask.long 0x4 0.--31. 1. "DESTADDR,DESTINATION ADDRESS"
line.long 0x8 "LLI3,DMA CHANNEL LINKED LIST ITEM REGISTERS"
hexmask.long 0x8 4.--31. 1. "LLI,LINKED LIST ITEM ADDRESS"
bitfld.long 0x8 1. "DESC_INT_EN,the interrupt enable for descriptor finish" "0,1"
bitfld.long 0x8 0. "STOP,STOP the channel after transaction is finished" "0,1"
line.long 0xC "CTRL3,DMA CONTROL REGISTERS"
bitfld.long 0xC 29.--31. "PROT,Protection info for AHB master bus" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 28. "SRCADDRINC,Source address increment" "0,1"
bitfld.long 0xC 27. "DESTADDRINC,destination address increment" "0,1"
bitfld.long 0xC 25.--26. "SRCWIDTH,Source peripheral/memory transfer width" "0,1,2,3"
newline
bitfld.long 0xC 23.--24. "DESTWIDTH,Destination peripheral/memory transfer width" "0,1,2,3"
bitfld.long 0xC 20.--22. "SRCBSIZE,Source peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 17.--19. "DESTBSIZE,Destination peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
hexmask.long.word 0xC 0.--12. 1. "LEN,Length of the transfer in bytes"
line.long 0x10 "CONFIG3,DMA CONFIGURE REGISTERS"
rbitfld.long 0x10 31. "FIFO_EMPTY,FIFO status of current channel" "0,1"
bitfld.long 0x10 30. "HW_EN,Hardware enable configuration of current channel" "0,1"
bitfld.long 0x10 27.--29. "HW_EN_SRC,hardware enable trigger source" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--25. "DMA_CRC_MODE,crc input data source select" "0,1,2,3"
newline
bitfld.long 0x10 20. "CRC_DATAIN_FORMAT_SEL,CRC input data format select if the dma_crc_mode is not configured to 2'b11 this field can only be confiured to 1" "0,1"
bitfld.long 0x10 16.--18. "CRC_MODE,CRC mode select if this filed is not configured to to 3'b011 the crc_ini_value[31:16]=16'b0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 13.--15. "FLOWCNTL,flow controller and transfer type" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 7.--12. 1. "SRC_PER,peripheral number"
newline
hexmask.long.byte 0x10 1.--6. 1. "DEST_PER,peripheral number"
bitfld.long 0x10 0. "LLE,Link List Enable" "0,1"
line.long 0x14 "CHL_EN3,DMA CHANNEL ENABLE REGISTERS"
bitfld.long 0x14 31. "CHL_EN,Enable/Disable the channel" "0,1"
hexmask.long.byte 0x14 4.--7. 1. "TEST_BUS_SIGNAL_SEL,TEST_BUS_SIGNAL_SEL"
hexmask.long.byte 0x14 0.--3. 1. "CHL_PRIORITY_WEIGHT,DMA Channel Priority Weight"
line.long 0x18 "CHL_STOP3,DMA CHANNEL STOP REGISTERS"
bitfld.long 0x18 31. "CHL_STOP,Stop the running channel" "0,1"
line.long 0x1C "CHNL_INT3,DMA INT REGISTERS"
bitfld.long 0x1C 31. "CRC_INT_STATUS,CRC calculation interrupt status" "0,1"
bitfld.long 0x1C 30. "CRC_INT_MASK,Mask of crc_done interrupt" "0,1"
bitfld.long 0x1C 10. "DESC_STATUS_TFRINT,configurable descriptor transfer interrupt bit" "0,1"
bitfld.long 0x1C 9. "MASK_DESC_TFRINT,descriptor transfer interrupt mask bit" "0,1"
newline
rbitfld.long 0x1C 8. "STATUS_CHLINT,DMA channel interrupt" "0,1"
bitfld.long 0x1C 7. "STATUS_ADDRERRINT,DMA Channel source/destination address alignment error interrupt bit" "0,1"
bitfld.long 0x1C 6. "MASK_ADDRERRINT,DMA Channel source/destination address alignment error interrupt mask bit" "0,1"
bitfld.long 0x1C 5. "STATUS_BUSERRINT,DMA channel bus error interrupt bit" "0,1"
newline
bitfld.long 0x1C 4. "MASK_BUSERRINT,DMA channel bus error interrupt mask bit" "0,1"
bitfld.long 0x1C 3. "STATUS_TFRINT,transfer interrupt bit" "0,1"
bitfld.long 0x1C 2. "MASK_TFRINT,transfer interrupt mask bit" "0,1"
bitfld.long 0x1C 1. "STATUS_BLOCKINT,DMA channel block transfer interrupt bit" "0,1"
newline
bitfld.long 0x1C 0. "MASK_BLOCKINT,DMA channel block transfer interrupt mask bit" "0,1"
line.long 0x20 "CRC_CPU_DATA_IN3,Stream Input Register"
hexmask.long 0x20 0.--31. 1. "DATA,Stream input data register"
line.long 0x24 "CRC_INI_VALUE3,CRC Calculation initial value"
hexmask.long 0x24 0.--31. 1. "DATA,CRC calculation initial value"
rgroup.long 0xE8++0x3
line.long 0x0 "CRC_RESULT3,CRC Calculation Result"
hexmask.long 0x0 0.--31. 1. "DATA,CRC calculation result"
group.long 0xEC++0x7
line.long 0x0 "CRC_LEN3,Stream Input length"
hexmask.long 0x0 0.--31. 1. "DATA,crc Stream input data length it should be equal to the CONFIG.len when it's normal work. but in linklist it should be the total length for crc calculation"
line.long 0x4 "NUM_OF_DESCRIPTOR3,the number of descriptor"
hexmask.long 0x4 0.--31. 1. "DATA,the number of descriptor"
group.long 0x100++0x27
line.long 0x0 "SADR4,DMA SOURCE ADDRESS REGISTERS"
hexmask.long 0x0 0.--31. 1. "SRCADDR,SOURCE ADDRESS"
line.long 0x4 "DADR4,DMA DESTINATION ADDRESS REGISTERS"
hexmask.long 0x4 0.--31. 1. "DESTADDR,DESTINATION ADDRESS"
line.long 0x8 "LLI4,DMA CHANNEL LINKED LIST ITEM REGISTERS"
hexmask.long 0x8 4.--31. 1. "LLI,LINKED LIST ITEM ADDRESS"
bitfld.long 0x8 1. "DESC_INT_EN,the interrupt enable for descriptor finish" "0,1"
bitfld.long 0x8 0. "STOP,STOP the channel after transaction is finished" "0,1"
line.long 0xC "CTRL4,DMA CONTROL REGISTERS"
bitfld.long 0xC 29.--31. "PROT,Protection info for AHB master bus" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 28. "SRCADDRINC,Source address increment" "0,1"
bitfld.long 0xC 27. "DESTADDRINC,destination address increment" "0,1"
bitfld.long 0xC 25.--26. "SRCWIDTH,Source peripheral/memory transfer width" "0,1,2,3"
newline
bitfld.long 0xC 23.--24. "DESTWIDTH,Destination peripheral/memory transfer width" "0,1,2,3"
bitfld.long 0xC 20.--22. "SRCBSIZE,Source peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 17.--19. "DESTBSIZE,Destination peripheral/memory transfer burst size" "0,1,2,3,4,5,6,7"
hexmask.long.word 0xC 0.--12. 1. "LEN,Length of the transfer in bytes"
line.long 0x10 "CONFIG4,DMA CONFIGURE REGISTERS"
rbitfld.long 0x10 31. "FIFO_EMPTY,FIFO status of current channel" "0,1"
bitfld.long 0x10 30. "HW_EN,Hardware enable configuration of current channel" "0,1"
bitfld.long 0x10 27.--29. "HW_EN_SRC,hardware enable trigger source" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--25. "DMA_CRC_MODE,crc input data source select" "0,1,2,3"
newline
bitfld.long 0x10 20. "CRC_DATAIN_FORMAT_SEL,CRC input data format select if the dma_crc_mode is not configured to 2'b11 this field can only be confiured to 1" "0,1"
bitfld.long 0x10 16.--18. "CRC_MODE,CRC mode select if this filed is not configured to to 3'b011 the crc_ini_value[31:16]=16'b0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 13.--15. "FLOWCNTL,flow controller and transfer type" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 7.--12. 1. "SRC_PER,peripheral number"
newline
hexmask.long.byte 0x10 1.--6. 1. "DEST_PER,peripheral number"
bitfld.long 0x10 0. "LLE,Link List Enable" "0,1"
line.long 0x14 "CHL_EN4,DMA CHANNEL ENABLE REGISTERS"
bitfld.long 0x14 31. "CHL_EN,Enable/Disable the channel" "0,1"
hexmask.long.byte 0x14 4.--7. 1. "TEST_BUS_SIGNAL_SEL,TEST_BUS_SIGNAL_SEL"
hexmask.long.byte 0x14 0.--3. 1. "CHL_PRIORITY_WEIGHT,DMA Channel Priority Weight"
line.long 0x18 "CHL_STOP4,DMA CHANNEL STOP REGISTERS"
bitfld.long 0x18 31. "CHL_STOP,Stop the running channel" "0,1"
line.long 0x1C "CHNL_INT4,DMA INT REGISTERS"
bitfld.long 0x1C 31. "CRC_INT_STATUS,CRC calculation interrupt status" "0,1"
bitfld.long 0x1C 30. "CRC_INT_MASK,Mask of crc_done interrupt" "0,1"
bitfld.long 0x1C 10. "DESC_STATUS_TFRINT,configurable descriptor transfer interrupt bit" "0,1"
bitfld.long 0x1C 9. "MASK_DESC_TFRINT,descriptor transfer interrupt mask bit" "0,1"
newline
rbitfld.long 0x1C 8. "STATUS_CHLINT,DMA channel interrupt" "0,1"
bitfld.long 0x1C 7. "STATUS_ADDRERRINT,DMA Channel source/destination address alignment error interrupt bit" "0,1"
bitfld.long 0x1C 6. "MASK_ADDRERRINT,DMA Channel source/destination address alignment error interrupt mask bit" "0,1"
bitfld.long 0x1C 5. "STATUS_BUSERRINT,DMA channel bus error interrupt bit" "0,1"
newline
bitfld.long 0x1C 4. "MASK_BUSERRINT,DMA channel bus error interrupt mask bit" "0,1"
bitfld.long 0x1C 3. "STATUS_TFRINT,transfer interrupt bit" "0,1"
bitfld.long 0x1C 2. "MASK_TFRINT,transfer interrupt mask bit" "0,1"
bitfld.long 0x1C 1. "STATUS_BLOCKINT,DMA channel block transfer interrupt bit" "0,1"
newline
bitfld.long 0x1C 0. "MASK_BLOCKINT,DMA channel block transfer interrupt mask bit" "0,1"
line.long 0x20 "CRC_CPU_DATA_IN4,Stream Input Register"
hexmask.long 0x20 0.--31. 1. "DATA,Stream input data register"
line.long 0x24 "CRC_INI_VALUE4,CRC Calculation initial value"
hexmask.long 0x24 0.--31. 1. "DATA,CRC calculation initial value"
rgroup.long 0x128++0x3
line.long 0x0 "CRC_RESULT4,CRC Calculation Result"
hexmask.long 0x0 0.--31. 1. "DATA,CRC calculation result"
group.long 0x12C++0x7
line.long 0x0 "CRC_LEN4,Stream Input length"
hexmask.long 0x0 0.--31. 1. "DATA,crc Stream input data length it should be equal to the CONFIG.len when it's normal work. but in linklist it should be the total length for crc calculation"
line.long 0x4 "NUM_OF_DESCRIPTOR4,the number of descriptor"
hexmask.long 0x4 0.--31. 1. "DATA,the number of descriptor"
tree.end
tree "GPIO (General Purpose I/Os)"
base ad:0x0
tree "GPIO"
base ad:0x40100000
repeat 2. (list 0x0 0x1)(list ad:0x40100000 ad:0x40100020)
tree "BYTE_PIN[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "B_[$1],Byte pin registers for all port GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Port Byte" "0,1"
repeat.end
tree.end
repeat.end
repeat 2. (list 0x0 0x1)(list ad:0x40101000 ad:0x40101080)
tree "WORD_PIN[$1]"
base $2
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "W_[$1],Word pin registers for all port GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,PWORD"
repeat.end
tree.end
repeat.end
base ad:0x40100000
newline
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2000)++0x3
line.long 0x0 "DIR[$1],Port direction"
bitfld.long 0x0 31. "DIRP31,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 30. "DIRP30,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 29. "DIRP29,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 28. "DIRP28,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 27. "DIRP27,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 26. "DIRP26,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 25. "DIRP25,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 24. "DIRP24,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 23. "DIRP23,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 22. "DIRP22,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 21. "DIRP21,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 20. "DIRP20,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 19. "DIRP19,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 18. "DIRP18,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 17. "DIRP17,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 16. "DIRP16,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 15. "DIRP15,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 14. "DIRP14,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 13. "DIRP13,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 12. "DIRP12,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 11. "DIRP11,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 10. "DIRP10,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 9. "DIRP9,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 8. "DIRP8,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 7. "DIRP7,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 6. "DIRP6,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 5. "DIRP5,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 4. "DIRP4,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 3. "DIRP3,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 2. "DIRP2,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 1. "DIRP1,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 0. "DIRP0,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2080)++0x3
line.long 0x0 "MASK[$1],Port mask"
bitfld.long 0x0 31. "MASKP31,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 30. "MASKP30,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 29. "MASKP29,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 28. "MASKP28,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 27. "MASKP27,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 26. "MASKP26,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 25. "MASKP25,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 24. "MASKP24,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 23. "MASKP23,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 22. "MASKP22,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 21. "MASKP21,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 20. "MASKP20,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 19. "MASKP19,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 18. "MASKP18,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 17. "MASKP17,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 16. "MASKP16,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 15. "MASKP15,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 14. "MASKP14,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 13. "MASKP13,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 12. "MASKP12,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 11. "MASKP11,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 10. "MASKP10,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 9. "MASKP9,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 8. "MASKP8,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 7. "MASKP7,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 6. "MASKP6,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 5. "MASKP5,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 4. "MASKP4,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 3. "MASKP3,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 2. "MASKP2,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 1. "MASKP1,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 0. "MASKP0,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "PIN[$1],Port pin"
bitfld.long 0x0 31. "PORT31,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 30. "PORT30,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 29. "PORT29,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 28. "PORT28,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 27. "PORT27,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 26. "PORT26,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 25. "PORT25,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 24. "PORT24,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 23. "PORT23,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 22. "PORT22,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 21. "PORT21,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 20. "PORT20,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 19. "PORT19,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 18. "PORT18,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 17. "PORT17,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 16. "PORT16,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 15. "PORT15,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 14. "PORT14,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 13. "PORT13,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 12. "PORT12,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 11. "PORT11,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 10. "PORT10,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 9. "PORT9,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 8. "PORT8,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 7. "PORT7,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 6. "PORT6,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 5. "PORT5,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 4. "PORT4,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 3. "PORT3,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 2. "PORT2,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 1. "PORT1,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 0. "PORT0,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2180)++0x3
line.long 0x0 "MPIN[$1],Masked Port Pin"
bitfld.long 0x0 31. "MPORTP31,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 30. "MPORTP30,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 29. "MPORTP29,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 28. "MPORTP28,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 27. "MPORTP27,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 26. "MPORTP26,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 25. "MPORTP25,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 24. "MPORTP24,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 23. "MPORTP23,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 22. "MPORTP22,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 21. "MPORTP21,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 20. "MPORTP20,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 19. "MPORTP19,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 18. "MPORTP18,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 17. "MPORTP17,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 16. "MPORTP16,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 15. "MPORTP15,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 14. "MPORTP14,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 13. "MPORTP13,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 12. "MPORTP12,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 11. "MPORTP11,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 10. "MPORTP10,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 9. "MPORTP9,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 8. "MPORTP8,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 7. "MPORTP7,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 6. "MPORTP6,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 5. "MPORTP5,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 4. "MPORTP4,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 3. "MPORTP3,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 2. "MPORTP2,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 1. "MPORTP1,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 0. "MPORTP0,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2200)++0x3
line.long 0x0 "SET[$1],Port set"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2280)++0x3
line.long 0x0 "CLR[$1],Port clear"
eventfld.long 0x0 31. "CLRP31,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 30. "CLRP30,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 29. "CLRP29,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 28. "CLRP28,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 27. "CLRP27,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 26. "CLRP26,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 25. "CLRP25,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 24. "CLRP24,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 23. "CLRP23,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 22. "CLRP22,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 21. "CLRP21,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 20. "CLRP20,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 19. "CLRP19,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 18. "CLRP18,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 17. "CLRP17,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 16. "CLRP16,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 15. "CLRP15,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 14. "CLRP14,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 13. "CLRP13,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 12. "CLRP12,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 11. "CLRP11,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 10. "CLRP10,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 9. "CLRP9,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 8. "CLRP8,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 7. "CLRP7,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 6. "CLRP6,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 5. "CLRP5,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 4. "CLRP4,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 3. "CLRP3,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 2. "CLRP2,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 1. "CLRP1,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 0. "CLRP0,Clear output bits" "0: No operation,1: Clears output bit"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2300)++0x3
line.long 0x0 "NOT[$1],Port toggle"
bitfld.long 0x0 31. "NOTP31,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 30. "NOTP30,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 29. "NOTP29,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 28. "NOTP28,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 27. "NOTP27,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 26. "NOTP26,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 25. "NOTP25,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 24. "NOTP24,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 23. "NOTP23,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 22. "NOTP22,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 21. "NOTP21,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 20. "NOTP20,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 19. "NOTP19,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 18. "NOTP18,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 17. "NOTP17,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 16. "NOTP16,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 15. "NOTP15,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 14. "NOTP14,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 13. "NOTP13,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 12. "NOTP12,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 11. "NOTP11,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 10. "NOTP10,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 9. "NOTP9,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 8. "NOTP8,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 7. "NOTP7,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 6. "NOTP6,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 5. "NOTP5,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 4. "NOTP4,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 3. "NOTP3,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 2. "NOTP2,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 1. "NOTP1,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 0. "NOTP0,Toggle output bits" "0: No operation,1: Toggle output bit"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2380)++0x3
line.long 0x0 "DIRSET[$1],Port direction set"
bitfld.long 0x0 31. "DIRSETP31,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 30. "DIRSETP30,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 29. "DIRSETP29,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 28. "DIRSETP28,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 27. "DIRSETP27,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 26. "DIRSETP26,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 25. "DIRSETP25,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 24. "DIRSETP24,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 23. "DIRSETP23,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 22. "DIRSETP22,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 21. "DIRSETP21,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 20. "DIRSETP20,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 19. "DIRSETP19,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 18. "DIRSETP18,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 17. "DIRSETP17,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 16. "DIRSETP16,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 15. "DIRSETP15,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 14. "DIRSETP14,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 13. "DIRSETP13,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 12. "DIRSETP12,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 11. "DIRSETP11,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 10. "DIRSETP10,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 9. "DIRSETP9,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 8. "DIRSETP8,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 7. "DIRSETP7,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 6. "DIRSETP6,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 5. "DIRSETP5,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 4. "DIRSETP4,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 3. "DIRSETP3,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 2. "DIRSETP2,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 1. "DIRSETP1,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 0. "DIRSETP0,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2400)++0x3
line.long 0x0 "DIRCLR[$1],Port direction clear"
eventfld.long 0x0 31. "DIRCLRP31,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 30. "DIRCLRP30,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 29. "DIRCLRP29,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 28. "DIRCLRP28,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 27. "DIRCLRP27,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 26. "DIRCLRP26,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 25. "DIRCLRP25,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 24. "DIRCLRP24,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 23. "DIRCLRP23,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 22. "DIRCLRP22,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 21. "DIRCLRP21,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 20. "DIRCLRP20,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 19. "DIRCLRP19,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 18. "DIRCLRP18,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 17. "DIRCLRP17,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 16. "DIRCLRP16,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 15. "DIRCLRP15,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 14. "DIRCLRP14,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 13. "DIRCLRP13,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 12. "DIRCLRP12,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 11. "DIRCLRP11,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 10. "DIRCLRP10,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 9. "DIRCLRP9,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 8. "DIRCLRP8,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 7. "DIRCLRP7,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 6. "DIRCLRP6,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 5. "DIRCLRP5,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 4. "DIRCLRP4,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 3. "DIRCLRP3,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 2. "DIRCLRP2,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 1. "DIRCLRP1,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 0. "DIRCLRP0,Clear direction bits." "0: No operation,1: Clears direction bits"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
wgroup.long ($2+0x2480)++0x3
line.long 0x0 "DIRNOT[$1],Port direction toggle"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2500)++0x3
line.long 0x0 "INTENA[$1],Interrupt A enable control"
bitfld.long 0x0 31. "INT_EN31,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 30. "INT_EN30,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 29. "INT_EN29,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 28. "INT_EN28,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 27. "INT_EN27,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 26. "INT_EN26,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 25. "INT_EN25,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 24. "INT_EN24,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 23. "INT_EN23,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 22. "INT_EN22,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 21. "INT_EN21,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 20. "INT_EN20,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 19. "INT_EN19,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 18. "INT_EN18,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 17. "INT_EN17,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 16. "INT_EN16,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 15. "INT_EN15,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 14. "INT_EN14,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 13. "INT_EN13,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 12. "INT_EN12,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 11. "INT_EN11,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 10. "INT_EN10,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 9. "INT_EN9,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 8. "INT_EN8,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 7. "INT_EN7,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 6. "INT_EN6,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 5. "INT_EN5,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 4. "INT_EN4,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 3. "INT_EN3,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 2. "INT_EN2,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 1. "INT_EN1,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 0. "INT_EN0,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2580)++0x3
line.long 0x0 "INTENB[$1],Interrupt B enable control"
bitfld.long 0x0 31. "INT_EN31,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 30. "INT_EN30,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 29. "INT_EN29,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 28. "INT_EN28,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 27. "INT_EN27,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 26. "INT_EN26,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 25. "INT_EN25,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 24. "INT_EN24,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 23. "INT_EN23,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 22. "INT_EN22,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 21. "INT_EN21,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 20. "INT_EN20,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 19. "INT_EN19,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 18. "INT_EN18,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 17. "INT_EN17,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 16. "INT_EN16,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 15. "INT_EN15,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 14. "INT_EN14,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 13. "INT_EN13,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 12. "INT_EN12,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 11. "INT_EN11,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 10. "INT_EN10,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 9. "INT_EN9,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 8. "INT_EN8,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 7. "INT_EN7,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 6. "INT_EN6,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 5. "INT_EN5,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 4. "INT_EN4,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 3. "INT_EN3,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 2. "INT_EN2,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 1. "INT_EN1,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 0. "INT_EN0,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2600)++0x3
line.long 0x0 "INTPOL[$1],Interupt polarity control"
bitfld.long 0x0 31. "POL_CTL31,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 30. "POL_CTL30,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 29. "POL_CTL29,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 28. "POL_CTL28,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 27. "POL_CTL27,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 26. "POL_CTL26,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 25. "POL_CTL25,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 24. "POL_CTL24,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 23. "POL_CTL23,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 22. "POL_CTL22,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 21. "POL_CTL21,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 20. "POL_CTL20,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 19. "POL_CTL19,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 18. "POL_CTL18,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 17. "POL_CTL17,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 16. "POL_CTL16,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 15. "POL_CTL15,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 14. "POL_CTL14,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 13. "POL_CTL13,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 12. "POL_CTL12,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 11. "POL_CTL11,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 10. "POL_CTL10,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 9. "POL_CTL9,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 8. "POL_CTL8,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 7. "POL_CTL7,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 6. "POL_CTL6,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 5. "POL_CTL5,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 4. "POL_CTL4,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 3. "POL_CTL3,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 2. "POL_CTL2,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 1. "POL_CTL1,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 0. "POL_CTL0,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2680)++0x3
line.long 0x0 "INTEDG[$1],Interrupt edge select"
bitfld.long 0x0 31. "EDGE31,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 30. "EDGE30,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 29. "EDGE29,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 28. "EDGE28,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 27. "EDGE27,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 26. "EDGE26,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 25. "EDGE25,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 24. "EDGE24,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 23. "EDGE23,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 22. "EDGE22,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 21. "EDGE21,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 20. "EDGE20,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 19. "EDGE19,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 18. "EDGE18,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 17. "EDGE17,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 16. "EDGE16,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 15. "EDGE15,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 14. "EDGE14,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 13. "EDGE13,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 12. "EDGE12,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 11. "EDGE11,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 10. "EDGE10,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 9. "EDGE9,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 8. "EDGE8,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 7. "EDGE7,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 6. "EDGE6,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 5. "EDGE5,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 4. "EDGE4,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 3. "EDGE3,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 2. "EDGE2,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 1. "EDGE1,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 0. "EDGE0,Edge or level mode select bits." "0: Level mode,1: Edge mode"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2700)++0x3
line.long 0x0 "INTSTATA[$1],Interrupt status for interrupt A"
hexmask.long 0x0 0.--31. 1. "STATUS,Interrupt status."
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2780)++0x3
line.long 0x0 "INTSTATB[$1],Interrupt status for interrupt B"
hexmask.long 0x0 0.--31. 1. "STATUS,Interrupt status"
repeat.end
tree.end
tree "SECGPIO"
base ad:0x40154000
group.byte 0x0++0x1F
line.byte 0x0 "B0_0,Byte pin registers for all port GPIO pins"
bitfld.byte 0x0 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1 "B0_1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1 0. "PBYTE,Port Byte" "0,1"
line.byte 0x2 "B0_2,Byte pin registers for all port GPIO pins"
bitfld.byte 0x2 0. "PBYTE,Port Byte" "0,1"
line.byte 0x3 "B0_3,Byte pin registers for all port GPIO pins"
bitfld.byte 0x3 0. "PBYTE,Port Byte" "0,1"
line.byte 0x4 "B0_4,Byte pin registers for all port GPIO pins"
bitfld.byte 0x4 0. "PBYTE,Port Byte" "0,1"
line.byte 0x5 "B0_5,Byte pin registers for all port GPIO pins"
bitfld.byte 0x5 0. "PBYTE,Port Byte" "0,1"
line.byte 0x6 "B0_6,Byte pin registers for all port GPIO pins"
bitfld.byte 0x6 0. "PBYTE,Port Byte" "0,1"
line.byte 0x7 "B0_7,Byte pin registers for all port GPIO pins"
bitfld.byte 0x7 0. "PBYTE,Port Byte" "0,1"
line.byte 0x8 "B0_8,Byte pin registers for all port GPIO pins"
bitfld.byte 0x8 0. "PBYTE,Port Byte" "0,1"
line.byte 0x9 "B0_9,Byte pin registers for all port GPIO pins"
bitfld.byte 0x9 0. "PBYTE,Port Byte" "0,1"
line.byte 0xA "B0_10,Byte pin registers for all port GPIO pins"
bitfld.byte 0xA 0. "PBYTE,Port Byte" "0,1"
line.byte 0xB "B0_11,Byte pin registers for all port GPIO pins"
bitfld.byte 0xB 0. "PBYTE,Port Byte" "0,1"
line.byte 0xC "B0_12,Byte pin registers for all port GPIO pins"
bitfld.byte 0xC 0. "PBYTE,Port Byte" "0,1"
line.byte 0xD "B0_13,Byte pin registers for all port GPIO pins"
bitfld.byte 0xD 0. "PBYTE,Port Byte" "0,1"
line.byte 0xE "B0_14,Byte pin registers for all port GPIO pins"
bitfld.byte 0xE 0. "PBYTE,Port Byte" "0,1"
line.byte 0xF "B0_15,Byte pin registers for all port GPIO pins"
bitfld.byte 0xF 0. "PBYTE,Port Byte" "0,1"
line.byte 0x10 "B0_16,Byte pin registers for all port GPIO pins"
bitfld.byte 0x10 0. "PBYTE,Port Byte" "0,1"
line.byte 0x11 "B0_17,Byte pin registers for all port GPIO pins"
bitfld.byte 0x11 0. "PBYTE,Port Byte" "0,1"
line.byte 0x12 "B0_18,Byte pin registers for all port GPIO pins"
bitfld.byte 0x12 0. "PBYTE,Port Byte" "0,1"
line.byte 0x13 "B0_19,Byte pin registers for all port GPIO pins"
bitfld.byte 0x13 0. "PBYTE,Port Byte" "0,1"
line.byte 0x14 "B0_20,Byte pin registers for all port GPIO pins"
bitfld.byte 0x14 0. "PBYTE,Port Byte" "0,1"
line.byte 0x15 "B0_21,Byte pin registers for all port GPIO pins"
bitfld.byte 0x15 0. "PBYTE,Port Byte" "0,1"
line.byte 0x16 "B0_22,Byte pin registers for all port GPIO pins"
bitfld.byte 0x16 0. "PBYTE,Port Byte" "0,1"
line.byte 0x17 "B0_23,Byte pin registers for all port GPIO pins"
bitfld.byte 0x17 0. "PBYTE,Port Byte" "0,1"
line.byte 0x18 "B0_24,Byte pin registers for all port GPIO pins"
bitfld.byte 0x18 0. "PBYTE,Port Byte" "0,1"
line.byte 0x19 "B0_25,Byte pin registers for all port GPIO pins"
bitfld.byte 0x19 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1A "B0_26,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1A 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1B "B0_27,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1B 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1C "B0_28,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1C 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1D "B0_29,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1D 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1E "B0_30,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1E 0. "PBYTE,Port Byte" "0,1"
line.byte 0x1F "B0_31,Byte pin registers for all port GPIO pins"
bitfld.byte 0x1F 0. "PBYTE,Port Byte" "0,1"
group.long 0x1000++0x7F
line.long 0x0 "W0_0,Word pin registers for all port GPIO pins"
hexmask.long 0x0 0.--31. 1. "PWORD,PWORD"
line.long 0x4 "W0_1,Word pin registers for all port GPIO pins"
hexmask.long 0x4 0.--31. 1. "PWORD,PWORD"
line.long 0x8 "W0_2,Word pin registers for all port GPIO pins"
hexmask.long 0x8 0.--31. 1. "PWORD,PWORD"
line.long 0xC "W0_3,Word pin registers for all port GPIO pins"
hexmask.long 0xC 0.--31. 1. "PWORD,PWORD"
line.long 0x10 "W0_4,Word pin registers for all port GPIO pins"
hexmask.long 0x10 0.--31. 1. "PWORD,PWORD"
line.long 0x14 "W0_5,Word pin registers for all port GPIO pins"
hexmask.long 0x14 0.--31. 1. "PWORD,PWORD"
line.long 0x18 "W0_6,Word pin registers for all port GPIO pins"
hexmask.long 0x18 0.--31. 1. "PWORD,PWORD"
line.long 0x1C "W0_7,Word pin registers for all port GPIO pins"
hexmask.long 0x1C 0.--31. 1. "PWORD,PWORD"
line.long 0x20 "W0_8,Word pin registers for all port GPIO pins"
hexmask.long 0x20 0.--31. 1. "PWORD,PWORD"
line.long 0x24 "W0_9,Word pin registers for all port GPIO pins"
hexmask.long 0x24 0.--31. 1. "PWORD,PWORD"
line.long 0x28 "W0_10,Word pin registers for all port GPIO pins"
hexmask.long 0x28 0.--31. 1. "PWORD,PWORD"
line.long 0x2C "W0_11,Word pin registers for all port GPIO pins"
hexmask.long 0x2C 0.--31. 1. "PWORD,PWORD"
line.long 0x30 "W0_12,Word pin registers for all port GPIO pins"
hexmask.long 0x30 0.--31. 1. "PWORD,PWORD"
line.long 0x34 "W0_13,Word pin registers for all port GPIO pins"
hexmask.long 0x34 0.--31. 1. "PWORD,PWORD"
line.long 0x38 "W0_14,Word pin registers for all port GPIO pins"
hexmask.long 0x38 0.--31. 1. "PWORD,PWORD"
line.long 0x3C "W0_15,Word pin registers for all port GPIO pins"
hexmask.long 0x3C 0.--31. 1. "PWORD,PWORD"
line.long 0x40 "W0_16,Word pin registers for all port GPIO pins"
hexmask.long 0x40 0.--31. 1. "PWORD,PWORD"
line.long 0x44 "W0_17,Word pin registers for all port GPIO pins"
hexmask.long 0x44 0.--31. 1. "PWORD,PWORD"
line.long 0x48 "W0_18,Word pin registers for all port GPIO pins"
hexmask.long 0x48 0.--31. 1. "PWORD,PWORD"
line.long 0x4C "W0_19,Word pin registers for all port GPIO pins"
hexmask.long 0x4C 0.--31. 1. "PWORD,PWORD"
line.long 0x50 "W0_20,Word pin registers for all port GPIO pins"
hexmask.long 0x50 0.--31. 1. "PWORD,PWORD"
line.long 0x54 "W0_21,Word pin registers for all port GPIO pins"
hexmask.long 0x54 0.--31. 1. "PWORD,PWORD"
line.long 0x58 "W0_22,Word pin registers for all port GPIO pins"
hexmask.long 0x58 0.--31. 1. "PWORD,PWORD"
line.long 0x5C "W0_23,Word pin registers for all port GPIO pins"
hexmask.long 0x5C 0.--31. 1. "PWORD,PWORD"
line.long 0x60 "W0_24,Word pin registers for all port GPIO pins"
hexmask.long 0x60 0.--31. 1. "PWORD,PWORD"
line.long 0x64 "W0_25,Word pin registers for all port GPIO pins"
hexmask.long 0x64 0.--31. 1. "PWORD,PWORD"
line.long 0x68 "W0_26,Word pin registers for all port GPIO pins"
hexmask.long 0x68 0.--31. 1. "PWORD,PWORD"
line.long 0x6C "W0_27,Word pin registers for all port GPIO pins"
hexmask.long 0x6C 0.--31. 1. "PWORD,PWORD"
line.long 0x70 "W0_28,Word pin registers for all port GPIO pins"
hexmask.long 0x70 0.--31. 1. "PWORD,PWORD"
line.long 0x74 "W0_29,Word pin registers for all port GPIO pins"
hexmask.long 0x74 0.--31. 1. "PWORD,PWORD"
line.long 0x78 "W0_30,Word pin registers for all port GPIO pins"
hexmask.long 0x78 0.--31. 1. "PWORD,PWORD"
line.long 0x7C "W0_31,Word pin registers for all port GPIO pins"
hexmask.long 0x7C 0.--31. 1. "PWORD,PWORD"
wgroup.long 0x2000++0x3
line.long 0x0 "DIR0,Port direction"
bitfld.long 0x0 31. "DIRP31,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 30. "DIRP30,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 29. "DIRP29,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 28. "DIRP28,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 27. "DIRP27,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 26. "DIRP26,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 25. "DIRP25,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 24. "DIRP24,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 23. "DIRP23,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 22. "DIRP22,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 21. "DIRP21,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 20. "DIRP20,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 19. "DIRP19,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 18. "DIRP18,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 17. "DIRP17,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 16. "DIRP16,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 15. "DIRP15,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 14. "DIRP14,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 13. "DIRP13,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 12. "DIRP12,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 11. "DIRP11,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 10. "DIRP10,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 9. "DIRP9,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 8. "DIRP8,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 7. "DIRP7,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 6. "DIRP6,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 5. "DIRP5,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 4. "DIRP4,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 3. "DIRP3,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 2. "DIRP2,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
newline
bitfld.long 0x0 1. "DIRP1,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
bitfld.long 0x0 0. "DIRP0,Selects pin direction for pin PIOa_b." "0: Input,1: Output"
group.long 0x2080++0x3
line.long 0x0 "MASK0,Port mask"
bitfld.long 0x0 31. "MASKP31,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 30. "MASKP30,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 29. "MASKP29,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 28. "MASKP28,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 27. "MASKP27,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 26. "MASKP26,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 25. "MASKP25,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 24. "MASKP24,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 23. "MASKP23,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 22. "MASKP22,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 21. "MASKP21,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 20. "MASKP20,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 19. "MASKP19,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 18. "MASKP18,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 17. "MASKP17,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 16. "MASKP16,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 15. "MASKP15,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 14. "MASKP14,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 13. "MASKP13,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 12. "MASKP12,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 11. "MASKP11,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 10. "MASKP10,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 9. "MASKP9,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 8. "MASKP8,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 7. "MASKP7,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 6. "MASKP6,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 5. "MASKP5,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 4. "MASKP4,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 3. "MASKP3,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 2. "MASKP2,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
newline
bitfld.long 0x0 1. "MASKP1,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
bitfld.long 0x0 0. "MASKP0,Port Mask" "0: Read MPIN: pin state; write MPIN: load output bit,1: Read MPIN: 0; write MPIN: output bit not affected"
group.long 0x2100++0x3
line.long 0x0 "PIN0,Port pin"
bitfld.long 0x0 31. "PORT31,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 30. "PORT30,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 29. "PORT29,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 28. "PORT28,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 27. "PORT27,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 26. "PORT26,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 25. "PORT25,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 24. "PORT24,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 23. "PORT23,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 22. "PORT22,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 21. "PORT21,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 20. "PORT20,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 19. "PORT19,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 18. "PORT18,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 17. "PORT17,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 16. "PORT16,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 15. "PORT15,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 14. "PORT14,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 13. "PORT13,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 12. "PORT12,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 11. "PORT11,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 10. "PORT10,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 9. "PORT9,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 8. "PORT8,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 7. "PORT7,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 6. "PORT6,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 5. "PORT5,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 4. "PORT4,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 3. "PORT3,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 2. "PORT2,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
newline
bitfld.long 0x0 1. "PORT1,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
bitfld.long 0x0 0. "PORT0,Port pins" "0: Read- pin is low; Write- clear output bit,1: Read- pin is high; Write- set output bit"
group.long 0x2180++0x3
line.long 0x0 "MPIN0,Masked Port Pin"
bitfld.long 0x0 31. "MPORTP31,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 30. "MPORTP30,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 29. "MPORTP29,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 28. "MPORTP28,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 27. "MPORTP27,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 26. "MPORTP26,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 25. "MPORTP25,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 24. "MPORTP24,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 23. "MPORTP23,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 22. "MPORTP22,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 21. "MPORTP21,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 20. "MPORTP20,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 19. "MPORTP19,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 18. "MPORTP18,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 17. "MPORTP17,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 16. "MPORTP16,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 15. "MPORTP15,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 14. "MPORTP14,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 13. "MPORTP13,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 12. "MPORTP12,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 11. "MPORTP11,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 10. "MPORTP10,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 9. "MPORTP9,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 8. "MPORTP8,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 7. "MPORTP7,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 6. "MPORTP6,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 5. "MPORTP5,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 4. "MPORTP4,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 3. "MPORTP3,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 2. "MPORTP2,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
newline
bitfld.long 0x0 1. "MPORTP1,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
bitfld.long 0x0 0. "MPORTP0,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit in..,1: Read- pin is HIGH and the corresponding bit in.."
group.long 0x2200++0x3
line.long 0x0 "SET0,Port set"
hexmask.long 0x0 0.--31. 1. "SETP,Read or set output bits"
group.long 0x2280++0x3
line.long 0x0 "CLR0,Port clear"
eventfld.long 0x0 31. "CLRP31,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 30. "CLRP30,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 29. "CLRP29,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 28. "CLRP28,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 27. "CLRP27,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 26. "CLRP26,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 25. "CLRP25,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 24. "CLRP24,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 23. "CLRP23,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 22. "CLRP22,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 21. "CLRP21,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 20. "CLRP20,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 19. "CLRP19,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 18. "CLRP18,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 17. "CLRP17,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 16. "CLRP16,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 15. "CLRP15,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 14. "CLRP14,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 13. "CLRP13,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 12. "CLRP12,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 11. "CLRP11,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 10. "CLRP10,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 9. "CLRP9,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 8. "CLRP8,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 7. "CLRP7,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 6. "CLRP6,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 5. "CLRP5,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 4. "CLRP4,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 3. "CLRP3,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 2. "CLRP2,Clear output bits" "0: No operation,1: Clears output bit"
newline
eventfld.long 0x0 1. "CLRP1,Clear output bits" "0: No operation,1: Clears output bit"
eventfld.long 0x0 0. "CLRP0,Clear output bits" "0: No operation,1: Clears output bit"
wgroup.long 0x2300++0x3
line.long 0x0 "NOT0,Port toggle"
bitfld.long 0x0 31. "NOTP31,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 30. "NOTP30,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 29. "NOTP29,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 28. "NOTP28,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 27. "NOTP27,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 26. "NOTP26,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 25. "NOTP25,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 24. "NOTP24,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 23. "NOTP23,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 22. "NOTP22,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 21. "NOTP21,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 20. "NOTP20,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 19. "NOTP19,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 18. "NOTP18,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 17. "NOTP17,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 16. "NOTP16,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 15. "NOTP15,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 14. "NOTP14,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 13. "NOTP13,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 12. "NOTP12,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 11. "NOTP11,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 10. "NOTP10,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 9. "NOTP9,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 8. "NOTP8,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 7. "NOTP7,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 6. "NOTP6,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 5. "NOTP5,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 4. "NOTP4,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 3. "NOTP3,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 2. "NOTP2,Toggle output bits" "0: No operation,1: Toggle output bit"
newline
bitfld.long 0x0 1. "NOTP1,Toggle output bits" "0: No operation,1: Toggle output bit"
bitfld.long 0x0 0. "NOTP0,Toggle output bits" "0: No operation,1: Toggle output bit"
wgroup.long 0x2380++0x3
line.long 0x0 "DIRSET0,Port direction set"
bitfld.long 0x0 31. "DIRSETP31,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 30. "DIRSETP30,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 29. "DIRSETP29,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 28. "DIRSETP28,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 27. "DIRSETP27,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 26. "DIRSETP26,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 25. "DIRSETP25,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 24. "DIRSETP24,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 23. "DIRSETP23,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 22. "DIRSETP22,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 21. "DIRSETP21,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 20. "DIRSETP20,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 19. "DIRSETP19,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 18. "DIRSETP18,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 17. "DIRSETP17,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 16. "DIRSETP16,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 15. "DIRSETP15,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 14. "DIRSETP14,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 13. "DIRSETP13,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 12. "DIRSETP12,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 11. "DIRSETP11,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 10. "DIRSETP10,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 9. "DIRSETP9,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 8. "DIRSETP8,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 7. "DIRSETP7,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 6. "DIRSETP6,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 5. "DIRSETP5,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 4. "DIRSETP4,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 3. "DIRSETP3,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 2. "DIRSETP2,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
newline
bitfld.long 0x0 1. "DIRSETP1,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
bitfld.long 0x0 0. "DIRSETP0,Direction set bits for Port pins" "0: No operation,1: Sets direction bit"
group.long 0x2400++0x3
line.long 0x0 "DIRCLR0,Port direction clear"
eventfld.long 0x0 31. "DIRCLRP31,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 30. "DIRCLRP30,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 29. "DIRCLRP29,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 28. "DIRCLRP28,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 27. "DIRCLRP27,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 26. "DIRCLRP26,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 25. "DIRCLRP25,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 24. "DIRCLRP24,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 23. "DIRCLRP23,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 22. "DIRCLRP22,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 21. "DIRCLRP21,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 20. "DIRCLRP20,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 19. "DIRCLRP19,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 18. "DIRCLRP18,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 17. "DIRCLRP17,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 16. "DIRCLRP16,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 15. "DIRCLRP15,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 14. "DIRCLRP14,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 13. "DIRCLRP13,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 12. "DIRCLRP12,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 11. "DIRCLRP11,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 10. "DIRCLRP10,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 9. "DIRCLRP9,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 8. "DIRCLRP8,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 7. "DIRCLRP7,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 6. "DIRCLRP6,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 5. "DIRCLRP5,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 4. "DIRCLRP4,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 3. "DIRCLRP3,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 2. "DIRCLRP2,Clear direction bits." "0: No operation,1: Clears direction bits"
newline
eventfld.long 0x0 1. "DIRCLRP1,Clear direction bits." "0: No operation,1: Clears direction bits"
eventfld.long 0x0 0. "DIRCLRP0,Clear direction bits." "0: No operation,1: Clears direction bits"
wgroup.long 0x2480++0x3
line.long 0x0 "DIRNOT0,Port direction toggle"
hexmask.long 0x0 0.--28. 1. "DIRNOTP,Toggle direction bits."
group.long 0x2500++0x3
line.long 0x0 "INTENA0,Interrupt A enable control"
bitfld.long 0x0 31. "INT_EN31,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 30. "INT_EN30,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 29. "INT_EN29,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 28. "INT_EN28,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 27. "INT_EN27,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 26. "INT_EN26,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 25. "INT_EN25,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 24. "INT_EN24,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 23. "INT_EN23,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 22. "INT_EN22,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 21. "INT_EN21,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 20. "INT_EN20,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 19. "INT_EN19,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 18. "INT_EN18,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 17. "INT_EN17,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 16. "INT_EN16,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 15. "INT_EN15,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 14. "INT_EN14,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 13. "INT_EN13,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 12. "INT_EN12,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 11. "INT_EN11,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 10. "INT_EN10,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 9. "INT_EN9,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 8. "INT_EN8,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 7. "INT_EN7,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 6. "INT_EN6,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 5. "INT_EN5,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 4. "INT_EN4,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 3. "INT_EN3,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 2. "INT_EN2,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
newline
bitfld.long 0x0 1. "INT_EN1,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
bitfld.long 0x0 0. "INT_EN0,Interrupt A enable bits." "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A"
group.long 0x2580++0x3
line.long 0x0 "INTENB0,Interrupt B enable control"
bitfld.long 0x0 31. "INT_EN31,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 30. "INT_EN30,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 29. "INT_EN29,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 28. "INT_EN28,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 27. "INT_EN27,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 26. "INT_EN26,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 25. "INT_EN25,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 24. "INT_EN24,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 23. "INT_EN23,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 22. "INT_EN22,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 21. "INT_EN21,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 20. "INT_EN20,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 19. "INT_EN19,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 18. "INT_EN18,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 17. "INT_EN17,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 16. "INT_EN16,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 15. "INT_EN15,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 14. "INT_EN14,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 13. "INT_EN13,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 12. "INT_EN12,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 11. "INT_EN11,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 10. "INT_EN10,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 9. "INT_EN9,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 8. "INT_EN8,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 7. "INT_EN7,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 6. "INT_EN6,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 5. "INT_EN5,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 4. "INT_EN4,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 3. "INT_EN3,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 2. "INT_EN2,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
newline
bitfld.long 0x0 1. "INT_EN1,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
bitfld.long 0x0 0. "INT_EN0,Interrupt B enable bits." "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B"
group.long 0x2600++0x3
line.long 0x0 "INTPOL0,Interupt polarity control"
bitfld.long 0x0 31. "POL_CTL31,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 30. "POL_CTL30,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 29. "POL_CTL29,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 28. "POL_CTL28,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 27. "POL_CTL27,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 26. "POL_CTL26,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 25. "POL_CTL25,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 24. "POL_CTL24,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 23. "POL_CTL23,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 22. "POL_CTL22,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 21. "POL_CTL21,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 20. "POL_CTL20,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 19. "POL_CTL19,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 18. "POL_CTL18,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 17. "POL_CTL17,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 16. "POL_CTL16,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 15. "POL_CTL15,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 14. "POL_CTL14,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 13. "POL_CTL13,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 12. "POL_CTL12,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 11. "POL_CTL11,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 10. "POL_CTL10,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 9. "POL_CTL9,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 8. "POL_CTL8,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 7. "POL_CTL7,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 6. "POL_CTL6,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 5. "POL_CTL5,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 4. "POL_CTL4,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 3. "POL_CTL3,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 2. "POL_CTL2,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
newline
bitfld.long 0x0 1. "POL_CTL1,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
bitfld.long 0x0 0. "POL_CTL0,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered"
group.long 0x2680++0x3
line.long 0x0 "INTEDG0,Interrupt edge select"
bitfld.long 0x0 31. "EDGE31,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 30. "EDGE30,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 29. "EDGE29,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 28. "EDGE28,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 27. "EDGE27,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 26. "EDGE26,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 25. "EDGE25,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 24. "EDGE24,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 23. "EDGE23,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 22. "EDGE22,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 21. "EDGE21,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 20. "EDGE20,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 19. "EDGE19,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 18. "EDGE18,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 17. "EDGE17,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 16. "EDGE16,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 15. "EDGE15,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 14. "EDGE14,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 13. "EDGE13,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 12. "EDGE12,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 11. "EDGE11,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 10. "EDGE10,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 9. "EDGE9,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 8. "EDGE8,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 7. "EDGE7,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 6. "EDGE6,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 5. "EDGE5,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 4. "EDGE4,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 3. "EDGE3,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 2. "EDGE2,Edge or level mode select bits." "0: Level mode,1: Edge mode"
newline
bitfld.long 0x0 1. "EDGE1,Edge or level mode select bits." "0: Level mode,1: Edge mode"
bitfld.long 0x0 0. "EDGE0,Edge or level mode select bits." "0: Level mode,1: Edge mode"
group.long 0x2700++0x3
line.long 0x0 "INTSTATA0,Interrupt status for interrupt A"
hexmask.long 0x0 0.--31. 1. "STATUS,Interrupt status."
group.long 0x2780++0x3
line.long 0x0 "INTSTATB0,Interrupt status for interrupt B"
hexmask.long 0x0 0.--31. 1. "STATUS,Interrupt status"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
tree "I2C0"
base ad:0x40106000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable"
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled. The time-out function is disabled.,1: Enabled. The time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable" "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable" "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable" "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status Register"
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag" "0: Not idle. The I2C bus is not idle or MONIDLE..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag" "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag" "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred. An.."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready" "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag" "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State" "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (in..,2: Slave transmit. Data can be transmitted (in..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending" "0: In progress. The Slave function does not..,1: Pending. The Slave function needs software.."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code" "0: Idle. The Master function is available to be..,1: Receive ready. Received data is available (in..,2: Transmit ready. Data can be transmitted (in..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending" "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set Register"
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out Register"
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value"
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value the bottom 4 bits"
line.long 0x4 "CLKDIV,Clock Divider Register"
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Divider Value"
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: Not active,1: Active"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag" "0: Not active,1: Active"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready" "0: Not active,1: Active"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status" "0: Not active,1: Active"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending" "0: Not active,1: Active"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: Not active,1: Active"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending" "0: Not active,1: Active"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master Control Register"
bitfld.long 0x0 3. "MSTDMA,Master DMA enable" "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control(write-only)" "0: No effect,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control(write-only)" "0: No effect,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue(write-only)" "0: No effect,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master Timing Register"
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks. Minimum SCL high time is 2 clocks of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clocks of..,3: 5 clocks. Minimum SCL high time is 5 clocks of..,4: 6 clocks. Minimum SCL high time is 6 clocks of..,5: 7 clocks. Minimum SCL high time is 7 clocks of..,6: 8 clocks. Minimum SCL high time is 8 clocks of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Master Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x1B
line.long 0x0 "SLVCTL,Slave Control Register"
bitfld.long 0x0 9. "AUTOMATCHREAD,Automatic Match Read" "0: In Automatic Mode the expected next operation is..,1: In Automatic Mode the expected next operation is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable" "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK" "0: No effect,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue" "0: No effect,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Slave Data Register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register"
line.long 0x8 "SLVADR0,Slave Address Register"
bitfld.long 0x8 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x8 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0x8 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0xC "SLVADR1,Slave Address Register"
bitfld.long 0xC 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0xC 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0xC 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x10 "SLVADR2,Slave Address Register"
bitfld.long 0x10 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x10 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0x10 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x14 "SLVADR3,Slave Address Register"
bitfld.long 0x14 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x14 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0x14 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x18 "SLVQUAL0,Slave Qualification for Address 0 Register"
hexmask.long.byte 0x18 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x18 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor Receiver Data Register"
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK" "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start" "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2C1"
base ad:0x40107000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable"
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
newline
bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled. The time-out function is disabled.,1: Enabled. The time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable" "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
newline
bitfld.long 0x0 1. "SLVEN,Slave Enable" "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable" "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status Register"
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag" "0: Not idle. The I2C bus is not idle or MONIDLE..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag" "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag" "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred. An.."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready" "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
newline
bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag" "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
newline
rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State" "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (in..,2: Slave transmit. Data can be transmitted (in..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending" "0: In progress. The Slave function does not..,1: Pending. The Slave function needs software.."
newline
bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code" "0: Idle. The Master function is available to be..,1: Receive ready. Received data is available (in..,2: Transmit ready. Data can be transmitted (in..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending" "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set Register"
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
newline
bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out Register"
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value"
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value the bottom 4 bits"
line.long 0x4 "CLKDIV,Clock Divider Register"
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Divider Value"
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: Not active,1: Active"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag" "0: Not active,1: Active"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready" "0: Not active,1: Active"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status" "0: Not active,1: Active"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending" "0: Not active,1: Active"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: Not active,1: Active"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending" "0: Not active,1: Active"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master Control Register"
bitfld.long 0x0 3. "MSTDMA,Master DMA enable" "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control(write-only)" "0: No effect,1: Stop. A Stop will be generated on the I2C bus at.."
newline
bitfld.long 0x0 1. "MSTSTART,Master Start control(write-only)" "0: No effect,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue(write-only)" "0: No effect,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master Timing Register"
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks. Minimum SCL high time is 2 clocks of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clocks of..,3: 5 clocks. Minimum SCL high time is 5 clocks of..,4: 6 clocks. Minimum SCL high time is 6 clocks of..,5: 7 clocks. Minimum SCL high time is 7 clocks of..,6: 8 clocks. Minimum SCL high time is 8 clocks of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Master Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x1B
line.long 0x0 "SLVCTL,Slave Control Register"
bitfld.long 0x0 9. "AUTOMATCHREAD,Automatic Match Read" "0: In Automatic Mode the expected next operation is..,1: In Automatic Mode the expected next operation is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x0 3. "SLVDMA,Slave DMA enable" "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK" "0: No effect,1: NACK. Causes the Slave function to NACK the.."
newline
bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue" "0: No effect,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Slave Data Register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register"
line.long 0x8 "SLVADR0,Slave Address Register"
bitfld.long 0x8 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x8 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0x8 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0xC "SLVADR1,Slave Address Register"
bitfld.long 0xC 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0xC 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0xC 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x10 "SLVADR2,Slave Address Register"
bitfld.long 0x10 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x10 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0x10 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x14 "SLVADR3,Slave Address Register"
bitfld.long 0x14 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x14 1.--7. 1. "SLVADR,Slave Address."
newline
bitfld.long 0x14 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x18 "SLVQUAL0,Slave Qualification for Address 0 Register"
hexmask.long.byte 0x18 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x18 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor Receiver Data Register"
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK" "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
newline
bitfld.long 0x0 8. "MONSTART,Monitor Received Start" "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2C2"
base ad:0x40108000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable"
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled. The time-out function is disabled.,1: Enabled. The time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable" "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable" "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable" "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status Register"
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag" "0: Not idle. The I2C bus is not idle or MONIDLE..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag" "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag" "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred. An.."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready" "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag" "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State" "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (in..,2: Slave transmit. Data can be transmitted (in..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending" "0: In progress. The Slave function does not..,1: Pending. The Slave function needs software.."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code" "0: Idle. The Master function is available to be..,1: Receive ready. Received data is available (in..,2: Transmit ready. Data can be transmitted (in..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending" "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set Register"
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out Register"
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value"
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value the bottom 4 bits"
line.long 0x4 "CLKDIV,Clock Divider Register"
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Divider Value"
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: Not active,1: Active"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: Not active,1: Active"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag" "0: Not active,1: Active"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag" "0: Not active,1: Active"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready" "0: Not active,1: Active"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag" "0: Not active,1: Active"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status" "0: Not active,1: Active"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending" "0: Not active,1: Active"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: Not active,1: Active"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: Not active,1: Active"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending" "0: Not active,1: Active"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master Control Register"
bitfld.long 0x0 3. "MSTDMA,Master DMA enable" "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control(write-only)" "0: No effect,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control(write-only)" "0: No effect,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue(write-only)" "0: No effect,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master Timing Register"
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks. Minimum SCL high time is 2 clocks of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clocks of..,3: 5 clocks. Minimum SCL high time is 5 clocks of..,4: 6 clocks. Minimum SCL high time is 6 clocks of..,5: 7 clocks. Minimum SCL high time is 7 clocks of..,6: 8 clocks. Minimum SCL high time is 8 clocks of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Master Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x1B
line.long 0x0 "SLVCTL,Slave Control Register"
bitfld.long 0x0 9. "AUTOMATCHREAD,Automatic Match Read" "0: In Automatic Mode the expected next operation is..,1: In Automatic Mode the expected next operation is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable" "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK" "0: No effect,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue" "0: No effect,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Slave Data Register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register"
line.long 0x8 "SLVADR0,Slave Address Register"
bitfld.long 0x8 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x8 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x8 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0xC "SLVADR1,Slave Address Register"
bitfld.long 0xC 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0xC 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0xC 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x10 "SLVADR2,Slave Address Register"
bitfld.long 0x10 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x10 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x10 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x14 "SLVADR3,Slave Address Register"
bitfld.long 0x14 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x14 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x14 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x18 "SLVQUAL0,Slave Qualification for Address 0 Register"
hexmask.long.byte 0x18 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x18 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor Receiver Data Register"
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK" "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start" "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2C3"
base ad:0x40109000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable"
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled. The time-out function is disabled.,1: Enabled. The time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable" "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable" "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable" "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status Register"
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
newline
bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag" "0: Not idle. The I2C bus is not idle or MONIDLE..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag" "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
newline
bitfld.long 0x4 17. "MONOV,Monitor Overflow flag" "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred. An.."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready" "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag" "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
newline
rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State" "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (in..,2: Slave transmit. Data can be transmitted (in..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending" "0: In progress. The Slave function does not..,1: Pending. The Slave function needs software.."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss. The Master function has.."
newline
rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code" "0: Idle. The Master function is available to be..,1: Receive ready. Received data is available (in..,2: Transmit ready. Data can be transmitted (in..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending" "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set Register"
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
newline
bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
newline
bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
newline
bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
newline
bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
newline
bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out Register"
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value"
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value the bottom 4 bits"
line.long 0x4 "CLKDIV,Clock Divider Register"
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Divider Value"
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: Not active,1: Active"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag" "0: Not active,1: Active"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 16. "MONRDY,Monitor Ready" "0: Not active,1: Active"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status" "0: Not active,1: Active"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending" "0: Not active,1: Active"
newline
bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: Not active,1: Active"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 0. "MSTPENDING,Master Pending" "0: Not active,1: Active"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master Control Register"
bitfld.long 0x0 3. "MSTDMA,Master DMA enable" "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control(write-only)" "0: No effect,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control(write-only)" "0: No effect,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue(write-only)" "0: No effect,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master Timing Register"
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks. Minimum SCL high time is 2 clocks of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clocks of..,3: 5 clocks. Minimum SCL high time is 5 clocks of..,4: 6 clocks. Minimum SCL high time is 6 clocks of..,5: 7 clocks. Minimum SCL high time is 7 clocks of..,6: 8 clocks. Minimum SCL high time is 8 clocks of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Master Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x1B
line.long 0x0 "SLVCTL,Slave Control Register"
bitfld.long 0x0 9. "AUTOMATCHREAD,Automatic Match Read" "0: In Automatic Mode the expected next operation is..,1: In Automatic Mode the expected next operation is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable" "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK" "0: No effect,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue" "0: No effect,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Slave Data Register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register"
line.long 0x8 "SLVADR0,Slave Address Register"
bitfld.long 0x8 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x8 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x8 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0xC "SLVADR1,Slave Address Register"
bitfld.long 0xC 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0xC 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0xC 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x10 "SLVADR2,Slave Address Register"
bitfld.long 0x10 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x10 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x10 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x14 "SLVADR3,Slave Address Register"
bitfld.long 0x14 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x14 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x14 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x18 "SLVQUAL0,Slave Qualification for Address 0 Register"
hexmask.long.byte 0x18 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x18 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor Receiver Data Register"
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK" "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start" "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2C14"
base ad:0x40126000
group.long 0x800++0xB
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable"
bitfld.long 0x0 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled. The Monitor function will not perform..,1: Enabled. The Monitor function will perform clock.."
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bitfld.long 0x0 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled. The time-out function is disabled.,1: Enabled. The time-out function is enabled. Both.."
bitfld.long 0x0 2. "MONEN,Monitor Enable" "0: Disabled. The I2C Monitor function is disabled.,1: Enabled. The I2C Monitor function is enabled."
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bitfld.long 0x0 1. "SLVEN,Slave Enable" "0: Disabled. The I2C slave function is disabled.,1: Enabled. The I2C slave function is enabled."
bitfld.long 0x0 0. "MSTEN,Master Enable" "0: Disabled. The I2C Master function is disabled.,1: Enabled. The I2C Master function is enabled."
line.long 0x4 "STAT,Status Register"
bitfld.long 0x4 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out. SCL low time has not caused a..,1: Time-out. SCL low time has caused a time-out."
bitfld.long 0x4 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out. I2C bus events have not caused a..,1: Event time-out. The time between I2C bus events.."
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bitfld.long 0x4 19. "MONIDLE,Monitor Idle flag" "0: Not idle. The I2C bus is not idle or MONIDLE..,1: Idle. The I2C bus has gone idle at least once.."
rbitfld.long 0x4 18. "MONACTIVE,Monitor Active flag" "0: Inactive. The Monitor function considers the I2C..,1: Active. The Monitor function considers the I2C.."
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bitfld.long 0x4 17. "MONOV,Monitor Overflow flag" "0: No overrun. Monitor data has not overrun.,1: Overrun. A Monitor data overrun has occurred. An.."
rbitfld.long 0x4 16. "MONRDY,Monitor Ready" "0: No data. The Monitor function does not currently..,1: Data waiting. The Monitor function has data.."
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bitfld.long 0x4 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected. The Slave function has not..,1: Deselected. The Slave function has become.."
rbitfld.long 0x4 14. "SLVSEL,Slave selected flag" "0: Not selected. The Slave function is not..,1: Selected. The Slave function is currently.."
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rbitfld.long 0x4 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0. Slave address 0 was matched.,1: Address 1. Slave address 1 was matched.,2: Address 2. Slave address 2 was matched.,3: Address 3. Slave address 3 was matched."
rbitfld.long 0x4 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching. The slave function is currently..,1: Not stretching. The slave function is not.."
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rbitfld.long 0x4 9.--10. "SLVSTATE,Slave State" "0: Slave address. Address plus R/W received. At..,1: Slave receive. Received data is available (in..,2: Slave transmit. Data can be transmitted (in..,?"
rbitfld.long 0x4 8. "SLVPENDING,Slave Pending" "0: In progress. The Slave function does not..,1: Pending. The Slave function needs software.."
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bitfld.long 0x4 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred.,1: The Master function has experienced a Start/Stop.."
bitfld.long 0x4 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss. The Master function has.."
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rbitfld.long 0x4 1.--3. "MSTSTATE,Master State code" "0: Idle. The Master function is available to be..,1: Receive ready. Received data is available (in..,2: Transmit ready. Data can be transmitted (in..,3: NACK Address. Slave NACKed address.,4: NACK Data. Slave NACKed transmitted data.,?,?,?"
rbitfld.long 0x4 0. "MSTPENDING,Master Pending" "0: In progress. Communication is in progress and..,1: Pending. The Master function needs software.."
line.long 0x8 "INTENSET,Interrupt Enable Set Register"
bitfld.long 0x8 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled. The SCL time-out interrupt is disabled.,1: Enabled. The SCL time-out interrupt is enabled."
bitfld.long 0x8 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled. The Event time-out interrupt is..,1: Enabled. The Event time-out interrupt is enabled."
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bitfld.long 0x8 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled. The MonIdle interrupt is disabled.,1: Enabled. The MonIdle interrupt is enabled."
bitfld.long 0x8 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled. The MonOv interrupt is disabled.,1: Enabled. The MonOv interrupt is enabled."
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bitfld.long 0x8 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled. The MonRdy interrupt is disabled.,1: Enabled. The MonRdy interrupt is enabled."
bitfld.long 0x8 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled. The SlvDeSel interrupt is disabled.,1: Enabled. The SlvDeSel interrupt is enabled."
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bitfld.long 0x8 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled. The SlvNotStr interrupt is disabled.,1: Enabled. The SlvNotStr interrupt is enabled."
bitfld.long 0x8 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled. The SlvPending interrupt is disabled.,1: Enabled. The SlvPending interrupt is enabled."
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bitfld.long 0x8 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled. The MstStStpErr interrupt is disabled.,1: Enabled. The MstStStpErr interrupt is enabled."
bitfld.long 0x8 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled. The MstArbLoss interrupt is disabled.,1: Enabled. The MstArbLoss interrupt is enabled."
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bitfld.long 0x8 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled. The MstPending interrupt is disabled.,1: Enabled. The MstPending interrupt is enabled."
wgroup.long 0x80C++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
bitfld.long 0x0 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
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bitfld.long 0x0 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register"
group.long 0x810++0x7
line.long 0x0 "TIMEOUT,Time-out Register"
hexmask.long.word 0x0 4.--15. 1. "TO,Time-out time value"
hexmask.long.byte 0x0 0.--3. 1. "TOMIN,Time-out time value the bottom 4 bits"
line.long 0x4 "CLKDIV,Clock Divider Register"
hexmask.long.word 0x4 0.--15. 1. "DIVVAL,Divider Value"
rgroup.long 0x818++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: Not active,1: Active"
bitfld.long 0x0 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: Not active,1: Active"
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bitfld.long 0x0 19. "MONIDLE,Monitor Idle flag" "0: Not active,1: Active"
bitfld.long 0x0 17. "MONOV,Monitor Overflow flag" "0: Not active,1: Active"
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bitfld.long 0x0 16. "MONRDY,Monitor Ready" "0: Not active,1: Active"
bitfld.long 0x0 15. "SLVDESEL,Slave Deselected flag" "0: Not active,1: Active"
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bitfld.long 0x0 11. "SLVNOTSTR,Slave Not Stretching status" "0: Not active,1: Active"
bitfld.long 0x0 8. "SLVPENDING,Slave Pending" "0: Not active,1: Active"
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bitfld.long 0x0 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: Not active,1: Active"
bitfld.long 0x0 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: Not active,1: Active"
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bitfld.long 0x0 0. "MSTPENDING,Master Pending" "0: Not active,1: Active"
group.long 0x820++0xB
line.long 0x0 "MSTCTL,Master Control Register"
bitfld.long 0x0 3. "MSTDMA,Master DMA enable" "0: Disable. No DMA requests are generated for..,1: Enable. A DMA request is generated for I2C.."
bitfld.long 0x0 2. "MSTSTOP,Master Stop control(write-only)" "0: No effect,1: Stop. A Stop will be generated on the I2C bus at.."
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bitfld.long 0x0 1. "MSTSTART,Master Start control(write-only)" "0: No effect,1: Start. A Start will be generated on the I2C bus.."
bitfld.long 0x0 0. "MSTCONTINUE,Master Continue(write-only)" "0: No effect,1: Continue. Informs the Master function to.."
line.long 0x4 "MSTTIME,Master Timing Register"
bitfld.long 0x4 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks. Minimum SCL high time is 2 clocks of..,1: 3 clocks. Minimum SCL high time is 3 clocks of..,2: 4 clocks. Minimum SCL high time is 4 clocks of..,3: 5 clocks. Minimum SCL high time is 5 clocks of..,4: 6 clocks. Minimum SCL high time is 6 clocks of..,5: 7 clocks. Minimum SCL high time is 7 clocks of..,6: 8 clocks. Minimum SCL high time is 8 clocks of..,7: 9 clocks. Minimum SCL high time is 9 clocks of.."
bitfld.long 0x4 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks. Minimum SCL low time is 2 clocks of..,1: 3 clocks. Minimum SCL low time is 3 clocks of..,2: 4 clocks. Minimum SCL low time is 4 clocks of..,3: 5 clocks. Minimum SCL low time is 5 clocks of..,4: 6 clocks. Minimum SCL low time is 6 clocks of..,5: 7 clocks. Minimum SCL low time is 7 clocks of..,6: 8 clocks. Minimum SCL low time is 8 clocks of..,7: 9 clocks. Minimum SCL low time is 9 clocks of.."
line.long 0x8 "MSTDAT,Master Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x1B
line.long 0x0 "SLVCTL,Slave Control Register"
bitfld.long 0x0 9. "AUTOMATCHREAD,Automatic Match Read" "0: In Automatic Mode the expected next operation is..,1: In Automatic Mode the expected next operation is.."
bitfld.long 0x0 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation. If AUTONACK = 0..,1: A header with matching SLVADR0 and matching.."
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bitfld.long 0x0 3. "SLVDMA,Slave DMA enable" "0: Disabled. No DMA requests are issued for Slave..,1: Enabled. DMA requests are issued for I2C slave.."
bitfld.long 0x0 1. "SLVNACK,Slave NACK" "0: No effect,1: NACK. Causes the Slave function to NACK the.."
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bitfld.long 0x0 0. "SLVCONTINUE,Slave Continue" "0: No effect,1: Continue. Informs the Slave function to continue.."
line.long 0x4 "SLVDAT,Slave Data Register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,Slave function data register"
line.long 0x8 "SLVADR0,Slave Address Register"
bitfld.long 0x8 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x8 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x8 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0xC "SLVADR1,Slave Address Register"
bitfld.long 0xC 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0xC 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0xC 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x10 "SLVADR2,Slave Address Register"
bitfld.long 0x10 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x10 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x10 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x14 "SLVADR3,Slave Address Register"
bitfld.long 0x14 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are not..,1: Automatic-only mode. All incoming addresses are.."
hexmask.long.byte 0x14 1.--7. 1. "SLVADR,Slave Address."
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bitfld.long 0x14 0. "SADISABLE,Slave Address n Disable" "0: Enabled. Slave Address n is enabled.,1: Ignored. Slave Address n is ignored."
line.long 0x18 "SLVQUAL0,Slave Qualification for Address 0 Register"
hexmask.long.byte 0x18 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x18 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask. The SLVQUAL0 field is used as a logical..,1: Extend. The SLVQUAL0 field is used to extend.."
rgroup.long 0x880++0x3
line.long 0x0 "MONRXDAT,Monitor Receiver Data Register"
bitfld.long 0x0 10. "MONNACK,Monitor Received NACK" "0: Acknowledged. The data currently being provided..,1: Not acknowledged. The data currently being.."
bitfld.long 0x0 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected. The Monitor function..,1: Repeated start detected. The Monitor function.."
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bitfld.long 0x0 8. "MONSTART,Monitor Received Start" "0: No start detected. The Monitor function has not..,1: Start detected. The Monitor function has.."
hexmask.long.byte 0x0 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
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hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree.end
tree "I2S (Inter-Integrated Sound)"
base ad:0x0
tree "I2S0"
base ad:0x40106000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration Register 1 for the Primary Channel Pair"
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length"
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bitfld.long 0x0 13. "WS_POL,WS Polarity" "0: Not inverted,1: Inverted. The WS signal is inverted."
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bitfld.long 0x0 12. "SCK_POL,SCK Polarity" "0: Falling edge,1: Rising edge"
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bitfld.long 0x0 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC subsystem"
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bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual channel,1: Single channel"
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bitfld.long 0x0 9. "LEFTJUST,Left-Justify Data" "0: Right-justified,1: Left-justified"
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bitfld.long 0x0 8. "RIGHTLOW,Right Channel Low" "0: Right high,1: Right low"
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bitfld.long 0x0 6.--7. "MODE,Mode" "0: Classic Mode,1: DSP mode WS 50% duty cycle,2: DSP mode WS 1 clock,3: DSP mode WS 1 data"
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bitfld.long 0x0 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: Normal Slave Mode,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode"
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bitfld.long 0x0 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs"
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bitfld.long 0x0 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: Pause"
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bitfld.long 0x0 0. "MAINENABLE,Main Enable" "0: Disabled,1: Enabled"
line.long 0x4 "CFG2,Configuration Register 2 for the Primary Channel Pair"
hexmask.long.word 0x4 16.--26. 1. "POSITION,Data Position"
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hexmask.long.word 0x4 0.--10. 1. "FRAMELEN,Frame Length"
line.long 0x8 "STAT,Status Register for the Primary Channel Pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused" "0: Not Paused,1: Paused"
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rbitfld.long 0x8 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
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eventfld.long 0x8 1. "SLVFRMERR,Slave Frame Error" "0: No error,1: Error"
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rbitfld.long 0x8 0. "BUSY,Busy Status" "0: Idle,1: Busy"
group.long 0xC1C++0xB
line.long 0x0 "DIV,Clock Divider"
hexmask.long.word 0x0 0.--11. 1. "DIV,Divider"
line.long 0x4 "P1CFG1,Configuration Register 1 for Channel Pair 1"
bitfld.long 0x4 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
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bitfld.long 0x4 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x8 "P2CFG1,Configuration Register 2 for Channel Pair 1"
hexmask.long.word 0x8 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC28++0x3
line.long 0x0 "PSTAT1,Status Register for Channel Pair 1"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
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bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC40++0x7
line.long 0x0 "P1CFG2,Configuration Register 1 for Channel Pair 2"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG2,Configuration Register 2 for Channel Pair 2"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC48++0x3
line.long 0x0 "PSTAT2,Status Register for Channel Pair 2"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC60++0x7
line.long 0x0 "P1CFG3,Configuration Register 1 for Channel Pair 3"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG3,Configuration Register 2 for Channel Pair 3"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC68++0x3
line.long 0x0 "PSTAT3,Status Register for Channel Pair 3"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration and Enable"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read causes the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device from..,1: A device wake-up for DMA occurs if the receive.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 13. "DMARX,DMA Receive" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 12. "DMATX,DMA Transmit" "0: Disabled,1: Enabled"
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits"
newline
bitfld.long 0x0 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16"
newline
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S Empty 0" "0: Last value,1: Zero"
newline
bitfld.long 0x0 1. "ENABLERX,Enable Receive FIFO" "0: Disabled. The receive FIFO is not enabled.,1: Enabled. The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit. The transmit FIFO is not..,1: Enabled transmit. The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty; however the peripheral.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No interrupt,1: Interrupt"
newline
eventfld.long 0x4 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured"
newline
eventfld.long 0x4 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured"
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO level.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO level.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Set and Read"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TXLVL,Transmit Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt" "0: Disabled. No interrupt generates for a transmit..,1: Enabled. An interrupt generates when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit Data to the FIFO"
line.long 0x4 "FIFOWR48H,FIFO Write Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO Read Data"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48H,FIFO Read Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0xB
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
line.long 0x8 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x8 0.--4. 1. "FIFOSIZE,Provides the size of the FIFO for software. FIFOSIZE is 8 entries for this chip."
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,I2S Module Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module Identifier"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major Revision"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor Revision"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2S1"
base ad:0x40107000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration Register 1 for the Primary Channel Pair"
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length"
newline
bitfld.long 0x0 13. "WS_POL,WS Polarity" "0: Not inverted,1: Inverted. The WS signal is inverted."
newline
bitfld.long 0x0 12. "SCK_POL,SCK Polarity" "0: Falling edge,1: Rising edge"
newline
bitfld.long 0x0 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC subsystem"
newline
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual channel,1: Single channel"
newline
bitfld.long 0x0 9. "LEFTJUST,Left-Justify Data" "0: Right-justified,1: Left-justified"
newline
bitfld.long 0x0 8. "RIGHTLOW,Right Channel Low" "0: Right high,1: Right low"
newline
bitfld.long 0x0 6.--7. "MODE,Mode" "0: Classic Mode,1: DSP mode WS 50% duty cycle,2: DSP mode WS 1 clock,3: DSP mode WS 1 data"
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: Normal Slave Mode,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode"
newline
bitfld.long 0x0 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: Pause"
newline
bitfld.long 0x0 0. "MAINENABLE,Main Enable" "0: Disabled,1: Enabled"
line.long 0x4 "CFG2,Configuration Register 2 for the Primary Channel Pair"
hexmask.long.word 0x4 16.--26. 1. "POSITION,Data Position"
newline
hexmask.long.word 0x4 0.--10. 1. "FRAMELEN,Frame Length"
line.long 0x8 "STAT,Status Register for the Primary Channel Pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused" "0: Not Paused,1: Paused"
newline
rbitfld.long 0x8 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
eventfld.long 0x8 1. "SLVFRMERR,Slave Frame Error" "0: No error,1: Error"
newline
rbitfld.long 0x8 0. "BUSY,Busy Status" "0: Idle,1: Busy"
group.long 0xC1C++0xB
line.long 0x0 "DIV,Clock Divider"
hexmask.long.word 0x0 0.--11. 1. "DIV,Divider"
line.long 0x4 "P1CFG1,Configuration Register 1 for Channel Pair 1"
bitfld.long 0x4 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x4 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x8 "P2CFG1,Configuration Register 2 for Channel Pair 1"
hexmask.long.word 0x8 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC28++0x3
line.long 0x0 "PSTAT1,Status Register for Channel Pair 1"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC40++0x7
line.long 0x0 "P1CFG2,Configuration Register 1 for Channel Pair 2"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG2,Configuration Register 2 for Channel Pair 2"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC48++0x3
line.long 0x0 "PSTAT2,Status Register for Channel Pair 2"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC60++0x7
line.long 0x0 "P1CFG3,Configuration Register 1 for Channel Pair 3"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG3,Configuration Register 2 for Channel Pair 3"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC68++0x3
line.long 0x0 "PSTAT3,Status Register for Channel Pair 3"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration and Enable"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read causes the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device from..,1: A device wake-up for DMA occurs if the receive.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 13. "DMARX,DMA Receive" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 12. "DMATX,DMA Transmit" "0: Disabled,1: Enabled"
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits"
newline
bitfld.long 0x0 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16"
newline
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S Empty 0" "0: Last value,1: Zero"
newline
bitfld.long 0x0 1. "ENABLERX,Enable Receive FIFO" "0: Disabled. The receive FIFO is not enabled.,1: Enabled. The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit. The transmit FIFO is not..,1: Enabled transmit. The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty; however the peripheral.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No interrupt,1: Interrupt"
newline
eventfld.long 0x4 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured"
newline
eventfld.long 0x4 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured"
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO level.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO level.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Set and Read"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TXLVL,Transmit Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt" "0: Disabled. No interrupt generates for a transmit..,1: Enabled. An interrupt generates when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit Data to the FIFO"
line.long 0x4 "FIFOWR48H,FIFO Write Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO Read Data"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48H,FIFO Read Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0xB
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
line.long 0x8 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x8 0.--4. 1. "FIFOSIZE,Provides the size of the FIFO for software. FIFOSIZE is 8 entries for this chip."
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,I2S Module Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module Identifier"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major Revision"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor Revision"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2S2"
base ad:0x40108000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration Register 1 for the Primary Channel Pair"
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length"
newline
bitfld.long 0x0 13. "WS_POL,WS Polarity" "0: Not inverted,1: Inverted. The WS signal is inverted."
newline
bitfld.long 0x0 12. "SCK_POL,SCK Polarity" "0: Falling edge,1: Rising edge"
newline
bitfld.long 0x0 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC subsystem"
newline
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual channel,1: Single channel"
newline
bitfld.long 0x0 9. "LEFTJUST,Left-Justify Data" "0: Right-justified,1: Left-justified"
newline
bitfld.long 0x0 8. "RIGHTLOW,Right Channel Low" "0: Right high,1: Right low"
newline
bitfld.long 0x0 6.--7. "MODE,Mode" "0: Classic Mode,1: DSP mode WS 50% duty cycle,2: DSP mode WS 1 clock,3: DSP mode WS 1 data"
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: Normal Slave Mode,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode"
newline
bitfld.long 0x0 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: Pause"
newline
bitfld.long 0x0 0. "MAINENABLE,Main Enable" "0: Disabled,1: Enabled"
line.long 0x4 "CFG2,Configuration Register 2 for the Primary Channel Pair"
hexmask.long.word 0x4 16.--26. 1. "POSITION,Data Position"
newline
hexmask.long.word 0x4 0.--10. 1. "FRAMELEN,Frame Length"
line.long 0x8 "STAT,Status Register for the Primary Channel Pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused" "0: Not Paused,1: Paused"
newline
rbitfld.long 0x8 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
eventfld.long 0x8 1. "SLVFRMERR,Slave Frame Error" "0: No error,1: Error"
newline
rbitfld.long 0x8 0. "BUSY,Busy Status" "0: Idle,1: Busy"
group.long 0xC1C++0xB
line.long 0x0 "DIV,Clock Divider"
hexmask.long.word 0x0 0.--11. 1. "DIV,Divider"
line.long 0x4 "P1CFG1,Configuration Register 1 for Channel Pair 1"
bitfld.long 0x4 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x4 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x8 "P2CFG1,Configuration Register 2 for Channel Pair 1"
hexmask.long.word 0x8 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC28++0x3
line.long 0x0 "PSTAT1,Status Register for Channel Pair 1"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC40++0x7
line.long 0x0 "P1CFG2,Configuration Register 1 for Channel Pair 2"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG2,Configuration Register 2 for Channel Pair 2"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC48++0x3
line.long 0x0 "PSTAT2,Status Register for Channel Pair 2"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC60++0x7
line.long 0x0 "P1CFG3,Configuration Register 1 for Channel Pair 3"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG3,Configuration Register 2 for Channel Pair 3"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC68++0x3
line.long 0x0 "PSTAT3,Status Register for Channel Pair 3"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration and Enable"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read causes the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device from..,1: A device wake-up for DMA occurs if the receive.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 13. "DMARX,DMA Receive" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 12. "DMATX,DMA Transmit" "0: Disabled,1: Enabled"
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits"
newline
bitfld.long 0x0 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16"
newline
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S Empty 0" "0: Last value,1: Zero"
newline
bitfld.long 0x0 1. "ENABLERX,Enable Receive FIFO" "0: Disabled. The receive FIFO is not enabled.,1: Enabled. The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit. The transmit FIFO is not..,1: Enabled transmit. The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty; however the peripheral.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No interrupt,1: Interrupt"
newline
eventfld.long 0x4 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured"
newline
eventfld.long 0x4 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured"
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO level.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO level.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Set and Read"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TXLVL,Transmit Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt" "0: Disabled. No interrupt generates for a transmit..,1: Enabled. An interrupt generates when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit Data to the FIFO"
line.long 0x4 "FIFOWR48H,FIFO Write Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO Read Data"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48H,FIFO Read Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0xB
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
line.long 0x8 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x8 0.--4. 1. "FIFOSIZE,Provides the size of the FIFO for software. FIFOSIZE is 8 entries for this chip."
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,I2S Module Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module Identifier"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major Revision"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor Revision"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2S3"
base ad:0x40109000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration Register 1 for the Primary Channel Pair"
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length"
newline
bitfld.long 0x0 13. "WS_POL,WS Polarity" "0: Not inverted,1: Inverted. The WS signal is inverted."
newline
bitfld.long 0x0 12. "SCK_POL,SCK Polarity" "0: Falling edge,1: Rising edge"
newline
bitfld.long 0x0 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC subsystem"
newline
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual channel,1: Single channel"
newline
bitfld.long 0x0 9. "LEFTJUST,Left-Justify Data" "0: Right-justified,1: Left-justified"
newline
bitfld.long 0x0 8. "RIGHTLOW,Right Channel Low" "0: Right high,1: Right low"
newline
bitfld.long 0x0 6.--7. "MODE,Mode" "0: Classic Mode,1: DSP mode WS 50% duty cycle,2: DSP mode WS 1 clock,3: DSP mode WS 1 data"
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: Normal Slave Mode,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode"
newline
bitfld.long 0x0 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: Pause"
newline
bitfld.long 0x0 0. "MAINENABLE,Main Enable" "0: Disabled,1: Enabled"
line.long 0x4 "CFG2,Configuration Register 2 for the Primary Channel Pair"
hexmask.long.word 0x4 16.--26. 1. "POSITION,Data Position"
newline
hexmask.long.word 0x4 0.--10. 1. "FRAMELEN,Frame Length"
line.long 0x8 "STAT,Status Register for the Primary Channel Pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused" "0: Not Paused,1: Paused"
newline
rbitfld.long 0x8 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
eventfld.long 0x8 1. "SLVFRMERR,Slave Frame Error" "0: No error,1: Error"
newline
rbitfld.long 0x8 0. "BUSY,Busy Status" "0: Idle,1: Busy"
group.long 0xC1C++0xB
line.long 0x0 "DIV,Clock Divider"
hexmask.long.word 0x0 0.--11. 1. "DIV,Divider"
line.long 0x4 "P1CFG1,Configuration Register 1 for Channel Pair 1"
bitfld.long 0x4 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x4 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x8 "P2CFG1,Configuration Register 2 for Channel Pair 1"
hexmask.long.word 0x8 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC28++0x3
line.long 0x0 "PSTAT1,Status Register for Channel Pair 1"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC40++0x7
line.long 0x0 "P1CFG2,Configuration Register 1 for Channel Pair 2"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG2,Configuration Register 2 for Channel Pair 2"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC48++0x3
line.long 0x0 "PSTAT2,Status Register for Channel Pair 2"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC60++0x7
line.long 0x0 "P1CFG3,Configuration Register 1 for Channel Pair 3"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG3,Configuration Register 2 for Channel Pair 3"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC68++0x3
line.long 0x0 "PSTAT3,Status Register for Channel Pair 3"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration and Enable"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read causes the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device from..,1: A device wake-up for DMA occurs if the receive.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 13. "DMARX,DMA Receive" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 12. "DMATX,DMA Transmit" "0: Disabled,1: Enabled"
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits"
newline
bitfld.long 0x0 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16"
newline
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S Empty 0" "0: Last value,1: Zero"
newline
bitfld.long 0x0 1. "ENABLERX,Enable Receive FIFO" "0: Disabled. The receive FIFO is not enabled.,1: Enabled. The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit. The transmit FIFO is not..,1: Enabled transmit. The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty; however the peripheral.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No interrupt,1: Interrupt"
newline
eventfld.long 0x4 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured"
newline
eventfld.long 0x4 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured"
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO level.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO level.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Set and Read"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TXLVL,Transmit Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt" "0: Disabled. No interrupt generates for a transmit..,1: Enabled. An interrupt generates when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit Data to the FIFO"
line.long 0x4 "FIFOWR48H,FIFO Write Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO Read Data"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48H,FIFO Read Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0xB
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
line.long 0x8 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x8 0.--4. 1. "FIFOSIZE,Provides the size of the FIFO for software. FIFOSIZE is 8 entries for this chip."
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,I2S Module Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module Identifier"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major Revision"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor Revision"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "I2S14"
base ad:0x40126000
group.long 0xC00++0xB
line.long 0x0 "CFG1,Configuration Register 1 for the Primary Channel Pair"
hexmask.long.byte 0x0 16.--20. 1. "DATALEN,Data Length"
newline
bitfld.long 0x0 13. "WS_POL,WS Polarity" "0: Not inverted,1: Inverted. The WS signal is inverted."
newline
bitfld.long 0x0 12. "SCK_POL,SCK Polarity" "0: Falling edge,1: Rising edge"
newline
bitfld.long 0x0 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC subsystem"
newline
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual channel,1: Single channel"
newline
bitfld.long 0x0 9. "LEFTJUST,Left-Justify Data" "0: Right-justified,1: Left-justified"
newline
bitfld.long 0x0 8. "RIGHTLOW,Right Channel Low" "0: Right high,1: Right low"
newline
bitfld.long 0x0 6.--7. "MODE,Mode" "0: Classic Mode,1: DSP mode WS 50% duty cycle,2: DSP mode WS 1 clock,3: DSP mode WS 1 data"
newline
bitfld.long 0x0 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: Normal Slave Mode,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode"
newline
bitfld.long 0x0 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs"
newline
bitfld.long 0x0 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: Pause"
newline
bitfld.long 0x0 0. "MAINENABLE,Main Enable" "0: Disabled,1: Enabled"
line.long 0x4 "CFG2,Configuration Register 2 for the Primary Channel Pair"
hexmask.long.word 0x4 16.--26. 1. "POSITION,Data Position"
newline
hexmask.long.word 0x4 0.--10. 1. "FRAMELEN,Frame Length"
line.long 0x8 "STAT,Status Register for the Primary Channel Pair"
rbitfld.long 0x8 3. "DATAPAUSED,Data Paused" "0: Not Paused,1: Paused"
newline
rbitfld.long 0x8 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
eventfld.long 0x8 1. "SLVFRMERR,Slave Frame Error" "0: No error,1: Error"
newline
rbitfld.long 0x8 0. "BUSY,Busy Status" "0: Idle,1: Busy"
group.long 0xC1C++0xB
line.long 0x0 "DIV,Clock Divider"
hexmask.long.word 0x0 0.--11. 1. "DIV,Divider"
line.long 0x4 "P1CFG1,Configuration Register 1 for Channel Pair 1"
bitfld.long 0x4 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x4 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x8 "P2CFG1,Configuration Register 2 for Channel Pair 1"
hexmask.long.word 0x8 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC28++0x3
line.long 0x0 "PSTAT1,Status Register for Channel Pair 1"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC40++0x7
line.long 0x0 "P1CFG2,Configuration Register 1 for Channel Pair 2"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG2,Configuration Register 2 for Channel Pair 2"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC48++0x3
line.long 0x0 "PSTAT2,Status Register for Channel Pair 2"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xC60++0x7
line.long 0x0 "P1CFG3,Configuration Register 1 for Channel Pair 3"
bitfld.long 0x0 10. "ONECHANNEL,Single Channel Mode" "0: Dual Channel,1: Single Channel"
newline
bitfld.long 0x0 0. "PAIRENABLE,Pair Enable" "0: Disabled,1: Enabled"
line.long 0x4 "P2CFG3,Configuration Register 2 for Channel Pair 3"
hexmask.long.word 0x4 16.--24. 1. "POSITION,Data Position"
rgroup.long 0xC68++0x3
line.long 0x0 "PSTAT3,Status Register for Channel Pair 3"
bitfld.long 0x0 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused. Data is not currently paused. A..,1: Data Paused. A data pause has been requested and.."
newline
bitfld.long 0x0 2. "LR,Left/Right Indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x0 1. "SLVFRMERR,Save Frame Error Flag" "0: No Error,1: Error"
newline
bitfld.long 0x0 0. "BUSY,Busy Status for Channel Pair" "0: Idle. The transmitter/receiver for this channel..,1: Busy. The transmitter/receiver for this channel.."
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration and Enable"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read causes the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty command for the receive FIFO. When a 1 is written to this bit the RX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty command for the transmit FIFO. When a 1 is written to this bit the TX FIFO is emptied." "0,1"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device from..,1: A device wake-up for DMA occurs if the receive.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 13. "DMARX,DMA Receive" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 12. "DMATX,DMA Transmit" "0: Disabled,1: Enabled"
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits"
newline
bitfld.long 0x0 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16"
newline
bitfld.long 0x0 2. "TXI2SE0,Transmit I2S Empty 0" "0: Last value,1: Zero"
newline
bitfld.long 0x0 1. "ENABLERX,Enable Receive FIFO" "0: Disabled. The receive FIFO is not enabled.,1: Enabled. The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit. The transmit FIFO is not..,1: Enabled transmit. The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty; however the peripheral.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No interrupt,1: Interrupt"
newline
eventfld.long 0x4 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured"
newline
eventfld.long 0x4 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured"
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO level.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO level.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Set and Read"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "TXLVL,Transmit Level Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt" "0: Disabled. No interrupt generates for a transmit..,1: Enabled. An interrupt generates when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared.,1: Interrupt is cleared."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x7
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long 0x0 0.--31. 1. "TXDATA,Transmit Data to the FIFO"
line.long 0x4 "FIFOWR48H,FIFO Write Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x7
line.long 0x0 "FIFORD,FIFO Read Data"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48H,FIFO Read Data for Upper Data Bits"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0xB
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data from the FIFO"
line.long 0x4 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop"
hexmask.long.tbyte 0x4 0.--23. 1. "RXDATA,Received Data from the FIFO"
line.long 0x8 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x8 0.--4. 1. "FIFOSIZE,Provides the size of the FIFO for software. FIFOSIZE is 8 entries for this chip."
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,I2S Module Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module Identifier"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major Revision"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor Revision"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree.end
tree "INPUTMUX (Input Multiplexer)"
base ad:0x40026000
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SCT0_IN_SEL$1,SCT Peripheral Input Multiplexers N"
hexmask.long.byte 0x0 0.--4. 1. "SCT_IN_SEL,SCT0 Input(n) Selection. 24:1 Selection for each. . ."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "PINT_SEL$1,GPIO Pin Input Multiplexer N"
hexmask.long.byte 0x0 0.--7. 1. "PINT_SEL,Port Input (PIOx.y) 64 to 8 Mux Select. . . Pin number select for pin interrupt or pattern match engine input. (For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63."
repeat.end
repeat 33. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "DMAC0_ITRIG_SEL[$1],DMAC0 Input Trigger Multiplexers N"
hexmask.long.byte 0x0 0.--5. 1. "DMA0_ITRIG_SEL,DMA Input Triggers(n) Selection. 22:1 Selection for each. . ."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "DMAC0_OTRIG_SEL$1,DMAC0 Output Trigger Multiplexers N"
hexmask.long.byte 0x0 0.--5. 1. "DMAC0_OTRIG_SEL,DMAC0 Output Triggers Select for A B C D IE. DMAC0_OTRIG_A DMAC0_OTRIG_B DMAC0_OTRIG_C DMAC0_OTRIG_D DMA0 Output Triggers(n) Selection. 32:1 Selection for each. . ."
repeat.end
repeat 33. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "DMAC1_ITRIG_SEL[$1],DMAC1 Input Trigger Multiplexers N"
hexmask.long.byte 0x0 0.--5. 1. "DMA1_ITRIG_SEL,DMA Input Triggers(n) Selection. 18:1 Selection for each. . ."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x500)++0x3
line.long 0x0 "DMAC1_OTRIG_SEL$1,DMAC1 Output Trigger Multiplexers N"
hexmask.long.byte 0x0 0.--5. 1. "DMA1_OTRIG_SEL,DMA1 Output Triggers Select for A B C D IE. DMA1_OTRIG_A DMA1_OTRIG_B DM1_OTRIG_C DMA1_OTRIG_D DMA0 Output Triggers(n) Selection. 32:1 Selection for each. . ."
repeat.end
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40026600 ad:0x40026610 ad:0x40026620 ad:0x40026630)
tree "CT32BIT_CAP_SEL[$1]"
base $2
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "CT32BIT_CAP_SEL$1,CT32BIT N Counter Timer Capture Trigger Multiplexers M"
hexmask.long.byte 0x0 0.--4. 1. "CAPN_SEL,Counter Timer m Capture Port Input n 19:1 Mux Select. . ."
repeat.end
tree.end
repeat.end
base ad:0x40026000
newline
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x700)++0x3
line.long 0x0 "FMEASURE_CH_SEL$1,Frequency Measurement Input Channel Multiplexers"
hexmask.long.byte 0x0 0.--4. 1. "FMEASURE_SEL,Frequency Measure Channel n Selection 7:1 Mux Select. . ."
repeat.end
group.long 0x740++0x3
line.long 0x0 "DMAC0_REQ_ENA0,DMAC0 request enable 0"
bitfld.long 0x0 30. "HASHCRYPT,hash enable" "0: disable,1: enable"
bitfld.long 0x0 29. "FLEXSPI_TX,FLEXSPI TX enable" "0: disable,1: enable"
bitfld.long 0x0 28. "FLEXSPI_RX,FLEXSPI RX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable" "0: disable,1: enable"
bitfld.long 0x0 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable" "0: disable,1: enable"
bitfld.long 0x0 23. "DMIC0CH7,DMIC0 channel 7 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 22. "DMIC0CH6,DMIC0 channel 6 enable" "0: disable,1: enable"
bitfld.long 0x0 21. "DMIC0CH5,DMIC0 channel 5 enable" "0: disable,1: enable"
bitfld.long 0x0 20. "DMIC0CH4,DMIC0 channel 4 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 19. "DMIC0CH3,DMIC0 channel 3 enable" "0: disable,1: enable"
bitfld.long 0x0 18. "DMIC0CH2,DMIC0 channel 2 enable" "0: disable,1: enable"
bitfld.long 0x0 17. "DMIC0CH1,DMIC0 channel 1 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 16. "DMIC0CH0,DMIC0 channel 0 enable" "0: disable,1: enable"
bitfld.long 0x0 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable" "0: disable,1: enable"
bitfld.long 0x0 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable" "0: disable,1: enable"
bitfld.long 0x0 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable" "0: disable,1: enable"
bitfld.long 0x0 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable" "0: disable,1: enable"
bitfld.long 0x0 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable" "0: disable,1: enable"
bitfld.long 0x0 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable" "0: disable,1: enable"
bitfld.long 0x0 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable" "0: disable,1: enable"
bitfld.long 0x0 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable" "0: disable,1: enable"
wgroup.long 0x748++0x3
line.long 0x0 "DMAC0_REQ_ENA0_SET,DMAC0 request enable set 0"
bitfld.long 0x0 30. "HASHCRYPT,Hash enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 29. "FLEXSPI_TX,FLEXSPI TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 28. "FLEXSPI_RX,FLEXSPI RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 27. "FLEXCOMM14_TX,FLEXCOMM15 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 26. "FLEXCOMM14_RX,FLEXCOMM14 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 23. "DMIC0CH7,DMIC0 channel 7 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMIC0CH6,DMIC0 channel 6 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 21. "DMIC0CH5,DMIC0 channel 5 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 20. "DMIC0CH4,DMIC0 channel 4 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMIC0CH3,DMIC0 channel 3 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 18. "DMIC0CH2,DMIC0 channel 2 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 17. "DMIC0CH1,DMIC0 channel 1 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMIC0CH0,DMIC0 channel 0 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
wgroup.long 0x750++0x3
line.long 0x0 "DMAC0_REQ_ENA0_CLR,DMAC0 request enable clear 0"
bitfld.long 0x0 30. "HASHCRYPT,Hash enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 29. "FLEXSPI_TX,FLEXSPI TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 28. "FLEXSPI_RX,FLEXSPI RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 23. "DMIC0CH7,DMIC0 channel 7 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMIC0CH6,DMIC0 channel 6 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 21. "DMIC0CH5,DMIC0 channel 5 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 20. "DMIC0CH4,DMIC0 channel 4 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMIC0CH3,DMIC0 channel 3 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 18. "DMIC0CH2,DMIC0 channel 2 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 17. "DMIC0CH1,DMIC0 channel 1 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMIC0CH0,DMIC0 channel 0 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
group.long 0x760++0x3
line.long 0x0 "DMAC1_REQ_ENA0,DMAC1 request enable 0"
bitfld.long 0x0 30. "HASHCRYPT,hash enable" "0: disable,1: enable"
bitfld.long 0x0 29. "FLEXSPI_TX,FLEXSPI TX enable" "0: disable,1: enable"
bitfld.long 0x0 28. "FLEXSPI_RX,FLEXSPI RX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable" "0: disable,1: enable"
bitfld.long 0x0 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable" "0: disable,1: enable"
bitfld.long 0x0 23. "DMIC0CH7,DMIC0 channel 7 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 22. "DMIC0CH6,DMIC0 channel 6 enable" "0: disable,1: enable"
bitfld.long 0x0 21. "DMIC0CH5,DMIC0 channel 5 enable" "0: disable,1: enable"
bitfld.long 0x0 20. "DMIC0CH4,DMIC0 channel 4 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 19. "DMIC0CH3,DMIC0 channel 3 enable" "0: disable,1: enable"
bitfld.long 0x0 18. "DMIC0CH2,DMIC0 channel 2 enable" "0: disable,1: enable"
bitfld.long 0x0 17. "DMIC0CH1,DMIC0 channel 1 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 16. "DMIC0CH0,DMIC0 channel 0 enable" "0: disable,1: enable"
bitfld.long 0x0 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable" "0: disable,1: enable"
bitfld.long 0x0 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable" "0: disable,1: enable"
bitfld.long 0x0 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable" "0: disable,1: enable"
bitfld.long 0x0 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable" "0: disable,1: enable"
bitfld.long 0x0 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable" "0: disable,1: enable"
bitfld.long 0x0 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable" "0: disable,1: enable"
bitfld.long 0x0 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable" "0: disable,1: enable"
bitfld.long 0x0 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable" "0: disable,1: enable"
newline
bitfld.long 0x0 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable" "0: disable,1: enable"
wgroup.long 0x768++0x3
line.long 0x0 "DMAC1_REQ_ENA0_SET,DMAC1 request enable set 0"
bitfld.long 0x0 30. "HASHCRYPT,Hash enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 29. "FLEXSPI_TX,FLEXSPI TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 28. "FLEXSPI_RX,FLEXSPI RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 27. "FLEXCOMM14_TX,FLEXCOMM15 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 26. "FLEXCOMM14_RX,FLEXCOMM14 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 23. "DMIC0CH7,DMIC0 channel 7 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMIC0CH6,DMIC0 channel 6 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 21. "DMIC0CH5,DMIC0 channel 5 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 20. "DMIC0CH4,DMIC0 channel 4 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMIC0CH3,DMIC0 channel 3 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 18. "DMIC0CH2,DMIC0 channel 2 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 17. "DMIC0CH1,DMIC0 channel 1 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMIC0CH0,DMIC0 channel 0 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable set" "0: No Effect,1: Sets the ENA0 Bit"
wgroup.long 0x770++0x3
line.long 0x0 "DMAC1_REQ_ENA0_CLR,DMAC1 request enable clear 0"
bitfld.long 0x0 30. "HASHCRYPT,Hash enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 29. "FLEXSPI_TX,FLEXSPI TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 28. "FLEXSPI_RX,FLEXSPI RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 27. "FLEXCOMM14_TX,FLEXCOMM14 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 26. "FLEXCOMM14_RX,FLEXCOMM14 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 23. "DMIC0CH7,DMIC0 channel 7 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMIC0CH6,DMIC0 channel 6 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 21. "DMIC0CH5,DMIC0 channel 5 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 20. "DMIC0CH4,DMIC0 channel 4 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMIC0CH3,DMIC0 channel 3 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 18. "DMIC0CH2,DMIC0 channel 2 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 17. "DMIC0CH1,DMIC0 channel 1 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMIC0CH0,DMIC0 channel 0 enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 11. "FLEXCOMM5_TX,FLEXCOMM5 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 10. "FLEXCOMM5_RX,FLEXCOMM5 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 9. "FLEXCOMM4_TX,FLEXCOMM4 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 8. "FLEXCOMM4_RX,FLEXCOMM4 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 7. "FLEXCOMM3_TX,FLEXCOMM3 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 6. "FLEXCOMM3_RX,FLEXCOMM3 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 5. "FLEXCOMM2_TX,FLEXCOMM2 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 4. "FLEXCOMM2_RX,FLEXCOMM2 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 3. "FLEXCOMM1_TX,FLEXCOMM1 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 2. "FLEXCOMM1_RX,FLEXCOMM1 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
bitfld.long 0x0 1. "FLEXCOMM0_TX,FLEXCOMM0 TX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
newline
bitfld.long 0x0 0. "FLEXCOMM0_RX,FLEXCOMM0 RX enable clear" "0: No Effect,1: Clears the ENA0 Bit"
group.long 0x780++0x3
line.long 0x0 "DMAC0_ITRIG_ENA0,DMAC0 input trigger enable 0"
bitfld.long 0x0 31. "DMAC0_ITRIG_INMUX31,DMAC0 input trigger inmux 31 enable" "0: disable,1: enable"
bitfld.long 0x0 30. "DMAC0_ITRIG_INMUX30,DMAC0 input trigger inmux 30 enable" "0: disable,1: enable"
bitfld.long 0x0 29. "DMAC0_ITRIG_INMUX29,DMAC0 input trigger inmux 29 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 28. "DMAC0_ITRIG_INMUX28,DMAC0 input trigger inmux 28 enable" "0: disable,1: enable"
bitfld.long 0x0 27. "DMAC0_ITRIG_INMUX27,DMAC0 input trigger inmux 27 enable" "0: disable,1: enable"
bitfld.long 0x0 26. "DMAC0_ITRIG_INMUX26,DMAC0 input trigger inmux 26 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 25. "DMAC0_ITRIG_INMUX25,DMAC0 input trigger inmux 25 enable" "0: disable,1: enable"
bitfld.long 0x0 24. "DMAC0_ITRIG_INMUX24,DMAC0 input trigger inmux 24 enable" "0: disable,1: enable"
bitfld.long 0x0 23. "DMAC0_ITRIG_INMUX23,DMAC0 input trigger inmux 23 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 22. "DMAC0_ITRIG_INMUX22,DMAC0 input trigger inmux 22 enable" "0: disable,1: enable"
bitfld.long 0x0 21. "DMAC0_ITRIG_INMUX21,DMAC0 input trigger inmux 21 enable" "0: disable,1: enable"
bitfld.long 0x0 20. "DMAC0_ITRIG_INMUX20,DMAC0 input trigger inmux 20 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 19. "DMAC0_ITRIG_INMUX19,DMAC0 input trigger inmux 19 enable" "0: disable,1: enable"
bitfld.long 0x0 18. "DMAC0_ITRIG_INMUX18,DMAC0 input trigger inmux 18 enable" "0: disable,1: enable"
bitfld.long 0x0 17. "DMAC0_ITRIG_INMUX17,DMAC0 input trigger inmux 17 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 16. "DMAC0_ITRIG_INMUX16,DMAC0 input trigger inmux 16 enable" "0: disable,1: enable"
bitfld.long 0x0 15. "DMAC0_ITRIG_INMUX15,DMAC0 input trigger inmux 15 enable" "0: disable,1: enable"
bitfld.long 0x0 14. "DMAC0_ITRIG_INMUX14,DMAC0 input trigger inmux 14 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 13. "DMAC0_ITRIG_INMUX13,DMAC0 input trigger inmux 13 enable" "0: disable,1: enable"
bitfld.long 0x0 12. "DMAC0_ITRIG_INMUX12,DMAC0 input trigger inmux 12 enable" "0: disable,1: enable"
bitfld.long 0x0 11. "DMAC0_ITRIG_INMUX11,DMAC0 input trigger inmux 11 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 10. "DMAC0_ITRIG_INMUX10,DMAC0 input trigger inmux 10 enable" "0: disable,1: enable"
bitfld.long 0x0 9. "DMAC0_ITRIG_INMUX9,DMAC0 input trigger inmux 9 enable" "0: disable,1: enable"
bitfld.long 0x0 8. "DMAC0_ITRIG_INMUX8,DMAC0 input trigger inmux 8 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 7. "DMAC0_ITRIG_INMUX7,DMAC0 input trigger inmux 7 enable" "0: disable,1: enable"
bitfld.long 0x0 6. "DMAC0_ITRIG_INMUX6,DMAC0 input trigger inmux 6 enable" "0: disable,1: enable"
bitfld.long 0x0 5. "DMAC0_ITRIG_INMUX5,DMAC0 input trigger inmux 5 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 4. "DMAC0_ITRIG_INMUX4,DMAC0 input trigger inmux 4 enable" "0: disable,1: enable"
bitfld.long 0x0 3. "DMAC0_ITRIG_INMUX3,DMAC0 input trigger inmux 3 enable" "0: disable,1: enable"
bitfld.long 0x0 2. "DMAC0_ITRIG_INMUX2,DMAC0 input trigger inmux 2 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 1. "DMAC0_ITRIG_INMUX1,DMAC0 input trigger inmux 1 enable" "0: disable,1: enable"
bitfld.long 0x0 0. "DMAC0_ITRIG_INMUX0,DMAC0 input trigger inmux 0 enable" "0: disable,1: enable"
wgroup.long 0x788++0x3
line.long 0x0 "DMAC0_ITRIG_ENA0_SET,DMAC0 input trigger enable set 0"
bitfld.long 0x0 31. "DMAC0_ITRIG_INMUX31,DMAC0 input trigger inmux 31 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 30. "DMAC0_ITRIG_INMUX30,DMAC0 input trigger inmux 30 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 29. "DMAC0_ITRIG_INMUX29,DMAC0 input trigger inmux 29 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 28. "DMAC0_ITRIG_INMUX28,DMAC0 input trigger inmux 28 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 27. "DMAC0_ITRIG_INMUX27,DMAC0 input trigger inmux 27 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 26. "DMAC0_ITRIG_INMUX26,DMAC0 input trigger inmux 26 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 25. "DMAC0_ITRIG_INMUX25,DMAC0 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 24. "DMAC0_ITRIG_INMUX24,DMAC0 input trigger inmux 24 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 23. "DMAC0_ITRIG_INMUX23,DMAC0 input trigger inmux 23 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMAC0_ITRIG_INMUX22,DMAC0 input trigger inmux 22 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 21. "DMAC0_ITRIG_INMUX21,DMAC0 input trigger inmux 21 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 20. "DMAC0_ITRIG_INMUX20,DMAC0 input trigger inmux 20 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMAC0_ITRIG_INMUX19,DMAC0 input trigger inmux 19 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 18. "DMAC0_ITRIG_INMUX18,DMAC0 input trigger inmux 18 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 17. "DMAC0_ITRIG_INMUX17,DMAC0 input trigger inmux 17 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMAC0_ITRIG_INMUX16,DMAC0 input trigger inmux 16 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 15. "DMAC0_ITRIG_INMUX15,DMAC0 input trigger inmux 15 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 14. "DMAC0_ITRIG_INMUX14,DMAC0 input trigger inmux 14 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 13. "DMAC0_ITRIG_INMUX13,DMAC0 input trigger inmux 13 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 12. "DMAC0_ITRIG_INMUX12,DMAC0 input trigger inmux 12 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 11. "DMAC0_ITRIG_INMUX11,DMAC0 input trigger inmux 11 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 10. "DMAC0_ITRIG_INMUX10,DMAC0 input trigger inmux 10 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 9. "DMAC0_ITRIG_INMUX9,DMAC0 input trigger inmux 9 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 8. "DMAC0_ITRIG_INMUX8,DMAC0 input trigger inmux 8 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 7. "DMAC0_ITRIG_INMUX7,DMAC0 input trigger inmux 7 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 6. "DMAC0_ITRIG_INMUX6,DMAC0 input trigger inmux 6 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 5. "DMAC0_ITRIG_INMUX5,DMAC0 input trigger inmux 5 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 4. "DMAC0_ITRIG_INMUX4,DMAC0 input trigger inmux 4 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 3. "DMAC0_ITRIG_INMUX3,DMAC0 input trigger inmux 3 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 2. "DMAC0_ITRIG_INMUX2,DMAC0 input trigger inmux 2 enable set" "0,1"
newline
bitfld.long 0x0 1. "DMAC0_ITRIG_INMUX1,DMAC0 input trigger inmux 1 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 0. "DMAC0_ITRIG_INMUX0,DMAC0 input trigger inmux 0 enable set" "0: No Effect,1: Sets the ENA0 Bit"
wgroup.long 0x790++0x3
line.long 0x0 "DMAC0_ITRIG_ENA0_CLR,DMAC0 input trigger enable clear 0"
bitfld.long 0x0 31. "DMAC0_ITRIG_INMUX31,DMAC0 input trigger inmux 31 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 30. "DMAC0_ITRIG_INMUX30,DMAC0 input trigger inmux 30 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 29. "DMAC0_ITRIG_INMUX29,DMAC0 input trigger inmux 29 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 28. "DMAC0_ITRIG_INMUX28,DMAC0 input trigger inmux 28 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 27. "DMAC0_ITRIG_INMUX27,DMAC0 input trigger inmux 27 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 26. "DMAC0_ITRIG_INMUX26,DMAC0 input trigger inmux 26 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 25. "DMAC0_ITRIG_INMUX25,DMAC0 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 24. "DMAC0_ITRIG_INMUX24,DMAC0 input trigger inmux 24 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 23. "DMAC0_ITRIG_INMUX23,DMAC0 input trigger inmux 23 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMAC0_ITRIG_INMUX22,DMAC0 input trigger inmux 22 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 21. "DMAC0_ITRIG_INMUX21,DMAC0 input trigger inmux 21 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 20. "DMAC0_ITRIG_INMUX20,DMAC0 input trigger inmux 20 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMAC0_ITRIG_INMUX19,DMAC0 input trigger inmux 19 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 18. "DMAC0_ITRIG_INMUX18,DMAC0 input trigger inmux 18 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 17. "DMAC0_ITRIG_INMUX17,DMAC0 input trigger inmux 17 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMAC0_ITRIG_INMUX16,DMAC0 input trigger inmux 16 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 15. "DMAC0_ITRIG_INMUX15,DMAC0 input trigger inmux 15 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 14. "DMAC0_ITRIG_INMUX14,DMAC0 input trigger inmux 14 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 13. "DMAC0_ITRIG_INMUX13,DMAC0 input trigger inmux 13 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 12. "DMAC0_ITRIG_INMUX12,DMAC0 input trigger inmux 12 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 11. "DMAC0_ITRIG_INMUX11,DMAC0 input trigger inmux 11 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 10. "DMAC0_ITRIG_INMUX10,DMAC0 input trigger inmux 10 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 9. "DMAC0_ITRIG_INMUX9,DMAC0 input trigger inmux 9 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 8. "DMAC0_ITRIG_INMUX8,DMAC0 input trigger inmux 8 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 7. "DMAC0_ITRIG_INMUX7,DMAC0 input trigger inmux 7 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 6. "DMAC0_ITRIG_INMUX6,DMAC0 input trigger inmux 6 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 5. "DMAC0_ITRIG_INMUX5,DMAC0 input trigger inmux 5 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 4. "DMAC0_ITRIG_INMUX4,DMAC0 input trigger inmux 4 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 3. "DMAC0_ITRIG_INMUX3,DMAC0 input trigger inmux 3 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 2. "DMAC0_ITRIG_INMUX2,DMAC0 input trigger inmux 2 enable clear" "0,1"
newline
bitfld.long 0x0 1. "DMAC0_ITRIG_INMUX1,DMAC0 input trigger inmux 1 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 0. "DMAC0_ITRIG_INMUX0,DMAC0 input trigger inmux 0 enable clear" "0: No Effect,1: clears the ENA0 Bit"
group.long 0x7A0++0x3
line.long 0x0 "DMAC1_ITRIG_ENA0,DMAC1 input trigger enable 0"
bitfld.long 0x0 31. "DMAC1_ITRIG_INMUX31,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
bitfld.long 0x0 30. "DMAC1_ITRIG_INMUX30,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
bitfld.long 0x0 29. "DMAC1_ITRIG_INMUX29,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 28. "DMAC1_ITRIG_INMUX28,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
bitfld.long 0x0 27. "DMAC1_ITRIG_INMUX27,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
bitfld.long 0x0 26. "DMAC1_ITRIG_INMUX26,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 25. "DMAC1_ITRIG_INMUX25,DMAC1 input trigger inmux 25 enable" "0: disable,1: enable"
bitfld.long 0x0 24. "DMAC1_ITRIG_INMUX24,DMAC1 input trigger inmux 24 enable" "0: disable,1: enable"
bitfld.long 0x0 23. "DMAC1_ITRIG_INMUX23,DMAC1 input trigger inmux 23 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 22. "DMAC1_ITRIG_INMUX22,DMAC1 input trigger inmux 22 enable" "0: disable,1: enable"
bitfld.long 0x0 21. "DMAC1_ITRIG_INMUX21,DMAC1 input trigger inmux 21 enable" "0: disable,1: enable"
bitfld.long 0x0 20. "DMAC1_ITRIG_INMUX20,DMAC1 input trigger inmux 20 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 19. "DMAC1_ITRIG_INMUX19,DMAC1 input trigger inmux 19 enable" "0: disable,1: enable"
bitfld.long 0x0 18. "DMAC1_ITRIG_INMUX18,DMAC1 input trigger inmux 18 enable" "0: disable,1: enable"
bitfld.long 0x0 17. "DMAC1_ITRIG_INMUX17,DMAC1 input trigger inmux 17 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 16. "DMAC1_ITRIG_INMUX16,DMAC1 input trigger inmux 16 enable" "0: disable,1: enable"
bitfld.long 0x0 15. "DMAC1_ITRIG_INMUX15,DMAC1 input trigger inmux 15 enable" "0: disable,1: enable"
bitfld.long 0x0 14. "DMAC1_ITRIG_INMUX14,DMAC1 input trigger inmux 14 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 13. "DMAC1_ITRIG_INMUX13,DMAC1 input trigger inmux 13 enable" "0: disable,1: enable"
bitfld.long 0x0 12. "DMAC1_ITRIG_INMUX12,DMAC1 input trigger inmux 12 enable" "0: disable,1: enable"
bitfld.long 0x0 11. "DMAC1_ITRIG_INMUX11,DMAC1 input trigger inmux 11 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 10. "DMAC1_ITRIG_INMUX10,DMAC1 input trigger inmux 10 enable" "0: disable,1: enable"
bitfld.long 0x0 9. "DMAC1_ITRIG_INMUX9,DMAC1 input trigger inmux 9 enable" "0: disable,1: enable"
bitfld.long 0x0 8. "DMAC1_ITRIG_INMUX8,DMAC1 input trigger inmux 8 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 7. "DMAC1_ITRIG_INMUX7,DMAC1 input trigger inmux 7 enable" "0: disable,1: enable"
bitfld.long 0x0 6. "DMAC1_ITRIG_INMUX6,DMAC1 input trigger inmux 6 enable" "0: disable,1: enable"
bitfld.long 0x0 5. "DMAC1_ITRIG_INMUX5,DMAC1 input trigger inmux 5 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 4. "DMAC1_ITRIG_INMUX4,DMAC1 input trigger inmux 4 enable" "0: disable,1: enable"
bitfld.long 0x0 3. "DMAC1_ITRIG_INMUX3,DMAC1 input trigger inmux 3 enable" "0: disable,1: enable"
bitfld.long 0x0 2. "DMAC1_ITRIG_INMUX2,DMAC1 input trigger inmux 2 enable" "0: disable,1: enable"
newline
bitfld.long 0x0 1. "DMAC1_ITRIG_INMUX1,DMAC1 input trigger inmux 1 enable" "0: disable,1: enable"
bitfld.long 0x0 0. "DMAC1_ITRIG_INMUX0,DMAC1 input trigger inmux 0 enable" "0: disable,1: enable"
wgroup.long 0x7A8++0x3
line.long 0x0 "DMAC1_ITRIG_ENA0_SET,DMAC1 input trigger enable set 0"
bitfld.long 0x0 31. "DMAC1_ITRIG_INMUX31,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 30. "DMAC1_ITRIG_INMUX30,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 29. "DMAC1_ITRIG_INMUX29,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 28. "DMAC1_ITRIG_INMUX28,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 27. "DMAC1_ITRIG_INMUX27,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 26. "DMAC1_ITRIG_INMUX26,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 25. "DMAC1_ITRIG_INMUX25,DMAC1 input trigger inmux 25 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 24. "DMAC1_ITRIG_INMUX24,DMAC1 input trigger inmux 24 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 23. "DMAC1_ITRIG_INMUX23,DMAC1 input trigger inmux 23 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMAC1_ITRIG_INMUX22,DMAC1 input trigger inmux 22 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 21. "DMAC1_ITRIG_INMUX21,DMAC1 input trigger inmux 21 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 20. "DMAC1_ITRIG_INMUX20,DMAC1 input trigger inmux 20 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMAC1_ITRIG_INMUX19,DMAC1 input trigger inmux 19 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 18. "DMAC1_ITRIG_INMUX18,DMAC1 input trigger inmux 18 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 17. "DMAC1_ITRIG_INMUX17,DMAC1 input trigger inmux 17 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMAC1_ITRIG_INMUX16,DMAC1 input trigger inmux 16 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 15. "DMAC1_ITRIG_INMUX15,DMAC1 input trigger inmux 15 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 14. "DMAC1_ITRIG_INMUX14,DMAC1 input trigger inmux 14 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 13. "DMAC1_ITRIG_INMUX13,DMAC1 input trigger inmux 13 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 12. "DMAC1_ITRIG_INMUX12,DMAC1 input trigger inmux 12 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 11. "DMAC1_ITRIG_INMUX11,DMAC1 input trigger inmux 11 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 10. "DMAC1_ITRIG_INMUX10,DMAC1 input trigger inmux 10 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 9. "DMAC1_ITRIG_INMUX9,DMAC1 input trigger inmux 9 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 8. "DMAC1_ITRIG_INMUX8,DMAC1 input trigger inmux 8 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 7. "DMAC1_ITRIG_INMUX7,DMAC1 input trigger inmux 7 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 6. "DMAC1_ITRIG_INMUX6,DMAC1 input trigger inmux 6 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 5. "DMAC1_ITRIG_INMUX5,DMAC1 input trigger inmux 5 enable set" "0: No Effect,1: Sets the ENA0 Bit"
newline
bitfld.long 0x0 4. "DMAC1_ITRIG_INMUX4,DMAC1 input trigger inmux 4 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 3. "DMAC1_ITRIG_INMUX3,DMAC1 input trigger inmux 3 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 2. "DMAC1_ITRIG_INMUX2,DMAC1 input trigger inmux 2 enable set" "0,1"
newline
bitfld.long 0x0 1. "DMAC1_ITRIG_INMUX1,DMAC1 input trigger inmux 1 enable set" "0: No Effect,1: Sets the ENA0 Bit"
bitfld.long 0x0 0. "DMAC1_ITRIG_INMUX0,DMAC1 input trigger inmux 0 enable set" "0: No Effect,1: Sets the ENA0 Bit"
wgroup.long 0x7B0++0x3
line.long 0x0 "DMAC1_ITRIG_ENA0_CLR,DMAC1 input trigger enable clear 0"
bitfld.long 0x0 31. "DMAC1_ITRIG_INMUX31,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 30. "DMAC1_ITRIG_INMUX30,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 29. "DMAC1_ITRIG_INMUX29,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 28. "DMAC1_ITRIG_INMUX28,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 27. "DMAC1_ITRIG_INMUX27,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 26. "DMAC1_ITRIG_INMUX26,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 25. "DMAC1_ITRIG_INMUX25,DMAC1 input trigger inmux 25 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 24. "DMAC1_ITRIG_INMUX24,DMAC1 input trigger inmux 24 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 23. "DMAC1_ITRIG_INMUX23,DMAC1 input trigger inmux 23 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 22. "DMAC1_ITRIG_INMUX22,DMAC1 input trigger inmux 22 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 21. "DMAC1_ITRIG_INMUX21,DMAC1 input trigger inmux 21 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 20. "DMAC1_ITRIG_INMUX20,DMAC1 input trigger inmux 20 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 19. "DMAC1_ITRIG_INMUX19,DMAC1 input trigger inmux 19 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 18. "DMAC1_ITRIG_INMUX18,DMAC1 input trigger inmux 18 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 17. "DMAC1_ITRIG_INMUX17,DMAC1 input trigger inmux 17 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 16. "DMAC1_ITRIG_INMUX16,DMAC1 input trigger inmux 16 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 15. "DMAC1_ITRIG_INMUX15,DMAC1 input trigger inmux 15 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 14. "DMAC1_ITRIG_INMUX14,DMAC1 input trigger inmux 14 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 13. "DMAC1_ITRIG_INMUX13,DMAC1 input trigger inmux 13 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 12. "DMAC1_ITRIG_INMUX12,DMAC1 input trigger inmux 12 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 11. "DMAC1_ITRIG_INMUX11,DMAC1 input trigger inmux 11 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 10. "DMAC1_ITRIG_INMUX10,DMAC1 input trigger inmux 10 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 9. "DMAC1_ITRIG_INMUX9,DMAC1 input trigger inmux 9 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 8. "DMAC1_ITRIG_INMUX8,DMAC1 input trigger inmux 8 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 7. "DMAC1_ITRIG_INMUX7,DMAC1 input trigger inmux 7 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 6. "DMAC1_ITRIG_INMUX6,DMAC1 input trigger inmux 6 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 5. "DMAC1_ITRIG_INMUX5,DMAC1 input trigger inmux 5 enable clear" "0: No Effect,1: clears the ENA0 Bit"
newline
bitfld.long 0x0 4. "DMAC1_ITRIG_INMUX4,DMAC1 input trigger inmux 4 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 3. "DMAC1_ITRIG_INMUX3,DMAC1 input trigger inmux 3 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 2. "DMAC1_ITRIG_INMUX2,DMAC1 input trigger inmux 2 enable clear" "0,1"
newline
bitfld.long 0x0 1. "DMAC1_ITRIG_INMUX1,DMAC1 input trigger inmux 1 enable clear" "0: No Effect,1: clears the ENA0 Bit"
bitfld.long 0x0 0. "DMAC1_ITRIG_INMUX0,DMAC1 input trigger inmux 0 enable clear" "0: No Effect,1: clears the ENA0 Bit"
tree.end
tree "ITRC (Intrusion and Tamper Response Controller)"
base ad:0x40024000
group.long 0x0++0x17
line.long 0x0 "STATUS0,Status0 register"
eventfld.long 0x0 17. "OUT1_STATUS,ITRC triggered CHIP_RESET to reset the chip after all other response process finished." "0,1"
eventfld.long 0x0 16. "OUT0_STATUS,ITRC triggered ITRC_IRQ output." "0,1"
eventfld.long 0x0 15. "IN15_STATUS,True Random Number generator error event." "0,1"
eventfld.long 0x0 14. "IN14_STATUS,Security IP Command violation error event." "0,1"
eventfld.long 0x0 13. "IN13_STATUS,Digital Clock glitch detector module detected an error event." "0,1"
newline
eventfld.long 0x0 12. "IN12_STATUS,Prince IP module detected an error event." "0,1"
eventfld.long 0x0 11. "IN11_STATUS,OTP module detected an error event." "0,1"
eventfld.long 0x0 10. "IN10_STATUS,PKC module detected an error event." "0,1"
eventfld.long 0x0 9. "IN9_STATUS,CSS error event occurred." "0,1"
eventfld.long 0x0 8. "IN8_STATUS,Code watchdog detected an code execution anomaly." "0,1"
newline
eventfld.long 0x0 7. "IN7_STATUS,AHB secure bus checkers detected illegal access." "0,1"
eventfld.long 0x0 6. "IN6_STATUS,Analog Sensor configuration control anamoly detected." "0,1"
eventfld.long 0x0 5. "IN5_STATUS,CAU Analog glitch sensor event occurred on VDD_CORE rail." "0,1"
eventfld.long 0x0 4. "IN4_STATUS,Voltage Sensor detector event occured on VDD_33 rail." "0,1"
eventfld.long 0x0 3. "IN3_STATUS,Voltage Sensor detector event occured on VDD_18 rail." "0,1"
newline
eventfld.long 0x0 2. "IN2_STATUS,Voltage Sensor detector event occured on VDD_CORE rail." "0,1"
eventfld.long 0x0 1. "IN1_STATUS,PMIP Temperature Sensor detector event occurred." "0,1"
eventfld.long 0x0 0. "IN0_STATUS,CAU Temeprature Sensor detector event occurred." "0,1"
line.long 0x4 "STATUS1,Status1 register"
eventfld.long 0x4 5. "IN21_STATUS,Software event 1 occurred." "0,1"
eventfld.long 0x4 4. "IN20_STATUS,Software event 0 occurred." "0,1"
eventfld.long 0x4 3. "IN19_STATUS,T3 PLL UnLock Error occurred." "0,1"
eventfld.long 0x4 2. "IN18_STATUS,TCPU PLL UnLock Error occurred." "0,1"
eventfld.long 0x4 1. "IN17_STATUS,PMIP Analog glitch sensor event occurred on VDD_CORE rail." "0,1"
newline
eventfld.long 0x4 0. "IN16_STATUS,PMIP Analog glitch sensor event occurred on VDD_18 rail." "0,1"
line.long 0x8 "OUT0_SEL0,ITRC_IRQ Trigger source selector 0 register for Event 0 to 15."
bitfld.long 0x8 30.--31. "IN15_SEL0,Selects TRNG violation error event as a trigger source." "0,1,2,3"
bitfld.long 0x8 28.--29. "IN14_SEL0,Selects Security IP Command violation error event as a trigger source." "0,1,2,3"
bitfld.long 0x8 26.--27. "IN13_SEL0,Selects Clock Glitch detector error event as a trigger source." "0,1,2,3"
bitfld.long 0x8 24.--25. "IN12_SEL0,Selects PRINCE IP error event as a trigger source." "0,1,2,3"
bitfld.long 0x8 22.--23. "IN11_SEL0,Selects OTP error event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x8 20.--21. "IN10_SEL0,Selects PKC error event as a trigger source." "0,1,2,3"
bitfld.long 0x8 18.--19. "IN9_SEL0,Selects CSS error event as a trigger source." "0,1,2,3"
bitfld.long 0x8 16.--17. "IN8_SEL0,Selects Code Watch Dog event as a trigger source." "0,1,2,3"
bitfld.long 0x8 14.--15. "IN7_SEL0,Selects AHB secure bus illegal access event as a trigger source." "0,1,2,3"
bitfld.long 0x8 12.--13. "IN6_SEL0,Selects Analog Sensor configuration anamoly event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "IN5_SEL0,Selects Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0x8 8.--9. "IN4_SEL0,Selects Voltage Sensor detector event on VDD_33 rail as a trigger source." "0,1,2,3"
bitfld.long 0x8 6.--7. "IN3_SEL0,Selects Voltage Sensor detector event on VDD_18 rail as a trigger source." "0,1,2,3"
bitfld.long 0x8 4.--5. "IN2_SEL0,Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0x8 2.--3. "IN1_SEL0,Selects PMIP Temperature Sensor event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "IN0_SEL0,Selects CAU Temeprature Sensor event as a trigger source." "0,1,2,3"
line.long 0xC "OUT0_SEL1,ITRC_IRQ Trigger source selector 1 register for Event 0 to 15."
bitfld.long 0xC 30.--31. "IN15_SEL1,Selects TRNG violation error event as a trigger source." "0,1,2,3"
bitfld.long 0xC 28.--29. "IN14_SEL1,Selects Security IP Command violation error event as a trigger source." "0,1,2,3"
bitfld.long 0xC 26.--27. "IN13_SEL1,Selects Clock Glitch detector error event as a trigger source." "0,1,2,3"
bitfld.long 0xC 24.--25. "IN12_SEL1,Selects PRINCE IP error event as a trigger source." "0,1,2,3"
bitfld.long 0xC 22.--23. "IN11_SEL1,Selects OTP error event as a trigger source." "0,1,2,3"
newline
bitfld.long 0xC 20.--21. "IN10_SEL1,Selects PKC error event as a trigger source." "0,1,2,3"
bitfld.long 0xC 18.--19. "IN9_SEL1,Selects CSS error event as a trigger source." "0,1,2,3"
bitfld.long 0xC 16.--17. "IN8_SEL1,Selects Code Watch Dog event as a trigger source." "0,1,2,3"
bitfld.long 0xC 14.--15. "IN7_SEL1,Selects AHB secure bus illegal access event as a trigger source." "0,1,2,3"
bitfld.long 0xC 12.--13. "IN6_SEL1,>Selects Analog Sensor configuration anamoly event as a trigger source." "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "IN5_SEL1,Selects Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0xC 8.--9. "IN4_SEL1,Selects Voltage Sensor detector event on VDD_33 rail as a trigger source." "0,1,2,3"
bitfld.long 0xC 6.--7. "IN3_SEL1,Selects Voltage Sensor detector event on VDD_18 rail as a trigger source." "0,1,2,3"
bitfld.long 0xC 4.--5. "IN2_SEL1,Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0xC 2.--3. "IN1_SEL1,Selects PMIP Temperature Sensor event as a trigger source." "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "IN0_SEL1,Selects CAU Temeprature Sensor event as a trigger source." "0,1,2,3"
line.long 0x10 "OUT1_SEL0,CHIP_RESET Trigger source selector 0 register for Event 0 to 15."
bitfld.long 0x10 30.--31. "IN15_SEL0,Selects TRNG violation error event as a trigger source." "0,1,2,3"
bitfld.long 0x10 28.--29. "IN14_SEL0,Selects Security IP Command violation error event as a trigger source." "0,1,2,3"
bitfld.long 0x10 26.--27. "IN13_SEL0,Selects Clock Glitch detector error event as a trigger source." "0,1,2,3"
bitfld.long 0x10 24.--25. "IN12_SEL0,Selects PRINCE IP error event as a trigger source." "0,1,2,3"
bitfld.long 0x10 22.--23. "IN11_SEL0,Selects OTP error event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x10 20.--21. "IN10_SEL0,Selects PKC error event as a trigger source." "0,1,2,3"
bitfld.long 0x10 18.--19. "IN9_SEL0,Selects CSS error event as a trigger source." "0,1,2,3"
bitfld.long 0x10 16.--17. "IN8_SEL0,Selects Code Watch Dog event as a trigger source." "0,1,2,3"
bitfld.long 0x10 14.--15. "IN7_SEL0,Selects AHB secure bus illegal access event as a trigger source." "0,1,2,3"
bitfld.long 0x10 12.--13. "IN6_SEL0,>Selects Analog Sensor configuration anamoly event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "IN5_SEL0,Selects Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0x10 8.--9. "IN4_SEL0,Selects Voltage Sensor detector event on VDD_33 rail as a trigger source." "0,1,2,3"
bitfld.long 0x10 6.--7. "IN3_SEL0,Selects Voltage Sensor detector event on VDD_18 rail as a trigger source." "0,1,2,3"
bitfld.long 0x10 4.--5. "IN2_SEL0,Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0x10 2.--3. "IN1_SEL0,Selects PMIP Temperature Sensor event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "IN0_SEL0,Selects CAU Temeprature Sensor event as a trigger source." "0,1,2,3"
line.long 0x14 "OUT1_SEL1,CHIP_RESET Trigger source selector 1 register for Event 0 to 15."
bitfld.long 0x14 30.--31. "IN15_SEL1,Selects TRNG violation error event as a trigger source." "0,1,2,3"
bitfld.long 0x14 28.--29. "IN14_SEL1,Selects Security IP Command violation error event as a trigger source." "0,1,2,3"
bitfld.long 0x14 26.--27. "IN13_SEL1,Selects Clock Glitch detector error event as a trigger source." "0,1,2,3"
bitfld.long 0x14 24.--25. "IN12_SEL1,Selects PRINCE IP error event as a trigger source." "0,1,2,3"
bitfld.long 0x14 22.--23. "IN11_SEL1,Selects OTP error event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x14 20.--21. "IN10_SEL1,Selects PKC error event as a trigger source." "0,1,2,3"
bitfld.long 0x14 18.--19. "IN9_SEL1,Selects CSS error event as a trigger source." "0,1,2,3"
bitfld.long 0x14 16.--17. "IN8_SEL1,Selects Code Watch Dog event as a trigger source." "0,1,2,3"
bitfld.long 0x14 14.--15. "IN7_SEL1,Selects AHB secure bus illegal access event as a trigger source." "0,1,2,3"
bitfld.long 0x14 12.--13. "IN6_SEL1,>Selects Analog Sensor configuration anamoly event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "IN5_SEL1,Selects Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0x14 8.--9. "IN4_SEL1,Selects Voltage Sensor detector event on VDD_33 rail as a trigger source." "0,1,2,3"
bitfld.long 0x14 6.--7. "IN3_SEL1,Selects Voltage Sensor detector event on VDD_18 rail as a trigger source." "0,1,2,3"
bitfld.long 0x14 4.--5. "IN2_SEL1,Selects Voltage Sensor detector event on VDD_CORE rail as a trigger source." "0,1,2,3"
bitfld.long 0x14 2.--3. "IN1_SEL1,Selects PMIP Temperature Sensor event as a trigger source." "0,1,2,3"
newline
bitfld.long 0x14 0.--1. "IN0_SEL1,Selects CAU Temeprature Sensor event as a trigger source." "0,1,2,3"
group.long 0x48++0xF
line.long 0x0 "OUT0_SEL0_EVENT16_31,ITRC_IRQ Trigger source selector 0 register for Event 16 to 31."
bitfld.long 0x0 10.--11. "IN21_SEL0,Selects software event 1 as a trigger source." "0,1,2,3"
bitfld.long 0x0 8.--9. "IN20_SEL0,Selects software event 0 as a trigger source." "0,1,2,3"
bitfld.long 0x0 6.--7. "IN19_SEL0,Selects T3 PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0x0 4.--5. "IN18_SEL0,Selects TCPU PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0x0 2.--3. "IN17_SEL0,Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "IN16_SEL0,Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source." "0,1,2,3"
line.long 0x4 "OUT0_SEL1_EVENT16_31,ITRC_IRQ Trigger source selector 1 register for Event 16 to 31."
bitfld.long 0x4 10.--11. "IN21_SEL1,Selects software event 1 as a trigger source." "0,1,2,3"
bitfld.long 0x4 8.--9. "IN20_SEL1,Selects software event 0 as a trigger source." "0,1,2,3"
bitfld.long 0x4 6.--7. "IN19_SEL1,Selects T3 PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0x4 4.--5. "IN18_SEL1,Selects TCPU PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0x4 2.--3. "IN17_SEL1,Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "IN16_SEL1,Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source." "0,1,2,3"
line.long 0x8 "OUT1_SEL0_EVENT16_31,CHIP_RESET Trigger source selector 0 register for Event 16 to 31."
bitfld.long 0x8 10.--11. "IN21_SEL0,Selects software event 1 as a trigger source." "0,1,2,3"
bitfld.long 0x8 8.--9. "IN20_SEL0,Selects software event 0 as a trigger source." "0,1,2,3"
bitfld.long 0x8 6.--7. "IN19_SEL0,Selects T3 PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0x8 4.--5. "IN18_SEL0,Selects TCPU PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0x8 2.--3. "IN17_SEL0,Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "IN16_SEL0,Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source." "0,1,2,3"
line.long 0xC "OUT1_SEL1_EVENT16_31,CHIP_RESET Trigger source selector 1 register for Event 16 to 31."
bitfld.long 0xC 10.--11. "IN21_SEL1,Selects software event 1 as a trigger source." "0,1,2,3"
bitfld.long 0xC 8.--9. "IN20_SEL1,Selects software event 0 as a trigger source." "0,1,2,3"
bitfld.long 0xC 6.--7. "IN19_SEL1,Selects T3 PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0xC 4.--5. "IN18_SEL1,Selects TCPU PLL Unlock event as a trigger source." "0,1,2,3"
bitfld.long 0xC 2.--3. "IN17_SEL1,Selects PMIP Analog glitch sensor event on VDD_CORE rail as a trigger source." "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "IN16_SEL1,Selects PMIP Analog glitch sensor event on VDD_18 rail as a trigger source." "0,1,2,3"
wgroup.long 0xF0++0x7
line.long 0x0 "SW_EVENT0,Software event 0"
hexmask.long 0x0 0.--31. 1. "TRIGGER_SW_EVENT_0,Trigger software event 0."
line.long 0x4 "SW_EVENT1,Software event 1"
hexmask.long 0x4 0.--31. 1. "TRIGGER_SW_EVENT_1,Trigger software event 1."
tree.end
tree "LCDIC"
base ad:0x40128000
group.long 0x8++0x23
line.long 0x0 "CTRL,LCDIC Control Register"
bitfld.long 0x0 4. "DAT_ENDIAN,Byte data endian." "0,1"
bitfld.long 0x0 3. "DMA_EN,DMA enable." "0,1"
bitfld.long 0x0 2. "SPI_MD,SPI mode. Only valid when lcdic_md = 1'd0." "0,1"
bitfld.long 0x0 1. "LCDIC_MD,LCDIC mode." "0,1"
newline
bitfld.long 0x0 0. "LCDIC_EN,LCDIC enable." "0,1"
line.long 0x4 "FIFO_CTRL,FIFO Control Register"
bitfld.long 0x4 3. "RFIFO_THRES,RX FIFO threshold." "0,1"
bitfld.long 0x4 0.--2. "TFIFO_THRES,TX FIFO threshold." "0,1,2,3,4,5,6,7"
line.long 0x8 "TIMER_CTRL,Timer Control Register"
hexmask.long.byte 0x8 4.--7. 1. "TIMER_RATIO1,Timer ratio1."
hexmask.long.byte 0x8 0.--3. 1. "TIMER_RATIO0,Timer ratio0."
line.long 0xC "RST_CTRL,Reset Control Register"
hexmask.long.byte 0xC 13.--18. 1. "RST_WIDTH,Width of each reset pulse. Unit is T(timer_base0). T(reset pulse) = T(timer_base0)*(rst_width+1)."
hexmask.long.byte 0xC 5.--12. 1. "RST_SEQ,Reset sequence. LCD_RST will send rst_seq[0] onto lcd_reset first and then followed by rst_seq[1] until rst_seq_num is reached."
bitfld.long 0xC 2.--4. "RST_SEQ_NUM,Reset sequence pulse number. 3'd0: 1 pulse; 3'd7: 8 pulse." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 1. "RST_POL,Reset signal polarity." "0,1"
newline
bitfld.long 0xC 0. "RST_START,LCD reset start signal. Single pulse." "0,1"
line.long 0x10 "I8080_CTRL0,I8080 Control0 Register"
bitfld.long 0x10 29.--31. "TWDH,Write data hold time. Minimum write data setup time after WR active. T(wdh)=T(lcdic_clk)*twdh." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 26.--28. "TWDS,Write data setup time. Minimum write data setup time before WR active. T(wds)=T(lcdic_clk)*twds." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 23.--25. "TDCH,DC hold time. Minimum DC hold time after WR/RD/CS. T(dch)=T(lcdic_clk)*tdch." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 20.--22. "TDCS,DC setupt time. Minimum DC setup time before WR/RD/CS. T(dcs)=T(lcdic_clk)*tdcs." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 17.--19. "TCSH,CS hold time. Minimum CS hold time after WR/RD. T(csh)=T(lcdic_clk)*tcsh." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 9.--16. 1. "TCSS,CS setup time. Minimum CS setup time before WR/RD. T(css)=T(lcdic_clk)*tcss."
bitfld.long 0x10 6.--8. "TCSW,CS wait time. Minimum CS inactive pulse width. T(csw)=T(lcdic_clk)*tcsw." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 5. "EN_IDLE_OFF,CS off while no transmission." "0,1"
newline
bitfld.long 0x10 4. "EN_DC_OFF,CS off while DC switches." "0,1"
bitfld.long 0x10 3. "WR_POL,WR polarity." "0,1"
bitfld.long 0x10 2. "RD_POL,RD polarity." "0,1"
bitfld.long 0x10 1. "DC_POL,DC polarity." "0,1"
newline
bitfld.long 0x10 0. "CS_POL,CS polarity." "0,1"
line.long 0x14 "I8080_CTRL1,I8080 Control1 Reigster"
hexmask.long.byte 0x14 20.--27. 1. "TRIW,Minmum read enable inactive pulse width. T(riw)=T(lcdic_clk)*triw."
hexmask.long.byte 0x14 12.--19. 1. "TRAW,Minmum read enable active pulse width. T(raw)=T(lcdic_clk)*traw."
hexmask.long.byte 0x14 6.--11. 1. "TWIW,Minmum write enable inactive pulse width. T(wiw)=T(lcdic_clk)*twiw."
hexmask.long.byte 0x14 0.--5. 1. "TWAW,Minmum write enable active pulse width. T(waw)=T(lcdic_clk)*twaw."
line.long 0x18 "SPI_CTRL,SPI Control"
bitfld.long 0x18 3. "SDAT_ENDIAN,SPI serial data endian." "0,1"
bitfld.long 0x18 2. "CPHA,SPI CPHA." "0,1"
bitfld.long 0x18 1. "CPOL,SPI CPOL." "0,1"
bitfld.long 0x18 0. "DC_POL,DC polarity." "0,1"
line.long 0x1C "TE_CTRL,Tearing Effect Control"
hexmask.long.byte 0x1C 6.--11. 1. "TE_TO,Tearing effect timeout time. Unit is T(timer_base1). T(te_to)=T(timer_base1)*te_to. 6'd0 means no te_to check."
hexmask.long.byte 0x1C 0.--5. 1. "TTEW,Tearing effect signal synchronization wait time. Unit is T(timer_base1). T(tew)=T(timer_base1)*ttew."
line.long 0x20 "TO_CTRL,Baseline Control Register 0"
hexmask.long.byte 0x20 4.--9. 1. "CMD_LONG_TO,Command long timeout. Unit is T(timer_base1). T(cmd_long_to)=T(timer_base1)*cmd_long_to. 16'd0 means no cmd_long_to check."
hexmask.long.byte 0x20 0.--3. 1. "CMD_SHORT_TO,Command short timeout. Unit is T(timer_base0). T(cmd_short_to)=T(timer_base0)*cmd_short_to. 4'd0 means no cmd_short_to check."
wgroup.long 0x2C++0x3
line.long 0x0 "TFIFO_WDATA,Baseline Control Register 1"
hexmask.long 0x0 0.--31. 1. "TFIFO_WDATA,TX FIFO write data."
group.long 0x30++0x3
line.long 0x0 "RFIFO_RDATA,Baseline Control Register 2"
hexmask.long 0x0 0.--31. 1. "RFIFO_RDATA,RX FIFO read data."
rgroup.long 0x34++0x7
line.long 0x0 "ISR,Interrupt Status Register"
bitfld.long 0x0 7. "RST_DONE_INTR,Reset done interrupt." "0,1"
bitfld.long 0x0 6. "CMD_DONE_INTR,TRX command done interrupt." "0,1"
bitfld.long 0x0 5. "CMD_TO_INTR,TRX command timeout interrupt." "0,1"
bitfld.long 0x0 4. "TE_TO_INTR,TE timeout interrupt." "0,1"
newline
bitfld.long 0x0 3. "TFIFO_OVERFLOW_INTR,TX FIFO overflow interrupt." "0,1"
bitfld.long 0x0 2. "TFIFO_THRES_INTR,TX FIFO threshold interrupt." "0,1"
bitfld.long 0x0 1. "RFIFO_UNDERFLOW_INTR,RX FIFO underflow interrupt." "0,1"
bitfld.long 0x0 0. "RFIFO_THRES_INTR,RX FIFO threshold interrupt." "0,1"
line.long 0x4 "IRSR,Interrupt Raw Status Register"
bitfld.long 0x4 7. "RST_DONE_RAW_INTR,Reset done raw interrupt." "0,1"
bitfld.long 0x4 6. "CMD_DONE_RAW_INTR,TRX command done raw interrupt." "0,1"
bitfld.long 0x4 5. "CMD_TO_RAW_INTR,TRX command timeout raw interrupt." "0,1"
bitfld.long 0x4 4. "TE_TO_RAW_INTR,TE timeout raw interrupt." "0,1"
newline
bitfld.long 0x4 3. "TFIFO_OVERFLOW_RAW_INTR,TX FIFO overflow raw interrupt." "0,1"
bitfld.long 0x4 2. "TFIFO_THRES_RAW_INTR,TX FIFO threshold raw interrupt." "0,1"
bitfld.long 0x4 1. "RFIFO_UNDERFLOW_RAW_INTR,RX FIFO underflow raw interrupt." "0,1"
bitfld.long 0x4 0. "RFIFO_THRES_RAW_INTR,RX FIFO threshold raw interrupt." "0,1"
group.long 0x3C++0xF
line.long 0x0 "ICR,Interrupt Clear Register"
bitfld.long 0x0 7. "RST_DONE_INTR_CLR,Reset done interrupt clear." "0,1"
bitfld.long 0x0 6. "CMD_DONE_INTR_CLR,TRX command done interrupt clear." "0,1"
bitfld.long 0x0 5. "CMD_TO_INTR_CLR,TRX command timeout interrupt clear." "0,1"
bitfld.long 0x0 4. "TE_TO_INTR_CLR,TE timeout interrupt clear." "0,1"
newline
bitfld.long 0x0 3. "TFIFO_OVERFLOW_INTR_CLR,TX FIFO overflow interrupt clear." "0,1"
bitfld.long 0x0 2. "TFIFO_THRES_INTR_CLR,TX FIFO threshold interrupt clear." "0,1"
bitfld.long 0x0 1. "RFIFO_UNDERFLOW_INTR_CLR,RX FIFO underflow interrupt clear." "0,1"
bitfld.long 0x0 0. "RFIFO_THRES_INTR_CLR,RX FIFO threshold interrupt clear." "0,1"
line.long 0x4 "IMR,Touch Detection Control Register2"
bitfld.long 0x4 7. "RST_DONE_INTR_MSK,Reset done interrupt mask." "0,1"
bitfld.long 0x4 6. "CMD_DONE_INTR_MSK,TRX command done interrupt mask." "0,1"
bitfld.long 0x4 5. "CMD_TO_INTR_MSK,TRX command timeout interrupt mask." "0,1"
bitfld.long 0x4 4. "TE_TO_INTR_MSK,TE timeout interrupt mask." "0,1"
newline
bitfld.long 0x4 3. "TFIFO_OVERFLOW_INTR_MSK,TX FIFO overflow interrupt mask." "0,1"
bitfld.long 0x4 2. "TFIFO_THRES_INTR_MSK,TX FIFO threshold interrupt mask." "0,1"
bitfld.long 0x4 1. "RFIFO_UNDERFLOW_INTR_MSK,RX FIFO underflow interrupt mask." "0,1"
bitfld.long 0x4 0. "RFIFO_THRES_INTR_MSK,RX FIFO threshold interrupt mask." "0,1"
line.long 0x8 "STATUS0,Status Register"
hexmask.long.tbyte 0x8 5.--22. 1. "TB_CNT,Transmission byte counter which indicates how many TB has been successfully transmitted."
bitfld.long 0x8 4. "RFIFO_EMPTY,RX FIFO empty." "0,1"
bitfld.long 0x8 3. "RFIFO_THRES,RX FIFO threshold status." "0,1"
bitfld.long 0x8 2. "TFIFO_FULL,TX FIFO full." "0,1"
newline
bitfld.long 0x8 1. "TFIFO_THRES,TX FIFO threshold status." "0,1"
bitfld.long 0x8 0. "LCDIC_IDLE,lcdic system idle." "0,1"
line.long 0xC "STATUS1,Touch Detection Control Register4"
hexmask.long 0xC 0.--31. 1. "TRX_CMD,TRX command which is under processing."
tree.end
tree "MCI_IO_MUX"
base ad:0x40004000
group.long 0x0++0x13
line.long 0x0 "S_GPIO,security GPIO sel"
hexmask.long 0x0 0.--31. 1. "SEL,spio0[31:0] selection high valid"
line.long 0x4 "FC0,flexcomm0 function sel"
bitfld.long 0x4 10. "SEL_FC0_USART_CMD,flexcomm0:select GPIO-0/5 as usart cts/rts" "0,1"
bitfld.long 0x4 9. "SEL_FC0_USART_DATA,flexcomm0:select GPIO-2/3 as usart rxd/txd" "0,1"
bitfld.long 0x4 8. "SEL_FC0_I2S_DATA_ONLY,flexcomm0:select GPIO-2 as i2s data" "0,1"
bitfld.long 0x4 5. "SEL_FC0_SPI_COPY1,flexcomm0:select GPIO-2/3/4/5 as spi function different slave sel pin compare with field-3" "0,1"
newline
bitfld.long 0x4 4. "SEL_FC0_I2C_COPY_PIN,flexcomm0:select GPIO-0/5 as i2c function" "0,1"
bitfld.long 0x4 3. "SEL_FC0_SPI,flexcomm0:select GPIO-0/2/3/4 as spi function" "0,1"
bitfld.long 0x4 2. "SEL_FC0_I2S,flexcomm0:select GPIO-2/3/4 as i2s function" "0,1"
bitfld.long 0x4 1. "SEL_FC0_I2C,flexcomm0:select GPIO-2/3 as i2c function" "0,1"
newline
bitfld.long 0x4 0. "SEL_FC0_USART_SCK,flexcomm0:select GPIO-4 as usart sck" "0,1"
line.long 0x8 "FC1,flexcomm1 function sel"
bitfld.long 0x8 10. "SEL_FC1_USART_CMD,flexcomm1:select GPIO-6/10 as usart cts/rts" "0,1"
bitfld.long 0x8 9. "SEL_FC1_USART_DATA,flexcomm1:select GPIO-8/9 as usart txd/rxd" "0,1"
bitfld.long 0x8 8. "SEL_FC1_I2S_DATA_ONLY,flexcomm1:select GPIO-9 as i2s data" "0,1"
bitfld.long 0x8 7. "SEL_FC1_SPI_COPY3,flexcomm1:select GPIO-7/8/9/12 as spi function use different slave sel pin compare with field-3/5/6" "0,1"
newline
bitfld.long 0x8 6. "SEL_FC1_SPI_COPY2,flexcomm1:select GPIO-7/8/9/11 as spi function use different slave sel pin compare with field-3/5" "0,1"
bitfld.long 0x8 5. "SEL_FC1_SPI_COPY1,flexcomm1:select GPIO-7/8/9/10 as spi function use different slave sel pin compare with field-3" "0,1"
bitfld.long 0x8 4. "SEL_FC1_I2C_COPY_PIN,flexcomm1:select GPIO-6/10 as i2c function" "0,1"
bitfld.long 0x8 3. "SEL_FC1_SPI,flexcomm1:select GPIO-6/7/8/9 as spi function" "0,1"
newline
bitfld.long 0x8 2. "SEL_FC1_I2S,flexcomm1:select GPIO-7/8/9 as i2s function" "0,1"
bitfld.long 0x8 1. "SEL_FC1_I2C,flexcomm1:select GPIO-8/9 as i2c function" "0,1"
bitfld.long 0x8 0. "SEL_FC1_USART_SCK,flexcomm1:select GPIO-7 as usart sck" "0,1"
line.long 0xC "FC2,flexcomm2 function sel"
bitfld.long 0xC 10. "SEL_FC2_USART_CMD,flexcomm2:select GPIO-16/17 as usart cts/rts" "0,1"
bitfld.long 0xC 9. "SEL_FC2_USART_DATA,flexcomm2:select GPIO-13/14 as usart rxd/txd" "0,1"
bitfld.long 0xC 8. "SEL_FC2_I2S_DATA_ONLY,flexcomm2:select GPIO-13 as i2s data function" "0,1"
bitfld.long 0xC 7. "SEL_FC2_SPI_COPY3,flexcomm2:select GPIO-13/14/15/18 as spi function use different slave sel pin compare with field-3/5/6" "0,1"
newline
bitfld.long 0xC 6. "SEL_FC2_SPI_COPY2,flexcomm2:select GPIO-13/14/15/21 as spi function use different slave sel pin compare with field-3/5" "0,1"
bitfld.long 0xC 5. "SEL_FC2_SPI_COPY1,flexcomm2:select GPIO-13/14/15/17 as spi function use different slave sel pin compare with field-3" "0,1"
bitfld.long 0xC 4. "SEL_FC2_I2C_COPY_PIN,flexcomm2:select GPIO-16/17 as i2c function" "0,1"
bitfld.long 0xC 3. "SEL_FC2_SPI,flexcomm2:select GPIO-13/14/15/16 as spi function" "0,1"
newline
bitfld.long 0xC 2. "SEL_FC2_I2S,flexcomm2:select GPIO-13/14/15 as i2s function" "0,1"
bitfld.long 0xC 1. "SEL_FC2_I2C,flexcomm2:select GPIO-13/14 as i2c function" "0,1"
bitfld.long 0xC 0. "SEL_FC2_USART_SCK,flexcomm2:select GPIO-15 as usart sck" "0,1"
line.long 0x10 "FC3,flexcomm3 function sel"
bitfld.long 0x10 10. "SEL_FC3_USART_CMD,flexcomm3:select GPIO-19/20 as usart rts/cts" "0,1"
bitfld.long 0x10 9. "SEL_FC3_USART_DATA,flexcomm3:select GPIO-24/26 as usart rxd/txd" "0,1"
bitfld.long 0x10 8. "SEL_FC3_I2S_DATA_ONLY,flexcomm3:select GPIO-24 as i2s data" "0,1"
bitfld.long 0x10 7. "SEL_FC3_SPI_COPY3,flexcomm3:select GPIO-23/24/25/26 as spi function use different slave sel pin compare with field-3/5/6" "0,1"
newline
bitfld.long 0x10 6. "SEL_FC3_SPI_COPY2,flexcomm3:select GPIO-22/24/25/26 as spi function use different slave sel pin compare with field-3/5" "0,1"
bitfld.long 0x10 5. "SEL_FC3_SPI_COPY1,flexcomm3:select GPIO-19/24/25/26 as spi function use different slave sel pin compare with field-3" "0,1"
bitfld.long 0x10 4. "SEL_FC3_I2C_COPY_PIN,flexcomm3:select GPIO-19/20 as i2c function" "0,1"
bitfld.long 0x10 3. "SEL_FC3_SPI,flexcomm3:select GPIO-20/24/25/26 as spi function" "0,1"
newline
bitfld.long 0x10 2. "SEL_FC3_I2S,flexcomm3:select GPIO-24/25/26 as i2s function" "0,1"
bitfld.long 0x10 1. "SEL_FC3_I2C,flexcomm3:select GPIO-24/26 as i2c function" "0,1"
bitfld.long 0x10 0. "SEL_FC3_USART_SCK,flexcomm3:select GPIO-25 as usart sck" "0,1"
group.long 0x1C++0x1F
line.long 0x0 "FC14,flexcomm14 function sel"
bitfld.long 0x0 10. "SEL_FC14_USART_CMD,flexcomm14:select GPIO-53/55 as usart cts/rts" "0,1"
bitfld.long 0x0 9. "SEL_FC14_USART_DATA,flexcomm14:select GPIO-56/57 as usart txd/rxd" "0,1"
bitfld.long 0x0 8. "SEL_FC14_I2S_DATA_ONLY,flexcomm14:select GPIO-57 as i2s data" "0,1"
bitfld.long 0x0 7. "SEL_FC14_SPI_COPY3,flexcomm14:select GPIO-52/54/56/57 as spi function use different slave sel pin compare with field-3/5/6" "0,1"
newline
bitfld.long 0x0 6. "SEL_FC14_SPI_COPY2,flexcomm14:select GPIO-51/54/56/57 as spi function use different slave sel pin compare with field-3/5" "0,1"
bitfld.long 0x0 5. "SEL_FC14_SPI_COPY1,flexcomm14:select GPIO-54/55/56/57 as spi function use different slave sel pin compare with field-3" "0,1"
bitfld.long 0x0 4. "SEL_FC14_I2C_COPY_PIN,flexcomm14:select GPIO-53/55 as i2c function" "0,1"
bitfld.long 0x0 3. "SEL_FC14_SPI,flexcomm14:select GPIO-53/54/56/57 as spi function" "0,1"
newline
bitfld.long 0x0 2. "SEL_FC14_I2S,flexcomm14:select GPIO-54/56/57 as i2s function" "0,1"
bitfld.long 0x0 1. "SEL_FC14_I2C,flexcomm14:select GPIO-56/57 as i2c function" "0,1"
bitfld.long 0x0 0. "SEL_FC14_USART_SCK,flexcomm14:select GPIO-54 as usart sck" "0,1"
line.long 0x4 "FSEL,function sel"
bitfld.long 0x4 31. "SEL_ENET_TIMER3,select enet function timer3 pin" "0,1"
bitfld.long 0x4 30. "SEL_ENET_TIMER2,select enet function timer2 pin" "0,1"
bitfld.long 0x4 29. "SEL_ENET_TIMER1,select enet function timer1 pin" "0,1"
bitfld.long 0x4 28. "SEL_ENET_TIMER0,select enet function timer0 pin" "0,1"
newline
bitfld.long 0x4 27. "SEL_ENET_MDIO,select enet function mdio pin" "0,1"
bitfld.long 0x4 26. "SEL_ENET_RX,select enet function rx pin" "0,1"
bitfld.long 0x4 25. "SEL_ENET_TX,select enet function tx pin" "0,1"
bitfld.long 0x4 24. "SEL_FLEXSPI_TEST,select flexspi test function" "0,1"
newline
bitfld.long 0x4 23. "SEL_CLKIN_FRM_PD,select clkin function" "0,1"
hexmask.long.byte 0x4 17.--22. 1. "SEL_GAU_TRIG,select gau trigger function"
bitfld.long 0x4 16. "SEL_ENET_CLK,select enet function clk pin" "0,1"
bitfld.long 0x4 15. "SEL_SDIO,select sdio function" "0,1"
newline
bitfld.long 0x4 14. "SEL_GPIO_INT_BMATCH,select gpio_int_bmatch function" "0,1"
bitfld.long 0x4 13. "SEL_FREQ_GPIO_CLK,select freq_gpio_clk function" "0,1"
bitfld.long 0x4 12. "SEL_LCD_SPI,select lcd_spi function" "0,1"
bitfld.long 0x4 11. "SEL_LCD_8080,select lcd_8080 function" "0,1"
newline
bitfld.long 0x4 10. "SEL_USIM,select usim function" "0,1"
bitfld.long 0x4 9. "SEL_UTICK,select utick function" "0,1"
bitfld.long 0x4 6. "SEL_MCLK,select mclk function" "0,1"
bitfld.long 0x4 5. "SEL_USB,select usb function" "0,1"
newline
bitfld.long 0x4 4. "SEL_PDM,select pdm function" "0,1"
bitfld.long 0x4 3. "SEL_QUAD_SPI_PSRAM,select quad_spi_psram function" "0,1"
bitfld.long 0x4 1. "SEL_QUAD_SPI_FLASH,select quad_spi_flash function" "0,1"
line.long 0x8 "C_TIMER_IN,ctimer input function sel"
hexmask.long.word 0x8 0.--14. 1. "SEL_INPUT,select ctimer input function"
line.long 0xC "C_TIMER_OUT,C_TIMER_OUT"
hexmask.long.word 0xC 0.--14. 1. "SEL_OUTPUT,select ctimer output function"
line.long 0x10 "SC_TIMER,sctimer function sel"
hexmask.long.word 0x10 16.--25. 1. "SEL_OUTPUT,select sctimer output function"
hexmask.long.byte 0x10 0.--7. 1. "SEL_INPUT,select sctimer input function"
line.long 0x14 "GPIO_GRP0,GPIO[31:0] sel"
hexmask.long 0x14 0.--31. 1. "SEL,pio0[31:0] selection high valid"
line.long 0x18 "GPIO_GRP1,GPIO[63:32] sel"
hexmask.long 0x18 0.--31. 1. "SEL,pio0[63:32] selection high valid"
line.long 0x1C "TEST_MODE,test_mode[31:0] sel"
hexmask.long 0x1C 0.--31. 1. "SEL,test_mode[31:0] selection high valid"
tree.end
tree "MRT (Multi-Rate Timer)"
base ad:0x0
tree "MRT0"
base ad:0x4002D000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4002D000 ad:0x4002D010 ad:0x4002D020 ad:0x4002D030)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,Time Interval Value"
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register." "0: No force load.,1: Force load. T"
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,Timer"
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,Control"
bitfld.long 0x0 1.--2. "MODE,Selects the timer mode" "0: Repeat interrupt mode,1: One-shot interrupt mode,2: One-shot stall mode,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMER n interrupt." "0: Disabled. TIMER n interrupt is disabled.,1: Enabled. TIMER n interrupt is enabled."
line.long 0x4 "STAT,Status"
bitfld.long 0x4 2. "INUSE,Channel-In-Use flag. Operating details depend on the operating mode bit (MODCFG.MULTITASK) and affects the use of the Idle Channel register (IDLE_CH)." "0: This timer channel is not in use.,1: This timer channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMER n . RUN bit is read-only." "0: Idle state. TIMER n has stopped.,1: Running. TIMER n is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag" "0: No pending interrupt. Writing a zero is..,1: Pending interrupt."
tree.end
repeat.end
base ad:0x4002D000
newline
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration"
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode"
hexmask.long.byte 0x0 4.--8. 1. "NOB,Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle Channel"
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits returns the lowest idle timer channel. The number is positioned so that it can be used as an offset from the MRT base address to access the registers for the allocated channel. If all timer channels are running .."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global Interrupt Flag"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3 and acts similarly to channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2 and acts similarly to channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1 and acts similarly to channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
rgroup.long 0xFC++0x3
line.long 0x0 "ID_CODE,Multi-Rate Timer ID code"
hexmask.long 0x0 0.--31. 1. "ID_CODE,Multi-Rate Timer ID code"
tree.end
tree "MRT1"
base ad:0x4003F000
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4003F000 ad:0x4003F010 ad:0x4003F020 ad:0x4003F030 ad:0x4003F040 ad:0x4003F050 ad:0x4003F060 ad:0x4003F070)
tree "CHANNEL[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "INTVAL,Time Interval Value"
bitfld.long 0x0 31. "LOAD,Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register." "0: No force load.,1: Force load. T"
hexmask.long.tbyte 0x0 0.--23. 1. "IVALUE,Time interval load value."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "TIMER,Timer"
hexmask.long.tbyte 0x0 0.--23. 1. "VALUE,Holds the current timer value of the down-counter."
group.long ($2+0x8)++0x7
line.long 0x0 "CTRL,Control"
bitfld.long 0x0 1.--2. "MODE,Selects the timer mode" "0: Repeat interrupt mode,1: One-shot interrupt mode,2: One-shot stall mode,?"
bitfld.long 0x0 0. "INTEN,Enable the TIMER n interrupt." "0: Disabled. TIMER n interrupt is disabled.,1: Enabled. TIMER n interrupt is enabled."
line.long 0x4 "STAT,Status"
bitfld.long 0x4 2. "INUSE,Channel-In-Use flag. Operating details depend on the operating mode bit (MODCFG.MULTITASK) and affects the use of the Idle Channel register (IDLE_CH)." "0: This timer channel is not in use.,1: This timer channel is in use."
bitfld.long 0x4 1. "RUN,Indicates the state of TIMER n . RUN bit is read-only." "0: Idle state. TIMER n has stopped.,1: Running. TIMER n is running."
newline
bitfld.long 0x4 0. "INTFLAG,Monitors the interrupt flag" "0: No pending interrupt. Writing a zero is..,1: Pending interrupt."
tree.end
repeat.end
base ad:0x4003F000
newline
group.long 0xF0++0x3
line.long 0x0 "MODCFG,Module Configuration"
bitfld.long 0x0 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register." "0: Hardware status mode. In this mode the INUSE(n)..,1: Multi-task mode"
hexmask.long.byte 0x0 4.--8. 1. "NOB,Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device)"
hexmask.long.byte 0x0 0.--3. 1. "NOC,Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded)"
rgroup.long 0xF4++0x3
line.long 0x0 "IDLE_CH,Idle Channel"
hexmask.long.byte 0x0 4.--7. 1. "CHAN,Idle channel. Reading the CHAN bits returns the lowest idle timer channel. The number is positioned so that it can be used as an offset from the MRT base address to access the registers for the allocated channel. If all timer channels are running .."
group.long 0xF8++0x3
line.long 0x0 "IRQ_FLAG,Global Interrupt Flag"
bitfld.long 0x0 3. "GFLAG3,Monitors the interrupt flag of TIMER3 and acts similarly to channel 0." "0,1"
bitfld.long 0x0 2. "GFLAG2,Monitors the interrupt flag of TIMER2 and acts similarly to channel 0." "0,1"
bitfld.long 0x0 1. "GFLAG1,Monitors the interrupt flag of TIMER1 and acts similarly to channel 0." "0,1"
newline
bitfld.long 0x0 0. "GFLAG0,Monitors the interrupt flag of TIMER0." "0: No pending interrupt. Writing a zero is..,1: Pending interrupt. The interrupt is pending.."
rgroup.long 0xFC++0x3
line.long 0x0 "ID_CODE,Multi-Rate Timer ID code"
hexmask.long 0x0 0.--31. 1. "ID_CODE,Multi-Rate Timer ID code"
tree.end
tree.end
tree "OCOTP (On-Chip One-Time Programmable Controller)"
base ad:0x4000A000
repeat 420. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "OTP_SHADOW[$1],OTP shadow register N"
hexmask.long 0x0 0.--31. 1. "SHADOW,OTP shadow register"
repeat.end
group.long 0x800++0x1B
line.long 0x0 "OTP_CTRL,OTP Controller Control Register"
hexmask.long.word 0x0 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
bitfld.long 0x0 14. "SUPPADD,This bit should be set when programming pr reading the supplementary address space (aka test row)." "0,1"
newline
bitfld.long 0x0 12.--13. "RED_MUX_SEL,For fuse word with Redundancy mode if set red_mux_sel to 0 low 16bit fuse OR high 16bit fuse value can be read if set red_mux_sel to 1 low 16bit fuse value can be read if set red_mux_sel to 2 high 16bit fuse value can be read" "0,1,2,3"
bitfld.long 0x0 11. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
newline
bitfld.long 0x0 10. "SRAM_ENTROPY_DATA_EN,Default is disable read value of sram entropy data read avaliable when set to 1" "0,1"
bitfld.long 0x0 9. "PRNG_OUTPUT_DATA_EN,Default is disable read value of sram entrop data read avaliable when set to 1" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "ADDR,OTP word address for read/programming."
line.long 0x4 "OTP_PDN,OTP Controller PDN Register"
bitfld.long 0x4 0. "PDN,This bit indicates the PDN value of OTP memory" "0,1"
line.long 0x8 "OTP_WRITE_DATA,OTP Controller Write Data Register"
hexmask.long 0x8 0.--31. 1. "WRITE_DATA,Fuse word programming data"
line.long 0xC "OTP_READ_CTRL,OTP Controller Read Ctrl Register"
bitfld.long 0xC 0. "READ,Writing 1 to start a fuse word read operation" "0,1"
line.long 0x10 "OTP_READ_DATA,OTP Controller Read Data Register"
hexmask.long 0x10 0.--31. 1. "READ_DATA,Fuse word read data from read operation."
line.long 0x14 "OTP_CLK_DIV,OTP Controller Clock Divider register"
rbitfld.long 0x14 31. "REQFLAG,Divider status flag" "0,1"
bitfld.long 0x14 30. "HALT,Halts the divider counter" "0,1"
newline
bitfld.long 0x14 29. "RESET,Resets the divider counter" "0,1"
hexmask.long.byte 0x14 0.--3. 1. "DIV,Clock divider value by 1 encoding"
line.long 0x18 "OTP_CRC_CTRL,OTP Controller CRC Ctrl Register"
hexmask.long.byte 0x18 16.--19. 1. "CRC_LUT_SEL,CRC_LUT control register lookup table selection"
bitfld.long 0x18 3. "CRC_RUN_LOCK,This bit is a sticky-bit reset by POR if set this bit will mask enablement of CRC_RUN." "0,1"
newline
rbitfld.long 0x18 2. "CRC_STATUS,1'b1 indicated CRC fail if crc fails set when CRC_DONE asserted" "0,1"
rbitfld.long 0x18 1. "CRC_DONE,1'b1 indicates CRC has completed" "0,1"
newline
bitfld.long 0x18 0. "CRC_RUN,If not mask off set to enable and cleared by CRC_DONE." "0,1"
rgroup.long 0x81C++0x3
line.long 0x0 "OTP_CRC_VALUE,OTP Controller CRC Value Register"
hexmask.long 0x0 0.--31. 1. "CRC_VALUE,The CRC result value. When it is locked reading from it returns value 32'hDEAD_BADA."
group.long 0x820++0x3
line.long 0x0 "OTP_STATUS,OTP Controller Status Register"
rbitfld.long 0x0 26. "CALIBRATED,OTP CALIBRATED status." "0,1"
rbitfld.long 0x0 25. "FUSE_LATCHED,Indicate all shadows registers have been loaded with their corresponding fuse words when set by the controller after reset" "0,1"
newline
bitfld.long 0x0 22. "BUSY,OTP controller status bit" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "FLAGSTATE,OTP FLAGSTATE[3:0] value."
newline
rbitfld.long 0x0 14. "PWOK,OTP PWOK value." "0,1"
rbitfld.long 0x0 13. "ACK,OTP ACK value." "0,1"
newline
rbitfld.long 0x0 12. "PROGFAIL,OTP PROGFAIL status. Write 1 to clear." "0,1"
rbitfld.long 0x0 11. "LOCKED,OTP LOCKED status during read/write operation. Write 1 to clear." "0,1"
newline
rbitfld.long 0x0 9. "LC_NOT_BLANK_STICKY,indicate lc not blank has been blown." "0,1"
hexmask.long.word 0x0 0.--8. 1. "LOAD_COUNTER,store load fuse number when load finished."
rgroup.long 0x824++0x7
line.long 0x0 "OTP_STARTWORD,OTP Controller Startword Register"
hexmask.long.word 0x0 0.--15. 1. "STARTWORD,OTP memory STARTWORD value (i.e. test row word 0 value)."
line.long 0x4 "OTP_VERSION,OTP Controller Version Register"
hexmask.long.byte 0x4 24.--31. 1. "MAJOR_VER,OTP controller major version."
hexmask.long.byte 0x4 16.--23. 1. "MINOR_VER,OTP controller minor version."
newline
hexmask.long.word 0x4 0.--15. 1. "STEP_VER,OTP controller step version."
group.long 0x82C++0x13
line.long 0x0 "OTP_NONMASK_STATUS1,OTP Controller Nonmask Status1 Register"
bitfld.long 0x0 31. "NONMASK_SHADOW_NO_ACCESS,Asserted if access non-exist shadow register without mask. set 1 to clear." "0,1"
bitfld.long 0x0 30. "NONMASK_FUSE_PROG_ERR,Asserted if fuse prog error is generated. set 1 to clear." "0,1"
newline
bitfld.long 0x0 29. "NONMASK_FUSE_READ_ERR,Asserted if fuse read error is generated. Set 1 to clear." "0,1"
bitfld.long 0x0 28. "NONMASK_SHADOW_SRAM_WRITE_ERR,Asserted if shadow sram write error is generated. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 27. "NONMASK_SHADOW_SRAM_READ_ERR,Asserted if shadow sram read error is generated. Set 1 to clear." "0,1"
bitfld.long 0x0 26. "NONMASK_SHADOW_HVF_WRITE_ERR,Asserted if shadow hvf write error is generated. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 25. "NONMASK_SHADOW_HVF_READ_ERR,Asserted if shadow hvf read error is generated. Set 1 to clear." "0,1"
bitfld.long 0x0 24. "NONMASK_WRITE_DURING_RELOAD_ERR,Asserted if writing operation occurs during reload. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 23. "NONMASK_RELOAD_REQ_ERR,Asserted if reload operation occurs when lmda_ocotp_no_reload equal to 1. Set 1 to clear." "0,1"
bitfld.long 0x0 22. "NONMASK_FUSE_ACCESS_ERR,Asserted if fuse read/prog operation occurs when lmda_ocotp_no_fuse_access equal to 1" "0,1"
newline
bitfld.long 0x0 21. "NONMASK_ECC_ZEROIZED_ERR,Asserted if zeroized fuse word is detetced. Set 1 to clear." "0,1"
bitfld.long 0x0 20. "NONMASK_PRNG_O_FAULT,Asserted if output signal o_default of prng module is not equal to 1. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 19. "NONMASK_BITPROTECT_ERR,Asserted if bit protect error is generated. Set 1 to clear." "0,1"
bitfld.long 0x0 18. "NONMASK_COUNTER_ERR,Asserted if load counter is not equal to fuse word number when load finished. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 17. "NONMASK_LOAD_ERR,Asserted if load glitch is detected. Set 1 to clear." "0,1"
bitfld.long 0x0 16. "NONMASK_WRITE_ERR,Asserted if write glitch is detected. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 15. "NONMASK_CRC_SECURTY_PROTECT_ERR,Asserted if not in secured state when SECURITY PROTECTION bit in associated CRC_LUT register is set" "0,1"
bitfld.long 0x0 14. "NONMASK_CRC_WRITE_PROTECT_ERR,Asserted if write access occurs when WRITE PROTECTION bit in associated CRC_LUT register is set" "0,1"
newline
bitfld.long 0x0 13. "NONMASK_CRC_ADDRESS_RANGE_ERR,Asserted if CRC_START_ADDR and CRC_END_ADDR bits in associated CRC_LUT register is out of range both CRC_END_ADDR is smaller than CRC_START_ADDR OR CRC_SATRT_ADDR is larger than 124 OR CRC_END_ADDR is larger than 128 will.." "0,1"
bitfld.long 0x0 12. "NONMASK_CRC_LUT_SEL_ERR,Asserted if CRC_LUT_SEL bits in CRC_CTRL register is out range ([1 8]) when CRC_RUN bit in CRC_CTRL register is set" "0,1"
newline
bitfld.long 0x0 11. "NONMASK_CRC_DONE,Asserted if CRC done. Set 1 to clear." "0,1"
bitfld.long 0x0 10. "NONMASK_SEC,OTP SEC status during read operation. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 9. "NONMASK_SEC_RELOAD,OTP SEC status during reload process. Set 1 to clear." "0,1"
bitfld.long 0x0 8. "NONMASK_DED,OTP DED status during read operation. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 7. "NONMASK_DED_RELOAD,OTP DED status during reload process. Set 1 to clear." "0,1"
bitfld.long 0x0 6. "NONMASK_OTP_STATE_ERR,Asserted if state machine go to invalid state. Set 1 to clear." "0,1"
newline
bitfld.long 0x0 5. "NONMASK_PBRICK_ERR,Asserted if ctrl_ocotp_nxp_zeroization_mask_fuse_wp and ctrl_ocotp_nxp_zeroization_mask_fuse_wp_n are both 0/1 OR ctrl_ocotp_oem_zeroization_mask_wp and ctrl_ocotp_oem_zeroization_mask_wp_n are both 0/1" "0,1"
line.long 0x4 "OTP_MASK_CTRL1,OTP Controller Mask Ctrl1 Register"
bitfld.long 0x4 31. "CTRL_MASK_SHADOW_NO_ACCESS,Used for mask NONMASK_SHADOW_NO_ACCESS bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 30. "CTRL_MASK_FUSE_PROG_ERR,Used for mask NONMASK_FUSE_PROG_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 29. "CTRL_MASK_FUSE_READ_ERR,Used for mask NONMASK_FUSE_READ_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 28. "CTRL_MASK_SHADOW_SRAM_WRITE_ERR,Used for mask NONMASK_SHADOW_SRAM_WRITE_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 27. "CTRL_MASK_SHADOW_SRAM_READ_ERR,Used for mask NONMASK_SHADOW_SRAM_READ_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 26. "CTRL_MASK_SHADOW_HVF_WRITE_ERR,Used for mask NONMASK_SHADOW_HVF_WRITE_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 25. "CTRL_MASK_SHADOW_HVF_READ_ERR,Used for mask NONMASK_SHADOW_HVF_READ_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 24. "CTRL_MASK_WRITE_DURING_RELOAD_ERR,Used for mask NONMASK_WRITE_DURING_RELOAD_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 23. "CTRL_MASK_RELOAD_REQ_ERR,Used for mask NONMASK_RELOAD_REQ_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 22. "CTRL_MASK_FUSE_ACCESS_ERR,Used for mask NONMASK_FUSE_ACCESS_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 21. "CTRL_MASK_ECC_ZEROIZED_ERR,Used for mask NONMASK_ECC_ZEROIZED_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 20. "CTRL_MASK_PRNG_O_FAULT,Used for mask NONMASK_PRNG_O_FAULT bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 19. "CTRL_MASK_BITPROTECT_ERR,Used for mask NONMASK_BITPROTECT_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 18. "CTRL_MASK_COUNTER_ERR,Used for mask NONMASK_COUNTER_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 17. "CTRL_MASK_LOAD_ERR,Used for mask NONMASK_LOAD_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 16. "CTRL_MASK_WRITE_ERR,Used for mask NONMASK_WRITE_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 15. "CTRL_MASK_CRC_SECURTY_PROTECT_ERR,Used for mask NONMASK_CRC_SECURTY_PROTECT_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 14. "CTRL_MASK_CRC_WRITE_PROTECT_ERR,Used for mask NONMASK_CRC_WRITE_PROTECT_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 13. "CTRL_MASK_CRC_ADDRESS_RANGE_ERR,Used for mask NONMASK_CRC_ADDRESS_RANGE_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 12. "CTRL_MASK_CRC_LUT_SEL_ERR,Used for mask NONMASK_CRC_LUT_SEL_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 11. "CTRL_MASK_CRC_DONE,Used for mask NONMASK_CRC_DONE bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 10. "CTRL_MASK_SEC,Used for mask NONMASK_SEC bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 9. "CTRL_MASK_SEC_RELOAD,Used for mask NONMASK_SEC_RELOAD bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 8. "CTRL_MASK_DED,Used for mask NONMASK_DED bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 7. "CTRL_MASK_DED_RELOAD,Used for mask NONMASK_DED_RELOAD bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 6. "CTRL_MASK_OTP_STATE_ERR,Used for mask NONMASK_OTP_STATE_ERR bit in NONMASK_STATUS1 register." "0,1"
newline
bitfld.long 0x4 5. "CTRL_MASK_PBRICK_ERR,Used for mask NONMASK_PBRICK_ERR bit in NONMASK_STATUS1 register." "0,1"
bitfld.long 0x4 3. "TMEOUT_COUNTER_EN,Enable of timeout counter feature." "0,1"
newline
bitfld.long 0x4 0.--2. "TIMEOUT_COUNTER,De-asserted cycle number of apb_ready." "0,1,2,3,4,5,6,7"
line.long 0x8 "OTP_MASK_STATUS1,OTP Controller Nonmask Status1 Register"
rbitfld.long 0x8 31. "MASK_SHADOW_NO_ACCESS,asserted if access non-exist shadow register with mask." "0,1"
rbitfld.long 0x8 30. "MASK_FUSE_PROG_ERR,Asserted if fuse prog error is generated." "0,1"
newline
rbitfld.long 0x8 29. "MASK_FUSE_READ_ERR,Asserted if fuse read error is generated." "0,1"
rbitfld.long 0x8 28. "MASK_SHADOW_SRAM_WRITE_ERR,Asserted if shadow sram write error is generated." "0,1"
newline
rbitfld.long 0x8 27. "MASK_SHADOW_SRAM_READ_ERR,Asserted if shadow sram read error is generated." "0,1"
rbitfld.long 0x8 26. "MASK_SHADOW_HVF_WRITE_ERR,Asserted if shadow hvf write error is generated." "0,1"
newline
rbitfld.long 0x8 25. "MASK_SHADOW_HVF_READ_ERR,Asserted if shadow hvf read error is generated." "0,1"
rbitfld.long 0x8 24. "MASK_WRITE_DURING_RELOAD_ERR,Asserted if writing operation occurs during reload." "0,1"
newline
rbitfld.long 0x8 23. "MASK_RELOAD_REQ_ERR,Asserted if reload operation occurs when lmda_ocotp_no_reload equal to 1." "0,1"
rbitfld.long 0x8 22. "MASK_FUSE_ACCESS_ERR,Asserted if fuse read/prog operation occurs when lmda_ocotp_no_fuse_access equal to 1." "0,1"
newline
rbitfld.long 0x8 21. "MASK_ECC_ZEROIZED_ERR,Asserted if zeroized fuse word is detetced." "0,1"
rbitfld.long 0x8 20. "MASK_PRNG_O_FAULT,Asserted if output signal o_default of prng module is not equal to 1." "0,1"
newline
rbitfld.long 0x8 19. "MASK_BITPROTECT_ERR,Asserted if bit protect error is generated." "0,1"
rbitfld.long 0x8 18. "MASK_COUNTER_ERR,Asserted if load counter is not equal to fuse word number when load finished." "0,1"
newline
rbitfld.long 0x8 17. "MASK_LOAD_ERR,Asserted if load glitch is detected." "0,1"
rbitfld.long 0x8 16. "MASK_WRITE_ERR,Asserted if write glitch is detected." "0,1"
newline
rbitfld.long 0x8 15. "MASK_CRC_SECURTY_PROTECT_ERR,Asserted if not in secured state when SECURITY PROTECTION bit in associated CRC_LUT register is set" "0,1"
rbitfld.long 0x8 14. "MASK_CRC_WRITE_PROTECT_ERR,Asserted if write access occurs when WRITE PROTECTION bit in associated CRC_LUT register is set." "0,1"
newline
rbitfld.long 0x8 13. "MASK_CRC_ADDRESS_RANGE_ERR,Asserted if CRC_START_ADDR and CRC_END_ADDR bits in associated CRC_LUT register is out of range both CRC_END_ADDR is smaller than CRC_START_ADDR OR CRC_SATRT_ADDR is larger than 124 OR CRC_END_ADDR is larger than 128 will.." "0,1"
rbitfld.long 0x8 12. "MASK_CRC_LUT_SEL_ERR,Asserted if CRC_LUT_SEL bits in CRC_CTRL register is out range ([1 8]) when CRC_RUN bit in CRC_CTRL register is set" "0,1"
newline
rbitfld.long 0x8 11. "MASK_CRC_DONE,Asserted if CRC done." "0,1"
rbitfld.long 0x8 10. "MASK_SEC,OTP SEC status during read operation." "0,1"
newline
rbitfld.long 0x8 9. "SEC_RELOAD,OTP SEC status during reload process." "0,1"
rbitfld.long 0x8 8. "MASK_DED,OTP DED status during read operation." "0,1"
newline
rbitfld.long 0x8 7. "DED_RELOAD,OTP DED status during reload process." "0,1"
bitfld.long 0x8 6. "MASK_OTP_STATE_ERR,Asserted if state machine go to invalid state." "0,1"
newline
bitfld.long 0x8 5. "MASK_PBRICK_ERR,Asserted if ctrl_ocotp_nxp_zeroization_mask_fuse_wp and ctrl_ocotp_nxp_zeroization_mask_fuse_wp_n are both 0/1 OR ctrl_ocotp_oem_zeroization_mask_wp and ctrl_ocotp_oem_zeroization_mask_wp_n are both 0/1" "0,1"
line.long 0xC "OTP_ECC_CTRL,OTP Controller ECC Ctrl Register"
bitfld.long 0xC 31. "CTRL_ECC_ZERO,Start zeroized." "0,1"
bitfld.long 0xC 30. "CTRL_ECC_BLOCK,Prevent ECC generation when fuses are being provisiond" "0,1"
newline
bitfld.long 0xC 29. "CTRL_ECC_BLOCK_DISABLE,When set to 1 the CTRL_ECC_BLOCK will be masked." "0,1"
bitfld.long 0xC 28. "CTRL_ECC_GEN_DATA_SEL,When 1 - the OTP controller will be provisioned to ECC fuses" "0,1"
newline
bitfld.long 0xC 27. "CTRL_ECC_GEN_EN,When set control register will initialOTP controller to provision the ECC data" "0,1"
bitfld.long 0xC 26. "CTRL_ECC_SEC_DISABLE,When set disable applying ECC signal bit correction of fuse data" "0,1"
newline
bitfld.long 0xC 25. "CTRL_ECC_GEN_RD_DATA_SEL,when 1 - the OTP controller will read the eFuse word contents to generate the ECC parity value to be provisioned" "0,1"
hexmask.long.byte 0xC 16.--22. 1. "CTRL_ECC_GEN_DATA,ECC value to be burned (i.e.needed to be blow out write protected fuses)."
newline
hexmask.long.word 0xC 0.--8. 1. "CTRL_ECC_GEN_ADDR,Fuse word address to perform a read-mod-write of data contents to generate ECC."
line.long 0x10 "OTP_ECC_DATA,OTP Controller ECC Date Register"
hexmask.long 0x10 0.--31. 1. "DATA,Used for ecc zeroized OR when CTRL_ECC_BLOCK = 1 and CTRL_ECC_GEN_DATA_SEL = 0 and CTRL_ECC_GEN_RD_DATA_SEL = 0"
rgroup.long 0x840++0x7
line.long 0x0 "OTP_ECC_DBG1,OTP Controller ECC DBG Register1"
hexmask.long.word 0x0 16.--24. 1. "DED_ADDR,Indicates the fuse address generated the first ded that has not been cleared."
hexmask.long.word 0x0 0.--8. 1. "SEC_ADDR,Indicates the fuse address generated the first sec that has not been cleared."
line.long 0x4 "OTP_ECC_DBG2,OTP Controller ECC DBG Register2"
hexmask.long.byte 0x4 24.--30. 1. "ECC_CORRECTION_DETECTION_PARITYBITS,ECC_CORRECTION_DETECTION_PARITYBITS for ECC debug."
hexmask.long.byte 0x4 16.--22. 1. "ECC_SYNDROME,ECC_SYNDROME for ECC debug."
newline
hexmask.long.byte 0x4 8.--14. 1. "READ_ECC_PARITY,READ_ECC_PARITY for ECC debug."
hexmask.long.byte 0x4 0.--6. 1. "WRITE_ECC_PARITY,WRITE_ECC_PARITY for ECC debug."
group.long 0x848++0x7
line.long 0x0 "OTP_ECC_DBG3,OTP Controller ECC DBG Register3"
hexmask.long 0x0 0.--31. 1. "BITS,Access interface for MTR fuse word 7."
line.long 0x4 "OTP_PRNG_RAND_SEED,OTP Controller PRNG Random Seed Register"
hexmask.long 0x4 0.--31. 1. "PRNG_RAND_SEED,One random seed input of PRNG from sentinel configration."
rgroup.long 0x850++0x7
line.long 0x0 "OTP_SRAM_ENTROPY_DATA,OTP Controller SRAM Entropy Data Register"
hexmask.long 0x0 0.--31. 1. "SRAM_ENTROPY_DATA,One random seed input of PRNG from initial sram data."
line.long 0x4 "OTP_PRNG_OUTPUT_DATA,OTP Controller PRNG Output Data Register"
hexmask.long.tbyte 0x4 0.--17. 1. "PRNG_OUTPUT_DATA,Output of PRNG."
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x85C)++0x3
line.long 0x0 "OTP_CRC_LUT_[$1],OTP Controller CRC LUT Registerindex"
bitfld.long 0x0 31. "WRITE_PROTECTION,Write-protection sticky-bit reset by POR" "0,1"
bitfld.long 0x0 30. "SECURITY_PROTECTION,Security protection bit" "0,1"
newline
rbitfld.long 0x0 29. "READ_PROTECTION,CRC read protect" "0,1"
hexmask.long.byte 0x0 16.--22. 1. "CRC_FUSE_END_ADDR,CRC fuse end address."
newline
bitfld.long 0x0 8.--10. "CRC_EXP_VAL_FUSE_ADDR,CRC expected value fuse address." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--6. 1. "CRC_FUSE_START_ADDR,CRC fuse start address."
repeat.end
group.long 0x87C++0x2F
line.long 0x0 "OTP_LOCK_STICKY_0,OTP Controller Lock Sticky Register0"
bitfld.long 0x0 29. "LOCK_STICKY_BIT29,Lock sticky bit29." "0,1"
bitfld.long 0x0 28. "LOCK_STICKY_BIT28,Lock sticky bit28." "0,1"
newline
bitfld.long 0x0 27. "LOCK_STICKY_BIT27,Lock sticky bit27." "0,1"
bitfld.long 0x0 26. "LOCK_STICKY_BIT26,Lock sticky bit26." "0,1"
newline
bitfld.long 0x0 25. "LOCK_STICKY_BIT25,Lock sticky bit25." "0,1"
bitfld.long 0x0 24. "LOCK_STICKY_BIT24,Lock sticky bit24." "0,1"
newline
bitfld.long 0x0 23. "LOCK_STICKY_BIT23,Lock sticky bit23." "0,1"
bitfld.long 0x0 22. "LOCK_STICKY_BIT22,Lock sticky bit22." "0,1"
newline
bitfld.long 0x0 21. "LOCK_STICKY_BIT21,Lock sticky bit21." "0,1"
bitfld.long 0x0 20. "LOCK_STICKY_BIT20,Lock sticky bit20." "0,1"
newline
bitfld.long 0x0 19. "LOCK_STICKY_BIT19,Lock sticky bit19." "0,1"
bitfld.long 0x0 18. "LOCK_STICKY_BIT18,Lock sticky bit18." "0,1"
newline
bitfld.long 0x0 17. "LOCK_STICKY_BIT17,Lock sticky bit17." "0,1"
bitfld.long 0x0 16. "LOCK_STICKY_BIT16,Lock sticky bit16." "0,1"
newline
bitfld.long 0x0 15. "LOCK_STICKY_BIT15,Lock sticky bit15." "0,1"
bitfld.long 0x0 14. "LOCK_STICKY_BIT14,Lock sticky bit14." "0,1"
newline
bitfld.long 0x0 13. "LOCK_STICKY_BIT13,Lock sticky bit13." "0,1"
bitfld.long 0x0 12. "LOCK_STICKY_BIT12,Lock sticky bit12." "0,1"
newline
bitfld.long 0x0 11. "LOCK_STICKY_BIT11,Lock sticky bit11." "0,1"
bitfld.long 0x0 10. "LOCK_STICKY_BIT10,Lock sticky bit10." "0,1"
newline
bitfld.long 0x0 9. "LOCK_STICKY_BIT9,Lock sticky bit9." "0,1"
bitfld.long 0x0 8. "LOCK_STICKY_BIT8,Lock sticky bit8." "0,1"
newline
bitfld.long 0x0 7. "LOCK_STICKY_BIT7,Lock sticky bit7." "0,1"
bitfld.long 0x0 6. "LOCK_STICKY_BIT6,Lock sticky bit6." "0,1"
newline
bitfld.long 0x0 5. "LOCK_STICKY_BIT5,Lock sticky bit5." "0,1"
bitfld.long 0x0 4. "LOCK_STICKY_BIT4,Lock sticky bit4." "0,1"
newline
bitfld.long 0x0 3. "LOCK_STICKY_BIT3,Lock sticky bit3." "0,1"
bitfld.long 0x0 2. "LOCK_STICKY_BIT2,Lock sticky bit2." "0,1"
newline
bitfld.long 0x0 1. "LOCK_STICKY_BIT1,Lock sticky bit1." "0,1"
bitfld.long 0x0 0. "LOCK_STICKY_BIT0,Lock sticky bit0." "0,1"
line.long 0x4 "OTP_LOCK_STICKY_1,OTP Controller Lock Sticky Register1"
bitfld.long 0x4 29. "LOCK_STICKY_BIT59,Lock sticky bit59." "0,1"
bitfld.long 0x4 28. "LOCK_STICKY_BIT58,Lock sticky bit58." "0,1"
newline
bitfld.long 0x4 27. "LOCK_STICKY_BIT57,Lock sticky bit57." "0,1"
bitfld.long 0x4 26. "LOCK_STICKY_BIT56,Lock sticky bit56." "0,1"
newline
bitfld.long 0x4 25. "LOCK_STICKY_BIT55,Lock sticky bit55." "0,1"
bitfld.long 0x4 24. "LOCK_STICKY_BIT54,Lock sticky bit54." "0,1"
newline
bitfld.long 0x4 23. "LOCK_STICKY_BIT53,Lock sticky bit53." "0,1"
bitfld.long 0x4 22. "LOCK_STICKY_BIT52,Lock sticky bit52." "0,1"
newline
bitfld.long 0x4 21. "LOCK_STICKY_BIT51,Lock sticky bit51." "0,1"
bitfld.long 0x4 20. "LOCK_STICKY_BIT50,Lock sticky bit50." "0,1"
newline
bitfld.long 0x4 19. "LOCK_STICKY_BIT49,Lock sticky bit49." "0,1"
bitfld.long 0x4 18. "LOCK_STICKY_BIT48,Lock sticky bit48." "0,1"
newline
bitfld.long 0x4 17. "LOCK_STICKY_BIT47,Lock sticky bit47." "0,1"
bitfld.long 0x4 16. "LOCK_STICKY_BIT46,Lock sticky bit46." "0,1"
newline
bitfld.long 0x4 15. "LOCK_STICKY_BIT45,Lock sticky bit45." "0,1"
bitfld.long 0x4 14. "LOCK_STICKY_BIT44,Lock sticky bit44." "0,1"
newline
bitfld.long 0x4 13. "LOCK_STICKY_BIT43,Lock sticky bit43." "0,1"
bitfld.long 0x4 12. "LOCK_STICKY_BIT42,Lock sticky bit42." "0,1"
newline
bitfld.long 0x4 11. "LOCK_STICKY_BIT41,Lock sticky bit41." "0,1"
bitfld.long 0x4 10. "LOCK_STICKY_BIT40,Lock sticky bit40." "0,1"
newline
bitfld.long 0x4 9. "LOCK_STICKY_BIT39,Lock sticky bit39." "0,1"
bitfld.long 0x4 8. "LOCK_STICKY_BIT38,Lock sticky bit38." "0,1"
newline
bitfld.long 0x4 7. "LOCK_STICKY_BIT37,Lock sticky bit37." "0,1"
bitfld.long 0x4 6. "LOCK_STICKY_BIT36,Lock sticky bit36." "0,1"
newline
bitfld.long 0x4 5. "LOCK_STICKY_BIT35,Lock sticky bit35." "0,1"
bitfld.long 0x4 4. "LOCK_STICKY_BIT34,Lock sticky bit34." "0,1"
newline
bitfld.long 0x4 3. "LOCK_STICKY_BIT33,Lock sticky bit33." "0,1"
bitfld.long 0x4 2. "LOCK_STICKY_BIT32,Lock sticky bit32." "0,1"
newline
bitfld.long 0x4 1. "LOCK_STICKY_BIT31,Lock sticky bit31." "0,1"
bitfld.long 0x4 0. "LOCK_STICKY_BIT30,Lock sticky bit30." "0,1"
line.long 0x8 "OTP_LOCK_STICKY_2,OTP Controller Lock Sticky Register2"
bitfld.long 0x8 29. "LOCK_STICKY_BIT89,Lock sticky bit89." "0,1"
bitfld.long 0x8 28. "LOCK_STICKY_BIT88,Lock sticky bit88." "0,1"
newline
bitfld.long 0x8 27. "LOCK_STICKY_BIT87,Lock sticky bit87." "0,1"
bitfld.long 0x8 26. "LOCK_STICKY_BIT86,Lock sticky bit86." "0,1"
newline
bitfld.long 0x8 25. "LOCK_STICKY_BIT85,Lock sticky bit85." "0,1"
bitfld.long 0x8 24. "LOCK_STICKY_BIT84,Lock sticky bit84." "0,1"
newline
bitfld.long 0x8 23. "LOCK_STICKY_BIT83,Lock sticky bit83." "0,1"
bitfld.long 0x8 22. "LOCK_STICKY_BIT82,Lock sticky bit82." "0,1"
newline
bitfld.long 0x8 21. "LOCK_STICKY_BIT81,Lock sticky bit81." "0,1"
bitfld.long 0x8 20. "LOCK_STICKY_BIT80,Lock sticky bit80." "0,1"
newline
bitfld.long 0x8 19. "LOCK_STICKY_BIT79,Lock sticky bit79." "0,1"
bitfld.long 0x8 18. "LOCK_STICKY_BIT78,Lock sticky bit78." "0,1"
newline
bitfld.long 0x8 17. "LOCK_STICKY_BIT77,Lock sticky bit77." "0,1"
bitfld.long 0x8 16. "LOCK_STICKY_BIT76,Lock sticky bit76." "0,1"
newline
bitfld.long 0x8 15. "LOCK_STICKY_BIT75,Lock sticky bit75." "0,1"
bitfld.long 0x8 14. "LOCK_STICKY_BIT74,Lock sticky bit74." "0,1"
newline
bitfld.long 0x8 13. "LOCK_STICKY_BIT73,Lock sticky bit73." "0,1"
bitfld.long 0x8 12. "LOCK_STICKY_BIT72,Lock sticky bit72." "0,1"
newline
bitfld.long 0x8 11. "LOCK_STICKY_BIT71,Lock sticky bit71." "0,1"
bitfld.long 0x8 10. "LOCK_STICKY_BIT70,Lock sticky bit70." "0,1"
newline
bitfld.long 0x8 9. "LOCK_STICKY_BIT69,Lock sticky bit69." "0,1"
bitfld.long 0x8 8. "LOCK_STICKY_BIT68,Lock sticky bit68." "0,1"
newline
bitfld.long 0x8 7. "LOCK_STICKY_BIT67,Lock sticky bit67." "0,1"
bitfld.long 0x8 6. "LOCK_STICKY_BIT66,Lock sticky bit66." "0,1"
newline
bitfld.long 0x8 5. "LOCK_STICKY_BIT65,Lock sticky bit65." "0,1"
bitfld.long 0x8 4. "LOCK_STICKY_BIT64,Lock sticky bit64." "0,1"
newline
bitfld.long 0x8 3. "LOCK_STICKY_BIT63,Lock sticky bit63." "0,1"
bitfld.long 0x8 2. "LOCK_STICKY_BIT62,Lock sticky bit62." "0,1"
newline
bitfld.long 0x8 1. "LOCK_STICKY_BIT61,Lock sticky bit61." "0,1"
bitfld.long 0x8 0. "LOCK_STICKY_BIT60,Lock sticky bit60." "0,1"
line.long 0xC "OTP_LOCK_STICKY_3,OTP Controller Lock Sticky Register3"
bitfld.long 0xC 29. "LOCK_STICKY_BIT119,Lock sticky bit119." "0,1"
bitfld.long 0xC 28. "LOCK_STICKY_BIT118,Lock sticky bit118." "0,1"
newline
bitfld.long 0xC 27. "LOCK_STICKY_BIT117,Lock sticky bit117." "0,1"
bitfld.long 0xC 26. "LOCK_STICKY_BIT116,Lock sticky bit116." "0,1"
newline
bitfld.long 0xC 25. "LOCK_STICKY_BIT115,Lock sticky bit115." "0,1"
bitfld.long 0xC 24. "LOCK_STICKY_BIT114,Lock sticky bit114." "0,1"
newline
bitfld.long 0xC 23. "LOCK_STICKY_BIT113,Lock sticky bit113." "0,1"
bitfld.long 0xC 22. "LOCK_STICKY_BIT112,Lock sticky bit112." "0,1"
newline
bitfld.long 0xC 21. "LOCK_STICKY_BIT111,Lock sticky bit111." "0,1"
bitfld.long 0xC 20. "LOCK_STICKY_BIT110,Lock sticky bit110." "0,1"
newline
bitfld.long 0xC 19. "LOCK_STICKY_BIT109,Lock sticky bit109." "0,1"
bitfld.long 0xC 18. "LOCK_STICKY_BIT108,Lock sticky bit108." "0,1"
newline
bitfld.long 0xC 17. "LOCK_STICKY_BIT107,Lock sticky bit107." "0,1"
bitfld.long 0xC 16. "LOCK_STICKY_BIT106,Lock sticky bit106." "0,1"
newline
bitfld.long 0xC 15. "LOCK_STICKY_BIT105,Lock sticky bit105." "0,1"
bitfld.long 0xC 14. "LOCK_STICKY_BIT104,Lock sticky bit104." "0,1"
newline
bitfld.long 0xC 13. "LOCK_STICKY_BIT103,Lock sticky bit103." "0,1"
bitfld.long 0xC 12. "LOCK_STICKY_BIT102,Lock sticky bit102." "0,1"
newline
bitfld.long 0xC 11. "LOCK_STICKY_BIT101,Lock sticky bit101." "0,1"
bitfld.long 0xC 10. "LOCK_STICKY_BIT100,Lock sticky bit100." "0,1"
newline
bitfld.long 0xC 9. "LOCK_STICKY_BIT99,Lock sticky bit99." "0,1"
bitfld.long 0xC 8. "LOCK_STICKY_BIT98,Lock sticky bit98." "0,1"
newline
bitfld.long 0xC 7. "LOCK_STICKY_BIT97,Lock sticky bit97." "0,1"
bitfld.long 0xC 6. "LOCK_STICKY_BIT96,Lock sticky bit96." "0,1"
newline
bitfld.long 0xC 5. "LOCK_STICKY_BIT95,Lock sticky bit95." "0,1"
bitfld.long 0xC 4. "LOCK_STICKY_BIT94,Lock sticky bit94." "0,1"
newline
bitfld.long 0xC 3. "LOCK_STICKY_BIT93,Lock sticky bit93." "0,1"
bitfld.long 0xC 2. "LOCK_STICKY_BIT92,Lock sticky bit92." "0,1"
newline
bitfld.long 0xC 1. "LOCK_STICKY_BIT91,Lock sticky bit91." "0,1"
bitfld.long 0xC 0. "LOCK_STICKY_BIT90,Lock sticky bit90." "0,1"
line.long 0x10 "OTP_LOCK_STICKY_4,OTP Controller Lock Sticky Register4"
bitfld.long 0x10 29. "LOCK_STICKY_BIT149,Lock sticky bit149." "0,1"
bitfld.long 0x10 28. "LOCK_STICKY_BIT148,Lock sticky bit148." "0,1"
newline
bitfld.long 0x10 27. "LOCK_STICKY_BIT147,Lock sticky bit147." "0,1"
bitfld.long 0x10 26. "LOCK_STICKY_BIT146,Lock sticky bit146." "0,1"
newline
bitfld.long 0x10 25. "LOCK_STICKY_BIT145,Lock sticky bit145." "0,1"
bitfld.long 0x10 24. "LOCK_STICKY_BIT144,Lock sticky bit144." "0,1"
newline
bitfld.long 0x10 23. "LOCK_STICKY_BIT143,Lock sticky bit143." "0,1"
bitfld.long 0x10 22. "LOCK_STICKY_BIT142,Lock sticky bit142." "0,1"
newline
bitfld.long 0x10 21. "LOCK_STICKY_BIT141,Lock sticky bit141." "0,1"
bitfld.long 0x10 20. "LOCK_STICKY_BIT140,Lock sticky bit140." "0,1"
newline
bitfld.long 0x10 19. "LOCK_STICKY_BIT139,Lock sticky bit139." "0,1"
bitfld.long 0x10 18. "LOCK_STICKY_BIT138,Lock sticky bit138." "0,1"
newline
bitfld.long 0x10 17. "LOCK_STICKY_BIT137,Lock sticky bit137." "0,1"
bitfld.long 0x10 16. "LOCK_STICKY_BIT136,Lock sticky bit136." "0,1"
newline
bitfld.long 0x10 15. "LOCK_STICKY_BIT135,Lock sticky bit135." "0,1"
bitfld.long 0x10 14. "LOCK_STICKY_BIT134,Lock sticky bit134." "0,1"
newline
bitfld.long 0x10 13. "LOCK_STICKY_BIT133,Lock sticky bit133." "0,1"
bitfld.long 0x10 12. "LOCK_STICKY_BIT132,Lock sticky bit132." "0,1"
newline
bitfld.long 0x10 11. "LOCK_STICKY_BIT131,Lock sticky bit131." "0,1"
bitfld.long 0x10 10. "LOCK_STICKY_BIT130,Lock sticky bit130." "0,1"
newline
bitfld.long 0x10 9. "LOCK_STICKY_BIT129,Lock sticky bit129." "0,1"
bitfld.long 0x10 8. "LOCK_STICKY_BIT128,Lock sticky bit128." "0,1"
newline
bitfld.long 0x10 7. "LOCK_STICKY_BIT127,Lock sticky bit127." "0,1"
bitfld.long 0x10 6. "LOCK_STICKY_BIT126,Lock sticky bit126." "0,1"
newline
bitfld.long 0x10 5. "LOCK_STICKY_BIT125,Lock sticky bit125." "0,1"
bitfld.long 0x10 4. "LOCK_STICKY_BIT124,Lock sticky bit124." "0,1"
newline
bitfld.long 0x10 3. "LOCK_STICKY_BIT123,Lock sticky bit123." "0,1"
bitfld.long 0x10 2. "LOCK_STICKY_BIT122,Lock sticky bit122." "0,1"
newline
bitfld.long 0x10 1. "LOCK_STICKY_BIT121,Lock sticky bit121." "0,1"
bitfld.long 0x10 0. "LOCK_STICKY_BIT120,Lock sticky bit120." "0,1"
line.long 0x14 "OTP_LOCK_STICKY_5,OTP Controller Lock Sticky Register5"
bitfld.long 0x14 29. "LOCK_STICKY_BIT179,Lock sticky bit179." "0,1"
bitfld.long 0x14 28. "LOCK_STICKY_BIT178,Lock sticky bit178." "0,1"
newline
bitfld.long 0x14 27. "LOCK_STICKY_BIT177,Lock sticky bit177." "0,1"
bitfld.long 0x14 26. "LOCK_STICKY_BIT176,Lock sticky bit176." "0,1"
newline
bitfld.long 0x14 25. "LOCK_STICKY_BIT175,Lock sticky bit175." "0,1"
bitfld.long 0x14 24. "LOCK_STICKY_BIT174,Lock sticky bit174." "0,1"
newline
bitfld.long 0x14 23. "LOCK_STICKY_BIT173,Lock sticky bit173." "0,1"
bitfld.long 0x14 22. "LOCK_STICKY_BIT172,Lock sticky bit172." "0,1"
newline
bitfld.long 0x14 21. "LOCK_STICKY_BIT171,Lock sticky bit171." "0,1"
bitfld.long 0x14 20. "LOCK_STICKY_BIT170,Lock sticky bit170." "0,1"
newline
bitfld.long 0x14 19. "LOCK_STICKY_BIT169,Lock sticky bit169." "0,1"
bitfld.long 0x14 18. "LOCK_STICKY_BIT168,Lock sticky bit168." "0,1"
newline
bitfld.long 0x14 17. "LOCK_STICKY_BIT167,Lock sticky bit167." "0,1"
bitfld.long 0x14 16. "LOCK_STICKY_BIT166,Lock sticky bit166." "0,1"
newline
bitfld.long 0x14 15. "LOCK_STICKY_BIT165,Lock sticky bit165." "0,1"
bitfld.long 0x14 14. "LOCK_STICKY_BIT164,Lock sticky bit164." "0,1"
newline
bitfld.long 0x14 13. "LOCK_STICKY_BIT163,Lock sticky bit163." "0,1"
bitfld.long 0x14 12. "LOCK_STICKY_BIT162,Lock sticky bit162." "0,1"
newline
bitfld.long 0x14 11. "LOCK_STICKY_BIT161,Lock sticky bit161." "0,1"
bitfld.long 0x14 10. "LOCK_STICKY_BIT160,Lock sticky bit160." "0,1"
newline
bitfld.long 0x14 9. "LOCK_STICKY_BIT159,Lock sticky bit159." "0,1"
bitfld.long 0x14 8. "LOCK_STICKY_BIT158,Lock sticky bit158." "0,1"
newline
bitfld.long 0x14 7. "LOCK_STICKY_BIT157,Lock sticky bit157." "0,1"
bitfld.long 0x14 6. "LOCK_STICKY_BIT156,Lock sticky bit156." "0,1"
newline
bitfld.long 0x14 5. "LOCK_STICKY_BIT155,Lock sticky bit155." "0,1"
bitfld.long 0x14 4. "LOCK_STICKY_BIT154,Lock sticky bit154." "0,1"
newline
bitfld.long 0x14 3. "LOCK_STICKY_BIT153,Lock sticky bit153." "0,1"
bitfld.long 0x14 2. "LOCK_STICKY_BIT152,Lock sticky bit152." "0,1"
newline
bitfld.long 0x14 1. "LOCK_STICKY_BIT151,Lock sticky bit151." "0,1"
bitfld.long 0x14 0. "LOCK_STICKY_BIT150,Lock sticky bit150." "0,1"
line.long 0x18 "OTP_LOCK_STICKY_6,OTP Controller Lock Sticky Register6"
bitfld.long 0x18 29. "LOCK_STICKY_BIT209,Lock sticky bit209." "0,1"
bitfld.long 0x18 28. "LOCK_STICKY_BIT208,Lock sticky bit208." "0,1"
newline
bitfld.long 0x18 27. "LOCK_STICKY_BIT207,Lock sticky bit207." "0,1"
bitfld.long 0x18 26. "LOCK_STICKY_BIT206,Lock sticky bit206." "0,1"
newline
bitfld.long 0x18 25. "LOCK_STICKY_BIT205,Lock sticky bit205." "0,1"
bitfld.long 0x18 24. "LOCK_STICKY_BIT204,Lock sticky bit204." "0,1"
newline
bitfld.long 0x18 23. "LOCK_STICKY_BIT203,Lock sticky bit203." "0,1"
bitfld.long 0x18 22. "LOCK_STICKY_BIT202,Lock sticky bit202." "0,1"
newline
bitfld.long 0x18 21. "LOCK_STICKY_BIT201,Lock sticky bit201." "0,1"
bitfld.long 0x18 20. "LOCK_STICKY_BIT200,Lock sticky bit200." "0,1"
newline
bitfld.long 0x18 19. "LOCK_STICKY_BIT199,Lock sticky bit199." "0,1"
bitfld.long 0x18 18. "LOCK_STICKY_BIT198,Lock sticky bit198." "0,1"
newline
bitfld.long 0x18 17. "LOCK_STICKY_BIT197,Lock sticky bit197." "0,1"
bitfld.long 0x18 16. "LOCK_STICKY_BIT196,Lock sticky bit196." "0,1"
newline
bitfld.long 0x18 15. "LOCK_STICKY_BIT195,Lock sticky bit195." "0,1"
bitfld.long 0x18 14. "LOCK_STICKY_BIT194,Lock sticky bit194." "0,1"
newline
bitfld.long 0x18 13. "LOCK_STICKY_BIT193,Lock sticky bit193." "0,1"
bitfld.long 0x18 12. "LOCK_STICKY_BIT192,Lock sticky bit192." "0,1"
newline
bitfld.long 0x18 11. "LOCK_STICKY_BIT191,Lock sticky bit191." "0,1"
bitfld.long 0x18 10. "LOCK_STICKY_BIT190,Lock sticky bit190." "0,1"
newline
bitfld.long 0x18 9. "LOCK_STICKY_BIT189,Lock sticky bit189." "0,1"
bitfld.long 0x18 8. "LOCK_STICKY_BIT188,Lock sticky bit188." "0,1"
newline
bitfld.long 0x18 7. "LOCK_STICKY_BIT187,Lock sticky bit187." "0,1"
bitfld.long 0x18 6. "LOCK_STICKY_BIT186,Lock sticky bit186." "0,1"
newline
bitfld.long 0x18 5. "LOCK_STICKY_BIT185,Lock sticky bit185." "0,1"
bitfld.long 0x18 4. "LOCK_STICKY_BIT184,Lock sticky bit184." "0,1"
newline
bitfld.long 0x18 3. "LOCK_STICKY_BIT183,Lock sticky bit183." "0,1"
bitfld.long 0x18 2. "LOCK_STICKY_BIT182,Lock sticky bit182." "0,1"
newline
bitfld.long 0x18 1. "LOCK_STICKY_BIT181,Lock sticky bit181." "0,1"
bitfld.long 0x18 0. "LOCK_STICKY_BIT180,Lock sticky bit180." "0,1"
line.long 0x1C "OTP_LOCK_STICKY_7,OTP Controller Lock Sticky Register7"
bitfld.long 0x1C 29. "LOCK_STICKY_BIT239,Lock sticky bit239." "0,1"
bitfld.long 0x1C 28. "LOCK_STICKY_BIT238,Lock sticky bit238." "0,1"
newline
bitfld.long 0x1C 27. "LOCK_STICKY_BIT237,Lock sticky bit237." "0,1"
bitfld.long 0x1C 26. "LOCK_STICKY_BIT236,Lock sticky bit236." "0,1"
newline
bitfld.long 0x1C 25. "LOCK_STICKY_BIT235,Lock sticky bit235." "0,1"
bitfld.long 0x1C 24. "LOCK_STICKY_BIT234,Lock sticky bit234." "0,1"
newline
bitfld.long 0x1C 23. "LOCK_STICKY_BIT233,Lock sticky bit233." "0,1"
bitfld.long 0x1C 22. "LOCK_STICKY_BIT232,Lock sticky bit232." "0,1"
newline
bitfld.long 0x1C 21. "LOCK_STICKY_BIT231,Lock sticky bit231." "0,1"
bitfld.long 0x1C 20. "LOCK_STICKY_BIT230,Lock sticky bit230." "0,1"
newline
bitfld.long 0x1C 19. "LOCK_STICKY_BIT229,Lock sticky bi229." "0,1"
bitfld.long 0x1C 18. "LOCK_STICKY_BIT228,Lock sticky bit228." "0,1"
newline
bitfld.long 0x1C 17. "LOCK_STICKY_BIT227,Lock sticky bit227." "0,1"
bitfld.long 0x1C 16. "LOCK_STICKY_BIT226,Lock sticky bit226." "0,1"
newline
bitfld.long 0x1C 15. "LOCK_STICKY_BIT225,Lock sticky bit225." "0,1"
bitfld.long 0x1C 14. "LOCK_STICKY_BIT224,Lock sticky bit224." "0,1"
newline
bitfld.long 0x1C 13. "LOCK_STICKY_BIT223,Lock sticky bit223." "0,1"
bitfld.long 0x1C 12. "LOCK_STICKY_BIT222,Lock sticky bit222." "0,1"
newline
bitfld.long 0x1C 11. "LOCK_STICKY_BIT221,Lock sticky bit221." "0,1"
bitfld.long 0x1C 10. "LOCK_STICKY_BIT220,Lock sticky bit220." "0,1"
newline
bitfld.long 0x1C 9. "LOCK_STICKY_BIT219,Lock sticky bit219." "0,1"
bitfld.long 0x1C 8. "LOCK_STICKY_BIT218,Lock sticky bit218." "0,1"
newline
bitfld.long 0x1C 7. "LOCK_STICKY_BIT217,Lock sticky bit217." "0,1"
bitfld.long 0x1C 6. "LOCK_STICKY_BIT216,Lock sticky bit216." "0,1"
newline
bitfld.long 0x1C 5. "LOCK_STICKY_BIT215,Lock sticky bit215." "0,1"
bitfld.long 0x1C 4. "LOCK_STICKY_BIT214,Lock sticky bit214." "0,1"
newline
bitfld.long 0x1C 3. "LOCK_STICKY_BIT213,Lock sticky bit213." "0,1"
bitfld.long 0x1C 2. "LOCK_STICKY_BIT212,Lock sticky bit212." "0,1"
newline
bitfld.long 0x1C 1. "LOCK_STICKY_BIT211,Lock sticky bit211." "0,1"
bitfld.long 0x1C 0. "LOCK_STICKY_BIT210,Lock sticky bit210." "0,1"
line.long 0x20 "OTP_LOCK_STICKY_8,OTP Controller Lock Sticky Register8"
bitfld.long 0x20 29. "LOCK_STICKY_BIT269,Lock sticky bit269." "0,1"
bitfld.long 0x20 28. "LOCK_STICKY_BIT268,Lock sticky bit268." "0,1"
newline
bitfld.long 0x20 27. "LOCK_STICKY_BIT267,Lock sticky bit267." "0,1"
bitfld.long 0x20 26. "LOCK_STICKY_BIT266,Lock sticky bit266." "0,1"
newline
bitfld.long 0x20 25. "LOCK_STICKY_BIT265,Lock sticky bit265." "0,1"
bitfld.long 0x20 24. "LOCK_STICKY_BIT264,Lock sticky bit264." "0,1"
newline
bitfld.long 0x20 23. "LOCK_STICKY_BIT263,Lock sticky bit263." "0,1"
bitfld.long 0x20 22. "LOCK_STICKY_BIT262,Lock sticky bit262." "0,1"
newline
bitfld.long 0x20 21. "LOCK_STICKY_BIT261,Lock sticky bit261." "0,1"
bitfld.long 0x20 20. "LOCK_STICKY_BIT260,Lock sticky bit260." "0,1"
newline
bitfld.long 0x20 19. "LOCK_STICKY_BIT259,Lock sticky bit259." "0,1"
bitfld.long 0x20 18. "LOCK_STICKY_BIT258,Lock sticky bit258." "0,1"
newline
bitfld.long 0x20 17. "LOCK_STICKY_BIT257,Lock sticky bit257." "0,1"
bitfld.long 0x20 16. "LOCK_STICKY_BIT256,Lock sticky bit256." "0,1"
newline
bitfld.long 0x20 15. "LOCK_STICKY_BIT255,Lock sticky bit255." "0,1"
bitfld.long 0x20 14. "LOCK_STICKY_BIT254,Lock sticky bit254." "0,1"
newline
bitfld.long 0x20 13. "LOCK_STICKY_BIT253,Lock sticky bit253." "0,1"
bitfld.long 0x20 12. "LOCK_STICKY_BIT252,Lock sticky bit252." "0,1"
newline
bitfld.long 0x20 11. "LOCK_STICKY_BIT251,Lock sticky bit251." "0,1"
bitfld.long 0x20 10. "LOCK_STICKY_BIT250,Lock sticky bit250." "0,1"
newline
bitfld.long 0x20 9. "LOCK_STICKY_BIT249,Lock sticky bit249." "0,1"
bitfld.long 0x20 8. "LOCK_STICKY_BIT248,Lock sticky bit248." "0,1"
newline
bitfld.long 0x20 7. "LOCK_STICKY_BIT247,Lock sticky bit247." "0,1"
bitfld.long 0x20 6. "LOCK_STICKY_BIT246,Lock sticky bit246." "0,1"
newline
bitfld.long 0x20 5. "LOCK_STICKY_BIT245,Lock sticky bit245." "0,1"
bitfld.long 0x20 4. "LOCK_STICKY_BIT244,Lock sticky bit244." "0,1"
newline
bitfld.long 0x20 3. "LOCK_STICKY_BIT243,Lock sticky bit243." "0,1"
bitfld.long 0x20 2. "LOCK_STICKY_BIT242,Lock sticky bit242." "0,1"
newline
bitfld.long 0x20 1. "LOCK_STICKY_BIT241,Lock sticky bit241." "0,1"
bitfld.long 0x20 0. "LOCK_STICKY_BIT240,Lock sticky bit240." "0,1"
line.long 0x24 "OTP_LOCK_STICKY_9,OTP Controller Lock Sticky Register9"
bitfld.long 0x24 29. "LOCK_STICKY_BIT299,Lock sticky bit299." "0,1"
bitfld.long 0x24 28. "LOCK_STICKY_BIT298,Lock sticky bit298." "0,1"
newline
bitfld.long 0x24 27. "LOCK_STICKY_BIT297,Lock sticky bit297." "0,1"
bitfld.long 0x24 26. "LOCK_STICKY_BIT296,Lock sticky bit296." "0,1"
newline
bitfld.long 0x24 25. "LOCK_STICKY_BIT295,Lock sticky bit295." "0,1"
bitfld.long 0x24 24. "LOCK_STICKY_BIT294,Lock sticky bit294." "0,1"
newline
bitfld.long 0x24 23. "LOCK_STICKY_BIT293,Lock sticky bit293." "0,1"
bitfld.long 0x24 22. "LOCK_STICKY_BIT292,Lock sticky bit292." "0,1"
newline
bitfld.long 0x24 21. "LOCK_STICKY_BIT291,Lock sticky bit291." "0,1"
bitfld.long 0x24 20. "LOCK_STICKY_BIT290,Lock sticky bit290." "0,1"
newline
bitfld.long 0x24 19. "LOCK_STICKY_BIT289,Lock sticky bit289." "0,1"
bitfld.long 0x24 18. "LOCK_STICKY_BIT288,Lock sticky bit288." "0,1"
newline
bitfld.long 0x24 17. "LOCK_STICKY_BIT287,Lock sticky bit287." "0,1"
bitfld.long 0x24 16. "LOCK_STICKY_BIT286,Lock sticky bit286." "0,1"
newline
bitfld.long 0x24 15. "LOCK_STICKY_BIT285,Lock sticky bit285." "0,1"
bitfld.long 0x24 14. "LOCK_STICKY_BIT284,Lock sticky bit284." "0,1"
newline
bitfld.long 0x24 13. "LOCK_STICKY_BIT283,Lock sticky bit283." "0,1"
bitfld.long 0x24 12. "LOCK_STICKY_BIT282,Lock sticky bit282." "0,1"
newline
bitfld.long 0x24 11. "LOCK_STICKY_BIT281,Lock sticky bit281." "0,1"
bitfld.long 0x24 10. "LOCK_STICKY_BIT280,Lock sticky bit280." "0,1"
newline
bitfld.long 0x24 9. "LOCK_STICKY_BIT279,Lock sticky bit279." "0,1"
bitfld.long 0x24 8. "LOCK_STICKY_BIT278,Lock sticky bit278." "0,1"
newline
bitfld.long 0x24 7. "LOCK_STICKY_BIT277,Lock sticky bit277." "0,1"
bitfld.long 0x24 6. "LOCK_STICKY_BIT276,Lock sticky bit276." "0,1"
newline
bitfld.long 0x24 5. "LOCK_STICKY_BIT275,Lock sticky bit275." "0,1"
bitfld.long 0x24 4. "LOCK_STICKY_BIT274,Lock sticky bit274." "0,1"
newline
bitfld.long 0x24 3. "LOCK_STICKY_BIT273,Lock sticky bit273." "0,1"
bitfld.long 0x24 2. "LOCK_STICKY_BIT272,Lock sticky bit272." "0,1"
newline
bitfld.long 0x24 1. "LOCK_STICKY_BIT271,Lock sticky bit271." "0,1"
bitfld.long 0x24 0. "LOCK_STICKY_BIT270,Lock sticky bit270." "0,1"
line.long 0x28 "OTP_LOCK_STICKY_10,OTP Controller Lock Sticky Register10"
bitfld.long 0x28 29. "LOCK_STICKY_BIT329,Lock sticky bit329." "0,1"
bitfld.long 0x28 28. "LOCK_STICKY_BIT328,Lock sticky bit328." "0,1"
newline
bitfld.long 0x28 27. "LOCK_STICKY_BIT327,Lock sticky bit327." "0,1"
bitfld.long 0x28 26. "LOCK_STICKY_BIT326,Lock sticky bit326." "0,1"
newline
bitfld.long 0x28 25. "LOCK_STICKY_BIT325,Lock sticky bit325." "0,1"
bitfld.long 0x28 24. "LOCK_STICKY_BIT324,Lock sticky bit324." "0,1"
newline
bitfld.long 0x28 23. "LOCK_STICKY_BIT323,Lock sticky bit323." "0,1"
bitfld.long 0x28 22. "LOCK_STICKY_BIT322,Lock sticky bit322." "0,1"
newline
bitfld.long 0x28 21. "LOCK_STICKY_BIT321,Lock sticky bit321." "0,1"
bitfld.long 0x28 20. "LOCK_STICKY_BIT320,Lock sticky bit320." "0,1"
newline
bitfld.long 0x28 19. "LOCK_STICKY_BIT319,Lock sticky bit319." "0,1"
bitfld.long 0x28 18. "LOCK_STICKY_BIT318,Lock sticky bit318." "0,1"
newline
bitfld.long 0x28 17. "LOCK_STICKY_BIT317,Lock sticky bit317." "0,1"
bitfld.long 0x28 16. "LOCK_STICKY_BIT316,Lock sticky bit316." "0,1"
newline
bitfld.long 0x28 15. "LOCK_STICKY_BIT315,Lock sticky bit315." "0,1"
bitfld.long 0x28 14. "LOCK_STICKY_BIT314,Lock sticky bit314." "0,1"
newline
bitfld.long 0x28 13. "LOCK_STICKY_BIT313,Lock sticky bit313." "0,1"
bitfld.long 0x28 12. "LOCK_STICKY_BIT312,Lock sticky bit312." "0,1"
newline
bitfld.long 0x28 11. "LOCK_STICKY_BIT311,Lock sticky bit311." "0,1"
bitfld.long 0x28 10. "LOCK_STICKY_BIT310,Lock sticky bit310." "0,1"
newline
bitfld.long 0x28 9. "LOCK_STICKY_BIT309,Lock sticky bit309." "0,1"
bitfld.long 0x28 8. "LOCK_STICKY_BIT308,Lock sticky bit308." "0,1"
newline
bitfld.long 0x28 7. "LOCK_STICKY_BIT307,Lock sticky bit307." "0,1"
bitfld.long 0x28 6. "LOCK_STICKY_BIT306,Lock sticky bit306." "0,1"
newline
bitfld.long 0x28 5. "LOCK_STICKY_BIT305,Lock sticky bit305." "0,1"
bitfld.long 0x28 4. "LOCK_STICKY_BIT304,Lock sticky bit304." "0,1"
newline
bitfld.long 0x28 3. "LOCK_STICKY_BIT303,Lock sticky bit303." "0,1"
bitfld.long 0x28 2. "LOCK_STICKY_BIT302,Lock sticky bit302." "0,1"
newline
bitfld.long 0x28 1. "LOCK_STICKY_BIT301,Lock sticky bit301." "0,1"
bitfld.long 0x28 0. "LOCK_STICKY_BIT300,Lock sticky bit300." "0,1"
line.long 0x2C "OTP_LOCK_STICKY_11,OTP Controller Lock Sticky Register11"
bitfld.long 0x2C 4. "LOCK_STICKY_BIT334,Lock sticky bit334." "0,1"
bitfld.long 0x2C 3. "LOCK_STICKY_BIT333,Lock sticky bit333." "0,1"
newline
bitfld.long 0x2C 2. "LOCK_STICKY_BIT332,Lock sticky bit332." "0,1"
bitfld.long 0x2C 1. "LOCK_STICKY_BIT331,Lock sticky bit331." "0,1"
newline
bitfld.long 0x2C 0. "LOCK_STICKY_BIT330,Lock sticky bit330." "0,1"
tree.end
tree "OCOTP_ADAPTER (On-Chip One-Time Programmable Adapter)"
base ad:0x4000B000
group.word 0x200++0x1
line.word 0x0 "OTP_SPARE0_REG,OTP_SPARE0_REG"
hexmask.word 0x0 0.--15. 1. "OTP_SPARE0_REG,Spare register for future ECOs HW default is 0x0000"
group.word 0x204++0x1
line.word 0x0 "OTP_SPARE1_REG,OTP_SPARE1_REG"
hexmask.word 0x0 0.--15. 1. "OTP_SPARE1_REG,Spare register for future ECOs HW default is 0xFFFF"
rgroup.word 0x218++0x1
line.word 0x0 "OTP_TEST_STATUS_REG,OTP_TEST_STATUS_REG"
bitfld.word 0x0 2. "SECURITY_BIT,Security Fuse Status bit (READ ONLY This bit is for DFT/ATE testing use). If Security Fuse bit was set that 67-bits line is write protected forever it cannot reverse back even after por." "0,1"
bitfld.word 0x0 0. "ATE_TEST_BIT,ATE Test Status bit (READ ONLY These bits are for DFT/ATE testing use)." "0,1"
group.word 0x21C++0x1
line.word 0x0 "OTP_ADDR_REG,OTP_ADDR_REG"
hexmask.word 0x0 0.--9. 1. "OTP_ADDR,The otp_addr is composed of Bank select[16:13](there are only 4 physical banks) and row address[12:7] the address will select a row or a line of a bank that contains the ATE test bit and the security bit."
group.word 0x220++0x1
line.word 0x0 "OTP_CTRL0_REG,OTP_CTRL0_REG"
rbitfld.word 0x0 15. "CTRL_CMD_DONE,otp access command done." "0,1"
hexmask.word.byte 0x0 8.--11. 1. "MACRO_TEST,S/W control bits to TEST[3:0] inputs."
rbitfld.word 0x0 7. "MACRO_RD_DONE,RD_DONE is status from the OTP bank (selected by otp_addr_reg[9:6])." "0,1"
group.word 0x224++0x1
line.word 0x0 "OTP_CTRL1_REG,OTP_CTRL1_REG"
hexmask.word.byte 0x0 8.--15. 1. "MACRO_MATCH,0: match code does not match."
bitfld.word 0x0 1. "OTP_PROG_SEQ_CODE_OTPMEM,Data input used by SW to program the match code into all the OTP memories." "0,1"
bitfld.word 0x0 0. "OTP_PROG_SEQ_CODE_CLK_OTPMEM,Clock input used by SW to program the match code into all the OTP memories" "0,1"
group.word 0x228++0x1
line.word 0x0 "OTP_CMD_START_REG,OTP_CMD_START_REG"
hexmask.word.byte 0x0 4.--7. 1. "OTP_CMD,OTP access commands (the command execution finishes when the [ctrl_cmd_done] bit is set):"
bitfld.word 0x0 2.--3. "ADPT_READ_MODE,These two bits are used to set Normal Read or Margin_0 Read or Margin_1 Read from OCOTP Controller it is used by DFT/ATE for testing purpose." "0,1,2,3"
bitfld.word 0x0 0. "OTP_CMD_START,Write '1' to start otp access command execution and it also clears the [ctrl_cmd_done] bit." "0,1"
group.word 0x22C++0x1
line.word 0x0 "OTP_PARAM0_REG,OTP_PARAM0_REG"
bitfld.word 0x0 14.--15. "TRD_20NS_LOW,For 28nm. Read pulse width lower two bits(higher two bits are in OTP_PARAM2_REG[12:11]). The default value is based on 32MHz LSB clock." "0,1,2,3"
hexmask.word.byte 0x0 10.--13. 1. "TSQ_MINUS_TRD,Read data access time the value to enter is tSQ(70ns)-tRD. The default value is based on 32MHz LSB clock."
hexmask.word 0x0 0.--9. 1. "TPGM_2US,Specify the width of the programming pulse (in number of pclk cycle) the number depends on the pclk frequency and the pulse width requirement (OTP macro specifies between 2us up to 10us)."
group.word 0x230++0x1
line.word 0x0 "OTP_PARAM1_REG,OTP_PARAM1_REG"
hexmask.word.byte 0x0 11.--15. 1. "TSU_300NS,Specify setup time for few of the OTP control signals. The default value is based on 32MHz LSB clock."
hexmask.word 0x0 0.--10. 1. "TVHV_OFF_10US,Reserved VHV/V18 of the Adapter is controller by external SW register"
group.word 0x234++0x1
line.word 0x0 "OTP_PARAM2_REG,OTP_PARAM2_REG"
bitfld.word 0x0 11.--12. "TRD_20NS_HIGH,For 28nm Read pulse width higher two bits (lower two bits are in OTP_PARAM0_REG[15:14]). The default value is based on 32MHz LSB clock." "0,1,2,3"
hexmask.word 0x0 0.--10. 1. "TVHV_ON_10US,Reserved VHV/V18 of the Adapter is controller by external SW register"
group.word 0x240++0x1
line.word 0x0 "OTP_TESTBUS_SEL_REG,OTP_TESTBUS_SEL_REG"
hexmask.word.byte 0x0 0.--3. 1. "OTP_TESTBUS_SEL_REG,OTP Test Bus Select"
rgroup.word 0x244++0x1
line.word 0x0 "OTP_TESTBUS_REG,OTP_TESTBUS_REG"
hexmask.word 0x0 0.--15. 1. "OTP_TESTBUS,OTP Test Bus"
group.word 0x24C++0x1
line.word 0x0 "OTP_RST_B_REG,OTP_RST_B_REG"
hexmask.word 0x0 0.--15. 1. "OTP_RST_B,S/W reset bit to RST_B input of each OTP macro"
group.word 0x250++0x1
line.word 0x0 "OTP_POR_B_REG,OTP_POR_B_REG"
hexmask.word 0x0 0.--15. 1. "OTP_POR_B,S/W por bit to POR_B input of each OTP macro."
group.word 0x280++0x1
line.word 0x0 "OTP_ADPT_ECC_BASE_LINE_ADDR,OTP_ADPT_ECC_BASE_LINE_ADDR"
hexmask.word 0x0 0.--15. 1. "REG_ADPT_ECC_BASE_LINE_ADDR,Starting line number of the ECC code area for 4 OTP memory banks (HW Default=0xcc=d204)"
tree.end
tree "OSTIMER (OS Event Timer)"
base ad:0x4013B000
rgroup.long 0x0++0xF
line.long 0x0 "EVTIMERL,EVTIMER Low Register"
hexmask.long 0x0 0.--31. 1. "EVTIMER_COUNT_VALUE,EVTimer Count value"
line.long 0x4 "EVTIMERH,EVTIMER High Register"
hexmask.long 0x4 0.--31. 1. "EVTIMER_COUNT_VALUE,EVTimer Count value"
line.long 0x8 "CAPTURE_L,Local Capture Low Register for CPU"
hexmask.long 0x8 0.--31. 1. "CAPTURE_VALUE,EVTimer Capture value"
line.long 0xC "CAPTURE_H,Local Capture High Register for CPU"
hexmask.long 0xC 0.--31. 1. "CAPTURE_VALUE,EVTimer Capture value"
group.long 0x10++0x7
line.long 0x0 "MATCH_L,Local Match Low Register for CPU"
hexmask.long 0x0 0.--31. 1. "MATCH_VALUE,EVTimer Match value"
line.long 0x4 "MATCH_H,Local Match High Register for CPU"
hexmask.long 0x4 0.--31. 1. "MATCH_VALUE,EVTimer Match value"
group.long 0x1C++0x3
line.long 0x0 "OSEVENT_CTRL,OS Event Timer Control Register for CPU"
bitfld.long 0x0 2. "MATCH_WR_RDY,EVTimer Match Write Ready" "0,1"
bitfld.long 0x0 1. "OSTIMER_INTENA,Interrupt/Wake-up Request" "0: Interrupt/wake-up requests due to the..,1: An interrupt/wake-up request to the domain.."
bitfld.long 0x0 0. "OSTIMER_INTRFLAG,Interrupt Flag" "0,1"
tree.end
tree "PINT (Pin Interrupt and Pattern Match)"
base ad:0x40025000
group.long 0x0++0x7
line.long 0x0 "ISEL,Pin Interrupt Mode"
hexmask.long.byte 0x0 0.--7. 1. "PMODE,Interrupt mode"
line.long 0x4 "IENR,Pin Interrupt Level or Rising Edge Interrupt Enable"
hexmask.long.byte 0x4 0.--7. 1. "ENRL,Enable Interrupt"
wgroup.long 0x8++0x3
line.long 0x0 "SIENR,Pin Interrupt Level or Rising Edge Interrupt Set"
hexmask.long.byte 0x0 0.--7. 1. "SETENRL,Set bits in the IENR"
group.long 0xC++0x7
line.long 0x0 "CIENR,Pin Interrupt Level (Rising Edge Interrupt) Clear"
hexmask.long.byte 0x0 0.--7. 1. "CENRL,Clear bits in the IENR"
line.long 0x4 "IENF,Pin Interrupt Active Level or Falling Edge Interrupt Enable"
hexmask.long.byte 0x4 0.--7. 1. "ENAF,Enable Interrupt"
wgroup.long 0x14++0x7
line.long 0x0 "SIENF,Pin Interrupt Active Level or Falling Edge Interrupt Set"
hexmask.long.byte 0x0 0.--7. 1. "SETENAF,Set bits in the IENF"
line.long 0x4 "CIENF,Pin Interrupt Active Level or Falling Edge Interrupt Clear"
hexmask.long.byte 0x4 0.--7. 1. "CENAF,Clear bits in the IENF"
group.long 0x1C++0x17
line.long 0x0 "RISE,Pin Interrupt Rising Edge"
hexmask.long.byte 0x0 0.--7. 1. "RDET,Rising edge detect"
line.long 0x4 "FALL,Pin Interrupt Falling Edge"
hexmask.long.byte 0x4 0.--7. 1. "FDET,Falling edge detect"
line.long 0x8 "IST,Pin Interrupt Status"
hexmask.long.byte 0x8 0.--7. 1. "PSTAT,Pin interrupt status"
line.long 0xC "PMCTRL,Pattern Match Interrupt Control"
hexmask.long.byte 0xC 24.--31. 1. "PMAT,Pattern Matches"
bitfld.long 0xC 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true." "0: Disabled- RXEV output to the CPU is disabled.,1: Enabled- RXEV output to the CPU is enabled."
newline
bitfld.long 0xC 0. "SEL_PMATCH,Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function." "0: Pin interrupt- interrupts are driven in response..,1: Pattern match- interrupts are driven in response.."
line.long 0x10 "PMSRC,Pattern Match Interrupt Bit-Slice Source"
bitfld.long 0x10 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
newline
bitfld.long 0x10 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
newline
bitfld.long 0x10 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
newline
bitfld.long 0x10 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
bitfld.long 0x10 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0. Selects the pin selected in the..,1: Input 1. Selects the pin selected in the..,2: Input 2. Selects the pin selected in the..,3: Input 3. Selects the pin selected in the..,4: Input 4. Selects the pin selected in the..,5: Input 5. Selects the pin selected in the..,6: Input 6. Selects the pin selected in the..,7: Input 7. Selects the pin selected in the.."
line.long 0x14 "PMCFG,Pattern Match Interrupt Bit Slice Configuration"
bitfld.long 0x14 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
bitfld.long 0x14 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0." "0: Constant HIGH,1: Sticky rising edge. Match occurs if a rising..,2: Sticky falling edge. Match occurs if a falling..,3: Sticky rising or falling edge. Match occurs if..,4: High level. Match (for this bit slice) occurs..,5: Low level. Match occurs when there is a low..,6: Constant 0. This bit slice never contributes to..,7: Event. Non-sticky rising or falling edge. Match.."
newline
bitfld.long 0x14 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint." "0: No effect. Slice 6 is not an endpoint.,1: Endpoint. Slice 6 is the endpoint of a product.."
bitfld.long 0x14 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint." "0: No effect. Slice 5 is not an endpoint.,1: Endpoint. Slice 5 is the endpoint of a product.."
newline
bitfld.long 0x14 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint." "0: No effect. Slice 4 is not an endpoint.,1: Endpoint. Slice 4 is the endpoint of a product.."
bitfld.long 0x14 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint." "0: No effect. Slice 3 is not an endpoint.,1: Endpoint. Slice 3 is the endpoint of a product.."
newline
bitfld.long 0x14 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint." "0: No effect. Slice 2 is not an endpoint.,1: Endpoint. Slice 2 is the endpoint of a product.."
bitfld.long 0x14 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint." "0: No effect. Slice 1 is not an endpoint.,1: Endpoint. Slice 1 is the endpoint of a product.."
newline
bitfld.long 0x14 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint." "0: No effect. Slice 0 is not an endpoint.,1: Endpoint. Slice 0 is the endpoint of a product.."
tree.end
tree "PKC (Public Key Cryptography)"
base ad:0x40009000
rgroup.long 0x0++0x3
line.long 0x0 "PKC_STATUS,Status register"
bitfld.long 0x0 5.--6. "LOCKED,Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten." "0,1,2,3"
bitfld.long 0x0 3. "GOANY,Combined GO status flag: GOANY is set in case either PKC_CTRL." "0,1"
newline
bitfld.long 0x0 2. "ZERO,Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result of the calculation is equal zero." "0,1"
bitfld.long 0x0 1. "CARRY,Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case; - an addition or multiplication with addition operation has been executed and an overflow in the most significant bit has occured." "0,1"
newline
bitfld.long 0x0 0. "ACTIV,PKC active: ACTIV=1 signals that a calculation is in progress or about to start." "0,1"
group.long 0x4++0x7
line.long 0x0 "PKC_CTRL,Control register"
bitfld.long 0x0 10.--11. "REDMUL,Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor." "0,1,2,3"
bitfld.long 0x0 9. "CACHE_EN,Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer parameters is enabled." "0,1"
newline
bitfld.long 0x0 8. "CLRCACHE,Clear universal pointer cache: Invalidates the cache such that all previously fetched parameters are withdrawn and have to be fetched again via DMA accesses." "0,1"
bitfld.long 0x0 7. "GF2CONV,Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes." "0,1"
newline
bitfld.long 0x0 6. "GOU,Control bit to start pipe operation: If GOU is set PKC will start the pipe / layer2 operation (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch Operation'." "0,1"
bitfld.long 0x0 5. "GOM2,Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC pattern / layer1 operation using parameter set 2 (PKC_MODE2 PKC_XYPTR2 PKC_ZRPTR2 PKC_LEN2)." "?,?"
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bitfld.long 0x0 4. "GOM1,Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC pattern / layer1 operation using parameter set 1 (PKC_MODE1 PKC_XYPTR1 PKC_ZRPTR1 PKC_LEN1)." "?,1: If GOM1 is set PKC will start a MC pattern /.."
bitfld.long 0x0 3. "GOD2,Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will start a direct / layer0 operation using parameter set 2 (PKC_MODE2 PKC_XYPTR2 PKC_ZRPTR2 PKC_LEN2)." "?,?"
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bitfld.long 0x0 2. "GOD1,Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will start a direct / layer0 operation using parameter set 1 (PKC_MODE1 PKC_XYPTR1 PKC_ZRPTR1 PKC_LEN1)." "?,1: If GOD1 is set PKC will start a direct / layer0.."
bitfld.long 0x0 1. "STOP,Freeze PKC calculation: STOP=1 freezes all PKC activity incl." "0,1"
newline
bitfld.long 0x0 0. "RESET,PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation cannot be started and by which any ongoing calculation process is stopped." "0,1"
line.long 0x4 "PKC_CFG,Configuration register"
bitfld.long 0x4 10. "FMULNOISE,Noise feature not available in this version (flag is don't care)." "0,1"
bitfld.long 0x4 9. "ALPNOISE,Noise feature not available in this version (flag is don't care)." "0,1"
newline
bitfld.long 0x4 8. "SBXNOISE,Noise feature not available in this version (flag is don't care)." "0,1"
bitfld.long 0x4 5.--7. "RNDDLY,Random delay feature not available in this version (flag is don't care)." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "REDMULNOISE,Noise in reduced multiplier mode feature not available in this version (flag is don't care)." "0,1"
bitfld.long 0x4 3. "CLKRND,Clock randomization feature not available in this version (flag is don't care)." "0,1"
newline
bitfld.long 0x4 2. "RFU2,RFU" "0,1"
bitfld.long 0x4 1. "RFU1,RFU" "0,1"
newline
bitfld.long 0x4 0. "IDLEOP,Idle operation feature not available in this version (flag is don't care)." "0,1"
group.long 0x10++0x1F
line.long 0x0 "PKC_MODE1,Mode register. parameter set 1"
hexmask.long.byte 0x0 0.--7. 1. "MODE,Calculation Mode / MC Start address:; Calculation mode of direct calculation (layer0) are listed in a table in Section 'PKC arithmetic unit (layer 0)'."
line.long 0x4 "PKC_XYPTR1,X+Y pointer register. parameter set 1"
hexmask.long.word 0x4 16.--31. 1. "YPTR,Start address of Y operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL."
hexmask.long.word 0x4 0.--15. 1. "XPTR,Start address of X operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL."
line.long 0x8 "PKC_ZRPTR1,Z+R pointer register. parameter set 1"
hexmask.long.word 0x8 16.--31. 1. "RPTR,Start address of R result in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL."
hexmask.long.word 0x8 0.--15. 1. "ZPTR,Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST:; If ZPTR is used as address pointer the least significant bits are ignored depending on PKC_CTRL."
line.long 0xC "PKC_LEN1,Length register. parameter set 1"
hexmask.long.word 0xC 16.--31. 1. "MCLEN,Loop counter for microcode pattern: MCLEN defines the length of the loop counter that can be used in layer1 calculation mode e."
hexmask.long.word 0xC 0.--15. 1. "LEN,Operand length: LEN defines the length of the operands and the result in bytes."
line.long 0x10 "PKC_MODE2,Mode register. parameter set 2"
hexmask.long.byte 0x10 0.--7. 1. "MODE,Calculation Mode / MC Start address:; Calculation mode of direct calculation (layer0) are listed in a table in Section 'PKC arithmetic unit (layer 0)'."
line.long 0x14 "PKC_XYPTR2,X+Y pointer register. parameter set 2"
hexmask.long.word 0x14 16.--31. 1. "YPTR,Start address of Y operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL."
hexmask.long.word 0x14 0.--15. 1. "XPTR,Start address of X operand in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL."
line.long 0x18 "PKC_ZRPTR2,Z+R pointer register. parameter set 2"
hexmask.long.word 0x18 16.--31. 1. "RPTR,Start address of R result in PKCRAM with byte granularity: Least significant bits are ignored depending on PKC_CTRL."
hexmask.long.word 0x18 0.--15. 1. "ZPTR,Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST:; If ZPTR is used as address pointer the least significant bits are ignored depending on PKC_CTRL."
line.long 0x1C "PKC_LEN2,Length register. parameter set 2"
hexmask.long.word 0x1C 16.--31. 1. "MCLEN,Loop counter for microcode pattern: MCLEN defines the length of the loop counter that can be used in layer1 calculation mode e."
hexmask.long.word 0x1C 0.--15. 1. "LEN,Operand length: LEN defines the length of the operands and the result in bytes."
group.long 0x40++0xB
line.long 0x0 "PKC_UPTR,Universal pointer FUP program"
hexmask.long 0x0 0.--31. 1. "PTR,Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting a universal pointer PKC calculation (layer2) via PKC_CTRL."
line.long 0x4 "PKC_UPTRT,Universal pointer FUP table"
hexmask.long 0x4 0.--31. 1. "PTR,Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a universal pointer PKC calculation (layer2) via PKC_CTRL."
line.long 0x8 "PKC_ULEN,Universal pointer length"
hexmask.long.byte 0x8 0.--7. 1. "LEN,Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries shall be processed for one layer2 calculation started via PKC_CTRL."
group.long 0x50++0x3
line.long 0x0 "PKC_MCDATA,MC pattern data interface"
hexmask.long 0x0 0.--31. 1. "MCDATA,Microcode read/write data: This IP version does not support flexible MC patterns (only hard coded ones)."
rgroup.long 0x60++0x3
line.long 0x0 "PKC_VERSION,PKC version register"
hexmask.long.byte 0x0 12.--19. 1. "MCRECONF_SIZE,Size of reconfigurable MC table in bytes"
bitfld.long 0x0 11. "SBX3AVAIL,SBX3 operation is available" "0,1"
newline
bitfld.long 0x0 10. "SBX2AVAIL,SBX2 operation is available" "0,1"
bitfld.long 0x0 9. "SBX1AVAIL,SBX1 operation is available" "0,1"
newline
bitfld.long 0x0 8. "SBX0AVAIL,SBX0 operation is available" "0,1"
bitfld.long 0x0 6.--7. "PARAMNUM,Number of parameter sets for real calculation" "0,1,2,3"
newline
bitfld.long 0x0 5. "GF2AVAIL,GF2 calculation modes are available" "0,1"
bitfld.long 0x0 4. "UPCACHEAVAIL,UP cache is available" "0,1"
newline
bitfld.long 0x0 3. "UPAVAIL,UP feature (layer2 calculation) is available" "0,1"
bitfld.long 0x0 2. "MCAVAIL,MC feature (layer1 calculation) is available" "0,1"
newline
bitfld.long 0x0 0.--1. "MULSIZE,native multiplier size and operand granularity" "0,1,2,3"
wgroup.long 0xFB0++0x3
line.long 0x0 "PKC_SOFT_RST,Software reset"
bitfld.long 0x0 0. "SOFT_RST,Write 1 to reset module (0 has no effect)." "0,1"
rgroup.long 0xFC0++0x3
line.long 0x0 "PKC_ACCESS_ERR,Access Error"
bitfld.long 0x0 19. "UCRC,Error in layer2 CRC check" "0,1"
bitfld.long 0x0 18. "CTRL,Error in PKC software control" "0,1"
newline
bitfld.long 0x0 17. "FDET,Error due to error detection circuitry" "0,1"
bitfld.long 0x0 16. "PKCC,Error in PKC coprocessor kernel" "0,1"
newline
bitfld.long 0x0 10. "AHB,AHB Error: invalid AHB access Layer2 Only" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "APB_MASTER,APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)"
newline
bitfld.long 0x0 1. "APB_WRGMD,APB Error: Wrong access mode" "0,1"
bitfld.long 0x0 0. "APB_NOTAV,APB Error: address not available" "0,1"
wgroup.long 0xFC4++0x3
line.long 0x0 "PKC_ACCESS_ERR_CLR,Clear Access Error"
bitfld.long 0x0 0. "ERR_CLR,Write 1 to reset PKC_ACCESS_ERR SFR." "0,1"
wgroup.long 0xFD8++0x7
line.long 0x0 "PKC_INT_CLR_ENABLE,Interrupt enable clear"
bitfld.long 0x0 0. "EN_PDONE,Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE." "0,1"
line.long 0x4 "PKC_INT_SET_ENABLE,Interrupt enable set"
bitfld.long 0x4 0. "EN_PDONE,Write to set PDONE interrupt enable flag (PKC_INT_ENABLE." "0,1"
rgroup.long 0xFE0++0x7
line.long 0x0 "PKC_INT_STATUS,Interrupt status"
bitfld.long 0x0 0. "INT_PDONE,End-of-computation status flag: INT_PDONE is set after EACH single PKC layer0 or layer1 calculation." "0,1"
line.long 0x4 "PKC_INT_ENABLE,Interrupt enable"
bitfld.long 0x4 0. "EN_PDONE,PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time PKC_INT_STATUS." "0,1"
wgroup.long 0xFE8++0x7
line.long 0x0 "PKC_INT_CLR_STATUS,Interrupt status clear"
bitfld.long 0x0 0. "INT_PDONE,Write to clear End-of-computation status flag (PKC_INT_STATUS." "0,1"
line.long 0x4 "PKC_INT_SET_STATUS,Interrupt status set"
bitfld.long 0x4 0. "INT_PDONE,Write to set End-of-computation status flag (PKC_INT_STATUS." "0,1"
rgroup.long 0xFFC++0x3
line.long 0x0 "PKC_MODULE_ID,Module ID"
hexmask.long.word 0x0 16.--31. 1. "ID,Module ID"
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision"
hexmask.long.byte 0x0 0.--7. 1. "SIZE,Address space of the IP"
tree.end
tree "PMU (Power Management Unit)"
base ad:0x40031000
group.long 0x0++0x3
line.long 0x0 "PWR_MODE,Power mode control register"
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode switch" "0: PM0 or PM1,1: no description available,2: no description available,3: no description available"
rgroup.long 0x4++0x3
line.long 0x0 "PWR_MODE_STATUS,Power mode status register"
bitfld.long 0x0 0.--1. "PWR_MODE_STATUS,Power mode status" "0: PM0 or PM1,1: no description available,2: no description available,3: no description available"
group.long 0x8++0x3
line.long 0x0 "SYS_RST_EN,sys reset enable resister"
bitfld.long 0x0 5. "ITRC_EN,itrc_chip rst enable" "0,1"
newline
bitfld.long 0x0 4. "CODE_WDT_EN,code_wdt rst enable" "0,1"
newline
bitfld.long 0x0 3. "AP_SYSRESETREQ_EN,ap_sysresetreq rst enable" "0,1"
newline
bitfld.long 0x0 2. "WDT_EN,wdt rst enable" "0,1"
newline
bitfld.long 0x0 1. "CM33_LOCKUP_EN,cm33_lockup reset enable" "0,1"
newline
bitfld.long 0x0 0. "CM33_SYSRESETREQ_EN,cm33_sysresetreq reset enable" "0,1"
rgroup.long 0xC++0x3
line.long 0x0 "SYS_RST_STATUS,Reset status Register"
bitfld.long 0x0 6. "SW_RESETB_SCANTEST,sw_resetb_scantest Reset" "0: reset cause is not sw_resetb_scantest reset,1: reset cause is sw_resetb_scantest reset"
newline
bitfld.long 0x0 5. "ITRC_CHIP_RST,ITRC_CHIP Reset" "0: reset cause is not itrc chip reset,1: reset cause is itrc chip reset"
newline
bitfld.long 0x0 4. "CODE_WDT_RST,CODE_WDT Reset" "0: reset cause is not code watchdog timer,1: reset cause is code watchdog timer"
newline
bitfld.long 0x0 3. "AP_SYSRESETREQ,Debug mailbox Reset" "0: reset cause is not ap_sysresetreq,1: reset cause is ap_sysresetreq"
newline
bitfld.long 0x0 2. "WDT_RST,WDT Reset" "0: reset cause is not watchdog timer,1: reset cause is watchdog timer"
newline
bitfld.long 0x0 1. "CM33_LOCKUP,CM4 Lockup" "0: reset cause is not lockup,1: reset cause is lockup"
newline
bitfld.long 0x0 0. "CM33_SYSRESETREQ,CM4 System software reset request" "0: reset cause is not system software reset request,1: reset cause is system software reset request"
group.long 0x10++0xB
line.long 0x0 "SYS_RST_CLR,sys reset clear resister"
bitfld.long 0x0 6. "SW_RESETB_SCANTEST_CLR,sw_resetb_scantest rst clear" "0,1"
newline
bitfld.long 0x0 5. "ITRC_CLR,itrc chip rst clear" "0,1"
newline
bitfld.long 0x0 4. "CODE_WDT_CLR,code_wdt rst clear" "0,1"
newline
bitfld.long 0x0 3. "AP_SYSRESETREQ_CLR,ap_sysresetreq rst clear" "0,1"
newline
bitfld.long 0x0 2. "WDT_CLR,wdt rst clear" "0,1"
newline
bitfld.long 0x0 1. "CM33_LOCKUP_CLR,cm33_lockup reset clear" "0,1"
newline
bitfld.long 0x0 0. "CM33_SYSRESETREQ_CLR,cm33_sysresetreq reset clear" "0,1"
line.long 0x4 "WAKEUP_LEVEL,Wakeup Level Register"
bitfld.long 0x4 1. "PIN1,0 = connect to gound wake up" "0: connect to gound wake up,1: connect to VDDO wake up"
newline
bitfld.long 0x4 0. "PIN0,0 = connect to gound wake up" "0: connect to gound wake up,1: connect to VDDO wake up"
line.long 0x8 "WAKEUP_MASK,Wakeup Mask Interrupt Register"
bitfld.long 0x8 9. "BOD1_MASK,bod1 Wakeup Mask" "0: mask bod1 wakeup interrupt,1: unmask bod1 wakeup interrupt"
newline
bitfld.long 0x8 7.--8. "BLE_MASK,BLE Wakeup Mask" "0: mask BLE wakeup interrupt,1: unmask BLE wakeup interrupt,?,?"
newline
bitfld.long 0x8 5.--6. "WL_MASK,WLAN Wakeup Mask" "0: mask WLAN wakeup interrupt,1: unmask WLAN wakeup interrupt,?,?"
newline
bitfld.long 0x8 4. "CAPT_MASK,capture pulse Wakeup Mask" "0: mask capt wakeup interrupt,1: unmask capt wakeup interrupt"
newline
bitfld.long 0x8 2. "RTC_MASK,RTC Wakeup Mask" "0: mask RTC wakeup interrupt,1: unmask RTC wakeup interrupt"
newline
bitfld.long 0x8 1. "PIN1_MASK,Pin1 Wakeup Mask" "0: mask pin1 wakeup interrupt,1: unmask pin1 wakeup interrupt"
newline
bitfld.long 0x8 0. "PIN0_MASK,Pin0 Wakeup Mask" "0: mask pin0 wakeup interrupt,1: unmask pin0 wakeup interrupt"
rgroup.long 0x1C++0x3
line.long 0x0 "WAKEUP_STATUS,Wakeup status register"
bitfld.long 0x0 9. "BOD1,bod1 wakeup status" "0,1"
newline
bitfld.long 0x0 7.--8. "BLE,BLE interrupt wakeup status" "0,1,2,3"
newline
bitfld.long 0x0 5.--6. "WL,WL interrupt wakeup status" "0,1,2,3"
newline
bitfld.long 0x0 4. "CAPT,capt interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 2. "RTC,RTC wakeup status" "0,1"
newline
bitfld.long 0x0 1. "PIN1,External Pin1 wakeup status" "0,1"
newline
bitfld.long 0x0 0. "PIN0,External Pin0 wakeup status" "0,1"
group.long 0x20++0xB
line.long 0x0 "WAKE_SRC_CLR,Wake up source clear register"
bitfld.long 0x0 9. "BOD1_CLR,Clear bod1 interrupt request" "0,1"
newline
bitfld.long 0x0 7.--8. "BLE_CLR,Clear BLE interrupt request" "0,1,2,3"
newline
bitfld.long 0x0 5.--6. "WL_CLR,Clear WL interrupt request" "0,1,2,3"
newline
bitfld.long 0x0 4. "CAPT_CLR,Clear capture interrupt request" "0,1"
newline
bitfld.long 0x0 2. "RTC_CLR,Clear RTC interrupt request" "0,1"
newline
bitfld.long 0x0 1. "PIN1_CLR,Clear Pin1 interrupt request" "0,1"
newline
bitfld.long 0x0 0. "PIN0_CLR,Clear Pin0 interrupt request" "0,1"
line.long 0x4 "WL_BLE_WAKEUP_DONE,Wake up done register"
bitfld.long 0x4 8. "BLE_DONE_BIT1,BLE wake up MCI done signal" "0,1"
newline
bitfld.long 0x4 7. "BLE_DONE_BIT0,BLE wake up MCI done signal" "0,1"
newline
bitfld.long 0x4 6. "WL_DONE_BIT1,WL wake up MCI done bit1 signal" "0,1"
newline
bitfld.long 0x4 5. "WL_DONE_BIT0,WL wake up MCI done bit0 signal" "0,1"
line.long 0x8 "CAU_SLP_CTRL,CAU sleep clock control register"
bitfld.long 0x8 2. "CAU_SOC_SLP_CG,gate cau_soc_slp_ref_gen_clk" "0,1"
newline
rbitfld.long 0x8 1. "SOC_SLP_RDY,CAU_SOC_SLP_REF_GEN_CLK is ready" "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "SOC_CIU_RDY,soc_ciu_rdy register"
bitfld.long 0x0 2. "VAL,indicate soc IO strap finish boot rom can read strap value" "0,1"
group.long 0x30++0x7
line.long 0x0 "CAPT_PULSE,pulse in register"
bitfld.long 0x0 10. "CLK_SEL,0 choose 32k for slow capture 1 choose 3.84/4M for fast capture as functional clock" "0,1"
newline
bitfld.long 0x0 9. "IRQ_MSK,only mask the interrupt" "0,1"
newline
rbitfld.long 0x0 8. "IRQ_STATUS,interrupt status" "0,1"
newline
bitfld.long 0x0 7. "IRQ_CLR,clear the interrupt and wakeup" "0,1"
newline
bitfld.long 0x0 4.--6. "IC_WIDTH_CLK_CNT,Input Capture Filter Width only used when capture_slow_pulse_cnt_en=1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2.--3. "IC_EDGE_CLK_CNT,when capture_slow_pulse_cnt_en=1 indicate the trigger condition of counter 0: rising edge 1: falling edge ; others: both" "0: rising edge,1: falling edge,?,?"
newline
bitfld.long 0x0 1. "CAPTURE_FAST_PULSE_CNT_EN,enable signal" "0,1"
newline
bitfld.long 0x0 0. "CAPTURE_SLOW_PULSE_CNT_EN,enable signal" "0,1"
line.long 0x4 "CAPT_PULSE_BASE_VAL,capt_pulse_base_val"
hexmask.long 0x4 0.--31. 1. "CAPTURE_CNT_BASE_VAL,the counter reaches this register value interrupt will be generated"
rgroup.long 0x38++0x3
line.long 0x0 "CAPT_PULSE_VAL,capt_pulse_val"
hexmask.long 0x0 0.--31. 1. "CAPTURE_CNT_VAL,counter pulse value"
group.long 0x3C++0x3
line.long 0x0 "XTAL32K_CTRL,XTAL32k Control Register"
bitfld.long 0x0 12.--13. "X32K_DLY_SEL,32k Delay Select" "0,1,2,3"
newline
bitfld.long 0x0 11. "X32K_EN,Enable 32k oscillator" "0,1"
newline
bitfld.long 0x0 10. "X32K_EXT_OSC_EN,Enable external oscillator mode for outside clock" "0,1"
newline
bitfld.long 0x0 8.--9. "X32K_VDDXO_CNTL,Control VDDXO level" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "X32K_TMODE,Test mode enabling for 32k xtal ckt" "0,1,2,3"
newline
bitfld.long 0x0 3. "X32K_TEST_EN,Test enabling for 32k xtal ckt" "0,1"
newline
bitfld.long 0x0 1.--2. "X32K_STUP_ASSIST,Use startup assist ckt for 32 kHz xosc" "0,1,2,3"
newline
rbitfld.long 0x0 0. "X32K_RDY,Assert high when ready" "0,1"
group.long 0x44++0xF
line.long 0x0 "PMIP_BUCK_LVL,PMIP BUCK LEVEL"
hexmask.long.byte 0x0 24.--30. 1. "SLEEP_BUCK18_SEL,Select sleep mode output voltage for v18_aon VOUT = LVL*10mV + 840mV"
newline
hexmask.long.byte 0x0 16.--22. 1. "SLEEP_BUCK11_SEL,Select sleep mode output voltage for v11_aon VOUT = LVL*5mV + 630mV"
newline
hexmask.long.byte 0x0 8.--14. 1. "NORMAL_BUCK18_SEL,Select normal mode output voltage for v18_aon VOUT = LVL*10mV + 840mV"
newline
hexmask.long.byte 0x0 0.--6. 1. "NORMAL_BUCK11_SEL,Select normal mode output voltage for v11_aon VOUT = LVL*5mV + 630mV"
line.long 0x4 "PMIP_BUCK_CTRL,PMIP BUCK ctrl"
bitfld.long 0x4 7. "PM3_BUCK18_ON,provide a enable when sleep condition:1'b1:PM3 BUCK18 ON;1'b0:PM3 BUCK18 SLEEP" "0: PM3 BUCK18 SLEEP,1: PM3 BUCK18 ON"
newline
bitfld.long 0x4 6. "PM3_BUCK11_ON,provide a enable when sleep condition:1'b1:PM3 BUCK11 ON;1'b0:PM3 BUCK11 SLEEP" "0: PM3 BUCK11 SLEEP,1: PM3 BUCK11 ON"
newline
rbitfld.long 0x4 3. "BUCK18_SW_PD,Power Down BUCK18" "0,1"
newline
rbitfld.long 0x4 2. "BUCK18_SLP_EN,1'b1: sleep mode; 1'b0: active mode." "0: active mode,1: sleep mode"
newline
rbitfld.long 0x4 1. "BUCK11_SW_PD,Power Down BUCK11" "0,1"
newline
rbitfld.long 0x4 0. "BUCK11_SLP_EN,1'b1: sleep mode; 1'b0: active mode." "0: active mode,1: sleep mode"
line.long 0x8 "PMIP_LDO_LVL,PMIP LDO level ctrl"
bitfld.long 0x8 4.--6. "LDO11_SEL,Select output voltage for v11_aon" "0: 0.75V,1: 0.80V,2: 0.85V,3: 0.90V,4: 0.95V,5: 1.00V,6: 1.05V,7: 1.10V"
newline
bitfld.long 0x8 0.--2. "LDO18_SEL,Select output voltage for v18_aon" "0: 1.60V,1: 1.65V,2: 1.70V,3: 1.75V,4: 1.80V,5: 1.85V,6: 1.90V,7: 1.95V"
line.long 0xC "PMIP_RST,PMIP reset request register"
bitfld.long 0xC 0. "SW_RST_REQ,PMIP software por request" "0: no rst request,1: send rst request need write 1->0->1->0 sequence"
rgroup.long 0x54++0x7
line.long 0x0 "PMIP_TEST_BUCK11,PMIP test register"
hexmask.long.byte 0x0 16.--19. 1. "SOC_EXTRA,Extra bits from PMIP to SOC"
newline
hexmask.long.word 0x0 0.--15. 1. "SOC_TESTBUS,Bring BUCK11 testbus on GPIO"
line.long 0x4 "PMIP_TEST_BUCK18,PMIP test register"
hexmask.long.byte 0x4 16.--19. 1. "SOC_EXTRA,Extra bits from PMIP to SOC"
newline
hexmask.long.word 0x4 0.--15. 1. "SOC_TESTBUS,Bring BUCK18 testbus on GPIO"
group.long 0x5C++0x1B
line.long 0x0 "BOD,BOD register"
bitfld.long 0x0 5. "_1_85_INT_CLR_NEG,clr bod_1_85_int negedge" "0,1"
newline
rbitfld.long 0x0 4. "_1_85_INT_NEG,bod_1_85_int negedge" "0,1"
newline
bitfld.long 0x0 0. "EN,bod enable" "0,1"
line.long 0x4 "MEM_CFG,mem configuration register"
bitfld.long 0x4 8. "AON_MEM_RET,aon mem Retention enable register in PM4 mode" "0: in PM4 it will keep retention,1: in PM4 it will shut down"
newline
hexmask.long.byte 0x4 0.--5. 1. "MEM_RET,mem Retention enable register in PM3 mode"
line.long 0x8 "RESET_DISABLE,reset disable register"
bitfld.long 0x8 0. "PINMUX,avoid reset warm reset" "0: not disable warm reset for pinmux,1: disable warm reset for pinmux"
line.long 0xC "WLAN_CTRL,WLAN Control Register"
hexmask.long.byte 0xC 8.--15. 1. "WL_WAKEUP,MCI_WL_WAKEUP"
newline
rbitfld.long 0xC 2.--3. "WL_SLEEP,WLAN SYS sleep; bit[0]:SOCWLAPU_WLGATED_PSW_PD_AON bit[1]:cpu1_cp15_sleep" "0,1,2,3"
newline
rbitfld.long 0xC 1. "WL_XOSC_EN,wl request control different modes for CAU XTAL (1 for normal mode 0 for sleep/full PD)" "0,1"
newline
bitfld.long 0xC 0. "PD_REQ,cfg WLAN to power down" "0,1"
line.long 0x10 "BLE_CTRL,BLEControl Register"
hexmask.long.byte 0x10 8.--15. 1. "BLE_WAKEUP,MCI_BLE_WAKEUP"
newline
rbitfld.long 0x10 2.--3. "BLE_SLEEP,BLE SYS sleep; bit[0]:SOCBTAPU_BLEGATED_PSW_PD_AON bit[1]:cpu2_cp15_sleep" "0,1,2,3"
newline
rbitfld.long 0x10 1. "BLE_XOSC_EN,ble request control different modes for CAU XTAL (1 for normal mode 0 for sleep/full PD)" "0,1"
newline
bitfld.long 0x10 0. "PD_REQ,cfg BLE to power down" "0,1"
line.long 0x14 "CLK_AON,Always on Domain Clock select"
rbitfld.long 0x14 4. "PMIP_SLOW_CLK_RDY,one of 32k source ready signal" "0: one of 32k source is ready,1: none 32k is ready"
newline
rbitfld.long 0x14 2. "PMU_CLK,pmu clock select" "0: fast clock sys clock after divider,1: slow clock clk_32k"
newline
bitfld.long 0x14 0.--1. "CLK_32K_AON,32K clock select for PMU and RTC" "0: RC32K clock,1: XTAL32K clock,2: NCO32K clock,?"
line.long 0x18 "SOC_MEM_PDWN,soc mem pdwn register"
bitfld.long 0x18 7. "SOCTOP_OTP_PDWN2,soc_top_otp_pdwn2 cfg register" "0: de-assert pdwn,1: assert pdwn"
newline
bitfld.long 0x18 6. "SOCTOP_OTP_PDWN1,soc_top_otp_pdwn1 cfg register" "0: de-assert pdwn,1: assert pdwn"
newline
bitfld.long 0x18 5. "SOCTOP_OTP_PDWN0,soc_top_otp_pdwn0 cfg register" "0: de-assert pdwn,1: assert pdwn"
newline
bitfld.long 0x18 4. "MSC_MEM_PDWN,msc mem pdwn cfg register" "0: de-assert mem_pdwn,1: assert mem_pdwn"
newline
bitfld.long 0x18 1. "SOCTOP_OTP_PDWN_CTRL,soc top otp pdwn control register" "0: HW control pdwn,1: SW CFG pdwn"
newline
bitfld.long 0x18 0. "MSC_MEM_PDWN_CTRL,msc mem pdwn control register" "0: HW control mem_pdwn,1: SW CFG mem_pdwn"
group.long 0x80++0xB
line.long 0x0 "AON_PAD_OUT_CTRL,aon pad out control"
bitfld.long 0x0 1. "VALUE,aon pad output value" "0,1"
newline
bitfld.long 0x0 0. "EN,aon pad ouput en" "0,1"
line.long 0x4 "WAKEUP_PM2_MASK0,Wakeup PM2 state Mask Interrupt Register"
bitfld.long 0x4 29. "HWVAD,Hardware Voice Activity Detector Wakeup Mask" "0: mask hwvad wakeup interrupt,1: unmask hwvad wakeup interrupt"
newline
bitfld.long 0x4 28. "SECUREVIOLATION,Secure Violation Wakeup Mask" "0: mask secure violation wakeup interrupt,1: unmask secure violation wakeup interrupt"
newline
bitfld.long 0x4 27. "HYPERVISOR,HYPERVISOR Wakeup Mask" "0: mask hypervisor wakeup interrupt,1: unmask hypervisor wakeup interrupt"
newline
bitfld.long 0x4 26. "WAKEUP_FROM_DEEPSLEEP,Wakeup from Deepsleep Wakeup Mask" "0: mask wakeup_from_deepsleep wakeup interrupt,1: unmask wakeup_from_deepsleep wakeup interrupt"
newline
bitfld.long 0x4 25. "DMIC,DMIC Wakeup Mask" "0: mask dmic wakeup interrupt,1: unmask dmic wakeup interrupt"
newline
bitfld.long 0x4 23. "FREEMRT_GLOBAL,Free Multi-rate timer Wakeup Mask" "0: mask freemrt_global wakeup interrupt,1: unmask freemrt_global wakeup interrupt"
newline
bitfld.long 0x4 20. "FLEXCOMM14,FLEXCOMM14 Wakeup Mask" "0: mask flexcomm14 wakeup interrupt,1: unmask flexcomm14 wakeup interrupt"
newline
bitfld.long 0x4 17. "FLEXCOMM3,FLEXCOMM3 Wakeup Mask" "0: mask flexcomm3 wakeup interrupt,1: unmask flexcomm3 wakeup interrupt"
newline
bitfld.long 0x4 16. "FLEXCOMM2,FLEXCOMM2 Wakeup Mask" "0: mask flexcomm2 wakeup interrupt,1: unmask flexcomm2 wakeup interrupt"
newline
bitfld.long 0x4 15. "FLEXCOMM1,FLEXCOMM1 Wakeup Mask" "0: mask flexcomm1 wakeup interrupt,1: unmask flexcomm1 wakeup interrupt"
newline
bitfld.long 0x4 14. "FLEXCOMM0,FLEXCOMM0 Wakeup Mask" "0: mask flexcomm0 wakeup interrupt,1: unmask flexcomm0 wakeup interrupt"
newline
bitfld.long 0x4 13. "CTIMER3,CTIMER3 Wakeup Mask" "0: mask ctimer3 wakeup interrupt,1: unmask ctimer3 wakeup interrupt"
newline
bitfld.long 0x4 12. "SCT0,SCT0 Wakeup Mask" "0: mask sct0 wakeup interrupt,1: unmask sct0 wakeup interrupt"
newline
bitfld.long 0x4 11. "CTIMER1,CTIMER1 Wakeup Mask" "0: mask CTIMER1 wakeup interrupt,1: unmask CTIMER1 wakeup interrupt"
newline
bitfld.long 0x4 10. "CTIMER0,CTIMER0 Wakeup Mask" "0: mask ctimer0 wakeup interrupt,1: unmask ctimer0 wakeup interrupt"
newline
bitfld.long 0x4 9. "MRT,MRT Wakeup Mask" "0: mask mrt wakeup interrupt,1: unmask mrt wakeup interrupt"
newline
bitfld.long 0x4 8. "UTICK,UTICK Wakeup Mask" "0: mask utick wakeup interrupt,1: unmask utick wakeup interrupt"
newline
bitfld.long 0x4 7. "PIN_INT3,PIN_INT3 Wakeup Mask" "0: mask pin_int3 wakeup interrupt,1: unmask pin_int3 wakeup interrupt"
newline
bitfld.long 0x4 6. "PIN_INT2,PIN_INT2 Wakeup Mask" "0: mask pin_int2 wakeup interrupt,1: unmask pin_int2 wakeup interrupt"
newline
bitfld.long 0x4 5. "PIN_INT1,PIN_INT1 Wakeup Mask" "0: mask pin_int1 wakeup interrupt,1: unmask pin_int1 wakeup interrupt"
newline
bitfld.long 0x4 4. "PIN_INT0,PIN_INT0 Wakeup Mask" "0: mask pin_int0 wakeup interrupt,1: unmask pin_int0 wakeup interrupt"
newline
bitfld.long 0x4 3. "GPIO_INTB,GPIO_INTB Wakeup Mask" "0: mask gpio_intb wakeup interrupt,1: unmask gpio_intb wakeup interrupt"
newline
bitfld.long 0x4 2. "GPIO_INTA,GPIO_INTA Wakeup Mask" "0: mask gpio_inta wakeup interrupt,1: unmask gpio_inta wakeup interrupt"
newline
bitfld.long 0x4 1. "DMA0,DMA0 Wakeup Mask" "0: mask dma0 wakeup interrupt,1: unmask dma0 wakeup interrupt"
newline
bitfld.long 0x4 0. "WDT0,WDT0 Wakeup Mask" "0: mask wdt0 wakeup interrupt,1: unmask wdt0 wakeup interrupt"
line.long 0x8 "WAKEUP_PM2_MASK1,Wakeup PM2 state Mask Interrupt Register"
bitfld.long 0x8 24. "POWER_QUAD,POWER QUAD Wakeup Mask" "0: mask power_quad wakeup interrupt,1: unmask power_quad wakeup interrupt"
newline
bitfld.long 0x8 23. "PUF,PUF Wakeup Mask" "0: mask puf wakeup interrupt,1: unmask puf wakeup interrupt"
newline
bitfld.long 0x8 22. "DMA1,DMA1 Wakeup Mask" "0: mask dma1 wakeup interrupt,1: unmask dma1 wakeup interrupt"
newline
bitfld.long 0x8 18. "USB,USB Wakeup Mask" "0: mask usb wakeup interrupt,1: unmask usb wakeup interrupt"
newline
bitfld.long 0x8 16. "SGPIO_INTB,SGPIO_INTB Wakeup Mask" "0: mask sgpio_intb wakeup interrupt,1: unmask sgpio_intb wakeup interrupt"
newline
bitfld.long 0x8 15. "SGPIO_INTA,SGPIO_INTA Wakeup Mask" "0: mask sgpio_inta wakeup interrupt,1: unmask sgpio_inta wakeup interrupt"
newline
bitfld.long 0x8 14. "SDU,SDU Wakeup Mask" "0: mask sdu wakeup interrupt,1: unmask sdu wakeup interrupt"
newline
bitfld.long 0x8 10. "FLEX_SPI,Flex SPI Wakeup Mask" "0: mask flex_spi wakeup interrupt,1: unmask flex_spi wakeup interrupt"
newline
bitfld.long 0x8 9. "OS_EVENT_TIMER,OS_EVENT_TIMER Wakeup Mask" "0: mask os_event_timer wakeup interrupt,1: unmask os_event_timer wakeup interrupt"
newline
bitfld.long 0x8 7. "CTIMER2,CTIMER2 Wakeup Mask" "0: mask ctimer2 wakeup interrupt,1: unmask ctimer2 wakeup interrupt"
newline
bitfld.long 0x8 6. "PIN_INT7,PIN_INT7 Wakeup Mask" "0: mask pin_int7 wakeup interrupt,1: unmask pin_int7 wakeup interrupt"
newline
bitfld.long 0x8 5. "PIN_INT6,PIN_INT6 Wakeup Mask" "0: mask pin_int6 wakeup interrupt,1: unmask pin_int6 wakeup interrupt"
newline
bitfld.long 0x8 4. "PIN_INT5,PIN_INT5 Wakeup Mask" "0: mask pin_int5 wakeup interrupt,1: unmask pin_int5 wakeup interrupt"
newline
bitfld.long 0x8 3. "PIN_INT4,PIN_INT4 Wakeup Mask" "0: mask pin_int4 wakeup interrupt,1: unmask pin_int4 wakeup interrupt"
newline
bitfld.long 0x8 0. "RTC,RTC Wakeup Mask" "0: mask rtc wakeup interrupt,1: unmask rtc wakeup interrupt"
group.long 0x90++0x3
line.long 0x0 "WAKEUP_PM2_MASK3,Wakeup PM2 state Mask Interrupt Register"
bitfld.long 0x0 23. "ITRC_RST,itrc_rst Wakeup Mask" "0: mask itrc_rst wakeup interrupt,1: unmask itrc_rst wakeup interrupt"
newline
bitfld.long 0x0 20. "ENET_TIMER,enet_timer Wakeup Mask" "0: mask enet_timer wakeup interrupt,1: unmask enet_timer wakeup interrupt"
newline
bitfld.long 0x0 19. "ENET,enet Wakeup Mask" "0: mask enet wakeup interrupt,1: unmask enet wakeup interrupt"
newline
bitfld.long 0x0 17. "USIM,usim Wakeup Mask" "0: mask usim wakeup interrupt,1: unmask usim wakeup interrupt"
newline
bitfld.long 0x0 16. "GAU_GPADC0_INT_FUNC11,gau_gpadc0_int_func11 Wakeup Mask" "0: mask gau_gpadc0_int_func11 wakeup interrupt,1: unmask gau_gpadc0_int_func11 wakeup interrupt"
newline
bitfld.long 0x0 15. "GAU_GPADC1_INT_FUNC11,gau_gpadc1_int_func11 Wakeup Mask" "0: mask gau_gpadc1_int_func11 wakeup interrupt,1: unmask gau_gpadc1_int_func11 wakeup interrupt"
newline
bitfld.long 0x0 14. "GAU_ACOMP_INT_FUNC11,gau_acomp_int_func11 Wakeup Mask" "0: mask gau_acomp_int_func11 wakeup interrupt,1: unmask gau_acomp_int_func11 wakeup interrupt"
newline
bitfld.long 0x0 13. "GAU_ACOMP_INT_WKUP11,gau_acomp_int_wkup11 Wakeup Mask" "0: mask gau_acomp_int_wkup11 wakeup interrupt,1: unmask gau_acomp_int_wkup11 wakeup interrupt"
newline
bitfld.long 0x0 12. "GAU_GPDAC_INT_FUN11,gau_gpdac_int_fun11 Wakeup Mask" "0: mask gau_gpdac_int_fun11 wakeup interrupt,1: unmask gau_gpdac_int_fun11 wakeup interrupt"
rgroup.long 0x94++0x7
line.long 0x0 "WAKEUP_PM2_STATUS0,Wakeup PM2 status Register"
bitfld.long 0x0 29. "HWVAD,Hardware Voice Activity Detector interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 28. "SECUREVIOLATION,Secure Violation interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 27. "HYPERVISOR,HYPERVISOR interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 26. "WAKEUP_FROM_DEEPSLEEP,Wakeup from Deepsleep interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 25. "DMIC,DMIC interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 23. "FREEMRT_GLOBAL,Free Multi-rate timer interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 20. "FLEXCOMM14,FLEXCOMM14 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,FLEXCOMM3 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 16. "FLEXCOMM2,FLEXCOMM2 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,FLEXCOMM1 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 14. "FLEXCOMM0,FLEXCOMM0 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,CTIMER3 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 12. "SCT0,SCT0 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,CTIMER1 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 10. "CTIMER0,CTIMER0 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 9. "MRT,MRT interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 8. "UTICK,UTICK interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,PIN_INT3 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 6. "PIN_INT2,PIN_INT2 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,PIN_INT1 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 4. "PIN_INT0,PIN_INT0 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 3. "GPIO_INTB,GPIO_INTB interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 2. "GPIO_INTA,GPIO_INTA interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 1. "DMA0,DMA0 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 0. "WDT0,WDT0 interrupt wakeup status" "0,1"
line.long 0x4 "WAKEUP_PM2_STATUS1,Wakeup PM2 status Register"
bitfld.long 0x4 24. "POWER_QUAD,POWER QUAD interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 23. "PUF,PUF interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 22. "DMA1,DMA1 interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 18. "USB,USB interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 16. "SGPIO_INTB,SGPIO_INTB interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 15. "SGPIO_INTA,SGPIO_INTA interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 14. "SDU,SDU interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 10. "FLEX_SPI,Flex SPI interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 9. "OS_EVENT_TIMER,OS_EVENT_TIMER interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 7. "CTIMER2,CTIMER2 interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 6. "PIN_INT7,PIN_INT7 interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 5. "PIN_INT6,PIN_INT6 interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 4. "PIN_INT5,PIN_INT5 interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 3. "PIN_INT4,PIN_INT4 interrupt wakeup status" "0,1"
newline
bitfld.long 0x4 0. "RTC,rtc interrupt wakeup status" "0,1"
rgroup.long 0xA0++0x3
line.long 0x0 "WAKEUP_PM2_STATUS3,WAKEUP_PM2_STATUS3"
bitfld.long 0x0 23. "ITRC_RST,itrc_rst interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 20. "ENET_TIMER,enet_timer interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 19. "ENET,enet interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 17. "USIM,usim interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 16. "GAU_GPADC0_INT_FUNC11,gau_gpadc0_int_func11 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 15. "GAU_GPADC1_INT_FUNC11,gau_gpadc1_int_func11 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 14. "GAU_ACOMP_INT_FUNC11,gau_acomp_int_func11 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 13. "GAU_ACOMP_INT_WKUP11,gau_acomp_int_wkup11 interrupt wakeup status" "0,1"
newline
bitfld.long 0x0 12. "GAU_GPDAC_INT_FUN11,gau_gpdac_int_fun11 interrupt wakeup status" "0,1"
group.long 0xA4++0x7
line.long 0x0 "WAKEUP_PM2_SRC_CLR0,Wakeup PM2 source clear Register"
bitfld.long 0x0 29. "HWVAD,clear Hardware Voice Activity Detector interrupt request" "0,1"
newline
bitfld.long 0x0 28. "SECUREVIOLATION,clear Secure Violation interrupt request" "0,1"
newline
bitfld.long 0x0 27. "HYPERVISOR,clear HYPERVISOR interrupt request" "0,1"
newline
bitfld.long 0x0 26. "WAKEUP_FROM_DEEPSLEEP,clear Wakeup from Deepsleep interrupt request" "0,1"
newline
bitfld.long 0x0 25. "DMIC,clear DMIC interrupt request" "0,1"
newline
bitfld.long 0x0 23. "FREEMRT_GLOBAL,clear Free Multi-rate timer interrupt request" "0,1"
newline
bitfld.long 0x0 20. "FLEXCOMM14,clear FLEXCOMM14 interrupt request" "0,1"
newline
bitfld.long 0x0 17. "FLEXCOMM3,clear FLEXCOMM3 interrupt request" "0,1"
newline
bitfld.long 0x0 16. "FLEXCOMM2,clear FLEXCOMM2 interrupt request" "0,1"
newline
bitfld.long 0x0 15. "FLEXCOMM1,clear FLEXCOMM1 interrupt request" "0,1"
newline
bitfld.long 0x0 14. "FLEXCOMM0,clear FLEXCOMM0 interrupt request" "0,1"
newline
bitfld.long 0x0 13. "CTIMER3,clear CTIMER3 interrupt request" "0,1"
newline
bitfld.long 0x0 12. "SCT0,clear SCT0 interrupt request" "0,1"
newline
bitfld.long 0x0 11. "CTIMER1,clear CTIMER1 interrupt request" "0,1"
newline
bitfld.long 0x0 10. "CTIMER0,clear CTIMER0 interrupt request" "0,1"
newline
bitfld.long 0x0 9. "MRT,clear MRT interrupt request" "0,1"
newline
bitfld.long 0x0 8. "UTICK,clear UTICK interrupt request" "0,1"
newline
bitfld.long 0x0 7. "PIN_INT3,clear PIN_INT3 interrupt request" "0,1"
newline
bitfld.long 0x0 6. "PIN_INT2,clear PIN_INT2 interrupt request" "0,1"
newline
bitfld.long 0x0 5. "PIN_INT1,clear PIN_INT1 interrupt request" "0,1"
newline
bitfld.long 0x0 4. "PIN_INT0,clear PIN_INT0 interrupt request" "0,1"
newline
bitfld.long 0x0 3. "GPIO_INTB,clear GPIO_INTB interrupt request" "0,1"
newline
bitfld.long 0x0 2. "GPIO_INTA,clear GPIO_INTA interrupt request" "0,1"
newline
bitfld.long 0x0 1. "DMA0,clear DMA0 interrupt request" "0,1"
newline
bitfld.long 0x0 0. "WDT0,clear WDT0 interrupt request" "0,1"
line.long 0x4 "WAKEUP_PM2_SRC_CLR1,Wakeup PM2 source clear Register"
bitfld.long 0x4 24. "POWER_QUAD,clear POWER QUAD interrupt request" "0,1"
newline
bitfld.long 0x4 23. "PUF,clear PUF interrupt request" "0,1"
newline
bitfld.long 0x4 22. "DMA1,clear DMA1 interrupt request" "0,1"
newline
bitfld.long 0x4 18. "USB,clear USB interrupt request" "0,1"
newline
bitfld.long 0x4 16. "SGPIO_INTB,clear SGPIO_INTB interrupt request" "0,1"
newline
bitfld.long 0x4 15. "SGPIO_INTA,clear SGPIO_INTA interrupt request" "0,1"
newline
bitfld.long 0x4 14. "SDU,clear SDU interrupt request" "0,1"
newline
bitfld.long 0x4 10. "FLEX_SPI,clear Flex SPI interrupt request" "0,1"
newline
bitfld.long 0x4 9. "OS_EVENT_TIMER,clear OS_EVENT_TIMER interrupt request" "0,1"
newline
bitfld.long 0x4 7. "CTIMER2,clear CTIMER2 interrupt request" "0,1"
newline
bitfld.long 0x4 6. "PIN_INT7,clear PIN_INT7 interrupt request" "0,1"
newline
bitfld.long 0x4 5. "PIN_INT6,clear PIN_INT6 interrupt request" "0,1"
newline
bitfld.long 0x4 4. "PIN_INT5,clear PIN_INT5 interrupt request" "0,1"
newline
bitfld.long 0x4 3. "PIN_INT4,clear PIN_INT4 interrupt request" "0,1"
newline
bitfld.long 0x4 0. "RTC,clear rtc interrupt request" "0,1"
group.long 0xB0++0x3F
line.long 0x0 "WAKEUP_PM2_SRC_CLR3,Wakeup PM2 source clear Register"
bitfld.long 0x0 23. "ITRC_RST,clear itrc_rst interrupt request" "0,1"
newline
bitfld.long 0x0 20. "ENET_TIMER,clear enet_timer interrupt request" "0,1"
newline
bitfld.long 0x0 19. "ENET,clear enet interrupt request" "0,1"
newline
bitfld.long 0x0 17. "USIM,clear usim interrupt request" "0,1"
newline
bitfld.long 0x0 16. "GAU_GPADC0_INT_FUNC11,clear gau_gpadc0_int_func11 interrupt request" "0,1"
newline
bitfld.long 0x0 15. "GAU_GPADC1_INT_FUNC11,clear gau_gpadc1_int_func11 interrupt request" "0,1"
newline
bitfld.long 0x0 14. "GAU_ACOMP_INT_FUNC11,clear gau_acomp_int_func11 interrupt request" "0,1"
newline
bitfld.long 0x0 13. "GAU_ACOMP_INT_WKUP11,clear gau_acomp_int_wkup11 interrupt request" "0,1"
newline
bitfld.long 0x0 12. "GAU_GPDAC_INT_FUN11,clear gau_gpdac_int_fun11 interrupt request" "0,1"
line.long 0x4 "SW_CTRL0,SW Control register bypass HW output"
hexmask.long.word 0x4 16.--31. 1. "MCI_SW_TIME_CNT,SW control use mci counter"
newline
bitfld.long 0x4 0. "MCI_EN,SW bypass pmu MCI HW output enable" "0,1"
line.long 0x8 "SW_CTRL_WL,WL part-SW Control register bypass HW output"
bitfld.long 0x8 15. "SET_WL_SLP,set_wl_slp provide another slp way if you don't want use HW slp signal" "0,1"
newline
bitfld.long 0x8 13. "WL_BUCK_OFF_REQ,wl request buck off need to be cfg after iso en psw pd" "0,1"
newline
bitfld.long 0x8 11. "WL_BUCK_ON_REQ,wl request buck on then need wait 5 fast clk_pmu cycles(about 96ns) do psw on then iso release" "0,1"
newline
bitfld.long 0x8 9. "MCI_WL_PU_RST,mci_wl_pu_rst 0:reset release; 1:reset assert" "0: reset release,1: reset assert"
newline
bitfld.long 0x8 6. "PSW_WL_PD,psw_wl 0:power on after request buck on then delay some time to set psw on; 1:power gated do it before request buck off" "0: power on,1: power gated"
newline
bitfld.long 0x8 3. "MCI_ISO_WL_N,MCI_ISO_WL_EN_N 0:iso enable assert iso before psw off; 1:iso disable release iso after psw on;" "0: iso enable,1: iso disable"
newline
bitfld.long 0x8 0. "WL_EN,WL part-SW bypass pmu HW output enable;1:SW mode;0:HW mode" "0: HW mode,1: SW mode"
line.long 0xC "SW_CTRL_BLE,BLE part-SW Control register bypass HW output"
bitfld.long 0xC 15. "SET_BLE_SLP,set_ble_slp provide another slp way if you don't want use HW slp signal" "0,1"
newline
bitfld.long 0xC 13. "BLE_BUCK_OFF_REQ,ble request buck off need to be cfg after iso en psw pd" "0,1"
newline
bitfld.long 0xC 11. "BLE_BUCK_ON_REQ,ble request buck on then need wait 5 fast clk_pmu cycles(about 96ns) do psw on then iso release" "0,1"
newline
bitfld.long 0xC 9. "MCI_BLE_PU_RST,mci_ble_pu_rst 0:reset release; 1:reset assert" "0: reset release,1: reset assert"
newline
bitfld.long 0xC 6. "PSW_BLE_PD,psw_ble 0:power on after request buck on then delay some time to set psw on; 1:power gated do it before request buck off" "0: power on,1: power gated"
newline
bitfld.long 0xC 3. "MCI_ISO_BLE_N,MCI_ISO_BLE_EN_N 0:iso enable assert iso before psw off; 1:iso disable release iso after psw on;" "0: iso enable,1: iso disable"
newline
bitfld.long 0xC 0. "BLE_EN,BLE part-SW bypass pmu HW output enable;1:SW mode;0:HW mode" "0: HW mode,1: SW mode"
line.long 0x10 "SW_CTRL_MCI_FSM,SW Control MCI FSM condition"
bitfld.long 0x10 17. "WAKE_UP_PM3_PM4,wake_up_pm3_pm4" "0,1"
newline
bitfld.long 0x10 16. "WAKE_UP_PM3_PM4_EN,wake_up_pm3_pm4 enable signal" "0,1"
newline
bitfld.long 0x10 15. "WAKE_UP_PM2,wake_up_pm2" "0,1"
newline
bitfld.long 0x10 14. "WAKE_UP_PM2_EN,wake_up_pm2 enable signal" "0,1"
newline
bitfld.long 0x10 13. "REF_CLK_RDY,ref_clk_rdy" "0,1"
newline
bitfld.long 0x10 12. "REF_CLK_RDY_EN,ref_clk_rdy enable signal" "0,1"
newline
bitfld.long 0x10 11. "SLOW_CLK_RDY,slow_clk_rdy" "0,1"
newline
bitfld.long 0x10 10. "SLOW_CLK_RDY_EN,slow_clk_rdy enable signal" "0,1"
newline
bitfld.long 0x10 9. "CPU_SLEEP_HOLD_ACKN,cpu_sleep_hold_ackn" "0,1"
newline
bitfld.long 0x10 8. "CPU_SLEEP_HOLD_ACKN_EN,cpu_sleep_hold_ackn enable signal" "0,1"
newline
bitfld.long 0x10 0. "EN,SW Control MCI FSM condition enable signal" "0,1"
line.long 0x14 "MCI_ISO_N_TIME_POINT,MCI_ISO_MCI_EN_N toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x14 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x14 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x18 "PSW_MCI_PD_TIME_POINT,psw_mci_pd toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x18 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x18 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x1C "PSW_MCI_AON_PD_TIME_POINT,psw_mci_aon_pd toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x1C 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x1C 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x20 "GATE_SYS_CLK_TIME_POINT,gate_sys_clk toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x20 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x20 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x24 "GATE_CPU_CLK_TIME_POINT,gate_cpu_clk toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x24 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x24 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x28 "WAKEUP_RESETN_TIME_POINT,wakeup_resetn toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x28 16.--31. 1. "SECOND1,second1 half(wakeup up from sleep/down stage) se-assert time point"
newline
hexmask.long.word 0x28 0.--15. 1. "SECOND0,second0 half(wakeup up from sleep/down stage) assert time point"
line.long 0x2C "MEM_PDWN_TIME_POINT,mem_pdwn toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x2C 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x2C 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x30 "MEM_PDWN_PM2_TIME_POINT,mem_pdwn_pm2 toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x30 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x30 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x34 "ANA_PDWN_TIME_POINT,ana_pdwn toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x34 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x34 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x38 "MCI_WAKEUP_TIME_POINT,set mci_wakeup time point only in first half:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x38 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x3C "ANA_PDWN_PM2_TIME_POINT,ana_pdwn_pm2 toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x3C 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x3C 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
group.long 0xF4++0x23
line.long 0x0 "ONO_ISO_N_TIME_POINT,ONO_ISO_EN_N toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x0 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x0 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x4 "BUCK11_PD_TIME_POINT,BUCK11_PD toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x4 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x4 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x8 "BUCK18_PD_TIME_POINT,BUCK18_PD toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x8 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x8 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0xC "BUCK11_SLP_TIME_POINT,BUCK11_SLP toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0xC 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0xC 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x10 "BUCK18_SLP_TIME_POINT,BUCK18_SLP toggle time point:if want to toggle can cfg. no want can keep 0"
hexmask.long.word 0x10 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
newline
hexmask.long.word 0x10 0.--15. 1. "FIRST,first half(enter sleep/down stage) toggle time point"
line.long 0x14 "CLR_CPU_HOLD_REQ_TIME_POINT,clr cpu_hold_req_n time point. must cfg bigger than other second time point"
hexmask.long.word 0x14 16.--31. 1. "SECOND,second half(wakeup up from sleep/down stage) toggle time point"
line.long 0x18 "PSW18_OTP,PSW18 OTP psw control signal"
bitfld.long 0x18 0. "CTRL,0:power on; 1:power down" "0: power on,1: power down"
line.long 0x1C "TIME_OUT_CTRL,tieme out control signal"
bitfld.long 0x1C 2. "PSW_MCI_RDY_NO_TMT,psw_mci_rdy_n use psw output/time out generated logic;" "0: use time out generated,1: use PSW output signal"
newline
bitfld.long 0x1C 1. "V18_RDY_NO_TMT,v18_rdy use PMIP output/time out generated logic;" "0: use time out generated,1: use PMIP output signal"
newline
bitfld.long 0x1C 0. "V11_RDY_NO_TMT,v11_rdy use PMIP output/time out generated logic;" "0: use time out generated,1: use PMIP output signal"
line.long 0x20 "TIME_OUT_CFG_VALUE,tieme out configure value"
hexmask.long.byte 0x20 25.--29. 1. "PSW_MCI_RDY_DE_ASRT,the time from psw_mci off to psw_mci_rdy de-assert"
newline
hexmask.long.byte 0x20 20.--24. 1. "PSW_MCI_RDY_ASRT,the time from psw_mci on to psw_mci_rdy assert"
newline
hexmask.long.byte 0x20 15.--19. 1. "V18_RDY_DE_ASRT,the time from buck18 off to v18_rdy de-assert"
newline
hexmask.long.byte 0x20 10.--14. 1. "V18_RDY_ASRT,the time from buck18 on to v18_rdy assert"
newline
hexmask.long.byte 0x20 5.--9. 1. "V11_RDY_DE_ASRT,the time from buck11 off to v11_rdy de-assert"
newline
hexmask.long.byte 0x20 0.--4. 1. "V11_RDY_ASRT,the time from buck11 on to v11_rdy assert"
group.long 0x120++0x7
line.long 0x0 "SEC_REG,SEC REG control_bit_apply control signal"
bitfld.long 0x0 0. "CONTROL_BIT_APPLY,control bit apply" "0,1"
line.long 0x4 "RESERVE_REG0,reserve R/W regs"
hexmask.long 0x4 0.--31. 1. "VALUE,reserve R/W regs"
rgroup.long 0x128++0x3
line.long 0x0 "RESERVE_REG1,reserve Read only regs"
hexmask.long 0x0 0.--31. 1. "VALUE,reserve Read only regs"
tree.end
tree "POWERQUAD (PowerQuad DSP Coprocessor and Accelerator)"
base ad:0x40150000
group.long 0x0++0x1F
line.long 0x0 "OUTBASE,Base address register for output region"
hexmask.long 0x0 0.--31. 1. "OUTBASE,Base address register for the output region"
line.long 0x4 "OUTFORMAT,Output format"
hexmask.long.byte 0x4 8.--15. 1. "OUT_SCALER,Output Scaler value (for scaled 'q31' formats)"
bitfld.long 0x4 4.--5. "OUT_FORMATEXT,Output External format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
newline
bitfld.long 0x4 0.--1. "OUT_FORMATINT,Output Internal format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
line.long 0x8 "TMPBASE,Base address register for temp region"
hexmask.long 0x8 0.--31. 1. "TMPBASE,Base address register for the temporary region"
line.long 0xC "TMPFORMAT,Temp format"
hexmask.long.byte 0xC 8.--15. 1. "TMP_SCALER,Temp Scaler value (for scaled 'q31' formats)"
bitfld.long 0xC 4.--5. "TMP_FORMATEXT,Temp External format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
newline
bitfld.long 0xC 0.--1. "TMP_FORMATINT,Temp Internal format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
line.long 0x10 "INABASE,Base address register for input A region"
hexmask.long 0x10 0.--31. 1. "INABASE,Base address register for the input A region"
line.long 0x14 "INAFORMAT,Input A format"
hexmask.long.byte 0x14 8.--15. 1. "INA_SCALER,Input A Scaler value (for scaled 'q31' formats)"
bitfld.long 0x14 4.--5. "INA_FORMATEXT,Input A External format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
newline
bitfld.long 0x14 0.--1. "INA_FORMATINT,Input A Internal format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
line.long 0x18 "INBBASE,Base address register for input B region"
hexmask.long 0x18 0.--31. 1. "INBBASE,Base address register for the input B region"
line.long 0x1C "INBFORMAT,Input B format"
hexmask.long.byte 0x1C 8.--15. 1. "INB_SCALER,Input B Scaler value (for scaled 'q31' formats)"
bitfld.long 0x1C 4.--5. "INB_FORMATEXT,Input B External format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
newline
bitfld.long 0x1C 0.--1. "INB_FORMATINT,Input B Internal format (00: q15; 01:q31; 10:float)" "0: q15,1: q31,?,?"
group.long 0x100++0x13
line.long 0x0 "CONTROL,PowerQuad Control register"
rbitfld.long 0x0 31. "INST_BUSY,Instruction busy signal when high indicates processing is on" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "DECODE_MACHINE,0 : Coprocessor 1 : matrix 2 : fft 3 : fir 4 : stat 5 : cordic 6 -15 : NA"
newline
hexmask.long.byte 0x0 0.--3. 1. "DECODE_OPCODE,opcode specific to decode_machine"
line.long 0x4 "LENGTH,Length register"
hexmask.long 0x4 0.--31. 1. "INST_LENGTH,Length register. When FIR : fir_xlength = inst_length[15:0] fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] cols_a = inst_length[12:8] cols_b = inst_length[20:16]"
line.long 0x8 "CPPRE,Pre-scale register"
bitfld.long 0x8 17. "CPPRE_SAT8,0 = 8bits 1 = 16bits" "0: 8bits,1: 16bits"
bitfld.long 0x8 16. "CPPRE_SAT,1 : forces sub-32 bit saturation" "?,1: forces sub-32 bit saturation"
newline
hexmask.long.byte 0x8 8.--15. 1. "CPPRE_OUT,co-processor fixed point output"
hexmask.long.byte 0x8 0.--7. 1. "CPPRE_IN,co-processor scaling of input"
line.long 0xC "MISC,Misc register"
hexmask.long 0xC 0.--31. 1. "INST_MISC,Misc register. For Matrix : Used for scale factor"
line.long 0x10 "CURSORY,Cursory register"
bitfld.long 0x10 0. "CURSORY,1 : Enable cursory mode" "?,1: Enable cursory mode"
group.long 0x180++0x1B
line.long 0x0 "CORDIC_X,Cordic input X register"
hexmask.long 0x0 0.--31. 1. "CORDIC_X,Cordic input x"
line.long 0x4 "CORDIC_Y,Cordic input Y register"
hexmask.long 0x4 0.--31. 1. "CORDIC_Y,Cordic input y"
line.long 0x8 "CORDIC_Z,Cordic input Z register"
hexmask.long 0x8 0.--31. 1. "CORDIC_Z,Cordic input z"
line.long 0xC "ERRSTAT,Read/Write register where error statuses are captured (sticky)"
bitfld.long 0xC 4. "BUSERROR,bus_error" "0,1"
bitfld.long 0xC 3. "UNDERFLOW,underflow" "0,1"
newline
bitfld.long 0xC 2. "FIXEDOVERFLOW,fixed_pt_overflow" "0,1"
bitfld.long 0xC 1. "NAN,nan" "0,1"
newline
bitfld.long 0xC 0. "OVERFLOW,overflow" "0,1"
line.long 0x10 "INTREN,INTERRUPT enable register"
bitfld.long 0x10 7. "INTR_COMP,1: Enable interrupt on instruction completion" "?,1: Enable interrupt on instruction completion"
bitfld.long 0x10 4. "INTR_BERR,1: Enable interrupt on AHBM Buss Error" "?,1: Enable interrupt on AHBM Buss Error"
newline
bitfld.long 0x10 3. "INTR_UFLOW,1 : Enable interrupt on Subnormal truncation" "?,1: Enable interrupt on Subnormal truncation"
bitfld.long 0x10 2. "INTR_FIXED,1: Enable interrupt on Fixed point Overflow" "?,1: Enable interrupt on Fixed point Overflow"
newline
bitfld.long 0x10 1. "INTR_NAN,1 : Enable interrupt on Floating point NaN" "?,1: Enable interrupt on Floating point NaN"
bitfld.long 0x10 0. "INTR_OFLOW,1 : Enable interrupt on Floating point overflow" "?,1: Enable interrupt on Floating point overflow"
line.long 0x14 "EVENTEN,Event Enable register"
bitfld.long 0x14 7. "EVENT_COMP,1: Enable event trigger on instruction completion" "?,1: Enable event trigger on instruction completion"
bitfld.long 0x14 4. "EVENT_BERR,1: Enable event trigger on AHBM Buss Error" "?,1: Enable event trigger on AHBM Buss Error"
newline
bitfld.long 0x14 3. "EVENT_UFLOW,1 : Enable event trigger on Subnormal truncation" "?,1: Enable event trigger on Subnormal truncation"
bitfld.long 0x14 2. "EVENT_FIXED,1: Enable event trigger on Fixed point Overflow" "?,1: Enable event trigger on Fixed point Overflow"
newline
bitfld.long 0x14 1. "EVENT_NAN,1 : Enable event trigger on Floating point NaN" "?,1: Enable event trigger on Floating point NaN"
bitfld.long 0x14 0. "EVENT_OFLOW,1 : Enable event trigger on Floating point overflow" "?,1: Enable event trigger on Floating point overflow"
line.long 0x18 "INTRSTAT,INTERRUPT STATUS register"
bitfld.long 0x18 0. "INTR_STAT,Intr status ( 1 bit to indicate interrupt captured 0 means no new interrupt) write any value will clear this bit" "0,1"
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "GPREG[$1],General purpose register bank N."
hexmask.long 0x0 0.--31. 1. "GPREG,General purpose register bank"
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x240)++0x3
line.long 0x0 "COMPREG[$1],Compute register bank"
hexmask.long 0x0 0.--31. 1. "COMPREG,Compute register bank"
repeat.end
tree.end
tree "PUF (Physically Unclonable Function)"
base ad:0x40006000
group.long 0x0++0x7
line.long 0x0 "PUF_MODE,Mode register"
hexmask.long.byte 0x0 28.--31. 1. "ENR_LMT,Power of 2 count limit for enrollment"
hexmask.long.byte 0x0 24.--27. 1. "MODE_RSVD_0,Reserved"
hexmask.long.byte 0x0 20.--23. 1. "REC_LMT,Power of 2 count limit for reconstruction"
newline
hexmask.long.byte 0x0 16.--19. 1. "MODE_RSVD_1,Reserved"
hexmask.long.byte 0x0 12.--15. 1. "WRM_LMT,Power of 2 count limit for warmup"
hexmask.long.byte 0x0 8.--11. 1. "MODE_RSVD_2,Reserved"
newline
hexmask.long.byte 0x0 4.--7. 1. "SLW_LMT,Power of 2 count limit for slow limit"
rbitfld.long 0x0 2.--3. "MODE_RSVD_3,Reserved" "0,1,2,3"
bitfld.long 0x0 1. "ENROLL,Enrollment; 1'b0 - Reconstruction; 1'b1 - Enrollment" "0,1"
newline
bitfld.long 0x0 0. "START,Start" "0,1"
line.long 0x4 "PUF_CTRL,Control register"
bitfld.long 0x4 31. "PUF_RST,Synchronous Reset" "0,1"
hexmask.long.tbyte 0x4 8.--30. 1. "CTRL_RSVD_0,Reserved"
hexmask.long.byte 0x4 4.--7. 1. "KEY_ID,Key ID; Upper nibble of the key generation seed."
newline
rbitfld.long 0x4 2.--3. "CTRL_RSVD_1,Reserved" "0,1,2,3"
bitfld.long 0x4 1. "NEXT_CHUNK,Next Key Chunk; Request next chunk of key with current key ID" "0,1"
bitfld.long 0x4 0. "GEN_KEY,Generate Next Key; Request another key of a different KEY_ID" "0,1"
rgroup.long 0x8++0x7
line.long 0x0 "PUF_STATUS,Status register"
hexmask.long.byte 0x0 28.--31. 1. "STATUS_RSVD_0,Reserved"
hexmask.long.byte 0x0 24.--27. 1. "ERROR,Error Code; 4'b0001 - Checksum mismatch; 4'b0010 - Chunk overflow next chunk invalid; 4'b0011 - Key ID requested is locked; 4'b0100 - Invalid counter limit; 4'b0101 - Enroll/reconstruction is locked; 4'b0110 - Next chunk requested before key.."
hexmask.long.tbyte 0x0 1.--23. 1. "STATUS_RSVD_1,Reserved"
newline
bitfld.long 0x0 0. "BUSY,PUF is busy" "0,1"
line.long 0x4 "PUF_VERSION,Version register"
hexmask.long.byte 0x4 24.--31. 1. "MAJ_VER,Major Version"
hexmask.long.byte 0x4 16.--23. 1. "MIN_VER,Minor Version"
hexmask.long.byte 0x4 8.--15. 1. "NUM_RO_GRP,Number of RO Groups"
newline
hexmask.long.byte 0x4 0.--7. 1. "ENTROPY,Entropy Divided by Four"
group.long 0x10++0x3
line.long 0x0 "PUF_CKSUM,Checksum register"
hexmask.long 0x0 0.--31. 1. "CKSUM,Checksum; Enrollment: read after operation to store computed checksum; Reconstruction: rxpected checksum to compare written before operation"
group.long 0x20++0xB
line.long 0x0 "PUF_PARITY_0,Parity register"
hexmask.long 0x0 0.--31. 1. "PARITY_0,Bits [31:0] of the helper parity data"
line.long 0x4 "PUF_PARITY_1,Parity register"
hexmask.long 0x4 0.--31. 1. "PARITY_1,Bits [63:32] of the helper parity data"
line.long 0x8 "PUF_PARITY_2,Parity register"
hexmask.long.tbyte 0x8 12.--31. 1. "PAR_RSVD,Reserved"
hexmask.long.word 0x8 0.--11. 1. "PARITY_2,Bits [75:64] of the helper parity data"
group.long 0x40++0x3
line.long 0x0 "PUF_IGNORE,Ignore register"
hexmask.long 0x0 0.--31. 1. "IGNORE,Ignore data; Enrollment: Read after operation to store computed ignore tags; Reconstruction: Written before operation to load ignore tags"
group.long 0x50++0x3
line.long 0x0 "PUF_RNG,Random Number register"
hexmask.long 0x0 0.--31. 1. "RNG,Random bits used for masking during reconstruction"
rgroup.long 0x60++0x7
line.long 0x0 "PUF_KEY_0,Key register"
hexmask.long 0x0 0.--31. 1. "KEY_0,Bits [31:0] of generated key chunk"
line.long 0x4 "PUF_KEY_1,Key register"
hexmask.long 0x4 0.--31. 1. "KEY_1,Bits [63:32] of generated key chunk"
group.long 0x70++0x3
line.long 0x0 "PUF_LOCK,Lock register"
hexmask.long.byte 0x0 28.--31. 1. "ENR_LCK,Enrollment lock; 4'h5 - Locked; 4'hA - Unlocked"
hexmask.long.byte 0x0 24.--27. 1. "REC_LCK,Reconstruction lock; 4'h5 - Locked; 4'hA - Unlocked"
hexmask.long.byte 0x0 16.--23. 1. "LOCK_RSVD,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "KEY_ID_LCK,Key Lock; Each bit position represents the Key ID of a key; 1'b0 - Unlocked; 1'b1 - Locked"
rgroup.long 0x74++0x7
line.long 0x0 "PUF_RO_FREQ,RO Frequency register"
hexmask.long 0x0 0.--31. 1. "RO_FREQ,System clock count it takes for the fastest RO of each group to reach the limit"
line.long 0x4 "PUF_SLW_RO,Slow RO register"
hexmask.long.word 0x4 16.--24. 1. "SLW_TOTAL,Running total number of slow ROs"
hexmask.long.byte 0x4 8.--12. 1. "SLW_MAX_PER_GRP,Largest number of slow ROs detected in a single group"
hexmask.long.byte 0x4 0.--4. 1. "SLW_RO,Number of slow ROs in the current group."
group.long 0x80++0x3
line.long 0x0 "PUF_EVAL_SEL,Evaluation Select register"
hexmask.long.tbyte 0x0 15.--31. 1. "E_RSVD_0,Reserved"
bitfld.long 0x0 12.--14. "E_FREE_SEC,Free run mode section select" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 10.--11. "E_RSVD_1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "E_FREE_GRP,Free run mode group select" "0,1,2,3"
rbitfld.long 0x0 5.--7. "E_RSVD_2,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--4. 1. "E_RANK_SEL,Select RO based its post-ranking position"
rgroup.long 0x84++0x1F
line.long 0x0 "PUF_EVAL_VAL,Evaluation Value register"
bitfld.long 0x0 29.--31. "E_RSVD_3,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 24.--28. 1. "E_RO_NUM,Original position of the selected RO in PUF_EVAL_SEL"
hexmask.long.byte 0x0 16.--23. 1. "E_RSVD_4,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "E_CNT,Counter value of the selected RO in PUF_EVAL_SEL"
line.long 0x4 "PUF_EVAL_RAW,Evaluation Raw register"
hexmask.long.tbyte 0x4 12.--31. 1. "E_RSVD_5,Reserved"
hexmask.long.word 0x4 0.--11. 1. "E_RAW,Raw value generated by the current group of ROs"
line.long 0x8 "PUF_EVAL_BCH,Evaluation BCH register"
hexmask.long.tbyte 0x8 12.--31. 1. "E_RSVD_6,Reserved"
hexmask.long.byte 0x8 8.--11. 1. "E_ERR_LMT,Number of errors PUF can detect"
hexmask.long.byte 0x8 4.--7. 1. "E_RSVD_7,Reserved"
newline
hexmask.long.byte 0x8 0.--3. 1. "E_BCH_ERR,Number of errors PUF detected"
line.long 0xC "PUF_EVAL_ERR_LOC_0_1,Error Location register"
hexmask.long.byte 0xC 24.--31. 1. "E_RSVD_8,Reserved"
hexmask.long.byte 0xC 16.--23. 1. "E_ERR_LOC_1,Error location 1"
hexmask.long.byte 0xC 8.--15. 1. "E_RSVD_9,Reserved"
newline
hexmask.long.byte 0xC 0.--7. 1. "E_ERR_LOC_0,Error location 0"
line.long 0x10 "PUF_EVAL_ERR_LOC_2_3,Error Location register"
hexmask.long.byte 0x10 24.--31. 1. "E_RSVD_10,Reserved"
hexmask.long.byte 0x10 16.--23. 1. "E_ERR_LOC_3,Error location 3"
hexmask.long.byte 0x10 8.--15. 1. "E_RSVD_11,Reserved"
newline
hexmask.long.byte 0x10 0.--7. 1. "E_ERR_LOC_2,Error location 2"
line.long 0x14 "PUF_EVAL_ERR_LOC_4_5,Error Location register"
hexmask.long.byte 0x14 24.--31. 1. "E_RSVD_12,Reserved"
hexmask.long.byte 0x14 16.--23. 1. "E_ERR_LOC_5,Error location 5"
hexmask.long.byte 0x14 8.--15. 1. "E_RSVD_13,Reserved"
newline
hexmask.long.byte 0x14 0.--7. 1. "E_ERR_LOC_4,Error location 4"
line.long 0x18 "PUF_EVAL_ERR_LOC_6_7,Error Location register"
hexmask.long.byte 0x18 24.--31. 1. "E_RSVD_14,Reserved"
hexmask.long.byte 0x18 16.--23. 1. "E_ERR_LOC_7,Error location 7"
hexmask.long.byte 0x18 8.--15. 1. "E_RSVD_15,Reserved"
newline
hexmask.long.byte 0x18 0.--7. 1. "E_ERR_LOC_6,Error location 6"
line.long 0x1C "PUF_EVAL_ERR_LOC_8_9,Error Location register"
hexmask.long.byte 0x1C 24.--31. 1. "E_RSVD_16,Reserved"
hexmask.long.byte 0x1C 16.--23. 1. "E_ERR_LOC_9,Error location 9"
hexmask.long.byte 0x1C 8.--15. 1. "E_RSVD_17,Reserved"
newline
hexmask.long.byte 0x1C 0.--7. 1. "E_ERR_LOC_8,Error location 8"
rgroup.long 0xF0++0x7
line.long 0x0 "PUF_EVAL_RND_KEY_0,Evaluation Round Key register"
hexmask.long 0x0 0.--31. 1. "E_RND_KEY_0,Bits [31:0] of current round key used in PRASH"
line.long 0x4 "PUF_EVAL_RND_KEY_1,Evaluation Round Key register"
hexmask.long 0x4 0.--31. 1. "E_RND_KEY_1,Bits [63:32] of current round key used in PRASH"
group.long 0xFC++0x3
line.long 0x0 "PUF_EVAL_CTRL,Evaluation Control register"
hexmask.long.tbyte 0x0 9.--31. 1. "E_RSVD_18,Reserved"
bitfld.long 0x0 8. "E_FREE,Free running mode; 1'b0 - Off; 1'b1 - On" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "E_EVAL_LCK,Evaluation mode lock; 4'h5 - Locked; 4'hA - Unlocked"
newline
hexmask.long.byte 0x0 0.--3. 1. "E_EVAL_EN,Evaluation mode enable; 4'h5 - Disabled; 4'hA - Enabled"
rgroup.long 0xFC0++0x3
line.long 0x0 "PUF_ACCESS_ERR,Access Error register"
hexmask.long.tbyte 0x0 8.--31. 1. "ACCESS_ERR_RSVD_0,Reserved"
hexmask.long.byte 0x0 4.--7. 1. "APB_MASTER,APB Master that triggered the APB error"
bitfld.long 0x0 2.--3. "ACCESS_ERR_RSVD_1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "APB_WRGMD,APB error: wrong access mode" "0,1"
bitfld.long 0x0 0. "APB_NOTAV,APB error: address not available" "0,1"
group.long 0xFC4++0x3
line.long 0x0 "PUF_ACCESS_ERR_CLR,Access Error Clear register"
hexmask.long 0x0 1.--31. 1. "ACCESS_ERR_CLR_RSVD,Reserved"
bitfld.long 0x0 0. "ACCESS_ERR_CLR,Clear access errors" "0,1"
rgroup.long 0xFE0++0x3
line.long 0x0 "PUF_INT_STATUS,Interrupt Status register"
hexmask.long 0x0 7.--31. 1. "INT_RSVD,Reserved"
bitfld.long 0x0 6. "KEY_RDY,Key chunk has been generated and ready to be read" "0,1"
bitfld.long 0x0 5. "IGN_LOAD,Reconstruction only: ignore data is required to be loaded" "0,1"
newline
bitfld.long 0x0 4. "CKS_RDY,Checksum has been calculated and ready to be read" "0,1"
bitfld.long 0x0 3. "PAR_RDY,Parity data has been calculated and ready to be read" "0,1"
bitfld.long 0x0 2. "RANK_DONE,Enrollment only: Ranking is complete and ignore data is ready to be read" "0,1"
newline
bitfld.long 0x0 1. "RNG_RDY,Reconstruction only: more random data is required" "0,1"
bitfld.long 0x0 0. "INT_ERROR,Error has occured" "0,1"
group.long 0xFE4++0xB
line.long 0x0 "PUF_INT_ENABLE,Interrupt Enable register"
hexmask.long 0x0 7.--31. 1. "INT_EN_RSVD,Reserved"
bitfld.long 0x0 6. "INT_EN_KEY_RDY,Interrupt enable for KEY_RDY" "0,1"
bitfld.long 0x0 5. "INT_EN_IGN_LOAD,Interrupt enable for IGN_LOAD" "0,1"
newline
bitfld.long 0x0 4. "INT_EN_CKS_RDY,Interrupt enable for CKS_RDY" "0,1"
bitfld.long 0x0 3. "INT_EN_PAR_RDY,Interrupt enable for PAR_RDY" "0,1"
bitfld.long 0x0 2. "INT_EN_RANK_DONE,Interrupt enable for RANK_DONE" "0,1"
newline
bitfld.long 0x0 1. "INT_EN_RNG_RDY,Interrupt enable for RNG_RDY" "0,1"
bitfld.long 0x0 0. "INT_EN_ERROR,Interrupt enable for error interrupt" "0,1"
line.long 0x4 "PUF_INT_STATUS_CLR,Interrupt Status Clear register"
hexmask.long 0x4 7.--31. 1. "INT_CLR_RSVD,Reserved"
bitfld.long 0x4 6. "INT_CLR_KEY_RDY,Interrupt clear for KEY_RDY" "0,1"
bitfld.long 0x4 5. "INT_CLR_IGN_LOAD,Interrupt clear for IGN_LOAD" "0,1"
newline
bitfld.long 0x4 4. "INT_CLR_CKS_RDY,Interrupt clear for CKS_RDY" "0,1"
bitfld.long 0x4 3. "INT_CLR_PAR_RDY,Interrupt clear for PAR_RDY" "0,1"
bitfld.long 0x4 2. "INT_CLR_RANK_DONE,Interrupt clear for RANK_DONE" "0,1"
newline
bitfld.long 0x4 1. "INT_CLR_RNG_RDY,Interrupt clear for RNG_RDY" "0,1"
bitfld.long 0x4 0. "INT_CLR_ERROR,Interrupt clear for error interrupt" "0,1"
line.long 0x8 "PUF_INT_STATUS_SET,Interrupt Status Set register"
hexmask.long 0x8 7.--31. 1. "INT_SET_RSVD,Reserved"
bitfld.long 0x8 6. "INT_SET_KEY_RDY,Interrupt set for KEY_RDY" "0,1"
bitfld.long 0x8 5. "INT_SET_IGN_LOAD,Interrupt set for IGN_LOAD" "0,1"
newline
bitfld.long 0x8 4. "INT_SET_CKS_RDY,Interrupt set for CKS_RDY" "0,1"
bitfld.long 0x8 3. "INT_SET_PAR_RDY,Interrupt set for PAR_RDY" "0,1"
bitfld.long 0x8 2. "INT_SET_RANK_DONE,Interrupt set for RANK_DONE" "0,1"
newline
bitfld.long 0x8 1. "INT_SET_RNG_RDY,Interrupt set for RNG_RDY" "0,1"
bitfld.long 0x8 0. "INT_SET_ERROR,Interrupt set for error interrupt" "0,1"
rgroup.long 0xFFC++0x3
line.long 0x0 "PUF_MODULE_ID,Module ID register"
hexmask.long 0x0 0.--31. 1. "PLACEHOLDER,Module ID"
tree.end
tree "ROMCP"
base ad:0x4013C000
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xD4)++0x3
line.long 0x0 "ROMPATCHD$1,ROMC Data Registers"
hexmask.long 0x0 0.--31. 1. "DATAX,Data Fix Registers"
repeat.end
group.long 0xF4++0x3
line.long 0x0 "ROMPATCHCNTL,ROMC Control Register"
bitfld.long 0x0 31. "LK,Register Lock" "0: All registers remain accessible (unlocked).,1: Lock access to all registers. All ROMCP register.."
bitfld.long 0x0 29. "DIS,ROMC Disable" "0: Does not affect any ROMC functions (default),1: Disables all ROMC functions: data fixing and.."
newline
bitfld.long 0x0 7. "DATAFIX7,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
bitfld.long 0x0 6. "DATAFIX6,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
newline
bitfld.long 0x0 5. "DATAFIX5,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
bitfld.long 0x0 4. "DATAFIX4,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
newline
bitfld.long 0x0 3. "DATAFIX3,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
bitfld.long 0x0 2. "DATAFIX2,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
newline
bitfld.long 0x0 1. "DATAFIX1,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
bitfld.long 0x0 0. "DATAFIX0,Data Fix Enable" "0: Trigger an opcode patch,1: Trigger a data fix"
rgroup.long 0xF8++0x3
line.long 0x0 "ROMPATCHENH,ROMC Enable Register High"
group.long 0xFC++0x3
line.long 0x0 "ROMPATCHENL,ROMC Enable Register Low"
bitfld.long 0x0 15. "ENABLE15,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 14. "ENABLE14,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "ENABLE13,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 12. "ENABLE12,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "ENABLE11,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 10. "ENABLE10,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "ENABLE9,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 8. "ENABLE8,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "ENABLE7,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 6. "ENABLE6,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "ENABLE5,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 4. "ENABLE4,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 3. "ENABLE3,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 2. "ENABLE2,Enable Address Comparator n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "ENABLE1,Enable Address Comparator n" "0: Disable,1: Enable"
bitfld.long 0x0 0. "ENABLE0,Enable Address Comparator n" "0: Disable,1: Enable"
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "ROMPATCHA[$1],ROMC Address Registers"
hexmask.long.tbyte 0x0 1.--22. 1. "ADDRX,Address Comparator Registers"
bitfld.long 0x0 0. "THUMBX,THUMB Comparator Select" "0: ARM patch,1: THUMB patch (ignore if a data fix)"
repeat.end
group.long 0x208++0x3
line.long 0x0 "ROMPATCHSR,ROMC Status Register"
eventfld.long 0x0 17. "SW,ROMC AHB Multiple Address Comparator Match Indicator" "0: No event or comparator collisions have occurred,1: A collision has occurred"
hexmask.long.byte 0x0 0.--5. 1. "SOURCE,ROMC Source Number"
tree.end
tree "RSTCTL (Reset Controller)"
base ad:0x0
tree "RSTCTL0"
base ad:0x40000000
group.long 0x10++0xB
line.long 0x0 "PRSTCTL0,Peripheral reset control 0"
bitfld.long 0x0 31. "SDIO,sdio reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 30. "DMA1,dma1 reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 29. "DMA0,dma0 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 28. "GDMA,gdma reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 25. "AON_MEM,aon_mem reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 24. "SCT,sct reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 22. "USB,usb reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 20. "HPU,hpu reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 16. "FLEXSPI0,flexspi0 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 11. "PUF,puf reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 10. "CSS,css reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 9. "PKC,pkc reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 8. "PQ,pq reset control" "0: Clear reset,1: Set reset"
line.long 0x4 "PRSTCTL1,Peripheral reset control 1"
bitfld.long 0x4 27. "TRNG,trng reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x4 26. "ENET_IPG_S,enet_ipg_s reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x4 25. "ENET_IPG,enet_ipg reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x4 24. "SECURE_GPIO,secure_gpio reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x4 17. "OTP,otp reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x4 16. "GAU,gau reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x4 2. "SDIO_SLV,sdio_slv reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x4 1. "CSS_GDET_REF_RST_N,css_gdet_ref_rst_n control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x4 0. "CSS_APB,css_apb reset control" "0: Clear reset,1: Set reset"
line.long 0x8 "PRSTCTL2,Peripheral reset control 2"
bitfld.long 0x8 31. "AON_DOMAIN_TEST_MON,aon_domain_test_mon reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 30. "C0_DOMAIN_TEST_MON,c0_domain_test_mon reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x8 27. "LCDIC,lcdic reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 26. "FREEMRT,freemrt reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x8 2. "USIM,usim reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 1. "WWDT0,wwdt0 reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x8 0. "UTICK,utick reset control" "0: Clear reset,1: Set reset"
group.long 0x40++0x3
line.long 0x0 "PRSTCTL0_SET,Peripheral reset set 0"
bitfld.long 0x0 31. "SDIO,sdio reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 30. "DMA1,dma1 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 29. "DMA0,dma0 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 28. "GDMA,gdma reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 25. "AON_MEM,aon_mem reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 24. "SCT,sct reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 22. "USB,usb reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 20. "HPU,hpu reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 16. "FLEXSPI0,flexspi0 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 11. "PUF,puf reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 10. "CSS,css reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 9. "PKC,pkc reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 8. "PQ,pq reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
wgroup.long 0x44++0x7
line.long 0x0 "PRSTCTL1_SET,Peripheral reset set 1"
bitfld.long 0x0 27. "TRNG,trng reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x0 26. "ENET_IPG_S,enet_ipg_s reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x0 25. "ENET_IPG,enet_ipg reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x0 24. "SECURE_GPIO,secure_gpio reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x0 17. "OTP,otp reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 16. "GAU,gau reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x0 2. "SDIO_SLV,sdio_slv reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x0 1. "CSS_GDET_REF_RST_N,css_gdet_ref_rst_n reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x0 0. "CSS_APB,css_apb reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
line.long 0x4 "PRSTCTL2_SET,Peripheral reset set 2"
bitfld.long 0x4 31. "AON_DOMAIN_TEST_MON,aon_domain_test_mon reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x4 30. "C0_DOMAIN_TEST_MON,c0_domain_test_mon reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x4 27. "LCDIC,lcdic reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x4 26. "FREEMRT,freemrt reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x4 2. "USIM,usim reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x4 1. "WWDT0,wwdt0 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x4 0. "UTICK,utick reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
wgroup.long 0x70++0xB
line.long 0x0 "PRSTCTL0_CLR,Peripheral reset clear 0"
bitfld.long 0x0 31. "SDIO,sdio reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 30. "DMA1,dma1 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 29. "DMA0,dma0 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 28. "GDMA,gdma reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 25. "AON_MEM,aon_mem reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 24. "SCT,sct reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 22. "USB,usb reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 20. "HPU,hpu reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 16. "FLEXSPI0,flexspi0 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 11. "PUF,puf reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 10. "CSS,css reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 9. "PKC,pkc reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 8. "PQ,pq reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
line.long 0x4 "PRSTCTL1_CLR,Peripheral reset clear 1"
bitfld.long 0x4 27. "TRNG,trng reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x4 26. "ENET_IPG_S,enet_ipg_s reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x4 25. "ENET_IPG,enet_ipg reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x4 24. "SECURE_GPIO,secure_gpio reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x4 17. "OTP,otp reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x4 16. "GAU,gau reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x4 2. "SDIO_SLV,sdio_slv reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x4 1. "CSS_GDET_REF_RST_N,css_gdet_ref_rst_n reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x4 0. "CSS_APB,css_apb reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
line.long 0x8 "PRSTCTL2_CLR,Peripheral reset clear 2"
bitfld.long 0x8 31. "AON_DOMAIN_TEST_MON,aon_domain_test_mon reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 30. "C0_DOMAIN_TEST_MON,c0_domain_test_mon reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x8 27. "LCDIC,lcdic reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 26. "FREEMRT,freemrt reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x8 2. "USIM,usim reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 1. "WWDT0,wwdt0 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x8 0. "UTICK,utick reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
tree.end
tree "RSTCTL1"
base ad:0x40020000
group.long 0x10++0xB
line.long 0x0 "PRSTCTL0,Peripheral reset control 0"
bitfld.long 0x0 27. "OSEVENTTIMER,oseventtimer reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 24. "DMIC0,dmic0 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 22. "FC14,fc14 reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 11. "FC3,fc3 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 10. "FC2,fc2 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x0 9. "FC1,fc1 reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x0 8. "FC0,fc0 reset control" "0: Clear reset,1: Set reset"
line.long 0x4 "PRSTCTL1,Peripheral reset control 1"
bitfld.long 0x4 31. "FREQME,freqme reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x4 16. "CRC,crc reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x4 1. "HSGPIO1,hsgpio1 reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x4 0. "HSGPIO0,hsgpio0 reset control" "0: Clear reset,1: Set reset"
line.long 0x8 "PRSTCTL2,Peripheral reset control 2"
bitfld.long 0x8 31. "PMUX,pmux reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 30. "GPIO_INT,gpio_int reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 8. "MRT,mrt reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x8 4. "CT32B4,ct32b4 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 3. "CT32B3,ct32b3 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 2. "CT32B2,ct32b2 reset control" "0: Clear reset,1: Set reset"
newline
bitfld.long 0x8 1. "CT32B1,ct32b1 reset control" "0: Clear reset,1: Set reset"
bitfld.long 0x8 0. "CT32B0,ct32b0 reset control" "0: Clear reset,1: Set reset"
wgroup.long 0x40++0x3
line.long 0x0 "PRSTCTL0_SET,Peripheral reset set 0"
bitfld.long 0x0 27. "OSEVENTTIMER,oseventtimer reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 24. "DMIC0,dmic0 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 22. "FC14,fc14 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 11. "FC3,fc3 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 10. "FC2,fc2 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
bitfld.long 0x0 9. "FC1,fc1 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
newline
bitfld.long 0x0 8. "FC0,fc0 reset set" "0: No effect,1: Sets the PRSTCTL0 Bit"
group.long 0x44++0x3
line.long 0x0 "PRSTCTL1_SET,Peripheral reset set 1"
bitfld.long 0x0 31. "FREQME,freqme reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x0 16. "CRC,crc reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
bitfld.long 0x0 1. "HSGPIO1,hsgpio1 reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
newline
bitfld.long 0x0 0. "HSGPIO0,hsgpio0 reset set" "0: No effect,1: Sets the PRSTCTL1 Bit"
wgroup.long 0x48++0x3
line.long 0x0 "PRSTCTL2_SET,Peripheral reset set 2"
bitfld.long 0x0 31. "PMUX,pmux reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x0 30. "GPIO_INT,gpio_int reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x0 8. "MRT,mrt reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x0 4. "CT32B4,ct32b4 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x0 3. "CT32B3,ct32b3 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x0 2. "CT32B2,ct32b2 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
newline
bitfld.long 0x0 1. "CT32B1,ct32b1 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
bitfld.long 0x0 0. "CT32B0,ct32b0 reset set" "0: No effect,1: Sets the PRSTCTL2 Bit"
wgroup.long 0x70++0xB
line.long 0x0 "PRSTCTL0_CLR,Peripheral reset clear 0"
bitfld.long 0x0 27. "OSEVENTTIMER,oseventtimer reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 24. "DMIC0,dmic0 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 22. "FC14,fc14 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 11. "FC3,fc3 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 10. "FC2,fc2 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
bitfld.long 0x0 9. "FC1,fc1 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
newline
bitfld.long 0x0 8. "FC0,fc0 reset clear" "0: No effect,1: Clears the PRSTCTL0 Bit"
line.long 0x4 "PRSTCTL1_CLR,Peripheral reset clear 1"
bitfld.long 0x4 31. "FREQME,freqme reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x4 16. "CRC,crc reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
bitfld.long 0x4 1. "HSGPIO1,hsgpio1 reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
newline
bitfld.long 0x4 0. "HSGPIO0,hsgpio0 reset clear" "0: No effect,1: Clears the PRSTCTL1 Bit"
line.long 0x8 "PRSTCTL2_CLR,Peripheral reset clear 2"
bitfld.long 0x8 31. "PMUX,pmux reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 30. "GPIO_INT,gpio_int reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 8. "MRT,mrt reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x8 4. "CT32B4,ct32b4 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 3. "CT32B3,ct32b3 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 2. "CT32B2,ct32b2 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
newline
bitfld.long 0x8 1. "CT32B1,ct32b1 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
bitfld.long 0x8 0. "CT32B0,ct32b0 reset clear" "0: No effect,1: Clears the PRSTCTL2 Bit"
group.long 0x90++0x3
line.long 0x0 "SDIO,SDIO sdclk_sw_rst_n control"
bitfld.long 0x0 0. "SDCLK_SW_RST_N,0: sw reset 1: reset release" "0: sw reset,1: reset release"
tree.end
tree.end
tree "RTC (Real-Time Clock)"
base ad:0x40030000
group.long 0x0++0xF
line.long 0x0 "CTRL,RTC control register"
hexmask.long.byte 0x0 28.--31. 1. "RTC_OSC_LOADCAP,capacitive load selection"
bitfld.long 0x0 10. "RTC_SUBSEC_ENA,The 32 KHz sub-second counter enable" "0: The sub-second counter (if implemented) is..,1: The 32 KHz sub-second counter is enabled (if.."
newline
bitfld.long 0x0 9. "RTC_OSC_BYPASS,The RTC Oscillator bypass" "0: The RTC Oscillator operates normally as a..,1: The RTC oscillator is in bypass mode. In this.."
bitfld.long 0x0 8. "RTC_OSC_PD,The RTC oscillator enable" "0: The RTC oscillator is enabled. This bit must be..,1: The RTC oscillator is shut-off to reserve power.."
newline
bitfld.long 0x0 7. "RTC_EN,RTC enable." "0: Disable. The RTC 1 Hz and 1 kHz clocks are shut..,1: Enable. The 1 Hz RTC clock is running and RTC.."
bitfld.long 0x0 6. "RTC1KHZ_EN,RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)." "0: Disable. A match on the 1 kHz RTC timer will not..,1: Enable. The 1 kHz RTC timer is enabled."
newline
bitfld.long 0x0 5. "WAKEDPD_EN,RTC 1 kHz timer wake-up enable for Deep power-down." "0: Disable. A match on the 1 kHz RTC timer will not..,1: Enable. A match on the 1 kHz RTC timer bring the.."
bitfld.long 0x0 4. "ALARMDPD_EN,RTC 1 Hz timer alarm enable for Deep power-down." "0: Disable. A match on the 1 Hz RTC timer will not..,1: Enable. A match on the 1 Hz RTC timer bring the.."
newline
bitfld.long 0x0 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status." "0: Run. The RTC 1 kHz timer is running. Writing a 0..,1: Time-out. The 1 kHz high-resolution/wake-up.."
bitfld.long 0x0 2. "ALARM1HZ,RTC 1 Hz timer alarm flag status." "0: No match. No match has occurred on the 1 Hz RTC..,1: Match. A match condition has occurred on the 1.."
newline
bitfld.long 0x0 1. "OFD,Oscillator fail detect status." "0: Run. The RTC oscillator is running properly.,1: Fail. RTC oscillator fail detected. Clear this.."
bitfld.long 0x0 0. "SWRESET,Software reset control" "0: Not in reset. The RTC is not held in reset. This..,1: In reset. The RTC is held in reset. All register.."
line.long 0x4 "MATCH,RTC match register"
hexmask.long 0x4 0.--31. 1. "MATVAL,Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled."
line.long 0x8 "COUNT,RTC counter register"
hexmask.long 0x8 0.--31. 1. "VAL,A read reflects the current value of the main 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL.."
line.long 0xC "WAKE,High-resolution/wake-up timer control register"
hexmask.long.word 0xC 0.--15. 1. "VAL,A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress."
rgroup.long 0x10++0x3
line.long 0x0 "SUBSEC,RTC Sub-second Counter register"
hexmask.long.word 0x0 0.--14. 1. "RTC_SUBSEC,A read reflects the current value of the 32Khz sub-second counter. This counter will be cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32 KHz rate commences at the start of the next one-second interval.."
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x80)++0x3
line.long 0x0 "GPREG[$1],General Purpose register"
hexmask.long 0x0 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied."
repeat.end
tree.end
tree "SCTIMER"
base ad:0x40146000
group.long 0x0++0x17
line.long 0x0 "CONFIG,SCTimer Configuration"
bitfld.long 0x0 18. "AUTOLIMIT_H,Auto Limit Higher" "0: Disable.,1: Enable. A match on match register 0 is the LIMIT.."
bitfld.long 0x0 17. "AUTOLIMIT_L,Auto Limit Lower" "0: Disable.,1: Enable. A match on match register 0 is the LIMIT.."
newline
hexmask.long.byte 0x0 9.--16. 1. "INSYNC,Input Synchronization"
bitfld.long 0x0 8. "NORELOAD_H,No Reload Higher Match" "0: Reload. The default setting.,1: No Reload. Prevents the higher match registers.."
newline
bitfld.long 0x0 7. "NORELOAD_L,No Reload Lower Match" "0: Reload. The default setting.,1: No Reload. Prevents the lower match registers.."
hexmask.long.byte 0x0 3.--6. 1. "CKSEL,SCT Clock Select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register."
newline
bitfld.long 0x0 1.--2. "CLKMODE,SCT Clock Mode" "0: System Clock Mode. The system clock clocks the..,1: Sampled System Clock Mode. The system clock..,2: SCT Input Clock Mode. The input/edge selected by..,3: Asynchronous Mode. The entire SCT module is.."
bitfld.long 0x0 0. "UNIFY,SCT Operation" "0: Dual counter. The SCT operates as two 16-bit..,1: Unified counter. The SCT operates as a unified.."
line.long 0x4 "CTRL,SCT Control"
hexmask.long.byte 0x4 21.--28. 1. "PRE_H,Prescaler for High Counter"
bitfld.long 0x4 20. "BIDIR_H,Bidirectional Select High" "0: Up. The H counter counts up to its limit..,1: Up-down. The H counter counts up to its limit.."
newline
bitfld.long 0x4 19. "CLRCTR_H,Clear Counter High" "0,1"
bitfld.long 0x4 18. "HALT_H,Halt Counter High" "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "STOP_H,Stop Counter High" "0: Disable,1: Enable"
bitfld.long 0x4 16. "DOWN_H,Down Counter High" "0: Up. The H counter is counting up.,1: Down. The H counter is counting down."
newline
hexmask.long.byte 0x4 5.--12. 1. "PRE_L,Prescaler for Low Counter"
bitfld.long 0x4 4. "BIDIR_L,Bidirectional Select Low" "0: Up. The counter counts up to a limit condition..,1: Up-down. The counter counts up to a limit then.."
newline
bitfld.long 0x4 3. "CLRCTR_L,Clear Counter Low" "0,1"
bitfld.long 0x4 2. "HALT_L,Halt Counter Low" "0: Disable,1: Enable"
newline
bitfld.long 0x4 1. "STOP_L,Stop Counter Low" "0: Disable,1: Enable"
bitfld.long 0x4 0. "DOWN_L,Down Counter Low" "0: Up. The L or unified counter is counting up.,1: Down. The L or unified counter is counting down."
line.long 0x8 "LIMIT,SCT Limit Event Select"
hexmask.long.word 0x8 16.--31. 1. "LIMMSK_H,Limit Event Counter High"
hexmask.long.word 0x8 0.--15. 1. "LIMMSK_L,Limit Event Counter Low"
line.long 0xC "HALT,Halt Event Select"
hexmask.long.word 0xC 16.--31. 1. "HALTMSK_H,Halt Event High"
hexmask.long.word 0xC 0.--15. 1. "HALTMSK_L,Halt Event Low"
line.long 0x10 "STOP,Stop Event Select"
hexmask.long.word 0x10 16.--31. 1. "STOPMSK_H,Stop Event High"
hexmask.long.word 0x10 0.--15. 1. "STOPMSK_L,Stop Event Low"
line.long 0x14 "START,Start Event Select"
hexmask.long.word 0x14 16.--31. 1. "STARTMSK_H,If bit n is one event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16 event 1 = bit 17 etc.). The number of bits = number of events in this SCT."
hexmask.long.word 0x14 0.--15. 1. "STARTMSK_L,If bit n is one event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0 event 1 = bit 1 etc.). The number of bits = number of events in this SCT."
group.long 0x40++0x7
line.long 0x0 "COUNT,Counter"
hexmask.long.word 0x0 16.--31. 1. "CTR_H,Counter High"
hexmask.long.word 0x0 0.--15. 1. "CTR_L,Counter Low"
line.long 0x4 "STATE,State"
hexmask.long.byte 0x4 16.--20. 1. "STATE_H,State variable"
hexmask.long.byte 0x4 0.--4. 1. "STATE_L,State variable"
rgroup.long 0x48++0x3
line.long 0x0 "INPUT,Input"
bitfld.long 0x0 31. "SIN15,Input 15 state. Input 15 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 30. "SIN14,Input 14 state. Input 14 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 29. "SIN13,Input 13 state. Input 13 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 28. "SIN12,Input 12 state. Input 12 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 27. "SIN11,Input 11 state. Input 11 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 26. "SIN10,Input 10 state. Input 10 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 25. "SIN9,Input 9 state. Input 9 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 24. "SIN8,Input 8 state. Input 8 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 23. "SIN7,Input 7 state. Input 7 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 22. "SIN6,Input 6 state. Input 6 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 21. "SIN5,Input 5 state. Input 5 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 20. "SIN4,Input 4 state. Input 4 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 19. "SIN3,Input 3 state. Input 3 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 18. "SIN2,Input 2 state. Input 2 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 17. "SIN1,Input 1 state. Input 1 state following the synchronization specified by INSYNC." "0,1"
bitfld.long 0x0 16. "SIN0,Input 0 state. Input 0 state following the synchronization specified by INSYNC." "0,1"
newline
bitfld.long 0x0 15. "AIN15,Input 15 state. Input 15 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 14. "AIN14,Input 14 state. Input 14 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 13. "AIN13,Input 13 state. Input 13 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 12. "AIN12,Input 12 state. Input 12 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 11. "AIN11,Input 11 state. Input 11 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 10. "AIN10,Input 10 state. Input 10 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 9. "AIN9,Input 9 state. Input 9 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 8. "AIN8,Input 8 state. Input 8 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 7. "AIN7,Input 7 state. Input 7 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 6. "AIN6,Input 6 state. Input 6 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 5. "AIN5,Input 5 state. Input 5 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 4. "AIN4,Input 4 state. Input 4 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 3. "AIN3,Input 3 state. Input 3 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 2. "AIN2,Input 2 state. Input 2 state on the last SCT clock edge." "0,1"
newline
bitfld.long 0x0 1. "AIN1,Input 1 state. Input 1 state on the last SCT clock edge." "0,1"
bitfld.long 0x0 0. "AIN0,Input 0 state. Input 0 state on the last SCT clock edge." "0,1"
group.long 0x4C++0x17
line.long 0x0 "REGMODE,Match/Capture Mode"
bitfld.long 0x0 31. "REGMOD_H15,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 30. "REGMOD_H14,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 29. "REGMOD_H13,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 28. "REGMOD_H12,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 27. "REGMOD_H11,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 26. "REGMOD_H10,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 25. "REGMOD_H9,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 24. "REGMOD_H8,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 23. "REGMOD_H7,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 22. "REGMOD_H6,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 21. "REGMOD_H5,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 20. "REGMOD_H4,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 19. "REGMOD_H3,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 18. "REGMOD_H2,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 17. "REGMOD_H1,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 16. "REGMOD_H0,Register Mode High n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 15. "REGMOD_L15,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 14. "REGMOD_L14,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 13. "REGMOD_L13,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 12. "REGMOD_L12,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 11. "REGMOD_L11,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 10. "REGMOD_L10,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 9. "REGMOD_L9,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 8. "REGMOD_L8,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 7. "REGMOD_L7,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 6. "REGMOD_L6,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 5. "REGMOD_L5,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 4. "REGMOD_L4,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 3. "REGMOD_L3,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 2. "REGMOD_L2,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
newline
bitfld.long 0x0 1. "REGMOD_L1,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
bitfld.long 0x0 0. "REGMOD_L0,Register Mode Low n" "0: Match. Register n operates as a match register,1: Capture. Register n operates as a capture register"
line.long 0x4 "OUTPUT,Output"
bitfld.long 0x4 9. "OUT9,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
bitfld.long 0x4 8. "OUT8,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
newline
bitfld.long 0x4 7. "OUT7,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
bitfld.long 0x4 6. "OUT6,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
newline
bitfld.long 0x4 5. "OUT5,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
bitfld.long 0x4 4. "OUT4,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
newline
bitfld.long 0x4 3. "OUT3,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
bitfld.long 0x4 2. "OUT2,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
newline
bitfld.long 0x4 1. "OUT1,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
bitfld.long 0x4 0. "OUT0,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output high"
line.long 0x8 "OUTPUTDIRCTRL,Output Counter Direction Control"
bitfld.long 0x8 18.--19. "SETCLR9,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 16.--17. "SETCLR8,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
newline
bitfld.long 0x8 14.--15. "SETCLR7,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 12.--13. "SETCLR6,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
newline
bitfld.long 0x8 10.--11. "SETCLR5,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 8.--9. "SETCLR4,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
newline
bitfld.long 0x8 6.--7. "SETCLR3,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 4.--5. "SETCLR2,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
newline
bitfld.long 0x8 2.--3. "SETCLR1,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
bitfld.long 0x8 0.--1. "SETCLR0,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction of..,1: Set and clear are reversed when counter L or the..,2: Set and clear are reversed when counter H is..,?"
line.long 0xC "RES,Output Conflict Resolution"
bitfld.long 0xC 18.--19. "O9RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
bitfld.long 0xC 16.--17. "O8RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
newline
bitfld.long 0xC 14.--15. "O7RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
bitfld.long 0xC 12.--13. "O6RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
newline
bitfld.long 0xC 10.--11. "O5RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
bitfld.long 0xC 8.--9. "O4RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
newline
bitfld.long 0xC 6.--7. "O3RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
bitfld.long 0xC 4.--5. "O2RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
newline
bitfld.long 0xC 2.--3. "O1RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
bitfld.long 0xC 0.--1. "O0RES,Effect of simultaneous set and clear on output n" "0: No change,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: Toggle output"
line.long 0x10 "DMAREQ0,DMA Request 0"
rbitfld.long 0x10 31. "DRQ0,DMA Request 0 State" "0,1"
bitfld.long 0x10 30. "DRL0,A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers." "0,1"
newline
bitfld.long 0x10 15. "DEV_15,DMA Request Event n" "0,1"
bitfld.long 0x10 14. "DEV_14,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 13. "DEV_13,DMA Request Event n" "0,1"
bitfld.long 0x10 12. "DEV_12,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 11. "DEV_11,DMA Request Event n" "0,1"
bitfld.long 0x10 10. "DEV_10,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 9. "DEV_9,DMA Request Event n" "0,1"
bitfld.long 0x10 8. "DEV_8,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 7. "DEV_7,DMA Request Event n" "0,1"
bitfld.long 0x10 6. "DEV_6,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 5. "DEV_5,DMA Request Event n" "0,1"
bitfld.long 0x10 4. "DEV_4,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 3. "DEV_3,DMA Request Event n" "0,1"
bitfld.long 0x10 2. "DEV_2,DMA Request Event n" "0,1"
newline
bitfld.long 0x10 1. "DEV_1,DMA Request Event n" "0,1"
bitfld.long 0x10 0. "DEV_0,DMA Request Event n" "0,1"
line.long 0x14 "DMAREQ1,DMA Request 1"
rbitfld.long 0x14 31. "DRQ1,DMA Request 1 State" "0,1"
bitfld.long 0x14 30. "DRL1,A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers." "0,1"
newline
bitfld.long 0x14 15. "DEV_15,DMA Request Event n" "0,1"
bitfld.long 0x14 14. "DEV_14,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 13. "DEV_13,DMA Request Event n" "0,1"
bitfld.long 0x14 12. "DEV_12,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 11. "DEV_11,DMA Request Event n" "0,1"
bitfld.long 0x14 10. "DEV_10,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 9. "DEV_9,DMA Request Event n" "0,1"
bitfld.long 0x14 8. "DEV_8,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 7. "DEV_7,DMA Request Event n" "0,1"
bitfld.long 0x14 6. "DEV_6,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 5. "DEV_5,DMA Request Event n" "0,1"
bitfld.long 0x14 4. "DEV_4,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 3. "DEV_3,DMA Request Event n" "0,1"
bitfld.long 0x14 2. "DEV_2,DMA Request Event n" "0,1"
newline
bitfld.long 0x14 1. "DEV_1,DMA Request Event n" "0,1"
bitfld.long 0x14 0. "DEV_0,DMA Request Event n" "0,1"
group.long 0xF0++0x13
line.long 0x0 "EVEN,Event Interrupt Enable"
bitfld.long 0x0 15. "IEN15,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 14. "IEN14,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "IEN13,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 12. "IEN12,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "IEN11,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 10. "IEN10,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "IEN9,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 8. "IEN8,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "IEN7,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 6. "IEN6,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "IEN5,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 4. "IEN4,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 3. "IEN3,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 2. "IEN2,Event Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "IEN1,Event Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x0 0. "IEN0,Event Interrupt Enable n" "0: Disable,1: Enable"
line.long 0x4 "EVFLAG,Event Flag"
bitfld.long 0x4 15. "FLAG15,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 14. "FLAG14,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 13. "FLAG13,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 12. "FLAG12,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 11. "FLAG11,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 10. "FLAG10,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 9. "FLAG9,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 8. "FLAG8,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 7. "FLAG7,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 6. "FLAG6,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 5. "FLAG5,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 4. "FLAG4,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 3. "FLAG3,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 2. "FLAG2,Event Flag n" "0: No Flag,1: Event n Flag"
newline
bitfld.long 0x4 1. "FLAG1,Event Flag n" "0: No Flag,1: Event n Flag"
bitfld.long 0x4 0. "FLAG0,Event Flag n" "0: No Flag,1: Event n Flag"
line.long 0x8 "CONEN,Conflict Interrupt Enable"
bitfld.long 0x8 9. "NCEN9,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
bitfld.long 0x8 8. "NCEN8,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
newline
bitfld.long 0x8 7. "NCEN7,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
bitfld.long 0x8 6. "NCEN6,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
newline
bitfld.long 0x8 5. "NCEN5,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
bitfld.long 0x8 4. "NCEN4,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
newline
bitfld.long 0x8 3. "NCEN3,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
bitfld.long 0x8 2. "NCEN2,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
newline
bitfld.long 0x8 1. "NCEN1,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
bitfld.long 0x8 0. "NCEN0,No Change Conflict Event/Interrupt Enable" "0: No interrupt,1: Interrupt"
line.long 0xC "CONFLAG,Conflict Flag"
bitfld.long 0xC 31. "BUSERRH,Bus Error High" "0,1"
bitfld.long 0xC 30. "BUSERRL,Bus Error Low/Unified" "0,1"
newline
bitfld.long 0xC 9. "NCFLAG9,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0xC 8. "NCFLAG8,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0xC 7. "NCFLAG7,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0xC 6. "NCFLAG6,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0xC 5. "NCFLAG5,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0xC 4. "NCFLAG4,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0xC 3. "NCFLAG3,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0xC 2. "NCFLAG2,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
newline
bitfld.long 0xC 1. "NCFLAG1,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
bitfld.long 0xC 0. "NCFLAG0,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured"
line.long 0x10 "CAP0,Capture Value"
hexmask.long.word 0x10 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x10 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x100++0x7
line.long 0x0 "MATCH0,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP1,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x104++0x7
line.long 0x0 "MATCH1,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP2,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x108++0x7
line.long 0x0 "MATCH2,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP3,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x10C++0x7
line.long 0x0 "MATCH3,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP4,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x110++0x7
line.long 0x0 "MATCH4,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP5,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x114++0x7
line.long 0x0 "MATCH5,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP6,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x118++0x7
line.long 0x0 "MATCH6,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP7,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x11C++0x7
line.long 0x0 "MATCH7,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP8,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x120++0x7
line.long 0x0 "MATCH8,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP9,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x124++0x7
line.long 0x0 "MATCH9,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP10,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x128++0x7
line.long 0x0 "MATCH10,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP11,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x12C++0x7
line.long 0x0 "MATCH11,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP12,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x130++0x7
line.long 0x0 "MATCH12,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP13,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x134++0x7
line.long 0x0 "MATCH13,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP14,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x138++0x7
line.long 0x0 "MATCH14,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
line.long 0x4 "CAP15,Capture Value"
hexmask.long.word 0x4 16.--31. 1. "CAPN_H,Capture n High"
hexmask.long.word 0x4 0.--15. 1. "CAPN_L,Capture n Low"
group.long 0x13C++0x3
line.long 0x0 "MATCH15,Match Value"
hexmask.long.word 0x0 16.--31. 1. "MATCHN_H,Match n High"
hexmask.long.word 0x0 0.--15. 1. "MATCHN_L,Match n Low"
group.long 0x200++0x3
line.long 0x0 "CAPCTRL0,Capture Control"
hexmask.long.word 0x0 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x0 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x200++0x7
line.long 0x0 "MATCHREL0,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL1,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x204++0x7
line.long 0x0 "MATCHREL1,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL2,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x208++0x7
line.long 0x0 "MATCHREL2,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL3,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x20C++0x7
line.long 0x0 "MATCHREL3,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL4,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x210++0x7
line.long 0x0 "MATCHREL4,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL5,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x214++0x7
line.long 0x0 "MATCHREL5,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL6,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x218++0x7
line.long 0x0 "MATCHREL6,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL7,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x21C++0x7
line.long 0x0 "MATCHREL7,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL8,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x220++0x7
line.long 0x0 "MATCHREL8,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL9,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x224++0x7
line.long 0x0 "MATCHREL9,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL10,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x228++0x7
line.long 0x0 "MATCHREL10,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL11,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x22C++0x7
line.long 0x0 "MATCHREL11,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL12,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x230++0x7
line.long 0x0 "MATCHREL12,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL13,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x234++0x7
line.long 0x0 "MATCHREL13,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL14,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x238++0x7
line.long 0x0 "MATCHREL14,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
line.long 0x4 "CAPCTRL15,Capture Control"
hexmask.long.word 0x4 16.--31. 1. "CAPCONN_H,Capture Control n High"
hexmask.long.word 0x4 0.--15. 1. "CAPCONN_L,Capture Control n Low"
group.long 0x23C++0x3
line.long 0x0 "MATCHREL15,Match Reload Value"
hexmask.long.word 0x0 16.--31. 1. "RELOADN_H,Reload n High"
hexmask.long.word 0x0 0.--15. 1. "RELOADN_L,Reload n Low"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40146300 ad:0x40146308 ad:0x40146310 ad:0x40146318 ad:0x40146320 ad:0x40146328 ad:0x40146330 ad:0x40146338 ad:0x40146340 ad:0x40146348 ad:0x40146350 ad:0x40146358 ad:0x40146360 ad:0x40146368 ad:0x40146370 ad:0x40146378)
tree "EVENT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "EV_STATE,Event n State"
hexmask.long 0x0 0.--31. 1. "STATEMSKN,Event State Mask n"
line.long 0x4 "EV_CTRL,Event n Control"
bitfld.long 0x4 21.--22. "DIRECTION,Direction" "0: Direction independent. This event is triggered..,1: Counting up. This event is triggered only during..,2: Counting down. This event is triggered only..,?"
bitfld.long 0x4 20. "MATCHMEM,Match Mem" "0,1"
newline
hexmask.long.byte 0x4 15.--19. 1. "STATEV,State Value"
bitfld.long 0x4 14. "STATELD,State Load" "0: Add. STATEV value is added into STATE (the..,1: Load. STATEV value is loaded into STATE."
newline
bitfld.long 0x4 12.--13. "COMBMODE,Combination Mode" "0: OR. The event occurs when either the specified..,1: MATCH. Uses the specified match only.,2: IO. Uses the specified I/O condition only.,3: AND. The event occurs when the specified match.."
bitfld.long 0x4 10.--11. "IOCOND,Input/Output Condition" "0: Low,1: Rise,2: Fall,3: High"
newline
hexmask.long.byte 0x4 6.--9. 1. "IOSEL,Input/Output Signal Select"
bitfld.long 0x4 5. "OUTSEL,Input/Output Select" "0: Selects the inputs selected by IOSEL.,1: Selects the outputs selected by IOSEL."
newline
bitfld.long 0x4 4. "HEVENT,High Event" "0: Low Counter,1: High Counter"
hexmask.long.byte 0x4 0.--3. 1. "MATCHSEL,Match Select"
tree.end
repeat.end
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40146500 ad:0x40146508 ad:0x40146510 ad:0x40146518 ad:0x40146520 ad:0x40146528 ad:0x40146530 ad:0x40146538 ad:0x40146540 ad:0x40146548)
tree "OUT[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "OUT_SET,Output n Set"
hexmask.long.word 0x0 0.--15. 1. "SET,Set"
line.long 0x4 "OUT_CLR,Output n Clear"
hexmask.long.word 0x4 0.--15. 1. "CLR,Clear"
tree.end
repeat.end
tree.end
tree "SDU"
base ad:0x0
tree "SDU_FBR_CARD"
base ad:0x40158020
group.byte 0x0++0x0
line.byte 0x0 "FN_CODE,Function Code"
rbitfld.byte 0x0 7. "CSA_EN,Function CSA Enable" "0,1"
rbitfld.byte 0x0 6. "CSA,Function supports Code Storage Area (CSA) 0 = function does not support CSA 1 = function supports CSA" "0: function does not support CSA,1: function supports CSA"
hexmask.byte 0x0 0.--3. 1. "CODE,Standard I/O device interface code"
rgroup.byte 0x1++0x0
line.byte 0x0 "FN_EXT_CODE,Extended Function Code"
hexmask.byte 0x0 0.--7. 1. "FN_EXT_CODE,Extended SDIO standard function interface code."
group.byte 0x2++0x0
line.byte 0x0 "FN_POWER_SELECT,Function Power Select"
hexmask.byte 0x0 4.--7. 1. "FN_PS,Power State"
rbitfld.byte 0x0 1. "EPS,Current Mode 0 = function operates in high current mode 1 = function operates in low current mode" "0: function operates in high current mode,1: function operates in low current mode"
bitfld.byte 0x0 0. "SPS,Power Selection 0 = no power selection 1 = two power modes selected by EPS bit" "0: no power selection,1: two power modes selected by EPS bit"
rgroup.byte 0x5++0x4
line.byte 0x0 "FN_CIS_0,Function CIS Pointer 0"
hexmask.byte 0x0 0.--7. 1. "FN_CIS_PTR0,24b Function Pointer [7:0] Function card information structure pointer [7:0] Function n CIS pointer is (0x8000 | n << 7) Therefore Function 1 CIS pointer is 0x008080 Function 2 CIS pointer is 0x008100 Function 3 CIS pointer is 0x008180 ..."
line.byte 0x1 "FN_CIS_1,Function CIS Pointer 1"
hexmask.byte 0x1 0.--7. 1. "FN_CIS_PTR1,24b Function 1 Pointer [15:8] Function card information structure pointer [15:8]"
line.byte 0x2 "FN_CIS_2,Function CIS Pointer 2"
hexmask.byte 0x2 0.--7. 1. "FN_CIS_PTR2,24b Function 1 Pointer [23:16] Function card information structure pointer [23:16]"
line.byte 0x3 "FN_BLOCK_SIZE_0,Function Block Size 0"
hexmask.byte 0x3 0.--7. 1. "FN_BLK_SIZE0,Block Size [7:0] for I/O Block Operation"
line.byte 0x4 "FN_BLOCK_SIZE_1,Function Block Size 1"
bitfld.byte 0x4 0. "FN_BLK_SIZE1,Block Size [8] for I/O Block Operation" "0,1"
tree.end
tree "SDU_FN0_CARD"
base ad:0x40158000
group.byte 0x0++0x1
line.byte 0x0 "CCCR,CCCR/SDIO Revision"
hexmask.byte 0x0 4.--7. 1. "SDIO_REV,SDIO Specification Revision Number Version of the SDIO specification that this card supports."
newline
hexmask.byte 0x0 0.--3. 1. "CCCR_REV,CCCR Format Version Number Version of the CCCR format that this card supports."
line.byte 0x1 "VER,SD Specification Revision"
hexmask.byte 0x1 0.--3. 1. "SD_PHY_REV,SD Format Version Number Version of the SD Physical specification that this card supports."
rgroup.byte 0x2++0x4
line.byte 0x0 "IO_ENABLE,I/O Enable"
hexmask.byte 0x0 1.--7. 1. "IOE,Function I/O enable 0 = function disabled 1 = function enabled"
line.byte 0x1 "IO_READY,I/O Function Ready"
hexmask.byte 0x1 1.--7. 1. "FN_IO_RDY,Function I/O ready 0 = function not ready to operate 1 = function ready to operate"
line.byte 0x2 "INT_ENABLE,Interrupt Enable"
hexmask.byte 0x2 1.--7. 1. "IEN,Function Interrupt Enable 0 = interrupt from this function not sent to host 1 = interrupt from this function sent to host (host_ien must also be set)"
newline
bitfld.byte 0x2 0. "HOST_IEN,Host Interrupt Enable 0 = no interrupts from this card sent to host 1 = any function's interrupt sent to host" "0: no interrupts from this card sent to host,1: any function's interrupt sent to host"
line.byte 0x3 "INT_PENDING,Interrupt Pending"
hexmask.byte 0x3 1.--7. 1. "FN_INT_HOST,Function Interrupt Pending 0 = no interrupts pending from this function 1 = interrupt pending If the ien[x] or host_ien bits are not set in INT_ENABLE the host will not receive the pending interrupt."
line.byte 0x4 "IO_ABORT,I/O Abort"
bitfld.byte 0x4 3. "IO_CARD_RST,I/O Card Reset If host sets this bit an interrupt is generated to the card." "0,1"
newline
bitfld.byte 0x4 0.--2. "ABORT_SEL,Abort Select To abort an I/O read or write to free the SD bus the function that is currently transferring data must be addressed." "0,1,2,3,4,5,6,7"
group.byte 0x7++0x0
line.byte 0x0 "BUS_INTF_CTRL,Bus Interface Control"
rbitfld.byte 0x0 7. "CD_DISABLE,Connect/Disconnet Disable Connect[0]/disconnect[1] the 10K-90 kO pull-up resistor on pin 1 of card." "0,1"
newline
bitfld.byte 0x0 6. "SCSI,Support continuous SPI Interrupt writable from internal bus only 0 = SPI supports interrupt assertion only when CS (SD)DAT[3] pin) is asserted 1 = SPI supports interrupt assertion independent of CS" "0: SPI supports interrupt assertion only when CS,1: SPI supports interrupt assertion independent of CS"
newline
rbitfld.byte 0x0 5. "ECSI,ecsi" "0,1"
newline
rbitfld.byte 0x0 0.--1. "BUS_WIDTH,Bus Width Data bus width used for data transfer 00 = 1 bit 10 = 4 bits All full-speed SDIO cards support both 1-bit and 4-bit bus." "0: 1 bit,?,?,?"
rgroup.byte 0x8++0x9
line.byte 0x0 "CAPAB,Card Capability"
bitfld.byte 0x0 5. "E4MI,Enable 4-bit Mode Interrupt Enable interrupt between blocks of data in 4-bit mode." "0,1"
newline
bitfld.byte 0x0 4. "S4MI,Support 4-bit Mode Interrupt Supports interrupt between blocks of data in 4-bit mode 0 = card not able to signal an interrupt during a 4-bit multi-block data transfer 1 = card is able to signal an interrupt between blocks during data transfer" "0: card not able to signal an interrupt during a..,1: card is able to signal an interrupt between.."
newline
bitfld.byte 0x0 1. "SMB,Support Multi-Block Card supports multi block indicator 0 = all I/O functions do not accept and execute 1 = all I/O functions accept and execute" "0: all I/O functions do not accept and execute,1: all I/O functions accept and execute"
newline
bitfld.byte 0x0 0. "SDC,Support Direct Commands Card supports direct commands during multi-byte transfer 0 = all I/O functions do not accept and execute 1 = all I/O functions accept and execute" "0: all I/O functions do not accept and execute,1: all I/O functions accept and execute"
line.byte 0x1 "FUNC0_CIS_0,Function 0 CIS Pointer 0"
hexmask.byte 0x1 0.--7. 1. "F0_CIS_PTR0,CIS Pointer Bits[7:0]"
line.byte 0x2 "FUNC0_CIS_1,Function 0 CIS Pointer 1"
hexmask.byte 0x2 0.--7. 1. "F0_CIS_PTR1,CIS Pointer Bits[15:8]"
line.byte 0x3 "FUNC0_CIS_2,Function 0 CIS Pointer 2"
hexmask.byte 0x3 0.--7. 1. "F0_CIS_PTR2,CIS Pointer Bits[23:16]"
line.byte 0x4 "BUS_SUSP,Bus Suspend"
bitfld.byte 0x4 1. "BUS_RELEASE,Bus Release Bus release request/status indicator 0 = N/A 1 = suspend request still in progress" "0: N/A,1: suspend request still in progress"
newline
bitfld.byte 0x4 0. "BUS_STATUS,Bus Status Bus status indicator 0 = N/A 1 = currently addressed function is currently executing a command" "0: N/A,1: currently addressed function is currently.."
line.byte 0x5 "BUS_SEL,Function Select"
bitfld.byte 0x5 7. "DATA_FLAG,Data Flag (Not used)" "0,1"
newline
hexmask.byte 0x5 0.--3. 1. "FN_SELECT,Select Function (Not used)"
line.byte 0x6 "EXEC,Execute Flags"
hexmask.byte 0x6 1.--7. 1. "FN_EXEC,Execution Flag for functions (Not used)"
newline
bitfld.byte 0x6 0. "MEM_EXEC,Execution Flag for memory (Not used)" "0,1"
line.byte 0x7 "READY,Ready Flags"
hexmask.byte 0x7 1.--7. 1. "FN_RDY_FLAG,Ready Flag for functions (Not used)"
newline
bitfld.byte 0x7 0. "MEM_RDY_FLAG,Ready Flag for memory (Not used)" "0,1"
line.byte 0x8 "FN0_BLOCK_SIZE_0,Function 0 Block Size 0"
hexmask.byte 0x8 0.--7. 1. "FN0_BLK_SIZE0,Block size [7:0] for Function 0 I/O block operations"
line.byte 0x9 "FN0_BLOCK_SIZE_1,Function 0 Block Size 1"
bitfld.byte 0x9 0. "FN0_BLK_SIZE1,Block size [8] for Function 0 I/O block operations" "0,1"
group.byte 0x12++0x4
line.byte 0x0 "POWER_CONTROL,Power Control"
rbitfld.byte 0x0 1. "EMPC,Enable Master Power Control 0 = disable 1 = enable" "0: disable,1: enable"
newline
bitfld.byte 0x0 0. "SMPC,Support Master Power Control 0 = do not support 1 = support" "0: do not support,1: support"
line.byte 0x1 "BUS_SPEED_SELECT,Bus Speed Select"
rbitfld.byte 0x1 1.--3. "BSS,Select Ultra High Speed Mode BSS Bus speed(1." "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x1 0. "SHS,Support High Speed Mode 0 = do not support 1 = support" "0: do not support,1: support"
line.byte 0x2 "UHS_SUPPORT,UHS-I Support"
bitfld.byte 0x2 2. "SDDR50,This bit indicates support of ddr50." "0,1"
newline
bitfld.byte 0x2 1. "SSDR104,This bit indicates support of sdr104." "0,1"
newline
bitfld.byte 0x2 0. "SSDR50,This bit indicates support of sdr50." "0,1"
line.byte 0x3 "DRIVER_STR,Driver Strength"
rbitfld.byte 0x3 4.--5. "DTS,Driver Type Select" "0,1,2,3"
newline
bitfld.byte 0x3 2. "SDTD,Support Driver Type D This bit indicates support of Driver Type D" "0,1"
newline
bitfld.byte 0x3 1. "SDTC,Support Driver Type C This bit indicates support of Driver Type C" "0,1"
newline
bitfld.byte 0x3 0. "SDTA,Support Driver Type A This bit indicates support of Driver Type A" "0,1"
line.byte 0x4 "INTERRUPT_EXT,Interrupt Extension"
rbitfld.byte 0x4 1. "EAI,Enable Asynchronous Interrupt Enable bit of asynchronous interrupt." "0,1"
newline
bitfld.byte 0x4 0. "SAI,Support Asynchronous Interrupt Support bit of asynchronous interrupt." "0,1"
group.byte 0x8C++0x3
line.byte 0x0 "CARD_CTRL1,Card Control 1"
bitfld.byte 0x0 6.--7. "CMD53_RFIFO_TH,CMD53 read fifo threshold 00 = 1 block size 01 = .5 block size 10 = block size 11 = block size" "0: 1 block size,1: .5 block size,?,?"
newline
bitfld.byte 0x0 4. "SD_HOST_INT_ACT_LVL,SD Host Interrupt Active Level 0 = Active Low 1 = Active High" "0: Active Low,1: Active High"
newline
bitfld.byte 0x0 3. "CMD53_RD_ERR_WKUP_EN,CMD53 Read Error Wakeup Enable If host issues CMD53 read access during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
newline
bitfld.byte 0x0 2. "CMD53_WR_ERR_WKUP_EN,CMD53 Write Error Wakeup Enable If host issues CMD53 write access during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
newline
bitfld.byte 0x0 1. "CMD52_RD_ERR_WKUP_EN,CMD52 Read Error Wakeup Enable If host issues CMD52 read access to any off-domain register during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
newline
bitfld.byte 0x0 0. "CMD52_WR_ERR_WKUP_EN,CMD52 Write Error Wakeup Enable If host issues CMD52 write access to any off-domain register during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
line.byte 0x1 "CARD_CTRL2,Card Control 2"
bitfld.byte 0x1 5. "APU_DEV_SLEEP_EN,If this is set to 1 the IO_READY status and Card Ready status depend on APU sleep/wake state." "0,1"
newline
bitfld.byte 0x1 4. "CMD52_PWUP_EN,If this is set to 1 host can issue any CMD52 to wake up the chip." "0,1"
newline
bitfld.byte 0x1 3. "CMD52_DLY_RES_RDATA_EN,Delay latching of CMD52 read data until it is serially shifted out" "0,1"
newline
bitfld.byte 0x1 2. "CMD52_WR_RESP_EN,Enable delay of CMD52 write response (Not used)" "0,1"
newline
bitfld.byte 0x1 1. "NGFF_SD_RST_EN,Allow NGFF SDIO RESET# to reset OCR value." "0,1"
newline
bitfld.byte 0x1 0. "ASYNC_INT_MASK_EN,Enable asynchronous interrupt mask" "0,1"
line.byte 0x2 "CMD19_CTRL1,CMD19 Control1"
hexmask.byte 0x2 0.--7. 1. "CMD19_TP_ADDR,CMD19 tuning pattern address Set address value for CMD19 tuning pattern array"
line.byte 0x3 "CMD19_CTRL2,CMD19 Control2"
hexmask.byte 0x3 0.--7. 1. "CMD19_TP_DATA,CMD19 tuning pattern data CMD19 tuning pattern data at cmd19_tp_addr"
rgroup.byte 0x90++0x0
line.byte 0x0 "FUNC_CARD_INT,Function Card Interrupt"
hexmask.byte 0x0 4.--7. 1. "FN_CARD_INT2,Pending card interrupt for each function to cpu2"
newline
hexmask.byte 0x0 0.--3. 1. "FN_CARD_INT1,Pending card interrupt for each function to cpu1"
group.byte 0x91++0x6
line.byte 0x0 "FUNC0_CARD_INTMASK,Function Card Interrupt Mask"
hexmask.byte 0x0 4.--7. 1. "FN_CARD_INT3,Pending card interrupt for each function to cpu3"
newline
bitfld.byte 0x0 0.--2. "FN0_CARD_INTMASK,Card interrupt mask for function 0." "0,1,2,3,4,5,6,7"
line.byte 0x1 "DEV_SLEEP,Device Sleep"
bitfld.byte 0x1 0. "DEV_SLEEP,Device Sleep If this is set to 1 IO_READY and CARD_READY status will be 0." "0,1"
line.byte 0x2 "CARD_CTRL3,Card Control 3"
rbitfld.byte 0x2 6. "CMD52_PWUP,Wakeup signal to APU." "0,1"
newline
bitfld.byte 0x2 0. "CMD53_WR_BUSY_HW_EN,Main enable bit for cmd53_wr_busy_hw_ctrl feature." "0,1"
line.byte 0x3 "FN0_CARD_INTMASK0,Function 0 Card Interrupt Mask 0"
hexmask.byte 0x3 0.--7. 1. "FN0_CARD_INTMASK0,Function 0 card interrupt mask [7:0]"
line.byte 0x4 "FN0_CARD_INTMASK1,Function 0 Card Interrupt Mask 1"
hexmask.byte 0x4 0.--7. 1. "FN0_CARD_INTMASK1,Function 0 card interrupt mask [15:8]"
line.byte 0x5 "FN0_CARD_INTRSR0,Function 0 Card Interrupt Reset Select 0"
hexmask.byte 0x5 0.--7. 1. "FN0_CARD_INTRSR0,Function 0 card interrupt reset select [7:0] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
line.byte 0x6 "FN0_CARD_INTRSR1,Function 0 Card Interrupt Reset Select 1"
hexmask.byte 0x6 0.--7. 1. "FN0_CARD_INTRSR1,Function 0 card interrupt reset select [15:8] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
rgroup.byte 0x98++0x3
line.byte 0x0 "FN0_CARD_INTSTATUS0,Function 0 Card Interrupt Status 0"
hexmask.byte 0x0 0.--7. 1. "FN0_CARD_INTSTAT0,Function 0 card interrupt status [7:0] of the following events: [7:1] = fn_ps_event [0] = drv_snth_event"
line.byte 0x1 "FN0_CARD_INTSTATUS1,Function 0 Card Interrupt Status 1"
hexmask.byte 0x1 0.--7. 1. "FN0_CARD_INTSTAT1,Function 0 card interrupt status [15:8] of the following events: [7] = FN0 CMD53 read access during sleep mode [6] = FN0 CMD53 write access during sleep mode [5] = FN0 CMD52 read access to off-domain sdu register during sleep mode [4] =.."
line.byte 0x2 "FN0_CARD_ACTVINTMASK0,Function 0 Card Active Interrupt Mask 0"
hexmask.byte 0x2 0.--7. 1. "FN0_CARD_ACTVINTMASK0,Function 0 card active interrupt mask[7:0]"
line.byte 0x3 "FN0_CARD_ACTVINTMASK1,Function 0 Card Active Interrupt Mask 1"
hexmask.byte 0x3 0.--7. 1. "FN0_CARD_ACTVINTMASK1,Function 0 card active interrupt mask[15:8]"
group.byte 0x9C++0x3
line.byte 0x0 "CARD_CTRL4,Card Control 4"
bitfld.byte 0x0 7. "CMD5_S18R_CHK,If this is set S18A in R4 depends on CMD5 S18R bit." "0,1"
newline
bitfld.byte 0x0 6. "SET_CMD11_ILLEGAL,If this is set and SD VIO pad sensor V18=1 (1." "0,1"
newline
bitfld.byte 0x0 5. "CMD5_R4_S18A_BYPASS_EN,If this is set the S18A field in cmd5 R4 response is bypassed." "0,1"
newline
bitfld.byte 0x0 4. "CMD5_R4_S18A_BYPASS_VAL,FW bypass value that overrides the S18A field in cmd5 R4 response." "0,1"
newline
bitfld.byte 0x0 3. "CMD11_SD_CLK_STOP_BYPASS,If this is set the cmd11 state machine will bypass the SD clk idle checking logic." "0,1"
newline
bitfld.byte 0x0 2. "CMD11_VIO_CHK_BYPASS,If this is set the cmd11 state machine will bypass the VIO pad sensor check." "0,1"
newline
bitfld.byte 0x0 1. "CMD11_V18_BYPASS_EN,If this is set the V18 signal from the SD pad voltage sensor is bypassed." "0,1"
newline
bitfld.byte 0x0 0. "CMD11_V18_BYPASS_VAL,FW bypass value that overrides the V18 signal from the SD pad voltage sensor." "0,1"
line.byte 0x1 "CARD_CTRL5,Card Control 5"
bitfld.byte 0x1 7. "CMD52_RES_VALID_MODE,CMD52 response valid mode 0 = CMD52 response valid is generated only after write operation is completed in the ahb_clk domain." "0: CMD52 response valid is generated only after..,?"
newline
bitfld.byte 0x1 6. "SD_RESET_AFTER_CMD52_R5,Generate sd_reset after cmd52 R5 response." "0,1"
newline
bitfld.byte 0x1 5. "RESET_RCA,Reset RCA." "0,1"
newline
bitfld.byte 0x1 4. "REPEAT_SDU_INIT,If this is set sdu can handle enumeration sequence initiated by host multiple times" "0,1"
newline
bitfld.byte 0x1 3. "CMD5_R4_FN_BYPASS_EN,If this is set the function number field of R4 is controlled by cmd5_r4_fn_bypass_val rather than from chip strap settings." "0,1"
newline
bitfld.byte 0x1 0.--2. "CMD5_R4_FN_BYPASS_VAL,FW bypass value that overrides the function number derived from chip strap settings." "0,1,2,3,4,5,6,7"
line.byte 0x2 "CARD_CTRL6,Card Control 6"
hexmask.byte 0x2 0.--7. 1. "TESTBUS_SEL_LO,SDU testbus select [7:0]"
line.byte 0x3 "CARD_CTRL7,Card Control 7"
hexmask.byte 0x3 0.--7. 1. "TESTBUS_SEL_HI,SDU testbus select [15:8]"
tree.end
tree "SDU_FN_CARD"
base ad:0x40158100
rgroup.byte 0x0++0x0
line.byte 0x0 "H2C_INTEVENT,Host to Card Interrupt Event"
bitfld.byte 0x0 4. "HOST_RST_EVENT,Host reset event When host sets this bit interrupt is generated to the CPU." "0,1"
newline
bitfld.byte 0x0 3. "HOST_TO_CARD_EVENT,Host to card event When host sets this bit interrupt is generated to the CPU." "0,1"
newline
bitfld.byte 0x0 2. "HOST_TERMINATE_CMD53,Host terminates CMD53 When host sets this bit current cmd53 data transfer will terminate." "0,1"
newline
bitfld.byte 0x0 1. "HOST_PWR_UP,Host power up event When host sets this bit interrupt is generated to the CPU." "0,1"
newline
bitfld.byte 0x0 0. "HOST_PWR_DOWN,Host power down event When host sets this bit interrupt is generated to the CPU." "0,1"
rgroup.byte 0x4++0x1
line.byte 0x0 "HOST_INTRSR0,Host Interrupt Reset Select 0"
hexmask.byte 0x0 0.--7. 1. "HOST_INT_RSR0,Host Interrupt Reset Select [7:0] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
line.byte 0x1 "HOST_INTRSR1,Host Interrupt Reset Select 1"
hexmask.byte 0x1 0.--7. 1. "HOST_INT_RSR1,Host Interrupt Reset Select [15:8] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
rgroup.byte 0x8++0x1
line.byte 0x0 "HOST_INTMASK0,Host Interrupt Mask 0"
hexmask.byte 0x0 0.--7. 1. "HOST_INT_MASK0,Host Interrupt Mask [7:0] 0 = disable card to host interrupt 1 = enable card to host interrupt"
line.byte 0x1 "HOST_INTMASK1,Host Interrupt Mask 1"
hexmask.byte 0x1 0.--7. 1. "HOST_INT_MASK1,Host Interrupt Mask [15:8] 0 = disable card to host interrupt 1 = enable card to host interrupt"
rgroup.byte 0xC++0x1
line.byte 0x0 "HOST_INTSTATUS0,Host Interrupt Status 0"
bitfld.byte 0x0 7. "CMD_PORT_DNLD_INT,Command Port Download Host Interrupt Status Set when card is ready for command port download from host." "0,1"
newline
bitfld.byte 0x0 6. "CMD_PORT_UPLD_INT,Command Port Upload Host Interrupt Status Set when card has packet ready for command port upload and card is in I/O ready state." "0,1"
newline
bitfld.byte 0x0 4.--5. "CARD_TO_HOST_INT,2-bit FW controlled interrupts to host." "0,1,2,3"
newline
bitfld.byte 0x0 3. "FIFO_OVERFLOW,Fifo Overflow Set when FIFO overflow occurs during download." "0,1"
newline
bitfld.byte 0x0 2. "FIFO_UNDERFLOW,Fifo Underflow Set when FIFO underflow occurs during upload." "0,1"
newline
bitfld.byte 0x0 1. "Q0_DNLD_HOST_INT,Queue 0 Download Host Interrupt Status Set when card is ready for download from host." "0,1"
newline
bitfld.byte 0x0 0. "Q0_UPLD_HOST_INT,Queue 0 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state." "0,1"
line.byte 0x1 "HOST_INTSTATUS1,Host Interrupt Status 1"
bitfld.byte 0x1 5. "Q3_DNLD_HOST_INT,Queue 3 Download Host Interrupt Status Set when card is ready for download from host." "0,1"
newline
bitfld.byte 0x1 4. "Q2_DNLD_HOST_INT,Queue 2 Download Host Interrupt Status Set when card is ready for download from host." "0,1"
newline
bitfld.byte 0x1 3. "Q1_DNLD_HOST_INT,Queue 1 Download Host Interrupt Status Set when card is ready for download from host." "0,1"
newline
bitfld.byte 0x1 2. "Q3_UPLD_HOST_INT,Queue 3 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state." "0,1"
newline
bitfld.byte 0x1 1. "Q2_UPLD_HOST_INT,Queue 2 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state." "0,1"
newline
bitfld.byte 0x1 0. "Q1_UPLD_HOST_INT,Queue 1 Upload Host Interrupt Status Set when card has packet ready for upload and card is in I/O ready state." "0,1"
group.byte 0x10++0x47
line.byte 0x0 "PKT_RD_BITMAP0,Packet Read Bitmap 0"
bitfld.byte 0x0 7. "PKT_RD_BITMAP7,Packet read bitmap[7]." "0,1"
newline
bitfld.byte 0x0 6. "PKT_RD_BITMAP6,Packet read bitmap[6]" "0,1"
newline
bitfld.byte 0x0 5. "PKT_RD_BITMAP5,Packet read bitmap[5]" "0,1"
newline
bitfld.byte 0x0 4. "PKT_RD_BITMAP4,Packet read bitmap[4]" "0,1"
newline
bitfld.byte 0x0 3. "PKT_RD_BITMAP3,Packet read bitmap[3]" "0,1"
newline
bitfld.byte 0x0 2. "PKT_RD_BITMAP2,Packet read bitmap[2]" "0,1"
newline
bitfld.byte 0x0 1. "PKT_RD_BITMAP1,Packet read bitmap[1]" "0,1"
newline
bitfld.byte 0x0 0. "PKT_RD_BITMAP0,Packet read bitmap[0]" "0,1"
line.byte 0x1 "PKT_RD_BITMAP1,Packet Read Bitmap 1"
bitfld.byte 0x1 7. "PKT_RD_BITMAP15,Packet read bitmap[15]." "0,1"
newline
bitfld.byte 0x1 6. "PKT_RD_BITMAP14,Packet read bitmap[14]" "0,1"
newline
bitfld.byte 0x1 5. "PKT_RD_BITMAP13,Packet read bitmap[13]" "0,1"
newline
bitfld.byte 0x1 4. "PKT_RD_BITMAP12,Packet read bitmap[12]" "0,1"
newline
bitfld.byte 0x1 3. "PKT_RD_BITMAP11,Packet read bitmap[11]" "0,1"
newline
bitfld.byte 0x1 2. "PKT_RD_BITMAP10,Packet read bitmap[10]" "0,1"
newline
bitfld.byte 0x1 1. "PKT_RD_BITMAP9,Packet read bitmap[9]" "0,1"
newline
bitfld.byte 0x1 0. "PKT_RD_BITMAP8,Packet read bitmap[8]" "0,1"
line.byte 0x2 "PKT_RD_BITMAP2,Packet Read Bitmap 2"
bitfld.byte 0x2 7. "PKT_RD_BITMAP23,Packet read bitmap[23]." "0,1"
newline
bitfld.byte 0x2 6. "PKT_RD_BITMAP22,Packet read bitmap[22]" "0,1"
newline
bitfld.byte 0x2 5. "PKT_RD_BITMAP21,Packet read bitmap[21]" "0,1"
newline
bitfld.byte 0x2 4. "PKT_RD_BITMAP20,Packet read bitmap[20]" "0,1"
newline
bitfld.byte 0x2 3. "PKT_RD_BITMAP19,Packet read bitmap[19]" "0,1"
newline
bitfld.byte 0x2 2. "PKT_RD_BITMAP18,Packet read bitmap[18]" "0,1"
newline
bitfld.byte 0x2 1. "PKT_RD_BITMAP17,Packet read bitmap[17]" "0,1"
newline
bitfld.byte 0x2 0. "PKT_RD_BITMAP16,Packet read bitmap[16]" "0,1"
line.byte 0x3 "PKT_RD_BITMAP3,Packet Read Bitmap 3"
bitfld.byte 0x3 7. "PKT_RD_BITMAP31,Packet read bitmap[31]." "0,1"
newline
bitfld.byte 0x3 6. "PKT_RD_BITMAP30,Packet read bitmap[30]" "0,1"
newline
bitfld.byte 0x3 5. "PKT_RD_BITMAP29,Packet read bitmap[29]" "0,1"
newline
bitfld.byte 0x3 4. "PKT_RD_BITMAP28,Packet read bitmap[28]" "0,1"
newline
bitfld.byte 0x3 3. "PKT_RD_BITMAP27,Packet read bitmap[27]" "0,1"
newline
bitfld.byte 0x3 2. "PKT_RD_BITMAP26,Packet read bitmap[26]" "0,1"
newline
bitfld.byte 0x3 1. "PKT_RD_BITMAP25,Packet read bitmap[25]" "0,1"
newline
bitfld.byte 0x3 0. "PKT_RD_BITMAP24,Packet read bitmap[24]" "0,1"
line.byte 0x4 "PKT_WR_BITMAP0,Packet Write Bitmap 0"
bitfld.byte 0x4 7. "PKT_WR_BITMAP7,Packet write bitmap[7]." "0,1"
newline
bitfld.byte 0x4 6. "PKT_WR_BITMAP6,Packet write bitmap[6]" "0,1"
newline
bitfld.byte 0x4 5. "PKT_WR_BITMAP5,Packet write bitmap[5]" "0,1"
newline
bitfld.byte 0x4 4. "PKT_WR_BITMAP4,Packet write bitmap[4]" "0,1"
newline
bitfld.byte 0x4 3. "PKT_WR_BITMAP3,Packet write bitmap[3]" "0,1"
newline
bitfld.byte 0x4 2. "PKT_WR_BITMAP2,Packet write bitmap[2]" "0,1"
newline
bitfld.byte 0x4 1. "PKT_WR_BITMAP1,Packet write bitmap[1]" "0,1"
newline
bitfld.byte 0x4 0. "PKT_WR_BITMAP0,Packet write bitmap[0]" "0,1"
line.byte 0x5 "PKT_WR_BITMAP1,Packet Write Bitmap 1"
bitfld.byte 0x5 7. "PKT_WR_BITMAP15,Packet write bitmap[15]." "0,1"
newline
bitfld.byte 0x5 6. "PKT_WR_BITMAP14,Packet write bitmap[14]" "0,1"
newline
bitfld.byte 0x5 5. "PKT_WR_BITMAP13,Packet write bitmap[13]" "0,1"
newline
bitfld.byte 0x5 4. "PKT_WR_BITMAP12,Packet write bitmap[12]" "0,1"
newline
bitfld.byte 0x5 3. "PKT_WR_BITMAP11,Packet write bitmap[11]" "0,1"
newline
bitfld.byte 0x5 2. "PKT_WR_BITMAP10,Packet write bitmap[10]" "0,1"
newline
bitfld.byte 0x5 1. "PKT_WR_BITMAP9,Packet write bitmap[9]" "0,1"
newline
bitfld.byte 0x5 0. "PKT_WR_BITMAP8,Packet write bitmap[8]" "0,1"
line.byte 0x6 "PKT_WR_BITMAP2,Packet Write Bitmap 2"
bitfld.byte 0x6 7. "PKT_WR_BITMAP23,Packet write bitmap[23]." "0,1"
newline
bitfld.byte 0x6 6. "PKT_WR_BITMAP22,Packet write bitmap[22]" "0,1"
newline
bitfld.byte 0x6 5. "PKT_WR_BITMAP21,Packet write bitmap[21]" "0,1"
newline
bitfld.byte 0x6 4. "PKT_WR_BITMAP20,Packet write bitmap[20]" "0,1"
newline
bitfld.byte 0x6 3. "PKT_WR_BITMAP19,Packet write bitmap[19]" "0,1"
newline
bitfld.byte 0x6 2. "PKT_WR_BITMAP18,Packet write bitmap[18]" "0,1"
newline
bitfld.byte 0x6 1. "PKT_WR_BITMAP17,Packet write bitmap[17]" "0,1"
newline
bitfld.byte 0x6 0. "PKT_WR_BITMAP16,Packet write bitmap[16]" "0,1"
line.byte 0x7 "PKT_WR_BITMAP3,Packet Write Bitmap 3"
bitfld.byte 0x7 7. "PKT_WR_BITMAP31,Packet write bitmap[31]." "0,1"
newline
bitfld.byte 0x7 6. "PKT_WR_BITMAP30,Packet write bitmap[30]" "0,1"
newline
bitfld.byte 0x7 5. "PKT_WR_BITMAP29,Packet write bitmap[29]" "0,1"
newline
bitfld.byte 0x7 4. "PKT_WR_BITMAP28,Packet write bitmap[28]" "0,1"
newline
bitfld.byte 0x7 3. "PKT_WR_BITMAP27,Packet write bitmap[27]" "0,1"
newline
bitfld.byte 0x7 2. "PKT_WR_BITMAP26,Packet write bitmap[26]" "0,1"
newline
bitfld.byte 0x7 1. "PKT_WR_BITMAP25,Packet write bitmap[25]" "0,1"
newline
bitfld.byte 0x7 0. "PKT_WR_BITMAP24,Packet write bitmap[24]" "0,1"
line.byte 0x8 "PORT0_RD_LEN0,Port 0 Packet Read Length 0"
hexmask.byte 0x8 0.--7. 1. "PORT0_RD_LEN0,Port 0 read length [7:0]"
line.byte 0x9 "PORT0_RD_LEN1,Port 0 Packet Read Length 1"
hexmask.byte 0x9 0.--7. 1. "PORT0_RD_LEN1,Port 0 read length [15:8]"
line.byte 0xA "PORT1_RD_LEN0,Port 1 Packet Read Length 0"
hexmask.byte 0xA 0.--7. 1. "PORT1_RD_LEN0,Port 1 read length [7:0]"
line.byte 0xB "PORT1_RD_LEN1,Port 1 Packet Read Length 1"
hexmask.byte 0xB 0.--7. 1. "PORT1_RD_LEN1,Port 1 read length [15:8]"
line.byte 0xC "PORT2_RD_LEN0,Port 2 Packet Read Length 0"
hexmask.byte 0xC 0.--7. 1. "PORT2_RD_LEN0,Port 2 read length [7:0]"
line.byte 0xD "PORT2_RD_LEN1,Port 2 Packet Read Length 1"
hexmask.byte 0xD 0.--7. 1. "PORT2_RD_LEN1,Port 2 read length [15:8]"
line.byte 0xE "PORT3_RD_LEN0,Port 3 Packet Read Length 0"
hexmask.byte 0xE 0.--7. 1. "PORT3_RD_LEN0,Port 3 read length [7:0]"
line.byte 0xF "PORT3_RD_LEN1,Port 3 Packet Read Length 1"
hexmask.byte 0xF 0.--7. 1. "PORT3_RD_LEN1,Port 3 read length [15:8]"
line.byte 0x10 "PORT4_RD_LEN0,Port 4 Packet Read Length 0"
hexmask.byte 0x10 0.--7. 1. "PORT4_RD_LEN0,Port 4 read length [7:0]"
line.byte 0x11 "PORT4_RD_LEN1,Port 4 Packet Read Length 1"
hexmask.byte 0x11 0.--7. 1. "PORT4_RD_LEN1,Port 4 read length [15:8]"
line.byte 0x12 "PORT5_RD_LEN0,Port 5 Packet Read Length 0"
hexmask.byte 0x12 0.--7. 1. "PORT5_RD_LEN0,Port 5 read length [7:0]"
line.byte 0x13 "PORT5_RD_LEN1,Port 5 Packet Read Length 1"
hexmask.byte 0x13 0.--7. 1. "PORT5_RD_LEN1,Port 5 read length [15:8]"
line.byte 0x14 "PORT6_RD_LEN0,Port 6 Packet Read Length 0"
hexmask.byte 0x14 0.--7. 1. "PORT6_RD_LEN0,Port 6 read length [7:0]"
line.byte 0x15 "PORT6_RD_LEN1,Port 6 Packet Read Length 1"
hexmask.byte 0x15 0.--7. 1. "PORT6_RD_LEN1,Port 6 read length [15:8]"
line.byte 0x16 "PORT7_RD_LEN0,Port 7 Packet Read Length 0"
hexmask.byte 0x16 0.--7. 1. "PORT7_RD_LEN0,Port 7 read length [7:0]"
line.byte 0x17 "PORT7_RD_LEN1,Port 7 Packet Read Length 1"
hexmask.byte 0x17 0.--7. 1. "PORT7_RD_LEN1,Port 7 read length [15:8]"
line.byte 0x18 "PORT8_RD_LEN0,Port 8 Packet Read Length 0"
hexmask.byte 0x18 0.--7. 1. "PORT8_RD_LEN0,Port 8 read length [7:0]"
line.byte 0x19 "PORT8_RD_LEN1,Port 8 Packet Read Length 1"
hexmask.byte 0x19 0.--7. 1. "PORT8_RD_LEN1,Port 8 read length [15:8]"
line.byte 0x1A "PORT9_RD_LEN0,Port 9 Packet Read Length 0"
hexmask.byte 0x1A 0.--7. 1. "PORT9_RD_LEN0,Port 9 read length [7:0]"
line.byte 0x1B "PORT9_RD_LEN1,Port 9 Packet Read Length 1"
hexmask.byte 0x1B 0.--7. 1. "PORT9_RD_LEN1,Port 9 read length [15:8]"
line.byte 0x1C "PORT10_RD_LEN0,Port 10 Packet Read Length 0"
hexmask.byte 0x1C 0.--7. 1. "PORT10_RD_LEN0,Port 10 read length [7:0]"
line.byte 0x1D "PORT10_RD_LEN1,Port 10 Packet Read Length 1"
hexmask.byte 0x1D 0.--7. 1. "PORT10_RD_LEN1,Port 10 read length [15:8]"
line.byte 0x1E "PORT11_RD_LEN0,Port 11 Packet Read Length 0"
hexmask.byte 0x1E 0.--7. 1. "PORT11_RD_LEN0,Port 11 read length [7:0]"
line.byte 0x1F "PORT11_RD_LEN1,Port 11 Packet Read Length 1"
hexmask.byte 0x1F 0.--7. 1. "PORT11_RD_LEN1,Port 11 read length [15:8]"
line.byte 0x20 "PORT12_RD_LEN0,Port 12 Packet Read Length 0"
hexmask.byte 0x20 0.--7. 1. "PORT12_RD_LEN0,Port 12 read length [7:0]"
line.byte 0x21 "PORT12_RD_LEN1,Port 12 Packet Read Length 1"
hexmask.byte 0x21 0.--7. 1. "PORT12_RD_LEN1,Port 12 read length [15:8]"
line.byte 0x22 "PORT13_RD_LEN0,Port 13 Packet Read Length 0"
hexmask.byte 0x22 0.--7. 1. "PORT13_RD_LEN0,Port 13 read length [7:0]"
line.byte 0x23 "PORT13_RD_LEN1,Port 13 Packet Read Length 1"
hexmask.byte 0x23 0.--7. 1. "PORT13_RD_LEN1,Port 13 read length [15:8]"
line.byte 0x24 "PORT14_RD_LEN0,Port 14 Packet Read Length 0"
hexmask.byte 0x24 0.--7. 1. "PORT14_RD_LEN0,Port 14 read length [7:0]"
line.byte 0x25 "PORT14_RD_LEN1,Port 14 Packet Read Length 1"
hexmask.byte 0x25 0.--7. 1. "PORT14_RD_LEN1,Port 14 read length [15:8]"
line.byte 0x26 "PORT15_RD_LEN0,Port 15 Packet Read Length 0"
hexmask.byte 0x26 0.--7. 1. "PORT15_RD_LEN0,Port 15 read length [7:0]"
line.byte 0x27 "PORT15_RD_LEN1,Port 15 Packet Read Length 1"
hexmask.byte 0x27 0.--7. 1. "PORT15_RD_LEN1,Port 15 read length [15:8]"
line.byte 0x28 "PORT16_RD_LEN0,Port 16 Packet Read Length 0"
hexmask.byte 0x28 0.--7. 1. "PORT16_RD_LEN0,Port 16 read length [7:0]"
line.byte 0x29 "PORT16_RD_LEN1,Port 16 Packet Read Length 1"
hexmask.byte 0x29 0.--7. 1. "PORT16_RD_LEN1,Port 16 read length [15:8]"
line.byte 0x2A "PORT17_RD_LEN0,Port 17 Packet Read Length 0"
hexmask.byte 0x2A 0.--7. 1. "PORT17_RD_LEN0,Port 17 read length [7:0]"
line.byte 0x2B "PORT17_RD_LEN1,Port 17 Packet Read Length 1"
hexmask.byte 0x2B 0.--7. 1. "PORT17_RD_LEN1,Port 17 read length [15:8]"
line.byte 0x2C "PORT18_RD_LEN0,Port 18 Packet Read Length 0"
hexmask.byte 0x2C 0.--7. 1. "PORT18_RD_LEN0,Port 18 read length [7:0]"
line.byte 0x2D "PORT18_RD_LEN1,Port 18 Packet Read Length 1"
hexmask.byte 0x2D 0.--7. 1. "PORT18_RD_LEN1,Port 18 read length [15:8]"
line.byte 0x2E "PORT19_RD_LEN0,Port 19 Packet Read Length 0"
hexmask.byte 0x2E 0.--7. 1. "PORT19_RD_LEN0,Port 19 read length [7:0]"
line.byte 0x2F "PORT19_RD_LEN1,Port 19 Packet Read Length 1"
hexmask.byte 0x2F 0.--7. 1. "PORT19_RD_LEN1,Port 19 read length [15:8]"
line.byte 0x30 "PORT20_RD_LEN0,Port 20 Packet Read Length 0"
hexmask.byte 0x30 0.--7. 1. "PORT20_RD_LEN0,Port 20 read length [7:0]"
line.byte 0x31 "PORT20_RD_LEN1,Port 20 Packet Read Length 1"
hexmask.byte 0x31 0.--7. 1. "PORT20_RD_LEN1,Port 20 read length [15:8]"
line.byte 0x32 "PORT21_RD_LEN0,Port 21 Packet Read Length 0"
hexmask.byte 0x32 0.--7. 1. "PORT21_RD_LEN0,Port 21 read length [7:0]"
line.byte 0x33 "PORT21_RD_LEN1,Port 21 Packet Read Length 1"
hexmask.byte 0x33 0.--7. 1. "PORT21_RD_LEN1,Port 21 read length [15:8]"
line.byte 0x34 "PORT22_RD_LEN0,Port 22 Packet Read Length 0"
hexmask.byte 0x34 0.--7. 1. "PORT22_RD_LEN0,Port 22 read length [7:0]"
line.byte 0x35 "PORT22_RD_LEN1,Port 22 Packet Read Length 1"
hexmask.byte 0x35 0.--7. 1. "PORT22_RD_LEN1,Port 22 read length [15:8]"
line.byte 0x36 "PORT23_RD_LEN0,Port 23 Packet Read Length 0"
hexmask.byte 0x36 0.--7. 1. "PORT23_RD_LEN0,Port 23 read length [7:0]"
line.byte 0x37 "PORT23_RD_LEN1,Port 23 Packet Read Length 1"
hexmask.byte 0x37 0.--7. 1. "PORT23_RD_LEN1,Port 23 read length [15:8]"
line.byte 0x38 "PORT24_RD_LEN0,Port 24 Packet Read Length 0"
hexmask.byte 0x38 0.--7. 1. "PORT24_RD_LEN0,Port 24 read length [7:0]"
line.byte 0x39 "PORT24_RD_LEN1,Port 24 Packet Read Length 1"
hexmask.byte 0x39 0.--7. 1. "PORT24_RD_LEN1,Port 24 read length [15:8]"
line.byte 0x3A "PORT25_RD_LEN0,Port 25 Packet Read Length 0"
hexmask.byte 0x3A 0.--7. 1. "PORT25_RD_LEN0,Port 25 read length [7:0]"
line.byte 0x3B "PORT25_RD_LEN1,Port 25 Packet Read Length 1"
hexmask.byte 0x3B 0.--7. 1. "PORT25_RD_LEN1,Port 25 read length [15:8]"
line.byte 0x3C "PORT26_RD_LEN0,Port 26 Packet Read Length 0"
hexmask.byte 0x3C 0.--7. 1. "PORT26_RD_LEN0,Port 26 read length [7:0]"
line.byte 0x3D "PORT26_RD_LEN1,Port 26 Packet Read Length 1"
hexmask.byte 0x3D 0.--7. 1. "PORT26_RD_LEN1,Port 26 read length [15:8]"
line.byte 0x3E "PORT27_RD_LEN0,Port 27 Packet Read Length 0"
hexmask.byte 0x3E 0.--7. 1. "PORT27_RD_LEN0,Port 27 read length [7:0]"
line.byte 0x3F "PORT27_RD_LEN1,Port 27 Packet Read Length 1"
hexmask.byte 0x3F 0.--7. 1. "PORT27_RD_LEN1,Port 27 read length [15:8]"
line.byte 0x40 "PORT28_RD_LEN0,Port 28 Packet Read Length 0"
hexmask.byte 0x40 0.--7. 1. "PORT28_RD_LEN0,Port 28 read length [7:0]"
line.byte 0x41 "PORT28_RD_LEN1,Port 28 Packet Read Length 1"
hexmask.byte 0x41 0.--7. 1. "PORT28_RD_LEN1,Port 28 read length [15:8]"
line.byte 0x42 "PORT29_RD_LEN0,Port 29 Packet Read Length 0"
hexmask.byte 0x42 0.--7. 1. "PORT29_RD_LEN0,Port 29 read length [7:0]"
line.byte 0x43 "PORT29_RD_LEN1,Port 29 Packet Read Length 1"
hexmask.byte 0x43 0.--7. 1. "PORT29_RD_LEN1,Port 29 read length [15:8]"
line.byte 0x44 "PORT30_RD_LEN0,Port 30 Packet Read Length 0"
hexmask.byte 0x44 0.--7. 1. "PORT30_RD_LEN0,Port 30 read length [7:0]"
line.byte 0x45 "PORT30_RD_LEN1,Port 30 Packet Read Length 1"
hexmask.byte 0x45 0.--7. 1. "PORT30_RD_LEN1,Port 30 read length [15:8]"
line.byte 0x46 "PORT31_RD_LEN0,Port 31 Packet Read Length 0"
hexmask.byte 0x46 0.--7. 1. "PORT31_RD_LEN0,Port 31 read length [7:0]"
line.byte 0x47 "PORT31_RD_LEN1,Port 31 Packet Read Length 1"
hexmask.byte 0x47 0.--7. 1. "PORT31_RD_LEN1,Port 31 read length [15:8]"
rgroup.byte 0x58++0x0
line.byte 0x0 "HOST_RESTART,Host Transfer Status"
bitfld.byte 0x0 2. "DNLD_CRC_ERR,Download Cyclic Redundancy Check Error This bit is set by HW if there is a data CRC error after a data block is downloaded." "0,1"
newline
bitfld.byte 0x0 1. "UPLD_RESTART,Upload Restart Host sets this bit for the card to retransmit packet." "0,1"
newline
bitfld.byte 0x0 0. "DNLD_RESTART,Download Restart Host sets this bit for the card to retransmit packet." "0,1"
group.byte 0x59++0x4
line.byte 0x0 "FN_CARD_INTMASK,Function Card Interrupt Mask"
bitfld.byte 0x0 0.--2. "FN_CARD_INT_MASK,Function card interrupt masks." "0,1,2,3,4,5,6,7"
line.byte 0x1 "Q_PRT_RANGE0,Queue Port Range 0"
bitfld.byte 0x1 4.--6. "Q1_PRT_RANGE,Queue 1 Port Range Number of ports assigned per queue." "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x1 0.--2. "Q0_PRT_RANGE,Queue 0 Port Range Number of ports assigned per queue." "0,1,2,3,4,5,6,7"
line.byte 0x2 "Q_PRT_RANGE1,Queue Port Range 1"
bitfld.byte 0x2 4.--6. "Q3_PRT_RANGE,Queue 3 Port Range Number of ports assigned per queue." "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x2 0.--2. "Q2_PRT_RANGE,Queue 2 Port Range Number of ports assigned per queue." "0,1,2,3,4,5,6,7"
line.byte 0x3 "C2H_INTEVENT0,Card to Host Event 0"
bitfld.byte 0x3 7. "CMD_PORT_DNLD_RDY,Command Port Download Ready" "0,1"
newline
bitfld.byte 0x3 6. "CMD_PORT_UPLD_RDY,Command Port Upload Ready" "0,1"
newline
bitfld.byte 0x3 4.--5. "CARD_TO_HOST_EVENT,Firmware controlled events to host." "0,1,2,3"
newline
rbitfld.byte 0x3 3. "IO_READY,I/O Ready Indicator SD target device accepts CMD53 only after the previous CMD53 has finished." "0,1"
newline
bitfld.byte 0x3 2. "CIS_CARD_RDY,Card Information Structure Card Ready Firmware sets this bit after CIS table is initialized" "0,1"
newline
bitfld.byte 0x3 1. "Q0_UPLD_CARD_RDY,Queue 0 Upload Card Ready Firmware sets this bit when one packet is ready." "0,1"
newline
bitfld.byte 0x3 0. "Q0_DNLD_CARD_RDY,Queue 0 Download Card Ready Firmware sets this bit when one packet is ready." "0,1"
line.byte 0x4 "C2H_INTEVENT1,Card to Host Event 1"
bitfld.byte 0x4 5. "Q3_UPLD_CARD_RDY,Queue 3 Upload Card Ready" "0,1"
newline
bitfld.byte 0x4 4. "Q2_UPLD_CARD_RDY,Queue 2 Upload Card Ready" "0,1"
newline
bitfld.byte 0x4 3. "Q1_UPLD_CARD_RDY,Queue 1 Upload Card Ready" "0,1"
newline
bitfld.byte 0x4 2. "Q3_DNLD_CARD_RDY,Queue 3 Download Card Ready" "0,1"
newline
bitfld.byte 0x4 1. "Q2_DNLD_CARD_RDY,Queue 2 Download Card Ready" "0,1"
newline
bitfld.byte 0x4 0. "Q1_DNLD_CARD_RDY,Queue 1 Download Card Ready" "0,1"
group.byte 0x60++0x2
line.byte 0x0 "CARD_INTMASK0,Card Interrupt Mask 0"
hexmask.byte 0x0 0.--7. 1. "CARD_INT_MASK0,Host to Card Interrupt Mask[7:0] 0 = disable host to card interrupt 1 = enable host to card interrupt"
line.byte 0x1 "CARD_INTMASK1,Card Interrupt Mask 1"
hexmask.byte 0x1 0.--7. 1. "CARD_INT_MASK1,Host to Card Interrupt Mask[15:8] 0 = disable host to card interrupt 1 = enable host to card interrupt"
line.byte 0x2 "CARD_INTMASK2,Card Interrupt Mask 2"
hexmask.byte 0x2 0.--7. 1. "CARD_INT_MASK2,Host to Card Interrupt Mask [23:16] 0 = disable host to card interrupt 1 = enable host to card interrupt"
rgroup.byte 0x64++0x2
line.byte 0x0 "CARD_INTSTATUS0,Card Interrupt Status 0"
bitfld.byte 0x0 7. "HOST_TO_CARD_EVENT,Host interrupt to card" "0,1"
newline
bitfld.byte 0x0 6. "OVERFLOW_CARD_INT,Fifo overflow" "0,1"
newline
bitfld.byte 0x0 5. "UNDERFLOW_CARD_INT,Fifo underflow" "0,1"
newline
bitfld.byte 0x0 4. "HOST_PWR_UP_INT,Power up interrupt" "0,1"
newline
bitfld.byte 0x0 3. "HOST_PWR_DOWN_INT,Power down interrupt" "0,1"
newline
bitfld.byte 0x0 2. "ABORT_CARD_INT,Abort CardInt event when abort pulse." "0,1"
newline
bitfld.byte 0x0 1. "Q0_UPLD_CARD_INT,Queue 0 UpldCardInt event when (IO_Ready) && SD_Finish." "0,1"
newline
bitfld.byte 0x0 0. "Q0_DNLD_CARD_INT,Queue 0 DnldCardInt event when (IO_Write) && DMA_Finish." "0,1"
line.byte 0x1 "CARD_INTSTATUS1,Card Interrupt Status 1"
bitfld.byte 0x1 7. "CMD53_RD_ERR_INT,This event is set if host issues cmd53 read access to off-domain register during sleep mode." "0,1"
newline
bitfld.byte 0x1 6. "CMD53_WR_ERR_INT,This event is set if host issues cmd53 write access to off-domain register during sleep mode." "0,1"
newline
bitfld.byte 0x1 5. "CMD52_RD_ERR_INT,This event is set if host issues cmd52 read access to off-domain register during sleep mode." "0,1"
newline
bitfld.byte 0x1 4. "CMD52_WR_ERR_INT,This event is set if host issues cmd52 write access to off-domain register during sleep mode." "0,1"
newline
bitfld.byte 0x1 3. "CMD_PORT_DNLD_CARD_INT,This event is set if current cmd53 download/tx data transfer is completed." "0,1"
newline
bitfld.byte 0x1 2. "CMD_PORT_UPLD_CARD_INT,This event is set if current cmd53 upload/rx data transfer is completed." "0,1"
newline
bitfld.byte 0x1 1. "IO_DISABLE_INT,This event is set when IO_ENABLE[fn] at FN0 0x02 is transitioned from 1-to-0 that is written by host" "0,1"
newline
bitfld.byte 0x1 0. "IO_ENABLE_INT,This event is set when IO_ENABLE[fn] at FN0 0x02 is transitioned from 0-to-1 that is written by host" "0,1"
line.byte 0x2 "CARD_INTSTATUS2,Card Interrupt Status 2"
bitfld.byte 0x2 7. "REGION_ACCESS_ABORT_INT,Region access abort CardInt event." "0,1"
newline
bitfld.byte 0x2 6. "HOST_RST_INT,Host reset event." "0,1"
newline
bitfld.byte 0x2 5. "Q3_UPLD_CARD_INT,Queue 3 UpldCardInt event when (IO_Ready) && SD_Finish." "0,1"
newline
bitfld.byte 0x2 4. "Q2_UPLD_CARD_INT,Queue 2 UpldCardInt event when (IO_Ready) && SD_Finish." "0,1"
newline
bitfld.byte 0x2 3. "Q1_UPLD_CARD_INT,Queue 1 UpldCardInt event when (IO_Ready) && SD_Finish." "0,1"
newline
bitfld.byte 0x2 2. "Q3_DNLD_CARD_INT,Queue 3 DnldCardInt event when (IO_Write) && DMA_Finish." "0,1"
newline
bitfld.byte 0x2 1. "Q2_DNLD_CARD_INT,Queue 2 DnldCardInt event when (IO_Write) && DMA_Finish." "0,1"
newline
bitfld.byte 0x2 0. "Q1_DNLD_CARD_INT,Queue 1 DnldCardInt event when (IO_Write) && DMA_Finish." "0,1"
group.byte 0x68++0x2
line.byte 0x0 "CARD_INTRSR0,Card Interrupt Reset Select 0"
hexmask.byte 0x0 0.--7. 1. "CARD_INT_RSR0,Card Interrupt Reset Select[7:0] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
line.byte 0x1 "CARD_INTRSR1,Card Interrupt Reset Select 1"
hexmask.byte 0x1 0.--7. 1. "CARD_INT_RSR1,Card Interrupt Reset Select[15:8] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
line.byte 0x2 "CARD_INTRSR2,Card Interrupt Reset Select 2"
hexmask.byte 0x2 0.--7. 1. "CARD_INT_RSR2,Card Interrupt Reset Select[23:16] 0 = ISR bit clears when 0 is written to it 1 = ISR bit clears when read"
group.byte 0x6C++0x9
line.byte 0x0 "RD_BASE0,SQ Read Base Address 0"
hexmask.byte 0x0 0.--7. 1. "SQ_READ_ADDR0,SQ read base address bit [7:0]."
line.byte 0x1 "RD_BASE1,SQ Read Base Address 1"
hexmask.byte 0x1 0.--7. 1. "SQ_READ_ADDR1,SQ read base address bit [15:8]"
line.byte 0x2 "RD_BASE2,SQ Read Base Address 2"
hexmask.byte 0x2 0.--7. 1. "SQ_READ_ADDR2,SQ read base address bit [23:16]"
line.byte 0x3 "RD_BASE3,SQ Read Base Address 3"
hexmask.byte 0x3 0.--7. 1. "SQ_READ_ADDR3,SQ read base address bit [31:24]"
line.byte 0x4 "WR_BASE0,SQ Write Base Address 0"
hexmask.byte 0x4 0.--7. 1. "SQ_WRITE_ADDR0,SQ Write base address bit [7:0]."
line.byte 0x5 "WR_BASE1,SQ Write Base Address 1"
hexmask.byte 0x5 0.--7. 1. "SQ_WRITE_ADDR1,SQ Write base address bit [15:8]"
line.byte 0x6 "WR_BASE2,SQ Write Base Address 2"
hexmask.byte 0x6 0.--7. 1. "SQ_WRITE_ADDR2,SQ Write base address bit [23:16]"
line.byte 0x7 "WR_BASE3,SQ Write Base Address 3"
hexmask.byte 0x7 0.--7. 1. "SQ_WRITE_ADDR3,SQ Write base address bit [31:24]"
line.byte 0x8 "RD_IDX,Read Base Address Index"
hexmask.byte 0x8 0.--4. 1. "RD_INDEX,Index to current read base address [15:0]"
line.byte 0x9 "WR_IDX,Write Base Address Index"
hexmask.byte 0x9 0.--4. 1. "WR_INDEX,Index to current write base address [15:0]"
group.byte 0x78++0x7
line.byte 0x0 "APU_SLP_RDY_EN,APU Sleep Ready Enable"
bitfld.byte 0x0 0. "APU_SLP_RDY_EN,APU Sleep Ready Enable If this bit is enabled any pending host interrupt status will deassert sdu_apu_slp_rdy to prevent APU from going into sleep mode." "0,1"
line.byte 0x1 "REGION0_ADDR0,Security Access Address0 for Region 0"
hexmask.byte 0x1 0.--7. 1. "REGION0_ADDR0,Accessible region 0 address [7:0]."
line.byte 0x2 "REGION1_ADDR0,Security Access Address0 for Region 1"
hexmask.byte 0x2 0.--7. 1. "REGION1_ADDR0,Accessible region 1 address [7:0]."
line.byte 0x3 "REGION2_ADDR0,Security Access Address0 for Region 2"
hexmask.byte 0x3 0.--7. 1. "REGION2_ADDR0,Accessible region 2 address [7:0]."
line.byte 0x4 "HOST_ERR_WKUP_EN,Host Error Wakeup Enable"
bitfld.byte 0x4 4.--5. "TESTBUS_BIT_SEL_EN,If bit 0 is 1 testbus_lo bits are individually selected by TESTBUS_BIT_SEL0 and TESTBUS_BIT_SEL1." "0,1,2,3"
newline
bitfld.byte 0x4 3. "CMD53_RD_ERR_WKUP_EN,CMD53 Read Error Wakeup Enable If host issues CMD53 read access during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
newline
bitfld.byte 0x4 2. "CMD53_WR_ERR_WKUP_EN,CMD53 Write Error Wakeup Enable If host issues CMD53 write access during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
newline
bitfld.byte 0x4 1. "CMD52_RD_ERR_WKUP_EN,CMD52 Read Error Wakeup Enable If host issues CMD52 read access to any off-domain register during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
newline
bitfld.byte 0x4 0. "CMD52_WR_ERR_WKUP_EN,CMD52 Write Error Wakeup Enable If host issues CMD52 write access to any off-domain register during sleep mode setting this bit will trigger wakeup event to the APU." "0,1"
line.byte 0x5 "REGION0_MASK_ADDR0,Security Access Mask Address0 for Region 0"
hexmask.byte 0x5 0.--7. 1. "REGION0_MASK_ADDR0,Region 0 mask address [7:0]."
line.byte 0x6 "REGION1_MASK_ADDR0,Security Access Mask Address0 for Region 1"
hexmask.byte 0x6 0.--7. 1. "REGION1_MASK_ADDR0,Region 1 mask address [7:0]."
line.byte 0x7 "REGION2_MASK_ADDR0,Security Access Mask Address0 for Region 2"
hexmask.byte 0x7 0.--7. 1. "REGION2_MASK_ADDR0,Region 2 mask address [7:0]."
rgroup.byte 0x80++0x5
line.byte 0x0 "HOST_ERR_CMD0,Host Error Command 0"
hexmask.byte 0x0 0.--7. 1. "HOST_ERR_CMD0,Host Error Command[7:0] Capture 48-bit content of either CMD52 or CMD53 depending on one of the four error conditions in CARD_INTSTATUS1[7:4]."
line.byte 0x1 "HOST_ERR_CMD1,Host Error Command 1"
hexmask.byte 0x1 0.--7. 1. "HOST_ERR_CMD1,Host Error Command[15:8] Capture 48-bit content of either CMD52 or CMD53 depending on one of the four error conditions in CARD_INTSTATUS1[7:4]."
line.byte 0x2 "HOST_ERR_CMD2,Host Error Command 2"
hexmask.byte 0x2 0.--7. 1. "HOST_ERR_CMD2,Host Error Command[23:16] Capture 48-bit content of either CMD52 or CMD53 depending on one of the four error conditions in CARD_INTSTATUS1[7:4]."
line.byte 0x3 "HOST_ERR_CMD3,Host Error Command 3"
hexmask.byte 0x3 0.--7. 1. "HOST_ERR_CMD3,Host Error Command[31:24] Capture 48-bit content of either CMD52 or CMD53 depending on one of the four error conditions in CARD_INTSTATUS1[7:4]."
line.byte 0x4 "HOST_ERR_CMD4,Host Error Command 4"
hexmask.byte 0x4 0.--7. 1. "HOST_ERR_CMD4,Host Error Command[39:32] Capture 48-bit content of either CMD52 or CMD53 depending on one of the four error conditions in CARD_INTSTATUS1[7:4]."
line.byte 0x5 "HOST_ERR_CMD5,Host Error Command 5"
hexmask.byte 0x5 0.--7. 1. "HOST_ERR_CMD5,Host Error Command[47:40] Capture 48-bit content of either CMD52 or CMD53 depending on one of the four error conditions in CARD_INTSTATUS1[7:4]."
group.byte 0x86++0x1
line.byte 0x0 "REGION3_ADDR0,Security Access Address0 for Region 3"
hexmask.byte 0x0 0.--7. 1. "REGION3_ADDR0,Accessible region 3 address [7:0]"
line.byte 0x1 "REGION3_MASK_ADDR0,Security Access Mask Address0 for Region 3"
hexmask.byte 0x1 0.--7. 1. "REGION3_MASK_ADDR0,Region 3 mask address [7:0]"
wgroup.byte 0x88++0x7
line.byte 0x0 "PKT_WR_BITMAP_CLR0,Packet Write Bitmap Clear 0"
hexmask.byte 0x0 0.--7. 1. "PKT_WR_BITMAP_SW_CLR0,Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit."
line.byte 0x1 "PKT_WR_BITMAP_CLR1,Packet Write Bitmap Clear 1"
hexmask.byte 0x1 0.--7. 1. "PKT_WR_BITMAP_SW_CLR1,Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit."
line.byte 0x2 "PKT_WR_BITMAP_CLR2,Packet Write Bitmap Clear 2"
hexmask.byte 0x2 0.--7. 1. "PKT_WR_BITMAP_SW_CLR2,Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit."
line.byte 0x3 "PKT_WR_BITMAP_CLR3,Packet Write Bitmap Clear 3"
hexmask.byte 0x3 0.--7. 1. "PKT_WR_BITMAP_SW_CLR3,Setting 1 to each bit will clear the corresponding pkt_wr_bitmap bit."
line.byte 0x4 "PKT_RD_BITMAP_CLR0,Packet Read Bitmap Clear 0"
hexmask.byte 0x4 0.--7. 1. "PKT_RD_BITMAP_SW_CLR0,Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit."
line.byte 0x5 "PKT_RD_BITMAP_CLR1,Packet Read Bitmap Clear 1"
hexmask.byte 0x5 0.--7. 1. "PKT_RD_BITMAP_SW_CLR1,Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit."
line.byte 0x6 "PKT_RD_BITMAP_CLR2,Packet Read Bitmap Clear 2"
hexmask.byte 0x6 0.--7. 1. "PKT_RD_BITMAP_SW_CLR2,Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit."
line.byte 0x7 "PKT_RD_BITMAP_CLR3,Packet Read Bitmap Clear 3"
hexmask.byte 0x7 0.--7. 1. "PKT_RD_BITMAP_SW_CLR3,Setting 1 to each bit will clear the corresponding pkt_rd_bitmap bit."
group.byte 0x90++0x3
line.byte 0x0 "HOST_INT_ACT_MASK_EN0,Host Interrupt Active Mask Enable 0"
hexmask.byte 0x0 0.--7. 1. "HOST_INT_ACT_MASK_EN0,Enable host interrupt controller active mask [7:0]"
line.byte 0x1 "HOST_INT_ACT_MASK_EN1,Host Interrupt Active Mask Enable 1"
hexmask.byte 0x1 0.--7. 1. "HOST_INT_ACT_MASK_EN1,Enable host interrupt controller active mask [15:8]"
line.byte 0x2 "HOST_INT_ACT_MASK_EN2,Host Interrupt Active Mask Enable 2"
hexmask.byte 0x2 0.--7. 1. "HOST_INT_ACT_MASK_EN2,Enable host interrupt controller active mask [23:16]"
line.byte 0x3 "HOST_INT_ACT_MASK_EN3,Host Interrupt Active Mask Enable 3"
hexmask.byte 0x3 0.--7. 1. "HOST_INT_ACT_MASK_EN3,Enable host interrupt controller active mask [31:24]"
wgroup.byte 0x94++0x3
line.byte 0x0 "HOST_INT_ACT_MASK_CLR0,Host Interrupt Active Mask Clear 0"
hexmask.byte 0x0 0.--7. 1. "HOST_INT_ACT_MASK_CLR0,Host interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding host interrupt active mask bit."
line.byte 0x1 "HOST_INT_ACT_MASK_CLR1,Host Interrupt Active Mask Clear 1"
hexmask.byte 0x1 0.--7. 1. "HOST_INT_ACT_MASK_CLR1,Host interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding host interrupt active mask bit."
line.byte 0x2 "HOST_INT_ACT_MASK_CLR2,Host Interrupt Active Mask Clear 2"
hexmask.byte 0x2 0.--7. 1. "HOST_INT_ACT_MASK_CLR2,Host interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding host interrupt active mask bit."
line.byte 0x3 "HOST_INT_ACT_MASK_CLR3,Host Interrupt Active Mask Clear 3"
hexmask.byte 0x3 0.--7. 1. "HOST_INT_ACT_MASK_CLR3,Host interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding host interrupt active mask bit."
rgroup.byte 0x98++0x3
line.byte 0x0 "HOST_INT_ACT_MASK_STATUS0,Host Interrupt Active Mask Status 0"
hexmask.byte 0x0 0.--7. 1. "HOST_INT_ACT_MASK_STATUS0,Host interrupt active mask status"
line.byte 0x1 "HOST_INT_ACT_MASK_STATUS1,Host Interrupt Active Mask Status 1"
hexmask.byte 0x1 0.--7. 1. "HOST_INT_ACT_MASK_STATUS1,Host interrupt active mask status"
line.byte 0x2 "HOST_INT_ACT_MASK_STATUS2,Host Interrupt Active Mask Status 2"
hexmask.byte 0x2 0.--7. 1. "HOST_INT_ACT_MASK_STATUS2,Host interrupt active mask status"
line.byte 0x3 "HOST_INT_ACT_MASK_STATUS3,Host Interrupt Active Mask Status 3"
hexmask.byte 0x3 0.--7. 1. "HOST_INT_ACT_MASK_STATUS3,Host interrupt active mask status"
group.byte 0x9C++0x3
line.byte 0x0 "CARD_INT_ACT_MASK_EN0,Card Interrupt Active Mask Enable 0"
hexmask.byte 0x0 0.--7. 1. "CARD_INT_ACT_MASK_EN0,Enable card interrupt controller active mask [7:0]"
line.byte 0x1 "CARD_INT_ACT_MASK_EN1,Card Interrupt Active Mask Enable 1"
hexmask.byte 0x1 0.--7. 1. "CARD_INT_ACT_MASK_EN1,Enable card interrupt controller active mask [15:8]"
line.byte 0x2 "CARD_INT_ACT_MASK_EN2,Card Interrupt Active Mask Enable 2"
hexmask.byte 0x2 0.--7. 1. "CARD_INT_ACT_MASK_EN2,Enable card interrupt controller active mask [23:16]"
line.byte 0x3 "CARD_INT_ACT_MASK_EN3,Card Interrupt Active Mask Enable 3"
hexmask.byte 0x3 0.--7. 1. "CARD_INT_ACT_MASK_EN3,Enable card interrupt controller active mask [31:24]"
wgroup.byte 0xA0++0x3
line.byte 0x0 "CARD_INT_ACT_MASK_CLR0,Card Interrupt Active Mask Clear 0"
hexmask.byte 0x0 0.--7. 1. "CARD_INT_ACT_MASK_CLR0,Card interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding card interrupt active mask bit."
line.byte 0x1 "CARD_INT_ACT_MASK_CLR1,Card Interrupt Active Mask Clear 1"
hexmask.byte 0x1 0.--7. 1. "CARD_INT_ACT_MASK_CLR1,Card interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding card interrupt active mask bit."
line.byte 0x2 "CARD_INT_ACT_MASK_CLR2,Card Interrupt Active Mask Clear 2"
hexmask.byte 0x2 0.--7. 1. "CARD_INT_ACT_MASK_CLR2,Card interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding card interrupt active mask bit."
line.byte 0x3 "CARD_INT_ACT_MASK_CLR3,Card Interrupt Active Mask Clear 3"
hexmask.byte 0x3 0.--7. 1. "CARD_INT_ACT_MASK_CLR3,Card interrupt active mask write-1-to-clear Setting 1 to each bit will clear the corresponding card interrupt active mask bit."
rgroup.byte 0xA4++0x3
line.byte 0x0 "CARD_INT_ACT_MASK_STATUS0,Card Interrupt Active Mask Status 0"
hexmask.byte 0x0 0.--7. 1. "CARD_INT_ACT_MASK_STATUS0,Card interrupt active mask status"
line.byte 0x1 "CARD_INT_ACT_MASK_STATUS1,Card Interrupt Active Mask Status 1"
hexmask.byte 0x1 0.--7. 1. "CARD_INT_ACT_MASK_STATUS1,Card interrupt active mask status"
line.byte 0x2 "CARD_INT_ACT_MASK_STATUS2,Card Interrupt Active Mask Status 2"
hexmask.byte 0x2 0.--7. 1. "CARD_INT_ACT_MASK_STATUS2,Card interrupt active mask status"
line.byte 0x3 "CARD_INT_ACT_MASK_STATUS3,Card Interrupt Active Mask Status 3"
hexmask.byte 0x3 0.--7. 1. "CARD_INT_ACT_MASK_STATUS3,Card interrupt active mask status"
group.byte 0xA8++0x19
line.byte 0x0 "REGION0_ADDR1,Security Access Address1 for Region 0"
hexmask.byte 0x0 0.--7. 1. "REGION0_ADDR1,Accessible region 0 address [15:8]."
line.byte 0x1 "REGION0_ADDR2,Security Access Address2 for Region 0"
hexmask.byte 0x1 0.--7. 1. "REGION0_ADDR2,Accessisble region 0 address [23:16]."
line.byte 0x2 "REGION0_MASK_ADDR1,Security Access Mask Address1 for Region 0"
hexmask.byte 0x2 0.--7. 1. "REGION0_MASK_ADDR1,Region 0 mask address [15:8]."
line.byte 0x3 "REGION0_ADDR,Security Access Mask Address2 for Region 0"
hexmask.byte 0x3 0.--7. 1. "REGION0_MASK_ADDR2,Region 1 mask address [23:16]."
line.byte 0x4 "REGION1_ADDR1,Security Access Address1 for Region 1"
hexmask.byte 0x4 0.--7. 1. "REGION1_ADDR1,Accessible region 1 address [15:8]."
line.byte 0x5 "REGION1_ADDR2,Security Access Address2 for Region 1"
hexmask.byte 0x5 0.--7. 1. "REGION1_ADDR2,Accessible region 1 address [23:16]."
line.byte 0x6 "REGION1_MASK_ADDR1,Security Access Mask Address1 for Region 1"
hexmask.byte 0x6 0.--7. 1. "REGION1_MASK_ADDR1,Region 1 mask address [15:8]."
line.byte 0x7 "REGION1_MASK_ADDR2,Security Access Mask Address2 for Region 1"
hexmask.byte 0x7 0.--7. 1. "REGION1_MASK_ADDR2,Region 1 mask address [23:16]."
line.byte 0x8 "REGION2_ADDR1,Security Access Address1 for Region 2"
hexmask.byte 0x8 0.--7. 1. "REGION2_ADDR1,Accessible region 2 address [15:8]."
line.byte 0x9 "REGION2_ADDR2,Security Access Address2 for Region 2"
hexmask.byte 0x9 0.--7. 1. "REGION2_ADDR2,Accessible region 2 address [23:16]."
line.byte 0xA "REGION2_MASK_ADDR1,Security Access Mask Address1 for Region 2"
hexmask.byte 0xA 0.--7. 1. "REGION2_MASK_ADDR1,Region 2 mask address [15:8]."
line.byte 0xB "REGION2_MASK_ADDR2,Security Access Mask Address2 for Region 2"
hexmask.byte 0xB 0.--7. 1. "REGION2_MASK_ADDR2,Region 2 mask address [23:16]."
line.byte 0xC "REGION3_ADDR1,Security Access Address1 for Region 3"
hexmask.byte 0xC 0.--7. 1. "REGION3_ADDR1,Accessible region 3 address [15:8]."
line.byte 0xD "REGION3_ADDR2,Security Access Address2 for Region 3"
hexmask.byte 0xD 0.--7. 1. "REGION3_ADDR2,Accessible region 3 address [23:16]."
line.byte 0xE "REGION3_MASK_ADDR1,Security Access Mask Address1 for Region 3"
hexmask.byte 0xE 0.--7. 1. "REGION3_MASK_ADDR1,Region 3 mask address [15:8]."
line.byte 0xF "REGION3_MASK_ADDR2,Security Access Mask Address2 for Region 3"
hexmask.byte 0xF 0.--7. 1. "REGION3_MASK_ADDR2,Region 3 mask address [23:16]."
line.byte 0x10 "CMD_PORT_WR_BASE_0,Command Port SQ Write Base Address 0"
hexmask.byte 0x10 0.--7. 1. "CMD_SQ_WRITE_ADDR0,Command Port SQ Write base address bit [7:0]."
line.byte 0x11 "CMD_PORT_WR_BASE_1,Command Port SQ Write Base Address 1"
hexmask.byte 0x11 0.--7. 1. "CMD_SQ_WRITE_ADDR1,Command Port SQ Write base address bit [15:8]."
line.byte 0x12 "CMD_PORT_WR_BASE_2,Command Port SQ Write Base Address 2"
hexmask.byte 0x12 0.--7. 1. "CMD_SQ_WRITE_ADDR2,Command Port SQ Write base address bit [23:16]."
line.byte 0x13 "CMD_PORT_WR_BASE_3,Command Port SQ Write Base Address 3"
hexmask.byte 0x13 0.--7. 1. "CMD_SQ_WRITE_ADDR3,Command Port SQ Write base address bit [31:24]."
line.byte 0x14 "CMD_PORT_RD_BASE_0,Command Port SQ Read Base Address 0"
hexmask.byte 0x14 0.--7. 1. "CMD_SQ_READ_ADDR0,Command Port SQ Read base address bit [7:0]."
line.byte 0x15 "CMD_PORT_RD_BASE_1,Command Port SQ Read Base Address 1"
hexmask.byte 0x15 0.--7. 1. "CMD_SQ_READ_ADDR1,Command Port SQ Read base address bit [15:8]."
line.byte 0x16 "CMD_PORT_RD_BASE_2,Command Port SQ Read Base Address 2"
hexmask.byte 0x16 0.--7. 1. "CMD_SQ_READ_ADDR2,Command Port SQ Read base address bit [23:16]."
line.byte 0x17 "CMD_PORT_RD_BASE_3,Command Port SQ Read Base Address 3"
hexmask.byte 0x17 0.--7. 1. "CMD_SQ_READ_ADDR3,Command Port SQ Read base address bit [31:24]."
line.byte 0x18 "CMD_PORT_RD_LEN_0,Command Port Read Length 0"
hexmask.byte 0x18 0.--7. 1. "CMD_PORT_RD_LEN0,Command Port Read Length [7:0]"
line.byte 0x19 "CMD_PORT_RD_LEN_1,Command Port Read Length 1"
hexmask.byte 0x19 0.--7. 1. "CMD_PORT_RD_LEN1,Command Port Read Length [15:8]"
group.byte 0xC4++0x1
line.byte 0x0 "CMD_PORT_CONFIG_0,Command Port Config 0"
bitfld.byte 0x0 7. "EXPLICIT_CMD_PORT_DNLD_OVER,Explicit Download Over 0 = download over is generated on completion of CMD53 write 1 = download over is generated when host clears download ready interrupt" "0: download over is generated on completion of..,1: download over is generated when host clears.."
newline
bitfld.byte 0x0 6. "EXPLICIT_CMD_PORT_UPLD_OVER,Explicit Upload Update 0 = bitmap update is done on completion of CMD53 read 1 = bitmap update is done when host clears upload" "0: bitmap update is done on completion of CMD53 read,1: bitmap update is done when host clears upload"
newline
bitfld.byte 0x0 5. "CMD_PORT_DNLD_AUTO_RESET,Reset control for cmd_port_dnld_card_rdy event in C2H_INTEVENT 0 = download ready event is reset to 0 after the current cmd53 is completed." "0: download ready event is reset to 0 after the..,?"
newline
bitfld.byte 0x0 4. "CMD_PORT_UPLD_AUTO_RESET,Reset control for cmd_port_upld_card_rdy event in C2H_INTEVENT 0 = upload ready event is reset to 0 after the current cmd53 is completed." "0: upload ready event is reset to 0 after the..,?"
newline
bitfld.byte 0x0 2. "CMD_PORT_RD_LEN_EN,cmd_port_rd_len_en" "0,1"
newline
bitfld.byte 0x0 0.--1. "CMD_PORT_TX_LEN_FORMAT,Define the cmd53 command port tx length (tx_len) header format attached in the beginning of data payload: 0 = no tx_len header info." "0: no tx_len header info,?,?,?"
line.byte 0x1 "CMD_PORT_CONFIG_1,Command Port Config 1"
bitfld.byte 0x1 0. "CMD_PORT_AUTO_ENABLE,If this is enabled download and upload ready host interrupt is automatically cleared and re-enabled after the current cmd53 is completed." "0,1"
rgroup.byte 0xC6++0x2
line.byte 0x0 "CMD_PORT_CONFIG_2,Command Port Config 2"
hexmask.byte 0x0 0.--7. 1. "RSVD,Reserved"
line.byte 0x1 "CMD_PORT_CONFIG_3,Command Port Config 3"
hexmask.byte 0x1 0.--7. 1. "RSVD,Reserved"
line.byte 0x2 "CHIP_REV,Chip Revision"
hexmask.byte 0x2 0.--7. 1. "CHIP_REV,Chip Revision (same as CIU)"
rgroup.byte 0xCA++0x1
line.byte 0x0 "IP_REV0,SDU Minor IP Revision"
hexmask.byte 0x0 0.--7. 1. "SDU_MINOR_IP_REV,SDU minor IP revision"
line.byte 0x1 "IP_REV1,SDU Major IP Revision"
hexmask.byte 0x1 0.--7. 1. "SDU_MAJOR_IP_REV,SDU major IP revision"
group.byte 0xCC++0x7
line.byte 0x0 "PKT_END_RADDR0,PKT_END_RADDR0"
hexmask.byte 0x0 0.--7. 1. "PACKET_END_RADDR0,For function 1 this is used as CMD53 DMA read packet end addr [7:0] For other functions this is a scratch pad register"
line.byte 0x1 "PKT_END_RADDR1,PKT_END_RADDR1"
hexmask.byte 0x1 0.--7. 1. "PACKET_END_RADDR1,For function 1 this is used as CMD53 DMA read packet end addr [15:8] For other functions this is a scratch pad register"
line.byte 0x2 "PKT_END_RADDR2,PKT_END_RADDR2"
hexmask.byte 0x2 0.--7. 1. "PACKET_END_RADDR2,For function 1 this is used as CMD53 DMA read packet end addr [23:16] For other functions this is a scratch pad register"
line.byte 0x3 "PKT_END_RADDR3,PKT_END_RADDR3"
hexmask.byte 0x3 0.--7. 1. "PACKET_END_RADDR3,For function 1 this is used as CMD53 DMA read packet end addr [31:24] For other functions this is a scratch pad register"
line.byte 0x4 "PKT_END_WADDR0,PKT_END_WADDR0"
hexmask.byte 0x4 0.--7. 1. "PACKET_END_WADDR0,For function 1 this is used as CMD53 DMA write packet end addr [7:0] For other functions this is a scratch pad register"
line.byte 0x5 "PKT_END_WADDR1,PKT_END_WADDR1"
hexmask.byte 0x5 0.--7. 1. "PACKET_END_WADDR1,For function 1 this is used as CMD53 DMA write packet end addr [15:8] For other functions this is a scratch pad register"
line.byte 0x6 "PKT_END_WADDR2,PKT_END_WADDR2"
hexmask.byte 0x6 0.--7. 1. "PACKET_END_WADDR2,For function 1 this is used as CMD53 DMA write packet end addr [23:16] For other functions this is a scratch pad register"
line.byte 0x7 "PKT_END_WADDR3,PKT_END_WADDR3"
hexmask.byte 0x7 0.--7. 1. "PACKET_END_WADDR3,For function 1 this is used as CMD53 DMA write packet end addr [31:24] For other functions this is a scratch pad register"
rgroup.byte 0xD4++0x2
line.byte 0x0 "OCR_0,Operation Conditions 0"
hexmask.byte 0x0 0.--7. 1. "OCR0,Operation Conditions 0"
line.byte 0x1 "OCR_1,Operation Conditions 1"
hexmask.byte 0x1 0.--7. 1. "OCR1,Operation Conditions 1"
line.byte 0x2 "OCR_2,Operation Conditions 2"
hexmask.byte 0x2 0.--7. 1. "OCR2,Operation Conditions 2"
group.byte 0xD7++0x4
line.byte 0x0 "CARD_CONFIG_1,Card Config1"
bitfld.byte 0x0 7. "IOE_WAKEUP_EN,If this is enabled the 0-to-1 transition of the IO_ENABLE register bit of each function that is written by host will generate a function-specific wakeup event to the APU." "0,1"
newline
bitfld.byte 0x0 6. "EXPLICIT_UPLD_UPDATE,Explicit Upload Update 0 = bitmap update is done on completion of CMD53 read 1 = bitmap update is done when host clears upload" "0: bitmap update is done on completion of CMD53 read,1: bitmap update is done when host clears upload"
newline
bitfld.byte 0x0 5. "EXPLICIT_DNLD_UPDATE,Explicit Download Update 0 = bitmap update is done on completion of CMD53 write 1 = bitmap update is done when host clears download ready interrupt" "0: bitmap update is done on completion of CMD53 write,1: bitmap update is done when host clears download.."
newline
bitfld.byte 0x0 4. "AGGR_INTR_EN,Aggregation Interrupt Enable 0 = only one download/upload over interrupt per aggregate 1 = generate interrupt for each PDU in aggregate" "0: only one download/upload over interrupt per..,1: generate interrupt for each PDU in aggregate"
newline
bitfld.byte 0x0 3. "EXPLICIT_UPLD_OVER,Explicit Upload Over 0 = upload over is generated on completion of CMD53 read 1 = upload over is generated when host clears upload ready interrupt" "0: upload over is generated on completion of CMD53..,1: upload over is generated when host clears upload.."
newline
bitfld.byte 0x0 2. "EXPLICIT_DNLD_OVER,Explicit Download Over 0 = download over is generated on completion of CMD53 write 1 = download over is generated when host clears download ready interrupt" "0: download over is generated on completion of..,1: download over is generated when host clears.."
newline
bitfld.byte 0x0 1. "CMD53_FINISH_GBUS,Command 53 Finish Ahb Data transfer termination." "0,1"
newline
bitfld.byte 0x0 0. "SD_NEG_EDGE,Sample Data Negative Edge SD interface data sampling edge." "0,1"
line.byte 0x1 "CARD_CONFIG2_0,Card Config2 0"
bitfld.byte 0x1 7. "CMD53_WR_BUSY_WIDTH,cmd53_wr_busy_width" "0,1"
newline
bitfld.byte 0x1 6. "CMD53_WR_BUSY_SIGNAL,Generate cmd53 write busy signal 0 = Write busy signal is not generated on SD_DAT[0] line after each block of cmd53 write." "0: Write busy signal is not generated on SD_DAT[0]..,?"
newline
bitfld.byte 0x1 5. "ONE_BLOCK_XFRD_SLCT,Firmware control to enable packet length issue fix for aggregation mode." "0,1"
newline
bitfld.byte 0x1 4. "HOST_INT_AUTO_ENABLE,If this is enabled download and upload ready host interrupt is automatically cleared and re-enabled after the current cmd53 is completed." "0,1"
newline
bitfld.byte 0x1 3. "FORCE_ASYNC_4BIT_INT_EN,Force asynchronous interrupt in SD 4-bit mode enable." "0,1"
newline
bitfld.byte 0x1 2. "SD_POSEDGE_DRV_FORCE_EN,sd_posedge_drv_force_en" "0,1"
newline
bitfld.byte 0x1 1. "SQ_ADDR_WRAP_EN,If this is enabled the DMA address of the current cmd53 access is wrapped back to its starting address once it reaches the end address." "0,1"
newline
bitfld.byte 0x1 0. "CMD53_WR_BUSY_FORCE_EN,If this is enabled write busy signal can be forced to 1 or 0 (specified by cmd53_wr_busy_force_val) and sent to host during cmd53 write operation." "0,1"
line.byte 0x2 "CARD_CONFIG2_1,Card Config2 1"
bitfld.byte 0x2 6.--7. "CMD53_RD_LEN_FORMAT,cmd53_rd_len_format" "0,1,2,3"
newline
bitfld.byte 0x2 4.--5. "CMD53_TX_LEN_FORMAT,Define the cmd53 transmit/download length (tx_len) header format attached in the beginning of data payload: 0 = no tx_len header info 1= first 2 bytes contain tx_len info 2 = first 3 bytes contain tx_len info This field is applicable.." "0: no tx_len header info,1: first 2 bytes contain tx_len info,2: first 3 bytes contain tx_len info This field is..,?"
newline
bitfld.byte 0x2 3. "UPLD_RDY_AUTO_RESET,Reset control for upld_card_rdy event in C2H_INTEVENT 0 = upload ready event is reset to 0 after the current cmd53 is completed." "0: upload ready event is reset to 0 after the..,?"
newline
bitfld.byte 0x2 2. "DNLD_RDY_AUTO_RESET,Reset control for dnld_card_rdy event in C2H_INTEVENT 0 = download ready event is reset to 0 after the current cmd53 is completed." "0: download ready event is reset to 0 after the..,?"
newline
bitfld.byte 0x2 1. "SD_POSEDGE_DRV_FORCE_VAL,If this is set to 1 SD output is driven at rising edge." "0,1"
newline
bitfld.byte 0x2 0. "CMD53_NEW_MODE,Enable new encoding scheme of the 17b register address field in CMD53." "0,1"
line.byte 0x3 "CARD_CONFIG2_2,Card Config2 2"
bitfld.byte 0x3 7. "CMD53_RD_Q_EN,If this bit is 0 multiple queue feature is disabled for CMD53 read operation." "0,1"
newline
bitfld.byte 0x3 6. "CMD53_WR_Q_EN,If this bit is 0 multiple queue feature is disabled for CMD53 write operation." "0,1"
newline
bitfld.byte 0x3 5. "CMD53_WR_BUSY_FORCE_VAL,If cmd53_wr_busy_force_en is enabled this register bit is used to force write busy signal to host." "0,1"
newline
bitfld.byte 0x3 4. "TEST_CMD_OUT,Test output data for SD_CMD." "0,1"
newline
hexmask.byte 0x3 0.--3. 1. "TEST_DATA_OUT,Test output data for SD_DAT."
line.byte 0x4 "CARD_CONFIG2_3,Card Config2 3"
bitfld.byte 0x4 7. "REGION_ACCESS_EN,Enable region access security feature" "0,1"
newline
bitfld.byte 0x4 6. "CMD53_WR_BUSY_HW_CTRL_EN,Enable cmd53_wr_busy_hw_ctrl feature for each function." "0,1"
newline
bitfld.byte 0x4 5. "PAD_TEST_MODE,Enable test mode to directly drive SD_DAT and SD_CMD with test data specified by test_data_out test_cmd_out test_data_en and test_cmd_en fields." "0,1"
newline
bitfld.byte 0x4 4. "TEST_CMD_EN,Test output enable for SD_CMD." "0,1"
newline
hexmask.byte 0x4 0.--3. 1. "TEST_DATA_EN,Test output enable for SD_DAT."
rgroup.byte 0xDC++0xA
line.byte 0x0 "TESTBUS0,Testbus 0"
hexmask.byte 0x0 0.--7. 1. "TESTBUS0,SDU testbus0"
line.byte 0x1 "TESTBUS1,Testbus 1"
hexmask.byte 0x1 0.--7. 1. "TESTBUS1,SDU testbus1"
line.byte 0x2 "RCA0,RCA 0"
hexmask.byte 0x2 0.--7. 1. "RCA0,RCA[7:0]"
line.byte 0x3 "RCA1,RCA 1"
hexmask.byte 0x3 0.--7. 1. "RCA1,RCA[15:8]"
line.byte 0x4 "DMA_ADDR0,DMA Address 0"
hexmask.byte 0x4 0.--7. 1. "DMA_ADDR0,DMA address [7:0] of last system bus transfer"
line.byte 0x5 "DMA_ADDR1,DMA Address 1"
hexmask.byte 0x5 0.--7. 1. "DMA_ADDR1,DMA address [15:8] of last system bus transfer"
line.byte 0x6 "DMA_ADDR2,DMA Address 2"
hexmask.byte 0x6 0.--7. 1. "DMA_ADDR2,DMA address [23:16] of last system bus transfer"
line.byte 0x7 "DMA_ADDR3,DMA Address 3"
hexmask.byte 0x7 0.--7. 1. "DMA_ADDR3,DMA address [31:24] of last system bus transfer"
line.byte 0x8 "IO_PORT0,I/O Port 0"
hexmask.byte 0x8 0.--7. 1. "IO_ADDR0,I/O port address [7:0]"
line.byte 0x9 "IO_PORT1,I/O Port 1"
hexmask.byte 0x9 0.--7. 1. "IO_ADDR1,I/O port address [15:8]"
line.byte 0xA "IO_PORT2,I/O Port 2"
bitfld.byte 0xA 0. "IO_ADDR2,I/O port address [16]" "0,1"
group.byte 0xE8++0x17
line.byte 0x0 "SCRATCH2_0,Scratch 2 0"
hexmask.byte 0x0 0.--7. 1. "SCRATCH2_0,Scratch register 2 [7:0]"
line.byte 0x1 "SCRATCH2_1,Scratch 2 1"
hexmask.byte 0x1 0.--7. 1. "SCRATCH2_1,Scratch register 2 [15:8]"
line.byte 0x2 "SCRATCH2_2,Scratch 2 2"
hexmask.byte 0x2 0.--7. 1. "SCRATCH2_2,Scratch register 2 [23:16]"
line.byte 0x3 "SCRATCH2_3,Scratch 2 3"
hexmask.byte 0x3 0.--7. 1. "SCRATCH2_3,Scratch register 2 [31:24]"
line.byte 0x4 "SCRATCH3_0,Scratch 3 0"
hexmask.byte 0x4 0.--7. 1. "SCRATCH3_0,Scratch register 3 [7:0]"
line.byte 0x5 "SCRATCH3_1,Scratch 3 1"
hexmask.byte 0x5 0.--7. 1. "SCRATCH3_1,Scratch register 3 [15:8]"
line.byte 0x6 "SCRATCH3_2,Scratch 3 2"
hexmask.byte 0x6 0.--7. 1. "SCRATCH3_2,Scratch register 3 [23:16]"
line.byte 0x7 "SCRATCH3_3,Scratch 3 3"
hexmask.byte 0x7 0.--7. 1. "SCRATCH3_3,Scratch register 3 [31:24]"
line.byte 0x8 "SCRATCH4_0,Scratch 4 0"
hexmask.byte 0x8 0.--7. 1. "SCRATCH4_0,Scratch register 4 [7:0]"
line.byte 0x9 "SCRATCH4_1,Scratch 4 1"
hexmask.byte 0x9 0.--7. 1. "SCRATCH4_1,Scratch register 4 [15:8]"
line.byte 0xA "SCRATCH4_2,Scratch 4 2"
hexmask.byte 0xA 0.--7. 1. "SCRATCH4_2,Scratch register 4 [23:16]"
line.byte 0xB "SCRATCH4_3,Scratch 4 3"
hexmask.byte 0xB 0.--7. 1. "SCRATCH4_3,Scratch register 4 [31:24]"
line.byte 0xC "SCRATCH5_0,Scratch 5 0"
hexmask.byte 0xC 0.--7. 1. "SCRATCH5_0,Scratch register 5 [7:0]"
line.byte 0xD "SCRATCH5_1,Scratch 5 1"
hexmask.byte 0xD 0.--7. 1. "SCRATCH5_1,Scratch register 5 [15:8]"
line.byte 0xE "SCRATCH5_2,Scratch 5 2"
hexmask.byte 0xE 0.--7. 1. "SCRATCH5_2,Scratch register 5 [23:16]"
line.byte 0xF "SCRATCH5_3,Scratch 5 3"
hexmask.byte 0xF 0.--7. 1. "SCRATCH5_3,Scratch register 5 [31:24]"
line.byte 0x10 "SCRATCH6_0,Scratch 6 0"
hexmask.byte 0x10 0.--7. 1. "SCRATCH6_0,Scratch register 6 [7:0]"
line.byte 0x11 "SCRATCH6_1,Scratch 6 1"
hexmask.byte 0x11 0.--7. 1. "SCRATCH6_1,Scratch register 6 [15:8]"
line.byte 0x12 "SCRATCH6_2,Scratch 6 2"
hexmask.byte 0x12 0.--7. 1. "SCRATCH6_2,Scratch register 6 [23:16]"
line.byte 0x13 "SCRATCH6_3,Scratch 6 3"
hexmask.byte 0x13 0.--7. 1. "SCRATCH6_3,Scratch register 6 [31:24]"
line.byte 0x14 "SCRATCH7_0,Scratch 7 0"
hexmask.byte 0x14 0.--7. 1. "SCRATCH7_0,Scratch register 7 [7:0]"
line.byte 0x15 "SCRATCH7_1,Scratch 7 1"
hexmask.byte 0x15 0.--7. 1. "SCRATCH7_1,Scratch register 7 [15:8]"
line.byte 0x16 "SCRATCH7_2,Scratch 7 2"
hexmask.byte 0x16 0.--7. 1. "SCRATCH7_2,Scratch register 7 [23:16]"
line.byte 0x17 "SCRATCH7_3,Scratch 7 3"
hexmask.byte 0x17 0.--7. 1. "SCRATCH7_3,Scratch register 7 [31:24]"
tree.end
tree.end
tree "SENSOR_CTRL"
base ad:0x45004000
group.long 0x0++0x3
line.long 0x0 "ADC_CTRL_REG_1,General configuration of ADCC"
hexmask.long.byte 0x0 7.--10. 1. "ADCC_ERR_GAIN,IT is 4 bIT signed integer value of error gain of SARADC. If adcc_err_gain_bypass is set as 1 then this value is not considered for error gain adjustment of ADCC data output. Example: If value of this field is 4'b1110 then IT is -2 in.."
bitfld.long 0x0 6. "ADCC_ERR_GAIN_BYPASS,Bypass error gain adjustment in ADCC data output" "0,1"
bitfld.long 0x0 4.--5. "ADCC_TB_SEL,It selects one of the testbuses of ADCC." "0,1,2,3"
newline
bitfld.long 0x0 3. "ADCC_TEST_CAL_BYPASS,bypass calibration for ATE or other test" "0,1"
bitfld.long 0x0 2. "ADCC_SW_ENABLE,sw enable from CPU for sensor and controller" "0,1"
bitfld.long 0x0 1. "ADCC_SW_CAL_ENABLE,SW triggered calibration enable." "0,1"
newline
bitfld.long 0x0 0. "ADCC_SW_RESET,sw reset from CPU for sensor and controller" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "ADC_STATUS_REG,status of ADC and ADCC"
bitfld.long 0x0 14. "ADC_OUT_DFF_RSTB,Reset value:" "0,1"
bitfld.long 0x0 13. "PU_ADC_REG,Powerup/ power down value:" "0,1"
bitfld.long 0x0 12. "ADCC_CAL_DONE,Valid value:" "0,1"
newline
hexmask.long.word 0x0 0.--11. 1. "ADCC_OFFSET_CODE,OFFSET of ADC computed after calibration. It is a signed number (2's complement format) with 1 fractional bit. Example If binary value of this field is 1111_1111_0011 then it represents -6.5 in decimal. Note that this field is valid.."
group.long 0x8++0x3
line.long 0x0 "TSEN_CTRL_1_REG_1,TSEN Controller configuration"
hexmask.long.word 0x0 20.--29. 1. "TSEN_MAX_TEMP_THR,SW programmed maximum threshold for sensor. Default is 137C."
hexmask.long.word 0x0 8.--17. 1. "TSEN_MIN_TEMP_THR,SW programmed minimum threshold for sensor. Default is -37C."
bitfld.long 0x0 5. "TSEN_SW_TEMP_READ_EN,SW based temperature reading enable for tsen (corresponding to tsen_trigger_mode = 1)" "0,1"
newline
bitfld.long 0x0 4. "TSEN_TESTMODE,This bit is used to test sensor controller." "0,1"
bitfld.long 0x0 2.--3. "TSEN_TRIGGER_MODE,Trigger mode for sensor => DEFAULT: periodic" "0,1,2,3"
bitfld.long 0x0 1. "TSEN_SW_ENABLE,sw enable from CPU for sensor and controller" "0,1"
newline
bitfld.long 0x0 0. "TSEN_SW_RESET,sw reset from CPU for sensor and controller" "0,1"
rgroup.long 0xC++0x3
line.long 0x0 "TSEN_CTRL_1_REG_2,TSEN Controller Output status register"
hexmask.long.word 0x0 22.--31. 1. "TSENDC_DEBUG,Field description:"
bitfld.long 0x0 21. "SW_ON_DEMAND_TSEN_RD_DONE_STATUS,Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode." "0,1"
bitfld.long 0x0 20. "TSEN_ERROR,Error indication from sensor" "0,1"
newline
hexmask.long.word 0x0 10.--19. 1. "TSEN_TEMP_VALUE,reading from last sensor sampling available for SW to read out"
hexmask.long.word 0x0 0.--9. 1. "TSEN_ERR_TEMP_PVALUE,The sensor reading captured at the time of *sen_error event -> this is for SW"
group.long 0x10++0x3
line.long 0x0 "TSEN_CTRL_2_REG_1,TSEN Controller configuration"
hexmask.long.word 0x0 20.--29. 1. "TSEN_MAX_TEMP_THR,SW programmed maximum threshold for sensor. Default is 137C"
hexmask.long.word 0x0 8.--17. 1. "TSEN_MIN_TEMP_THR,SW programmed minimum threshold for sensor. Default is -37C."
bitfld.long 0x0 5. "TSEN_SW_TEMP_READ_EN,SW based temperature reading enable for tsen (corresponding to tsen_trigger_mode = 1)" "0,1"
newline
bitfld.long 0x0 4. "TSEN_TESTMODE,This bit is used to test sensor controller." "0,1"
bitfld.long 0x0 2.--3. "TSEN_TRIGGER_MODE,Trigger mode for sensor => DEFAULT: periodic" "0,1,2,3"
bitfld.long 0x0 1. "TSEN_SW_ENABLE,sw enable from CPU for sensor and controller(TSEN_PMIP is disabled by default)" "0,1"
newline
bitfld.long 0x0 0. "TSEN_SW_RESET,sw reset from CPU for sensor and controller" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "TSEN_CTRL_2_REG_2,TSEN Controller Output status register"
hexmask.long.word 0x0 22.--31. 1. "TSENDC_DEBUG,Field description:"
bitfld.long 0x0 21. "SW_ON_DEMAND_TSEN_RD_DONE_STATUS,Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode." "0,1"
bitfld.long 0x0 20. "TSEN_ERROR,Error indication from sensor" "0,1"
newline
hexmask.long.word 0x0 10.--19. 1. "TSEN_TEMP_VALUE,reading from last sensor sampling available for SW to read out"
hexmask.long.word 0x0 0.--9. 1. "TSEN_ERR_TEMP_PVALUE,The sensor reading captured at the time of *sen_error event -> this is for SW"
group.long 0x18++0x3
line.long 0x0 "VSEN_CTRL_1_REG_1,VSEN Controller configuration"
hexmask.long.word 0x0 20.--29. 1. "VSEN_MAX_VOLTAGE_THR,SW programmed maximum threshold for sensor. Default"
hexmask.long.word 0x0 8.--17. 1. "VSEN_MIN_VOLTAGE_THR,SW programmed minimum threshold for sensor. Default value is 0.925v."
bitfld.long 0x0 5. "VSEN_SW_VOLTAGE_READ_EN,SW based reading enable for sensor (corresponding to *sen_trigger_mode = 1)" "0,1"
newline
bitfld.long 0x0 4. "VSEN_TESTMODE,This bit is used to test sensor controller." "0,1"
bitfld.long 0x0 2.--3. "VSEN_TRIGGER_MODE,Trigger mode for sensor => DEFAULT: periodic" "0,1,2,3"
bitfld.long 0x0 1. "VSEN_SW_ENABLE,sw enable from CPU for sensor and controller" "0,1"
newline
bitfld.long 0x0 0. "VSEN_SW_RESET,sw reset from CPU for sensor and controller" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "VSEN_CTRL_1_REG_2,VSEN Controller Output status register"
hexmask.long.word 0x0 22.--31. 1. "VSENDC_DEBUG,Field description:"
bitfld.long 0x0 21. "SW_ON_DEMAND_VSEN_RD_DONE_STATUS,Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode." "0,1"
bitfld.long 0x0 20. "VSEN_ERROR,Error indication from sensor" "0,1"
newline
hexmask.long.word 0x0 10.--19. 1. "VSEN_VOLTAGE_VALUE,reading from last sensor sampling available for SW to read out"
hexmask.long.word 0x0 0.--9. 1. "VSEN_ERR_VOLTAGE_PVALUE,The sensor reading captured at the time of *sen_error event -> this is for SW"
group.long 0x20++0x3
line.long 0x0 "VSEN_CTRL_2_REG_1,VSEN2 Controller configuration"
hexmask.long.word 0x0 20.--29. 1. "VSEN_MAX_VOLTAGE_THR,SW programmed maximum threshold for sensor. Default"
hexmask.long.word 0x0 8.--17. 1. "VSEN_MIN_VOLTAGE_THR,SW programmed minimum threshold for sensor. Default"
bitfld.long 0x0 5. "VSEN_SW_VOLTAGE_READ_EN,SW based reading enable for sensor (corresponding to *sen_trigger_mode = 1)" "0,1"
newline
bitfld.long 0x0 4. "VSEN_TESTMODE,This bit is used to test sensor controller." "0,1"
bitfld.long 0x0 2.--3. "VSEN_TRIGGER_MODE,Trigger mode for sensor => DEFAULT: periodic" "0,1,2,3"
bitfld.long 0x0 1. "VSEN_SW_ENABLE,sw enable from CPU for sensor and controller" "0,1"
newline
bitfld.long 0x0 0. "VSEN_SW_RESET,sw reset from CPU for sensor and controller" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "VSEN_CTRL_2_REG_2,VSEN2 Controller Output status register"
hexmask.long.word 0x0 22.--31. 1. "VSENDC_DEBUG,Field description:"
bitfld.long 0x0 21. "SW_ON_DEMAND_VSEN_RD_DONE_STATUS,Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode." "0,1"
bitfld.long 0x0 20. "VSEN_ERROR,Error indication from sensor" "0,1"
newline
hexmask.long.word 0x0 10.--19. 1. "VSEN_VOLTAGE_VALUE,reading from last sensor sampling available for SW to read out"
hexmask.long.word 0x0 0.--9. 1. "VSEN_ERR_VOLTAGE_PVALUE,The sensor reading captured at the time of *sen_error event -> this is for SW"
group.long 0x28++0x3
line.long 0x0 "VSEN_CTRL_3_REG_1,VSEN3 Controller configuration"
hexmask.long.word 0x0 20.--29. 1. "VSEN_MAX_VOLTAGE_THR,SW programmed maximum threshold for sensor. Default"
hexmask.long.word 0x0 8.--17. 1. "VSEN_MIN_VOLTAGE_THR,SW programmed minimum threshold for sensor. Default"
bitfld.long 0x0 5. "VSEN_SW_VOLTAGE_READ_EN,SW based reading enable for sensor (corresponding to *sen_trigger_mode = 1)" "0,1"
newline
bitfld.long 0x0 4. "VSEN_TESTMODE,This bit is used to test sensor controller." "0,1"
bitfld.long 0x0 2.--3. "VSEN_TRIGGER_MODE,Trigger mode for sensor => DEFAULT: periodic" "0,1,2,3"
bitfld.long 0x0 1. "VSEN_SW_ENABLE,sw enable from CPU for sensor and controller" "0,1"
newline
bitfld.long 0x0 0. "VSEN_SW_RESET,sw reset from CPU for sensor and controller" "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "VSEN_CTRL_3_REG_2,VSEN3 Controller Output status register"
hexmask.long.word 0x0 22.--31. 1. "VSENDC_DEBUG,Field description:"
bitfld.long 0x0 21. "SW_ON_DEMAND_VSEN_RD_DONE_STATUS,Indicates sensor value[19:10] is valid for case of sw_on_demand trigger mode." "0,1"
bitfld.long 0x0 20. "VSEN_ERROR,Error indication from sensor" "0,1"
newline
hexmask.long.word 0x0 10.--19. 1. "VSEN_VOLTAGE_VALUE,reading from last sensor sampling available for SW to read out"
hexmask.long.word 0x0 0.--9. 1. "VSEN_ERR_VOLTAGE_PVALUE,The sensor reading captured at the time of *sen_error event -> this is for SW"
group.long 0x30++0x13
line.long 0x0 "VGLITCH_CTRL_REG_1,Voltage Glitch sensor controller configuration"
rbitfld.long 0x0 4. "VGLITCH_ERROR,Error indication from Voltage glitch sensor" "0,1"
bitfld.long 0x0 2. "VGLITCH_TESMODE,Testmode enable from CPU for Glitch Sensor" "0,1"
bitfld.long 0x0 1. "VGLITCH_SW_ENABLE,sw enable from CPU for Glitch Sensor" "0,1"
line.long 0x4 "MISC_CTRL_REG,Miscellaneous controls"
bitfld.long 0x4 17.--19. "TIMER_5_PERIOD,Pre defined sampling periods for this sensor" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16. "TIMER_5_ENABLE,enables the timer for sensor to start counting" "0,1"
bitfld.long 0x4 13.--15. "TIMER_4_PERIOD,Pre defined sampling periods for this sensor" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "TIMER_4_ENABLE,enables the timer for sensor to start counting" "0,1"
bitfld.long 0x4 9.--11. "TIMER_3_PERIOD,Pre defined sampling periods for this sensor" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8. "TIMER_3_ENABLE,enables the timer for sensor to start counting" "0,1"
newline
bitfld.long 0x4 5.--7. "TIMER_2_PERIOD,Pre defined sampling periods for this sensor" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4. "TIMER_2_ENABLE,enables the timer for sensor to start counting" "0,1"
bitfld.long 0x4 1.--3. "TIMER_1_PERIOD,Pre defined sampling periods for this sensor" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "TIMER_1_ENABLE,enables the timer for sensor to start counting" "0,1"
line.long 0x8 "CFG_ERR_STATUS_REG,CFG ERROR Control"
hexmask.long.byte 0x8 16.--22. 1. "SEC_SEN_ERR_MASK,SW Mask control bit for sensor Error."
rbitfld.long 0x8 8. "SEC_CFG_ERR,Indication to SW that Sensor config Registers are has Errors. Original and shadow registers are not same" "0,1"
bitfld.long 0x8 0.--2. "TB_SEL,Select Testbus that can go to GPIO" "0,1,2,3,4,5,6,7"
line.long 0xC "SEN_CLR_REG,CFG ERROR Control"
hexmask.long.byte 0xC 8.--12. 1. "SEN_RD_DONE_CLR,SW control to clear read done status bit of Sensor in case of trigger mode set to on demand."
hexmask.long.byte 0xC 0.--6. 1. "SEN_ERR_CLR,SW control to clear error status of Sensor."
line.long 0x10 "SEC_ECO_REG,ECO Bits"
hexmask.long 0x10 0.--31. 1. "ECO_BITS,Reserved for ECOs"
tree.end
tree "SOC_GPIO"
base ad:0x45003200
group.word 0x0++0x1
line.word 0x0 "GPIO_SELECT0,'"
bitfld.word 0x0 14.--15. "GPIO_SELECT_7,GPIO Output Source for Pin GPIO[7]" "0,1,2,3"
bitfld.word 0x0 12.--13. "GPIO_SELECT_6,GPIO Output Source for Pin GPIO[6]" "0,1,2,3"
bitfld.word 0x0 10.--11. "GPIO_SELECT_5,GPIO Output Source for Pin GPIO[5]" "0,1,2,3"
bitfld.word 0x0 8.--9. "GPIO_SELECT_4,GPIO Output Source for Pin GPIO[4]" "0,1,2,3"
bitfld.word 0x0 6.--7. "GPIO_SELECT_3,GPIO Output Source for Pin GPIO[3]" "0,1,2,3"
bitfld.word 0x0 4.--5. "GPIO_SELECT_2,GPIO Output Source for Pin GPIO[2]" "0,1,2,3"
newline
bitfld.word 0x0 2.--3. "GPIO_SELECT_1,GPIO Output Source for Pin GPIO[1]" "0,1,2,3"
bitfld.word 0x0 0.--1. "GPIO_SELECT_0,GPIO Output Source for Pin GPIO[0]" "0,1,2,3"
group.word 0x4++0x1
line.word 0x0 "GPIO_SELECT1,'"
bitfld.word 0x0 14.--15. "GPIO_SELECT_15,GPIO Output Source for Pin GPIO[15]" "0,1,2,3"
bitfld.word 0x0 12.--13. "GPIO_SELECT_14,GPIO Output Source for Pin GPIO[14]" "0,1,2,3"
bitfld.word 0x0 10.--11. "GPIO_SELECT_13,GPIO Output Source for Pin GPIO[13]" "0,1,2,3"
bitfld.word 0x0 8.--9. "GPIO_SELECT_12,GPIO Output Source for Pin GPIO[12]" "0,1,2,3"
bitfld.word 0x0 6.--7. "GPIO_SELECT_11,GPIO Output Source for Pin GPIO[11]" "0,1,2,3"
bitfld.word 0x0 4.--5. "GPIO_SELECT_10,GPIO Output Source for Pin GPIO[10]" "0,1,2,3"
newline
bitfld.word 0x0 2.--3. "GPIO_SELECT_9,GPIO Output Source for Pin GPIO[9]" "0,1,2,3"
bitfld.word 0x0 0.--1. "GPIO_SELECT_8,GPIO Output Source for Pin GPIO[8]" "0,1,2,3"
group.word 0x8++0x1
line.word 0x0 "GPIO_OUTPUT_ENABLE0,'"
hexmask.word 0x0 0.--15. 1. "GPIO_OUTPUT_EN,GPIO Output Enable"
group.word 0xC++0x1
line.word 0x0 "GPIO_OUTPUT0,'"
hexmask.word 0x0 0.--15. 1. "GPIO_OUT,GPIO Output"
rgroup.word 0x10++0x1
line.word 0x0 "GPIO_INPUT0,'"
hexmask.word 0x0 0.--15. 1. "GPIO_IN,GPIO Input"
group.word 0x14++0x1
line.word 0x0 "GPIO_IER0,GPIO Interrupt Edge Trigger Select (IER) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_IER,GPIO Interrupt Edge Trigger Select"
group.word 0x18++0x1
line.word 0x0 "GPIO_IMR0,GPIO Input Interrupt Mask (IMR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_IMR,GPIO Interrupt Mask Control"
group.word 0x1C++0x1
line.word 0x0 "GPIO_RSR0,GPIO Reset Select (RSR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_RSR,GPIO Interrupt Reset Select"
group.word 0x20++0x1
line.word 0x0 "GPIO_ISR0,GPIO Interrupt Status (ISR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_ISR,GPIO Interrupt Status Indicator"
group.word 0x24++0x1
line.word 0x0 "SOFTWARE_LED_OUTPUT_ENABLE,'"
bitfld.word 0x0 0.--1. "GPIO_LED_EN,GPIO LED Enable" "0,1,2,3"
group.word 0x28++0x1
line.word 0x0 "SOFTWARE_LED_CYCLE_0,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_CYCLE_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_CYCLE_0,Blink Rate control for LED[0]"
group.word 0x2C++0x1
line.word 0x0 "SOFTWARE_LED_CYCLE_1,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_CYCLE_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_CYCLE_0,Blink Rate control for LED[0]"
group.word 0x30++0x1
line.word 0x0 "SOFTWARE_LED_CYCLE_2,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_CYCLE_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_CYCLE_0,Blink Rate control for LED[0]"
group.word 0x34++0x1
line.word 0x0 "SOFTWARE_LED_CYCLE_3,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_CYCLE_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_CYCLE_0,Blink Rate control for LED[0]"
group.word 0x38++0x1
line.word 0x0 "SOFTWARE_LED_DUTY_CYCLE_0,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_DUTY_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_DUTY_0,Blink Rate control for LED[0]"
group.word 0x3C++0x1
line.word 0x0 "SOFTWARE_LED_DUTY_CYCLE_1,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_DUTY_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_DUTY_0,Blink Rate control for LED[0]"
group.word 0x40++0x1
line.word 0x0 "SOFTWARE_LED_DUTY_CYCLE_2,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_DUTY_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_DUTY_0,Blink Rate control for LED[0]"
group.word 0x44++0x1
line.word 0x0 "SOFTWARE_LED_DUTY_CYCLE_3,'"
hexmask.word.byte 0x0 4.--7. 1. "SW_LED_DUTY_1,Blink Rate control for LED[1]"
hexmask.word.byte 0x0 0.--3. 1. "SW_LED_DUTY_0,Blink Rate control for LED[0]"
group.word 0x48++0x1
line.word 0x0 "LED_OUTPUT_ENABLE,LED Output Enable for Status Signals"
bitfld.word 0x0 7. "SIU_RI_I_EN,GPIO Ring Indicator Enable" "0,1"
bitfld.word 0x0 6. "AU_CLK_EN,Audio Clock Enable" "0,1"
bitfld.word 0x0 5. "AU_SYNC_EN,Audio Sync Enable" "0,1"
bitfld.word 0x0 4. "AU_DIN_EN,Audio DIN Enable" "0,1"
bitfld.word 0x0 0.--1. "START_LED_EN,LED enable for Status Signals [1:0]" "0,1,2,3"
group.word 0x4C++0x1
line.word 0x0 "LED_STRETCH,'"
hexmask.word.byte 0x0 4.--7. 1. "LED_STRETCH_1,Pulse Stretch Duration for Status of WLAN Activity to Drive LED"
hexmask.word.byte 0x0 0.--3. 1. "LED_STRETCH_0,Pulse Stretch Duration for Status of WLAN Activity to Drive LED"
group.word 0x50++0x1
line.word 0x0 "LED_CLK_DIV,'"
hexmask.word.byte 0x0 0.--3. 1. "LED_CLK_DIV,LED Clock Divide"
group.word 0x54++0x1
line.word 0x0 "LEVEL_DETECT,'"
hexmask.word 0x0 0.--15. 1. "LEVEL_DET,Level Detect"
rgroup.word 0x58++0x1
line.word 0x0 "GPU_IP_REVISION,'"
hexmask.word 0x0 0.--15. 1. "GPIO_IP_VERSION,GPIO Unit (GPU) IP Version"
group.word 0x5C++0x1
line.word 0x0 "GPIO_SELECT2,'"
bitfld.word 0x0 14.--15. "GPIO_SELECT_23,GPIO Output Source for Pin GPIO[23]" "0,1,2,3"
bitfld.word 0x0 12.--13. "GPIO_SELECT_22,GPIO Output Source for Pin GPIO[22]" "0,1,2,3"
bitfld.word 0x0 10.--11. "GPIO_SELECT_21,GPIO Output Source for Pin GPIO[21]" "0,1,2,3"
bitfld.word 0x0 8.--9. "GPIO_SELECT_20,GPIO Output Source for Pin GPIO[20]" "0,1,2,3"
bitfld.word 0x0 6.--7. "GPIO_SELECT_19,GPIO Output Source for Pin GPIO[19]" "0,1,2,3"
bitfld.word 0x0 4.--5. "GPIO_SELECT_18,GPIO Output Source for Pin GPIO[18]" "0,1,2,3"
newline
bitfld.word 0x0 2.--3. "GPIO_SELECT_17,GPIO Output Source for Pin GPIO[17]" "0,1,2,3"
bitfld.word 0x0 0.--1. "GPIO_SELECT_16,GPIO Output Source for Pin GPIO[16]" "0,1,2,3"
group.word 0x60++0x1
line.word 0x0 "GPIO_SELECT3,'"
bitfld.word 0x0 14.--15. "GPIO_SELECT_31,GPIO Output Source for Pin GPIO[31]" "0,1,2,3"
bitfld.word 0x0 12.--13. "GPIO_SELECT_30,GPIO Output Source for Pin GPIO[30]" "0,1,2,3"
bitfld.word 0x0 10.--11. "GPIO_SELECT_29,GPIO Output Source for Pin GPIO[29]" "0,1,2,3"
bitfld.word 0x0 8.--9. "GPIO_SELECT_28,GPIO Output Source for Pin GPIO[28]" "0,1,2,3"
bitfld.word 0x0 6.--7. "GPIO_SELECT_27,GPIO Output Source for Pin GPIO[27]" "0,1,2,3"
bitfld.word 0x0 4.--5. "GPIO_SELECT_26,GPIO Output Source for Pin GPIO[26]" "0,1,2,3"
newline
bitfld.word 0x0 2.--3. "GPIO_SELECT_25,GPIO Output Source for Pin GPIO[25]" "0,1,2,3"
bitfld.word 0x0 0.--1. "GPIO_SELECT_24,GPIO Output Source for Pin GPIO[24]" "0,1,2,3"
group.word 0x64++0x1
line.word 0x0 "GPIO_OUTPUT_ENABLE1,'"
hexmask.word 0x0 0.--15. 1. "GPIO_OUTPUT_EN,GPIO Output Enable for GPIO[31:16]"
group.word 0x68++0x1
line.word 0x0 "GPIO_OUTPUT1,'"
hexmask.word 0x0 0.--15. 1. "GPIO_OUT,GPIO Output[31:16]"
group.word 0x6C++0x1
line.word 0x0 "GPIO_INPUT1,'"
hexmask.word 0x0 0.--15. 1. "GPIO_IN,GPIO Input[31:16]"
group.word 0x70++0x1
line.word 0x0 "GPIO_IER1,GPIO Interrupt Edge Trigger Select (IER) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_IER,GPIO Interrupt Edge Trigger Select[31:16]"
group.word 0x74++0x1
line.word 0x0 "GPIO_IMR1,GPIO Input Interrupt Mask (IMR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_IMR,GPIO Interrupt Mask Control[31:16]"
group.word 0x78++0x1
line.word 0x0 "GPIO_RSR1,GPIO Reset Select (RSR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_RSR,GPIO Interrupt Reset Select[31:16]"
group.word 0x7C++0x1
line.word 0x0 "GPIO_ISR1,GPIO Interrupt Status (ISR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_ISR,GPIO Interrupt Status Indicator[31:16]"
group.word 0x80++0x1
line.word 0x0 "LEVEL_DETECT_2,'"
hexmask.word 0x0 0.--15. 1. "LEVEL_DET,Level Detect"
group.word 0x84++0x1
line.word 0x0 "LED_INVERT,'"
bitfld.word 0x0 0.--1. "LED_INV,LED Invert" "0,1,2,3"
group.word 0x88++0x1
line.word 0x0 "LED_PAD_ENABLE,'"
hexmask.word 0x0 0.--15. 1. "LED_PAD_ENABLE,'"
group.word 0x8C++0x1
line.word 0x0 "LED_SELECT,'"
hexmask.word 0x0 0.--15. 1. "LED_SELECT,'"
rgroup.word 0x94++0x1
line.word 0x0 "LED_CONFIG_STATUS,LED Config status"
hexmask.word.byte 0x0 8.--15. 1. "NUMBER_OF_GPIO,'"
hexmask.word.byte 0x0 4.--7. 1. "NUMBER_OF_SW_LED,NUMBER_of_SW_LED"
hexmask.word.byte 0x0 0.--3. 1. "NUMBER_OF_HW_LED,NUMBER_of_HW_LED"
group.word 0x98++0x1
line.word 0x0 "CPU2_GPIO_IER0,CPU2 GPIO Interrupt Edge Trigger Select (IER) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_IER,GPIO Interrupt Edge Trigger Select"
group.word 0x9C++0x1
line.word 0x0 "CPU2_GPIO_IMR0,CPU2 GPIO Input Interrupt Mask (IMR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_IMR,GPIO Interrupt Mask Control"
group.word 0xA0++0x1
line.word 0x0 "CPU2_GPIO_RSR0,CPU2 GPIO Reset Select (RSR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_RSR,GPIO Interrupt Reset Select"
group.word 0xA4++0x1
line.word 0x0 "CPU2_GPIO_ISR0,CPU2 GPIO Interrupt Status (ISR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_ISR,GPIO Interrupt Status Indicator"
group.word 0xA8++0x1
line.word 0x0 "CPU2_LEVEL_DETECT,CPU2 Level Detect"
hexmask.word 0x0 0.--15. 1. "LEVEL_DET,Level Detect"
group.word 0xAC++0x1
line.word 0x0 "CPU2_GPIO_IER1,CPU2 GPIO Interrupt Edge Trigger Select (IER) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_IER,GPIO Interrupt Edge Trigger Select[31:16]"
group.word 0xB0++0x1
line.word 0x0 "CPU2_GPIO_IMR1,CPU2 GPIO Input Interrupt Mask (IMR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_IMR,GPIO Interrupt Mask Control[31:16]"
group.word 0xB4++0x1
line.word 0x0 "CPU2_GPIO_RSR1,CPU2 GPIO Reset Select (RSR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_RSR,GPIO Interrupt Reset Select[31:16]"
group.word 0xB8++0x1
line.word 0x0 "CPU2_GPIO_ISR1,CPU2 GPIO Interrupt Status (ISR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_ISR,GPIO Interrupt Status Indicator[31:16]"
group.word 0xBC++0x1
line.word 0x0 "CPU2_LEVEL_DETECT_2,CPU2 Level Detect 2"
hexmask.word 0x0 0.--15. 1. "LEVEL_DET,Level Detect"
group.word 0xC0++0x1
line.word 0x0 "CPU3_GPIO_IER0,CPU3 GPIO Interrupt Edge Trigger Select (IER) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_IER,GPIO Interrupt Edge Trigger Select"
group.word 0xC4++0x1
line.word 0x0 "CPU3_GPIO_IMR0,CPU3 GPIO Input Interrupt Mask (IMR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_IMR,GPIO Interrupt Mask Control"
group.word 0xC8++0x1
line.word 0x0 "CPU3_GPIO_RSR0,CPU3 GPIO Reset Select (RSR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_RSR,GPIO Interrupt Reset Select"
group.word 0xCC++0x1
line.word 0x0 "CPU3_GPIO_ISR0,CPU3 GPIO Interrupt Status (ISR) -- GPIO[15:0]"
hexmask.word 0x0 0.--15. 1. "GPIO_ISR,GPIO Interrupt Status Indicator"
group.word 0xD0++0x1
line.word 0x0 "CPU3_LEVEL_DETECT,CPU3 Level Detect"
hexmask.word 0x0 0.--15. 1. "LEVEL_DET,Level Detect"
group.word 0xD4++0x1
line.word 0x0 "CPU3_GPIO_IER1,CPU3 GPIO Interrupt Edge Trigger Select (IER) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_IER,GPIO Interrupt Edge Trigger Select[31:16]"
group.word 0xD8++0x1
line.word 0x0 "CPU3_GPIO_IMR1,CPU3 GPIO Input Interrupt Mask (IMR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_IMR,GPIO Interrupt Mask Control[31:16]"
group.word 0xDC++0x1
line.word 0x0 "CPU3_GPIO_RSR1,CPU3 GPIO Reset Select (RSR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_RSR,GPIO Interrupt Reset Select[31:16]"
group.word 0xE0++0x1
line.word 0x0 "CPU3_GPIO_ISR1,CPU3 GPIO Interrupt Status (ISR) -- GPIO[31:16]"
hexmask.word 0x0 0.--15. 1. "GPIO_ISR,GPIO Interrupt Status Indicator[31:16]"
group.word 0xE4++0x1
line.word 0x0 "CPU3_LEVEL_DETECT_2,CPU3 Level Detect 2"
hexmask.word 0x0 0.--15. 1. "LEVEL_DET,Level Detect"
tree.end
tree "SOC_HARDENING_MUX"
base ad:0x45005000
group.long 0x0++0x3
line.long 0x0 "MAGIC_WORD_0,magic word for cpu1 DBGEN"
hexmask.long.byte 0x0 0.--5. 1. "MAGIC_WORD,magic word"
rgroup.long 0x4++0x3
line.long 0x0 "FSM_STATE_0,FSM state status of cpu1 DBGEN"
hexmask.long.byte 0x0 0.--5. 1. "FSM_STATE,status of FSM state:"
group.long 0x8++0x3
line.long 0x0 "MAGIC_WORD_1,magic word for cpu1 NIDEN"
hexmask.long.byte 0x0 0.--5. 1. "MAGIC_WORD,magic word"
rgroup.long 0xC++0x3
line.long 0x0 "FSM_STATE_1,FSM state status of cpu1 NIDEN"
hexmask.long.byte 0x0 0.--5. 1. "FSM_STATE,status of FSM state:"
group.long 0x10++0x3
line.long 0x0 "MAGIC_WORD_2,magic word for cpu2 DBGEN"
hexmask.long.byte 0x0 0.--5. 1. "MAGIC_WORD,magic word"
rgroup.long 0x14++0x3
line.long 0x0 "FSM_STATE_2,FSM state status of cpu2 DBGEN"
hexmask.long.byte 0x0 0.--5. 1. "FSM_STATE,status of FSM state:"
group.long 0x18++0x3
line.long 0x0 "MAGIC_WORD_3,magic word for cpu2 NIDEN"
hexmask.long.byte 0x0 0.--5. 1. "MAGIC_WORD,magic word"
rgroup.long 0x1C++0x3
line.long 0x0 "FSM_STATE_3,FSM state status of cpu2 NIDEN"
hexmask.long.byte 0x0 0.--5. 1. "FSM_STATE,status of FSM state:"
group.long 0x20++0x3
line.long 0x0 "MAGIC_WORD_4,magic word for DFT"
hexmask.long.byte 0x0 0.--5. 1. "MAGIC_WORD,magic word"
rgroup.long 0x24++0x3
line.long 0x0 "FSM_STATE_4,FSM state status of DFT"
hexmask.long.byte 0x0 0.--5. 1. "FSM_STATE,status of FSM state:"
group.long 0x28++0x3
line.long 0x0 "MAGIC_WORD_5,magic word for dis tb bit0. This bit disables mci aon tb. cau standalone mode. sec sens tb"
hexmask.long.byte 0x0 0.--5. 1. "MAGIC_WORD,magic word"
rgroup.long 0x2C++0x3
line.long 0x0 "FSM_STATE_5,FSM state status of dis tb bit0"
hexmask.long.byte 0x0 0.--5. 1. "FSM_STATE,status of FSM state:"
group.long 0x38++0x7
line.long 0x0 "AHB_ACC_CTRL,AHB ACCESS Control for CPU1 and CPU2"
hexmask.long.byte 0x0 0.--4. 1. "AHB2SIF,Writing 1 will Block Register Access of CPU1(WLAN)/CPU2(BLE) to"
line.long 0x4 "DBG_ECO_REG,ECO Bits"
hexmask.long.byte 0x4 0.--5. 1. "ECO_BITS,Reserved for ECOs"
tree.end
tree "SOC_OTP_CTRL"
base ad:0x45003400
group.word 0x200++0x1
line.word 0x0 "OTP_SPARE0,OTP_SPARE0_REG"
hexmask.word 0x0 0.--15. 1. "OTP_SPARE0,SPARE register for future ECO's h/w default is 0x0000"
group.word 0x204++0x1
line.word 0x0 "OTP_SPARE1,OTP_SPARE1_REG"
hexmask.word 0x0 0.--15. 1. "OTP_SPARE1,SPARE register for future ECO's h/w default is 0xFFFF"
wgroup.word 0x208++0x1
line.word 0x0 "OTP_WDATA0,OTP_WDATA0_REG"
hexmask.word 0x0 0.--15. 1. "OTP_WDATA0,Data[15:0]"
group.word 0x20C++0x1
line.word 0x0 "OTP_WDATA1,OTP_WDATA1_REG"
hexmask.word 0x0 0.--15. 1. "OTP_WDATA1,Data[31:16]"
group.word 0x210++0x1
line.word 0x0 "OTP_WDATA2,OTP_WDATA2_REG"
hexmask.word 0x0 0.--15. 1. "OTP_WDATA2,Data[47:32]"
group.word 0x214++0x1
line.word 0x0 "OTP_WDATA3,OTP_WDATA3_REG"
hexmask.word 0x0 0.--15. 1. "OTP_WDATA3,Data[63:48]"
rgroup.word 0x218++0x1
line.word 0x0 "OTP_WDATA4,OTP_WDATA4_REG"
bitfld.word 0x0 3. "OTP_ALL_BITS_EQ_ZERO,All bits equal to zero (READ ONLY)" "0,1"
bitfld.word 0x0 2. "SECURITY_BIT,Security Fuse bit (READ ONLY)" "0,1"
bitfld.word 0x0 1. "DATA_LINE_VALID_BIT,Data line valid bit (READ ONLY)" "0,1"
bitfld.word 0x0 0. "ATE_TEST_BIT,ATE test bit (READ ONLY)" "0,1"
group.word 0x21C++0x1
line.word 0x0 "OTP_ADDR,OTP_ADDR_REG"
hexmask.word 0x0 0.--9. 1. "OTP_ADDR,The otp_addr is composed of Bank select[16:13] and row address[12:7] the address will select a row or a data line of a bank that contains 64 bits of s/w usable data plus the ATE test bit and data line valid bit and the security bit."
group.word 0x220++0x1
line.word 0x0 "OTP_CTRL0,OTP_CTRL0_REG"
rbitfld.word 0x0 15. "CTRL_CMD_DONE,otp access command done." "0,1"
bitfld.word 0x0 14. "REG_CSTATE_RESET,Reset OTP ctrl sm (for debugging purpose)." "0,1"
hexmask.word.byte 0x0 8.--11. 1. "MACRO_TEST,S/W control bits to 'TEST[3:0]' inputs."
rbitfld.word 0x0 7. "MACRO_RD_DONE,RD_DONE is from the OTP bank (selected by otp_addr_reg[9:6])." "0,1"
newline
bitfld.word 0x0 5. "REGULATOR_EN,Stepdown regulator output enable only valid if regulator_EN_bypass==1." "0,1"
bitfld.word 0x0 4. "REG_SETULATOR_EN_BYPASS,Enable/ disable value:" "0,1"
bitfld.word 0x0 2.--3. "REGULATOR_SV,Stepdown regulator Rate Control default = 2'b10 (2'b10==2.6V for 40nm)" "?,?,2: =2,?"
bitfld.word 0x0 1. "REGULATOR_EN25_33B,Stepdown regulator input voltage select" "0,1"
group.word 0x224++0x1
line.word 0x0 "OTP_CTRL1,OTP_CTRL1_REG"
hexmask.word.byte 0x0 8.--15. 1. "MACRO_MATCH,0: match code does not match."
rbitfld.word 0x0 7. "STEPDOWN_MATCH,Match value:" "0,1"
bitfld.word 0x0 6. "OTP_FORCE_STEPDOWN_PROG,For OTP memory programming: This bit need to be set before the match code programming and clear this bit after the otp memory contents programming is done." "0,1"
bitfld.word 0x0 5. "OTP_FORCE_SCLK_MEM_PROG,Only used for OTP memory programming: Set this bit to allow the match code programming clear this bit after the match code programming before start otp memory programming." "0,1"
newline
bitfld.word 0x0 4. "OTP_PROG_SEQ_CODE_MUX_SEL,SELECT OTP register for the match Code programming." "0,1"
bitfld.word 0x0 3. "OTP_PROG_SEQ_CODE_VTR,Data input used to program the match code into all the VTR (Step Down regulator)" "0,1"
bitfld.word 0x0 2. "OTP_PROG_SEQ_CODE_CLK_VTR,Clock input used to program the match code into all the VTR (Step Down regulator)" "0,1"
bitfld.word 0x0 1. "OTP_PROG_SEQ_CODE_OTPMEM,Data input used to program the match code into all the OTP memories." "0,1"
newline
bitfld.word 0x0 0. "OTP_PROG_SEQ_CODE_CLK_OTPMEM,Clock input used to program the match code into all the OTP memories" "0,1"
group.word 0x228++0x1
line.word 0x0 "OTP_CMD_START,OTP_CMD_START_REG"
hexmask.word.byte 0x0 4.--7. 1. "OTP_CMD,OTP access commands (the command execution finishes when the 'ctrl_cmd_done' bit is set):"
bitfld.word 0x0 0. "OTP_CMD_START,Write '1' to start otp access command execution and it clears the 'ctrl_cmd_done' bit." "0,1"
group.word 0x22C++0x1
line.word 0x0 "OTP_PARAM0,OTP_PARAM0_REG"
bitfld.word 0x0 14.--15. "TRD_20NS_LOW,For 28nm. Read pulse width lower two bits(higher two bits are in OTP_PARAM2_REG[12:11]). The default value is based on 32MHz LSB clock." "0,1,2,3"
hexmask.word.byte 0x0 10.--13. 1. "TSQ_MINUS_TRD,Read data access time the value to enter is tSQ(70ns)-tRD. The default value is based on 32MHz LSB clock."
hexmask.word 0x0 0.--9. 1. "TPGM_2US,Specify the width of the programming pulse (in number of pclk cycle) the number depends on the pclk frequency and the pulse width requirement (OTP macro specifies between 2us up to 10us)."
group.word 0x230++0x1
line.word 0x0 "OTP_PARAM1,OTP_PARAM1_REG"
hexmask.word.byte 0x0 11.--15. 1. "TSU_300NS,Specify setup time for few of the OTP control signals. The default value is based on 32MHz LSB clock."
hexmask.word 0x0 0.--10. 1. "TVHV_OFF_10US,Specify the VHV turn OFF time before the OTP read access. The default value is based on 32MHz"
group.word 0x234++0x1
line.word 0x0 "OTP_PARAM2,OTP_PARAM2_REG"
bitfld.word 0x0 11.--12. "TRD_20NS_HIGH,For 28nm Read pulse width higher two bits (lower two bits are in OTP_PARAM0_REG[15:14]). The default value is based on 32MHz LSB clock." "0,1,2,3"
hexmask.word 0x0 0.--10. 1. "TVHV_ON_10US,Specify the VHV turn ON time before the OTP programming access. The default value is based on 32MHz LSB clock."
group.word 0x238++0x1
line.word 0x0 "OTP_BYPASS_MODE0,OTP_BYPASS_MODE0_REG"
rbitfld.word 0x0 15. "MUX_RD_DONE,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)." "0,1"
rbitfld.word 0x0 14. "MUX_DOUT,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)." "0,1"
bitfld.word 0x0 8. "LOAD,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)." "0,1"
bitfld.word 0x0 7. "PGM_B,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)." "0,1"
newline
bitfld.word 0x0 6. "SCLK,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)." "0,1"
bitfld.word 0x0 0. "SET_OTP_BYPASS,SET OTP bypass mode all the OTP interface control signals are under register control by s/w." "0,1"
group.word 0x23C++0x1
line.word 0x0 "OTP_BYPASS_MODE1,OTP_BYPASS_MODE1_REG"
hexmask.word.byte 0x0 0.--6. 1. "BIT_ADDRESS,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)."
group.word 0x240++0x1
line.word 0x0 "OTP_TESTBUS_SEL,OTP_TESTBUS_SEL_REG"
hexmask.word.byte 0x0 0.--3. 1. "TESTBUS,OTP Test Bus"
rgroup.word 0x244++0x1
line.word 0x0 "OTP_TESTBUS,OTP_TESTBUS_REG"
hexmask.word 0x0 0.--15. 1. "TESTBUS,OTP Test Bus"
group.word 0x248++0x1
line.word 0x0 "OTP_BYPASS_MODE2,OTP_BYPASS_MODE2_REG"
hexmask.word 0x0 0.--15. 1. "CSB,Note: Only valid in the OTP BYPASS mode (OTP_BYPASS_MODE_REG[0]=1)."
group.word 0x24C++0x1
line.word 0x0 "OTP_RST_B,OTP_RST_B_REG"
hexmask.word 0x0 0.--15. 1. "OTP_RST_B,S/W reset bit to 'RST_B' input of each OTP macro"
group.word 0x250++0x1
line.word 0x0 "OTP_POR_B,OTP_POR_B_REG"
hexmask.word 0x0 0.--15. 1. "OTP_POR_B,S/W por bit to 'POR_B' input of each OTP macro."
group.word 0x25C++0x1
line.word 0x0 "OTP_WRITE_LOCK_REG,OTP_WRITE_LOCK_REG (Firecrest)"
bitfld.word 0x0 0. "OTP_WRITE_LOCK,'1 sticky bit once it is set it will stay at set state until POR_ONLY reset to 0." "0,1"
group.word 0x260++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_15_0,OTP_WRITE_DIS_REG[15:0] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[15:0]."
group.word 0x264++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_31_16,OTP_WRITE_DIS_REG[31:16] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[31:16]."
group.word 0x268++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_47_32,OTP_WRITE_DIS_REG[47:32] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[47:32]."
group.word 0x26C++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_63_48,OTP_WRITE_DIS_REG[63:48] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[63:48]."
group.word 0x270++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_79_64,OTP_WRITE_DIS_REG[79:64] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[79:64]."
group.word 0x274++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_95_80,OTP_WRITE_DIS_REG[95:80] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[95:80]."
group.word 0x278++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_111_96,OTP_WRITE_DIS_REG[111:96] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[111:96]."
group.word 0x27C++0x1
line.word 0x0 "OTP_WRITE_DIS_REG_127_112,OTP_WRITE_DIS_REG[127:112] (Firecrest)"
hexmask.word 0x0 0.--15. 1. "OTP_WRITE_DIS,OTP_Write_Disable bitmap for OTP Line[127:112]."
tree.end
tree "SOCCTRL"
base ad:0x45001000
group.long 0x0++0x3
line.long 0x0 "PAD_CONFIG0,'"
bitfld.long 0x0 30. "SD_D3_PU_CTRL,SD D3 PU Control function" "0,1"
bitfld.long 0x0 29. "LED_MODE,to enable disable led mode" "0,1"
newline
bitfld.long 0x0 28. "TRACE_PORT_MODE_CPU,Trace port mode enable" "0,1"
bitfld.long 0x0 26. "BT_DBG_UART_MODE_4PIN,BT 4 pin Debug Uart Mode" "0,1"
newline
bitfld.long 0x0 25. "WLAN_DBG_UART_MODE_4PIN,WLAN 4 Pin Debug Uart Mode" "0,1"
bitfld.long 0x0 24. "BT_DBG_UART_MODE,BT Debug Uart Mode" "0,1"
newline
bitfld.long 0x0 22. "BRF_W3_SOC_MASTER_SEL,BRF 3-Wire SoC Master Select" "0,1"
bitfld.long 0x0 20. "BRF_STDALONE,BRF Standalone" "0,1"
newline
bitfld.long 0x0 19. "CAU_STDALONE,CAU Standalone" "0,1"
bitfld.long 0x0 18. "RFU_STDALONE,RFU Standalone" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "ATEST_DIS_STDALONE_MODE_3_0,ATEST Pin Force disable Bits in standalone mode"
bitfld.long 0x0 11. "PAD_XOSC_EN_SEL,PAD XOSC Enable Control" "0,1"
newline
hexmask.long.byte 0x0 7.--10. 1. "ATEST_EN_3_0,ATEST Pin Force Bits"
bitfld.long 0x0 6. "RF_CNTL3_ATEST_EN,RF_CNTL3 pad ATEST mode Enable" "0,1"
newline
bitfld.long 0x0 5. "RF_CNTL2_ATEST_EN,RF_CNTL2 pad ATEST mode Enable" "0,1"
bitfld.long 0x0 4. "RF_CNTL1_ATEST_EN,RF_CNTL1 pad ATEST mode Enable" "0,1"
newline
bitfld.long 0x0 3. "RF_CNTL0_ATEST_EN,RF_CNTL0 pad ATEST mode Enable" "0,1"
bitfld.long 0x0 1. "PAD_PWRDOWN_LATCH,Enables the pd_sel latching" "0,1"
newline
bitfld.long 0x0 0. "ALL_PADS_TRISTATE_EN,Enable/disable Control for Pad Tristate" "0,1"
group.long 0x8++0x13
line.long 0x0 "PAD_PWRDOWN_CTRL0,Pad Power-down Control 0"
bitfld.long 0x0 28.--30. "GPIO7_PD_SEL,Power Down Output Value for GPIO[7] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24.--26. "GPIO6_PD_SEL,Power Down Output Value for GPIO[6] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20.--22. "GPIO5_PD_SEL,Power Down Output Value for GPIO[5] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "GPIO4_PD_SEL,Power Down Output Value for GPIO[4] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12.--14. "GPIO3_PD_SEL,Power Down Output Value for GPIO[3] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8.--10. "GPIO2_PD_SEL,Power Down Output Value for GPIO[2] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4.--6. "GPIO1_PD_SEL,Power Down Output Value for GPIO[1] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "GPIO0_PD_SEL,Power down output value for GPIO[0] pad" "0,1,2,3,4,5,6,7"
line.long 0x4 "PAD_PWRDOWN_CTRL1,Pad Power-down Control 1"
bitfld.long 0x4 28.--30. "GPIO21_PD_SEL,Power Down Output Value for GPIO[21] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 24.--26. "GPIO14_PD_SEL,Power Down Output Value for GPIO[14] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20.--22. "GPIO13_PD_SEL,Power Down Output Value for GPIO[13] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--18. "GPIO12_PD_SEL,Power Down Output Value for GPIO[12] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12.--14. "GPIO11_PD_SEL,Power Down Output Value for GPIO[11] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "GPIO10_PD_SEL,Power Down Output Value for GPIO[10] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4.--6. "GPIO9_PD_SEL,Power Down Output Value for GPIO[9] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "GPIO8_PD_SEL,Power Down Output Value for GPIO[8] Pad" "0,1,2,3,4,5,6,7"
line.long 0x8 "PAD_PWRDOWN_CTRL2,Pad Power-down Control 2"
bitfld.long 0x8 28.--30. "GPIO43_PD_SEL,Power Down Output Value for GPIO[43] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 24.--26. "GPIO42_PD_SEL,Power Down Output Value for GPIO[42] Pad" "0,1,2,3,4,5,6,7"
line.long 0xC "PAD_PWRDOWN_CTRL3,Pad Power-down Control 3"
bitfld.long 0xC 28.--30. "GPIO51_PD_SEL,Power Down Output Value for GPIO[51] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 24.--26. "GPIO50_PD_SEL,Power Down Output Value for GPIO[50] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 20.--22. "GPIO49_PD_SEL,Power Down Output Value for GPIO[49] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 16.--18. "GPIO48_PD_SEL,Power Down Output Value for GPIO[48] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 12.--14. "GPIO47_PD_SEL,Power Down Output Value for GPIO[47] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 8.--10. "GPIO46_PD_SEL,Power Down Output Value for GPIO[46] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 4.--6. "GPIO45_PD_SEL,Power Down Output Value for GPIO[45] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 0.--2. "GPIO44_PD_SEL,Power Down Output Value for GPIO[44] Pad" "0,1,2,3,4,5,6,7"
line.long 0x10 "PAD_PWRDOWN_CTRL4,Pad Power-down Control 4"
bitfld.long 0x10 28.--30. "GPIO59_PD_SEL,Power Down Output Value for GPIO[59] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "GPIO58_PD_SEL,Power Down Output Value for GPIO[58] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "GPIO57_PD_SEL,Power Down Output Value for GPIO[57] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "GPIO56_PD_SEL,Power Down Output Value for GPIO[56] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "GPIO55_PD_SEL,Power Down Output Value for GPIO[55] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "GPIO54_PD_SEL,Power Down Output Value for GPIO[54] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "GPIO53_PD_SEL,Power Down Output Value for GPIO[53] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "GPIO52_PD_SEL,Power Down Output Value for GPIO[52] Pad" "0,1,2,3,4,5,6,7"
group.long 0x2C++0xB
line.long 0x0 "PAD_PWRDOWN_CTRL5,Pad Power-down Control 5"
bitfld.long 0x0 28.--30. "RF_CNTL3_PD_SEL,Power Down Output Value for rf_cntl3 Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24.--26. "RF_CNTL2_PD_SEL,Power Down Output Value for rf_cntl2 Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20.--22. "RF_CNTL1_PD_SEL,Power Down Output Value for rf_cntl1 Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16.--18. "RF_CNTL0_PD_SEL,Power Down Output Value for rf_cntl0 Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12.--14. "GPIO63_PD_SEL,Power Down Output Value for GPIO[63] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8.--10. "GPIO62_PD_SEL,Power Down Output Value for GPIO[62] Pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4.--6. "GPIO61_PD_SEL,Power Down Output Value for GPIO[61] Pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "GPIO60_PD_SEL,Power Down Output Value for GPIO[60] Pad" "0,1,2,3,4,5,6,7"
line.long 0x4 "PAD_RF_SW_SLP_CONFIG,RF Switch Pad Sleep Mode Configuration"
bitfld.long 0x4 19. "RF_CNTL3_SLP_VAL,RF_CTRL3 Sleep Value" "0,1"
bitfld.long 0x4 18. "RF_CNTL2_SLP_VAL,RF_CTRL2 Sleep Value" "0,1"
newline
bitfld.long 0x4 17. "RF_CNTL1_SLP_VAL,RF_CTRL1 Sleep Value" "0,1"
bitfld.long 0x4 16. "RF_CNTL0_SLP_VAL,RF_CTRL0 Sleep Value" "0,1"
newline
bitfld.long 0x4 3. "RF_CNTL3_SLP_EN,RF_CNTL3 Sleep Force Enable" "0,1"
bitfld.long 0x4 2. "RF_CNTL2_SLP_EN,RF_CNTL2 Sleep Force Enable" "0,1"
newline
bitfld.long 0x4 1. "RF_CNTL1_SLP_EN,RF_CNTL1 Sleep Force Enable" "0,1"
bitfld.long 0x4 0. "RF_CNTL0_SLP_EN,RF_CNTL0 Sleep Force Enable" "0,1"
line.long 0x8 "PAD_ATEST_SW_SLP_CONFIG,ATEST Pad Sleep Mode Configuration"
bitfld.long 0x8 19. "ATEST3_SLP_VAL,ATEST3 Sleep Value" "0,1"
bitfld.long 0x8 18. "ATEST2_SLP_VAL,ATEST2 Sleep Value" "0,1"
newline
bitfld.long 0x8 17. "ATEST1_SLP_VAL,ATEST1 Sleep Value" "0,1"
bitfld.long 0x8 16. "ATEST0_SLP_VAL,ATEST0 Sleep Value" "0,1"
newline
bitfld.long 0x8 3. "ATEST3_SLP_EN,ATEST3 Sleep Force Enable" "0,1"
bitfld.long 0x8 2. "ATEST2_SLP_EN,ATEST2 Sleep Force Enable" "0,1"
newline
bitfld.long 0x8 1. "ATEST1_SLP_EN,ATEST1 Sleep Force Enable" "0,1"
bitfld.long 0x8 0. "ATEST0_SLP_EN,ATEST0 Sleep Force Enable" "0,1"
group.long 0x4C++0xF
line.long 0x0 "SR_CONFIG0,GPIO Slew Rate control"
bitfld.long 0x0 30.--31. "GPIO15_SR,Slew Rate Control for GPIO[15]" "0,1,2,3"
bitfld.long 0x0 28.--29. "GPIO14_SR,Slew Rate Control for GPIO[14]" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "GPIO13_SR,Slew Rate Control for GPIO[13]" "0,1,2,3"
bitfld.long 0x0 24.--25. "GPIO12_SR,Slew Rate Control for GPIO[12]" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "GPIO11_SR,Slew Rate Control for GPIO[11]" "0,1,2,3"
bitfld.long 0x0 20.--21. "GPIO10_SR,Slew Rate Control for GPIO[10]" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "GPIO9_SR,Slew Rate Control for GPIO[9]" "0,1,2,3"
bitfld.long 0x0 16.--17. "GPIO8_SR,Slew Rate Control for GPIO[8]" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "GPIO7_SR,Slew Rate Control for GPIO[7]" "0,1,2,3"
bitfld.long 0x0 12.--13. "GPIO6_SR,Slew Rate Control for GPIO[6]" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "GPIO5_SR,Slew Rate Control for GPIO[5]" "0,1,2,3"
bitfld.long 0x0 8.--9. "GPIO4_SR,Slew Rate Control for GPIO[4]" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "GPIO3_SR,Slew Rate Control for GPIO[3]" "0,1,2,3"
bitfld.long 0x0 4.--5. "GPIO2_SR,Slew Rate Control for GPIO[2]" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "GPIO1_SR,Slew Rate Control for GPIO[1]" "0,1,2,3"
bitfld.long 0x0 0.--1. "GPIO0_SR,Slew Rate Control for GPIO[0]" "0,1,2,3"
line.long 0x4 "SR_CONFIG1,GPIO Slew Rate control"
bitfld.long 0x4 30.--31. "GPIO31_SR,Slew Rate Control for GPIO[31]" "0,1,2,3"
bitfld.long 0x4 28.--29. "GPIO30_SR,Slew Rate Control for GPIO[30]" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "GPIO29_SR,Slew Rate Control for GPIO[29]" "0,1,2,3"
bitfld.long 0x4 24.--25. "GPIO28_SR,Slew Rate Control for GPIO[28]" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "GPIO21_SR,Slew Rate Control for GPIO[21]" "0,1,2,3"
bitfld.long 0x4 8.--9. "GPIO20_SR,Slew Rate Control for GPIO[20]" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "GPIO19_SR,Slew Rate Control for GPIO[19]" "0,1,2,3"
bitfld.long 0x4 4.--5. "GPIO18_SR,Slew Rate Control for GPIO[18]" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "GPIO17_SR,Slew Rate Control for GPIO[17]" "0,1,2,3"
bitfld.long 0x4 0.--1. "GPIO16_SR,Slew Rate Control for GPIO[16]" "0,1,2,3"
line.long 0x8 "SR_CONFIG2,GPIO Slew Rate control"
bitfld.long 0x8 30.--31. "GPIO47_SR,Slew Rate Control for GPIO[47]" "0,1,2,3"
bitfld.long 0x8 28.--29. "GPIO46_SR,Slew Rate Control for GPIO[46]" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "GPIO45_SR,Slew Rate Control for GPIO[45]" "0,1,2,3"
bitfld.long 0x8 24.--25. "GPIO44_SR,Slew Rate Control for GPIO[44]" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "GPIO43_SR,Slew Rate Control for GPIO[43]" "0,1,2,3"
bitfld.long 0x8 20.--21. "GPIO42_SR,Slew Rate Control for GPIO[42]" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "GPIO41_SR,Slew Rate Control for GPIO[41]" "0,1,2,3"
bitfld.long 0x8 16.--17. "GPIO40_SR,Slew Rate Control for GPIO[40]" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "GPIO39_SR,Slew Rate Control for GPIO[39]" "0,1,2,3"
bitfld.long 0x8 12.--13. "GPIO38_SR,Slew Rate Control for GPIO[38]" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "GPIO37_SR,Slew Rate Control for GPIO[37]" "0,1,2,3"
bitfld.long 0x8 8.--9. "GPIO36_SR,Slew Rate Control for GPIO[36]" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "GPIO35_SR,Slew Rate Control for GPIO[35]" "0,1,2,3"
bitfld.long 0x8 4.--5. "GPIO34_SR,Slew Rate Control for GPIO[34]" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "GPIO33_SR,Slew Rate Control for GPIO[33]" "0,1,2,3"
bitfld.long 0x8 0.--1. "GPIO32_SR,Slew Rate Control for GPIO[32]" "0,1,2,3"
line.long 0xC "SR_CONFIG3,GPIO Slew Rate control"
bitfld.long 0xC 30.--31. "GPIO63_SR,Slew Rate Control for GPIO[63]" "0,1,2,3"
bitfld.long 0xC 28.--29. "GPIO62_SR,Slew Rate Control for GPIO[62]" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "GPIO61_SR,Slew Rate Control for GPIO[61]" "0,1,2,3"
bitfld.long 0xC 24.--25. "GPIO60_SR,Slew Rate Control for GPIO[60]" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "GPIO59_SR,Slew Rate Control for GPIO[59]" "0,1,2,3"
bitfld.long 0xC 20.--21. "GPIO58_SR,Slew Rate Control for GPIO[58]" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "GPIO57_SR,Slew Rate Control for GPIO[57]" "0,1,2,3"
bitfld.long 0xC 16.--17. "GPIO56_SR,Slew Rate Control for GPIO[56]" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "GPIO55_SR,Slew Rate Control for GPIO[55]" "0,1,2,3"
bitfld.long 0xC 12.--13. "GPIO54_SR,Slew Rate Control for GPIO[54]" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "GPIO53_SR,Slew Rate Control for GPIO[53]" "0,1,2,3"
bitfld.long 0xC 8.--9. "GPIO52_SR,Slew Rate Control for GPIO[52]" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "GPIO51_SR,Slew Rate Control for GPIO[51]" "0,1,2,3"
bitfld.long 0xC 4.--5. "GPIO50_SR,Slew Rate Control for GPIO[50]" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "GPIO49_SR,Slew Rate Control for GPIO[49]" "0,1,2,3"
bitfld.long 0xC 0.--1. "GPIO48_SR,Slew Rate Control for GPIO[48]" "0,1,2,3"
group.long 0x64++0x7
line.long 0x0 "SR_CONFIG4,GPIO Slew Rate control"
bitfld.long 0x0 14.--15. "RF_CNTL3_SR,Slew Rate Control for rf_cntl3" "0,1,2,3"
bitfld.long 0x0 12.--13. "RF_CNTL2_SR,Slew Rate Control for rf_cntl2" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "RF_CNTL1_SR,Slew Rate Control for rf_cntl1" "0,1,2,3"
bitfld.long 0x0 8.--9. "RF_CNTL0_SR,Slew Rate Control for rf_cntl0" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ATEST3_SR,Slew Rate Control for atest3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ATEST2_SR,Slew Rate Control for atest2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ATEST1_SR,Slew Rate Control for atest1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ATEST0_SR,Slew Rate Control for atest0" "0,1,2,3"
line.long 0x4 "PAD_WKUP0,Pad Wakeup Mode Enable"
bitfld.long 0x4 0.--1. "ENABLE,Pad Wakeup Mode Enable [1:0]" "0,1,2,3"
group.long 0x70++0xF
line.long 0x0 "PAD_PU_PD_EN0,Pad Pull-up Pull-down Enable1"
bitfld.long 0x0 30.--31. "GPIO15_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[15]" "0,1,2,3"
bitfld.long 0x0 28.--29. "GPIO14_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[14]" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "GPIO13_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[13]" "0,1,2,3"
bitfld.long 0x0 24.--25. "GPIO12_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[12]" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "GPIO11_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[11]" "0,1,2,3"
bitfld.long 0x0 20.--21. "GPIO10_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[10]" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "GPIO9_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[9]" "0,1,2,3"
bitfld.long 0x0 16.--17. "GPIO8_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[8]" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "GPIO7_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[7]" "0,1,2,3"
bitfld.long 0x0 12.--13. "GPIO6_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[6]" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "GPIO5_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[5]" "0,1,2,3"
bitfld.long 0x0 8.--9. "GPIO4_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[4]" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "GPIO3_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[3]" "0,1,2,3"
bitfld.long 0x0 4.--5. "GPIO2_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[2]" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "GPIO1_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[1]" "0,1,2,3"
bitfld.long 0x0 0.--1. "GPIO0_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[0]" "0,1,2,3"
line.long 0x4 "PAD_PU_PD_EN1,Pad Pull-up Pull-down Enable2"
bitfld.long 0x4 30.--31. "GPIO31_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[31]" "0,1,2,3"
bitfld.long 0x4 28.--29. "GPIO30_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[30]" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "GPIO29_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[29]" "0,1,2,3"
bitfld.long 0x4 24.--25. "GPIO28_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[28]" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "GPIO21_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[21]" "0,1,2,3"
bitfld.long 0x4 8.--9. "GPIO20_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[20]" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "GPIO19_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[19]" "0,1,2,3"
bitfld.long 0x4 4.--5. "GPIO18_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[18]" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "GPIO17_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[17]" "0,1,2,3"
bitfld.long 0x4 0.--1. "GPIO16_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[16]" "0,1,2,3"
line.long 0x8 "PAD_PU_PD_EN2,Pad Pull-up Pull-down Enable2"
bitfld.long 0x8 30.--31. "GPIO47_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[47]" "0,1,2,3"
bitfld.long 0x8 28.--29. "GPIO46_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[46]" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "GPIO45_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[45]" "0,1,2,3"
bitfld.long 0x8 24.--25. "GPIO44_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[44]" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "GPIO43_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[43]" "0,1,2,3"
bitfld.long 0x8 20.--21. "GPIO42_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[42]" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "GPIO41_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[41]" "0,1,2,3"
bitfld.long 0x8 16.--17. "GPIO40_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[40]" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "GPIO39_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[39]" "0,1,2,3"
bitfld.long 0x8 12.--13. "GPIO38_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[38]" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "GPIO37_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[37]" "0,1,2,3"
bitfld.long 0x8 8.--9. "GPIO36_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[36]" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "GPIO35_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[35]" "0,1,2,3"
bitfld.long 0x8 4.--5. "GPIO34_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[34]" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "GPIO33_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[33]" "0,1,2,3"
bitfld.long 0x8 0.--1. "GPIO32_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[32]" "0,1,2,3"
line.long 0xC "PAD_PU_PD_EN3,Pad Pull-up Pull-down Enable2"
bitfld.long 0xC 30.--31. "GPIO63_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[63]" "0,1,2,3"
bitfld.long 0xC 28.--29. "GPIO62_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[62]" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "GPIO61_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[61]" "0,1,2,3"
bitfld.long 0xC 24.--25. "GPIO60_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[60]" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "GPIO59_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[59]" "0,1,2,3"
bitfld.long 0xC 20.--21. "GPIO58_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[58]" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "GPIO57_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[57]" "0,1,2,3"
bitfld.long 0xC 16.--17. "GPIO56_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[56]" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "GPIO55_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[55]" "0,1,2,3"
bitfld.long 0xC 12.--13. "GPIO54_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[54]" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "GPIO53_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[53]" "0,1,2,3"
bitfld.long 0xC 8.--9. "GPIO52_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[52]" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "GPIO51_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[51]" "0,1,2,3"
bitfld.long 0xC 4.--5. "GPIO50_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[50]" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "GPIO49_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[49]" "0,1,2,3"
bitfld.long 0xC 0.--1. "GPIO48_PU_PD_EN,Internal Pd and Internal Pu Config for GPIO[48]" "0,1,2,3"
group.long 0x88++0xB
line.long 0x0 "PAD_PU_PD_EN4,Pad Pull-up Pull-down Enable2"
bitfld.long 0x0 6.--7. "ATEST3_PU_PD_EN,Internal Pd and Internal Pu Config for ATEST3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ATEST2_PU_PD_EN,Internal Pd and Internal Pu Config for ATEST2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ATEST1_PU_PD_EN,Internal Pd and Internal Pu Config for ATEST1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ATEST0_PU_PD_EN,Internal Pd and Internal Pu Config for ATEST0" "0,1,2,3"
line.long 0x4 "PAD_SLP_EN0,Pad Sleep Mode Enable"
bitfld.long 0x4 31. "GPIO31_SLP_EN,Enable Forcing GPIO[31] Output During Sleep" "0,1"
bitfld.long 0x4 30. "GPIO30_SLP_EN,Enable Forcing GPIO[30] Output During Sleep" "0,1"
newline
bitfld.long 0x4 29. "GPIO29_SLP_EN,Enable Forcing GPIO[29] Output During Sleep" "0,1"
bitfld.long 0x4 28. "GPIO28_SLP_EN,Enable Forcing GPIO[28] Output During Sleep" "0,1"
newline
bitfld.long 0x4 21. "GPIO21_SLP_EN,Enable Forcing GPIO[21] Output During Sleep" "0,1"
bitfld.long 0x4 20. "GPIO20_SLP_EN,Enable Forcing GPIO[20] Output During Sleep" "0,1"
newline
bitfld.long 0x4 19. "GPIO19_SLP_EN,Enable Forcing GPIO[19] Output During Sleep" "0,1"
bitfld.long 0x4 18. "GPIO18_SLP_EN,Enable Forcing GPIO[18] Output During Sleep" "0,1"
newline
bitfld.long 0x4 17. "GPIO17_SLP_EN,Enable Forcing GPIO[17] Output During Sleep" "0,1"
bitfld.long 0x4 16. "GPIO16_SLP_EN,Enable Forcing GPIO[16] Output During Sleep" "0,1"
newline
bitfld.long 0x4 15. "GPIO15_SLP_EN,Enable Forcing GPIO[15] Output During Sleep" "0,1"
bitfld.long 0x4 14. "GPIO14_SLP_EN,Enable Forcing GPIO[14] Output During Sleep" "0,1"
newline
bitfld.long 0x4 13. "GPIO13_SLP_EN,Enable Forcing GPIO[13] Output During Sleep" "0,1"
bitfld.long 0x4 12. "GPIO12_SLP_EN,Enable Forcing GPIO[12] Output During Sleep" "0,1"
newline
bitfld.long 0x4 11. "GPIO11_SLP_EN,Enable Forcing GPIO[11] Output During Sleep" "0,1"
bitfld.long 0x4 10. "GPIO10_SLP_EN,Enable Forcing GPIO[10] Output During Sleep" "0,1"
newline
bitfld.long 0x4 9. "GPIO9_SLP_EN,Enable Forcing GPIO[9] Output During Sleep" "0,1"
bitfld.long 0x4 8. "GPIO8_SLP_EN,Enable Forcing GPIO[8] Output During Sleep" "0,1"
newline
bitfld.long 0x4 7. "GPIO7_SLP_EN,Enable Forcing GPIO[7] Output During Sleep" "0,1"
bitfld.long 0x4 6. "GPIO6_SLP_EN,Enable Forcing GPIO[6] Output During Sleep" "0,1"
newline
bitfld.long 0x4 5. "GPIO5_SLP_EN,Enable Forcing GPIO[5] Output During Sleep" "0,1"
bitfld.long 0x4 4. "GPIO4_SLP_EN,Enable Forcing GPIO[4] Output During Sleep" "0,1"
newline
bitfld.long 0x4 3. "GPIO3_SLP_EN,Enable Forcing GPIO[3] Output During Sleep" "0,1"
bitfld.long 0x4 2. "GPIO2_SLP_EN,Enable Forcing GPIO[2] Output During Sleep" "0,1"
newline
bitfld.long 0x4 1. "GPIO1_SLP_EN,Enable Forcing GPIO[1] Output During Sleep" "0,1"
bitfld.long 0x4 0. "GPIO0_SLP_EN,Enable Forcing GPIO[0] Output During Sleep" "0,1"
line.long 0x8 "PAD_SLP_EN1,Pad Sleep Mode Enable"
bitfld.long 0x8 31. "GPIO63_SLP_EN,Enable Forcing GPIO[63] Output During Sleep" "0,1"
bitfld.long 0x8 30. "GPIO62_SLP_EN,Enable Forcing GPIO[62] Output During Sleep" "0,1"
newline
bitfld.long 0x8 29. "GPIO61_SLP_EN,Enable Forcing GPIO[61] Output During Sleep" "0,1"
bitfld.long 0x8 28. "GPIO60_SLP_EN,Enable Forcing GPIO[60] Output During Sleep" "0,1"
newline
bitfld.long 0x8 27. "GPIO59_SLP_EN,Enable Forcing GPIO[59] Output During Sleep" "0,1"
bitfld.long 0x8 26. "GPIO58_SLP_EN,Enable Forcing GPIO[58] Output During Sleep" "0,1"
newline
bitfld.long 0x8 25. "GPIO57_SLP_EN,Enable Forcing GPIO[57] Output During Sleep" "0,1"
bitfld.long 0x8 24. "GPIO56_SLP_EN,Enable Forcing GPIO[56] Output During Sleep" "0,1"
newline
bitfld.long 0x8 23. "GPIO55_SLP_EN,Enable Forcing GPIO[55] Output During Sleep" "0,1"
bitfld.long 0x8 22. "GPIO54_SLP_EN,Enable Forcing GPIO[54] Output During Sleep" "0,1"
newline
bitfld.long 0x8 21. "GPIO53_SLP_EN,Enable Forcing GPIO[53] Output During Sleep" "0,1"
bitfld.long 0x8 20. "GPIO52_SLP_EN,Enable Forcing GPIO[52] Output During Sleep" "0,1"
newline
bitfld.long 0x8 19. "GPIO51_SLP_EN,Enable Forcing GPIO[51] Output During Sleep" "0,1"
bitfld.long 0x8 18. "GPIO50_SLP_EN,Enable Forcing GPIO[50] Output During Sleep" "0,1"
newline
bitfld.long 0x8 17. "GPIO49_SLP_EN,Enable Forcing GPIO[49] Output During Sleep" "0,1"
bitfld.long 0x8 16. "GPIO48_SLP_EN,Enable Forcing GPIO[48] Output During Sleep" "0,1"
newline
bitfld.long 0x8 15. "GPIO47_SLP_EN,Enable Forcing GPIO[47] Output During Sleep" "0,1"
bitfld.long 0x8 14. "GPIO46_SLP_EN,Enable Forcing GPIO[46] Output During Sleep" "0,1"
newline
bitfld.long 0x8 13. "GPIO45_SLP_EN,Enable Forcing GPIO[45] Output During Sleep" "0,1"
bitfld.long 0x8 12. "GPIO44_SLP_EN,Enable Forcing GPIO[44] Output During Sleep" "0,1"
newline
bitfld.long 0x8 11. "GPIO43_SLP_EN,Enable Forcing GPIO[43] Output During Sleep" "0,1"
bitfld.long 0x8 10. "GPIO42_SLP_EN,Enable Forcing GPIO[42] Output During Sleep" "0,1"
newline
bitfld.long 0x8 9. "GPIO41_SLP_EN,Enable Forcing GPIO[41] Output During Sleep" "0,1"
bitfld.long 0x8 8. "GPIO40_SLP_EN,Enable Forcing GPIO[40] Output During Sleep" "0,1"
newline
bitfld.long 0x8 7. "GPIO39_SLP_EN,Enable Forcing GPIO[39] Output During Sleep" "0,1"
bitfld.long 0x8 6. "GPIO38_SLP_EN,Enable Forcing GPIO[38] Output During Sleep" "0,1"
newline
bitfld.long 0x8 5. "GPIO37_SLP_EN,Enable Forcing GPIO[37] Output During Sleep" "0,1"
bitfld.long 0x8 4. "GPIO36_SLP_EN,Enable Forcing GPIO[36] Output During Sleep" "0,1"
newline
bitfld.long 0x8 3. "GPIO35_SLP_EN,Enable Forcing GPIO[35] Output During Sleep" "0,1"
bitfld.long 0x8 2. "GPIO34_SLP_EN,Enable Forcing GPIO[34] Output During Sleep" "0,1"
newline
bitfld.long 0x8 1. "GPIO33_SLP_EN,Enable Forcing GPIO[33] Output During Sleep" "0,1"
bitfld.long 0x8 0. "GPIO32_SLP_EN,Enable Forcing GPIO[32] Output During Sleep" "0,1"
group.long 0x98++0x7
line.long 0x0 "PAD_SLP_VAL0,Pad Sleep Mode Value"
bitfld.long 0x0 31. "GPIO31_SLP_VAL,Force GPIO[31] Output During Sleep" "0,1"
bitfld.long 0x0 30. "GPIO30_SLP_VAL,Force GPIO[30] Output During Sleep" "0,1"
newline
bitfld.long 0x0 29. "GPIO29_SLP_VAL,Force GPIO[29] Output During Sleep" "0,1"
bitfld.long 0x0 28. "GPIO28_SLP_VAL,Force GPIO[28] Output During Sleep" "0,1"
newline
bitfld.long 0x0 21. "GPIO21_SLP_VAL,Force GPIO[21] Output During Sleep" "0,1"
bitfld.long 0x0 20. "GPIO20_SLP_VAL,Force GPIO[20] Output During Sleep" "0,1"
newline
bitfld.long 0x0 19. "GPIO19_SLP_VAL,Force GPIO[19] Output During Sleep" "0,1"
bitfld.long 0x0 18. "GPIO18_SLP_VAL,Force GPIO[18] Output During Sleep" "0,1"
newline
bitfld.long 0x0 17. "GPIO17_SLP_VAL,Force GPIO[17] Output During Sleep" "0,1"
bitfld.long 0x0 16. "GPIO16_SLP_VAL,Force GPIO[16] Output During Sleep" "0,1"
newline
bitfld.long 0x0 15. "GPIO15_SLP_VAL,Force GPIO[15] Output During Sleep" "0,1"
bitfld.long 0x0 14. "GPIO14_SLP_VAL,Force GPIO[14] Output During Sleep" "0,1"
newline
bitfld.long 0x0 13. "GPIO13_SLP_VAL,Force GPIO[13] Output During Sleep" "0,1"
bitfld.long 0x0 12. "GPIO12_SLP_VAL,Force GPIO[12] Output During Sleep" "0,1"
newline
bitfld.long 0x0 11. "GPIO11_SLP_VAL,Force GPIO[11] Output During Sleep" "0,1"
bitfld.long 0x0 10. "GPIO10_SLP_VAL,Force GPIO[10] Output During Sleep" "0,1"
newline
bitfld.long 0x0 9. "GPIO9_SLP_VAL,Force GPIO[9] Output During Sleep" "0,1"
bitfld.long 0x0 8. "GPIO8_SLP_VAL,Force GPIO[8] Output During Sleep" "0,1"
newline
bitfld.long 0x0 7. "GPIO7_SLP_VAL,Force GPIO[7] Output During Sleep" "0,1"
bitfld.long 0x0 6. "GPIO6_SLP_VAL,Force GPIO[6] Output During Sleep" "0,1"
newline
bitfld.long 0x0 5. "GPIO5_SLP_VAL,Force GPIO[5] Output During Sleep" "0,1"
bitfld.long 0x0 4. "GPIO4_SLP_VAL,Force GPIO[4] Output During Sleep" "0,1"
newline
bitfld.long 0x0 3. "GPIO3_SLP_VAL,Force GPIO[3] Output During Sleep" "0,1"
bitfld.long 0x0 2. "GPIO2_SLP_VAL,Force GPIO[2] Output During Sleep" "0,1"
newline
bitfld.long 0x0 1. "GPIO1_SLP_VAL,Force GPIO[1] Output During Sleep" "0,1"
bitfld.long 0x0 0. "GPIO0_SLP_VAL,Force GPIO[0] Output During Sleep" "0,1"
line.long 0x4 "PAD_SLP_VAL1,Pad Sleep Mode Value"
bitfld.long 0x4 31. "GPIO63_SLP_VAL,Force GPIO[63] Output During Sleep" "0,1"
bitfld.long 0x4 30. "GPIO62_SLP_VAL,Force GPIO[62] Output During Sleep" "0,1"
newline
bitfld.long 0x4 29. "GPIO61_SLP_VAL,Force GPIO[61] Output During Sleep" "0,1"
bitfld.long 0x4 28. "GPIO60_SLP_VAL,Force GPIO[60] Output During Sleep" "0,1"
newline
bitfld.long 0x4 27. "GPIO59_SLP_VAL,Force GPIO[59] Output During Sleep" "0,1"
bitfld.long 0x4 26. "GPIO58_SLP_VAL,Force GPIO[58] Output During Sleep" "0,1"
newline
bitfld.long 0x4 25. "GPIO57_SLP_VAL,Force GPIO[57] Output During Sleep" "0,1"
bitfld.long 0x4 24. "GPIO56_SLP_VAL,Force GPIO[56] Output During Sleep" "0,1"
newline
bitfld.long 0x4 23. "GPIO55_SLP_VAL,Force GPIO[55] Output During Sleep" "0,1"
bitfld.long 0x4 22. "GPIO54_SLP_VAL,Force GPIO[54] Output During Sleep" "0,1"
newline
bitfld.long 0x4 21. "GPIO53_SLP_VAL,Force GPIO[53] Output During Sleep" "0,1"
bitfld.long 0x4 20. "GPIO52_SLP_VAL,Force GPIO[52] Output During Sleep" "0,1"
newline
bitfld.long 0x4 19. "GPIO51_SLP_VAL,Force GPIO[51] Output During Sleep" "0,1"
bitfld.long 0x4 18. "GPIO50_SLP_VAL,Force GPIO[50] Output During Sleep" "0,1"
newline
bitfld.long 0x4 17. "GPIO49_SLP_VAL,Force GPIO[49] Output During Sleep" "0,1"
bitfld.long 0x4 16. "GPIO48_SLP_VAL,Force GPIO[48] Output During Sleep" "0,1"
newline
bitfld.long 0x4 15. "GPIO47_SLP_VAL,Force GPIO[47] Output During Sleep" "0,1"
bitfld.long 0x4 14. "GPIO46_SLP_VAL,Force GPIO[46] Output During Sleep" "0,1"
newline
bitfld.long 0x4 13. "GPIO45_SLP_VAL,Force GPIO[45] Output During Sleep" "0,1"
bitfld.long 0x4 12. "GPIO44_SLP_VAL,Force GPIO[44] Output During Sleep" "0,1"
newline
bitfld.long 0x4 11. "GPIO43_SLP_VAL,Force GPIO[43] Output During Sleep" "0,1"
bitfld.long 0x4 10. "GPIO42_SLP_VAL,Force GPIO[42] Output During Sleep" "0,1"
newline
bitfld.long 0x4 9. "GPIO41_SLP_VAL,Force GPIO[41] Output During Sleep" "0,1"
bitfld.long 0x4 8. "GPIO40_SLP_VAL,Force GPIO[40] Output During Sleep" "0,1"
newline
bitfld.long 0x4 7. "GPIO39_SLP_VAL,Force GPIO[39] Output During Sleep" "0,1"
bitfld.long 0x4 6. "GPIO38_SLP_VAL,Force GPIO[38] Output During Sleep" "0,1"
newline
bitfld.long 0x4 5. "GPIO37_SLP_VAL,Force GPIO[37] Output During Sleep" "0,1"
bitfld.long 0x4 4. "GPIO36_SLP_VAL,Force GPIO[36] Output During Sleep" "0,1"
newline
bitfld.long 0x4 3. "GPIO35_SLP_VAL,Force GPIO[35] Output During Sleep" "0,1"
bitfld.long 0x4 2. "GPIO34_SLP_VAL,Force GPIO[34] Output During Sleep" "0,1"
newline
bitfld.long 0x4 1. "GPIO33_SLP_VAL,Force GPIO[33] Output During Sleep" "0,1"
bitfld.long 0x4 0. "GPIO32_SLP_VAL,Force GPIO[32] Output During Sleep" "0,1"
rgroup.long 0x100++0x3
line.long 0x0 "PSW_VD2_RDY0,Power Switch VD2_RDY Status"
hexmask.long 0x0 0.--31. 1. "PSW_STATUS,VD2_RDY Status of following Power Switches:"
group.long 0x104++0xB
line.long 0x0 "PSW_ECO_CTRL,Power Switch ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "CLK_SW,Clock Controls for SOC_CLK_TOP"
bitfld.long 0x4 17. "SOC_AHB_CLK_SEL,SOC TOP AHB Clock Frequency Select" "0,1"
bitfld.long 0x4 16. "CAU_SIF_CLK_SEL,CAU SIF Clock Frequency Select" "0,1"
newline
bitfld.long 0x4 11. "BT_CM3_CSCLKEN,clk en for CPU2 ATB (ETM and ITM) and CTI interface" "0,1"
bitfld.long 0x4 10. "WL_CM3_CSCLKEN,clk en for CPU1 ATB (ETM and ITM) and CTI interface" "0,1"
newline
bitfld.long 0x4 9. "CSCLKEN,clk en for SOC Coresight system (includes CTI CTM TPIU ATB Funnel ATB upsizer)" "0,1"
bitfld.long 0x4 7. "BT_CM3_DAPCLKEN,clk en for CPU2 DAP interface" "0,1"
newline
bitfld.long 0x4 6. "WL_CM3_DAPCLKEN,clk en for CPU1 DAP interface" "0,1"
bitfld.long 0x4 5. "DAPCLKEN,clk en for SOC DAP" "0,1"
newline
bitfld.long 0x4 1. "AHB2APB_CLK_EN,'" "0,1"
bitfld.long 0x4 0. "CAU_SIF_AHB_CLK_EN,'" "0,1"
line.long 0x8 "RST_SW,Reset Controls for SOC_RESET_GEN"
bitfld.long 0x8 23. "MSC_ITRC_CHIP_RSTB_EN,Default the itrc chip reset can reset MSC SW can disable this if not required" "0,1"
bitfld.long 0x8 22. "BLE_ITRC_CHIP_RSTB_EN,Default the itrc chip reset can reset BLE SW can disable this if not required" "0,1"
newline
bitfld.long 0x8 21. "WL_ITRC_CHIP_RSTB_EN,Default the itrc chip reset can reset WLAN SW can disable this if not required" "0,1"
bitfld.long 0x8 20. "SOC_ITRC_CHIP_RSTB_EN,Default the itrc chip reset can reset SOC SW can disable this if not required" "0,1"
newline
hexmask.long.byte 0x8 12.--19. 1. "WLAN_N_BLE_PORB_DELAY,PORB delay for wlan and ble bootrom can use this feature if needed"
bitfld.long 0x8 11. "DAP_RESETN,SW reset for the dap_resetn" "0,1"
newline
bitfld.long 0x8 10. "CSSYS_RESETN,SW reset for the cssys cs resetn" "0,1"
bitfld.long 0x8 5. "HCLK_,Auto clear SW reset for socciu" "0,1"
newline
bitfld.long 0x8 4. "AHB2APB_HRESETN,'" "0,1"
bitfld.long 0x8 3. "DRO_RSTN,DRO Clock Reset" "0,1"
newline
bitfld.long 0x8 2. "SOC_PERI_HRESETN,Falling edge detected on this in RTL to reset the ahb bus" "0,1"
bitfld.long 0x8 1. "CAU_SIF_HRESETN,'" "0,1"
newline
bitfld.long 0x8 0. "CAU_SIF_RSTN,'" "0,1"
rgroup.long 0x114++0x3
line.long 0x0 "CHIP_INFO,Chip Information"
hexmask.long.byte 0x0 8.--15. 1. "ID,Chip ID"
hexmask.long.byte 0x0 0.--7. 1. "REV_NUM,Chip Revision Number"
group.long 0x118++0x7
line.long 0x0 "AHB_TO_CTRL,SOCPERI AHB ARB Control"
bitfld.long 0x0 30.--31. "AHB_TIMEOUT_MODE,AHB_TimeoutMode[1:0]" "0,1,2,3"
hexmask.long.byte 0x0 12.--15. 1. "LAST_TO_MASTER_ID,SOC PERI AHB Last_TO_Master_ID"
newline
hexmask.long.byte 0x0 8.--11. 1. "CURRENT_TO_MASTER_ID,SOCPERI Current_TO_Master_ID"
hexmask.long.byte 0x0 4.--7. 1. "LAST_TO_SLAVE_ID,Last_TO_Slave_ID"
newline
hexmask.long.byte 0x0 0.--3. 1. "CURRENT_TO_SLAVE_ID,Current_TO_Slave_ID"
line.long 0x4 "AHB_TO_CLEAR,AHB timeout logic clear register"
bitfld.long 0x4 0. "AHB_TIMEOUT_CLEAR,After the timeout happened on SOCPERI AHB bus the cpu will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the SOCPERI AHB timeout logic to start recording next transaction. This is.." "0,1"
rgroup.long 0x120++0x7
line.long 0x0 "AHB_TO_LAST_ADDR,SOCPERI AHB Timeout Last Address"
hexmask.long 0x0 0.--31. 1. "ADDRESS,Last AHB Address Right Before the Current Timeout"
line.long 0x4 "AHB_TO_CUR_ADDR,SOCPERI AHB Current Timeout Address"
hexmask.long 0x4 0.--31. 1. "ADDRESS,Current_TO_Addr"
group.long 0x134++0x3
line.long 0x0 "MCI_POWER_MODE_STATUS,MCI POWER MODE Status"
bitfld.long 0x0 5. "CPU3_FW_READY,cpu3 FW sets this bit after cpu1 FW initialization is done." "0,1"
rbitfld.long 0x0 4. "CM33_RESET_N,CM33 Reset status. Active low." "0,1"
newline
rbitfld.long 0x0 3. "MCI_BIST_DONE,MCI g2bist done status" "0,1"
rbitfld.long 0x0 0.--2. "MCI_SLP_STATE,MCI Power Mode Status" "0,1,2,3,4,5,6,7"
rgroup.long 0x138++0x3
line.long 0x0 "PSW_VD2_RDY1,Power Switch VD2_RDY Status"
hexmask.long 0x0 0.--31. 1. "PSW_STATUS,VD2_RDY Status of following Power Switches:"
group.long 0x140++0x7
line.long 0x0 "WLAN_POWER_STATUS,WLAN POWER Status"
bitfld.long 0x0 5. "CPU1_FW_READY,cpu1 FW sets this bit after cpu1 FW initialization is done." "0,1"
rbitfld.long 0x0 4. "CPU1_RESET_N,CPU1 Reset status. Active low." "0,1"
newline
rbitfld.long 0x0 3. "CPU1_BIST_DONE,CPU1 memories g2bist done status" "0,1"
rbitfld.long 0x0 2. "CPU1_SLEEP,CPU1 cp15 sleep status" "0,1"
newline
rbitfld.long 0x0 1. "WLGATED_PSW_PD,WLAN-GATED domain power-switch control status:" "0,1"
rbitfld.long 0x0 0. "WLRET_PSW_PD,WLAN-RETENTION domain power-switch control status:" "0,1"
line.long 0x4 "BLE_POWER_STATUS,BLE POWER Status"
bitfld.long 0x4 5. "CPU2_FW_READY,cpu2 FW sets this bit after cpu2 FW initialization is done." "0,1"
rbitfld.long 0x4 4. "CPU2_RESET_N,CPU2 Reset status. Active low." "0,1"
newline
rbitfld.long 0x4 3. "CPU2_BIST_DONE,CPU2 memories g2bist done status" "0,1"
rbitfld.long 0x4 2. "CPU2_SLEEP,CPU2 cp15 sleep status" "0,1"
newline
rbitfld.long 0x4 1. "BLEGATED_PSW_PD,BLE-GATED domain power-switch control status:" "0,1"
rbitfld.long 0x4 0. "BLERET_PSW_PD,BLE-RETENTION domain power-switch control status:" "0,1"
group.long 0x200++0x3
line.long 0x0 "PAD_VREG_VSENSOR_CTRL,Vsensor and Vreg Pad Control"
rbitfld.long 0x0 28. "VIO_X6_VSENSOR_DETECT,VIO_X6_Vsensor_Detect_V18 Status" "0,1"
rbitfld.long 0x0 27. "VIO_X5_VSENSOR_DETECT,VIO_X5_Vsensor_Detect_V18 Status" "0,1"
newline
rbitfld.long 0x0 26. "VIO_X4_VSENSOR_DETECT,VIO_X4_Vsensor_Detect_V18 Status" "0,1"
rbitfld.long 0x0 25. "VIO_X3_VSENSOR_DETECT,VIO_X3_Vsensor_Detect_V18 Status" "0,1"
newline
rbitfld.long 0x0 24. "VIO_X2_VSENSOR_DETECT,VIO_X2_Vsensor_Detect_V18 Status" "0,1"
rbitfld.long 0x0 23. "VIO_X1_VSENSOR_DETECT,VIO_X1_Vsensor_Detect_V18 Status" "0,1"
newline
rbitfld.long 0x0 22. "VIO_X0_VSENSOR_DETECT,VIO_X0_Vsensor_Detect_V18 Status" "0,1"
bitfld.long 0x0 21. "V25EN_CORE,V25EN_CORE" "0,1"
newline
bitfld.long 0x0 20. "VSENSOR_VTHRESH,Vsensor Detection Threshold" "0,1"
bitfld.long 0x0 17.--19. "VSENSOR_TEST,Vsensor Test Point Mux Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "VSENSOR_TE,Vsensor Test Enable" "0,1"
bitfld.long 0x0 15. "VSENSOR_CLK_12,Vsensor Clock" "0,1"
newline
bitfld.long 0x0 14. "VSENSOR_DISABLE_12,Vsensor X1 disable" "0,1"
bitfld.long 0x0 13. "VSENSOR_V18EN_12_IN,Bypass Value when Vsensor_Bypass Bit Set" "0,1"
newline
bitfld.long 0x0 12. "VSENSOR_BYPASS,Active High Enable Signal for Bypass Mode" "0,1"
bitfld.long 0x0 7. "VIO_REG6_CTRL_EN,VIO_X6 Pad Regulator control" "0,1"
newline
bitfld.long 0x0 6. "VIO_REG6_ENB,VIO_6 Pad Regulator" "0,1"
bitfld.long 0x0 5. "VIO_REG5_CTRL_EN,VIO_X5 Pad Regulator control" "0,1"
newline
bitfld.long 0x0 4. "VIO_REG5_ENB,VIO_5 Pad Regulator" "0,1"
bitfld.long 0x0 3. "VIO_REG4_CTRL_EN,VIO_X4 Pad Regulator control" "0,1"
newline
bitfld.long 0x0 2. "VIO_REG4_ENB,VIO_4 Pad Regulator" "0,1"
bitfld.long 0x0 1. "VIO_REG1_CTRL_EN,VIO_X1 Pad Regulator control" "0,1"
newline
bitfld.long 0x0 0. "VIO_REG1_ENB,VIO_X1 Pad Regulator" "0,1"
group.long 0x208++0x3
line.long 0x0 "PAD_RF_VREG_VSENSOR_CTRL,RF Vsensor and Vreg Pad Control"
rbitfld.long 0x0 14. "VSENSOR_DETECT,VIO_RF_Vsensor_Detect_V18 Status" "0,1"
bitfld.long 0x0 13. "V25EN_CORE,V25EN_CORE" "0,1"
newline
bitfld.long 0x0 12. "VSENSOR_VTHRESH,Vsensor RF Detection Threshold" "0,1"
bitfld.long 0x0 9.--11. "VSENSOR_TEST,Vsensor RF Test Point Mux Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "VSENSOR_TE,Vsensor RF Test Enable" "0,1"
bitfld.long 0x0 7. "VSENSOR_CLK_12,Vsensor RF Clock" "0,1"
newline
bitfld.long 0x0 6. "VSENSOR_DISABLE_12,Vsensor RF disable" "0,1"
bitfld.long 0x0 5. "VSENSOR_V18EN_12_IN,Bypass Value when Vsensor_Bypass Bit Set" "0,1"
newline
bitfld.long 0x0 4. "VSENSOR_BYPASS,Active High Enable Signal for Bypass Mode" "0,1"
bitfld.long 0x0 1. "VIO_REG0_CTRL_EN,VIO reg0 control enable Function" "0,1"
newline
bitfld.long 0x0 0. "VIO_REG_ENB,VIO_RF Pad Regulator" "0,1"
group.long 0x21C++0x3
line.long 0x0 "PAD_SD_VREG_VSENSOR_CTRL,SD Vsensor and Vreg Pad Control"
rbitfld.long 0x0 14. "VSENSOR_DETECT,VIO_SD_Vsensor_Detect_V18 Status" "0,1"
bitfld.long 0x0 13. "V25EN_CORE,V25EN_CORE" "0,1"
newline
bitfld.long 0x0 12. "VSENSOR_VTHRESH,Vsensor SD Detection Threshold" "0,1"
bitfld.long 0x0 9.--11. "VSENSOR_TEST,Vsensor SD Test Point Mux Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "VSENSOR_TE,Vsensor SD Test Enable" "0,1"
bitfld.long 0x0 7. "VSENSOR_CLK_12,Vsensor SD Clock" "0,1"
newline
bitfld.long 0x0 6. "VSENSOR_DISABLE_12,Vsensor SD disable" "0,1"
bitfld.long 0x0 5. "VSENSOR_V18EN_12_IN,Bypass Value when Vsensor_Bypass Bit Set" "0,1"
newline
bitfld.long 0x0 4. "VSENSOR_BYPASS,Active High Enable Signal for Bypass Mode" "0,1"
bitfld.long 0x0 1. "VIO_REG_CTRL_EN,VIO reg control enable function" "0,1"
newline
bitfld.long 0x0 0. "VIO_REG_ENB,VIO_SD Pad Regulator" "0,1"
group.long 0x37C++0x3
line.long 0x0 "PAD_ECO_CTRL,Pad ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0x424++0x7
line.long 0x0 "TST_TSTBUS_CTRL1,Testbus Mux Control1"
bitfld.long 0x0 4.--6. "SOC_PERI_TB_SEL,Select for soc peri testbus:" "0,1,2,3,4,5,6,7"
line.long 0x4 "TST_TSTBUS_CTRL2,Testbus Mux Control2"
bitfld.long 0x4 20. "POR_MON_SEL,POR MON Testbus Select (to support more power domain busses)" "0,1"
bitfld.long 0x4 19. "CLK_OUT_EN_ALT,Clock Out Enable" "0,1"
newline
bitfld.long 0x4 18. "CLK_OUT_EN,Clock Out Enable" "0,1"
bitfld.long 0x4 16.--17. "CLK_OUT_PAGE_SEL,Clock out test page sel" "0,1,2,3"
newline
hexmask.long.byte 0x4 12.--15. 1. "CLK_OUT_SEL,//PAGE 0"
rgroup.long 0x430++0x3
line.long 0x0 "TST_CTRL,Test Control"
hexmask.long.byte 0x0 0.--3. 1. "RBIST_DONE,[3]: HMAC g2bist finish"
group.long 0x47C++0x3
line.long 0x0 "TST_ECO_CTRL,Test ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0x488++0x3
line.long 0x0 "DRO_CTRL,DRO Control"
hexmask.long 0x0 4.--31. 1. "DRO_COUNT_LIMIT,DRO Count Value"
rbitfld.long 0x0 2. "DRO_CNT_STATUS,0: dro counter is stopped; 1: dro counter is in process" "0: dro counter is stopped,1: dro counter is in process"
newline
bitfld.long 0x0 1. "DRO_CLK_GATE_EN,DRO Clock Gate Enable" "0,1"
bitfld.long 0x0 0. "DRO_EN,DRO Counter Enable" "0,1"
rgroup.long 0x48C++0x7
line.long 0x0 "DRO_1_2_CNT,DRO1 and DRO2 Counter Read back"
hexmask.long.word 0x0 16.--31. 1. "DRO1_CNT,DRO1 Count"
hexmask.long.word 0x0 0.--15. 1. "DRO2_CNT,DRO2 Count"
line.long 0x4 "DRO_3_CNT,DRO3 Counter Read back"
hexmask.long.word 0x4 0.--15. 1. "DRO3_CNT,DRO3 Count"
group.long 0x498++0x7
line.long 0x0 "DRO_PAR_SEL,DRO Parallel Counter Selection"
bitfld.long 0x0 4.--5. "DRO3_PAR_SEL,DRO3 counter selection" "0,1,2,3"
bitfld.long 0x0 2.--3. "DRO2_PAR_SEL,DRO2 counter selection" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "DRO1_PAR_SEL,DRO1 counter selection" "0,1,2,3"
line.long 0x4 "CLK_SOCCLK_CTRL,SOC Clock Control"
hexmask.long.byte 0x4 4.--7. 1. "SOC_TOP_AHB2APB_WAIT_CYCLES,SOC_TOP AHB2APB Wait Cycles between each APB transaction"
hexmask.long.byte 0x4 0.--3. 1. "SOC_TOP_AHB2APB_PCLK_DIV_SEL,SOC_TOP AHB2APB PCLK Divider Select"
group.long 0x500++0x7
line.long 0x0 "PAD_SLP_PU_PD_DIS0,Pad Sleep Pullup and Pulldown Disable1"
bitfld.long 0x0 31. "GPIO31_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[31] During Sleep Mode" "0,1"
bitfld.long 0x0 30. "GPIO30_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[30] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 29. "GPIO29_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[29] During Sleep Mode" "0,1"
bitfld.long 0x0 28. "GPIO28_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[28] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 21. "GPIO21_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[21] During Sleep Mode" "0,1"
bitfld.long 0x0 20. "GPIO20_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[20] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 19. "GPIO19_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[19] During Sleep Mode" "0,1"
bitfld.long 0x0 18. "GPIO18_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[18] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 17. "GPIO17_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[17] During Sleep Mode" "0,1"
bitfld.long 0x0 16. "GPIO16_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[16] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 15. "GPIO15_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[15] During Sleep Mode" "0,1"
bitfld.long 0x0 14. "GPIO14_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[14] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 13. "GPIO13_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[13] During Sleep Mode" "0,1"
bitfld.long 0x0 12. "GPIO12_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[12] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 11. "GPIO11_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[11] During Sleep Mode" "0,1"
bitfld.long 0x0 10. "GPIO10_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[10] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 9. "GPIO9_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[9] During Sleep Mode" "0,1"
bitfld.long 0x0 8. "GPIO8_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[8] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 7. "GPIO7_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[7] During Sleep Mode" "0,1"
bitfld.long 0x0 6. "GPIO6_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[6] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 5. "GPIO5_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[5] During Sleep Mode" "0,1"
bitfld.long 0x0 4. "GPIO4_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[4] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 3. "GPIO3_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[3] During Sleep Mode" "0,1"
bitfld.long 0x0 2. "GPIO2_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[2] During Sleep Mode" "0,1"
newline
bitfld.long 0x0 1. "GPIO1_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[1] During Sleep Mode" "0,1"
bitfld.long 0x0 0. "GPIO0_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[0] During Sleep Mode" "0,1"
line.long 0x4 "PAD_SLP_PU_PD_DIS1,Pad Sleep Pullup and Pulldown Disable2"
bitfld.long 0x4 31. "GPIO63_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[63] During Sleep Mode" "0,1"
bitfld.long 0x4 30. "GPIO62_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[62] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 29. "GPIO61_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[61] During Sleep Mode" "0,1"
bitfld.long 0x4 28. "GPIO60_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[60] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 27. "GPIO59_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[59] During Sleep Mode" "0,1"
bitfld.long 0x4 26. "GPIO58_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[58] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 25. "GPIO57_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[57] During Sleep Mode" "0,1"
bitfld.long 0x4 24. "GPIO56_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[56] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 23. "GPIO55_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[55] During Sleep Mode" "0,1"
bitfld.long 0x4 22. "GPIO54_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[54] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 21. "GPIO53_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[53] During Sleep Mode" "0,1"
bitfld.long 0x4 20. "GPIO52_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[52] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 19. "GPIO51_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[51] During Sleep Mode" "0,1"
bitfld.long 0x4 18. "GPIO50_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[50] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 17. "GPIO49_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[49] During Sleep Mode" "0,1"
bitfld.long 0x4 16. "GPIO48_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[48] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 15. "GPIO47_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[47] During Sleep Mode" "0,1"
bitfld.long 0x4 14. "GPIO46_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[46] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 13. "GPIO45_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[45] During Sleep Mode" "0,1"
bitfld.long 0x4 12. "GPIO44_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[44] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 11. "GPIO43_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[43] During Sleep Mode" "0,1"
bitfld.long 0x4 10. "GPIO42_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[42] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 9. "GPIO41_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[41] During Sleep Mode" "0,1"
bitfld.long 0x4 8. "GPIO40_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[40] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 7. "GPIO39_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[39] During Sleep Mode" "0,1"
bitfld.long 0x4 6. "GPIO38_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[38] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 5. "GPIO37_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[37] During Sleep Mode" "0,1"
bitfld.long 0x4 4. "GPIO36_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[36] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 3. "GPIO35_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[35] During Sleep Mode" "0,1"
bitfld.long 0x4 2. "GPIO34_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[34] During Sleep Mode" "0,1"
newline
bitfld.long 0x4 1. "GPIO33_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[33] During Sleep Mode" "0,1"
bitfld.long 0x4 0. "GPIO32_PU_PD_DIS,Internal Pd and Internal Pu Disable for GPIO[32] During Sleep Mode" "0,1"
group.long 0x510++0x7
line.long 0x0 "PAD_SLP_PU_PD_DIS2,Pad Sleep Pullup and Pulldown Disable4"
bitfld.long 0x0 3. "ATEST3_PU_PD_DIS,Internal Pd and Internal Pu Disable for ATEST3 During Sleep Mode" "0,1"
bitfld.long 0x0 2. "ATEST2_PU_PD_DIS,Internal Pd and Internal Pu Disable for ATEST2 During Sleep Mode" "0,1"
newline
bitfld.long 0x0 1. "ATEST1_PU_PD_DIS,Internal Pd and Internal Pu Disable for ATEST1 During Sleep Mode" "0,1"
bitfld.long 0x0 0. "ATEST0_PU_PD_DIS,Internal Pd and Internal Pu Disable for ATEST0 During Sleep Mode" "0,1"
line.long 0x4 "PAD_GPIO,GPIO Enable"
hexmask.long.word 0x4 0.--15. 1. "ENABLE,GPIO Automatic Forcing for GPIO[15:0]"
group.long 0x538++0x7
line.long 0x0 "MCI_IOMUX_EN0,mci_iomux_enable control for GPIO[31:0]"
hexmask.long.byte 0x0 28.--31. 1. "EN_31_28,Bitwise enable control for mci_io_mux GPIO[31:28]"
hexmask.long.tbyte 0x0 0.--21. 1. "EN_21_0,Bitwise enable control for mci_io_mux GPIO[21:0]"
line.long 0x4 "MCI_IOMUX_EN1,mci_iomux_enable control for GPIO[63:32]"
hexmask.long 0x4 0.--31. 1. "EN,Bitwise enable control for mci_io_mux GPIO[63:32]"
group.long 0x880++0x3
line.long 0x0 "CAU_EXTRA_PORT,CAU Extra Port Connections"
hexmask.long.byte 0x0 0.--3. 1. "SOC_CAU_EXTRA,SOC_CAU_EXTRA0[3:0]"
group.long 0x888++0x3
line.long 0x0 "CAU_CTRL,CAU Control"
rbitfld.long 0x0 21. "REF_CLK_RDY,CAU Ref clock Ready Status" "0,1"
rbitfld.long 0x0 20. "BUCK_VOUT_RDY,Buck power Status" "0,1"
newline
rbitfld.long 0x0 19. "CAU_BG_RDY,CAU bandgap Status" "0,1"
bitfld.long 0x0 11. "CAU_REFCLK_SEL,CAU Reference Clock Select" "0,1"
rgroup.long 0x8A4++0x3
line.long 0x0 "SYSPLL_CTRL,SYSPLL Control"
bitfld.long 0x0 10. "T3_PLL_LOCK,PLL T3 Lock Status" "0,1"
group.long 0x8FC++0x3
line.long 0x0 "CAU_ECO_CTRL,CAU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
tree.end
tree "SOCTOP_ARB"
base ad:0x45000000
group.long 0x0++0xB
line.long 0x0 "ARB2_PL1,Arbitration priority for master 1"
hexmask.long.byte 0x0 0.--3. 1. "PRI,'"
line.long 0x4 "ARB2_PL2,Arbitration priority for master 2"
hexmask.long.byte 0x4 0.--3. 1. "PRI,'"
line.long 0x8 "ARB2_PL3,Arbitration priority for master 3"
hexmask.long.byte 0x8 0.--3. 1. "PRI,'"
group.long 0x3C++0x7
line.long 0x0 "ARB2_EBTCOUNT,Early burst termination count"
hexmask.long.word 0x0 0.--9. 1. "COUNT,'"
line.long 0x4 "ARB2_EBT_EN,Early burst termination enable"
bitfld.long 0x4 0. "ENABLE,'" "0,1"
rgroup.long 0x44++0x7
line.long 0x0 "ARB2_EBT,Early burst termination"
bitfld.long 0x0 0. "EBT,'" "0,1"
line.long 0x4 "ARB2_DFT_MST,Default Master ID Number"
hexmask.long.byte 0x4 0.--3. 1. "ID,Read only if HC_DFLT_MSTR = 1 or AHB_HAS_ARBIF= 0"
group.long 0x4C++0x43
line.long 0x0 "ARB2_WTEN,Weighted-token arbitration scheme Enable"
bitfld.long 0x0 0. "WTEN,'" "0,1"
line.long 0x4 "ARB2_AHB_TCL,Master clock refresh period"
hexmask.long 0x4 0.--31. 1. "PERIOD,'"
line.long 0x8 "ARB2_AHB_CL_M1,Master clock token 1"
hexmask.long 0x8 0.--31. 1. "NUM_TOKENS,'"
line.long 0xC "ARB2_AHB_CL_M2,Master clock token 2"
hexmask.long 0xC 0.--31. 1. "NUM_TOKENS,'"
line.long 0x10 "ARB2_AHB_CL_M3,Master clock token 3"
hexmask.long 0x10 0.--31. 1. "NUM_TOKENS,'"
line.long 0x14 "ARB2_AHB_CL_M4,Master clock token 4"
hexmask.long 0x14 0.--31. 1. "NUM_TOKENS,'"
line.long 0x18 "ARB2_AHB_CL_M5,Master clock token 5"
hexmask.long 0x18 0.--31. 1. "NUM_TOKENS,'"
line.long 0x1C "ARB2_AHB_CL_M6,Master clock token 6"
hexmask.long 0x1C 0.--31. 1. "NUM_TOKENS,'"
line.long 0x20 "ARB2_AHB_CL_M7,Master clock token 7"
hexmask.long 0x20 0.--31. 1. "NUM_TOKENS,'"
line.long 0x24 "ARB2_AHB_CL_M8,Master clock token 8"
hexmask.long 0x24 0.--31. 1. "NUM_TOKENS,'"
line.long 0x28 "ARB2_AHB_CL_M9,Master clock token 9"
hexmask.long 0x28 0.--31. 1. "NUM_TOKENS,'"
line.long 0x2C "ARB2_AHB_CL_M10,Master clock token 10"
hexmask.long 0x2C 0.--31. 1. "NUM_TOKENS,'"
line.long 0x30 "ARB2_AHB_CL_M11,Master clock token 11"
hexmask.long 0x30 0.--31. 1. "NUM_TOKENS,'"
line.long 0x34 "ARB2_AHB_CL_M12,Master clock token 12"
hexmask.long 0x34 0.--31. 1. "NUM_TOKENS,'"
line.long 0x38 "ARB2_AHB_CL_M13,Master clock token 13"
hexmask.long 0x38 0.--31. 1. "NUM_TOKENS,'"
line.long 0x3C "ARB2_AHB_CL_M14,Master clock token 14"
hexmask.long 0x3C 0.--31. 1. "NUM_TOKENS,'"
line.long 0x40 "ARB2_AHB_CL_M15,Master clock token 15"
hexmask.long 0x40 0.--31. 1. "NUM_TOKENS,'"
tree.end
tree "SOCTOP_TSTMUX"
base ad:0x45003800
group.long 0x0++0x27
line.long 0x0 "CONFIG1_REG0,config1 reg for first block-1 of testmux"
hexmask.long.byte 0x0 24.--28. 1. "BIT_3_SEL,Same as Bit 0"
hexmask.long.byte 0x0 16.--20. 1. "BIT_2_SEL,Same as Bit 0"
hexmask.long.byte 0x0 8.--12. 1. "BIT_1_SEL,Same as Bit 0"
hexmask.long.byte 0x0 0.--4. 1. "BIT_0_SEL,Config1 reg0 bit0 select"
line.long 0x4 "CONFIG1_REG1,config1 reg for first block-1 of testmux"
hexmask.long.byte 0x4 24.--28. 1. "BIT_7_SEL,Same as Bit 0"
hexmask.long.byte 0x4 16.--20. 1. "BIT_6_SEL,Same as Bit 0"
hexmask.long.byte 0x4 8.--12. 1. "BIT_5_SEL,Same as Bit 0"
hexmask.long.byte 0x4 0.--4. 1. "BIT_4_SEL,Same as Bit 0"
line.long 0x8 "CONFIG1_REG2,config2 reg for block-2 of testmux"
hexmask.long.byte 0x8 24.--28. 1. "BIT_11_SEL,Same as Bit 0"
hexmask.long.byte 0x8 16.--20. 1. "BIT_10_SEL,Same as Bit 0"
hexmask.long.byte 0x8 8.--12. 1. "BIT_9_SEL,Same as Bit 0"
hexmask.long.byte 0x8 0.--4. 1. "BIT_8_SEL,Same as Bit 0"
line.long 0xC "CONFIG1_REG3,config2 reg for block-2 of testmux"
hexmask.long.byte 0xC 24.--28. 1. "BIT_15_SEL,Same as Bit 0"
hexmask.long.byte 0xC 16.--20. 1. "BIT_14_SEL,Same as Bit 0"
hexmask.long.byte 0xC 8.--12. 1. "BIT_13_SEL,Same as Bit 0"
hexmask.long.byte 0xC 0.--4. 1. "BIT_12_SEL,Same as Bit 0"
line.long 0x10 "CONFIG2_REG0,config1 reg for first block-1 of testmux"
hexmask.long.byte 0x10 24.--28. 1. "BIT_3_SEL,Same as Bit 0"
hexmask.long.byte 0x10 16.--20. 1. "BIT_2_SEL,Same as Bit 0"
hexmask.long.byte 0x10 8.--12. 1. "BIT_1_SEL,Same as Bit 0"
hexmask.long.byte 0x10 0.--4. 1. "BIT_0_SEL,Same as Bit 0"
line.long 0x14 "CONFIG2_REG1,config1 reg for first block-1 of testmux"
hexmask.long.byte 0x14 24.--28. 1. "BIT_7_SEL,Same as Bit 0"
hexmask.long.byte 0x14 16.--20. 1. "BIT_6_SEL,Same as Bit 0"
hexmask.long.byte 0x14 8.--12. 1. "BIT_5_SEL,Same as Bit 0"
hexmask.long.byte 0x14 0.--4. 1. "BIT_4_SEL,Same as Bit 0"
line.long 0x18 "CONFIG2_REG2,config2 reg for block-2 of testmux"
hexmask.long.byte 0x18 24.--28. 1. "BIT_11_SEL,Same as Bit 0"
hexmask.long.byte 0x18 16.--20. 1. "BIT_10_SEL,Same as Bit 0"
hexmask.long.byte 0x18 8.--12. 1. "BIT_9_SEL,Same as Bit 0"
hexmask.long.byte 0x18 0.--4. 1. "BIT_8_SEL,Same as Bit 0"
line.long 0x1C "CONFIG2_REG3,config2 reg for block-2 of testmux"
hexmask.long.byte 0x1C 24.--28. 1. "BIT_15_SEL,Same as Bit 0"
hexmask.long.byte 0x1C 16.--20. 1. "BIT_14_SEL,Same as Bit 0"
hexmask.long.byte 0x1C 8.--12. 1. "BIT_13_SEL,Same as Bit 0"
hexmask.long.byte 0x1C 0.--4. 1. "BIT_12_SEL,Same as Bit 0"
line.long 0x20 "TESTMUX_CONFIG_REG,config reg for testmux"
hexmask.long.byte 0x20 27.--31. 1. "ROTATE_SEL,rotation config : 1 bit roation"
bitfld.long 0x20 1.--2. "REMAP_SEL,Remaping scheme -" "0,1,2,3"
bitfld.long 0x20 0. "BITWISE_SEL_EN,Bitwise select enable" "0,1"
line.long 0x24 "CONFIG_TEST_MODE,testmode enable disable control"
hexmask.long 0x24 0.--31. 1. "EN,Config testmode enable"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI0"
base ad:0x40106000
group.long 0x400++0xF
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity Select" "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
newline
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity Select" "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity Select" "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
newline
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity Select" "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CPOL,Clock Polarity Select" "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase Select" "0: Change,1: Capture"
newline
bitfld.long 0x0 3. "LSBF,LSB First Mode Enable" "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master Mode Select" "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
newline
bitfld.long 0x0 0. "ENABLE,SPI Enable" "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,Delay Register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Transfer Delay"
newline
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,Frame Delay"
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Post-Delay"
newline
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Pre-Delay"
line.long 0x8 "STAT,Status Register"
rbitfld.long 0x8 8. "MSTIDLE,Master Idle Status Flag" "0,1"
newline
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer Control" "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled Status Flag" "0,1"
newline
bitfld.long 0x8 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert" "0,1"
line.long 0xC "INTENSET,Interrupt Enable Register"
bitfld.long 0xC 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
newline
bitfld.long 0xC 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Interrupt Enable" "0: No effect,1: Clear the Master Idle Interrupt Enable bit.."
newline
bitfld.long 0x0 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: No effect,1: Clear the Slave Select Deassert Interrupt Enable.."
newline
bitfld.long 0x0 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: No effect,1: Clear the Slave Select Assert Interrupt Enable.."
group.long 0x424++0x3
line.long 0x0 "DIV,Clock Divider Register"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate Divider Value"
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "SSD,Slave Select Deassert Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert Interrupt" "0: Disabled,1: Enabled"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration Register"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Issues a DMA request for the receive function if.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function if.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: FIFO is configured as 8 entries of 16 bits.,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
line.long 0x4 "FIFOSTAT,FIFO Status Register"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full. To prevent the.."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data can.."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.."
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Register"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the Receive FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the Transmit FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the Receive Error Interrupt Enable bit.."
newline
bitfld.long 0x4 0. "TXERR,TX Error Interrupt Enable" "0: No effect,1: Clear the TX Error Interrupt Enable bit.."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data Register"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length"
newline
bitfld.long 0x0 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore" "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
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bitfld.long 0x0 21. "EOF,End of Frame" "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
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bitfld.long 0x0 20. "EOT,End of Transfer" "0: SSEL is not deasserted. This piece of data is..,1: SSEL is deasserted. This piece of data is.."
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bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted"
newline
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted"
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted"
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bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted"
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went from.."
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bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Not selected,1: Selected"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "SPI1"
base ad:0x40107000
group.long 0x400++0xF
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity Select" "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
newline
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity Select" "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity Select" "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
newline
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity Select" "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CPOL,Clock Polarity Select" "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase Select" "0: Change,1: Capture"
newline
bitfld.long 0x0 3. "LSBF,LSB First Mode Enable" "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master Mode Select" "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
newline
bitfld.long 0x0 0. "ENABLE,SPI Enable" "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,Delay Register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Transfer Delay"
newline
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,Frame Delay"
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Post-Delay"
newline
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Pre-Delay"
line.long 0x8 "STAT,Status Register"
rbitfld.long 0x8 8. "MSTIDLE,Master Idle Status Flag" "0,1"
newline
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer Control" "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled Status Flag" "0,1"
newline
bitfld.long 0x8 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert" "0,1"
line.long 0xC "INTENSET,Interrupt Enable Register"
bitfld.long 0xC 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
newline
bitfld.long 0xC 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Interrupt Enable" "0: No effect,1: Clear the Master Idle Interrupt Enable bit.."
newline
bitfld.long 0x0 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: No effect,1: Clear the Slave Select Deassert Interrupt Enable.."
newline
bitfld.long 0x0 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: No effect,1: Clear the Slave Select Assert Interrupt Enable.."
group.long 0x424++0x3
line.long 0x0 "DIV,Clock Divider Register"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate Divider Value"
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "SSD,Slave Select Deassert Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert Interrupt" "0: Disabled,1: Enabled"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration Register"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Issues a DMA request for the receive function if.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function if.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: FIFO is configured as 8 entries of 16 bits.,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
line.long 0x4 "FIFOSTAT,FIFO Status Register"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full. To prevent the.."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data can.."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.."
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Register"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the Receive FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the Transmit FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the Receive Error Interrupt Enable bit.."
newline
bitfld.long 0x4 0. "TXERR,TX Error Interrupt Enable" "0: No effect,1: Clear the TX Error Interrupt Enable bit.."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data Register"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length"
newline
bitfld.long 0x0 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore" "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of Frame" "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
newline
bitfld.long 0x0 20. "EOT,End of Transfer" "0: SSEL is not deasserted. This piece of data is..,1: SSEL is deasserted. This piece of data is.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted"
newline
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted"
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted"
newline
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted"
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went from.."
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Not selected,1: Selected"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "SPI2"
base ad:0x40108000
group.long 0x400++0xF
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity Select" "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
newline
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity Select" "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity Select" "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
newline
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity Select" "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CPOL,Clock Polarity Select" "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase Select" "0: Change,1: Capture"
newline
bitfld.long 0x0 3. "LSBF,LSB First Mode Enable" "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master Mode Select" "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
newline
bitfld.long 0x0 0. "ENABLE,SPI Enable" "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,Delay Register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Transfer Delay"
newline
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,Frame Delay"
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Post-Delay"
newline
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Pre-Delay"
line.long 0x8 "STAT,Status Register"
rbitfld.long 0x8 8. "MSTIDLE,Master Idle Status Flag" "0,1"
newline
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer Control" "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled Status Flag" "0,1"
newline
bitfld.long 0x8 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert" "0,1"
line.long 0xC "INTENSET,Interrupt Enable Register"
bitfld.long 0xC 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
newline
bitfld.long 0xC 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Interrupt Enable" "0: No effect,1: Clear the Master Idle Interrupt Enable bit.."
newline
bitfld.long 0x0 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: No effect,1: Clear the Slave Select Deassert Interrupt Enable.."
newline
bitfld.long 0x0 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: No effect,1: Clear the Slave Select Assert Interrupt Enable.."
group.long 0x424++0x3
line.long 0x0 "DIV,Clock Divider Register"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate Divider Value"
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "SSD,Slave Select Deassert Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert Interrupt" "0: Disabled,1: Enabled"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration Register"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Issues a DMA request for the receive function if.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function if.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: FIFO is configured as 8 entries of 16 bits.,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
line.long 0x4 "FIFOSTAT,FIFO Status Register"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full. To prevent the.."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data can.."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.."
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Register"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the Receive FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the Transmit FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the Receive Error Interrupt Enable bit.."
newline
bitfld.long 0x4 0. "TXERR,TX Error Interrupt Enable" "0: No effect,1: Clear the TX Error Interrupt Enable bit.."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data Register"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length"
newline
bitfld.long 0x0 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore" "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of Frame" "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
newline
bitfld.long 0x0 20. "EOT,End of Transfer" "0: SSEL is not deasserted. This piece of data is..,1: SSEL is deasserted. This piece of data is.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted"
newline
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted"
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted"
newline
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted"
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went from.."
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Not selected,1: Selected"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "SPI3"
base ad:0x40109000
group.long 0x400++0xF
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity Select" "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
newline
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity Select" "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity Select" "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
newline
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity Select" "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CPOL,Clock Polarity Select" "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase Select" "0: Change,1: Capture"
newline
bitfld.long 0x0 3. "LSBF,LSB First Mode Enable" "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master Mode Select" "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
newline
bitfld.long 0x0 0. "ENABLE,SPI Enable" "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,Delay Register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Transfer Delay"
newline
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,Frame Delay"
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Post-Delay"
newline
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Pre-Delay"
line.long 0x8 "STAT,Status Register"
rbitfld.long 0x8 8. "MSTIDLE,Master Idle Status Flag" "0,1"
newline
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer Control" "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled Status Flag" "0,1"
newline
bitfld.long 0x8 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert" "0,1"
line.long 0xC "INTENSET,Interrupt Enable Register"
bitfld.long 0xC 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
newline
bitfld.long 0xC 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Interrupt Enable" "0: No effect,1: Clear the Master Idle Interrupt Enable bit.."
newline
bitfld.long 0x0 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: No effect,1: Clear the Slave Select Deassert Interrupt Enable.."
newline
bitfld.long 0x0 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: No effect,1: Clear the Slave Select Assert Interrupt Enable.."
group.long 0x424++0x3
line.long 0x0 "DIV,Clock Divider Register"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate Divider Value"
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "SSD,Slave Select Deassert Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert Interrupt" "0: Disabled,1: Enabled"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration Register"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Issues a DMA request for the receive function if.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function if.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: FIFO is configured as 8 entries of 16 bits.,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
line.long 0x4 "FIFOSTAT,FIFO Status Register"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full. To prevent the.."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data can.."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.."
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Register"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the Receive FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the Transmit FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the Receive Error Interrupt Enable bit.."
newline
bitfld.long 0x4 0. "TXERR,TX Error Interrupt Enable" "0: No effect,1: Clear the TX Error Interrupt Enable bit.."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data Register"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length"
newline
bitfld.long 0x0 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore" "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of Frame" "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
newline
bitfld.long 0x0 20. "EOT,End of Transfer" "0: SSEL is not deasserted. This piece of data is..,1: SSEL is deasserted. This piece of data is.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted"
newline
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted"
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted"
newline
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted"
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went from.."
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Not selected,1: Selected"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "SPI14"
base ad:0x40126000
group.long 0x400++0xF
line.long 0x0 "CFG,Configuration Register"
bitfld.long 0x0 11. "SPOL3,SSEL3 Polarity Select" "0: Low. The SSEL3 pin is active low.,1: High. The SSEL3 pin is active high."
newline
bitfld.long 0x0 10. "SPOL2,SSEL2 Polarity Select" "0: Low. The SSEL2 pin is active low.,1: High. The SSEL2 pin is active high."
newline
bitfld.long 0x0 9. "SPOL1,SSEL1 Polarity Select" "0: Low. The SSEL1 pin is active low.,1: High. The SSEL1 pin is active high."
newline
bitfld.long 0x0 8. "SPOL0,SSEL0 Polarity Select" "0: Low. The SSEL0 pin is active low.,1: High. The SSEL0 pin is active high."
newline
bitfld.long 0x0 7. "LOOP,Loopback Mode Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CPOL,Clock Polarity Select" "0: Low. The rest state of the clock (between..,1: High. The rest state of the clock (between.."
newline
bitfld.long 0x0 4. "CPHA,Clock Phase Select" "0: Change,1: Capture"
newline
bitfld.long 0x0 3. "LSBF,LSB First Mode Enable" "0: Standard. Data is transmitted and received in..,1: Reverse. Data is transmitted and received in.."
newline
bitfld.long 0x0 2. "MASTER,Master Mode Select" "0: Slave mode. The SPI will operate in slave mode.,1: Master mode. The SPI will operate in master.."
newline
bitfld.long 0x0 0. "ENABLE,SPI Enable" "0: Disabled. The SPI is disabled and the internal..,1: Enabled. The SPI is enabled for operation."
line.long 0x4 "DLY,Delay Register"
hexmask.long.byte 0x4 12.--15. 1. "TRANSFER_DELAY,Transfer Delay"
newline
hexmask.long.byte 0x4 8.--11. 1. "FRAME_DELAY,Frame Delay"
newline
hexmask.long.byte 0x4 4.--7. 1. "POST_DELAY,Post-Delay"
newline
hexmask.long.byte 0x4 0.--3. 1. "PRE_DELAY,Pre-Delay"
line.long 0x8 "STAT,Status Register"
rbitfld.long 0x8 8. "MSTIDLE,Master Idle Status Flag" "0,1"
newline
bitfld.long 0x8 7. "ENDTRANSFER,End Transfer Control" "0,1"
newline
rbitfld.long 0x8 6. "STALLED,Stalled Status Flag" "0,1"
newline
bitfld.long 0x8 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x8 4. "SSA,Slave Select Assert" "0,1"
line.long 0xC "INTENSET,Interrupt Enable Register"
bitfld.long 0xC 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
newline
bitfld.long 0xC 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when all.."
newline
bitfld.long 0xC 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled. No interrupt will be generated when..,1: Enabled. An interrupt will be generated when any.."
wgroup.long 0x410++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Interrupt Enable" "0: No effect,1: Clear the Master Idle Interrupt Enable bit.."
newline
bitfld.long 0x0 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: No effect,1: Clear the Slave Select Deassert Interrupt Enable.."
newline
bitfld.long 0x0 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: No effect,1: Clear the Slave Select Assert Interrupt Enable.."
group.long 0x424++0x3
line.long 0x0 "DIV,Clock Divider Register"
hexmask.long.word 0x0 0.--15. 1. "DIVVAL,Rate Divider Value"
rgroup.long 0x428++0x3
line.long 0x0 "INTSTAT,Interrupt Status Register"
bitfld.long 0x0 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "SSD,Slave Select Deassert Interrupt" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 4. "SSA,Slave Select Assert Interrupt" "0: Disabled,1: Enabled"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration Register"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop"
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied"
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied"
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Issues a DMA request for the receive function if.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function if.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: FIFO is configured as 8 entries of 16 bits.,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
line.long 0x4 "FIFOSTAT,FIFO Status Register"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full. To prevent the.."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data can.."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.."
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Register"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive error,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the Receive FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the Transmit FIFO Level Interrupt Enable.."
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the Receive Error Interrupt Enable bit.."
newline
bitfld.long 0x4 0. "TXERR,TX Error Interrupt Enable" "0: No effect,1: Clear the TX Error Interrupt Enable bit.."
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status Register"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data Register"
hexmask.long.byte 0x0 24.--27. 1. "LEN,Data Length"
newline
bitfld.long 0x0 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x0 22. "RXIGNORE,Receive Ignore" "0: Read received data. Received data must be read..,1: Ignore received data. Received data is ignored.."
newline
bitfld.long 0x0 21. "EOF,End of Frame" "0: Data not EOF. This piece of data transmitted is..,1: Data EOF. This piece of data is treated as the.."
newline
bitfld.long 0x0 20. "EOT,End of Transfer" "0: SSEL is not deasserted. This piece of data is..,1: SSEL is deasserted. This piece of data is.."
newline
bitfld.long 0x0 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted"
newline
bitfld.long 0x0 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted"
newline
bitfld.long 0x0 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted"
newline
bitfld.long 0x0 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted"
newline
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went from.."
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register"
bitfld.long 0x0 20. "SOT,Start of Transfer Flag" "0: Not active,1: Active"
newline
bitfld.long 0x0 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Not selected,1: Selected"
newline
bitfld.long 0x0 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Not selected,1: Selected"
newline
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size Register"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification Register"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree.end
tree "SYSCON (System Controller)"
base ad:0x4003B000
wgroup.long 0x0++0xF
line.long 0x0 "HARDENRING_FSM0_CTRL,Hardenring FSM0 Ctrl"
hexmask.long.byte 0x0 0.--5. 1. "HARDENRING_FSM0_CTRL,Hardenring FSM0 Ctrl - CM33-DBGEN(Default Disable)"
line.long 0x4 "HARDENRING_FSM1_CTRL,Hardenring FSM1 Ctrl"
hexmask.long.byte 0x4 0.--5. 1. "HARDENRING_FSM1_CTRL,Hardenring FSM1 Ctrl - CM33-SPIDEN(Default Disable)"
line.long 0x8 "HARDENRING_FSM2_CTRL,Hardenring FSM2 Ctrl"
hexmask.long.byte 0x8 0.--5. 1. "HARDENRING_FSM2_CTRL,Hardenring FSM2 Ctrl - CM33-NIDEN(Default Disable)"
line.long 0xC "HARDENRING_FSM3_CTRL,Hardenring FSM3 Ctrl"
hexmask.long.byte 0xC 0.--5. 1. "HARDENRING_FSM3_CTRL,Hardenring FSM3 Ctrl - CM33-SPNIDEN(Default Disable)"
wgroup.long 0x28++0xF
line.long 0x0 "HARDENRING_FSM10_CTRL,Hardenring FSM10 Ctrl"
hexmask.long.byte 0x0 0.--5. 1. "HARDENRING_FSM10_CTRL,Hardenring FSM10 Ctrl - CSS-CTRL-0 (Default Write Disable to Register Group)"
line.long 0x4 "HARDENRING_FSM11_CTRL,Hardenring FSM11 Ctrl"
hexmask.long.byte 0x4 0.--5. 1. "HARDENRING_FSM11_CTRL,Hardenring FSM11 Ctrl - CSS-CTRL-1(Default Write Disable to Register Group)"
line.long 0x8 "HARDENRING_FSM12_CTRL,Hardenring FSM12 Ctrl"
hexmask.long.byte 0x8 0.--5. 1. "HARDENRING_FSM12_CTRL,Hardenring FSM12 Ctrl - SCRATCH-Register (Default Write Disable to Register Group)"
line.long 0xC "HARDENRING_FSM13_CTRL,Hardenring FSM13 Ctrl"
hexmask.long.byte 0xC 0.--5. 1. "HARDENRING_FSM13_CTRL,Hardenring FSM13 Ctrl - CSS-PUF-CTRL-2 (Default Write Disable to Register Group)"
group.long 0x200++0x17
line.long 0x0 "I_CUSTOM_31_0,CSS sideband ctrl - i_custom[31:0]"
hexmask.long.word 0x0 16.--31. 1. "I_CUSTOM_31_16,CSS sideband ctrl - i_custom[31:16]. Real read data will be returned only when FSM10 Ctrl is ENABLE."
hexmask.long.word 0x0 0.--15. 1. "I_CUSTOM_15_0,CSS sideband ctrl - i_custom[15:0] temporal_boot_state. Real read data will be returned only when FSM10 Ctrl is ENABLE."
line.long 0x4 "I_CUSTOM_63_32,CSS sideband ctrl - i_custom[63:32]"
hexmask.long 0x4 0.--31. 1. "I_CUSTOM_63_32,CSS sideband ctrl - i_custom[63:32]. Real read data will be returned only when FSM10 Ctrl is ENABLE."
line.long 0x8 "I_CUSTOM_95_64,CSS sideband ctrl - i_custom[95:64]"
hexmask.long 0x8 0.--31. 1. "I_CUSTOM_95_64,CSS sideband ctrl - i_custom[95:64]. Real read data will be returned only when FSM10 Ctrl is ENABLE."
line.long 0xC "I_CUSTOM_127_96,CSS sideband ctrl - i_custom[127:96]"
hexmask.long 0xC 0.--31. 1. "I_CUSTOM_127_96,CSS sideband ctrl - i_custom[127:96]. Real read data will be returned only when FSM10 Ctrl is ENABLE."
line.long 0x10 "I_HW_DRV_DATA_31_0,CSS sideband ctrl - i_hw_drv_data[31:0]"
hexmask.long.word 0x10 16.--31. 1. "I_HW_DRV_DATA_31_16,CSS sideband ctrl - i_hw_drv_data[31:16]. Real read data will be returned only when FSM10 Ctrl is ENABLE."
hexmask.long.word 0x10 0.--15. 1. "I_HW_DRV_DATA_15_0,CSS sideband ctrl - i_hw_drv_data[15:0] temporal_boot_state. Real read data will be returned only when FSM10 Ctrl is ENABLE."
line.long 0x14 "I_HW_DRV_DATA_63_32,CSS sideband ctrl - i_hw_drv_data[63:32]"
hexmask.long 0x14 0.--31. 1. "I_HW_DRV_DATA_63_32,CSS sideband ctrl - i_hw_drv_data[63:32]. Real read data will be returned only when FSM10 Ctrl is ENABLE."
group.long 0x280++0x3
line.long 0x0 "I_CSS_FEATURE0_31_0,CSS sideband ctrl - i_css_feature0[31:0]"
hexmask.long 0x0 0.--31. 1. "I_CSS_FEATURE0_31_0,CSS sideband ctrl - i_css_feature0[31:0]. Real read data will be returned only when FSM12 Ctrl is ENABLE."
wgroup.long 0x284++0x3
line.long 0x0 "I_CSS_HW_EEM_EN_31_0,CSS sideband ctrl - i_css_hw_eem_en[31:0]"
hexmask.long 0x0 0.--31. 1. "I_CSS_HW_EEM_EN_31_0,CSS sideband ctrl - i_css_hw_eem_en[31:0] (Default Enable i_css_cmd_ena[31:0])"
group.long 0x288++0xF
line.long 0x0 "PUF_CONFIG,PUF sideband ctrl"
bitfld.long 0x0 16.--17. "I_PUF_FEATURE0_DP,PUF sideband ctrl - i_puf_feature0_dp. Real read data will be returned only when FSM12 Ctrl is ENABLE." "0,1,2,3"
hexmask.long.byte 0x0 8.--11. 1. "O_PUF_DATA_MASK,PUF sideband ctrl - puf_data_mask. Real read data will be returned only when FSM12 Ctrl is ENABLE."
bitfld.long 0x0 0.--1. "I_PUF_FEATURE0,PUF sideband ctrl - i_puf_feature0. Real read data will be returned only when FSM12 Ctrl is ENABLE." "0,1,2,3"
line.long 0x4 "I_CSS_FEATURE0_DP_31_0,CSS sideband ctrl - i_css_feature0_dp[31:0] (Default Enable i_css_cmd_ena[31:0])"
hexmask.long 0x4 0.--31. 1. "I_CSS_FEATURE0_DP_31_0,CSS sideband ctrl - i_css_feature0_dp[31:0]. Real read data will be returned only when FSM12 Ctrl is ENABLE."
line.long 0x8 "I_CSS_FEATURE0_63_32,CSS sideband ctrl - i_css_feature0[63:32]"
hexmask.long 0x8 0.--31. 1. "I_CSS_FEATURE0_63_32,CSS sideband ctrl - i_css_feature0[63:32] (Default Enable i_css_cmd_ena[63:32]). Real read data will be returned only when FSM12 Ctrl is ENABLE."
line.long 0xC "I_CSS_FEATURE0_DP_63_32,CSS sideband ctrl - i_css_feature0_dp[63:32]"
hexmask.long 0xC 0.--31. 1. "I_CSS_FEATURE0_DP_63_32,CSS sideband ctrl - i_css_feature0_dp[63:32] (Default Enable i_css_cmd_ena[63:32]). Real read data will be returned only when FSM12 Ctrl is ENABLE."
group.long 0x400++0x1F
line.long 0x0 "WO_SCRATCH_REG0,Write once scratch register 0"
hexmask.long 0x0 0.--31. 1. "WO_SCRATCH_REG0,Write once scratch register 0"
line.long 0x4 "WO_SCRATCH_REG1,Write once scratch register 1"
hexmask.long 0x4 0.--31. 1. "WO_SCRATCH_REG1,Write once scratch register 1"
line.long 0x8 "WO_SCRATCH_REG2,Write once scratch register 2"
hexmask.long 0x8 0.--31. 1. "WO_SCRATCH_REG2,Write once scratch register 2"
line.long 0xC "WO_SCRATCH_REG3,Write once scratch register 3"
hexmask.long 0xC 0.--31. 1. "WO_SCRATCH_REG3,Write once scratch register 3"
line.long 0x10 "WO_SCRATCH_REG4,Write once scratch register 4"
hexmask.long 0x10 0.--31. 1. "WO_SCRATCH_REG4,Write once scratch register 4"
line.long 0x14 "WO_SCRATCH_REG5,Write once scratch register 5"
hexmask.long 0x14 0.--31. 1. "WO_SCRATCH_REG5,Write once scratch register 5"
line.long 0x18 "WO_SCRATCH_REG6,Write once scratch register 6"
hexmask.long 0x18 0.--31. 1. "WO_SCRATCH_REG6,Write once scratch register 6"
line.long 0x1C "WO_SCRATCH_REG7,Write once scratch register 7"
hexmask.long 0x1C 0.--31. 1. "WO_SCRATCH_REG7,Write once scratch register 7"
group.long 0x480++0x1F
line.long 0x0 "RW_SCRATCH_REG0,Scratch register 0"
hexmask.long 0x0 0.--31. 1. "RW_SCRATCH_REG0,Scratch register 0"
line.long 0x4 "RW_SCRATCH_REG1,Scratch register 1"
hexmask.long 0x4 0.--31. 1. "RW_SCRATCH_REG1,Scratch register 1"
line.long 0x8 "RW_SCRATCH_REG2,Scratch register 2"
hexmask.long 0x8 0.--31. 1. "RW_SCRATCH_REG2,Scratch register 2"
line.long 0xC "RW_SCRATCH_REG3,Scratch register 3"
hexmask.long 0xC 0.--31. 1. "RW_SCRATCH_REG3,Scratch register 3"
line.long 0x10 "RW_SCRATCH_REG4,Scratch register 4"
hexmask.long 0x10 0.--31. 1. "RW_SCRATCH_REG4,Scratch register 4"
line.long 0x14 "RW_SCRATCH_REG5,Scratch register 5"
hexmask.long 0x14 0.--31. 1. "RW_SCRATCH_REG5,Scratch register 5"
line.long 0x18 "RW_SCRATCH_REG6,Scratch register 6"
hexmask.long 0x18 0.--31. 1. "RW_SCRATCH_REG6,Scratch register 6"
line.long 0x1C "RW_SCRATCH_REG7,Scratch register 7"
hexmask.long 0x1C 0.--31. 1. "RW_SCRATCH_REG7,Scratch register 7"
group.long 0x4C0++0x3
line.long 0x0 "PKC_RAM_SUBSYSTEM_CTRL,PKC ram subsystem ctrl"
hexmask.long.byte 0x0 2.--5. 1. "ENABLE_RAM0_PARITY_ERROR_CHECK,PKC ram subsystem ctrl - casper_interleave"
bitfld.long 0x0 1. "AUTO_CLK_OVERRIDE_RAM0,PKC ram subsystem ctrl - auto_clk_override_ram0" "0,1"
bitfld.long 0x0 0. "CASPER_INTERLEAVE,PKC ram subsystem ctrl - casper_interleave" "0,1"
rgroup.long 0x4C4++0x3
line.long 0x0 "CSS_STATUS,CSS status"
bitfld.long 0x0 1. "CSS_GDET_ERR,CSS status - GDET Error" "0,1"
bitfld.long 0x0 0. "CSS_GDET_ENABLED,CSS status - GDET Enable" "0,1"
group.long 0x4C8++0x7
line.long 0x0 "VTOR_CTRL,VTOR CTRL"
bitfld.long 0x0 0. "VTOR_ATE_EN,VTOR ATE Enable. Once 1'b0 is written it will retain 1'b0 till next power-on reset." "0,1"
line.long 0x4 "TESTBUS_CTRL,TESTBUS CTRL"
bitfld.long 0x4 0. "TESTBUS_EN,TestBus Enable. Once 1'b0 is written it will retain 1'b0 till next power-on reset." "0,1"
tree.end
tree "SYSCTL"
base ad:0x0
tree "SYSCTL0"
base ad:0x40002000
group.long 0x10++0x3
line.long 0x0 "AHBMATRIXPRIOR,AHB matrix priority"
bitfld.long 0x0 20.--21. "M10,Master 10 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 18.--19. "M9,Master 9 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 16.--17. "M8,Master 8 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
newline
bitfld.long 0x0 14.--15. "M7,Master 7 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 12.--13. "M6,Master 6 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 10.--11. "M5,Master 5 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
newline
bitfld.long 0x0 8.--9. "M4,Master 4 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 6.--7. "M3,Master 3 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 4.--5. "M2,Master 2 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
newline
bitfld.long 0x0 2.--3. "M1,Master 1 Priority. . . 0: 0 1: 1 2: 2 3: 3." "0: 0,1: 1,2: 2,3: 3"
bitfld.long 0x0 0.--1. "M0,Master 0 Priority. . . 0: 0 1: 1 2: 2 3: 3. (0 High)" "0: 0,1: 1,2: 2,3: 3"
group.long 0x30++0xB
line.long 0x0 "M33NMISRCSEL,M33 nmi source selection"
bitfld.long 0x0 31. "NMIEN,NMI interrupt enable" "0: Disable NMI Interrupt,1: Enable NMI Interrupt."
hexmask.long.byte 0x0 0.--6. 1. "NMISRCSEL,Selects one of the M33 interrupt sources as the NMI source. See M33 Interrupt Slot Table for Interrupt Slot Numers."
line.long 0x4 "SYSTEM_STICK_CALIB,system stick calibration"
hexmask.long 0x4 0.--25. 1. "SYSTEM_STICK_CALIB,Selects the system secure tick calibration value of the M33."
line.long 0x8 "SYSTEM_NSTICK_CALIB,system nstick calibration"
hexmask.long 0x8 0.--25. 1. "SYSTEM_NSTICK_CALIB,Selects the system non-secure tick calibration value of the M33."
rgroup.long 0x410++0x3
line.long 0x0 "USBCLKSTAT,USB clock status"
bitfld.long 0x0 1. "HOST_NEED_CLKST,USB0 Device Host USB0_NEEDCLK signal status:" "0: low,1: high"
bitfld.long 0x0 0. "DEV_NEED_CLKST,USB0 Device USB0_NEEDCLK signal status:" "0: low,1: high"
group.long 0x780++0x3
line.long 0x0 "HWWAKE,Hardware Wake-up control register. The primary use of the hardware Wake-up control register is to provide the possibility for some peripherals to have DMA service during deep-sleep mode without waking up entire device. These wake-ups are based on.."
bitfld.long 0x0 4. "DMAC1WAKE,Wake for DMAC1. When 1 DMAC1 being busy will cause peripheral clocking to remain running until DMAC1 completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as.." "0,1"
bitfld.long 0x0 3. "DMAC0WAKE,Wake for DMAC0. When 1 DMAC0 being busy will cause peripheral clocking to remain running until DMAC0 completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as.." "0,1"
bitfld.long 0x0 2. "DMICWAKE,Wake for Digital Microphone. When 1 the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
newline
bitfld.long 0x0 1. "FCWAKE,Wake for Flexcomm Interfaces. When 1 any Flexcomm Interface FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted." "0,1"
bitfld.long 0x0 0. "FORCEWAKE,Force peripheral clocking to stay on during deep-sleep mode. When 1 clocking to peripherals is prevented from being shut down when the CPU enters deep-sleep mode. This is intended to allow a coprocessor to continue operating while the main.." "0,1"
group.long 0xE20++0xB
line.long 0x0 "ROM_HIDING_ADDR_OFFSET,rom_hiding_addr_offset"
hexmask.long.word 0x0 0.--15. 1. "ROM_HIDING_ADDR_OFFSET,rom_hiding_addr_offset"
line.long 0x4 "ROM_HIDING_ADDR_OFFSET_DP,rom_hiding_addr_offset_dp"
hexmask.long.word 0x4 0.--15. 1. "ROM_HIDING_ADDR_OFFSET_DP,rom_hiding_addr_offset_dp"
line.long 0x8 "ROM_HIDING_LOCK,rom_hiding_lock"
hexmask.long 0x8 0.--31. 1. "ROM_HIDING_LOCK,rom_hiding_addr_offset"
tree.end
tree "SYSCTL1"
base ad:0x40022000
group.long 0x10++0x3
line.long 0x0 "MCLKPINDIR,mclk direction control"
bitfld.long 0x0 0. "MCLKPINDIR,mclk direction control" "0: MCLK is in input direction.,1: MCLK is in the output direction."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "FCCTRLSEL$1,flexcomm control selection N"
bitfld.long 0x0 24.--25. "DATAOUTSEL,DATA OUT Select. . ." "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals.,2: Shared Set1 I2S signals.,?"
bitfld.long 0x0 16.--17. "DATAINSEL,DATA IN Select. . ." "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals.,2: Shared Set1 I2S signals.,?"
newline
bitfld.long 0x0 8.--9. "WSINSEL,WS IN Select. . ." "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals.,2: Shared Set1 I2S signals.,?"
bitfld.long 0x0 0.--1. "SCKINSEL,SCK IN Select. . ." "0: Original FLEXCOMM I2S signals,1: Shared Set0 I2S signals.,2: Shared Set1 I2S signals.,?"
repeat.end
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x80)++0x3
line.long 0x0 "SHAREDCTRLSET$1,shared control set N"
bitfld.long 0x0 19. "FC3DATAOUTEN,FLEXCOMM3 DATAOUT OUTPUT ENABLE" "0: Input,1: Output"
bitfld.long 0x0 18. "F20DATAOUTEN,FLEXCOMM2 DATAOUT OUTPUT ENABLE" "0: Input,1: Output"
newline
bitfld.long 0x0 17. "FC1DATAOUTEN,FLEXCOMM1 DATAOUT OUTPUT ENABLE" "0: Input,1: Output"
bitfld.long 0x0 16. "FC0DATAOUTEN,FLEXCOMM0 DATAOUT OUTPUT ENABLE" "0: Input,1: Output"
newline
bitfld.long 0x0 8.--10. "SHAREDDATASEL,Shared DATA Select. . ." "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,?,?,?,?"
bitfld.long 0x0 4.--6. "SHAREDWSSEL,Shared WS Select. . ." "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,?,?,?,?"
newline
bitfld.long 0x0 0.--2. "SHAREDSCKSEL,Shared SCK Select. . ." "0: FLEXCOMM0,1: FLEXCOMM1,2: FLEXCOMM2,3: FLEXCOMM3,?,?,?,?"
repeat.end
group.long 0x9C++0x3
line.long 0x0 "CONFIG_LCKOUT,config lockout"
bitfld.long 0x0 0. "LCKOUT,Configuration Registers enable" "0: Enable Write to Configuration Registers,1: Disable Write to Configuration Registers."
group.long 0x200++0x3
line.long 0x0 "RXEVPULSEGEN,RX Event Pulse Generator"
bitfld.long 0x0 0. "RXEVPULSEGEN,RX Event Pulse Generator. Writing a '1' to this register will create a one PSCLK pulse width of logic '1'. It is automatically cleared." "0: No effect.,1: Pulse RXEV High for one PSCLK cycle."
group.long 0x3F0++0x7
line.long 0x0 "SCRATCH0,general purpose register 0"
hexmask.long 0x0 0.--31. 1. "SCRATCH,General Purpose 32-Bit Data Register"
line.long 0x4 "SCRATCH1,general purpose register 1"
hexmask.long 0x4 0.--31. 1. "SCRATCH,General Purpose 32-Bit Data Register"
tree.end
tree "SYSCTL2"
base ad:0x40003000
group.long 0x0++0x27
line.long 0x0 "RAM_CTRL0,RAM Memory Control Register 0"
bitfld.long 0x0 18.--19. "FLEXSPI_CACHE_TAG_WTC,flexspi_cache_tag_wtc" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "FLEXSPI_CACHE_TAG_RTC,flexspi_cache_tag_rtc" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "FLEXSPI_CACHE_WTC,flexspi_cache_wtc" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "FLEXSPI_CACHE_RTC,flexspi_cache_rtc" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "FLEXSPI_MEM_WTC,flexspi_mem_wtc" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "FLEXSPI_MEM_RTC,flexspi_mem_rtc" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "AON_MEM_WTC0,aon_mem_wtc0" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "AON_MEM_RTC0,aon_mem_rtc0" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "AON_MEM_WTC1,aon_mem_wtc1" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "AON_MEM_RTC1,aon_mem_rtc1" "0,1,2,3"
line.long 0x4 "USB_CTRL,USB Control Register"
bitfld.long 0x4 23. "USB_TX_BITSTUFF_EN,USM TX BITSTUFF EN" "0,1"
newline
bitfld.long 0x4 22. "MAC_CTRL_SEL,MAC Control Select" "0,1"
newline
bitfld.long 0x4 21. "SOFT_UTMI_IDDIG,Soft UTMI iddig" "0,1"
newline
bitfld.long 0x4 20. "SOFT_UTMI_XVALID,Soft UTMI xvalid" "0,1"
newline
bitfld.long 0x4 19. "SOFT_UTMI_SESSEND,Soft UTMI sessend" "0,1"
newline
bitfld.long 0x4 18. "PHY_RESET_SEL,PHY Reset Select" "0,1"
newline
bitfld.long 0x4 17. "SOFT_PHY_RESET,Soft PHY Reset" "0,1"
newline
bitfld.long 0x4 16. "IDDQ_TEST,iddq Test" "0,1"
newline
rbitfld.long 0x4 15. "USB_RESUME,USB Resume" "0,1"
newline
bitfld.long 0x4 13.--14. "REG_TX_BUF_WTC,reg_tx_buf_wtc" "0,1,2,3"
newline
bitfld.long 0x4 11.--12. "REG_TX_BUF_RTC,reg_tx_buf_rtc" "0,1,2,3"
newline
bitfld.long 0x4 9.--10. "REG_RX_BUF_WTC,reg_rx_buf_wtc" "0,1,2,3"
newline
bitfld.long 0x4 7.--8. "REG_RX_BUF_RTC,reg_rx_buf_rtc" "0,1,2,3"
newline
bitfld.long 0x4 6. "REG_TX_PDLVMC,reg_tx_pdlvmc" "0,1"
newline
bitfld.long 0x4 5. "REG_TX_PDFVSSM,reg_tx_pdfvssm" "0,1"
newline
bitfld.long 0x4 4. "REG_RX_PDLVMC,reg_rx_pdlvmc" "0,1"
newline
bitfld.long 0x4 3. "REG_RX_PDFVSSM,reg_rx_pdfvssm" "0,1"
newline
bitfld.long 0x4 2. "USB_PU,USB PU" "0,1"
newline
bitfld.long 0x4 1. "USB_PU_OTG,USB PU OTG" "0,1"
newline
bitfld.long 0x4 0. "USB_PU_PLL,USB PU PLL" "0,1"
line.long 0x8 "ANA_GRP_CTRL,ANA GRP control register"
bitfld.long 0x8 10.--12. "PU,Bit 12 : Analog Group Power Up . Bit11 :PU_OSC power up .Bit 10 :PU_XTL power up" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 6.--9. 1. "TEST_ANA,TEST ANA"
newline
bitfld.long 0x8 5. "AVDD1815_SEL,AVDD Select" "0,1"
newline
bitfld.long 0x8 2.--3. "IPP_ADJ,IPP_ADJ Current Select" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "ICC_ADJ,ICC_ADJ Current Select" "0,1,2,3"
line.long 0xC "AVPLL_CTRL0,Audio PLL Control register0"
hexmask.long.word 0xC 21.--29. 1. "CAL_FBDIV,FBDIV Calibration"
newline
bitfld.long 0xC 20. "CLK_DET_EN,PI Output Clock Enable for Internal Reset Circuit" "0,1"
newline
bitfld.long 0xC 19. "CLKOUT_TST_EN,Clock Out Test Output Enable" "0,1"
newline
bitfld.long 0xC 17.--18. "DPHER_DLY_SEL,DPHERCK Delay Tune" "0,1,2,3"
newline
bitfld.long 0xC 16. "EN_DPLL_C1,Enable/ Disable Channel CXs DPLL" "0,1"
newline
bitfld.long 0xC 14.--15. "EN_LP_C1,Channel CX LP Enable." "0,1,2,3"
newline
hexmask.long.byte 0xC 7.--13. 1. "EXT_SLLP_DAC,VCON Reference Value Set"
newline
bitfld.long 0xC 6. "EXT_SLLP_DAC_EN,EXT_SLLP_DAC Enable" "0,1"
newline
bitfld.long 0xC 5. "EXT_SP_FBRES_EN,External Speed Enable Pin." "0,1"
newline
hexmask.long.byte 0xC 1.--4. 1. "EXT_SPEED,External VCO Speed Control for Different VCO Frequencies."
newline
bitfld.long 0xC 0. "EXT_SPEED_EN,EXT_SPEED Enable" "0,1"
line.long 0x10 "AVPLL_CTRL1,Audio PLL Control register1"
hexmask.long.word 0x10 20.--28. 1. "FBDIV,Feedback Clock Divider Select"
newline
hexmask.long.tbyte 0x10 1.--19. 1. "FREQ_OFFSET_C1,FREQ_OFFSET_CX[18:0] Set"
newline
bitfld.long 0x10 0. "FREQ_OFFSET_READY_C1,Indicate Frequency Offset Value Readiness." "0,1"
line.long 0x14 "AVPLL_CTRL2,Audio PLL Control register2"
hexmask.long.byte 0x14 27.--30. 1. "ICP,Charge Pump Current Control Bits"
newline
hexmask.long.byte 0x14 23.--26. 1. "INTPI,PI Bias Current Select"
newline
bitfld.long 0x14 20.--22. "INTPR,PI Rload Resistor Select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 19. "MASTER_SLAVEB,This signal synchronizes frequencies of the two PLLs that are being used" "0,1"
newline
bitfld.long 0x14 17.--18. "MODE,Feedback Clock for PLL Select" "0,1,2,3"
newline
bitfld.long 0x14 16. "PLL_CAL_START,PLL Calibration Start." "0,1"
newline
hexmask.long.byte 0x14 11.--15. 1. "PLL_CALCLK_DIV,Divider Settings to Generate Calibration Clock."
newline
bitfld.long 0x14 10. "PLL_LPFC2_LESS,LPF C2 Capacitor Value Select" "0,1"
newline
bitfld.long 0x14 7.--9. "PLL_VDDRA_SEL,Gate Voltage Select for VDDBUF" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 6. "POSTDIV_0P5_C1,Audio Clock Divider Program Set" "0,1"
newline
bitfld.long 0x14 5. "PU,PLL Power-up Signal" "0,1"
newline
bitfld.long 0x14 4. "PU_C1,Power Up/Down Channel CX" "0,1"
newline
bitfld.long 0x14 3. "PU_OFST_CTRL_C1,Power Up/Down FREQ_OFFSET Integrator of CX" "0,1"
newline
bitfld.long 0x14 0.--2. "PW_SLLP,PLL in Slow Loop" "0,1,2,3,4,5,6,7"
line.long 0x18 "AVPLL_CTRL3,Audio PLL Control register3"
hexmask.long.tbyte 0x18 12.--31. 1. "P_SYNC1_C1,Set DPLLs Reference Divider"
newline
hexmask.long.byte 0x18 5.--11. 1. "REFDIV,Reference Clock Divider Select"
newline
bitfld.long 0x18 4. "REG_RING_EXTRA_I_EN,Extra Current Turn On Select." "0,1"
newline
hexmask.long.byte 0x18 0.--3. 1. "REG_SETTLE_LIMIT,Waiting Time Select Before Calibration Start.."
line.long 0x1C "AVPLL_CTRL4,Audio PLL Control register4"
hexmask.long.tbyte 0x1C 11.--30. 1. "P_SYNC2_C1,Set DPLLs Feedback Divider"
newline
bitfld.long 0x1C 9.--10. "RESERVE_IN_C1,Reserved pins" "0,1,2,3"
newline
hexmask.long.byte 0x1C 3.--8. 1. "RESERVE_PLL_IN,Reserved pins"
newline
bitfld.long 0x1C 2. "SEL_VTHVCOCONT,Select Threshold Source for Calibrated VDDVCO Voltage" "0,1"
newline
bitfld.long 0x1C 1. "SLLP_CLK_DIV5EN,Slow Loop Clock Enable" "0,1"
newline
bitfld.long 0x1C 0. "SLLP_EN_DIS,Slow Loop Select." "0,1"
line.long 0x20 "AVPLL_CTRL5,Audio PLL Control register5"
hexmask.long.word 0x20 19.--31. 1. "POSTDIV_C1,Audio Clock Divider Program Set"
newline
bitfld.long 0x20 16.--18. "SLLP_PSF_LEVEL,Slow Loop Current Generate." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 12.--15. 1. "SPEED_FBRES,External feedback resistor (VCO ring) set up bits"
newline
hexmask.long.byte 0x20 6.--11. 1. "SPEED_THRESH,Threshold for VCO Speed Setting Calibration."
newline
hexmask.long.byte 0x20 0.--5. 1. "TEST_MON,DC Test Point Register. For Internal Use Only."
line.long 0x24 "AVPLL_CTRL6,Audio PLL Control register6"
bitfld.long 0x24 17. "UPDATE_SEL,PLL Update Rate Select" "0,1"
newline
bitfld.long 0x24 15.--16. "VCO_REF1P45_SEL,VREF1P0V_VCO1P45 Value Select." "0,1,2,3"
newline
bitfld.long 0x24 13.--14. "VCON_SEL,VCON Value Set." "0,1,2,3"
newline
bitfld.long 0x24 11.--12. "VDDA23_PUMP_SEL,VREF0P96_VDDA23 PUMP Select" "0,1,2,3"
newline
bitfld.long 0x24 8.--10. "VDDBUF_ADJ,VDDVDOFBUF Voltage Level Adjust" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x24 4.--7. 1. "VDDL,Internal Regulated VDD Supply Voltage Control"
newline
bitfld.long 0x24 2.--3. "VTH_VCO_CAL,VDDVCO Voltage Threshold Select" "0,1,2,3"
newline
bitfld.long 0x24 0.--1. "VTH_VCO_PTAT,IPTAT Current to Generate VDDVCO Voltage Select" "0,1,2,3"
rgroup.long 0x28++0x3
line.long 0x0 "AVPLL_CTRL7,Audio PLL Control register7"
bitfld.long 0x0 26. "STARTC1_SEQ_HW_DONE,Start up and programming timing sequence done . After the enable of START_SEQ_HW_EN can check this status bit ." "0,1"
newline
bitfld.long 0x0 25. "PLL_CAL_DONE,Rising edge to indicate the end of PLL calibration" "0,1"
newline
bitfld.long 0x0 24. "PLL_LOCK,Lock Detect Output" "0,1"
group.long 0x2C++0x37
line.long 0x0 "AVPLL_CTRL8,Audio PLL Control register8"
bitfld.long 0x0 30. "CALI_START_SEQ_HW_EN,PLL Calibration start timing sequence hardware implementation enable . If this bit and START_SEQ_HW_EN be assarted . PLL_CAL_START bit also will be enable by hardware basing on AVPLL timing sequence . SW need to wait pll calibration.." "0,1"
newline
bitfld.long 0x0 29. "STARTC1_SEQ_HW_EN,Start up and programming the interpolator timing sequence hardware implementation enable . SW program the configure register especially FREQ_OFFSET_C1/FREQ_OFFSET_C8 firstly then enable this bit and PU field . HW will do the following.." "0,1"
newline
bitfld.long 0x0 28. "EN_DPLL_C8,Enable/ Disable Channel CXs DPLL" "0,1"
newline
bitfld.long 0x0 26.--27. "EN_LP_C8,Channel CX LP Enable." "0,1,2,3"
newline
hexmask.long.tbyte 0x0 7.--25. 1. "FREQ_OFFSET_C8,FREQ_OFFSET_CX[18:0] Set"
newline
bitfld.long 0x0 6. "FREQ_OFFSET_READY_C8,Indicate Frequency Offset Value Readiness." "0,1"
newline
bitfld.long 0x0 5. "PU_OFST_CTRL_C8,Power Up/Down FREQ_OFFSET Integrator of CX" "0,1"
newline
bitfld.long 0x0 3.--4. "RESERVE_IN_C8,Reserved pins" "0,1,2,3"
newline
bitfld.long 0x0 2. "AVPLL_RESET,SW Reset . Active high" "0,1"
newline
bitfld.long 0x0 1. "AVPLL_RESET_C1,C1 SW Reset . Active high" "0,1"
newline
bitfld.long 0x0 0. "AVPLL_RESET_C8,C8 SW Reset . Active high" "0,1"
line.long 0x4 "AVPLL_CTRL9,Audio PLL Control register9"
hexmask.long.tbyte 0x4 0.--19. 1. "P_SYNC1_C8,Set DPLLs Reference Divider"
line.long 0x8 "AVPLL_CTRL10,Audio PLL Control register10"
hexmask.long.tbyte 0x8 0.--19. 1. "P_SYNC2_C8,Set DPLLs Feedback Divider"
line.long 0xC "AVPLL_CTRL11,Audio PLL Control register11"
hexmask.long.word 0xC 19.--31. 1. "POSTDIV_C2,Audio Clock Divider Program Set"
newline
hexmask.long.tbyte 0xC 0.--18. 1. "FREQ_OFFSET_C2,FREQ_OFFSET_CX[18:0] Set"
line.long 0x10 "AVPLL_CTRL12,Audio PLL Control register12"
bitfld.long 0x10 26. "FREQ_OFFSET_READY_C2,Indicate Frequency Offset Value Readiness." "0,1"
newline
bitfld.long 0x10 25. "POSTDIV_0P5_C2,Audio Clock Divider Program Set" "0,1"
newline
bitfld.long 0x10 24. "PU_C2,Power Up/Down Channel CX" "0,1"
newline
bitfld.long 0x10 23. "PU_OFST_CTRL_C2,Power Up/Down FREQ_OFFSET Integrator of CX" "0,1"
newline
bitfld.long 0x10 22. "EN_DPLL_C2,Enable/ Disable Channel CXs DPLL" "0,1"
newline
bitfld.long 0x10 20.--21. "EN_LP_C2,Channel CX LP Enable." "0,1,2,3"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "P_SYNC1_C2,Set DPLLs Reference Divider"
line.long 0x14 "GAU_CTRL,GAU Control register"
bitfld.long 0x14 4. "GAU_ACOMP_MCLK_EN,gau acomp mclk enable" "0,1"
newline
bitfld.long 0x14 3. "GAU_GPADC0_MCLK_EN,gau gpadc0 mclk enable" "0,1"
newline
bitfld.long 0x14 2. "GAU_GPADC1_MCLK_EN,gau gpadc1 mclk enable" "0,1"
newline
bitfld.long 0x14 1. "GAU_BG_MCLK_EN,gau bg mclk enable" "0,1"
newline
bitfld.long 0x14 0. "GAU_GPDAC_MCLK_EN,gau gpdac mclk enable" "0,1"
line.long 0x18 "CTIMER_CTRL,CTIMER Control register"
bitfld.long 0x18 7. "CT3_TRIGGER_ENABLE,ctimer3 trigger_enable" "0,1"
newline
bitfld.long 0x18 6. "CT3_GLOBAL_ENABLE,ctimer3 global_enable" "0,1"
newline
bitfld.long 0x18 5. "CT2_TRIGGER_ENABLE,ctimer2 trigger_enable" "0,1"
newline
bitfld.long 0x18 4. "CT2_GLOBAL_ENABLE,ctimer2 global_enable" "0,1"
newline
bitfld.long 0x18 3. "CT1_TRIGGER_ENABLE,ctimer1 trigger_enable" "0,1"
newline
bitfld.long 0x18 2. "CT1_GLOBAL_ENABLE,ctimer1 global_enable" "0,1"
newline
bitfld.long 0x18 1. "CT0_TRIGGER_ENABLE,ctimer0 trigger_enable" "0,1"
newline
bitfld.long 0x18 0. "CT0_GLOBAL_ENABLE,ctimer0 global_enable" "0,1"
line.long 0x1C "EXT_H2H_CTRL,AHB async bridge Control register"
bitfld.long 0x1C 1. "BLE_H2H_PREFETCH_EN,ble_h2h_prefetch_en" "0,1"
newline
bitfld.long 0x1C 0. "WLAN_H2H_PREFETCH_EN,wlan_h2h_prefetch_en" "0,1"
line.long 0x20 "RAM_CTRL1,RAM Memory Control Register 1"
bitfld.long 0x20 26.--27. "ENET_WTC,enet_wtc" "0,1,2,3"
newline
bitfld.long 0x20 24.--25. "ENET_RTC,enet_rtc" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "SDU_TX_WTC,sdu_tx_wtc" "0,1,2,3"
newline
bitfld.long 0x20 20.--21. "SDU_TX_RTC,sdu_tx_rtc" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "SDU_RX_WTC,sdu_rx_wtc" "0,1,2,3"
newline
bitfld.long 0x20 16.--17. "SDU_RX_RTC,sdu_rx_rtc" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "SDU_CIS_WTC,sdu_cis_wtc" "0,1,2,3"
newline
bitfld.long 0x20 12.--13. "SDU_CIS_RTC,sdu_cis_rtc" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "S0_SRAM_WTC,s0_sram_wtc" "0,1,2,3"
newline
bitfld.long 0x20 8.--9. "S0_SRAM_RTC,s0_sram_rtc" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "PQ_WTC,pq_wtc" "0,1,2,3"
newline
bitfld.long 0x20 4.--5. "PQ_RTC,pq_rtc" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "PKC_WTC,pkc_wtc" "0,1,2,3"
newline
bitfld.long 0x20 0.--1. "PKC_RTC,pkc_rtc" "0,1,2,3"
line.long 0x24 "ROM_CTRL,ROM Control Register"
bitfld.long 0x24 8.--9. "S0_ROM_RTC_REF,s0_rom_rtc_ref" "0,1,2,3"
newline
bitfld.long 0x24 5.--7. "S0_ROM_RTC,s0_rom_rtc" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 3.--4. "CSSV2_RTC_REF,cssv2_rtc_ref" "0,1,2,3"
newline
bitfld.long 0x24 0.--2. "CSSV2_RTC,cssv2_rtc" "0,1,2,3,4,5,6,7"
line.long 0x28 "MEM_PD_CTRL,MEM PD Control enable register when PM2 mode"
bitfld.long 0x28 28. "ENET_SW_CTRL_EN,SW control enet mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 27. "SDIO_SW_CTRL_EN,SW control sdio mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 26. "OTP_SW_CTRL_EN,SW control otp mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 25. "ROM_SW_CTRL_EN,SW control rom mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 24. "FLEXSPI_SW_CTRL_EN,SW control flexspi mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 23. "PQ_SW_CTRL_EN,SW control pq mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 22. "PKC_SW_CTRL_EN,SW control pkc mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 21. "CSS_SW_CTRL_EN,SW control css mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 20. "AON1_SW_CTRL_EN,SW control aon1 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 19. "AON0_SW_CTRL_EN,SW control aon0 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 18. "SRAM18_SW_CTRL_EN,SW control sram18 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 17. "SRAM17_SW_CTRL_EN,SW control sram17 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 16. "SRAM16_SW_CTRL_EN,SW control sram16 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 15. "SRAM15_SW_CTRL_EN,SW control sram15 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 14. "SRAM14_SW_CTRL_EN,SW control sram14 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 13. "SRAM13_SW_CTRL_EN,SW control sram13 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 12. "SRAM12_SW_CTRL_EN,SW control sram12 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 11. "SRAM11_SW_CTRL_EN,SW control sram11 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 10. "SRAM10_SW_CTRL_EN,SW control sram10 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 9. "SRAM9_SW_CTRL_EN,SW control sram9 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 8. "SRAM8_SW_CTRL_EN,SW control sram8 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 7. "SRAM7_SW_CTRL_EN,SW control sram7 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 6. "SRAM6_SW_CTRL_EN,SW control sram6 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 5. "SRAM5_SW_CTRL_EN,SW control sram5 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 4. "SRAM4_SW_CTRL_EN,SW control sram4 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 3. "SRAM3_SW_CTRL_EN,SW control sram3 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 2. "SRAM2_SW_CTRL_EN,SW control sram2 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 1. "SRAM1_SW_CTRL_EN,SW control sram1 mem_pd signal enable when PM2 mode" "0,1"
newline
bitfld.long 0x28 0. "SRAM0_SW_CTRL_EN,SW control sram0 mem_pd signal enable when PM2 mode" "0,1"
line.long 0x2C "MEM_PD_CFG,MEM PD Configure register when PM2 mode"
bitfld.long 0x2C 28. "ENET_SW_CFG,sw cfg enet mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 27. "SDIO_SW_CFG,sw cfg sdio mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 26. "OTP_SW_CFG,sw cfg otp mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 25. "ROM_SW_CFG,sw cfg rom mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 24. "FLEXSPI_SW_CFG,sw cfg flexspi mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 23. "PQ_SW_CFG,sw cfg pq mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 22. "PKC_SW_CFG,sw cfg pkc mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 21. "CSS_SW_CFG,sw cfg css mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 20. "AON1_SW_CFG,sw cfg aon1 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 19. "AON0_SW_CFG,sw cfg aon0 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 18. "SRAM18_SW_CFG,sw cfg sram18 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 17. "SRAM17_SW_CFG,sw cfg sram17 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 16. "SRAM16_SW_CFG,sw cfg sram16 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 15. "SRAM15_SW_CFG,sw cfg sram15 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 14. "SRAM14_SW_CFG,sw cfg sram14 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 13. "SRAM13_SW_CFG,sw cfg sram13 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 12. "SRAM12_SW_CFG,sw cfg sram12 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 11. "SRAM11_SW_CFG,sw cfg sram11 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 10. "SRAM10_SW_CFG,sw cfg sram mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 9. "SRAM9_SW_CFG,sw cfg sram9 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 8. "SRAM8_SW_CFG,sw cfg sram8 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 7. "SRAM7_SW_CFG,sw cfg sram7 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 6. "SRAM6_SW_CFG,sw cfg sram6 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 5. "SRAM5_SW_CFG,sw cfg sram5 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 4. "SRAM4_SW_CFG,sw cfg sram4 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 3. "SRAM3_SW_CFG,sw cfg sram3 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 2. "SRAM2_SW_CFG,sw cfg sram2 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 1. "SRAM1_SW_CFG,sw cfg sram1 mem_pdwn signal when PM2 mode ; 0: active; 1: power down" "0: active,1: power down"
newline
bitfld.long 0x2C 0. "SRAM0_SW_CFG,sw cfg sram0 mem_pdwn signal when PM2 mode; 0: active; 1: power down" "0: active,1: power down"
line.long 0x30 "ENET_IN_SEL_TIMER,Select input source for enet pad0"
bitfld.long 0x30 0. "ENET_IN_SEL_TIMER,select input source as enet input" "0,1"
line.long 0x34 "ENET_IPG_STOP,Configure ipg_stop. used by enet wakeup sequence"
bitfld.long 0x34 0. "ENET_IPG_STOP,Configure ipg_stop used by enet wakeup sequence; 0: Drive enet input IPG_STOP low; 1: Drive enet input IPG_STOP high." "0: Drive enet input IPG_STOP low,1: Drive enet input IPG_STOP high"
rgroup.long 0x64++0x3
line.long 0x0 "ENET_IPG_STOP_ACK,Store ipg_stop_ack. used by enet wakeup sequence"
bitfld.long 0x0 0. "ENET_IPG_STOP_ACK,Store ipg_stop_ack used by enet wakeup sequence" "0,1"
group.long 0x68++0xF
line.long 0x0 "ROM_BRU_ADDR_MASK_DIS,Disable dynamic address masking feature"
bitfld.long 0x0 0. "ROM_BRU_ADDR_MASK_DIS,Disable dynamic address masking feature" "0,1"
line.long 0x4 "ROM_BRU_DYN_CLK_DIS,Disable dynamic clock gating feature"
bitfld.long 0x4 0. "ROM_BRU_DYN_CLK_DIS,Disable dynamic clock gating feature" "0,1"
line.long 0x8 "ROM_CPU_BIST_CLK_EN,Enable bist logic clock. need be 1 during rom bist test"
bitfld.long 0x8 0. "ROM_CPU_BIST_CLK_EN,Enable bist logic clock need be 1 during rom bist test" "0,1"
line.long 0xC "DRO_PAR_SEL,Control DRO and DR1 counter in MCI domain"
bitfld.long 0xC 2.--3. "DRO1_SEL,Control DR1 counter in MCI domain" "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "DRO0_SEL,Control DRO counter in MCI domain" "0,1,2,3"
rgroup.long 0x78++0xF
line.long 0x0 "DRO_COUNTER,16 bits counter value of DRO0 and DRO1"
hexmask.long.word 0x0 16.--31. 1. "DRO1_COUNTER,16 bits counter value of DRO1"
newline
hexmask.long.word 0x0 0.--15. 1. "DRO0_COUNTER,16 bits counter value of DRO0"
line.long 0x4 "OTP_EARLY_FUSE_VALID,Early fuse valid from OTP"
bitfld.long 0x4 0. "OTP_EARLY_FUSE_VALID,Early fuse valid from OTP" "0,1"
line.long 0x8 "OTP_MEDIUM_FUSE_VALID,Medium fuse valid from OTP"
bitfld.long 0x8 0. "OTP_MEDIUM_FUSE_VALID,Medium fuse valid from OTP" "0,1"
line.long 0xC "OTP_ALL_FUSE_VALID,All fuse valid from OTP"
bitfld.long 0xC 0. "OTP_ALL_FUSE_VALID,All fuse valid from OTP" "0,1"
group.long 0x88++0x23
line.long 0x0 "PLL_CTRL,PLL control register"
bitfld.long 0x0 20. "TCPU_ITRC_EN,0-disable the unlock event to ITRC; 1-enable the unlock event to ITRC" "0,1"
newline
bitfld.long 0x0 19. "T3_ITRC_EN,0-disable the unlock event to ITRC; 1-enable the unlock event to ITRC" "0,1"
newline
bitfld.long 0x0 17.--18. "TDDR_FLEXSPI_CLK_SEL,TDDR_PLL Clock selection from SOC for DDR CLOCK (00:3.2GHZ/11; 01: 3.2GHZ/10; 10: 3.2GHz/9;11: 3.2GHz/8)" "0: 3,1: 3,?,?"
newline
hexmask.long.byte 0x0 9.--16. 1. "TCPU_FBDIV,TCPU_PLL Feedback Divider Value ( Fxtal 40MHZ: 75 to 96 (decimal); 38.4MHz 78 to 100 (decimal))"
newline
bitfld.long 0x0 7.--8. "TCPU_FLEXSPI_CLK_SEL,TCPU_PLL DIV selection(00:3120/12; 01:3120/11; 10: 3120/10; 11:3120/9)" "0: 3120/12,1: 3120/11,?,?"
newline
rbitfld.long 0x0 6. "TCPU_LOCK,TCPU output clock lock signal" "0,1"
newline
bitfld.long 0x0 5. "TCPU_PDB,TCPU PLL enable signal from SOC" "0,1"
newline
rbitfld.long 0x0 4. "TDDR_LOCK,TDDR output clock lock signal" "0,1"
newline
bitfld.long 0x0 3. "TDDR_PDB,TDDR PLL enable signal from SOC" "0,1"
newline
rbitfld.long 0x0 1. "T3_LOCK,T3 output clock lock signal" "0,1"
newline
bitfld.long 0x0 0. "T3_PDB,T3 PLL enable signal from SOC" "0,1"
line.long 0x4 "ANA_PDWN_PM2,ana_pdwn control signal when PM2 mode"
bitfld.long 0x4 6. "T3_ANA_PDWN_PM2,T3 ana_pdwn control signal when PM2 mode 1: T3 is low power mode when PM2 0: T3 is normal mode when PM2" "0: T3 is normal mode when PM2,1: T3 is low power mode when PM2"
newline
bitfld.long 0x4 5. "TCPU_TOP_ANA_PDWN_PM2,TCPU_TOP ana_pdwn control signal when PM2 mode 1: TCPU_TOP is low power mode when PM2 0: TCPU_TOP is normal mode when PM2" "0: TCPU_TOP is normal mode when PM2,1: TCPU_TOP is low power mode when PM2"
newline
bitfld.long 0x4 4. "TDDR_TOP_ANA_PDWN_PM2,TDDR_TOP ana_pdwn control signal when PM2 mode 1: TDDR_TOP is low power mode when PM2 0: TDDR_TOP is normal mode when PM2" "0: TDDR_TOP is normal mode when PM2,1: TDDR_TOP is low power mode when PM2"
newline
bitfld.long 0x4 3. "ANA_TOP_ANA_PDWN_PM2,ANA_TOP ana_pdwn control signal when PM2 mode 1: ANA_TOP is low power mode when PM2 0: ANA_TOP is normal mode when PM2" "0: ANA_TOP is normal mode when PM2,1: ANA_TOP is low power mode when PM2"
newline
bitfld.long 0x4 2. "GAU_ANA_PDWN_PM2,GAU ana_pdwn control signal when PM2 mode 1: GAU is low power mode when PM2 0: GAU is normal mode when PM2" "0: GAU is normal mode when PM2,1: GAU is low power mode when PM2"
newline
bitfld.long 0x4 1. "USB_ANA_PDWN_PM2,USB ana_pdwn control signal when PM2 mode 1: USB is low power mode when PM2 0: USB is normal mode when PM2" "0: USB is normal mode when PM2,1: USB is low power mode when PM2"
newline
bitfld.long 0x4 0. "AVPLL_ANA_PDWN_PM2,AVPLL ana_pdwn control signal when PM2 mode 1: AVPLL is low power mode when PM2 0: AVPLL is normal mode when PM2" "0: AVPLL is normal mode when PM2,1: AVPLL is low power mode when PM2"
line.long 0x8 "SOURCE_CLK_GATE,source clock gate control"
bitfld.long 0x8 31. "REFCLK_USB_CG,gate CAU_PHY_RECLK_CPR_USB request when PM0;1:request;0:no request" "0: no request,1: request"
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bitfld.long 0x8 30. "REFCLK_AUD_CG,gate CAU_PHY_RECLK_CPR_AUD request when PM0; 1:request;0:no request" "0: no request,1: request"
newline
bitfld.long 0x8 29. "REFCLK_TDDR_CG,gate CAU_PHY_RECLK_CPR_TDDR request when PM0; MCI request CAU gate reference clock for PHY in PM2 mode (when USB/AUD/TCPU/TDDR PLL are all power down); 1:request;0:no request" "0: no request,1: request"
newline
bitfld.long 0x8 28. "REFCLK_TCPU_CG,gate CAU_PHY_RECLK_CPR_TCPU request when PM0; 1:request;0:no request" "0: no request,1: request"
newline
bitfld.long 0x8 16. "CPU_CLK_EN,enable cpu clk(c0_fr_hclk) bypass PMU gate_cpu_clk control" "0,1"
newline
bitfld.long 0x8 9. "REFCLK_SYS_CG,gate refclk_sys" "0,1"
newline
bitfld.long 0x8 7. "T3PLL_MCI_FLEXSPI_CLK_CG,gate t3pll_mci_flexspi_clk" "0,1"
newline
bitfld.long 0x8 6. "T3PLL_MCI_213P3M_CG,gate t3pll_mci_213p3m" "0,1"
newline
bitfld.long 0x8 5. "T3PLL_MCI_256M_CG,gate t3pll_mci_256m" "0,1"
newline
bitfld.long 0x8 4. "T3PLL_MCI_48_60M_IRC_CG,gate t3pll_mci_48_60m_irc" "0,1"
newline
bitfld.long 0x8 3. "TDDR_MCI_FLEXSPI_CLK_CG,gate tddr_mci_flexspi_clk" "0,1"
newline
bitfld.long 0x8 2. "TDDR_MCI_ENET_CLK_CG,gate tddr_mci_enet_clk" "0,1"
newline
bitfld.long 0x8 1. "TCPU_MCI_FLEXSPI_CLK_CG,gate tcpu_mci_flexspi_clk" "0,1"
newline
bitfld.long 0x8 0. "TCPU_MCI_CLK_CG,gate tcpu_mci_clk" "0,1"
line.long 0xC "TRNG_PWR_MODE,TRNG_PWR_MODE"
rbitfld.long 0xC 1. "STOP_ACK,The bit is used as the SoC low-power acknowledge. TRNG will generate this single clock cycle pulse one clock cycle after STOP_REQ has been asserted.0:No Acknowledge; 1:Acknowledge" "0: No Acknowledge,1: Acknowledge"
newline
bitfld.long 0xC 0. "STOP_REQ,The bit is used as the SoC low-power request. It is generated to tell TRNG that the clock to TRNG is going to stop running. This signal will be asserted no less than two clocks before TRNG clock is stopped to allow TRNG to prepare for stop.." "0: No request,1: Request"
line.long 0x10 "TRNG_PIN_CTRL,TRNG_PIN_CTRL"
rbitfld.long 0x10 2. "HW_ERROR,The bit indicate that the TRNG has generated a hardware error. This could be due to a Frequency Count Fail a run time or power on reset parameter misconfiguration and /or a failure of one or more of the built in internal entropy quality tests." "0: No Error,1: Error"
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rbitfld.long 0x10 1. "BUSY,The bit indicate that the TRNG is busy. This happens when the TRNG is busy sampling the entropy bits and has not issued an entropy valid signal.0: Free; 1: Busy; this bit should be zero after ENABLE(bit0 in this register) is set" "0: Free,1: Busy"
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bitfld.long 0x10 0. "ENABLE,The bit is used to control the interface of TRNG. 0:Disable; 1: Enable" "0: Disable,1: Enable"
line.long 0x14 "CAU_CTRL,CAU control register"
bitfld.long 0x14 31. "MCI_XOSC_EN,mci request control different modes for CAU XTAL (1 for normal mode 0 for sleep/full PD)" "0,1"
newline
rbitfld.long 0x14 0. "SOC_REFCLK_RDY,REFCLK ready signal if 1 can turn on PLL" "0,1"
line.long 0x18 "SOC_CIU_RDY_MASK,SOC_CIU_RDY_MASK"
bitfld.long 0x18 0. "SOC_CIU_RDY_MASK,1'b1:mask SOC_CIU_RDY think its value is 1; 1'b0:unmask SOC_CIU_RDY see its real value" "0: unmask SOC_CIU_RDY,1: mask SOC_CIU_RDY"
line.long 0x1C "LE_AUDIO_TIMER_ENABLE,Enable bit for le audio timer"
bitfld.long 0x1C 0. "ENABLE,1'b1:Timer is enabled; 1'b0:Timer is disabled" "0: Timer is disabled,1: Timer is enabled"
line.long 0x20 "LE_AUDIO_TIMER_CNT_CLR,Clear bit of internal counter"
bitfld.long 0x20 0. "CLR,When timer is enabled write 1 to clear internal counter write 0 has no effect" "0,1"
rgroup.long 0xAC++0xB
line.long 0x0 "LE_AUDIO_TIMER_CNT0,Counter value captured by trigger0"
hexmask.long 0x0 0.--31. 1. "CNT0,Counter value captured by trigger0"
line.long 0x4 "LE_AUDIO_TIMER_CNT1,Counter value captured by trigger1"
hexmask.long 0x4 0.--31. 1. "CNT1,Counter value captured by trigger1"
line.long 0x8 "LE_AUDIO_TIMER_CNT2,Counter value captured by trigger2"
hexmask.long 0x8 0.--31. 1. "CNT2,Counter value captured by trigger2"
group.long 0xC0++0x3
line.long 0x0 "AVPLL_CTRL13,Audio PLL Control register13"
hexmask.long.tbyte 0x0 11.--30. 1. "P_SYNC2_C2,Set DPLLs Feedback Divider"
newline
bitfld.long 0x0 9.--10. "RESERVE_IN_C2,Reserved pins" "0,1,2,3"
newline
rbitfld.long 0x0 2. "STARTC2_SEQ_HW_DONE,Start up and programming timing sequence done . After the enable of START_SEQ_HW_EN can check this status bit ." "0,1"
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bitfld.long 0x0 1. "STARTC2_SEQ_HW_EN,Start up and programming the interpolator timing sequence hardware implementation enable . SW program the configure register especially FREQ_OFFSET_C2/FREQ_OFFSET_C8 firstly then enable this bit and PU field . HW will do the following.." "0,1"
newline
bitfld.long 0x0 0. "AVPLL_RESET_C2,C2 SW Reset . Active high" "0,1"
rgroup.long 0xC4++0x3
line.long 0x0 "MEM_ACC_CHK_CODE_VIO_STATUS,CPU Code Bus Access Sram Checker Violation Status"
hexmask.long.tbyte 0x0 0.--18. 1. "STATUS,for each of these 19 bits: 0- No violation; 1-violation happened"
group.long 0xC8++0x3
line.long 0x0 "MEM_ACC_CHK_CODE_VIO_CLR,CPU Code Bus Access Sram Checker Violation Status Clear"
hexmask.long.tbyte 0x0 0.--18. 1. "STATUS_CLR,Write '1' to clear Violation Status bit; These bits are self-clear"
rgroup.long 0xCC++0x3
line.long 0x0 "MEM_ACC_CHK_SYS_VIO_STATUS,CPU SYS Bus Access Sram Checker Violation Status"
hexmask.long.tbyte 0x0 0.--18. 1. "STATUS,for each of these 19 bits: 0- No violation; 1-violation happened"
group.long 0xD0++0x7
line.long 0x0 "MEM_ACC_CHK_SYS_VIO_CLR,CPU SYS Bus Access Sram Checker Violation Status Clear"
hexmask.long.tbyte 0x0 0.--18. 1. "STATUS_CLR,Write '1' to clear Violation Status bit; These bits are self-clear"
line.long 0x4 "CFG_USB_EP_QUALITY_ADDR_FIX_DIS,disable cfg register which updates EP. qualify Address"
bitfld.long 0x4 0. "CFG_USB_EP_QUALITY_ADDR_FIX_DIS,disable cfg bit which updates EP qualify Address" "0,1"
rgroup.long 0xD8++0x3
line.long 0x0 "SOC_MCI_EXTRA,Reserved register"
hexmask.long 0x0 0.--31. 1. "SOC_MCI_EXTRA,Reserved register"
group.long 0xDC++0x23
line.long 0x0 "MCI_SOC_EXTRA,Reserved register"
hexmask.long 0x0 0.--31. 1. "MCI_SOC_EXTRA,Reserved register"
line.long 0x4 "RESERVED_REG0,Reserved register"
hexmask.long 0x4 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0x8 "RESERVED_REG1,Reserved register"
hexmask.long 0x8 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0xC "RESERVED_REG2,Reserved register"
hexmask.long 0xC 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0x10 "RESERVED_REG3,Reserved register"
hexmask.long 0x10 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0x14 "RESERVED_REG4,Reserved register"
hexmask.long 0x14 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0x18 "RESERVED_REG5,Reserved register"
hexmask.long 0x18 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0x1C "RESERVED_REG6,Reserved register"
hexmask.long 0x1C 0.--31. 1. "RESERVED_REG,Reserved register"
line.long 0x20 "RESERVED_REG7,Reserved register"
hexmask.long 0x20 0.--31. 1. "RESERVED_REG,Reserved register"
rgroup.long 0x100++0x97
line.long 0x0 "MEM_ACC_CHK_CODE_VIO_ADDR0,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x0 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x4 "MEM_ACC_CHK_CODE_VIO_MISC0,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x4 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
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bitfld.long 0x4 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
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bitfld.long 0x4 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x8 "MEM_ACC_CHK_CODE_VIO_ADDR1,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x8 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0xC "MEM_ACC_CHK_CODE_VIO_MISC1,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0xC 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0xC 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0xC 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x10 "MEM_ACC_CHK_CODE_VIO_ADDR2,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x10 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x14 "MEM_ACC_CHK_CODE_VIO_MISC2,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x14 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x14 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
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bitfld.long 0x14 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x18 "MEM_ACC_CHK_CODE_VIO_ADDR3,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x18 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x1C "MEM_ACC_CHK_CODE_VIO_MISC3,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x1C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x1C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x1C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x20 "MEM_ACC_CHK_CODE_VIO_ADDR4,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x20 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x24 "MEM_ACC_CHK_CODE_VIO_MISC4,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x24 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x24 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x24 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x28 "MEM_ACC_CHK_CODE_VIO_ADDR5,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x28 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x2C "MEM_ACC_CHK_CODE_VIO_MISC5,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x2C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x2C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x2C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x30 "MEM_ACC_CHK_CODE_VIO_ADDR6,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x30 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x34 "MEM_ACC_CHK_CODE_VIO_MISC6,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x34 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x34 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x34 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x38 "MEM_ACC_CHK_CODE_VIO_ADDR7,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x38 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x3C "MEM_ACC_CHK_CODE_VIO_MISC7,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x3C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x3C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x3C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x40 "MEM_ACC_CHK_CODE_VIO_ADDR8,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x40 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x44 "MEM_ACC_CHK_CODE_VIO_MISC8,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x44 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x44 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x44 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x48 "MEM_ACC_CHK_CODE_VIO_ADDR9,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x48 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x4C "MEM_ACC_CHK_CODE_VIO_MISC9,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x4C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x4C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x4C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x50 "MEM_ACC_CHK_CODE_VIO_ADDR10,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x50 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x54 "MEM_ACC_CHK_CODE_VIO_MISC10,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x54 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x54 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x54 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x58 "MEM_ACC_CHK_CODE_VIO_ADDR11,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x58 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x5C "MEM_ACC_CHK_CODE_VIO_MISC11,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x5C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x5C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x5C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x60 "MEM_ACC_CHK_CODE_VIO_ADDR12,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x60 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x64 "MEM_ACC_CHK_CODE_VIO_MISC12,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x64 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x64 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x64 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x68 "MEM_ACC_CHK_CODE_VIO_ADDR13,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x68 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x6C "MEM_ACC_CHK_CODE_VIO_MISC13,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x6C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x6C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x6C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x70 "MEM_ACC_CHK_CODE_VIO_ADDR14,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x70 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x74 "MEM_ACC_CHK_CODE_VIO_MISC14,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x74 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x74 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x74 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x78 "MEM_ACC_CHK_CODE_VIO_ADDR15,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x78 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x7C "MEM_ACC_CHK_CODE_VIO_MISC15,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x7C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x7C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x7C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x80 "MEM_ACC_CHK_CODE_VIO_ADDR16,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x80 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x84 "MEM_ACC_CHK_CODE_VIO_MISC16,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x84 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x84 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x84 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x88 "MEM_ACC_CHK_CODE_VIO_ADDR17,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x88 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x8C "MEM_ACC_CHK_CODE_VIO_MISC17,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x8C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x8C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x8C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x90 "MEM_ACC_CHK_CODE_VIO_ADDR18,CPU CODE Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x90 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x94 "MEM_ACC_CHK_CODE_VIO_MISC18,CPU CODE Bus Access Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x94 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x94 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x94 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
rgroup.long 0x200++0x97
line.long 0x0 "MEM_ACC_CHK_SYS_VIO_ADDR0,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x0 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x4 "MEM_ACC_CHK_SYS_VIO_MISC0,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x4 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x4 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x4 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x8 "MEM_ACC_CHK_SYS_VIO_ADDR1,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x8 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0xC "MEM_ACC_CHK_SYS_VIO_MISC1,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0xC 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0xC 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0xC 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x10 "MEM_ACC_CHK_SYS_VIO_ADDR2,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x10 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x14 "MEM_ACC_CHK_SYS_VIO_MISC2,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x14 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x14 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x14 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x18 "MEM_ACC_CHK_SYS_VIO_ADDR3,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x18 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x1C "MEM_ACC_CHK_SYS_VIO_MISC3,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x1C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x1C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x1C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x20 "MEM_ACC_CHK_SYS_VIO_ADDR4,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x20 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x24 "MEM_ACC_CHK_SYS_VIO_MISC4,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x24 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x24 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x24 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x28 "MEM_ACC_CHK_SYS_VIO_ADDR5,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x28 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x2C "MEM_ACC_CHK_SYS_VIO_MISC5,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x2C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x2C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x2C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x30 "MEM_ACC_CHK_SYS_VIO_ADDR6,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x30 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x34 "MEM_ACC_CHK_SYS_VIO_MISC6,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x34 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x34 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x34 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x38 "MEM_ACC_CHK_SYS_VIO_ADDR7,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x38 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x3C "MEM_ACC_CHK_SYS_VIO_MISC7,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x3C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x3C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x3C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x40 "MEM_ACC_CHK_SYS_VIO_ADDR8,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x40 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x44 "MEM_ACC_CHK_SYS_VIO_MISC8,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x44 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x44 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x44 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x48 "MEM_ACC_CHK_SYS_VIO_ADDR9,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x48 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x4C "MEM_ACC_CHK_SYS_VIO_MISC9,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x4C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x4C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x4C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x50 "MEM_ACC_CHK_SYS_VIO_ADDR10,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x50 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x54 "MEM_ACC_CHK_SYS_VIO_MISC10,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x54 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x54 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x54 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x58 "MEM_ACC_CHK_SYS_VIO_ADDR11,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x58 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x5C "MEM_ACC_CHK_SYS_VIO_MISC11,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x5C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x5C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x5C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x60 "MEM_ACC_CHK_SYS_VIO_ADDR12,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x60 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x64 "MEM_ACC_CHK_SYS_VIO_MISC12,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x64 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x64 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x64 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x68 "MEM_ACC_CHK_SYS_VIO_ADDR13,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x68 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x6C "MEM_ACC_CHK_SYS_VIO_MISC13,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x6C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x6C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x6C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x70 "MEM_ACC_CHK_SYS_VIO_ADDR14,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x70 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x74 "MEM_ACC_CHK_SYS_VIO_MISC14,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x74 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x74 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x74 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x78 "MEM_ACC_CHK_SYS_VIO_ADDR15,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x78 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x7C "MEM_ACC_CHK_SYS_VIO_MISC15,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x7C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x7C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x7C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x80 "MEM_ACC_CHK_SYS_VIO_ADDR16,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x80 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x84 "MEM_ACC_CHK_SYS_VIO_MISC16,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x84 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x84 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x84 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x88 "MEM_ACC_CHK_SYS_VIO_ADDR17,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x88 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x8C "MEM_ACC_CHK_SYS_VIO_MISC17,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x8C 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x8C 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x8C 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
line.long 0x90 "MEM_ACC_CHK_SYS_VIO_ADDR18,CPU SYS Bus Access Sram Checker: Address of Violated Transfer"
hexmask.long 0x90 0.--31. 1. "ADDR,Address of Violated Transfer"
line.long 0x94 "MEM_ACC_CHK_SYS_VIO_MISC18,CPU SYS BusAccess Sram Checker: Misc information of Violated Transfer"
hexmask.long.byte 0x94 4.--7. 1. "HSEC_LEVEL,HSEC_LEVEL of Violated Transfer."
newline
bitfld.long 0x94 1. "HPROT0,HPROT0 of Violated Transfer. 1-Data Access; 0-OPCODE" "0,1"
newline
bitfld.long 0x94 0. "WRITE,HWRITE of Violated Transfer. 1-Write; 0-Read" "0,1"
tree.end
tree.end
tree "SYSPLL"
base ad:0x0
tree "SYSPLL_T3"
base ad:0x45002000
rgroup.byte 0xC0++0x4
line.byte 0x0 "SYSBYPASS_SOC_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "SYSBYPASS_SOC_CTRL_ONE_RO,SYSBYPASS_SOC_CTRL_ONE_RO"
line.byte 0x1 "SYSBYPASS_SOC_CTRL_TWO_RO_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "SYSBYPASS_SOC_CTRL_TWO_RO,SYSBYPASS_SOC_CTRL_TWO_RO"
line.byte 0x2 "SYSBYPASS_SOC_CTRL_THREE_RO_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "SYSBYPASS_SOC_CTRL_THREE_RO,SYSBYPASS_SOC_CTRL_THREE_RO"
line.byte 0x3 "SYSBYPASS_BBUD_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "SYSBYPASS_BBUD_CTRL_FOUR_RO,SYSBYPASS_BBUD_CTRL_FOUR_RO"
line.byte 0x4 "REG_RO_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_RO,REG_RO"
group.byte 0xC5++0x1A
line.byte 0x0 "SYS_CTRL_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "SYS_CTRL,SYS_CTRL"
line.byte 0x1 "SYSBYPASS_SOC_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "SYSBYPASS_SOC_CTRL_ONE_RW,SYSBYPASS_SOC_CTRL_ONE_RW"
line.byte 0x2 "SYSBYPASS_SOC_CTRL_TWO_RW_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "SYSBYPASS_SOC_CTRL_TWO_RW,SYSBYPASS_SOC_CTRL_TWO_RW"
line.byte 0x3 "SYSBYPASS_SOC_CTRL_THREE_RW_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "SYSBYPASS_SOC_CTRL_THREE_RW,SYSBYPASS_SOC_CTRL_THREE_RW"
line.byte 0x4 "SYSBYPASS_BBUD_CTRL_FOUR_RW_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "SYSBYPASS_BBUD_CTRL_FOUR_RW,SYSBYPASS_BBUD_CTRL_FOUR_RW"
line.byte 0x5 "T3_CTRL_ONE_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "T3_CTRL_ONE,T3_CTRL_ONE"
line.byte 0x6 "T3_CTRL_TWO_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "T3_CTRL_TWO,T3_CTRL_TWO"
line.byte 0x7 "T3_CTRL_THREE_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "T3_CTRL_THREE,T3_CTRL_THREE"
line.byte 0x8 "T3_CTRL_FOUR_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "T3_CTRL_FOUR,T3_CTRL_FOUR"
line.byte 0x9 "T3_CTRL_FIVE_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "T3_CTRL_FIVE,T3_CTRL_FIVE"
line.byte 0xA "T3_CTRL_SIX_REG,no description available"
hexmask.byte 0xA 0.--7. 1. "T3_CTRL_SIX,T3_CTRL_SIX"
line.byte 0xB "T3_CTRL_SEVEN_REG,no description available"
hexmask.byte 0xB 0.--7. 1. "T3_CTRL_SEVEN,T3_CTRL_SEVEN"
line.byte 0xC "T3_CTRL_EIGHT_REG,no description available"
hexmask.byte 0xC 0.--7. 1. "T3_CTRL_EIGHT,T3_CTRL_EIGHT"
line.byte 0xD "T3_CTRL_NINE_REG,no description available"
hexmask.byte 0xD 0.--7. 1. "T3_CTRL_NINE,T3_CTRL_NINE"
line.byte 0xE "T3_CTRL_TEN_REG,no description available"
hexmask.byte 0xE 0.--7. 1. "T3_CTRL_TEN,T3_CTRL_TEN"
line.byte 0xF "CLKTREE_CTRL_ONE_REG,no description available"
hexmask.byte 0xF 0.--7. 1. "CLKTREE_CTRL_ONE,CLKTREE_CTRL_ONE"
line.byte 0x10 "CLKTREE_CTRL_TWO_REG,no description available"
hexmask.byte 0x10 0.--7. 1. "CLKTREE_CTRL_TWO,CLKTREE_CTRL_TWO"
line.byte 0x11 "CLKTREE_CTRL_THREE_REG,no description available"
hexmask.byte 0x11 0.--7. 1. "CLKTREE_CTRL_THREE,CLKTREE_CTRL_THREE"
line.byte 0x12 "CLKTREE_CTRL_FOUR_REG,no description available"
hexmask.byte 0x12 0.--7. 1. "CLKTREE_CTRL_FOUR,CLKTREE_CTRL_FOUR"
line.byte 0x13 "CLKTREE_CTRL_FIVE_REG,no description available"
hexmask.byte 0x13 0.--7. 1. "CLKTREE_CTRL_FIVE,CLKTREE_CTRL_FIVE"
line.byte 0x14 "CLKTREE_CTRL_SIX_REG,no description available"
hexmask.byte 0x14 0.--7. 1. "CLKTREE_CTRL_SIX,CLKTREE_CTRL_SIX"
line.byte 0x15 "GPIO_CTRL_REG,no description available"
hexmask.byte 0x15 0.--7. 1. "GPIO_CTRL,GPIO_CTRL"
line.byte 0x16 "ATEST_CTRL_REG,no description available"
hexmask.byte 0x16 0.--7. 1. "ATEST_CTRL,ATEST_CTRL"
line.byte 0x17 "RESERVED_LO_ONE_REG,no description available"
hexmask.byte 0x17 0.--7. 1. "RESERVED_LO_ONE,RESERVED_LO_ONE"
line.byte 0x18 "RESERVED_HI_ONE_REG,no description available"
hexmask.byte 0x18 0.--7. 1. "RESERVED_HI_ONE,RESERVED_HI_ONE"
line.byte 0x19 "RESERVED_MIX_ONE_REG,no description available"
hexmask.byte 0x19 0.--7. 1. "RESERVED_MIX_ONE,RESERVED_MIX_ONE"
line.byte 0x1A "RESERVED_MIX_TWO_REG,no description available"
hexmask.byte 0x1A 0.--7. 1. "RESERVED_MIX_TWO,RESERVED_MIX_TWO"
tree.end
tree "SYSPLL_TCPU"
base ad:0x45002000
rgroup.byte 0xE0++0x3
line.byte 0x0 "SYSBYPASS_SOC_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "SYSBYPASS_SOC_CTRL_ONE_RO,SYSBYPASS_SOC_CTRL_ONE_RO"
line.byte 0x1 "SYSBYPASS_SOC_CTRL_TWO_RO_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "SYSBYPASS_SOC_CTRL_TWO_RO,SYSBYPASS_SOC_CTRL_TWO_RO"
line.byte 0x2 "SYSBYPASS_SOC_CTRL_THREE_RO_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "SYSBYPASS_SOC_CTRL_THREE_RO,SYSBYPASS_SOC_CTRL_THREE_RO"
line.byte 0x3 "REG_RO_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_RO,REG_RO"
group.byte 0xE4++0xF
line.byte 0x0 "SYS_CTRL_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "SYS_CTRL,SYS_CTRL"
line.byte 0x1 "SYSBYPASS_SOC_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "SYSBYPASS_SOC_CTRL_ONE_RW,SYSBYPASS_SOC_CTRL_ONE_RW"
line.byte 0x2 "SYSBYPASS_SOC_CTRL_TWO_RW_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "SYSBYPASS_SOC_CTRL_TWO_RW,SYSBYPASS_SOC_CTRL_TWO_RW"
line.byte 0x3 "SYSBYPASS_SOC_CTRL_THREE_RW_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "SYSBYPASS_SOC_CTRL_THREE_RW,SYSBYPASS_SOC_CTRL_THREE_RW"
line.byte 0x4 "TCPU_CTRL_ONE_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "TCPU_CTRL_ONE,TCPU_CTRL_ONE"
line.byte 0x5 "TCPU_CTRL_TWO_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "TCPU_CTRL_TWO,TCPU_CTRL_TWO"
line.byte 0x6 "TCPU_CTRL_THREE_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "TCPU_CTRL_THREE,TCPU_CTRL_THREE"
line.byte 0x7 "TCPU_CTRL_FOUR_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "TCPU_CTRL_FOUR,TCPU_CTRL_FOUR"
line.byte 0x8 "TCPU_CTRL_FIVE_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "TCPU_CTRL_FIVE,TCPU_CTRL_FIVE"
line.byte 0x9 "TCPU_CTRL_SIX_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "TCPU_CTRL_SIX,TCPU_CTRL_SIX"
line.byte 0xA "CLKTREE_CTRL_ONE_REG,no description available"
hexmask.byte 0xA 0.--7. 1. "CLKTREE_CTRL_ONE,CLKTREE_CTRL_ONE"
line.byte 0xB "CLKTREE_CTRL_TWO_REG,no description available"
hexmask.byte 0xB 0.--7. 1. "CLKTREE_CTRL_TWO,CLKTREE_CTRL_TWO"
line.byte 0xC "GPIO_CTRL_REG,no description available"
hexmask.byte 0xC 0.--7. 1. "GPIO_CTRL,GPIO_CTRL"
line.byte 0xD "ATEST_CTRL_REG,no description available"
hexmask.byte 0xD 0.--7. 1. "ATEST_CTRL,ATEST_CTRL"
line.byte 0xE "RESERVED_LO_REG,no description available"
hexmask.byte 0xE 0.--7. 1. "RESERVED_LO,RESERVED_LO"
line.byte 0xF "RESERVED_HI_REG,no description available"
hexmask.byte 0xF 0.--7. 1. "RESERVED_HI,RESERVED_HI"
tree.end
tree "SYSPLL_TDDR"
base ad:0x45002000
rgroup.byte 0xA0++0x3
line.byte 0x0 "SYSBYPASS_SOC_CTRL_ONE_RO_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "SYSBYPASS_SOC_CTRL_ONE_RO,SYSBYPASS_SOC_CTRL_ONE_RO"
line.byte 0x1 "SYSBYPASS_SOC_CTRL_TWO_RO_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "SYSBYPASS_SOC_CTRL_TWO_RO,SYSBYPASS_SOC_CTRL_TWO_RO"
line.byte 0x2 "SYSBYPASS_SOC_CTRL_THREE_RO_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "SYSBYPASS_SOC_CTRL_THREE_RO,SYSBYPASS_SOC_CTRL_THREE_RO"
line.byte 0x3 "REG_RO_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_RO,REG_RO"
group.byte 0xA4++0xF
line.byte 0x0 "SYS_CTRL_REG,no description available"
hexmask.byte 0x0 0.--7. 1. "REG_SYS_CTRL,REG_SYS_CTRL"
line.byte 0x1 "SYSBYPASS_SOC_CTRL_ONE_RW_REG,no description available"
hexmask.byte 0x1 0.--7. 1. "REG_SYSBYPASS_SOC_CTRL_ONE_RW,REG_SYSBYPASS_SOC_CTRL_ONE_RW"
line.byte 0x2 "SYSBYPASS_SOC_CTRL_TWO_RW_REG,no description available"
hexmask.byte 0x2 0.--7. 1. "REG_SYSBYPASS_SOC_CTRL_TWO_RW,REG_SYSBYPASS_SOC_CTRL_TWO_RW"
line.byte 0x3 "SYSBYPASS_SOC_CTRL_THREE_RW_REG,no description available"
hexmask.byte 0x3 0.--7. 1. "REG_SYSBYPASS_SOC_CTRL_THREE_RW,REG_SYSBYPASS_SOC_CTRL_THREE_RW"
line.byte 0x4 "TDDR_CTRL_ONE_REG,no description available"
hexmask.byte 0x4 0.--7. 1. "REG_TDDR_CTRL_ONE,REG_TDDR_CTRL_ONE"
line.byte 0x5 "TDDR_CTRL_TWO_REG,no description available"
hexmask.byte 0x5 0.--7. 1. "REG_TDDR_CTRL_TWO,REG_TDDR_CTRL_TWO"
line.byte 0x6 "TDDR_CTRL_THREE_REG,no description available"
hexmask.byte 0x6 0.--7. 1. "REG_TDDR_CTRL_THREE,REG_TDDR_CTRL_THREE"
line.byte 0x7 "TDDR_CTRL_FOUR_REG,no description available"
hexmask.byte 0x7 0.--7. 1. "REG_TDDR_CTRL_FOUR,REG_TDDR_CTRL_FOUR"
line.byte 0x8 "TDDR_CTRL_FIVE_REG,no description available"
hexmask.byte 0x8 0.--7. 1. "REG_TDDR_CTRL_FIVE,REG_TDDR_CTRL_FIVE"
line.byte 0x9 "TDDR_CTRL_SIX_REG,no description available"
hexmask.byte 0x9 0.--7. 1. "REG_TDDR_CTRL_SIX,REG_TDDR_CTRL_SIX"
line.byte 0xA "CLKTREE_CTRL_ONE_REG,no description available"
hexmask.byte 0xA 0.--7. 1. "REG_CLKTREE_CTRL_ONE,REG_CLKTREE_CTRL_ONE"
line.byte 0xB "CLKTREE_CTRL_TWO_REG,no description available"
hexmask.byte 0xB 0.--7. 1. "REG_CLKTREE_CTRL_TWO,REG_CLKTREE_CTRL_TWO"
line.byte 0xC "GPIO_CTRL_REG,no description available"
hexmask.byte 0xC 0.--7. 1. "REG_GPIO_CTRL,REG_GPIO_CTRL"
line.byte 0xD "ATEST_CTRL_REG,no description available"
hexmask.byte 0xD 0.--7. 1. "REG_ATEST_CTRL,REG_ATEST_CTRL"
line.byte 0xE "RESERVED_LO_REG,no description available"
hexmask.byte 0xE 0.--7. 1. "REG_RESERVED_LO,REG_RESERVED_LO"
line.byte 0xF "RESERVED_HI_REG,no description available"
hexmask.byte 0xF 0.--7. 1. "REG_RESERVED_HI,REG_RESERVED_HI"
tree.end
tree.end
tree "TRNG (True Random Number Generator)"
base ad:0x40014000
group.long 0x0++0x7
line.long 0x0 "MCTL,Miscellaneous Control Register"
bitfld.long 0x0 16. "PRGM,Programming Mode Select" "0,1"
rbitfld.long 0x0 15. "OSC2_FAIL,Oscillator 2 Failure" "0,1"
newline
bitfld.long 0x0 14. "LRUN_CONT,Long run count continues between entropy generations" "0,1"
rbitfld.long 0x0 13. "TSTOP_OK,TRNG_OK_TO_STOP" "0,1"
newline
eventfld.long 0x0 12. "ERR,Read: Error status" "0,1"
rbitfld.long 0x0 11. "TST_OUT,Read only: Test point inside ring oscillator." "0,1"
newline
rbitfld.long 0x0 10. "ENT_VAL,Read only: Entropy Valid" "0,1"
rbitfld.long 0x0 9. "FCT_VAL,Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT." "0,1"
newline
rbitfld.long 0x0 8. "FCT_FAIL,Read only: Frequency Count Fail" "0,1"
bitfld.long 0x0 7. "FOR_SCLK,Force System Clock" "0,1"
newline
bitfld.long 0x0 6. "RST_DEF,Reset Defaults" "0,1"
rbitfld.long 0x0 5. "UNUSED5,This bit is unused. Always reads zero." "0,1"
newline
rbitfld.long 0x0 4. "UNUSED4,This bit is unused. Always reads zero." "0,1"
bitfld.long 0x0 2.--3. "OSC_DIV,Oscillator Divide" "0: use ring oscillator with no divide,1: use ring oscillator divided-by-2,2: use ring oscillator divided-by-4,3: use ring oscillator divided-by-8"
line.long 0x4 "SCMISC,Statistical Check Miscellaneous Register"
hexmask.long.byte 0x4 16.--19. 1. "RTY_CT,RETRY COUNT"
hexmask.long.byte 0x4 0.--7. 1. "LRUN_MAX,LONG RUN MAX LIMIT"
group.long 0x10++0x3
line.long 0x0 "SDCTL,Seed Control Register"
hexmask.long.word 0x0 16.--31. 1. "ENT_DLY,Entropy Delay"
hexmask.long.word 0x0 0.--15. 1. "SAMP_SIZE,Sample Size"
rgroup.long 0x14++0x3
line.long 0x0 "TOTSAM,Total Samples Register"
hexmask.long.tbyte 0x0 0.--19. 1. "TOT_SAM,Total Samples"
group.long 0x18++0x3
line.long 0x0 "FRQMIN,Frequency Count Minimum Limit Register"
hexmask.long.tbyte 0x0 0.--21. 1. "FRQ_MIN,Frequency Count Minimum Limit"
rgroup.long 0x18++0x7
line.long 0x0 "OSC2_FRQCNT,Oscillator-2 Frequency Count Register"
hexmask.long.tbyte 0x0 0.--21. 1. "OSC2_FRQ_CT,Frequency Count"
line.long 0x4 "FRQCNT,Frequency Count Register"
hexmask.long.tbyte 0x4 0.--21. 1. "FRQ_CT,Frequency Count"
group.long 0x1C++0x3
line.long 0x0 "FRQMAX,Frequency Count Maximum Limit Register"
hexmask.long.tbyte 0x0 0.--21. 1. "FRQ_MAX,Frequency Counter Maximum Limit"
rgroup.long 0x20++0x3
line.long 0x0 "SCMC,Statistical Check Monobit Count Register"
hexmask.long.word 0x0 0.--15. 1. "MONO_CT,Monobit Count"
group.long 0x20++0x3
line.long 0x0 "SCML,Statistical Check Monobit Limit Register"
hexmask.long.word 0x0 16.--31. 1. "MONO_RNG,Monobit Range"
hexmask.long.word 0x0 0.--15. 1. "MONO_MAX,Monobit Maximum Limit"
rgroup.long 0x24++0x3
line.long 0x0 "SCR1C,Statistical Check Run Length 1 Count Register"
hexmask.long.word 0x0 16.--30. 1. "R1_1_CT,Runs of One Length 1 Count"
hexmask.long.word 0x0 0.--14. 1. "R1_0_CT,Runs of Zero Length 1 Count"
group.long 0x24++0x3
line.long 0x0 "SCR1L,Statistical Check Run Length 1 Limit Register"
hexmask.long.word 0x0 16.--30. 1. "RUN1_RNG,Run Length 1 Range"
hexmask.long.word 0x0 0.--14. 1. "RUN1_MAX,Run Length 1 Maximum Limit"
rgroup.long 0x28++0x3
line.long 0x0 "SCR2C,Statistical Check Run Length 2 Count Register"
hexmask.long.word 0x0 16.--29. 1. "R2_1_CT,Runs of One Length 2 Count"
hexmask.long.word 0x0 0.--13. 1. "R2_0_CT,Runs of Zero Length 2 Count"
group.long 0x28++0x3
line.long 0x0 "SCR2L,Statistical Check Run Length 2 Limit Register"
hexmask.long.word 0x0 16.--29. 1. "RUN2_RNG,Run Length 2 Range"
hexmask.long.word 0x0 0.--13. 1. "RUN2_MAX,Run Length 2 Maximum Limit"
rgroup.long 0x2C++0x3
line.long 0x0 "SCR3C,Statistical Check Run Length 3 Count Register"
hexmask.long.word 0x0 16.--28. 1. "R3_1_CT,Runs of Ones Length 3 Count"
hexmask.long.word 0x0 0.--12. 1. "R3_0_CT,Runs of Zeroes Length 3 Count"
group.long 0x2C++0x3
line.long 0x0 "SCR3L,Statistical Check Run Length 3 Limit Register"
hexmask.long.word 0x0 16.--28. 1. "RUN3_RNG,Run Length 3 Range"
hexmask.long.word 0x0 0.--12. 1. "RUN3_MAX,Run Length 3 Maximum Limit"
rgroup.long 0x3C++0x3
line.long 0x0 "STATUS,Status Register"
hexmask.long.byte 0x0 16.--19. 1. "RETRY_CT,RETRY COUNT"
bitfld.long 0x0 15. "TFMB,Test Fail Mono Bit. If TFMB=1 the Mono Bit Test has failed." "0,1"
newline
bitfld.long 0x0 13. "TFLR,Test Fail Long Run. If TFLR=1 the Long Run Test has failed." "0,1"
bitfld.long 0x0 5. "TF3BR1,Test Fail 3-Bit Run Sampling 1s. If TF3BR1=1 the 3-Bit Run Sampling 1s Test has failed." "0,1"
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bitfld.long 0x0 4. "TF3BR0,Test Fail 3-Bit Run Sampling 0s. If TF3BR0=1 the 3-Bit Run Sampling 0s Test has failed." "0,1"
bitfld.long 0x0 3. "TF2BR1,Test Fail 2-Bit Run Sampling 1s. If TF2BR1=1 the 2-Bit Run Sampling 1s Test has failed." "0,1"
newline
bitfld.long 0x0 2. "TF2BR0,Test Fail 2-Bit Run Sampling 0s. If TF2BR0=1 the 2-Bit Run Sampling 0s Test has failed." "0,1"
bitfld.long 0x0 1. "TF1BR1,Test Fail 1-Bit Run Sampling 1s. If TF1BR1=1 the 1-Bit Run Sampling 1s Test has failed." "0,1"
newline
bitfld.long 0x0 0. "TF1BR0,Test Fail 1-Bit Run Sampling 0s. If TF1BR0=1 the 1-Bit Run Sampling 0s Test has failed." "0,1"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x40)++0x3
line.long 0x0 "ENT[$1],Entropy Read Register"
hexmask.long 0x0 0.--31. 1. "ENT,Entropy Value"
repeat.end
group.long 0xA0++0xB
line.long 0x0 "SEC_CFG,Security Configuration Register"
bitfld.long 0x0 2. "UNUSED2,This bit is unused. Ignore." "0,1"
bitfld.long 0x0 1. "NO_PRGM,If set the TRNG registers cannot be programmed" "0: Programability of registers controlled only by..,1: Overides Miscellaneous Control Register access.."
newline
bitfld.long 0x0 0. "UNUSED0,This bit is unused. Ignore." "0,1"
line.long 0x4 "INT_CTRL,Interrupt Control Register"
bitfld.long 0x4 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register." "0: Same behavior as bit 0 of this register.,1: Same behavior as bit 0 of this register."
bitfld.long 0x4 1. "ENT_VAL,Same behavior as bit 0 of this register." "0: Same behavior as bit 0 of this register.,1: Same behavior as bit 0 of this register."
newline
bitfld.long 0x4 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted." "0: Corresponding bit of INT_STATUS register cleared.,1: Corresponding bit of INT_STATUS register active."
line.long 0x8 "INT_MASK,Mask Register"
bitfld.long 0x8 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register." "0: Same behavior as bit 0 of this register.,1: Same behavior as bit 0 of this register."
bitfld.long 0x8 1. "ENT_VAL,Same behavior as bit 0 of this register." "0: Same behavior as bit 0 of this register.,1: Same behavior as bit 0 of this register."
newline
bitfld.long 0x8 0. "HW_ERR,Bit position that can be cleared or set to enable the corresponding bit of INT_STATUS to show interupt status" "0: Corresponding interrupt of INT_STATUS is masked.,1: Corresponding bit of INT_STATUS is active."
rgroup.long 0xAC++0x3
line.long 0x0 "INT_STATUS,Interrupt Status Register"
bitfld.long 0x0 2. "FRQ_CT_FAIL,Read only: Frequency Count Fail" "0: No hardware nor self test frequency errors.,1: The frequency counter has detected a failure."
bitfld.long 0x0 1. "ENT_VAL,Read only: Entropy Valid" "0: Busy generation entropy. Any value read is..,1: TRNG can be stopped and entropy is valid if read."
newline
bitfld.long 0x0 0. "HW_ERR,Read: Error status" "0: no error,1: error detected."
group.long 0xEC++0x3
line.long 0x0 "OSC2_CTL,RNG Oscillator 2 Control Register"
bitfld.long 0x0 14. "OSC_FAILSAFE_TEST,Test point inside ring oscillator 2." "0,1"
bitfld.long 0x0 12.--13. "OSC_FAILSAFE_LMT,Test point inside ring oscillator 2." "0,1,2,3"
newline
rbitfld.long 0x0 11. "OSC2_TST_OUT,Test point inside ring oscillator 2." "0,1"
rbitfld.long 0x0 9. "OSC2_FCT_VAL,TRNG Oscillator 2 Frequency Count Valid" "0,1"
newline
bitfld.long 0x0 4. "OSC2_OUT_EN,Oscillator 2 Output Enable." "0,1"
bitfld.long 0x0 2.--3. "OSC2_DIV,Oscillator 2 divide control" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "TRNG_ENT_CTL,TRNG entropy generation control." "0,1,2,3"
rgroup.long 0xF0++0x7
line.long 0x0 "VID1,Version ID Register (MS)"
hexmask.long.word 0x0 16.--31. 1. "IP_ID,Shows the IP ID."
hexmask.long.byte 0x0 8.--15. 1. "MAJ_REV,Shows the IP's Major revision of the TRNG."
newline
hexmask.long.byte 0x0 0.--7. 1. "MIN_REV,Shows the IP's Minor revision of the TRNG."
line.long 0x4 "VID2,Version ID Register (LS)"
hexmask.long.byte 0x4 24.--31. 1. "ERA,Shows the compile options for the TRNG."
hexmask.long.byte 0x4 16.--23. 1. "INTG_OPT,Shows the integration options for the TRNG. (For 2019 or newer SoCs)."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECO_REV,Shows the IP's ECO revision of the TRNG."
hexmask.long.byte 0x4 0.--7. 1. "CONFIG_OPT,Shows the IP's Configuaration options for the TRNG."
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver Transmitter)"
base ad:0x0
tree "USART0"
base ad:0x40106000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration"
bitfld.long 0x0 23. "TXPOL,Transmit data polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 22. "RXPOL,Receive Data Polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity" "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
newline
bitfld.long 0x0 20. "OESEL,Output Enable Select" "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal is configured to provide.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address Matching Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode"
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master Select" "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Clock Polarity" "0: Falling edge. RXD is sampled on the falling edge..,1: Rising edge. RXD is sampled on the rising edge.."
newline
bitfld.long 0x0 11. "SYNCEN,Synchronous Enable. Selects synchronous or asynchronous operation." "0: Asynchronous mode,1: Synchronous mode"
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable" "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 8. "LINMODE,LIN Break Mode Enable" "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Mode 32 kHz" "0: Disabled. USART uses standard clocking.,1: Enabled"
newline
bitfld.long 0x0 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits. This setting should be used only.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Parity Select. Selects what type of parity is used by the USART." "0: No parity,?,2: Even parity,3: Odd parity"
newline
bitfld.long 0x0 2.--3. "DATALEN,Data Length. Selects the data size for the USART." "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable" "0: Disabled,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect. No effect on the CC bit.,1: Auto-clear"
newline
bitfld.long 0x4 8. "CC,Continuous Clock Generation" "0: Clock on character,1: Continuous clock"
newline
bitfld.long 0x4 6. "TXDIS,Transmit Disable" "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled. The USART presents all incoming data.,1: Enabled"
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
line.long 0x8 "STAT,USART Status"
eventfld.long 0x8 16. "ABERR,Auto Baud Error" "0,1"
newline
eventfld.long 0x8 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
eventfld.long 0x8 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 12. "START,Start" "0,1"
newline
eventfld.long 0x8 11. "DELTARXBRK,Delta Received Break" "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break" "0,1"
newline
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle. Indicates that the USART transmitter..,1: Idle. Indicates that the USART transmitter is.."
newline
eventfld.long 0x8 5. "DELTACTS,Delta CTS" "0,1"
newline
rbitfld.long 0x8 4. "CTS,CTS value" "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data.,1: The transmitter is not currently sending data."
newline
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data.,1: The receiver is not currently receiving data."
line.long 0xC "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status"
bitfld.long 0xC 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.."
newline
bitfld.long 0xC 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected. See.."
newline
bitfld.long 0xC 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.."
newline
bitfld.long 0xC 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.."
newline
bitfld.long 0xC 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start bit.."
newline
bitfld.long 0xC 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: Enable"
newline
bitfld.long 0xC 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.."
newline
bitfld.long 0xC 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change in.."
newline
bitfld.long 0xC 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
bitfld.long 0x0 16. "ABERRCLR,Auto Baud Error Clear" "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Receive Noise Clear" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Parity Error Clear" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Frame Error Clear" "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Start Clear" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Transmit Disable Clear" "0,1"
newline
bitfld.long 0x0 5. "DELTACTSCLR,Delta CTS Clear" "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Transmit Idle Clear" "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator"
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,Baud Rate Generator Value"
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt Status"
bitfld.long 0x0 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 12. "START,Start Detected on Receiver Flag" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1"
newline
bitfld.long 0x0 5. "DELTACTS,Delta CTS Change Flag" "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle Flag" "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample Selection Register for Asynchronous Communication"
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value"
line.long 0x4 "ADDR,Address Register for Automatic Address Matching"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Address"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied."
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied."
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Triggers DMA for the receive function if the.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function.,1: Triggers DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: Not used,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full.,1: The receive FIFO is full."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty.,1: The receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty.,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt"
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable." "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit FIFO.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will be.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "USART1"
base ad:0x40107000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration"
bitfld.long 0x0 23. "TXPOL,Transmit data polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 22. "RXPOL,Receive Data Polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity" "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
newline
bitfld.long 0x0 20. "OESEL,Output Enable Select" "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal is configured to provide.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address Matching Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode"
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master Select" "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Clock Polarity" "0: Falling edge. RXD is sampled on the falling edge..,1: Rising edge. RXD is sampled on the rising edge.."
newline
bitfld.long 0x0 11. "SYNCEN,Synchronous Enable. Selects synchronous or asynchronous operation." "0: Asynchronous mode,1: Synchronous mode"
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable" "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 8. "LINMODE,LIN Break Mode Enable" "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Mode 32 kHz" "0: Disabled. USART uses standard clocking.,1: Enabled"
newline
bitfld.long 0x0 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits. This setting should be used only.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Parity Select. Selects what type of parity is used by the USART." "0: No parity,?,2: Even parity,3: Odd parity"
newline
bitfld.long 0x0 2.--3. "DATALEN,Data Length. Selects the data size for the USART." "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable" "0: Disabled,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect. No effect on the CC bit.,1: Auto-clear"
newline
bitfld.long 0x4 8. "CC,Continuous Clock Generation" "0: Clock on character,1: Continuous clock"
newline
bitfld.long 0x4 6. "TXDIS,Transmit Disable" "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled. The USART presents all incoming data.,1: Enabled"
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
line.long 0x8 "STAT,USART Status"
eventfld.long 0x8 16. "ABERR,Auto Baud Error" "0,1"
newline
eventfld.long 0x8 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
eventfld.long 0x8 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 12. "START,Start" "0,1"
newline
eventfld.long 0x8 11. "DELTARXBRK,Delta Received Break" "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break" "0,1"
newline
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle. Indicates that the USART transmitter..,1: Idle. Indicates that the USART transmitter is.."
newline
eventfld.long 0x8 5. "DELTACTS,Delta CTS" "0,1"
newline
rbitfld.long 0x8 4. "CTS,CTS value" "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data.,1: The transmitter is not currently sending data."
newline
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data.,1: The receiver is not currently receiving data."
line.long 0xC "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status"
bitfld.long 0xC 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.."
newline
bitfld.long 0xC 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected. See.."
newline
bitfld.long 0xC 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.."
newline
bitfld.long 0xC 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.."
newline
bitfld.long 0xC 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start bit.."
newline
bitfld.long 0xC 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: Enable"
newline
bitfld.long 0xC 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.."
newline
bitfld.long 0xC 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change in.."
newline
bitfld.long 0xC 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
bitfld.long 0x0 16. "ABERRCLR,Auto Baud Error Clear" "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Receive Noise Clear" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Parity Error Clear" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Frame Error Clear" "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Start Clear" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Transmit Disable Clear" "0,1"
newline
bitfld.long 0x0 5. "DELTACTSCLR,Delta CTS Clear" "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Transmit Idle Clear" "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator"
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,Baud Rate Generator Value"
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt Status"
bitfld.long 0x0 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 12. "START,Start Detected on Receiver Flag" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1"
newline
bitfld.long 0x0 5. "DELTACTS,Delta CTS Change Flag" "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle Flag" "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample Selection Register for Asynchronous Communication"
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value"
line.long 0x4 "ADDR,Address Register for Automatic Address Matching"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Address"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied."
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied."
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Triggers DMA for the receive function if the.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function.,1: Triggers DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: Not used,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full.,1: The receive FIFO is full."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty.,1: The receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty.,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt"
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable." "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit FIFO.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will be.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "USART2"
base ad:0x40108000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration"
bitfld.long 0x0 23. "TXPOL,Transmit data polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 22. "RXPOL,Receive Data Polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity" "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
newline
bitfld.long 0x0 20. "OESEL,Output Enable Select" "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal is configured to provide.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address Matching Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode"
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master Select" "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Clock Polarity" "0: Falling edge. RXD is sampled on the falling edge..,1: Rising edge. RXD is sampled on the rising edge.."
newline
bitfld.long 0x0 11. "SYNCEN,Synchronous Enable. Selects synchronous or asynchronous operation." "0: Asynchronous mode,1: Synchronous mode"
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable" "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 8. "LINMODE,LIN Break Mode Enable" "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Mode 32 kHz" "0: Disabled. USART uses standard clocking.,1: Enabled"
newline
bitfld.long 0x0 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits. This setting should be used only.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Parity Select. Selects what type of parity is used by the USART." "0: No parity,?,2: Even parity,3: Odd parity"
newline
bitfld.long 0x0 2.--3. "DATALEN,Data Length. Selects the data size for the USART." "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable" "0: Disabled,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect. No effect on the CC bit.,1: Auto-clear"
newline
bitfld.long 0x4 8. "CC,Continuous Clock Generation" "0: Clock on character,1: Continuous clock"
newline
bitfld.long 0x4 6. "TXDIS,Transmit Disable" "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled. The USART presents all incoming data.,1: Enabled"
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
line.long 0x8 "STAT,USART Status"
eventfld.long 0x8 16. "ABERR,Auto Baud Error" "0,1"
newline
eventfld.long 0x8 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
eventfld.long 0x8 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 12. "START,Start" "0,1"
newline
eventfld.long 0x8 11. "DELTARXBRK,Delta Received Break" "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break" "0,1"
newline
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle. Indicates that the USART transmitter..,1: Idle. Indicates that the USART transmitter is.."
newline
eventfld.long 0x8 5. "DELTACTS,Delta CTS" "0,1"
newline
rbitfld.long 0x8 4. "CTS,CTS value" "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data.,1: The transmitter is not currently sending data."
newline
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data.,1: The receiver is not currently receiving data."
line.long 0xC "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status"
bitfld.long 0xC 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.."
newline
bitfld.long 0xC 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected. See.."
newline
bitfld.long 0xC 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.."
newline
bitfld.long 0xC 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.."
newline
bitfld.long 0xC 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start bit.."
newline
bitfld.long 0xC 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: Enable"
newline
bitfld.long 0xC 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.."
newline
bitfld.long 0xC 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change in.."
newline
bitfld.long 0xC 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
bitfld.long 0x0 16. "ABERRCLR,Auto Baud Error Clear" "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Receive Noise Clear" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Parity Error Clear" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Frame Error Clear" "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Start Clear" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Transmit Disable Clear" "0,1"
newline
bitfld.long 0x0 5. "DELTACTSCLR,Delta CTS Clear" "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Transmit Idle Clear" "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator"
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,Baud Rate Generator Value"
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt Status"
bitfld.long 0x0 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 12. "START,Start Detected on Receiver Flag" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1"
newline
bitfld.long 0x0 5. "DELTACTS,Delta CTS Change Flag" "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle Flag" "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample Selection Register for Asynchronous Communication"
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value"
line.long 0x4 "ADDR,Address Register for Automatic Address Matching"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Address"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied."
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied."
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Triggers DMA for the receive function if the.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function.,1: Triggers DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: Not used,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full.,1: The receive FIFO is full."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty.,1: The receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty.,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt"
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable." "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit FIFO.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will be.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "USART3"
base ad:0x40109000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration"
bitfld.long 0x0 23. "TXPOL,Transmit data polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 22. "RXPOL,Receive Data Polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity" "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
newline
bitfld.long 0x0 20. "OESEL,Output Enable Select" "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal is configured to provide.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address Matching Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode"
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master Select" "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Clock Polarity" "0: Falling edge. RXD is sampled on the falling edge..,1: Rising edge. RXD is sampled on the rising edge.."
newline
bitfld.long 0x0 11. "SYNCEN,Synchronous Enable. Selects synchronous or asynchronous operation." "0: Asynchronous mode,1: Synchronous mode"
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable" "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 8. "LINMODE,LIN Break Mode Enable" "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Mode 32 kHz" "0: Disabled. USART uses standard clocking.,1: Enabled"
newline
bitfld.long 0x0 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits. This setting should be used only.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Parity Select. Selects what type of parity is used by the USART." "0: No parity,?,2: Even parity,3: Odd parity"
newline
bitfld.long 0x0 2.--3. "DATALEN,Data Length. Selects the data size for the USART." "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable" "0: Disabled,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect. No effect on the CC bit.,1: Auto-clear"
newline
bitfld.long 0x4 8. "CC,Continuous Clock Generation" "0: Clock on character,1: Continuous clock"
newline
bitfld.long 0x4 6. "TXDIS,Transmit Disable" "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled. The USART presents all incoming data.,1: Enabled"
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
line.long 0x8 "STAT,USART Status"
eventfld.long 0x8 16. "ABERR,Auto Baud Error" "0,1"
newline
eventfld.long 0x8 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
eventfld.long 0x8 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 12. "START,Start" "0,1"
newline
eventfld.long 0x8 11. "DELTARXBRK,Delta Received Break" "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break" "0,1"
newline
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle. Indicates that the USART transmitter..,1: Idle. Indicates that the USART transmitter is.."
newline
eventfld.long 0x8 5. "DELTACTS,Delta CTS" "0,1"
newline
rbitfld.long 0x8 4. "CTS,CTS value" "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data.,1: The transmitter is not currently sending data."
newline
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data.,1: The receiver is not currently receiving data."
line.long 0xC "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status"
bitfld.long 0xC 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.."
newline
bitfld.long 0xC 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected. See.."
newline
bitfld.long 0xC 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.."
newline
bitfld.long 0xC 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.."
newline
bitfld.long 0xC 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start bit.."
newline
bitfld.long 0xC 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: Enable"
newline
bitfld.long 0xC 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.."
newline
bitfld.long 0xC 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change in.."
newline
bitfld.long 0xC 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
bitfld.long 0x0 16. "ABERRCLR,Auto Baud Error Clear" "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Receive Noise Clear" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Parity Error Clear" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Frame Error Clear" "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Start Clear" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Transmit Disable Clear" "0,1"
newline
bitfld.long 0x0 5. "DELTACTSCLR,Delta CTS Clear" "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Transmit Idle Clear" "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator"
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,Baud Rate Generator Value"
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt Status"
bitfld.long 0x0 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 12. "START,Start Detected on Receiver Flag" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1"
newline
bitfld.long 0x0 5. "DELTACTS,Delta CTS Change Flag" "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle Flag" "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample Selection Register for Asynchronous Communication"
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value"
line.long 0x4 "ADDR,Address Register for Automatic Address Matching"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Address"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied."
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied."
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Triggers DMA for the receive function if the.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function.,1: Triggers DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: Not used,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full.,1: The receive FIFO is full."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty.,1: The receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty.,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt"
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable." "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit FIFO.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will be.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree "USART14"
base ad:0x40126000
group.long 0x0++0xF
line.long 0x0 "CFG,USART Configuration"
bitfld.long 0x0 23. "TXPOL,Transmit data polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 22. "RXPOL,Receive Data Polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x0 21. "OEPOL,Output Enable Polarity" "0: Low. If selected by OESEL the output enable is..,1: High. If selected by OESEL the output enable is.."
newline
bitfld.long 0x0 20. "OESEL,Output Enable Select" "0: Standard. The RTS signal is used as the standard..,1: RS-485. The RTS signal is configured to provide.."
newline
bitfld.long 0x0 19. "AUTOADDR,Automatic Address Matching Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation." "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode"
newline
bitfld.long 0x0 14. "SYNCMST,Synchronous mode Master Select" "0: Slave. When synchronous mode is enabled the..,1: Master. When synchronous mode is enabled the.."
newline
bitfld.long 0x0 12. "CLKPOL,Clock Polarity" "0: Falling edge. RXD is sampled on the falling edge..,1: Rising edge. RXD is sampled on the rising edge.."
newline
bitfld.long 0x0 11. "SYNCEN,Synchronous Enable. Selects synchronous or asynchronous operation." "0: Asynchronous mode,1: Synchronous mode"
newline
bitfld.long 0x0 9. "CTSEN,CTS Enable" "0: No flow control. The transmitter does not..,1: Flow control enabled. The transmitter uses the.."
newline
bitfld.long 0x0 8. "LINMODE,LIN Break Mode Enable" "0: Disabled. Break detect and generate is..,1: Enabled. Break detect and generate is configured.."
newline
bitfld.long 0x0 7. "MODE32K,Mode 32 kHz" "0: Disabled. USART uses standard clocking.,1: Enabled"
newline
bitfld.long 0x0 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits. This setting should be used only.."
newline
bitfld.long 0x0 4.--5. "PARITYSEL,Parity Select. Selects what type of parity is used by the USART." "0: No parity,?,2: Even parity,3: Odd parity"
newline
bitfld.long 0x0 2.--3. "DATALEN,Data Length. Selects the data size for the USART." "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length. The 9th bit is commonly used..,?"
newline
bitfld.long 0x0 0. "ENABLE,USART Enable" "0: Disabled,1: Enabled. The USART is enabled for operation."
line.long 0x4 "CTL,USART Control"
bitfld.long 0x4 16. "AUTOBAUD,Autobaud Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x4 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect. No effect on the CC bit.,1: Auto-clear"
newline
bitfld.long 0x4 8. "CC,Continuous Clock Generation" "0: Clock on character,1: Continuous clock"
newline
bitfld.long 0x4 6. "TXDIS,Transmit Disable" "0: Not disabled. USART transmitter is not disabled.,1: Disabled. USART transmitter is disabled after.."
newline
bitfld.long 0x4 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled. The USART presents all incoming data.,1: Enabled"
newline
bitfld.long 0x4 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
line.long 0x8 "STAT,USART Status"
eventfld.long 0x8 16. "ABERR,Auto Baud Error" "0,1"
newline
eventfld.long 0x8 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
eventfld.long 0x8 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
eventfld.long 0x8 12. "START,Start" "0,1"
newline
eventfld.long 0x8 11. "DELTARXBRK,Delta Received Break" "0,1"
newline
rbitfld.long 0x8 10. "RXBRK,Received Break" "0,1"
newline
rbitfld.long 0x8 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle. Indicates that the USART transmitter..,1: Idle. Indicates that the USART transmitter is.."
newline
eventfld.long 0x8 5. "DELTACTS,Delta CTS" "0,1"
newline
rbitfld.long 0x8 4. "CTS,CTS value" "0,1"
newline
rbitfld.long 0x8 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data.,1: The transmitter is not currently sending data."
newline
rbitfld.long 0x8 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data.,1: The receiver is not currently receiving data."
line.long 0xC "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status"
bitfld.long 0xC 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.."
newline
bitfld.long 0xC 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected. See.."
newline
bitfld.long 0xC 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.."
newline
bitfld.long 0xC 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.."
newline
bitfld.long 0xC 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start bit.."
newline
bitfld.long 0xC 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: Enable"
newline
bitfld.long 0xC 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.."
newline
bitfld.long 0xC 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change in.."
newline
bitfld.long 0xC 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.."
wgroup.long 0x10++0x3
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
bitfld.long 0x0 16. "ABERRCLR,Auto Baud Error Clear" "0,1"
newline
bitfld.long 0x0 15. "RXNOISECLR,Receive Noise Clear" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRCLR,Parity Error Clear" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRCLR,Frame Error Clear" "0,1"
newline
bitfld.long 0x0 12. "STARTCLR,Start Clear" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1"
newline
bitfld.long 0x0 6. "TXDISCLR,Transmit Disable Clear" "0,1"
newline
bitfld.long 0x0 5. "DELTACTSCLR,Delta CTS Clear" "0,1"
newline
bitfld.long 0x0 3. "TXIDLECLR,Transmit Idle Clear" "0,1"
group.long 0x20++0x3
line.long 0x0 "BRG,Baud Rate Generator"
hexmask.long.word 0x0 0.--15. 1. "BRGVAL,Baud Rate Generator Value"
rgroup.long 0x24++0x3
line.long 0x0 "INTSTAT,Interrupt Status"
bitfld.long 0x0 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1"
newline
bitfld.long 0x0 12. "START,Start Detected on Receiver Flag" "0,1"
newline
bitfld.long 0x0 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1"
newline
bitfld.long 0x0 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1"
newline
bitfld.long 0x0 5. "DELTACTS,Delta CTS Change Flag" "0,1"
newline
bitfld.long 0x0 3. "TXIDLE,Transmitter Idle Flag" "0,1"
group.long 0x28++0x7
line.long 0x0 "OSR,Oversample Selection Register for Asynchronous Communication"
hexmask.long.byte 0x0 0.--3. 1. "OSRVAL,Oversample Selection Value"
line.long 0x4 "ADDR,Address Register for Automatic Address Matching"
hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Address"
group.long 0xE00++0xB
line.long 0x0 "FIFOCFG,FIFO Configuration"
bitfld.long 0x0 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO.,1: A debug read will cause the FIFO to pop."
newline
bitfld.long 0x0 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: No effect,1: The RX FIFO is emptied."
newline
bitfld.long 0x0 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: No effect,1: The TX FIFO is emptied."
newline
bitfld.long 0x0 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the device..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x0 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function.,1: Triggers DMA for the receive function if the.."
newline
bitfld.long 0x0 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function.,1: Triggers DMA for the transmit function if the.."
newline
rbitfld.long 0x0 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits.,1: Not used,2: Not used,3: Not used"
newline
bitfld.long 0x0 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled.,1: The receive FIFO is enabled."
newline
bitfld.long 0x0 0. "ENABLETX,Enable the Transmit FIFO." "0: The transmit FIFO is not enabled.,1: The transmit FIFO is enabled."
line.long 0x4 "FIFOSTAT,FIFO Status"
eventfld.long 0x4 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.."
newline
hexmask.long.byte 0x4 16.--20. 1. "RXLVL,Receive FIFO Current Level"
newline
hexmask.long.byte 0x4 8.--12. 1. "TXLVL,Transmit FIFO Current Level"
newline
rbitfld.long 0x4 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full.,1: The receive FIFO is full."
newline
rbitfld.long 0x4 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty.,1: The receive FIFO is not empty so data can be read."
newline
rbitfld.long 0x4 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data can.."
newline
rbitfld.long 0x4 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty.,1: The transmit FIFO is empty although the.."
newline
rbitfld.long 0x4 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt"
newline
bitfld.long 0x4 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused by.."
newline
bitfld.long 0x4 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred.,1: A transmit FIFO error has occurred. This error.."
line.long 0x8 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request"
hexmask.long.byte 0x8 16.--19. 1. "RXLVL,Receive FIFO Level Trigger Point"
newline
hexmask.long.byte 0x8 8.--11. 1. "TXLVL,Transmit FIFO Level Trigger Point"
newline
bitfld.long 0x8 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive FIFO.."
newline
bitfld.long 0x8 0. "TXLVLENA,Transmit FIFO Level Trigger Enable." "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit FIFO.."
group.long 0xE10++0x7
line.long 0x0 "FIFOINTENSET,FIFO Interrupt Enable"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated.,1: Asserts RX interrupt if RX FIFO Timeout event.."
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the RX..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will be.."
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the TX..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt will.."
newline
bitfld.long 0x0 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
newline
bitfld.long 0x0 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a transmit.."
line.long 0x4 "FIFOINTENCLR,FIFO Interrupt Enable Clear"
bitfld.long 0x4 24. "RXTIMEOUT,Receive Timeout" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 1. "RXERR,Receive Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x4 0. "TXERR,Transmit Error Interrupt Enable" "0: No effect,1: Clear the interrupt"
rgroup.long 0xE18++0x3
line.long 0x0 "FIFOINTSTAT,FIFO Interrupt Status"
bitfld.long 0x0 24. "RXTIMEOUT,Receive Timeout Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 4. "PERINT,Peripheral Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 1. "RXERR,RX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
newline
bitfld.long 0x0 0. "TXERR,TX FIFO Error Interrupt Status" "0: Not pending,1: Pending"
wgroup.long 0xE20++0x3
line.long 0x0 "FIFOWR,FIFO Write Data"
hexmask.long.word 0x0 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x3
line.long 0x0 "FIFORD,FIFO Read Data"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE40++0x3
line.long 0x0 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop"
bitfld.long 0x0 15. "RXNOISE,Received Noise Flag" "0,1"
newline
bitfld.long 0x0 14. "PARITYERR,Parity Error Status Flag" "0,1"
newline
bitfld.long 0x0 13. "FRAMERR,Framing Error Status Flag" "0,1"
newline
hexmask.long.word 0x0 0.--8. 1. "RXDATA,Received Data from the FIFO"
rgroup.long 0xE48++0x3
line.long 0x0 "FIFOSIZE,FIFO Size"
hexmask.long.byte 0x0 0.--4. 1. "FIFOSIZE,FIFO Size"
group.long 0xE4C++0x3
line.long 0x0 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration"
bitfld.long 0x0 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the RX.."
newline
bitfld.long 0x0 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time data..,1: RX FIFO timeout counter is not reset every time.."
newline
bitfld.long 0x0 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout"
newline
hexmask.long.word 0x0 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value"
newline
hexmask.long.byte 0x0 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler"
rgroup.long 0xE50++0x3
line.long 0x0 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter"
hexmask.long.word 0x0 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value"
rgroup.long 0xFFC++0x3
line.long 0x0 "ID,Peripheral Identification"
hexmask.long.word 0x0 16.--31. 1. "ID,Module identifier for the selected function"
newline
hexmask.long.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision of module implementation"
newline
hexmask.long.byte 0x0 8.--11. 1. "MINOR_REV,Minor revision of module implementation"
newline
hexmask.long.byte 0x0 0.--7. 1. "APERTURE,Aperture"
tree.end
tree.end
tree "USBC (Universal Serial Bus Controller)"
base ad:0x40145000
rgroup.long 0x0++0x17
line.long 0x0 "ID,ID"
bitfld.long 0x0 29.--31. "CIVERSION,CIVERSION" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 25.--28. 1. "VERSION,VERSION"
hexmask.long.byte 0x0 21.--24. 1. "REVISION,REVISION"
newline
hexmask.long.byte 0x0 16.--20. 1. "TAG,TAG"
bitfld.long 0x0 14.--15. "UNUSED_14,UNUSED_14" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "NID,NID"
newline
bitfld.long 0x0 6.--7. "UNUSED_6,UNUSED_6" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "ID,ID"
line.long 0x4 "HWGENERAL,HWGENERAL"
hexmask.long.tbyte 0x4 12.--31. 1. "UNUSED_12,UNUSED_12"
bitfld.long 0x4 10.--11. "SM,SM" "0,1,2,3"
hexmask.long.byte 0x4 6.--9. 1. "PHYM,PHYM"
newline
bitfld.long 0x4 4.--5. "PHYW,PHYW" "0,1,2,3"
bitfld.long 0x4 3. "BWT,BWT" "0,1"
bitfld.long 0x4 1.--2. "CLKC,CLKC" "0,1,2,3"
newline
bitfld.long 0x4 0. "RT,RT" "0,1"
line.long 0x8 "HWHOST,HWHOST"
hexmask.long.byte 0x8 24.--31. 1. "TTPER,TTPER"
hexmask.long.byte 0x8 16.--23. 1. "TTASY,TTASY"
hexmask.long.word 0x8 4.--15. 1. "UNUSED_4,UNUSED_4"
newline
bitfld.long 0x8 1.--3. "NPORT,NPORT" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 0. "HC,HC" "0,1"
line.long 0xC "HWDEVICE,HWDEVICE"
hexmask.long 0xC 6.--31. 1. "UNUSED_6,UNUSED_6"
hexmask.long.byte 0xC 1.--5. 1. "DEVEP,DEVEP"
bitfld.long 0xC 0. "DC,DC" "0,1"
line.long 0x10 "HWTXBUF,HWTXBUF"
bitfld.long 0x10 31. "UNUSED_31,UNUSED_31" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "UNUSED_24,UNUSED_24"
hexmask.long.byte 0x10 16.--23. 1. "TXCHANADD,TXCHANADD"
newline
hexmask.long.byte 0x10 8.--15. 1. "TXADD,TXADD"
hexmask.long.byte 0x10 0.--7. 1. "TXBURST,TXBURST"
line.long 0x14 "HWRXBUF,HWRXBUF"
hexmask.long.word 0x14 16.--31. 1. "UNUSED_16,UNUSED_16"
hexmask.long.byte 0x14 8.--15. 1. "RXADD,RXADD"
hexmask.long.byte 0x14 0.--7. 1. "RXBURST,RXBURST"
group.long 0x18++0x7
line.long 0x0 "HWTXBUF0,HWTXBUF0"
hexmask.long 0x0 0.--31. 1. "TXBURST,TXBURST"
line.long 0x4 "HWTXBUF1,HWTXBUF1"
hexmask.long 0x4 0.--31. 1. "TXBURST,TXBURST"
group.long 0x80++0x13
line.long 0x0 "GPTIMER0LD,GPTIMER0LD"
hexmask.long.byte 0x0 24.--31. 1. "UNUSED_24,UNUSED_24"
hexmask.long.tbyte 0x0 0.--23. 1. "GPTLD,GPTLD"
line.long 0x4 "GPTIMER0CTRL,GPTIMER0CTRL"
bitfld.long 0x4 31. "GPTRUN,GPTRUN" "0,1"
rbitfld.long 0x4 30. "GPTRST,GPTRST" "0,1"
hexmask.long.byte 0x4 25.--29. 1. "UNUSED_25,UNUSED_25"
newline
bitfld.long 0x4 24. "GPTMODE,GPTMODE" "0,1"
hexmask.long.tbyte 0x4 0.--23. 1. "GPTCNT,GPTCNT"
line.long 0x8 "GPTTIMER1LD,GPTTIMER1LD"
hexmask.long.byte 0x8 24.--31. 1. "UNUSED_24,UNUSED_24"
hexmask.long.tbyte 0x8 0.--23. 1. "GPTLD,GPTLD"
line.long 0xC "GPTIMER1CTRL,GPTIMER1CTRL"
bitfld.long 0xC 31. "GPTRUN,GPTRUN" "0,1"
rbitfld.long 0xC 30. "GPTRST,GPTRST" "0,1"
hexmask.long.byte 0xC 25.--29. 1. "UNUSED_25,UNUSED_25"
newline
bitfld.long 0xC 24. "GPTMODE,GPTMODE" "0,1"
hexmask.long.tbyte 0xC 0.--23. 1. "GPTCNT,GPTCNT"
line.long 0x10 "SBUSCFG,SBUSCFG"
hexmask.long 0x10 3.--31. 1. "UNUSED_3,UNUSED_3"
bitfld.long 0x10 0.--2. "AHBBRST,AHBBRST" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0xB
line.long 0x0 "CAPLENGTH,CAPLENGTH"
hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,HCIVERSION"
hexmask.long.byte 0x0 8.--15. 1. "UNUSED_8,UNUSED_8"
hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,CAPLENGTH"
line.long 0x4 "HCSPARAMS,HCSPARAMS"
hexmask.long.byte 0x4 28.--31. 1. "UNUSED_28,UNUSED_28"
hexmask.long.byte 0x4 24.--27. 1. "N_TT,N_TT"
hexmask.long.byte 0x4 20.--23. 1. "N_PTT,N_PTT"
newline
bitfld.long 0x4 17.--19. "UNUSED_17,UNUSED_17" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16. "PI,PI" "0,1"
hexmask.long.byte 0x4 12.--15. 1. "N_CC,N_CC"
newline
hexmask.long.byte 0x4 8.--11. 1. "N_PCC,N_PCC"
bitfld.long 0x4 5.--7. "UNUSED_5,UNUSED_5" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4. "PPC,PPC" "0,1"
newline
hexmask.long.byte 0x4 0.--3. 1. "N_PORTS,N_PORTS"
line.long 0x8 "HCCPARAMS,HCCPARAMS"
hexmask.long.word 0x8 16.--31. 1. "UNUSED_16,UNUSED_16"
hexmask.long.byte 0x8 8.--15. 1. "EECP,EECP"
hexmask.long.byte 0x8 4.--7. 1. "IST,IST"
newline
bitfld.long 0x8 3. "UNUSED_3,UNUSED_3" "0,1"
bitfld.long 0x8 2. "ASP,ASP" "0,1"
bitfld.long 0x8 1. "PFL,PFL" "0,1"
newline
bitfld.long 0x8 0. "ADC,ADC" "0,1"
rgroup.long 0x120++0x7
line.long 0x0 "DCIVERSION,DCIVERSION"
hexmask.long.word 0x0 16.--31. 1. "UNUSED_16,UNUSED_16"
hexmask.long.word 0x0 0.--15. 1. "DCIVERSION,DCIVERSION"
line.long 0x4 "DCCPARAMS,DCCPARAMS"
bitfld.long 0x4 31. "LPM_EN,LPM_EN" "0,1"
hexmask.long.tbyte 0x4 9.--30. 1. "UNUSED_9,UNUSED_9"
bitfld.long 0x4 8. "HC,HC" "0,1"
newline
bitfld.long 0x4 7. "DC,DC" "0,1"
bitfld.long 0x4 5.--6. "UNUSED_5,UNUSED_5" "0,1,2,3"
hexmask.long.byte 0x4 0.--4. 1. "DEN,DEN"
group.long 0x128++0x3
line.long 0x0 "DEVLPMCSR,DevLPMCSR"
rbitfld.long 0x0 30.--31. "LPM_RSP,LPM_RSP" "0,1,2,3"
bitfld.long 0x0 29. "LPM_PHCD_ONLY,LPM_PHCD_only" "0,1"
rbitfld.long 0x0 28. "BRMTWAKE,BRMTWAKE" "0,1"
newline
hexmask.long.byte 0x0 24.--27. 1. "LINKSTATE,LINKSTATE"
hexmask.long.byte 0x0 20.--23. 1. "HIRD,HIRD"
rbitfld.long 0x0 18.--19. "UNUSED_18,UNUSED_18" "0,1,2,3"
newline
bitfld.long 0x0 17. "LPM_ANY_EP,LPM_ANY_EP" "0,1"
bitfld.long 0x0 16. "HST_RSM_EN,HST_RSM_EN" "0,1"
bitfld.long 0x0 15. "LPM_ON,LPM_ON" "0,1"
newline
bitfld.long 0x0 14. "ALWAYS_LOG,ALWAYS_LOG" "0,1"
bitfld.long 0x0 13. "MIN_SLP_EN,MIN_SLP_EN" "0,1"
bitfld.long 0x0 12. "STALL_OK,STALL_OK" "0,1"
newline
bitfld.long 0x0 11. "ACK_OK,ACK_OK" "0,1"
bitfld.long 0x0 10. "IE_L1STATE,IE_L1STATE" "0,1"
bitfld.long 0x0 9. "L1STATE,L1STATE" "0,1"
newline
bitfld.long 0x0 8. "RWAKE_EN,RWAKE_EN" "0,1"
bitfld.long 0x0 7. "IE_LPMERR,IE_LPMERR" "0,1"
bitfld.long 0x0 6. "IE_LPMACK,IE_LPMACK" "0,1"
newline
bitfld.long 0x0 5. "IE_LPMPKT,IE_LPMPKT" "0,1"
bitfld.long 0x0 4. "IE_L1RSM,IE_L1RSM" "0,1"
bitfld.long 0x0 3. "INT_LPMERR,INT_LPMERR" "0,1"
newline
bitfld.long 0x0 2. "INT_LPMACK,INT_LPMACK" "0,1"
bitfld.long 0x0 1. "INT_LPMPKT,INT_LPMPKT" "0,1"
bitfld.long 0x0 0. "INT_L1RSM,INT_L1RSM" "0,1"
group.long 0x140++0xF
line.long 0x0 "USBCMD,USBCMD"
hexmask.long.byte 0x0 24.--31. 1. "UNUSED_24,UNUSED_24"
hexmask.long.byte 0x0 16.--23. 1. "ITC,ITC"
bitfld.long 0x0 15. "FS2,HOST only" "0,1"
newline
bitfld.long 0x0 14. "ATDTW,ATDTW" "0,1"
bitfld.long 0x0 13. "SUTW,SUTW" "0,1"
rbitfld.long 0x0 12. "UNUSED_12,UNUSED_12" "0,1"
newline
bitfld.long 0x0 11. "ASPE,HOST only" "0,1"
rbitfld.long 0x0 10. "UNUSED_10,UNUSED_10" "0,1"
bitfld.long 0x0 9. "ASP1,HOST only" "0,1"
newline
bitfld.long 0x0 8. "ASP0,HOST only" "0,1"
rbitfld.long 0x0 7. "LR,LR" "0,1"
bitfld.long 0x0 6. "IAA,HOST only" "0,1"
newline
bitfld.long 0x0 5. "ASE,HOST only" "0,1"
bitfld.long 0x0 4. "PSE,HOST only" "0,1"
bitfld.long 0x0 3. "FS1,HOST only" "0,1"
newline
bitfld.long 0x0 2. "FS0,HOST only" "0,1"
bitfld.long 0x0 1. "RST,RST" "0,1"
bitfld.long 0x0 0. "RS,RS" "0,1"
line.long 0x4 "USBSTS,USBSTS"
hexmask.long.byte 0x4 26.--31. 1. "UNUSED_26,UNUSED_26"
bitfld.long 0x4 25. "TI1,rwc" "0,1"
bitfld.long 0x4 24. "TI0,rwc" "0,1"
newline
hexmask.long.byte 0x4 20.--23. 1. "UNUSED_20,UNUSED_20"
bitfld.long 0x4 19. "UPI,rwc" "0,1"
bitfld.long 0x4 18. "UAI,rwc" "0,1"
newline
rbitfld.long 0x4 17. "UNUSED_17,UNUSED_17" "0,1"
rbitfld.long 0x4 16. "NAKI,NAKI" "0,1"
rbitfld.long 0x4 15. "AS,AS" "0,1"
newline
rbitfld.long 0x4 14. "PS,PS" "0,1"
rbitfld.long 0x4 13. "RCL,RCL" "0,1"
rbitfld.long 0x4 12. "HCH,HOST only" "0,1"
newline
rbitfld.long 0x4 11. "UNUSED_11,UNUSED_11" "0,1"
bitfld.long 0x4 10. "ULPII,rwc" "0,1"
rbitfld.long 0x4 9. "UNUSED_9,UNUSED_9" "0,1"
newline
bitfld.long 0x4 8. "SLI,rwc" "0,1"
bitfld.long 0x4 7. "SRI,rwc" "0,1"
bitfld.long 0x4 6. "URI,rwc" "0,1"
newline
bitfld.long 0x4 5. "AAI,rwc" "0,1"
bitfld.long 0x4 4. "SEI,rwc" "0,1"
bitfld.long 0x4 3. "FRI,rwc" "0,1"
newline
bitfld.long 0x4 2. "PCI,rwc" "0,1"
bitfld.long 0x4 1. "UEI,rwc" "0,1"
bitfld.long 0x4 0. "UI,rwc" "0,1"
line.long 0x8 "USBINTR,USBINTR"
hexmask.long.byte 0x8 26.--31. 1. "UNUSED_26,UNUSED_26"
bitfld.long 0x8 25. "TIE1,TIE1" "0,1"
bitfld.long 0x8 24. "TIE0,TIE0" "0,1"
newline
hexmask.long.byte 0x8 20.--23. 1. "UNUSED_20,UNUSED_20"
bitfld.long 0x8 19. "UPE,Not use in Device mode" "0,1"
bitfld.long 0x8 18. "UAE,Not use in Device mode" "0,1"
newline
rbitfld.long 0x8 17. "UNUSED_17,UNUSED_17" "0,1"
rbitfld.long 0x8 16. "NAKE,NAKE" "0,1"
rbitfld.long 0x8 15. "UNUSED_15,Not define in DUT AS" "0,1"
newline
rbitfld.long 0x8 14. "UNUSED_14,Not define in DUT PS" "0,1"
rbitfld.long 0x8 13. "UNUSED_13,Not define in DUT RCL" "0,1"
rbitfld.long 0x8 12. "UNUSED_12,UNUSED_12" "0,1"
newline
rbitfld.long 0x8 11. "UNUSED_11,UNUSED_11" "0,1"
bitfld.long 0x8 10. "ULPE,ONLY used VUSB_HS_PHY_ULPI =1" "0,1"
rbitfld.long 0x8 9. "UNUSED_9,UNUSED_9" "0,1"
newline
bitfld.long 0x8 8. "SLE,SLE" "0,1"
bitfld.long 0x8 7. "SRE,SRE" "0,1"
bitfld.long 0x8 6. "URE,URE" "0,1"
newline
bitfld.long 0x8 5. "AAE,HOST only" "0,1"
bitfld.long 0x8 4. "SEE,SEE" "0,1"
bitfld.long 0x8 3. "FRE,HOST only" "0,1"
newline
bitfld.long 0x8 2. "PCE,PCE" "0,1"
bitfld.long 0x8 1. "UEE,rwc" "0,1"
bitfld.long 0x8 0. "UE,UE" "0,1"
line.long 0xC "FRINDEX,FRINDEX"
hexmask.long.tbyte 0xC 14.--31. 1. "UNUSED_14,UNUSED_14"
hexmask.long.word 0xC 0.--13. 1. "FRINDEX,device RO Host RW"
group.long 0x154++0x3
line.long 0x0 "DEVICEADDR,DEVICEADDR"
hexmask.long.byte 0x0 25.--31. 1. "USBADR,USBADR"
bitfld.long 0x0 24. "USBADRA,USBADRA" "0,1"
group.long 0x154++0x7
line.long 0x0 "PERIODICLISTBASE,PERIODICLISTBASE"
hexmask.long.tbyte 0x0 12.--31. 1. "PERBASE,PERBASE"
line.long 0x4 "ASYNCLISTADDR,ASYNCLISTADDR"
hexmask.long 0x4 5.--31. 1. "ASYBASE,ASYBASE"
group.long 0x158++0x1B
line.long 0x0 "ENDPOINTLISTADDR,ENDPOINTLISTADDR"
hexmask.long.tbyte 0x0 11.--31. 1. "EPBASE,EPBASE"
line.long 0x4 "TTCTRL,TTCTRL"
rbitfld.long 0x4 31. "UNUSED_31,UNUSED_31" "0,1"
hexmask.long.byte 0x4 24.--30. 1. "TTHA,TTHA"
hexmask.long.tbyte 0x4 2.--23. 1. "UNUSED_2,UNUSED_2"
newline
bitfld.long 0x4 1. "TTAC,TTAC" "0,1"
rbitfld.long 0x4 0. "TTAS,TTAS" "0,1"
line.long 0x8 "BURSTSIZE,BURSTSIZE"
hexmask.long.word 0x8 16.--31. 1. "UNUSED_16,UNUSED_16"
hexmask.long.byte 0x8 8.--15. 1. "TXPBURST,TXPBURST"
hexmask.long.byte 0x8 0.--7. 1. "RXPBURST,RXPBURST"
line.long 0xC "TXFILLTUNING,TXFILLTUNING"
hexmask.long.word 0xC 22.--31. 1. "UNUSED_22,UNUSED_22"
hexmask.long.byte 0xC 16.--21. 1. "TXFIFOTHRES,Only use in HOST & MPH mode"
rbitfld.long 0xC 13.--15. "UNUSED_13,UNUSED_13" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 8.--12. 1. "TXSCHHEALTH,Only use in HOST & MPH mode rwc"
rbitfld.long 0xC 7. "UNUSED_7,UNUSED_7" "0,1"
hexmask.long.byte 0xC 0.--6. 1. "TXSCHOH,Only use in HOST & MPH mode"
line.long 0x10 "TXTTFILLTUNING,TXTTFILLTUNING"
hexmask.long.tbyte 0x10 13.--31. 1. "UNUSED_13,UNUSED_13"
hexmask.long.byte 0x10 8.--12. 1. "TXTTSCHHEALTJ,Only use in HOST & MPH mode rwc"
rbitfld.long 0x10 5.--7. "UNUSED_5,UNUSED_5" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 0.--4. 1. "TXTTSCHOH,Only use in HOST & MPH mode"
line.long 0x14 "IC_USB,IC_USB"
bitfld.long 0x14 31. "IC8,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
bitfld.long 0x14 28.--30. "IC_VDD8,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 27. "IC7,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
newline
bitfld.long 0x14 24.--26. "IC_VDD7,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 23. "IC6,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
bitfld.long 0x14 20.--22. "IC_VDD6,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 19. "IC5,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
bitfld.long 0x14 16.--18. "IC_VDD5,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 15. "IC4,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
newline
bitfld.long 0x14 12.--14. "IC_VDD4,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 11. "IC3,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
bitfld.long 0x14 8.--10. "IC_VDD3,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 7. "IC2,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
bitfld.long 0x14 4.--6. "IC_VDD2,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 3. "IC1,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1"
newline
bitfld.long 0x14 0.--2. "IC_VDD1,available in MPH & VUSB_HS_PHY_IC_USB =1" "0,1,2,3,4,5,6,7"
line.long 0x18 "ULPI_VIEWPORT,ULPI_VIEWPORT"
bitfld.long 0x18 31. "ULPIWU,Not available" "0,1"
bitfld.long 0x18 30. "ULPIRUN,Not available" "0,1"
bitfld.long 0x18 29. "ULPIRW,Not available" "0,1"
newline
rbitfld.long 0x18 28. "UNUSED_28,Not available" "0,1"
bitfld.long 0x18 27. "ULPISS,Not available" "0,1"
bitfld.long 0x18 24.--26. "ULPIPORT,Not available" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 16.--23. 1. "ULPIADDR,Not available"
hexmask.long.byte 0x18 8.--15. 1. "ULPIDATRD,Not available"
hexmask.long.byte 0x18 0.--7. 1. "ULPIDATWR,Not available"
group.long 0x178++0x7
line.long 0x0 "ENDPTNAK,ENDPTNAK"
hexmask.long.word 0x0 16.--31. 1. "EPTN,rwc"
hexmask.long.word 0x0 0.--15. 1. "EPRN,rwc"
line.long 0x4 "ENDPTNAKEN,ENDPTNAKEN"
hexmask.long.word 0x4 16.--31. 1. "EPTNE,Only 3 PHY max"
hexmask.long.word 0x4 0.--15. 1. "EPRNE,Only 3 PHY max"
group.long 0x184++0x33
line.long 0x0 "PORTSC1,PORTSC1"
bitfld.long 0x0 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x0 29. "STS,STS" "0,1"
bitfld.long 0x0 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x0 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x0 25. "PTS2,PTS2" "0,1"
bitfld.long 0x0 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x0 23. "PHCD,PHCD" "0,1"
bitfld.long 0x0 22. "WKOC,WKOC" "0,1"
bitfld.long 0x0 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x0 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x0 16.--19. 1. "PTC,PTC"
bitfld.long 0x0 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x0 13. "PO,PO" "0,1"
bitfld.long 0x0 12. "PP,PP" "0,1"
rbitfld.long 0x0 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x0 9. "HSP,HSP" "0,1"
bitfld.long 0x0 8. "PR,PR" "0,1"
bitfld.long 0x0 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x0 6. "FPR,FPR" "0,1"
bitfld.long 0x0 5. "OCC,OCC" "0,1"
rbitfld.long 0x0 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x0 3. "PEC,rwc" "0,1"
rbitfld.long 0x0 2. "PE,rwc" "0,1"
rbitfld.long 0x0 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x0 0. "CCS,CCS" "0,1"
line.long 0x4 "PORTSC2,PORTSC2"
bitfld.long 0x4 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x4 29. "STS,STS" "0,1"
bitfld.long 0x4 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x4 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x4 25. "PTS2,PTS2" "0,1"
bitfld.long 0x4 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x4 23. "PHCD,PHCD" "0,1"
bitfld.long 0x4 22. "WKOC,WKOC" "0,1"
bitfld.long 0x4 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x4 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x4 16.--19. 1. "PTC,PTC"
bitfld.long 0x4 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x4 13. "PO,PO" "0,1"
bitfld.long 0x4 12. "PP,PP" "0,1"
rbitfld.long 0x4 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x4 9. "HSP,HSP" "0,1"
bitfld.long 0x4 8. "PR,PR" "0,1"
bitfld.long 0x4 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x4 6. "FPR,FPR" "0,1"
bitfld.long 0x4 5. "OCC,OCC" "0,1"
rbitfld.long 0x4 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x4 3. "PEC,rwc" "0,1"
rbitfld.long 0x4 2. "PE,rwc" "0,1"
rbitfld.long 0x4 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x4 0. "CCS,CCS" "0,1"
line.long 0x8 "PORTSC3,PORTSC3"
bitfld.long 0x8 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x8 29. "STS,STS" "0,1"
bitfld.long 0x8 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x8 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x8 25. "PTS2,PTS2" "0,1"
bitfld.long 0x8 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x8 23. "PHCD,PHCD" "0,1"
bitfld.long 0x8 22. "WKOC,WKOC" "0,1"
bitfld.long 0x8 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x8 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x8 16.--19. 1. "PTC,PTC"
bitfld.long 0x8 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x8 13. "PO,PO" "0,1"
bitfld.long 0x8 12. "PP,PP" "0,1"
rbitfld.long 0x8 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x8 9. "HSP,HSP" "0,1"
bitfld.long 0x8 8. "PR,PR" "0,1"
bitfld.long 0x8 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x8 6. "FPR,FPR" "0,1"
bitfld.long 0x8 5. "OCC,OCC" "0,1"
rbitfld.long 0x8 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x8 3. "PEC,rwc" "0,1"
rbitfld.long 0x8 2. "PE,rwc" "0,1"
rbitfld.long 0x8 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x8 0. "CCS,CCS" "0,1"
line.long 0xC "PORTSC4,PORTSC4"
bitfld.long 0xC 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0xC 29. "STS,STS" "0,1"
bitfld.long 0xC 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0xC 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0xC 25. "PTS2,PTS2" "0,1"
bitfld.long 0xC 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0xC 23. "PHCD,PHCD" "0,1"
bitfld.long 0xC 22. "WKOC,WKOC" "0,1"
bitfld.long 0xC 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0xC 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0xC 16.--19. 1. "PTC,PTC"
bitfld.long 0xC 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0xC 13. "PO,PO" "0,1"
bitfld.long 0xC 12. "PP,PP" "0,1"
rbitfld.long 0xC 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0xC 9. "HSP,HSP" "0,1"
bitfld.long 0xC 8. "PR,PR" "0,1"
bitfld.long 0xC 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0xC 6. "FPR,FPR" "0,1"
bitfld.long 0xC 5. "OCC,OCC" "0,1"
rbitfld.long 0xC 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0xC 3. "PEC,rwc" "0,1"
rbitfld.long 0xC 2. "PE,rwc" "0,1"
rbitfld.long 0xC 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0xC 0. "CCS,CCS" "0,1"
line.long 0x10 "PORTSC5,PORTSC5"
bitfld.long 0x10 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x10 29. "STS,STS" "0,1"
bitfld.long 0x10 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x10 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x10 25. "PTS2,PTS2" "0,1"
bitfld.long 0x10 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x10 23. "PHCD,PHCD" "0,1"
bitfld.long 0x10 22. "WKOC,WKOC" "0,1"
bitfld.long 0x10 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x10 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x10 16.--19. 1. "PTC,PTC"
bitfld.long 0x10 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x10 13. "PO,PO" "0,1"
bitfld.long 0x10 12. "PP,PP" "0,1"
rbitfld.long 0x10 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x10 9. "HSP,HSP" "0,1"
bitfld.long 0x10 8. "PR,PR" "0,1"
bitfld.long 0x10 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x10 6. "FPR,FPR" "0,1"
bitfld.long 0x10 5. "OCC,OCC" "0,1"
rbitfld.long 0x10 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x10 3. "PEC,rwc" "0,1"
rbitfld.long 0x10 2. "PE,rwc" "0,1"
rbitfld.long 0x10 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x10 0. "CCS,CCS" "0,1"
line.long 0x14 "PORTSC6,PORTSC6"
bitfld.long 0x14 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x14 29. "STS,STS" "0,1"
bitfld.long 0x14 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x14 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x14 25. "PTS2,PTS2" "0,1"
bitfld.long 0x14 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x14 23. "PHCD,PHCD" "0,1"
bitfld.long 0x14 22. "WKOC,WKOC" "0,1"
bitfld.long 0x14 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x14 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x14 16.--19. 1. "PTC,PTC"
bitfld.long 0x14 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x14 13. "PO,PO" "0,1"
bitfld.long 0x14 12. "PP,PP" "0,1"
rbitfld.long 0x14 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x14 9. "HSP,HSP" "0,1"
bitfld.long 0x14 8. "PR,PR" "0,1"
bitfld.long 0x14 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x14 6. "FPR,FPR" "0,1"
bitfld.long 0x14 5. "OCC,OCC" "0,1"
rbitfld.long 0x14 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x14 3. "PEC,rwc" "0,1"
rbitfld.long 0x14 2. "PE,rwc" "0,1"
rbitfld.long 0x14 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x14 0. "CCS,CCS" "0,1"
line.long 0x18 "PORTSC7,PORTSC7"
bitfld.long 0x18 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x18 29. "STS,STS" "0,1"
bitfld.long 0x18 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x18 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x18 25. "PTS2,PTS2" "0,1"
bitfld.long 0x18 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x18 23. "PHCD,PHCD" "0,1"
bitfld.long 0x18 22. "WKOC,WKOC" "0,1"
bitfld.long 0x18 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x18 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x18 16.--19. 1. "PTC,PTC"
bitfld.long 0x18 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x18 13. "PO,PO" "0,1"
bitfld.long 0x18 12. "PP,PP" "0,1"
rbitfld.long 0x18 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x18 9. "HSP,HSP" "0,1"
bitfld.long 0x18 8. "PR,PR" "0,1"
bitfld.long 0x18 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x18 6. "FPR,FPR" "0,1"
bitfld.long 0x18 5. "OCC,OCC" "0,1"
rbitfld.long 0x18 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x18 3. "PEC,rwc" "0,1"
rbitfld.long 0x18 2. "PE,rwc" "0,1"
rbitfld.long 0x18 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x18 0. "CCS,CCS" "0,1"
line.long 0x1C "PORTSC8,PORTSC8"
bitfld.long 0x1C 30.--31. "PTS,PTS" "0,1,2,3"
bitfld.long 0x1C 29. "STS,STS" "0,1"
bitfld.long 0x1C 28. "PTW,PTW" "0,1"
newline
rbitfld.long 0x1C 26.--27. "PSPD,PSPD" "0,1,2,3"
bitfld.long 0x1C 25. "PTS2,PTS2" "0,1"
bitfld.long 0x1C 24. "PFSC,PFSC" "0,1"
newline
bitfld.long 0x1C 23. "PHCD,PHCD" "0,1"
bitfld.long 0x1C 22. "WKOC,WKOC" "0,1"
bitfld.long 0x1C 21. "WKDS,WKDS" "0,1"
newline
bitfld.long 0x1C 20. "WKCN,WKCN" "0,1"
hexmask.long.byte 0x1C 16.--19. 1. "PTC,PTC"
bitfld.long 0x1C 14.--15. "PIC,PIC" "0,1,2,3"
newline
rbitfld.long 0x1C 13. "PO,PO" "0,1"
bitfld.long 0x1C 12. "PP,PP" "0,1"
rbitfld.long 0x1C 10.--11. "LS,LS" "0,1,2,3"
newline
rbitfld.long 0x1C 9. "HSP,HSP" "0,1"
bitfld.long 0x1C 8. "PR,PR" "0,1"
bitfld.long 0x1C 7. "SUSP,SUSP" "0,1"
newline
bitfld.long 0x1C 6. "FPR,FPR" "0,1"
bitfld.long 0x1C 5. "OCC,OCC" "0,1"
rbitfld.long 0x1C 4. "OCA,OCA" "0,1"
newline
rbitfld.long 0x1C 3. "PEC,rwc" "0,1"
rbitfld.long 0x1C 2. "PE,rwc" "0,1"
rbitfld.long 0x1C 1. "CSC,rwc" "0,1"
newline
rbitfld.long 0x1C 0. "CCS,CCS" "0,1"
line.long 0x20 "OTGSC,OTGSC"
rbitfld.long 0x20 31. "UNUSED_31,OTG not enable" "0,1"
bitfld.long 0x20 30. "DPIE,OTG not enable" "0,1"
bitfld.long 0x20 29. "OTGSC_1MSE,OTG not enable" "0,1"
newline
bitfld.long 0x20 28. "BSEIE,OTG not enable" "0,1"
bitfld.long 0x20 27. "BSVIE,OTG not enable" "0,1"
bitfld.long 0x20 26. "ASVIE,OTG not enable" "0,1"
newline
bitfld.long 0x20 25. "AVVIE,OTG not enable" "0,1"
bitfld.long 0x20 24. "IDIE,OTG not enable" "0,1"
rbitfld.long 0x20 23. "UNUSED_23,OTG not enable" "0,1"
newline
rbitfld.long 0x20 22. "DPIS,rwc" "0,1"
rbitfld.long 0x20 21. "OTGSC_1MSS,rwc" "0,1"
rbitfld.long 0x20 20. "BSEIS,rwc" "0,1"
newline
rbitfld.long 0x20 19. "BSVIS,rwc" "0,1"
rbitfld.long 0x20 18. "ASVIS,rwc" "0,1"
rbitfld.long 0x20 17. "AVVIS,rwc" "0,1"
newline
rbitfld.long 0x20 16. "IDIS,rwc" "0,1"
rbitfld.long 0x20 15. "UNUSED_15,OTG not enable" "0,1"
rbitfld.long 0x20 14. "DPS,OTG not enable" "0,1"
newline
rbitfld.long 0x20 13. "OTGSC_1MST,OTG not enable" "0,1"
rbitfld.long 0x20 12. "BSE,OTG not enable" "0,1"
rbitfld.long 0x20 11. "BSV,OTG not enable" "0,1"
newline
rbitfld.long 0x20 10. "ASV,OTG not enable" "0,1"
rbitfld.long 0x20 9. "AVV,OTG not enable" "0,1"
rbitfld.long 0x20 8. "ID,OTG not enable" "0,1"
newline
bitfld.long 0x20 7. "HABA,OTG not enable" "0,1"
bitfld.long 0x20 6. "HADP,OTG not enable" "0,1"
bitfld.long 0x20 5. "IDPU,OTG not enable" "0,1"
newline
bitfld.long 0x20 4. "DP,OTG not enable" "0,1"
bitfld.long 0x20 3. "OT,OTG not enable" "0,1"
bitfld.long 0x20 2. "HAAR,OTG not enable" "0,1"
newline
bitfld.long 0x20 1. "VC,OTG not enable" "0,1"
bitfld.long 0x20 0. "VD,OTG not enable" "0,1"
line.long 0x24 "USBMODE,USBMODE"
hexmask.long.word 0x24 16.--31. 1. "UNUSED_16,UNUSED_16"
bitfld.long 0x24 15. "SRT,SRT" "0,1"
bitfld.long 0x24 12.--14. "TXHSD,TXHSD" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x24 6.--11. 1. "UNUSED_6,UNUSED_6"
bitfld.long 0x24 5. "VBPS,Only used in Host" "0,1"
bitfld.long 0x24 4. "SDIS,SDIS" "0,1"
newline
bitfld.long 0x24 3. "SLOM,SLOM" "0,1"
bitfld.long 0x24 2. "ES,ES" "0,1"
bitfld.long 0x24 0.--1. "CM,fix device mode" "0,1,2,3"
line.long 0x28 "ENDPTSETUPSTAT,ENDPTSETUPSTAT"
hexmask.long.word 0x28 16.--31. 1. "UNUSED_16,UNUSED_16"
hexmask.long.word 0x28 0.--15. 1. "ENDPTSETUPSTAT,rwc"
line.long 0x2C "ENDPTPRIME,ENDPTPRIME"
hexmask.long.word 0x2C 16.--31. 1. "PETB,rws"
hexmask.long.word 0x2C 0.--15. 1. "PERB,rws"
line.long 0x30 "ENDPTFLUSH,ENDPTFLUSH"
hexmask.long.word 0x30 16.--31. 1. "FETB,rws"
hexmask.long.word 0x30 0.--15. 1. "FERB,rws"
rgroup.long 0x1B8++0x3
line.long 0x0 "ENDPTSTAT,ENDPTSTAT"
hexmask.long.word 0x0 16.--31. 1. "ETBR,ETBR"
hexmask.long.word 0x0 0.--15. 1. "ERBR,ERBR"
group.long 0x1BC++0x53
line.long 0x0 "ENDPTCOMPLETE,ENDPTCOMPLETE"
hexmask.long.word 0x0 16.--31. 1. "ETCE,rwc"
hexmask.long.word 0x0 0.--15. 1. "ERCE,rwc"
line.long 0x4 "ENDPTCTRL0,ENDPTCTRL0"
hexmask.long.byte 0x4 24.--31. 1. "UNUSED_24,UNUSED_24"
rbitfld.long 0x4 23. "TXE,TXE" "0,1"
rbitfld.long 0x4 20.--22. "UNUSED_20,UNUSED_20" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 18.--19. "TXT,TXT" "0,1,2,3"
rbitfld.long 0x4 17. "UNUSED_17,UNUSED_17" "0,1"
bitfld.long 0x4 16. "TXS,TXS" "0,1"
newline
hexmask.long.byte 0x4 8.--15. 1. "UNUSED_8,UNUSED_8"
rbitfld.long 0x4 7. "RXE,RXE" "0,1"
rbitfld.long 0x4 4.--6. "UNUSED_4,UNUSED_4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 2.--3. "RXT,RXT" "0,1,2,3"
rbitfld.long 0x4 1. "UNUSED_1,UNUSED_1" "0,1"
bitfld.long 0x4 0. "RXS,RXS" "0,1"
line.long 0x8 "ENDPTCTRL1,ENDPTCTRL1"
hexmask.long.byte 0x8 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x8 23. "TXE,TXE" "0,1"
rbitfld.long 0x8 22. "TXR,ws" "0,1"
newline
bitfld.long 0x8 21. "TXI,TXI" "0,1"
rbitfld.long 0x8 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x8 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x8 17. "TXD,TXD" "0,1"
bitfld.long 0x8 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x8 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x8 7. "RXE,RXE" "0,1"
rbitfld.long 0x8 6. "RXR,ws" "0,1"
bitfld.long 0x8 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x8 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x8 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x8 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x8 0. "RXS,RXS" "0,1"
line.long 0xC "ENDPTCTRL2,ENDPTCTRL2"
hexmask.long.byte 0xC 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0xC 23. "TXE,TXE" "0,1"
rbitfld.long 0xC 22. "TXR,ws" "0,1"
newline
bitfld.long 0xC 21. "TXI,TXI" "0,1"
rbitfld.long 0xC 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0xC 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0xC 17. "TXD,TXD" "0,1"
bitfld.long 0xC 16. "TXS,TXS" "0,1"
hexmask.long.byte 0xC 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0xC 7. "RXE,RXE" "0,1"
rbitfld.long 0xC 6. "RXR,ws" "0,1"
bitfld.long 0xC 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0xC 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0xC 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0xC 1. "RXD,RXD" "0,1"
newline
bitfld.long 0xC 0. "RXS,RXS" "0,1"
line.long 0x10 "ENDPTCTRL3,ENDPTCTRL3"
hexmask.long.byte 0x10 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x10 23. "TXE,TXE" "0,1"
rbitfld.long 0x10 22. "TXR,ws" "0,1"
newline
bitfld.long 0x10 21. "TXI,TXI" "0,1"
rbitfld.long 0x10 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x10 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x10 17. "TXD,TXD" "0,1"
bitfld.long 0x10 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x10 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x10 7. "RXE,RXE" "0,1"
rbitfld.long 0x10 6. "RXR,ws" "0,1"
bitfld.long 0x10 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x10 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x10 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x10 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x10 0. "RXS,RXS" "0,1"
line.long 0x14 "ENDPTCTRL4,ENDPTCTRL4"
hexmask.long.byte 0x14 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x14 23. "TXE,TXE" "0,1"
rbitfld.long 0x14 22. "TXR,ws" "0,1"
newline
bitfld.long 0x14 21. "TXI,TXI" "0,1"
rbitfld.long 0x14 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x14 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x14 17. "TXD,TXD" "0,1"
bitfld.long 0x14 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x14 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x14 7. "RXE,RXE" "0,1"
rbitfld.long 0x14 6. "RXR,ws" "0,1"
bitfld.long 0x14 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x14 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x14 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x14 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x14 0. "RXS,RXS" "0,1"
line.long 0x18 "ENDPTCTRL5,ENDPTCTRL5"
hexmask.long.byte 0x18 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x18 23. "TXE,TXE" "0,1"
rbitfld.long 0x18 22. "TXR,ws" "0,1"
newline
bitfld.long 0x18 21. "TXI,TXI" "0,1"
rbitfld.long 0x18 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x18 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x18 17. "TXD,TXD" "0,1"
bitfld.long 0x18 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x18 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x18 7. "RXE,RXE" "0,1"
rbitfld.long 0x18 6. "RXR,ws" "0,1"
bitfld.long 0x18 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x18 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x18 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x18 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x18 0. "RXS,RXS" "0,1"
line.long 0x1C "ENDPTCTRL6,ENDPTCTRL6"
hexmask.long.byte 0x1C 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x1C 23. "TXE,TXE" "0,1"
rbitfld.long 0x1C 22. "TXR,ws" "0,1"
newline
bitfld.long 0x1C 21. "TXI,TXI" "0,1"
rbitfld.long 0x1C 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x1C 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x1C 17. "TXD,TXD" "0,1"
bitfld.long 0x1C 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x1C 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x1C 7. "RXE,RXE" "0,1"
rbitfld.long 0x1C 6. "RXR,ws" "0,1"
bitfld.long 0x1C 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x1C 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x1C 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x1C 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x1C 0. "RXS,RXS" "0,1"
line.long 0x20 "ENDPTCTRL7,ENDPTCTRL7"
hexmask.long.byte 0x20 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x20 23. "TXE,TXE" "0,1"
rbitfld.long 0x20 22. "TXR,ws" "0,1"
newline
bitfld.long 0x20 21. "TXI,TXI" "0,1"
rbitfld.long 0x20 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x20 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x20 17. "TXD,TXD" "0,1"
bitfld.long 0x20 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x20 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x20 7. "RXE,RXE" "0,1"
rbitfld.long 0x20 6. "RXR,ws" "0,1"
bitfld.long 0x20 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x20 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x20 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x20 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x20 0. "RXS,RXS" "0,1"
line.long 0x24 "ENDPTCTRL8,ENDPTCTRL8"
hexmask.long.byte 0x24 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x24 23. "TXE,TXE" "0,1"
rbitfld.long 0x24 22. "TXR,ws" "0,1"
newline
bitfld.long 0x24 21. "TXI,TXI" "0,1"
rbitfld.long 0x24 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x24 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x24 17. "TXD,TXD" "0,1"
bitfld.long 0x24 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x24 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x24 7. "RXE,RXE" "0,1"
rbitfld.long 0x24 6. "RXR,ws" "0,1"
bitfld.long 0x24 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x24 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x24 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x24 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x24 0. "RXS,RXS" "0,1"
line.long 0x28 "ENDPTCTRL9,ENDPTCTRL9"
hexmask.long.byte 0x28 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x28 23. "TXE,TXE" "0,1"
rbitfld.long 0x28 22. "TXR,ws" "0,1"
newline
bitfld.long 0x28 21. "TXI,TXI" "0,1"
rbitfld.long 0x28 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x28 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x28 17. "TXD,TXD" "0,1"
bitfld.long 0x28 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x28 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x28 7. "RXE,RXE" "0,1"
rbitfld.long 0x28 6. "RXR,ws" "0,1"
bitfld.long 0x28 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x28 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x28 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x28 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x28 0. "RXS,RXS" "0,1"
line.long 0x2C "ENDPTCTRL10,ENDPTCTRL10"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x2C 23. "TXE,TXE" "0,1"
rbitfld.long 0x2C 22. "TXR,ws" "0,1"
newline
bitfld.long 0x2C 21. "TXI,TXI" "0,1"
rbitfld.long 0x2C 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x2C 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x2C 17. "TXD,TXD" "0,1"
bitfld.long 0x2C 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x2C 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x2C 7. "RXE,RXE" "0,1"
rbitfld.long 0x2C 6. "RXR,ws" "0,1"
bitfld.long 0x2C 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x2C 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x2C 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x2C 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x2C 0. "RXS,RXS" "0,1"
line.long 0x30 "ENDPTCTRL11,ENDPTCTRL11"
hexmask.long.byte 0x30 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x30 23. "TXE,TXE" "0,1"
rbitfld.long 0x30 22. "TXR,ws" "0,1"
newline
bitfld.long 0x30 21. "TXI,TXI" "0,1"
rbitfld.long 0x30 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x30 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x30 17. "TXD,TXD" "0,1"
bitfld.long 0x30 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x30 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x30 7. "RXE,RXE" "0,1"
rbitfld.long 0x30 6. "RXR,ws" "0,1"
bitfld.long 0x30 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x30 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x30 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x30 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x30 0. "RXS,RXS" "0,1"
line.long 0x34 "ENDPTCTRL12,ENDPTCTRL12"
hexmask.long.byte 0x34 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x34 23. "TXE,TXE" "0,1"
rbitfld.long 0x34 22. "TXR,ws" "0,1"
newline
bitfld.long 0x34 21. "TXI,TXI" "0,1"
rbitfld.long 0x34 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x34 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x34 17. "TXD,TXD" "0,1"
bitfld.long 0x34 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x34 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x34 7. "RXE,RXE" "0,1"
rbitfld.long 0x34 6. "RXR,ws" "0,1"
bitfld.long 0x34 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x34 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x34 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x34 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x34 0. "RXS,RXS" "0,1"
line.long 0x38 "ENDPTCTRL13,ENDPTCTRL13"
hexmask.long.byte 0x38 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x38 23. "TXE,TXE" "0,1"
rbitfld.long 0x38 22. "TXR,ws" "0,1"
newline
bitfld.long 0x38 21. "TXI,TXI" "0,1"
rbitfld.long 0x38 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x38 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x38 17. "TXD,TXD" "0,1"
bitfld.long 0x38 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x38 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x38 7. "RXE,RXE" "0,1"
rbitfld.long 0x38 6. "RXR,ws" "0,1"
bitfld.long 0x38 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x38 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x38 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x38 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x38 0. "RXS,RXS" "0,1"
line.long 0x3C "ENDPTCTRL14,ENDPTCTRL14"
hexmask.long.byte 0x3C 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x3C 23. "TXE,TXE" "0,1"
rbitfld.long 0x3C 22. "TXR,ws" "0,1"
newline
bitfld.long 0x3C 21. "TXI,TXI" "0,1"
rbitfld.long 0x3C 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x3C 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x3C 17. "TXD,TXD" "0,1"
bitfld.long 0x3C 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x3C 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x3C 7. "RXE,RXE" "0,1"
rbitfld.long 0x3C 6. "RXR,ws" "0,1"
bitfld.long 0x3C 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x3C 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x3C 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x3C 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x3C 0. "RXS,RXS" "0,1"
line.long 0x40 "ENDPTCTRL15,ENDPTCTRL15"
hexmask.long.byte 0x40 24.--31. 1. "UNUSED_24,UNUSED_24"
bitfld.long 0x40 23. "TXE,TXE" "0,1"
rbitfld.long 0x40 22. "TXR,ws" "0,1"
newline
bitfld.long 0x40 21. "TXI,TXI" "0,1"
rbitfld.long 0x40 20. "UNUSED_20,UNUSED_20" "0,1"
bitfld.long 0x40 18.--19. "TXT,TXT" "0,1,2,3"
newline
bitfld.long 0x40 17. "TXD,TXD" "0,1"
bitfld.long 0x40 16. "TXS,TXS" "0,1"
hexmask.long.byte 0x40 8.--15. 1. "UNUSED_8,UNUSED_8"
newline
bitfld.long 0x40 7. "RXE,RXE" "0,1"
rbitfld.long 0x40 6. "RXR,ws" "0,1"
bitfld.long 0x40 5. "RXI,RXI" "0,1"
newline
rbitfld.long 0x40 4. "UNUSED_4,UNUSED_4" "0,1"
bitfld.long 0x40 2.--3. "RXT,RXT" "0,1,2,3"
bitfld.long 0x40 1. "RXD,RXD" "0,1"
newline
bitfld.long 0x40 0. "RXS,RXS" "0,1"
line.long 0x44 "PLL_CONTROL_0,PLL_Control_0"
rbitfld.long 0x44 31. "PLL_READY,PLL_READY" "0,1"
bitfld.long 0x44 30. "R_ROTATE,R_ROTATE" "0,1"
bitfld.long 0x44 28.--29. "SEL_LPFR,SEL_LPFR" "0,1,2,3"
newline
rbitfld.long 0x44 25.--27. "UNUSED_25,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x44 16.--24. 1. "FBDIV,FBDIV"
bitfld.long 0x44 14.--15. "VDDL,VDDL" "0,1,2,3"
newline
bitfld.long 0x44 12.--13. "VDDM,VDDM" "0,1,2,3"
hexmask.long.byte 0x44 8.--11. 1. "ICP,ICP"
rbitfld.long 0x44 7. "UNUSED_7,Reserved" "0,1"
newline
hexmask.long.byte 0x44 0.--6. 1. "REFDIV,REFDIV"
line.long 0x48 "PLL_CONTROL_1,PLL_Control_1"
hexmask.long.tbyte 0x48 15.--31. 1. "UNUSED_15,Reserved"
bitfld.long 0x48 14. "PLL_STRESS_TEST,PLL_STRESS_TEST" "0,1"
bitfld.long 0x48 13. "CLK_BLK_EN,CLK_BLK_EN" "0,1"
newline
bitfld.long 0x48 12. "REFCLK_SEL,REFCLK_SEL" "0,1"
bitfld.long 0x48 11. "CLK160M_EN,CLK160M_EN" "0,1"
bitfld.long 0x48 10. "TXCLK_EN,TXCLK_EN" "0,1"
newline
rbitfld.long 0x48 8.--9. "UNUSED_8,Reserved" "0,1,2,3"
hexmask.long.byte 0x48 4.--7. 1. "TESTMON_PLL,TESTMON_PLL"
bitfld.long 0x48 3. "PLL_SUSPEND_EN,PLL_SUSPEND_EN" "0,1"
newline
bitfld.long 0x48 2. "PLL_RESET,PLL_RESET" "0,1"
bitfld.long 0x48 1. "PU_PLL_BY_REG,PU_PLL_BY_REG" "0,1"
bitfld.long 0x48 0. "PU_PLL,PU_PLL" "0,1"
line.long 0x4C "CALIBRATION_CONTROL,CALIBRATION_Control"
rbitfld.long 0x4C 31. "PLLCAL_DONE,PLLCAL_DONE" "0,1"
rbitfld.long 0x4C 28.--30. "CURRENT_KVCO,CURRENT_KVCO" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4C 24.--27. 1. "CURRENT_IMP,CURRENT_IMP"
newline
rbitfld.long 0x4C 23. "IMPCAL_DONE,IMPCAL_DONE" "0,1"
bitfld.long 0x4C 22. "PLLCAL_START,PLLCAL_START" "0,1"
bitfld.long 0x4C 20.--21. "PLLCAL,PLLCAL" "0,1,2,3"
newline
bitfld.long 0x4C 19. "KVCO_EXT,KVCO_EXT" "0,1"
bitfld.long 0x4C 16.--18. "KVCO,KVCO" "0,1,2,3,4,5,6,7"
bitfld.long 0x4C 15. "VCOCAL_POL,VCOCAL_POL" "0,1"
newline
bitfld.long 0x4C 14. "IMPCAL_POL,IMPCAL_POL" "0,1"
bitfld.long 0x4C 13. "IMPCAL_START,IMPCAL_START" "0,1"
bitfld.long 0x4C 12. "EXT_RCAL_EN,EXT_RCAL_EN" "0,1"
newline
bitfld.long 0x4C 11. "EXT_FS_IMP_EN,EXT_FS_IMP_EN" "0,1"
bitfld.long 0x4C 8.--10. "IMPCAL_VTH,IMPCAL_VTH" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4C 4.--7. 1. "EXT_RCAL,EXT_RCAL"
newline
hexmask.long.byte 0x4C 0.--3. 1. "EXT_FS_IMP,EXT_FS_IMP"
line.long 0x50 "TX_CHANNEL_CONTRL_0,Tx_Channel_Contrl_0"
hexmask.long.byte 0x50 26.--31. 1. "UNUSED_26,Reserved"
bitfld.long 0x50 25. "PU_BY_REG,PU_BY_REG" "0,1"
bitfld.long 0x50 24. "PU_ANA,PU_ANA" "0,1"
newline
bitfld.long 0x50 23. "PU_VDDR18,PU_VDDR18" "0,1"
bitfld.long 0x50 20.--22. "AMP,AMP" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x50 16.--19. 1. "IMP_SEL_LS,IMP_SEL_LS"
newline
hexmask.long.byte 0x50 12.--15. 1. "DRV_EN_LS,DRV_EN_LS"
hexmask.long.byte 0x50 8.--11. 1. "FSDRV_EN,FSDRV_EN"
rbitfld.long 0x50 7. "UNUSED_7,Reserved" "0,1"
newline
bitfld.long 0x50 6. "LOWVDD_EN,LOWVDD_EN" "0,1"
bitfld.long 0x50 4.--5. "HS_SR_SEL,HS_SR_SEL" "0,1,2,3"
hexmask.long.byte 0x50 0.--3. 1. "HSDRV_EN,HSDRV_EN"
rgroup.long 0x210++0x3
line.long 0x0 "TX_CHANNEL_CONTRL_1,Tx_Channel_Contrl_1"
hexmask.long 0x0 0.--31. 1. "UNUSED_0,Reserved"
group.long 0x214++0x27
line.long 0x0 "RX_CHANNEL_CONTRL_0,Rx_Channel_Contrl_0"
rbitfld.long 0x0 30.--31. "UNUSED_30,Reserved" "0,1,2,3"
bitfld.long 0x0 29. "CHIRPMODE_SEL,CHIRPMODE_SEL" "0,1"
bitfld.long 0x0 28. "SQ_ANA_DTC_SEL,SQ_ANA_DTC_SEL" "0,1"
newline
bitfld.long 0x0 26.--27. "SQ_ANA_VREF,SQ_ANA_VREF" "0,1,2,3"
bitfld.long 0x0 25. "RESET_EXT,RESET_EXT" "0,1"
bitfld.long 0x0 24. "RESET_EXT_EN,RESET_EXT_EN" "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "TESTMON,TESTMON"
bitfld.long 0x0 19. "STRESS_TEST_MODE,STRESS_TEST_MODE" "0,1"
rbitfld.long 0x0 17.--18. "UNUSED_17,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 16. "SQ_VHL_SEL,SQ_VHL_SEL" "0,1"
bitfld.long 0x0 15. "SQ_DET_EN,SQ_DET_EN" "0,1"
bitfld.long 0x0 14. "SQ_CM_SEL,SQ_CM_SEL" "0,1"
newline
bitfld.long 0x0 12.--13. "SQ_DLY_SEL,SQ_DLY_SEL" "0,1,2,3"
rbitfld.long 0x0 11. "UNUSED_11,Reserved" "0,1"
bitfld.long 0x0 10. "LINESTATE_EN,LINESTATE_EN" "0,1"
newline
bitfld.long 0x0 8.--9. "DISCON_THRESH,DISCON_THRESH" "0,1,2,3"
bitfld.long 0x0 6.--7. "RXVDDL,RXVDDL" "0,1,2,3"
bitfld.long 0x0 4.--5. "RXVDD18,RXVDD18" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "SQ_THRESH,SQ_THRESH"
line.long 0x4 "RX_CHANNEL_CONTRL_1,Rx_Channel_Contrl_1"
rbitfld.long 0x4 31. "REG_SQCAL_DONE,REG_SQCAL_DONE" "0,1"
hexmask.long.tbyte 0x4 8.--30. 1. "UNUSED_8,Reserved"
bitfld.long 0x4 6.--7. "SQ_DPDM_AMP_SEL,SQ_DPDM_AMP_SEL" "0,1,2,3"
newline
bitfld.long 0x4 5. "REG_SQ_UD_SWAP,REG_SQ_UD_SWAP" "0,1"
bitfld.long 0x4 4. "REQ_SQCAL_START,REQ_SQCAL_START" "0,1"
bitfld.long 0x4 3. "EXT_SQ_AMP_CAL_EN,EXT_SQ_AMP_CAL_EN" "0,1"
newline
bitfld.long 0x4 0.--2. "EXT_SQ_AMP_CAL,EXT_SQ_AMP_CAL" "0,1,2,3,4,5,6,7"
line.long 0x8 "DIGITAL_CONTRL_0,Digital_Contrl_0"
bitfld.long 0x8 31. "BITSTUFFING_ERROR,BITSTUFFING_ERROR" "0,1"
bitfld.long 0x8 30. "LOSS_OF_SYNC_ERROR,LOSS_OF_SYNC_ERROR" "0,1"
bitfld.long 0x8 29. "FIFO_OVF_ERROR,FIFO_OVF_ERROR" "0,1"
newline
bitfld.long 0x8 28. "PLL_LOCK_FORCE_EN,PLL_LOCK_FORCE_EN" "0,1"
bitfld.long 0x8 27. "PLL_LOCK_FORCE_VAL,PLL_LOCK_FORCE_VAL" "0,1"
bitfld.long 0x8 26. "CORE_UTMI_SEL,CORE_UTMI_SEL" "0,1"
newline
bitfld.long 0x8 25. "SE1_FILT_SEL,SE1_FILT_SEL" "0,1"
bitfld.long 0x8 24. "SE0_FILT_SEL,SE0_FILT_SEL" "0,1"
bitfld.long 0x8 23. "EDGE_OPT_EN,EDGE_OPT_EN" "0,1"
newline
bitfld.long 0x8 22. "STOP_AT_RXERR,STOP_AT_RXERR" "0,1"
bitfld.long 0x8 21. "RX_RUNAWAY_EN,RX_RUNAWAY_EN" "0,1"
bitfld.long 0x8 20. "LOSSOFSYNC_EN,LOSSOFSYNC_EN" "0,1"
newline
bitfld.long 0x8 19. "FIFOOVF_EN,FIFOOVF_EN" "0,1"
bitfld.long 0x8 16.--18. "SQ_FILT,SQ_FILT" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 15. "RXFILT3_EN,RXFILT3_EN" "0,1"
newline
bitfld.long 0x8 12.--14. "SQ_BLK,SQ_BLK" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 11. "EARLY_TX_ENABLE,EARLY_TX_ENABLE" "0,1"
bitfld.long 0x8 10. "RXFILT2_EN,RXFILT2_EN" "0,1"
newline
bitfld.long 0x8 9. "RXFILT1_EN,RXFILT1_EN" "0,1"
bitfld.long 0x8 8. "LONG_EOP,LONG_EOP" "0,1"
bitfld.long 0x8 7. "PLL_LOCK_BYPASS,PLL_LOCK_BYPASS" "0,1"
newline
rbitfld.long 0x8 6. "UNUSED_6,Reserved" "0,1"
bitfld.long 0x8 5. "HOST_DISCON_SEL1,HOST_DISCON_SEL1" "0,1"
bitfld.long 0x8 4. "HOST_DISCON_SEL0,HOST_DISCON_SEL0" "0,1"
newline
bitfld.long 0x8 3. "SYNCDET_WINDOW_EN,SYNCDET_WINDOW_EN" "0,1"
bitfld.long 0x8 2. "SYNCDET_WIN32,SYNCDET_WIN32" "0,1"
bitfld.long 0x8 0.--1. "SYNC_NUM,SYNC_NUM" "0,1,2,3"
line.long 0xC "DIGITAL_CONTRL_1,Digital_Contrl_1"
bitfld.long 0xC 31. "REG_VBUSON_SEL_HIGH,REG_VBUSON_SEL_HIGH" "0,1"
bitfld.long 0xC 30. "REG_LSIDLE_PRE,REG_LSIDLE_PRE" "0,1"
hexmask.long.byte 0xC 22.--29. 1. "REG_CLK_OUT_DLY,REG_CLK_OUT_DLY"
newline
bitfld.long 0xC 21. "REG_SAMPLER_PREOFF,REG_SAMPLER_PREOFF" "0,1"
bitfld.long 0xC 20. "REG_SAMPLER_ON,REG_SAMPLER_ON" "0,1"
hexmask.long.byte 0xC 16.--19. 1. "REG_SAMPLEROFF_DLY,REG_SAMPLEROFF_DLY"
newline
bitfld.long 0xC 15. "REG_SWAP_DPDM,REG_SWAP_DPDM" "0,1"
bitfld.long 0xC 14. "REG_LAT_UTMI,REG_LAT_UTMI" "0,1"
bitfld.long 0xC 13. "REG_OPMODE_SEL,REG_OPMODE_SEL" "0,1"
newline
bitfld.long 0xC 12. "REG_FLSMODELP_EN,REG_FLSMODELP_EN" "0,1"
bitfld.long 0xC 11. "REG_FREERUNCLK_EN,REG_FREERUNCLK_EN" "0,1"
bitfld.long 0xC 10. "REG_NOVBUS_DPDM00,REG_NOVBUS_DPDM00" "0,1"
newline
rbitfld.long 0xC 8.--9. "UNUSED_8,Reserved" "0,1,2,3"
bitfld.long 0xC 7. "REG_FS_EOP_MODE,REG_FS_EOP_MODE" "0,1"
bitfld.long 0xC 6. "REG_DP_PULLDOWN,REG_DP_PULLDOWN" "0,1"
newline
bitfld.long 0xC 5. "REG_DM_PULLDOWN,REG_DM_PULLDOWN" "0,1"
bitfld.long 0xC 4. "REG_ARC_DPDM_MODE,REG_ARC_DPDM_MODE" "0,1"
bitfld.long 0xC 3. "REG_FS_RX_ERROR_MODE2,REG_FS_RX_ERROR_MODE2" "0,1"
newline
bitfld.long 0xC 2. "REG_FS_RX_ERROR_MODE1,REG_FS_RX_ERROR_MODE1" "0,1"
bitfld.long 0xC 1. "REG_FS_RX_ERROR_MODE,REG_FS_RX_ERROR_MODE" "0,1"
bitfld.long 0xC 0. "REG_FORCE_END_EN,REG_FORCE_END_EN" "0,1"
line.long 0x10 "TEST_CONTRL_AND_STATUS_0,Test_Contrl_and_Status_0"
rbitfld.long 0x10 31. "TEST_FAIL,TEST_FAIL" "0,1"
rbitfld.long 0x10 30. "TEST_DONE,TEST_DONE" "0,1"
bitfld.long 0x10 29. "REG_TEST_EN,REG_TEST_EN" "0,1"
newline
bitfld.long 0x10 28. "REG_TEST_DIG_LPBK,REG_TEST_DIG_LPBK" "0,1"
bitfld.long 0x10 27. "REG_TEST_ANA_LPBK,REG_TEST_ANA_LPBK" "0,1"
bitfld.long 0x10 26. "REG_TEST_BYPASS,REG_TEST_BYPASS" "0,1"
newline
bitfld.long 0x10 25. "REG_TEST_UTMI_SEL,REG_TEST_UTMI_SEL" "0,1"
rbitfld.long 0x10 24. "UNUSED_24,Reserved" "0,1"
bitfld.long 0x10 23. "REG_TEST_TX_BITSTUFF_EN,REG_TEST_TX_BITSTUFF_EN" "0,1"
newline
bitfld.long 0x10 22. "REG_TEST_SUSPENDM,REG_TEST_SUSPENDM" "0,1"
bitfld.long 0x10 21. "REG_TEST_RESET,REG_TEST_RESET" "0,1"
bitfld.long 0x10 20. "REG_TEST_TERM_SELECT,REG_TEST_TERM_SELECT" "0,1"
newline
bitfld.long 0x10 18.--19. "REG_TEST_XVCR_SELECT,REG_TEST_XVCR_SELECT" "0,1,2,3"
bitfld.long 0x10 16.--17. "REG_TEST_OP_MODE,REG_TEST_OP_MODE" "0,1,2,3"
rbitfld.long 0x10 15. "UNUSED_15,Reserved" "0,1"
newline
bitfld.long 0x10 12.--14. "REG_TEST_SKIP,REG_TEST_SKIP" "0,1,2,3,4,5,6,7"
rbitfld.long 0x10 10.--11. "UNUSED_10,Reserved" "0,1,2,3"
bitfld.long 0x10 8.--9. "REG_TEST_MODE,REG_TEST_MODE" "0,1,2,3"
newline
hexmask.long.byte 0x10 0.--7. 1. "REG_TEST_TX_PATTERN,REG_TEST_TX_PATTERN"
line.long 0x14 "TEST_CONTRL_AND_STATUS_1,Test_Contrl_and_Status_1"
bitfld.long 0x14 31. "FLS_TX_FORCE_EN,fls_tx_force_en" "0,1"
bitfld.long 0x14 30. "FLS_TX_ENABLE,fls_tx_enable" "0,1"
bitfld.long 0x14 29. "FLS_TX_SE0,fls_tx_se0" "0,1"
newline
bitfld.long 0x14 28. "FLS_TX_DAT,fls_tx_dat" "0,1"
bitfld.long 0x14 27. "HS_TX_FORCE_EN,hs_tx_force_en" "0,1"
bitfld.long 0x14 26. "HS_TX_ENABLE,hs_tx_enable" "0,1"
newline
bitfld.long 0x14 25. "HS_TX_DATA,hs_tx_data" "0,1"
bitfld.long 0x14 24. "DOUT_HS_FORCE_EN,dout_hs_force_en" "0,1"
bitfld.long 0x14 23. "DOUT_HS_FORCE_VAL,dout_hs_force_val" "0,1"
newline
bitfld.long 0x14 22. "SQ_FORCE_EN,sq_force_en" "0,1"
bitfld.long 0x14 21. "SQ_FORCE_VAL,sq_force_val" "0,1"
bitfld.long 0x14 20. "DISCON_FORCE_EN,discon_force_en" "0,1"
newline
bitfld.long 0x14 19. "DISCON_FORCE_VAL,discon_force_val" "0,1"
bitfld.long 0x14 18. "LINESTATE_FORCE_EN,linestate_force_en" "0,1"
bitfld.long 0x14 16.--17. "LINESTATE_FORCE_VAL,linestate_force_val" "0,1,2,3"
newline
bitfld.long 0x14 15. "FLS_RX_FORCE_EN,fls_rx_force_en" "0,1"
bitfld.long 0x14 14. "DOUT_FS_LS,dout_fs_ls" "0,1"
bitfld.long 0x14 13. "FLS_RX_P,fls_rx_p" "0,1"
newline
bitfld.long 0x14 12. "FLS_RX_N,fls_rx_n" "0,1"
rbitfld.long 0x14 11. "UNUSED_11,Reserved" "0,1"
hexmask.long.word 0x14 0.--10. 1. "TEST_LEN,TEST_LEN"
line.long 0x18 "MONITOR,MONITOR"
hexmask.long.word 0x18 16.--31. 1. "USB_MON,USB_MON"
hexmask.long.word 0x18 6.--15. 1. "UNUSED_6,Reserved"
hexmask.long.byte 0x18 0.--5. 1. "REG_MON_SEL,REG_MON_SEL"
line.long 0x1C "RESERVE_ANA,PHY_RESERVE"
hexmask.long 0x1C 0.--31. 1. "PHY_RESERVE,PHY_RESERVE"
line.long 0x20 "PHY_REG_OTG_CONTROL,PHY_REG_OTG_CONTROL"
hexmask.long 0x20 7.--31. 1. "UNUSED_7,Reserved"
bitfld.long 0x20 6. "REG_COMP_I_CTRL,REG_COMP_I_CTRL" "0,1"
bitfld.long 0x20 5. "OTG_CONTROL_BY_PIN,OTG_CONTROL_BY_PIN" "0,1"
newline
bitfld.long 0x20 4. "PU_OTG,PU_OTG" "0,1"
rbitfld.long 0x20 3. "UNUSED_3,Reserved" "0,1"
bitfld.long 0x20 0.--2. "TESTMON_OTG,TESTMON_OTG" "0,1,2,3,4,5,6,7"
line.long 0x24 "PHY_REG_CHGDTC_CONTRL_1,PHY_REG_CHGDTC_CONTRL_1"
hexmask.long.tbyte 0x24 14.--31. 1. "UNUSED_14,Reserved"
bitfld.long 0x24 13. "ENABLE_SWITCH_DM,ENABLE_SWITCH_DM" "0,1"
bitfld.long 0x24 12. "ENABLE_SWITCH_DP,ENABLE_SWITCH_DP" "0,1"
newline
bitfld.long 0x24 10.--11. "VSRC_CHARGE,VSRC_CHARGE" "0,1,2,3"
bitfld.long 0x24 8.--9. "VDAT_CHARGE,VDAT_CHARGE" "0,1,2,3"
bitfld.long 0x24 7. "CDP_DM_AUTO_SWITCH,CDP_DM_AUTO_SWITCH" "0,1"
newline
bitfld.long 0x24 6. "DP_DM_SWAP_CTRL,DP_DM_SWAP_CTRL" "0,1"
bitfld.long 0x24 5. "PU_CHRG_DTC,PU_CHRG_DTC" "0,1"
bitfld.long 0x24 4. "PD_EN,PD_EN" "0,1"
newline
bitfld.long 0x24 3. "DCP_EN,DCP_EN" "0,1"
bitfld.long 0x24 2. "CDP_EN,CDP_EN" "0,1"
bitfld.long 0x24 0.--1. "TESTMON_CHRGDTC,TESTMON_CHRGDTC" "0,1,2,3"
rgroup.long 0x24C++0x3
line.long 0x0 "RESERVED,RESERVED"
hexmask.long 0x0 0.--31. 1. "RESERVED,RESERVED"
tree.end
tree "USIM"
base ad:0x40008000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register"
bitfld.long 0x0 8. "PERR,parity error bit -When not masked by the PEM bit in the FCR register the parity error indicator will appear in this bit." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "RB,Data byte received"
wgroup.long 0x4++0x3
line.long 0x0 "THR,Transmit Holding Register"
hexmask.long.byte 0x0 0.--7. 1. "TB,Data byte transmitted leaset significant bit first"
group.long 0x8++0xB
line.long 0x0 "IER,Interrupt Enable Register"
bitfld.long 0x0 15. "DMA_TX,DMA Transmit Request" "0,1"
bitfld.long 0x0 14. "DMA_RX,DMA Receive Request" "0,1"
bitfld.long 0x0 13. "DMA_TIME,DMA Receive Request in event of a Time Out situation" "0,1"
bitfld.long 0x0 10. "CARD_DET,SmartCard detection" "0,1"
bitfld.long 0x0 9. "TDR,Transmitter Data Refill Interrupt" "0,1"
bitfld.long 0x0 8. "RDR,Receiver Data Ready Interrupt" "0,1"
bitfld.long 0x0 6. "BWT,Block Waiting Time Interrupt" "0,1"
newline
bitfld.long 0x0 5. "CWT,Character Waiting Time Interrupt" "0,1"
bitfld.long 0x0 4. "TIMEO,Receiver Time Out Interrupt" "0,1"
bitfld.long 0x0 3. "FRAMERR,Framing Error Interrupt" "0,1"
bitfld.long 0x0 2. "T0ERR,T=0 Error Interrupt" "0,1"
bitfld.long 0x0 1. "PERR,Parity Error Interrupt" "0,1"
bitfld.long 0x0 0. "OVRN,Receiver Dta Overrun Interrupt" "0,1"
line.long 0x4 "IIR,Interrupt Identification Register"
bitfld.long 0x4 10. "CARD_DET,SmartCard detection" "0,1"
rbitfld.long 0x4 9. "TDR,Transmitter Data Refill Interrupt" "0,1"
rbitfld.long 0x4 8. "RDR,Receive Data Ready Interrupt" "0,1"
bitfld.long 0x4 6. "BWT,Block Waiting Time Interrupt" "0,1"
bitfld.long 0x4 5. "CWT,Character Waiting Time Interrupt" "0,1"
rbitfld.long 0x4 4. "TIMEO,Receiver Time Out Interrupt" "0,1"
bitfld.long 0x4 3. "FRAMERR,Framing Error Interrupt" "0,1"
newline
rbitfld.long 0x4 2. "T0ERR,T=0 Error Interrupt" "0,1"
bitfld.long 0x4 1. "PERR,Parity Error Interrupt" "0,1"
bitfld.long 0x4 0. "OVRN,Receiver Data Overrun Interrupt" "0,1"
line.long 0x8 "FCR,FIFO Control Register"
bitfld.long 0x8 8. "TX_TL,Transmitter Trigger Level" "0,1"
bitfld.long 0x8 6.--7. "RX_TL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x8 3. "PEM,Parity Error Mask" "0,1"
bitfld.long 0x8 2. "TX_HOLD,Transmission Hold" "0,1"
bitfld.long 0x8 1. "RESETTF,Reset Transmit FIFO" "0,1"
bitfld.long 0x8 0. "RESETRF,Reset Receive FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "FSR,FIFO Status Register"
hexmask.long.byte 0x0 10.--14. 1. "PERR_NUM,Parity Error Number"
hexmask.long.byte 0x0 5.--9. 1. "TX_LENGTH,Transmit FIFO length"
hexmask.long.byte 0x0 0.--4. 1. "RX_LENGTH,Receive FIFO length"
group.long 0x18++0xB
line.long 0x0 "ECR,Error Control Register"
bitfld.long 0x0 7. "T0_REPEAT,Repeat Character Transmission" "0,1"
bitfld.long 0x0 6. "T0_CLR,Clear T=0 Error" "0,1"
bitfld.long 0x0 3.--4. "PE_TL,Parity Error Trigger Level" "0,1,2,3"
bitfld.long 0x0 0.--1. "T0ERR_TL,T=0 Error Trigger Level" "0,1,2,3"
line.long 0x4 "LCR,Line Control Register"
bitfld.long 0x4 4. "TX_T1,Transmitter Protocol" "0,1"
bitfld.long 0x4 3. "RX_T1,Receiver Protocol" "0,1"
bitfld.long 0x4 2. "EPS,Even Parity Select(EPS) - This bit is the even parity select bit. When EPS is a logic 0 an odd number of logic ones is transmitted or checked in the data word bits and the parity bit. When EPS is a logic 1 an even number of logic ones is.." "0,1"
bitfld.long 0x4 1. "ORDER,Transmit/Receive Bit Order" "0,1"
bitfld.long 0x4 0. "INVERSE,Bit inversion" "0,1"
line.long 0x8 "USCCR,Card Control Register"
bitfld.long 0x8 4. "TXD_FORCE,Force TXD - This bit should always remain non-active unless running a deactivation process. In deactivation the I/O must be turned low before turning down the card's voltage" "0,1"
bitfld.long 0x8 1. "VCC,Card Voltage" "0,1"
bitfld.long 0x8 0. "RST_CARD_N,Card Reset" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "LSR,Line Status Register"
bitfld.long 0x0 15. "RXD,Reflects serail data from the I/O pad" "0,1"
bitfld.long 0x0 14. "RX_WORKING,Receiver Working" "0,1"
bitfld.long 0x0 13. "TX_WORKING,Transmitter Working" "0,1"
bitfld.long 0x0 12. "RX_EMPTY_N,Receive FIFO Empty" "0,1"
bitfld.long 0x0 11. "TDR,Transmitter Data Refill" "0,1"
bitfld.long 0x0 6. "BWT,Block Waiting Time" "0,1"
bitfld.long 0x0 5. "CWT,Character Waiting Time" "0,1"
newline
bitfld.long 0x0 4. "TIMEO,Receiver Time Out" "0,1"
bitfld.long 0x0 3. "FRAMERR,Framing Error" "0,1"
bitfld.long 0x0 2. "T0ERR,T=0 Error" "0,1"
bitfld.long 0x0 1. "PERR,Parity Error" "0,1"
bitfld.long 0x0 0. "OVRN,Receiver Data Overrun Error" "0,1"
group.long 0x28++0x1F
line.long 0x0 "EGTR,Extra Guard Time Register"
hexmask.long.byte 0x0 0.--7. 1. "EGTM,Extra Guard Time Moments: Number of total Guard Time moments"
line.long 0x4 "BGTR,Block Guard Time Register"
hexmask.long.byte 0x4 0.--7. 1. "BGT,Block Guard TIME: Number of total Block Guard Time moments"
line.long 0x8 "TOR,Time Out Register"
hexmask.long.byte 0x8 0.--7. 1. "TO,Time Out: Number of total Time Out moments"
line.long 0xC "CLKR,Clock Register"
bitfld.long 0xC 15. "STOP_CLK_USIM,Stop USIM_IF Clock" "0,1"
bitfld.long 0xC 14. "STOP_LEVEL,Stop Level" "0,1"
bitfld.long 0xC 13. "STOP_UCLK,Stop Card Clock" "0,1"
rbitfld.long 0xC 12. "RQST,Clock Change Request" "0,1"
hexmask.long.byte 0xC 0.--7. 1. "DIVISOR,Clock Divisor"
line.long 0x10 "DLR,Divisor Latch Register"
hexmask.long.word 0x10 0.--15. 1. "DIVISOR,Baud Divisor - Determines the number of USIM clock in between samples forcing the total length of a bit to be DIVISOR*(FACTOR+1)*(USIM_CYCLE). The value zero if forbidden for DIVISOR."
line.long 0x14 "FLR,Factor Latch Register"
hexmask.long.byte 0x14 0.--7. 1. "FACTOR,Baud Factor - Determines the number of samples per bit. Number of samples would be (FACTOR+1). ISO standard demands minimum of 6 samples; therefore 5 is the minimum value of FACTOR bits"
line.long 0x18 "CWTR,Character Waiting Time Register"
hexmask.long.word 0x18 0.--15. 1. "CWT,Character Waiting Time - Number of total Character Waiting Time moments"
line.long 0x1C "BWTR,Block Waiting Time Register"
hexmask.long.word 0x1C 0.--15. 1. "BWT,Block Waiting Time - Number of total Block Waiting Time moments"
tree.end
tree "UTICK (Micro-Tick Timer)"
base ad:0x4000F000
group.long 0x0++0xB
line.long 0x0 "CTRL,Control"
bitfld.long 0x0 31. "REPEAT,Repeat delay" "0: One-time delay,1: Delay repeats continuously"
hexmask.long 0x0 0.--30. 1. "DELAYVAL,Tick interval"
line.long 0x4 "STAT,Status"
bitfld.long 0x4 1. "ACTIVE,Timer active flag" "0: The Micro-Tick Timer is not active (stopped),1: The Micro-Tick Timer is currently active"
bitfld.long 0x4 0. "INTR,Interrupt flag" "0: No interrupt is pending,1: An interrupt is pending"
line.long 0x8 "CFG,Capture Configuration"
bitfld.long 0x8 11. "CAPPOL3,Capture Polarity 3" "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x8 10. "CAPPOL2,Capture Polarity 2" "0: Positive edge capture,1: Negative edge capture"
newline
bitfld.long 0x8 9. "CAPPOL1,Capture Polarity 1" "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x8 8. "CAPPOL0,Capture Polarity 0" "0: Positive edge capture,1: Negative edge capture"
newline
bitfld.long 0x8 3. "CAPEN3,Enable Capture 3" "0: Disabled,1: Enabled"
bitfld.long 0x8 2. "CAPEN2,Enable Capture 2" "0: Disabled,1: Enabled"
newline
bitfld.long 0x8 1. "CAPEN1,Enable Capture 1" "0: Disabled,1: Enabled"
bitfld.long 0x8 0. "CAPEN0,Enable Capture 0" "0: Disabled,1: Enabled"
wgroup.long 0xC++0x3
line.long 0x0 "CAPCLR,Capture Clear"
bitfld.long 0x0 3. "CAPCLR3,Clear capture 3" "0: Does nothing,1: Write 1 to clear the CAP3 register value"
bitfld.long 0x0 2. "CAPCLR2,Clear capture 2" "0: Does nothing,1: Write 1 to clear the CAP2 register value"
newline
bitfld.long 0x0 1. "CAPCLR1,Clear capture 1" "0: Does nothing,1: Write 1 to clear the CAP1 register value"
bitfld.long 0x0 0. "CAPCLR0,Clear capture 0" "0: Does nothing,1: Write 1 to clear the CAP0 register value"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x10)++0x3
line.long 0x0 "CAP[$1],Capture"
bitfld.long 0x0 31. "VALID,Captured value is valid" "0: A valid value has been not been captured,1: A valid value has been captured based on a.."
hexmask.long 0x0 0.--30. 1. "CAP_VALUE,Captured value for the related capture event"
repeat.end
tree.end
tree "WL (Wireless)"
base ad:0x0
tree "WLAPU (Wi)"
base ad:0x41258000
group.long 0x8++0xF
line.long 0x0 "SOCWLAPU_APU_BYPASS0,APU Bypass0"
bitfld.long 0x0 31. "RFU_PA_PE_G_BYPASS_VAL,RFU PA_PE_G Bypass Value" "0,1"
newline
bitfld.long 0x0 30. "RFU_PA_PE_A_BYPASS_VAL,RFU PA_PE_A Bypass Value" "0,1"
newline
bitfld.long 0x0 29. "RFU_PE2_BYPASS_VAL,RFU PE2 Bypass Value" "0,1"
newline
bitfld.long 0x0 28. "RFU_PE1_BYPASS_VAL,RFU PE1 Bypass Value" "0,1"
newline
bitfld.long 0x0 27. "RX_PE_BYPASS_VAL,Rx_Pe Bypass Value" "0,1"
newline
bitfld.long 0x0 26. "TX_PE_BYPASS_VAL,Tx_Pe Bypass Value" "0,1"
newline
bitfld.long 0x0 23. "TBG_MAC2_CLK_EN_BYPASS_VAL,TBG512_320_176_MAC2_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 22. "TBG_BBU2_CLK_EN_BYPASS_VAL,TBG512_320_176_BBU2_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 21. "TBG_SOC_CLK_EN_BYPASS_VAL,TBG512_320_176_SoC_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 20. "TBG_MAC1_CLK_EN_BYPASS_VAL,TBG512_320_176_MAC1_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 19. "TBG_T2_PDB_BYPASS_VAL,TBF176_Pdb Bypass Value" "0,1"
newline
bitfld.long 0x0 18. "TBG_BBU1_CLK_EN_BYPASS_VAL,TBG512_320_176_BBU1_Clk_En Bypass Value" "0,1"
newline
bitfld.long 0x0 17. "TBG_TCPU_PDB_BYPASS_VAL,TCPU_Pdb Bypass Value" "0,1"
newline
bitfld.long 0x0 16. "C2P_XOSC_EN_BYPASS_VAL,C2p_Xosc_En Bypass Value" "0,1"
newline
bitfld.long 0x0 15. "RFU_PA_PE_G_BYPASS_EN,RFU_PA_PE_G_Bypass Enable" "0,1"
newline
bitfld.long 0x0 14. "RFU_PA_PE_A_BYPASS_EN,RFU_PA_PE_A_Bypass Enable" "0,1"
newline
bitfld.long 0x0 13. "RFU_PE2_BYPASS_EN,RFU_PE2_Bypass Enable" "0,1"
newline
bitfld.long 0x0 12. "RFU_PE1_BYPASS_EN,RFU_PE1_Bypass Enable" "0,1"
newline
bitfld.long 0x0 11. "RX_PE_BYPASS_EN,BBU_Rx_Pe_Bypass Enable" "0,1"
newline
bitfld.long 0x0 10. "TX_PE_BYPASS_EN,BBU_Rx_Pe_Bypass Enable" "0,1"
newline
bitfld.long 0x0 7. "TBG_MAC2_CLK_EN_BYPASS_EN,TBG512_320_176_MAC2_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 6. "TBG_BBU2_CLK_EN_BYPASS_EN,TBG512_320_176_BBU2_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 5. "TBG_SOC_CLK_EN_BYPASS_EN,TBG512_320_176_SoC_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 4. "TBG_MAC1_CLK_EN_BYPASS_EN,TBG512_320_176_MAC1_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 3. "TBG_T2_PDB_BYPASS_EN,tbg t2_Pdb_Bypass" "0,1"
newline
bitfld.long 0x0 2. "TBG_BBU1_CLK_EN_BYPASS_EN,TBG512_320_176_BBU1_Clk_En_Bypass" "0,1"
newline
bitfld.long 0x0 1. "TBG_TCPU_PDB_BYPASS_EN,TCPU_Pdb_Bypass" "0,1"
newline
bitfld.long 0x0 0. "C2P_XOSC_EN_BYPASS_EN,C2p_Xosc_En_Bypass" "0,1"
line.long 0x4 "SOCWLAPU_APU_PWR_CTRL_BYPASS0,APU power control Bypass Register 0"
bitfld.long 0x4 29. "APU_WLAN1_NON_UDR_RSTB_BYPASS_EN,Firmware Bypass apu_wlan1_non_udr_rst" "0,1"
newline
bitfld.long 0x4 28. "APU_WLAN1_NON_UDR_RSTB_BYPASS_VAL,Firmware Bypass Value for apu_wlan1_non_udr_rst" "0,1"
newline
bitfld.long 0x4 25. "BBUD_SRAM_PD_BYPASS_EN,Firmware Bypass SRAM_PD from APU" "0,1"
newline
bitfld.long 0x4 24. "BBUD_SRAM_PD_BYPASS_VAL,Firmware Bypass Value for SRAM_PD (active high signal)" "0,1"
newline
bitfld.long 0x4 23. "SOC_BBUD_NON_UDR_RSTB_BYPASS_EN,Firmware Bypass SoC_BBUD_Non_Udr_Rstb from APU" "0,1"
newline
bitfld.long 0x4 22. "SOC_BBUD_NON_UDR_RSTB_BYPASS_VAL,Firmware Bypass Value for SoC_BBUD_Non_Udr_Rstb (active low signal)" "0,1"
newline
bitfld.long 0x4 21. "BBUD_ISO_EN_BYPASS_EN,BBUD Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0x4 20. "BBUD_ISO_EN_BYPASS_VAL,BBUD Isolation Cell Control" "0,1"
newline
bitfld.long 0x4 19. "BBUD_FWBAR_BYPASS_EN,BBUD Firewallbar Control Enable" "0,1"
newline
bitfld.long 0x4 18. "BBUD_FWBAR_BYPASS_VAL,BBUD Firewallbar Control" "0,1"
newline
bitfld.long 0x4 17. "BBUD_PSW_BYPASS_EN,BBUD Power Switch Control Enable" "0,1"
newline
bitfld.long 0x4 16. "BBUD_PSW_BYPASS_VAL,BBUD Power Switch Control" "0,1"
newline
bitfld.long 0x4 13. "APU_WLAN_NON_UDR_RSTB_BYPASS_VAL,Firmware Bypass apu_wlan_non_udr_rstb" "0,1"
newline
bitfld.long 0x4 12. "APU_WLAN_NON_UDR_RSTB_BYPASS_EN,Firmware Bypass Value for apu_wlan_non_udr_rstb" "0,1"
newline
bitfld.long 0x4 9. "SOC_NON_UDR_RST_BYPASS_EN,Firmware Bypass SoC non udr rst from APU (used for brf sif only in KF2)" "0,1"
newline
bitfld.long 0x4 8. "SOC_NON_UDR_RST_BYPASS_VAL,Firmware Bypass Value for SoC non udr rst (active low signal)" "0,1"
newline
bitfld.long 0x4 7. "SOC_CLK_DIV_RSTB_BYPASS_EN,Firmware Bypass SoC Clk_Div_Rstb from APU" "0,1"
newline
bitfld.long 0x4 6. "SOC_CLK_DIV_RSTB_BYPASS_VAL,Firmware Bypass Value for SoC Dlk_Div_Rstb (active low signal)" "0,1"
newline
bitfld.long 0x4 5. "SOC_ISO_EN_BYPASS_EN,SoC Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0x4 4. "SOC_ISO_EN_BYPASS_VAL,SoC Isolation Cell Control" "0,1"
newline
bitfld.long 0x4 3. "SOC_FWBAR_BYPASS_EN,SoC Firewallbar Control Enable" "0,1"
newline
bitfld.long 0x4 2. "SOC_FWBAR_BYPASS_VAL,SoC Firewallbar Control" "0,1"
newline
bitfld.long 0x4 1. "SOC_PSW_BYPASS_EN,SoC Power Switch Control Enable" "0,1"
newline
bitfld.long 0x4 0. "SOC_PSW_BYPASS_VAL,SoC Power Switch Control" "0,1"
line.long 0x8 "SOCWLAPU_APU_PWR_CTRL_BYPASS1,APU power control Bypass Register 1"
bitfld.long 0x8 9. "RFU_2G_SRAM_PD_BYPASS_EN,Firmware Bypass RFU 2G SRAM_PD from APU" "0,1"
newline
bitfld.long 0x8 8. "RFU_2G_SRAM_PD_BYPASS_VAL,Firmware Bypass Value for RFU 2G SRAM_PD (active high signal)" "0,1"
newline
bitfld.long 0x8 7. "RFU_2G_CLK_DIV_RSTB_BYPASS_EN,Firmware Bypass RFU 2G Clk_Div_Rstb from APU" "0,1"
newline
bitfld.long 0x8 6. "RFU_2G_CLK_DIV_RSTB_BYPASS_VAL,Firmware Bypass Value for RFU 2G Clk_Div_Rstb (active low signal)" "0,1"
newline
bitfld.long 0x8 5. "RFU_2G_ISO_EN_BYPASS_EN,RFU 2G Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0x8 4. "RFU_2G_ISO_EN_BYPASS_VAL,RFU 2G Isolation Cell Control" "0,1"
newline
bitfld.long 0x8 3. "RFU_2G_FWBAR_BYPASS_EN,RFU 2G Firewallbar Control Enable" "0,1"
newline
bitfld.long 0x8 2. "RFU_2G_FWBAR_BYPASS_VAL,RFU Firewallbar Control" "0,1"
newline
bitfld.long 0x8 1. "RFU_2G_PSW_BYPASS_EN,RFU 2G Power Switch Control Enable" "0,1"
newline
bitfld.long 0x8 0. "RFU_2G_PSW_BYPASS_VAL,RFU 2G Power Switch Control" "0,1"
line.long 0xC "SOCWLAPU_APU_PWR_CTRL_BYPASS2,APU power control Bypass Register 2"
bitfld.long 0xC 11. "WLAN_RET_PD_PSW_BYPASS_EN,wlan_ret_pd Power Switch Control Enable" "0,1"
newline
bitfld.long 0xC 10. "WLAN_RET_PD_PSW_BYPASS_VAL,wlan_ret_pd_psw_bypass_val" "0,1"
newline
bitfld.long 0xC 9. "WLAN_PD_SRAM_PD_BYPASS_EN,Firmware Bypass SRAM_PD from APU" "0,1"
newline
bitfld.long 0xC 8. "WLAN_PD_SRAM_PD_BYPASS_VAL,Firmware Bypass Value for SRAM_PD (active high signal)" "0,1"
newline
bitfld.long 0xC 7. "WLAN_PD_CLK_DIV_RSTB_BYPASS_EN,Firmware Bypass wlan_pd Clk_Div_Rstb from APU" "0,1"
newline
bitfld.long 0xC 6. "WLAN_PD_CLK_DIV_RSTB_BYPASS_VAL,Firmware Bypass Value for wlan_pd Clk_Div_Rstb (active low signal)" "0,1"
newline
bitfld.long 0xC 5. "WLAN_PD_ISO_EN_BYPASS_EN,wlan_pd Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0xC 4. "WLAN_PD_ISO_EN_BYPASS_VAL,wlan_pd Isolation Cell Control" "0,1"
newline
bitfld.long 0xC 3. "WLAN_PD_FWBAR_BYPASS_EN,wlan_pd Firewallbar Control Enable" "0,1"
newline
bitfld.long 0xC 2. "WLAN_PD_FWBAR_BYPASS_VAL,wlan_pd Firewallbar Control" "0,1"
newline
bitfld.long 0xC 1. "WLAN_PD_PSW_BYPASS_EN,wlan_pd Power Switch Control Enable" "0,1"
newline
bitfld.long 0xC 0. "WLAN_PD_PSW_BYPASS_VAL,wlan_pd Power Switch Control" "0,1"
group.long 0x1C++0xF
line.long 0x0 "SOCWLAPU_APU_BYPASS1,APU Bypass Register 1"
bitfld.long 0x0 29. "APU_WL_RF_CLK_EN_BYPASS_VAL,Firmware Bypass Value for APU_WL_RF_Clk_En (active high signal)" "0,1"
newline
bitfld.long 0x0 28. "APU_WL_RF_CLK_EN_BYPASS_EN,Firmware Bypass for APU_WL_RF_Clk_En" "0,1"
newline
bitfld.long 0x0 27. "SLNA_CLK_EN_BYPASS_VAL,Firmware Bypass Value for SLNA_Clk_En (active high signal)" "0,1"
newline
bitfld.long 0x0 26. "SLNA_CLK_EN_BYPASS_EN,Firmware Bypass for SLNA_Clk_En" "0,1"
newline
bitfld.long 0x0 19. "BCA_CLK_EN_BYPASS_VAL,Firmware Bypass Value for BCA_Clk_En (active high signal)" "0,1"
newline
bitfld.long 0x0 18. "BCA_CLK_EN_BYPASS_EN,Firmware Bypass BCA_Clk_En" "0,1"
newline
bitfld.long 0x0 10. "PLL_OVERRIDE_BYPASS,PLL Override Bypass" "0,1"
newline
bitfld.long 0x0 9. "PE1_DYN_BYPASS,PE1_Dyn_Bypass" "0,1"
newline
bitfld.long 0x0 8. "RXPE_DYN_BYPASS,Rxpe_Dyn_Bypass" "0,1"
newline
bitfld.long 0x0 7. "SOC_CAU_XOSC_EN_BP_VAL,Firmware Bypass Xosc_En Value for SoC_CAU_Xosc_En_Bp_En" "0,1"
newline
bitfld.long 0x0 6. "SOC_CAU_XOSC_EN_BP_EN,Firmware Bypass Xosc_En to CAU and other parts of the chip including pads" "0,1"
line.long 0x4 "SOCWLAPU_APU_BYPASS2,APU Bypass Register 2"
bitfld.long 0x4 28.--29. "PMIC_DVSC_CTRL_BYPASS_VAL,Firmware Bypass value for pmic dvsc ctrl from APU (default high power WLAN ode)" "0,1,2,3"
newline
bitfld.long 0x4 27. "PMIC_DVSC_CTRL_BYPASS_EN,Firmware Bypass enable for pmic dvsc ctrl from APU" "0,1"
newline
bitfld.long 0x4 26. "TBG_T1_STABLE_BYPASS_VAL,Firmware Bypass value for T1 pll_stable signal from APU" "0,1"
newline
bitfld.long 0x4 25. "TBG_T1_STABLE_BYPASS_EN,Firmware Bypass enable for T1 pll_stable signal from APU" "0,1"
newline
bitfld.long 0x4 13. "T3_PI2_PDB_BYPASS_VAL,Firmware Bypass Value for TBG256 aiu_pi2" "0,1"
newline
bitfld.long 0x4 12. "T3_PI2_PDB_BYPASS_EN,Firmware Bypass for TBG256 aiu_pi2" "0,1"
newline
bitfld.long 0x4 11. "T3_PI1_PDB_BYPASS_VAL,Firmware Bypass Value for TBG256 aiu pi1" "0,1"
newline
bitfld.long 0x4 10. "T3_PI1_PDB_BYPASS_EN,Firmware Bypass for TBG256 aiu_pi1" "0,1"
newline
bitfld.long 0x4 9. "TBG_T3_PDB_BYPASS_VAL,T3_Pdb Bypass Value" "0,1"
newline
bitfld.long 0x4 8. "TBG_T3_PDB_BYPASS_EN,Firmware Bypass for T3_pdb pll" "0,1"
line.long 0x8 "SOCWLAPU_APU_BYPASS3,APU Bypass Register 3"
bitfld.long 0x8 27. "RFU_REF_CLK_EN2_BYPASS_VAL,Firmware Bypass Value for RFU2G reference clk enable" "0,1"
newline
bitfld.long 0x8 26. "RFU_REF_CLK_EN2_BYPASS_EN,Firmware Bypass Enable for RFU2G reference clk enable" "0,1"
newline
bitfld.long 0x8 25. "RFU_REF_CLK_EN1_BYPASS_VAL,Firmware Bypass Value for RFU5G reference clk enable" "0,1"
newline
bitfld.long 0x8 24. "RFU_REF_CLK_EN1_BYPASS_EN,Firmware Bypass Enable for RFU5G reference clk enable" "0,1"
newline
bitfld.long 0x8 17. "SLNA_BBUD_BRF_BYPASS_VAL,Firmware Bypass Value for apu mux control of SLNA gain from bbud/brf" "0,1"
newline
bitfld.long 0x8 16. "SLNA_BBUD_BRF_BYPASS_EN,Firmware Bypass for apu mux control of SLNA gain from bbud/brf" "0,1"
newline
bitfld.long 0x8 15. "SPSRAM_RST_BYPASS_VAL,Firmware Bypass Value for single power sram reset(active low signal)" "0,1"
newline
bitfld.long 0x8 14. "SPSRAM_RST_BYPASS_EN,Firmware Bypass for Single power SRAM reset enable" "0,1"
newline
bitfld.long 0x8 13. "WLAN1_CLK_DIV_EN_BYPASS_VAL,Firmware Bypass Value for WLAN1 clocks divider enable(active high signal)" "0,1"
newline
bitfld.long 0x8 12. "WLAN1_CLK_DIV_EN_BYPASS_EN,Firmware Bypass for WLAN1 clocks divider clock enable" "0,1"
newline
bitfld.long 0x8 11. "WLAN1_PD_CLK_EN_BYPASS_VAL,Firmware Bypass Value for WLAN1 PD domain clock enable(active high signal)" "0,1"
newline
bitfld.long 0x8 10. "WLAN1_PD_CLK_EN_BYPASS_EN,Firmware Bypass for WLAN1 PD domain clock enable" "0,1"
newline
bitfld.long 0x8 5. "SYS_CLK_EN_BYPASS_VAL,Firmware Bypass Value for sys clock domain clock enable(active high signal)" "0,1"
newline
bitfld.long 0x8 4. "SYS_CLK_EN_BYPASS_EN,Firmware Bypass for sys clock domain clock enable" "0,1"
line.long 0xC "SOCWLAPU_APU_CTRL,APU Control"
bitfld.long 0xC 19. "APU_HOST_WKUP_CPU3,APU Wakeup triggered by CPU3" "0,1"
newline
bitfld.long 0xC 18. "APU_HOST_WKUP_CPU1,APU Wakeup triggered by CPU1" "0,1"
newline
bitfld.long 0xC 16. "SOC_PA_PE_EN_MAC2,PA_PE control from MAC2 to RFU SoC_PA_PE Input" "0,1"
newline
bitfld.long 0xC 15. "LMU_BYPASS,LMU global bypass bit" "0,1"
newline
bitfld.long 0xC 12. "RFU_2G_SRAM_PD_METHOD_SEL,Choose apu signal to use for SRAM PD of RFU 2G memories" "0,1"
newline
bitfld.long 0xC 11. "SOC_PA_PE_G_EN,PA_PE_G control from SoC to Pad" "0,1"
newline
bitfld.long 0xC 10. "SOC_PA_PE_A_EN,PA_PE_A control from SoC to Pad" "0,1"
newline
bitfld.long 0xC 9. "SOC_PA_PE_EN,PA_PE control from SoC to RFU SoC_PA_PE Input" "0,1"
newline
bitfld.long 0xC 8. "BRF_INT_WAKEUP,APU Wakeup" "0,1"
newline
bitfld.long 0xC 7. "APU_HOST_WKUP,APU Wakeup triggered by CPU2" "0,1"
newline
bitfld.long 0xC 6. "ISU_WKUP_IN_USE,APU Wakeup" "0,1"
newline
bitfld.long 0xC 4. "FORCE_BTU_WAKEUP,Force BTU Wakeup" "0,1"
newline
hexmask.long.byte 0xC 0.--3. 1. "APU_REFCLK_DIV_SEL,APU Reference Clock Divider Select"
rgroup.long 0x2C++0x3
line.long 0x0 "SOCWLAPU_APU_STATUS,APU Status Register"
bitfld.long 0x0 3. "SOC_CLK_TBG_SEL,Monitor SoC_Clk_TBG_Sel" "0,1"
newline
bitfld.long 0x0 2. "SOC_CLK_T3_REF_SEL,Monitor SoC_Clk_T3_Ref_Sel" "0,1"
newline
bitfld.long 0x0 1. "BTU_CLK_TBG_SEL,Monitor BTU_Clk_TBG_Sel" "0,1"
newline
bitfld.long 0x0 0. "BRF_CLK_TBG_SEL,Monitor BRF_Clk_TBG_Sel" "0,1"
group.long 0x30++0x13
line.long 0x0 "SOCWLAPU_CPU1_LMU_STA_BYPASS0,LMU static bank control byapss0 Register"
hexmask.long.byte 0x0 24.--31. 1. "LMU_STA_BANKS_PSW_EN_BP_VAL,Firmware Bypass value for lmu static banks psw_en"
newline
hexmask.long.byte 0x0 16.--23. 1. "LMU_STA_BANKS_PSW_EN_BP_EN,Firmware Bypass enable for lmu static banks psw_en"
newline
hexmask.long.byte 0x0 8.--15. 1. "LMU_STA_BANKS_ISO_EN_BP_VAL,Firmware Bypass value for lmu static banks iso_en"
newline
hexmask.long.byte 0x0 0.--7. 1. "LMU_STA_BANKS_ISO_EN_BP_EN,Firmware Bypass enable for lmu static banks iso_en"
line.long 0x4 "SOCWLAPU_CPU1_LMU_STA_BYPASS1,LMU static bank control byapss1 Register"
hexmask.long.byte 0x4 24.--31. 1. "LMU_STA_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu static banks fnrst"
newline
hexmask.long.byte 0x4 16.--23. 1. "LMU_STA_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu static banks fnrst"
newline
hexmask.long.byte 0x4 8.--15. 1. "LMU_STA_BANKS_SRAM_PD_BP_VAL,Firmware Bypass value for lmu static banks sram_pd"
newline
hexmask.long.byte 0x4 0.--7. 1. "LMU_STA_BANKS_SRAM_PD_BP_EN,Firmware Bypass enable for lmu static banks sram_pd"
line.long 0x8 "SOCWLAPU_CPU1_LMU_STA_BYPASS2,LMU static bank byapss2 Register"
hexmask.long.byte 0x8 8.--15. 1. "LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl"
newline
hexmask.long.byte 0x8 0.--7. 1. "LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl"
line.long 0xC "SOCWLAPU_LMU_DYN_BYPASS0,LMU dynamic bank control byapss0 Register"
bitfld.long 0xC 31. "LMU_DYN_BANKS_SRAM_FNRST_USE_WLAN_FNRST,1: By default WLAN_SRAM_FNRST is used for SMU off domain banks" "?,1: By default WLAN_SRAM_FNRST is used for SMU off.."
newline
bitfld.long 0xC 24.--26. "LMU_DYN_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu dynamic banks fnrst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 16.--18. "LMU_DYN_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu dynamic banks fnrst" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 8.--10. "LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu dynamic banks vddmc_sw_pd_ctrl" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0.--2. "LMU_DYN_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu dynamic banks vddmc_sw_pd_ctrl" "0,1,2,3,4,5,6,7"
line.long 0x10 "SOCWLAPU_LMU_G2BIST_CTRL_BYPASS,LMU G2Bist control bypass Register"
hexmask.long.byte 0x10 28.--31. 1. "G2BIST_STATUS,g2bist status"
newline
bitfld.long 0x10 27. "LMU_G2BIST_CLK_EN_BP_VAL,Firmware Bypass value for lmu g2bist clock en" "0,1"
newline
bitfld.long 0x10 26. "LMU_G2BIST_CLK_EN_BP_EN,Firmware Bypass enable for lmu g2bist clock en" "0,1"
newline
bitfld.long 0x10 25. "LMU_G2BIST_START_BP_VAL,Firmware Bypass value for lmu g2bist start" "0,1"
newline
bitfld.long 0x10 24. "LMU_G2BIST_START_BP_EN,Firmware Bypass enable for lmu g2bist start" "0,1"
newline
hexmask.long.byte 0x10 1.--5. 1. "LMU_G2BIST_MODE_BYPASS_VAL,Firmware Bypass value for lmu g2bist mode"
newline
bitfld.long 0x10 0. "LMU_G2BIST_MODE_BYPASS_EN,Firmware Bypass enable for lmu g2bist mode" "0,1"
group.long 0x50++0x3
line.long 0x0 "SOCWLAPU_CPU1_LMU_G2BIST_CTRL_BYPASS,LMU G2Bist control bypass Register for CPU1"
hexmask.long.byte 0x0 24.--27. 1. "LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_VAL,Firmware Bypass value for SMU1 dynamic banks lmu powerdomain repair request"
newline
bitfld.long 0x0 20. "LMU_SMU1_DYN_PWRDMN_RPR_REQ_BP_EN,Firmware Bypass enable for SMU1 dynamic banks lmu powerdomain repair request" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_VAL,Firmware Bypass value for CPU1 static banks lmu powerdomain repair request"
newline
bitfld.long 0x0 0. "LMU_CPU1_STA_PWRDMN_RPR_REQ_BP_EN,Firmware Bypass enable for CPU1 static banks lmu powerdomain repair request" "0,1"
group.long 0x58++0x1B
line.long 0x0 "SOCWLAPU_APU_PWR_CTRL_BYPASS4,'"
bitfld.long 0x0 11. "RFU_RTDP_WU_RSTB_BYPASS_EN,Firmware Bypass RFU /RTDP wakeup reset from APU" "0,1"
newline
bitfld.long 0x0 10. "RFU_RTDP_WU_RSTB_BYPASS_VAL,Firmware Bypass Value for RFU /RTDP Wakeup reset (active low signal)" "0,1"
line.long 0x4 "SOCWLAPU_APU_PWR_CTRL_BYPASS5,'"
bitfld.long 0x4 13. "CPU1_VINITHI_BYPASS_EN,Firmware Bypass enable for CPU1 Vinithi" "0,1"
newline
bitfld.long 0x4 12. "CPU1_VINITHI_BYPASS_VAL,Firmware Bypass Value for CPU1 Vinithi (default boot from ROM)" "0,1"
line.long 0x8 "SOCWLAPU_APU_PWR_CTRL_BYPASS6,APU power control Bypass Register 6"
bitfld.long 0x8 9. "WLAN1_PD_SRAM_PD_BYPASS_EN,Firmware Bypass SRAM_PD from APU" "0,1"
newline
bitfld.long 0x8 8. "WLAN1_PD_SRAM_PD_BYPASS_VAL,Firmware Bypass Value for SRAM_PD (active high signal)" "0,1"
newline
bitfld.long 0x8 7. "WLAN1_PD_CLK_DIV_RSTB_BYPASS_EN,Firmware Bypass wlan1_pd Clk_Div_Rstb from APU" "0,1"
newline
bitfld.long 0x8 6. "WLAN1_PD_CLK_DIV_RSTB_BYPASS_VAL,Firmware Bypass Value for wlan1_pd Clk_Div_Rstb (active low signal)" "0,1"
newline
bitfld.long 0x8 5. "WLAN1_PD_ISO_EN_BYPASS_EN,wlan1_pd Isolation Cell Control Enable" "0,1"
newline
bitfld.long 0x8 4. "WLAN1_PD_ISO_EN_BYPASS_VAL,wlan1_pd Isolation Cell Control" "0,1"
newline
bitfld.long 0x8 3. "WLAN1_PD_FWBAR_BYPASS_EN,wlan1_pd Firewallbar Control Enable" "0,1"
newline
bitfld.long 0x8 2. "WLAN1_PD_FWBAR_BYPASS_VAL,wlan1_pd Firewallbar Control" "0,1"
newline
bitfld.long 0x8 1. "WLAN1_PD_PSW_BYPASS_EN,wlan1_pd Power Switch Control Enable" "0,1"
newline
bitfld.long 0x8 0. "WLAN1_PD_PSW_BYPASS_VAL,wlan1_pd Power Switch Control" "0,1"
line.long 0xC "SOCWLAPU_APU_PWR_CTRL_BYPASS7,APU power control Bypass Register 7"
bitfld.long 0xC 11. "RFU_RTDP2_WU_RSTB_BYPASS_EN,Firmware Bypass RFU /rtdp2 wakeup reset from APU" "0,1"
newline
bitfld.long 0xC 10. "RFU_RTDP2_WU_RSTB_BYPASS_VAL,Firmware Bypass Value for RFU /rtdp2 Wakeup reset (active low signal)" "0,1"
line.long 0x10 "SOCWLAPU_SMU1_HYBRID_LMU_BYPASS0,LMU static bank control byapss0 Register for smu1 hybrid banks mem"
hexmask.long.byte 0x10 24.--31. 1. "LMU_HYBRID_BANKS_PSW_EN_BP_VAL,Firmware Bypass value for lmu static banks psw_en"
newline
hexmask.long.byte 0x10 16.--23. 1. "LMU_HYBRID_BANKS_PSW_EN_BP_EN,Firmware Bypass enable for lmu static banks psw_en"
newline
hexmask.long.byte 0x10 8.--15. 1. "LMU_HYBRID_BANKS_ISO_EN_BP_VAL,Firmware Bypass value for lmu static banks iso_en"
newline
hexmask.long.byte 0x10 0.--7. 1. "LMU_HYBRID_BANKS_ISO_EN_BP_EN,Firmware Bypass enable for lmu static banks iso_en"
line.long 0x14 "SOCWLAPU_SMU1_HYBRID_LMU_BYPASS1,LMU static bank control byapss1 Register for smu1 hybrid banks mem"
hexmask.long.byte 0x14 24.--31. 1. "LMU_HYBRID_BANKS_FNRST_BP_VAL,Firmware Bypass value for lmu static banks fnrst"
newline
hexmask.long.byte 0x14 16.--23. 1. "LMU_HYBRID_BANKS_FNRST_BP_EN,Firmware Bypass enable for lmu static banks fnrst"
newline
hexmask.long.byte 0x14 8.--15. 1. "LMU_HYBRID_BANKS_SRAM_PD_BP_VAL,Firmware Bypass value for lmu static banks sram_pd"
newline
hexmask.long.byte 0x14 0.--7. 1. "LMU_HYBRID_BANKS_SRAM_PD_BP_EN,Firmware Bypass enable for lmu static banks sram_pd"
line.long 0x18 "SOCWLAPU_SMU1_HYBRID_LMU_BYPASS2,LMU static bank control byapss2 Register for smu1 hybrid banks mem"
hexmask.long.byte 0x18 8.--15. 1. "LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_VAL,Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl"
newline
hexmask.long.byte 0x18 0.--7. 1. "LMU_HYBRID_BANKS_VDDMC_SW_PD_CTRL_BP_EN,Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl"
group.long 0x7C++0x2B
line.long 0x0 "SOCWLAPU_APU_ECO_CTRL,APU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "SOCWLAPU_GPIO_WKUP_CTRL0,'"
hexmask.long 0x4 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [0]"
line.long 0x8 "SOCWLAPU_GPIO_WKUP_CTRL1,'"
hexmask.long 0x8 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [4]"
line.long 0xC "SOCWLAPU_GPIO_WKUP_CTRL2,'"
hexmask.long 0xC 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [8]"
line.long 0x10 "SOCWLAPU_GPIO_WKUP_CTRL3,'"
hexmask.long 0x10 0.--31. 1. "P2C_WKUP_SELECT,[07:00]: Mux 1 of 32 p2c_pad_wkup input pins to APU wakeup input [12]"
line.long 0x14 "SOCWLAPU_HOST_WKUP_MODE,'"
hexmask.long.word 0x14 0.--15. 1. "GPIO_SEL,gpio_sel"
line.long 0x18 "SOCWLAPU_T3_CLK_DIV_EN_BYPASS,'"
bitfld.long 0x18 19. "TCPU_CPU_CLK_DIV_EN_BYPASS_VAL,bypass value for tcpu cpu_clk_en" "0,1"
newline
bitfld.long 0x18 18. "TCPU_CPU_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 17. "T3_BBUD_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 16. "T3_BBUD_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 15. "T3_MAC2_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 14. "T3_MAC2_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 13. "T3_MAC1_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 12. "T3_MAC1_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 11. "T3_213P3_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 10. "T3_213P3_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 9. "T3_SOC_512_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 8. "T3_SOC_512_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 7. "T3_SOC_426_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 6. "T3_SOC_426_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 5. "T3_SOC_365P7_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 4. "T3_SOC_365P7_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 3. "T3_SOC_320_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 2. "T3_SOC_320_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
newline
bitfld.long 0x18 1. "T3_SOC_256_CLK_DIV_EN_BYPASS_VAL,bypass value" "0,1"
newline
bitfld.long 0x18 0. "T3_SOC_256_CLK_DIV_EN_BYPASS_EN,Enable/ disable value:" "0,1"
line.long 0x1C "SOCWLAPU_LDO_LV_CTRL2,LV LDO Control 2"
bitfld.long 0x1C 5. "LDO_GLU_XOSC_BYPASS_EN,XOSC_EN control bypass for ldo control logic" "0,1"
newline
bitfld.long 0x1C 4. "LDO_GLU_XOSC_VAL,XOSC_EN value for ldo control logic set by FW" "0,1"
line.long 0x20 "SOCWLAPU_CAU_BYPASS,CAU Bypass"
bitfld.long 0x20 5. "WL_CLK_BYPASS_EN,bypass enable for wl clk enable" "0,1"
newline
bitfld.long 0x20 4. "WL_CLK_BYPASS_VAL,bypass value for wl clk enable" "0,1"
newline
bitfld.long 0x20 1. "PHY_REF_CLK_BYPASS_EN,bypass enable for phy ref clk enable" "0,1"
newline
bitfld.long 0x20 0. "PHY_REF_CLK_BYPASS_VAL,bypass value for phy ref clk enable" "0,1"
line.long 0x24 "SOCWLAPU_MEM_PWDN1,Memory Powerdown Control"
bitfld.long 0x24 31. "ADMA1_BYPASS_EN,Firmware Bypass Enable for ADMA1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 30. "SIU_DBG_BYPASS_EN,Firmware Bypass Enable for WLAN DBG UART Memories Power Down" "0,1"
newline
bitfld.long 0x24 29. "MCU1_BYPASS_EN,Firmware Bypass Enable for MCU1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 28. "SDU_BYPASS_EN,Firmware Bypass Enable for cisRAM (SDU) Memory Power Down" "0,1"
newline
bitfld.long 0x24 27. "WEU_BYPASS_EN,Firmware Bypass Enable for WEU Memories Power Down" "0,1"
newline
bitfld.long 0x24 26. "BCM_BYPASS_EN,Firmware Bypass Enable for BCM Memories Power Down" "0,1"
newline
bitfld.long 0x24 25. "SMU1_BYPASS_EN,Firmware Bypass Enable for amu1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 23. "CPU1_BPM_BYPASS_EN,Firmware Bypass Enable for cpu1 bpm Memories Power Down" "0,1"
newline
bitfld.long 0x24 17. "CPU1_TCM_BYPASS_EN,Firmware Bypass Enable for cpu1 ATCM/BTCM0/BTCM1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 16. "CPU1_DTCM_BYPASS_EN,Firmware Bypass Enable for cpu1 DTCM Memories Power Down." "0,1"
newline
bitfld.long 0x24 15. "ADMA1_BYPASS_VAL,Firmware Bypass value for ADMA1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 14. "SIU_DBG_BYPASS_VAL,Firmware Bypass value for WLAN DBG UART Memories Power Down" "0,1"
newline
bitfld.long 0x24 13. "MCU1_BYPASS_VAL,Firmware Bypass value for MCU1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 12. "SDU_BYPASS_VAL,Firmware Bypass value for cisRAM (SDU) Memory Power Down" "0,1"
newline
bitfld.long 0x24 11. "WEU_BYPASS_VAL,Firmware Bypass value for WEU Memories Power Down" "0,1"
newline
bitfld.long 0x24 10. "BCM_BYPASS_VAL,Firmware Bypass value for BCM Memories Power Down" "0,1"
newline
bitfld.long 0x24 9. "SMU1_BYPASS_VAL,Firmware Bypass value for amu1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 7. "CPU1_BPM_BYPASS_VAL,Firmware Bypass value for cpu1 bpm Memories Power Down" "0,1"
newline
bitfld.long 0x24 1. "CPU1_TCM_BYPASS_VAL,Firmware Bypass value for cpu1 ATCM/BTCM0/BTCM1 Memories Power Down" "0,1"
newline
bitfld.long 0x24 0. "CPU1_DTCM_BYPASS_VAL,Firmware Bypass value for cpu1 DTCM Memories Power Down. Not used for KF2" "0,1"
line.long 0x28 "SOCWLAPU_MEM_PWDN2,Memory Powerdown Control"
bitfld.long 0x28 23. "SSU_BYPASS_EN,Firmware Bypass Enable for SSU Memories Power Down" "0,1"
newline
bitfld.long 0x28 22. "CPU1_ROM_BYPASS_EN,Firmware Bypass Enable for cpu1 ROM Memories Power Down" "0,1"
newline
bitfld.long 0x28 21. "CPU1_ETB_BYPASS_EN,Firmware Bypass Enable for cpu1 ETB Memories Power Down" "0,1"
newline
bitfld.long 0x28 20. "CPU1_CACHE_BYPASS_EN,Firmware Bypass Enable for cpu1 cache Memories Power Down" "0,1"
newline
bitfld.long 0x28 19. "SMU0_BYPASS_EN,Firmware Bypass Enable for SMU0 Memories Power Down" "0,1"
newline
bitfld.long 0x28 17. "OTP_BYPASS_EN,Firmware Bypass Enable for OTP Power Down" "0,1"
newline
bitfld.long 0x28 7. "SSU_BYPASS_VAL,Firmware Bypass Value for SSU Memories Power Down" "0,1"
newline
bitfld.long 0x28 6. "CPU1_ROM_BYPASS_VAL,Firmware Bypass value for cpu1 ROM Memories Power Down" "0,1"
newline
bitfld.long 0x28 5. "CPU1_ETB_BYPASS_VAL,Firmware Bypass value for cpu1 ETB Memories Power Down" "0,1"
newline
bitfld.long 0x28 4. "CPU1_CACHE_BYPASS_VAL,Firmware Bypass value for cpu1 cache Memories Power Down" "0,1"
newline
bitfld.long 0x28 3. "SMU0_BYPASS_VAL,Firmware Bypass value for SMU0 Memories Power Down" "0,1"
newline
bitfld.long 0x28 1. "OTP_BYPASS_VAL,Firmware Bypass Value for OTP Power Down" "0,1"
group.long 0xB0++0x3
line.long 0x0 "SOCWLAPU_HOST_WKUP_SOURCE,Host Wakeup Source Control"
hexmask.long.word 0x0 0.--15. 1. "ENABLE,Enable/ disable value:"
group.long 0xC0++0x3
line.long 0x0 "SOCWLAPU_APU_IPS_PWR_CTRL_BYPASS0,APU IPS power control Bypass Register 0"
bitfld.long 0x0 1. "IPS_RAM_ROM_PD_BYPASS_EN,Firmware Bypass enable for IPS RAM/ROM PD from APU" "0,1"
newline
bitfld.long 0x0 0. "IPS_RAM_ROM_PD_BYPASS_VAL,Firmware Bypass value for IPS RAM/ROM PD from APU" "0,1"
tree.end
tree "WLCTRL"
base ad:0x41240000
rgroup.long 0x84++0x3
line.long 0x0 "CIU_CHIP_REV,CIU Revision"
hexmask.long.word 0x0 0.--15. 1. "CIU_IP_REVISION,CIU Revision Number"
group.long 0xFC++0xF
line.long 0x0 "CIU_CHIP_ECO_CTRL,Chip ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "CIU_CLK_ENABLE,Clock Enable"
bitfld.long 0x4 31. "CIU_WLAPU_DVFS_CLK_EN,APU DVFS Clock Enable" "0,1"
newline
bitfld.long 0x4 26. "MCU1_SYS_CLK_EN,MCU1 System Clock Enable" "0,1"
newline
bitfld.long 0x4 25. "WL_AHB2APB_HCLK_EN,Wireless AHB to APB Clock Enable" "0,1"
newline
bitfld.long 0x4 23. "MCU1_AHB_CLK_EN,MCU1 AHB Clock Enable" "0,1"
newline
bitfld.long 0x4 22. "EU1_CORE_CLK_EN,EU1 Core Clock Enable" "0,1"
newline
bitfld.long 0x4 20. "LBU1_LSBIF_CLK_EN,PBU Device Clock (PCLK) Enable" "0,1"
newline
bitfld.long 0x4 18. "MCI_LITE2AHB_HCLK_EN,Enable for mci lite2ahb module in wl_top" "0,1"
newline
bitfld.long 0x4 17. "IPS_PCLK_EN,Enable for ips apb clock" "0,1"
newline
bitfld.long 0x4 16. "IPS_CLK_EN,Enable for ips functional clock" "0,1"
newline
bitfld.long 0x4 15. "CIU_WLAPU_REF_CLK_EN,APU Reference Clock Enable" "0,1"
newline
bitfld.long 0x4 14. "CIU_WLAPU_CAL_CLK_EN,APU Calibration Clock Enable" "0,1"
newline
bitfld.long 0x4 13. "CIU_WLAPU_SLPCLK_EN,APU Sleep Clock Enable" "0,1"
newline
bitfld.long 0x4 12. "CIU_WLAPU_AHB_CLK_EN,APU AHB Clock Enable" "0,1"
newline
bitfld.long 0x4 11. "LBU1_AHB_CLK_EN,PBU AHB Clock Enable" "0,1"
newline
bitfld.long 0x4 10. "IPS_HCLK_EN,IPS AHB Clock Enable" "0,1"
newline
bitfld.long 0x4 9. "SMU1_AHB_CLK_EN,SMU1 AHB Clock Enable" "0,1"
newline
bitfld.long 0x4 8. "WLRTU1_AHB_CLK_EN,WLRTU1 AHB Clock Enable" "0,1"
newline
bitfld.long 0x4 6. "SMU1_DYN_CLK_GATING_DIS,SMU1 Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0x4 5. "CPU1_MEM_SLV_CLK_EN,CPU1 Memory Slave Clock Control Feature" "0,1"
newline
bitfld.long 0x4 4. "CPU1_FABRIC_CLK_EN,CPU1 Fabric Clock Control Feature" "0,1"
newline
bitfld.long 0x4 3. "CPU1_GATEHCLK_EN,CPU1 Gate HCLK Control Feature" "0,1"
newline
bitfld.long 0x4 0. "BIST_AHB1_CLK_GATING_EN,bist Clock gating for IMEM/DMEM/SMU1/ROM" "0,1"
line.long 0x8 "CIU_CLK_ENABLE2,Clock enable2"
bitfld.long 0x8 30. "SMU1_PORT0_SYS_CLK_EN,SMU1 Port 0 System Clock Enable" "0,1"
newline
bitfld.long 0x8 29. "SMU1_TOP_CLK_EN,SMU1 Top Clock Enable" "0,1"
newline
bitfld.long 0x8 28. "HPU1_CIU_CLK_EN,HPU1 CIU Clock Enable" "0,1"
newline
bitfld.long 0x8 27. "WEU_SYS_CLK_EN,WEU SYS Clock Enable" "0,1"
newline
bitfld.long 0x8 26. "WEU_AHB_CLK_EN,WEU AHB Clock Enable" "0,1"
newline
hexmask.long.byte 0x8 16.--20. 1. "BR_AHB1_CLK_EN,BRU AHB Clock Enable"
newline
bitfld.long 0x8 1. "IPS_PROM_DYN_CLK_DIS,ips ROM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0x8 0. "IPS_PROM_ADDR_MASK_DIS,ips prom ROM Address Mask Selection" "0,1"
line.long 0xC "CIU_CLK_ENABLE3,Clock Enable 3"
bitfld.long 0xC 31. "SMU1_MEM_SYS_CLK_EN,SMU1 mem banks and peripheral control logic Clock Enable" "0,1"
newline
bitfld.long 0xC 30. "MCI_A2A_CLK_EN,Enable Clock for MCI A2A" "0,1"
newline
hexmask.long.byte 0xC 16.--23. 1. "SMU1_BANK_SEG_CLK_EN,SMU1 bank segment Clock Enable"
newline
bitfld.long 0xC 15. "DTCM_AHB1_DYN_CLK_GATING_DIS,CPU1 DTCM/DMEM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0xC 14. "ITCM_AHB1_DYN_CLK_GATING_DIS,CPU1 ITCM/IMEM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0xC 13. "BRU_AHB1_DYN_CLK_GATING_DIS,CPU1 ROM Dynamic Clock Gating Feature" "0,1"
newline
bitfld.long 0xC 12. "BRU_AHB1_ADDR_MASK_DIS,CPU1 ROM Address Mask Selection" "0,1"
newline
bitfld.long 0xC 6. "WLRTU1_CLK_EN,Enable WL RTU1 timer clock" "0,1"
newline
bitfld.long 0xC 1. "WL_SOC_A2A_CLK_EN,Enable Clock for SOC A2A" "0,1"
newline
bitfld.long 0xC 0. "WL_MSC_A2A_CLK_EN,Enable Clock for MSC A2A" "0,1"
group.long 0x114++0x7
line.long 0x0 "CIU_CLK_CPU1CLK_CTRL,CPU1_AHB1 Clock Control"
hexmask.long.byte 0x0 0.--3. 1. "T1_FREQ_SEL,CPU1 Clock Frequency Select"
line.long 0x4 "CIU_CLK_SYSCLK_CTRL,SYS Clock Control"
hexmask.long.byte 0x4 0.--3. 1. "T1_FREQ_SEL,Sys Clock Frequency Select"
group.long 0x12C++0x1B
line.long 0x0 "CIU_CLK_RTU_NCO_CTRL,RTU NCO Clock Control"
hexmask.long.word 0x0 16.--31. 1. "CIU_WLRTU_NCO_STEP,Step size for RTU clock NCO (Reference Clock Based)"
newline
bitfld.long 0x0 2. "CIU_WLRTU_NCO_ENABLE,RTU NCO Enable (Reference Clock Based)" "0,1"
newline
bitfld.long 0x0 1. "CIU_WLRTU_NCO_OUT_SEL,RTU NCO Mode Select (Reference Clock Based)" "0,1"
newline
bitfld.long 0x0 0. "CIU_WLRTU_REF_CLK_SEL,RTU Reference Clock from UART reference clock tree" "0,1"
line.long 0x4 "CIU_CLK_LBU1_WLRTU_CTRL,LBU1 WLRTU1 Clock Control"
bitfld.long 0x4 15. "WLRTU1_DBG_CLK_CTRL,WLRTU1 Debug Clock Control Feature" "0,1"
newline
bitfld.long 0x4 12. "WLRTU1_USE_REF_CLK,Static bit set by FW. If it is required that timers need not be programmed with dynamic switching of T1/Reference the WL_RTU1 source clock is set on reference clock so that the timer are not disturbed." "0,1"
newline
bitfld.long 0x4 11. "WLRTU1_TIMER1_USE_SLP_CLK,Timer 1 WL_RTU1 Clock" "0,1"
newline
bitfld.long 0x4 7. "LBU1_DIV_BY_2_SEL,PBU Bus Reference Clock" "0,1"
newline
bitfld.long 0x4 6. "LBU1_HIGH_BAUD_SEL,PBU Bus Reference Clock" "0,1"
newline
bitfld.long 0x4 3.--5. "LBU1_CLK_SCALE_FACTOR,lbu1 lsb clock divider value[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 2. "LBU1_CLK_SCALE_EN,Enable lbu1 lsb clock div (upto div by 3/4/5/6 only)" "0,1"
newline
bitfld.long 0x4 1. "LBU1_USE_REFCLK,Static bit set by FW based on Reference Clock Frequency. If reference clock frequency is lower and LBU can not support high baud rate of UART then FW will set soc_use_ref_mode = 0. This is an indication for Bluetooth subsystem that there.." "0,1"
line.long 0x8 "CIU_CLK_SOCCLK_CTRL,SOC Clock Control"
hexmask.long.byte 0x8 28.--31. 1. "WL_AHB2APB_WAIT_CYCLES,WL AHB2APB Wait Cycles between each APB transaction"
newline
hexmask.long.byte 0x8 16.--19. 1. "WL_AHB2APB_PCLK_DIV_SEL,WL AHB2APB PCLK Divider Select"
newline
bitfld.long 0x8 14. "CIU_USE_REFCLK,SoC_Clk Clock" "0,1"
newline
bitfld.long 0x8 11. "CIU_WLAPU_CAL_CLK_SEL,PMU Calibration Clock" "0,1"
newline
bitfld.long 0x8 10. "CIU_WLAPU_CONST_CAL_CLK_SEL,PMU Constant Calibration Clock Select" "0,1"
newline
bitfld.long 0x8 0.--1. "EU1_CORE_CLK_SEL,EU1 Core Clock Select" "0,1,2,3"
line.long 0xC "CIU_CLK_SLEEPCLK_CTRL,Sleep Clock Control"
bitfld.long 0xC 28. "CIU_REFCLK_SLEEP_CLK_SEL,Reference Clock Sleep Clock Select" "0,1"
newline
bitfld.long 0xC 25. "CIU_NCO_SLEEP_CLK_SEL,NCO Sleep Clock Select" "0,1"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "CIU_SLEEP_CLK_NCO_MVAL,Sleep Clock NCO"
line.long 0x10 "CIU_CLK_CP15_DIS1,Clock Auto Shut-off Enable1"
bitfld.long 0x10 20. "CP15_DIS_WLAPU_AHB_CLK,APU Shut Off" "0,1"
newline
bitfld.long 0x10 18. "WLAN_HCLK,WLAN ahb Arbiter/Decoder Shut Off" "0,1"
line.long 0x14 "CIU_CLK_CP15_DIS2,Clock Auto Shut-off Enable2"
hexmask.long.byte 0x14 16.--20. 1. "CP15_DIS_CPU1_IMEM_CLK,APU Shut Off 0 = disable this auto shut off feature 1 = AHB clock for the IMEM is automatically shut off while CPU is asleep"
newline
bitfld.long 0x14 8.--9. "CP15_DIS_CPU1_DMEM_CLK,APU Shut Off" "0,1,2,3"
newline
hexmask.long.byte 0x14 0.--4. 1. "CP15_DIS_CPU1_BROM_CLK,APU Shut Off"
line.long 0x18 "CIU_CLK_CP15_DIS3,Clock Auto Shut-off Enable3"
bitfld.long 0x18 20. "CP15_DIS_WEU_AHB_CLK,TKIP/WEP WEU AHB Shut Off" "0,1"
group.long 0x14C++0x7
line.long 0x0 "CIU_CLK_ENABLE6,Clock Enable 6"
bitfld.long 0x0 14. "PTP_CLK_EN,PTP input capture pulse interrupt clock enable" "0,1"
newline
bitfld.long 0x0 13. "BBUD_MAC_CLK_SEL,BBUD MAC Clock Select" "0,1"
newline
bitfld.long 0x0 11. "MAC1_G2BIST_CLK_EN,Clock Enable for MAC1 BIST Controller Clock" "0,1"
newline
bitfld.long 0x0 10. "GPS_PPS_CLK_EN,GPS PPS Clock Enable" "0,1"
newline
bitfld.long 0x0 9. "CAU_SIF_AHB1_CLK_EN,CAU AHB2SIF AHB clock enable" "0,1"
newline
bitfld.long 0x0 8. "CAU_SIF_CLK_SEL,CAU SIF Clock Select" "0,1"
line.long 0x4 "CIU_CLK_SLEEPCLK_CTRL2,Sleep Clock Control 2"
bitfld.long 0x4 24. "CIU_SLEEP_CLK_NCO_MVAL_BYPASS,Sleep Clock NCO MVAL Bypass Feature" "0,1"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "CIU_SLEEP_CLK_NCO_MVAL_DURING_SLP,Sleep Clock NCO value for the sleep mode"
group.long 0x178++0xF
line.long 0x0 "CIU_MAC_CLK_CTRL,MAC clock CTRL"
bitfld.long 0x0 1.--2. "MAC1_BBUD_BYPASS_VAL,Bypass value" "0,1,2,3"
newline
bitfld.long 0x0 0. "MAC1_BBUD_BYPASS_EN,Bypass 11J_EN and PUB_SFT from BBUD1" "0,1"
line.long 0x4 "CIU_CLK_ECO_CTRL,Clock ECO Control"
hexmask.long 0x4 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x8 "CIU_RST_SW1,Software Module Reset"
bitfld.long 0x8 31. "MCU1_AHB_CLK_,MCU1 AHB Soft Reset" "0,1"
newline
bitfld.long 0x8 29. "EU1_CORE_CLK_,EU1 Core Soft Reset" "0,1"
newline
bitfld.long 0x8 28. "MCU1_MCLK_,MCU1 MCLK domain reset" "0,1"
newline
bitfld.long 0x8 27. "WLAPU_SLP_CLK_,APU Sleep Clock domain Reset" "0,1"
newline
bitfld.long 0x8 26. "WLAPU_AHB_CLK_,APU ARM Clock Reset" "0,1"
newline
bitfld.long 0x8 25. "RFU1_PR_,RFU1_PR Reset" "0,1"
newline
bitfld.long 0x8 24. "BBU1_DSP_,BBU1_DSP Reset" "0,1"
newline
bitfld.long 0x8 21. "WLAPU_REF_CLK_,APU ref Clock Reset" "0,1"
newline
bitfld.long 0x8 20. "LBU1_,LBU1 Soft Reset" "0,1"
newline
bitfld.long 0x8 19. "WL_AHB_RST_,WL AHB Decoder Mux and Arbiter and CIU AHB intf Soft Reset" "0,1"
newline
bitfld.long 0x8 16. "WL_AHB2APB_CLK_N,WL AHB2APB AHB clock domain reset" "0,1"
newline
bitfld.long 0x8 15. "MCU1_SYS_CLK_,MCU1 sysclk domain Soft Reset" "0,1"
newline
bitfld.long 0x8 11. "CIU1_REGISTER_RST_,CIU_Reg Module Soft Reset" "0,1"
newline
bitfld.long 0x8 10. "CIU1_CFG_RST_,//CIU ahb clock domain Soft Reset" "0,1"
newline
bitfld.long 0x8 9. "WEU_AHB_CLK_N,WEU ahb clock domain soft reset" "0,1"
newline
bitfld.long 0x8 8. "WEU_SYS_CLK_N,WEU sys clock domain soft reset" "0,1"
newline
bitfld.long 0x8 7. "SMU1_TM_RST_,SMU1 testmode logic reset" "0,1"
newline
bitfld.long 0x8 3. "SMU1_MEM_CLK_,SMU1 bank clock Soft Reset" "0,1"
newline
bitfld.long 0x8 2. "SMU1_PORT0_SYS_CLK_N,SMU1 port 0 (SYS_Clk) Soft Reset" "0,1"
newline
bitfld.long 0x8 0. "HPU1_,HPU1 Reset" "0,1"
line.long 0xC "CIU_RST_SW2,Software Module Reset"
bitfld.long 0xC 30. "CPU1_CORE_,CPU1 core reset" "0,1"
newline
bitfld.long 0xC 29. "WD1_CPU1_RST_DISABLE,CPU1 Reset Disable Feature" "0,1"
newline
bitfld.long 0xC 28. "WD1_CHIP_RST_DISABLE,WD1 Chip Reset Disable Feature" "0,1"
newline
bitfld.long 0xC 23. "APB_,APB core clock Soft Reset (TBD_TREEPIE may not need this)" "0,1"
newline
bitfld.long 0xC 22. "CPU1_TCM_,CPU1 TCM/DMA/Arbiter reset" "0,1"
newline
bitfld.long 0xC 19. "IPS_HCLK_,ips block hresetn" "0,1"
newline
bitfld.long 0xC 15. "WLAN_SUB_G2BIST_RSTB,SW reset for wlan sub-system g2bist controller" "0,1"
newline
bitfld.long 0xC 14. "IPS_PROM_CLK_,SW reset for ips_prom_clk" "0,1"
newline
bitfld.long 0xC 13. "IPS_CLK_,ips functional clock SW reset" "0,1"
newline
bitfld.long 0xC 3. "BRU_AHB1_CLK_,BRU_AHB1 Soft Reset" "0,1"
newline
bitfld.long 0xC 0. "W1_CLK_,W1 Interface (PM chip) Soft Reset" "0,1"
group.long 0x18C++0x7
line.long 0x0 "CIU_RST_SW4,Software Module Reset"
bitfld.long 0x0 26. "MCU1_SYS_CLK_RETENTION_,MCU1 sysclk domain Soft Retention Reset" "0,1"
newline
bitfld.long 0x0 25. "MCU1_MCLK_RETENTION_,MCU1 MCLK domain retention reset" "0,1"
newline
bitfld.long 0x0 24. "MCU1_AHB_CLK_RETENTION_,MCU1 AHB Soft Retention Reset" "0,1"
newline
bitfld.long 0x0 22. "WL_SYS_CLK_,WL SYS CLK Soft Reset (Not used in Rendfinch)" "0,1"
newline
bitfld.long 0x0 21. "WLM_SYS_CLK_,WLM SYS CLK Soft Reset" "0,1"
newline
bitfld.long 0x0 5. "CAU_SIF_AHB1_CLK_,CAU sif ahb1 Clock Soft Reset" "0,1"
newline
bitfld.long 0x0 4. "CAU_SIF_,CAU sif clock Soft Reset" "0,1"
newline
bitfld.long 0x0 3. "CPU1_G2BIST_,CPU1 g2bist soft reset" "0,1"
newline
bitfld.long 0x0 1. "CPU1_WATCHDOG_,CPU1 watchdog logic soft reset" "0,1"
newline
bitfld.long 0x0 0. "CPU1_DBG_,CPU1 debug logic soft reset." "0,1"
line.long 0x4 "CIU_RST_SW5,Software Module Reset"
bitfld.long 0x4 11. "PTP_RST_,SW reset for ptp input capture logic" "0,1"
newline
bitfld.long 0x4 10. "MCI_WL_A2A_MHRESETN,SW Reset for mci_wl_a2a_mhresetn" "0,1"
newline
bitfld.long 0x4 9. "GPS_PPS_RST_,SW Reset for the gps pss" "0,1"
newline
bitfld.long 0x4 8. "SMU1_UNGATED_CLK_RST_,SW reset for the NIC of smu1" "0,1"
newline
bitfld.long 0x4 7. "SMU1_CFG_RST_,SW reset for smu1 reg" "0,1"
newline
bitfld.long 0x4 6. "MCI_LITE2AHB_RST_,SW reset to mci lite2ahb in wl_top" "0,1"
newline
bitfld.long 0x4 5. "SMU1_AHB_RST_,SW reset for smu1 ahb" "0,1"
newline
bitfld.long 0x4 4. "WL_SOC_A2A_,SOC TOP a2a soft reset" "0,1"
newline
bitfld.long 0x4 3. "WL_MSC_A2A_,MSC a2a soft reset" "0,1"
group.long 0x1FC++0x3
line.long 0x0 "CIU_RST_ECO_CTRL,Reset ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,ECO Bits"
group.long 0x204++0x7
line.long 0x0 "CIU_MEM_WRTC2,Memory WRTC Control2"
bitfld.long 0x0 30.--31. "SMU1_SEG0_WTC,SMU1 SEG0 WTC" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "SMU1_SEG0_RTC,SMU1 SEG0 RTC" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "R2P_WTC,Small Dual Port SRAM WTC" "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "R2P_RTC,Small Dual Port SRAM RTC" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "R1P_WTC,Small Single Port SRAM WTC" "0,1,2,3"
newline
bitfld.long 0x0 16.--17. "R1P_RTC,Small Single Port SRAM RTC" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "SMU1_WTC,SMU1 SEG1 WTC" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "SMU1_RTC,SMU1 SEG1 RTC" "0,1,2,3"
line.long 0x4 "CIU_MEM_WRTC3,Memory WRTC Control 3"
bitfld.long 0x4 30.--31. "IPS_PROM_RTC_REF,IPS PROM RTC_REF" "0,1,2,3"
newline
bitfld.long 0x4 27.--29. "IPS_PROM_RTC,IPS PROM RTC" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 25.--26. "IPS_PRAM_WTC,IPS PRAM WTC" "0,1,2,3"
newline
bitfld.long 0x4 23.--24. "IPS_PRAM_RTC,IPS PRAM RTC" "0,1,2,3"
newline
bitfld.long 0x4 21.--22. "IPS_IRAM_WTC,IPS IRAM WTC" "0,1,2,3"
newline
bitfld.long 0x4 19.--20. "IPS_IRAM_RTC,IPS IRAM RTC" "0,1,2,3"
newline
bitfld.long 0x4 17.--18. "CPU1_ROM_RTC_REF,Cpu1 ROM RTC_REF" "0,1,2,3"
newline
bitfld.long 0x4 14.--16. "CPU1_ROM_RTC,CPU1 ROM RTC" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12.--13. "CPU1_DTCM_WTC,CPU1 DTCM WTC" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "CPU1_DTCM_RTC,CPU1 DTCM RTC" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "CPU1_ITCM_WTC,CPU1 ITCM WTC" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "CPU1_ITCM_RTC,CPU1 ITCM RTC" "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "WEU_ROM_RTC_REF,WEU 256x16 ROM RTC_REF" "0,1,2,3"
newline
bitfld.long 0x4 0.--2. "WEU_ROM_RTC,WEU 256x15 ROM RTC" "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x0 "CIU_MEM_CTRL,Memory Control"
bitfld.long 0x0 5. "SMU1_DEBUG_ON,1= enable smu internal register latch for debug" "?,1: enable smu internal register latch for debug"
rgroup.long 0x220++0xB
line.long 0x0 "CIU_SMU1_DBG_STAT0,SMU1 debug register0"
hexmask.long 0x0 0.--31. 1. "SMU1_DBG_STAT0,smu1 debug addr output"
line.long 0x4 "CIU_SMU1_DBG_STAT1,SMU1 debug register1"
hexmask.long 0x4 0.--31. 1. "SMU1_DBG_STAT1,smu1 debug data output"
line.long 0x8 "CIU_SMU1_DBG_STAT2,SMU1 debug register2"
hexmask.long 0x8 0.--31. 1. "SMU1_DBG_STAT2,smu1 debug ctrl output"
group.long 0x27C++0xF
line.long 0x0 "CIU_MEM_ECO_CTRL,Memory ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "CIU1_INT_MASK,CIU1 Interrupt Mask"
hexmask.long.word 0x4 16.--31. 1. "APU_INTR_HOST_WAKEUP,APU Host wakeup interrupt"
newline
bitfld.long 0x4 15. "APU_INTR_WAKEUP,APU default interrupt. The purpose of this interrupt is to catch any erroneous host wakeup case. In the event of an erroneous host wakeup it is possible that the host wakeup interrupt will not assert. In order to ensure that the APU does.." "0,1"
newline
bitfld.long 0x4 14. "APU_INTR_GEN_TIMER_WAKEUP,APU beacon Timer wakeup interrupt" "0,1"
newline
bitfld.long 0x4 13. "APU_INTR_WLAN_WAKEUP1,APU WLAN1 interrupt. This bit indicates that the WLAN hardware needs to wakeup for an incoming beacon. During WLAN wake time this interrupt path should not be taken. Refer to APU doc for more details on the sleep/wakeup interrupt.." "0,1"
newline
bitfld.long 0x4 12. "APU_INTR_BT_WAKEUP,APU BT interrupt. This bit indicates that the BTU has encountered some event during hardware sleep and would like the firmware to intervene. During BT wake time this interrupt path should not be taken. Refer to APU doc for more.." "0,1"
newline
bitfld.long 0x4 11. "GPS_INTR_CH_SW,GPS PPS timer interrupt" "0,1"
newline
bitfld.long 0x4 10. "GPS_INTR_CH_SW_EARLY,GPS PPS timer early interrupt" "0,1"
newline
bitfld.long 0x4 9. "RFU_INT_5G_A,RFU5G channel A interrupt" "0,1"
newline
bitfld.long 0x4 8. "RFU_INT_2G,RFU2G interrupt" "0,1"
newline
bitfld.long 0x4 7. "IMU12_CPU1_MSG_SPACE_AVAIL_IMU,CPU1 to CPU2 message FIFO space available for CPU1 to write more messages.(Not used)" "0,1"
newline
bitfld.long 0x4 6. "CPU1_TO_CPU2_MSG_DONE,CPU1 to CPU2 Message Done Interrupt. After CPU2 completed message processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU2_MSG_CTRL[8]" "0,1"
newline
bitfld.long 0x4 5. "IMU13_CPU1_MSG_SPACE_AVAIL_IMU,CPU1 to CPU3 message FIFO space available for CPU1 to write more messages. (Not used)" "0,1"
newline
bitfld.long 0x4 4. "CPU1_TO_CPU3_MSG_DONE,CPU1 to CPU3 Message Done Interrupt. After CPU3 completed message processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU3_MSG_CTRL[8]" "0,1"
newline
bitfld.long 0x4 2.--3. "MCI_WL_WAKEUP_DONE_INT,Wake up Interrupt done from MCI (CPU3) to WL (CPU1)" "0,1,2,3"
newline
bitfld.long 0x4 1. "PTP_INPUTCAPTURE_EVENT_INTR,PTP Input Capture Event Interrupt for Time Synchronization. In case of PTP mode input capture pulse from PAD or HMAC is used to latched PHC Value inside BBUD. On receiving this interrupt SW will read the PHC timestamp Value.." "0,1"
line.long 0x8 "CIU1_INT_SELECT,CIU1 Interrupt Select"
hexmask.long 0x8 0.--31. 1. "SEL,Interrupt Read/Write Clear for CIU1 Interrupts"
line.long 0xC "CIU1_INT_EVENT_MASK,CIU1 Interrupt Event Mask"
hexmask.long.word 0xC 16.--31. 1. "APU_INTR_HOST_WAKEUP,APU Host wakeup interrupt"
newline
bitfld.long 0xC 15. "APU_INTR_WAKEUP,APU default interrupt. The purpose of this interrupt is to catch any erroneous host wakeup case. In the event of an erroneous host wakeup it is possible that the host wakeup interrupt will not assert. In order to ensure that the APU does.." "0,1"
newline
bitfld.long 0xC 14. "APU_INTR_GEN_TIMER_WAKEUP,APU beacon Timer wakeup interrupt" "0,1"
newline
bitfld.long 0xC 13. "APU_INTR_WLAN_WAKEUP1,APU WLAN1 interrupt. This bit indicates that the WLAN hardware needs to wakeup for an incoming beacon. During WLAN wake time this interrupt path should not be taken. Refer to APU doc for more details on the sleep/wakeup interrupt.." "0,1"
newline
bitfld.long 0xC 12. "APU_INTR_BT_WAKEUP,APU BT interrupt. This bit indicates that the BTU has encountered some event during hardware sleep and would like the firmware to intervene. During BT wake time this interrupt path should not be taken. Refer to APU doc for more.." "0,1"
newline
bitfld.long 0xC 11. "GPS_INTR_CH_SW,GPS PPS timer interrupt" "0,1"
newline
bitfld.long 0xC 10. "GPS_INTR_CH_SW_EARLY,GPS PPS timer early interrupt" "0,1"
newline
bitfld.long 0xC 9. "RFU_INT_5G_A,RFU5G channel A interrupt" "0,1"
newline
bitfld.long 0xC 8. "RFU_INT_2G,RFU2G interrupt" "0,1"
newline
bitfld.long 0xC 7. "IMU12_CPU1_MSG_SPACE_AVAIL_IMU,CPU1 to CPU2 message FIFO space available for CPU1 to write more messages.(Not used)" "0,1"
newline
bitfld.long 0xC 6. "CPU1_TO_CPU2_MSG_DONE,CPU1 to CPU2 Message Done Interrupt. After CPU2 completed message processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU2_MSG_CTRL[8]" "0,1"
newline
bitfld.long 0xC 5. "IMU13_CPU1_MSG_SPACE_AVAIL_IMU,CPU1 to CPU3 message FIFO space available for CPU1 to write more messages. (Not used)" "0,1"
newline
bitfld.long 0xC 4. "CPU1_TO_CPU3_MSG_DONE,CPU1 to CPU3 Message Done Interrupt. After CPU3 completed message processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU3_MSG_CTRL[8]" "0,1"
newline
bitfld.long 0xC 2.--3. "MCI_WL_WAKEUP_DONE_INT,Wake up Interrupt done from MCI (CPU3) to WL (CPU1)" "0,1,2,3"
newline
bitfld.long 0xC 1. "PTP_INPUTCAPTURE_EVENT_INTR,PTP Input Capture Event Interrupt for Time Synchronization. In case of PTP mode input capture pulse from PAD or HMAC is used to latched PHC Value inside BBUD. On receiving this interrupt SW will read the PHC timestamp Value.." "0,1"
rgroup.long 0x28C++0x3
line.long 0x0 "CIU1_INT_STATUS,CIU1 Interrupt Status"
hexmask.long.word 0x0 16.--31. 1. "APU_INTR_HOST_WAKEUP,APU Host wakeup interrupt"
newline
bitfld.long 0x0 15. "APU_INTR_WAKEUP,APU default interrupt. The purpose of this interrupt is to catch any erroneous host wakeup case. In the event of an erroneous host wakeup it is possible that the host wakeup interrupt will not assert. In order to ensure that the APU does.." "0,1"
newline
bitfld.long 0x0 14. "APU_INTR_GEN_TIMER_WAKEUP,APU beacon Timer wakeup interrupt" "0,1"
newline
bitfld.long 0x0 13. "APU_INTR_WLAN_WAKEUP1,APU WLAN1 interrupt. This bit indicates that the WLAN hardware needs to wakeup for an incoming beacon. During WLAN wake time this interrupt path should not be taken. Refer to APU doc for more details on the sleep/wakeup interrupt.." "0,1"
newline
bitfld.long 0x0 12. "APU_INTR_BT_WAKEUP,APU BT interrupt. This bit indicates that the BTU has encountered some event during hardware sleep and would like the firmware to intervene. During BT wake time this interrupt path should not be taken. Refer to APU doc for more.." "0,1"
newline
bitfld.long 0x0 11. "GPS_INTR_CH_SW,GPS PPS timer interrupt" "0,1"
newline
bitfld.long 0x0 10. "GPS_INTR_CH_SW_EARLY,GPS PPS timer early interrupt" "0,1"
newline
bitfld.long 0x0 9. "RFU_INT_5G_A,RFU5G channel A interrupt" "0,1"
newline
bitfld.long 0x0 8. "RFU_INT_2G,RFU2G interrupt" "0,1"
newline
bitfld.long 0x0 7. "IMU12_CPU1_MSG_SPACE_AVAIL_IMU,CPU1 to CPU2 message FIFO space available for CPU1 to write more messages.(Not used)" "0,1"
newline
bitfld.long 0x0 6. "CPU1_TO_CPU2_MSG_DONE,CPU1 to CPU2 Message Done Interrupt. After CPU2 completed message processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU2_MSG_CTRL[8]" "0,1"
newline
bitfld.long 0x0 5. "IMU13_CPU1_MSG_SPACE_AVAIL_IMU,CPU1 to CPU3 message FIFO space available for CPU1 to write more messages. (Not used)" "0,1"
newline
bitfld.long 0x0 4. "CPU1_TO_CPU3_MSG_DONE,CPU1 to CPU3 Message Done Interrupt. After CPU3 completed message processing requested by CPU1 it sends this interrupt to CPU1 by set 1 to CIU_CPU_CPU3_MSG_CTRL[8]" "0,1"
newline
bitfld.long 0x0 2.--3. "MCI_WL_WAKEUP_DONE_INT,Wake up Interrupt done from MCI (CPU3) to WL (CPU1)" "0,1,2,3"
newline
bitfld.long 0x0 1. "PTP_INPUTCAPTURE_EVENT_INTR,PTP Input Capture Event Interrupt for Time Synchronization. In case of PTP mode input capture pulse from PAD or HMAC is used to latched PHC Value inside BBUD. On receiving this interrupt SW will read the PHC timestamp Value.." "0,1"
group.long 0x290++0xF
line.long 0x0 "CIU_INT_HOST_CTRL,Host Interrupt Control"
bitfld.long 0x0 0. "UART_RX_IDLE_STATE_DETECT_MODE,UART Rx IDLE State Detection Mode." "0,1"
line.long 0x4 "CIU_BCA1_INT_MASK,BCA1 to CPU1 Interrupt Mask"
hexmask.long 0x4 0.--31. 1. "IMR,Interrupt Mask for BCA1 to CPU1 Interrupts"
line.long 0x8 "CIU_BCA1_INT_SELECT,BCA1 to CPU1 Interrupt Select"
hexmask.long 0x8 0.--31. 1. "RSR,Interrupt Read/Write Clear for BCA1 to CPU1 Interrupts"
line.long 0xC "CIU_BCA1_INT_EVENT_MASK,BCA1 to CPU1 Interrupt Event Mask"
hexmask.long 0xC 0.--31. 1. "SMR,Interrupt Event Mask for BCA1 to CPU1 Interrupts"
rgroup.long 0x2A0++0x3
line.long 0x0 "CIU_BCA1_INT_STATUS,BCA1 to CPU1 Interrupt Status"
hexmask.long 0x0 0.--31. 1. "ISR,BCA1 to CPU1 Interrupt Status"
group.long 0x2B4++0xB
line.long 0x0 "CPU1_ERR_INT_MASK,CPU1 ERR Interrupt Mask"
hexmask.long 0x0 0.--31. 1. "MASK,Interrupt Mask for CPU1 ERR Interrupts"
line.long 0x4 "CPU1_ERR_INT_SELECT,CPU1 ERR Interrupt Clear Select"
hexmask.long 0x4 0.--31. 1. "SEL,Interrupt Read/Write Clear for CPU1 ERR Interrupts"
line.long 0x8 "CPU1_ERR_INT_EVENT_MASK,CPU1 ERR Interrupt Event Mask"
hexmask.long 0x8 0.--31. 1. "MASK,Interrupt Event Mask for CPU1 ERR Interrupts"
rgroup.long 0x2C0++0x3
line.long 0x0 "CPU1_ERR_INT_STATUS,CPU1 ERR Interrupt Status"
hexmask.long 0x0 0.--31. 1. "ERR_ISR,CPU1 ERR Interrupt Status (ISR)"
group.long 0x2E4++0x3
line.long 0x0 "CPU2_INT_CTRL,CPU2 INT control"
bitfld.long 0x0 0. "CPU2_SW_INT,SW programmed interrupt register for cpu2. write 1 to generate interrupt to CPU2." "0,1"
group.long 0x2F8++0xB
line.long 0x0 "CPU3_INT_CTRL,CPU3 INT control"
hexmask.long.byte 0x0 0.--3. 1. "CPU1_CPU3_GP_INT,SW programmed interrupt register for cpu3. write 1 to generate interrupt to CPU3."
line.long 0x4 "CIU_INT_ECO_CTRL,Interrupt ECO Control"
hexmask.long 0x4 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x8 "CIU_PTP_CTRL,Vsensor and Vreg Pad Control"
hexmask.long.byte 0x8 0.--7. 1. "MODE_EN,PTP mode enable in iomux (bitwise)"
group.long 0x3A0++0x7
line.long 0x0 "CIU_RFU_DBC_MUX_SEL,RFU related DBC mux selection for different mode"
bitfld.long 0x0 31. "BRF_TXPWR_SEL,SOC_BRF_PE1/2_2G and SOC_BRF_TXPWR_2G selection" "0,1"
newline
bitfld.long 0x0 27.--28. "BBUD1_TRX_RDY_B_SEL,bbud1_RFU_RDY_E and bbud1_RFU_INC_CAL_E selection" "0,1,2,3"
newline
bitfld.long 0x0 25.--26. "BBUD2_TRX_RDY_SEL,bbud2_RFU_RDY and bbud2_RFU_INC_CAL selection" "0,1,2,3"
newline
bitfld.long 0x0 23.--24. "BBUD1_TRX_RDY_A_SEL,bbud1_RFU_RDY_A and bbud1_RFU_INC_CAL_A selection" "0,1,2,3"
newline
bitfld.long 0x0 22. "RFU2G_B_MUX16_SEL_1,RFU 2G path B other input selection from two mac" "0,1"
newline
bitfld.long 0x0 21. "RFU2G_A_MUX15_SEL_1,RFU 2G path A other input selection from two mac" "0,1"
newline
bitfld.long 0x0 20. "RFU5G_B_MUX14_SEL_1,RFU 5G path B other input selection from two mac" "0,1"
newline
bitfld.long 0x0 19. "RFU5G_A_MUX13_SEL_1,RFU 5G path A other input selection from two mac" "0,1"
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bitfld.long 0x0 17.--18. "RFU2G_B_MUX16_SEL_0,RFU 2G path B PE1/PE2/PAPE input selection from two mac" "0,1,2,3"
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bitfld.long 0x0 15.--16. "RFU2G_A_MUX15_SEL_0,RFU 2G path A PE1/PE2/PAPE input selection from two mac" "0,1,2,3"
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bitfld.long 0x0 13.--14. "RFU5G_B_MUX14_SEL_0,RFU 5G path B PE1/PE2/PAPE input selection from two mac" "0,1,2,3"
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bitfld.long 0x0 11.--12. "RFU5G_A_MUX13_SEL_0,RFU 5G path A PE1/PE2/PAPE input selection from two mac" "0,1,2,3"
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bitfld.long 0x0 10. "BBUD2_A_MUX8_SEL,bbud2 path A input selection from two RFU" "0,1"
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bitfld.long 0x0 9. "BBUD2_B_MUX7_SEL,bbud2 path B input selection from two RFU" "0,1"
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bitfld.long 0x0 8. "BBUD1_B_MUX6_SEL,bbud1 path B input selection from two RFU" "0,1"
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bitfld.long 0x0 7. "BBUD1_A_MUX5_SEL,bbud1 path A input selection from two RFU" "0,1"
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bitfld.long 0x0 6. "RFU2G_B_MUX4_SEL,RFU 2G path B input selection from two bbud" "0,1"
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bitfld.long 0x0 5. "RFU2G_A_MUX3_SEL,RFU 2G path A input selection from two bbud" "0,1"
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bitfld.long 0x0 4. "RFU5G_B_MUX2_SEL,RFU 5G path B input selection from two bbud" "0,1"
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bitfld.long 0x0 3. "RFU5G_A_MUX1_SEL,RFU 5G path A input selection from two bbud" "0,1"
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bitfld.long 0x0 2. "RFU5G_B_MUX18_SEL,RFU 5G path B input selection from two bca" "0,1"
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bitfld.long 0x0 1. "RFU5G_A_MUX17_SEL,RFU 5G path A input selection from two bca" "0,1"
line.long 0x4 "CIU_BCA_DBC_MUX_SEL,BCA related DBC mux selection for different mode"
bitfld.long 0x4 9. "BCA2_EPA_BYPASS_SEL,bca2 epa_bypass signal selction from two RFU" "0,1"
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bitfld.long 0x4 8. "BCA1_EPA_BYPASS_SEL,bca1 epa_bypass signal selction from two RFU" "0,1"
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bitfld.long 0x4 6.--7. "BCA2_MUX20_SEL,bca2 ros cal input selection from two RFU" "0,1,2,3"
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bitfld.long 0x4 4.--5. "BCA1_MUX19_SEL,bca1 ros cal input selection from two RFU" "0,1,2,3"
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bitfld.long 0x4 3. "MCU2_MUX10_SEL,mcu2 input selection from two bca" "0,1"
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bitfld.long 0x4 2. "MCU1_MUX9_SEL,mcu1 input selection from two bca" "0,1"
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bitfld.long 0x4 1. "BCA2_MUX12_SEL,bca2 input selection from two mcu" "0,1"
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bitfld.long 0x4 0. "BCA1_MUX11_SEL,bca1 input selection from two mcu" "0,1"
rgroup.long 0x400++0xB
line.long 0x0 "CIU_TST_G2BIST_STATUS,WL G2BIST Status"
bitfld.long 0x0 5. "MAC1_G2B_FINISH,MAC1 Bist Done" "0,1"
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bitfld.long 0x0 4. "WL_G2B_FINISH,WL Bist Done" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "WL_G2B_STATUS,Redundant Bist Selection"
line.long 0x4 "CIU_TST_MBIST_READY,MBIST Status (BIST_READY)"
hexmask.long 0x4 0.--31. 1. "BIST_READY,Bist ready[31:0]"
line.long 0x8 "CIU_TST_MBIST_FAIL,MBIST Status (BIST_FAIL)"
hexmask.long 0x8 0.--31. 1. "BIST_FAIL,Bist Fail[31:0]"
group.long 0x428++0x3
line.long 0x0 "CIU_TST_TSTBUS_CTRL2,Testbux Mux Control2"
hexmask.long.byte 0x0 3.--7. 1. "SMU_DEBUG_SEL,SMU1/SMU2 Debug Select"
group.long 0x430++0x3
line.long 0x0 "CIU_TST_CTRL,Test Control"
bitfld.long 0x0 21. "BBU_TEST_MODE_EN,Baseband Test Mode Enable" "0,1"
group.long 0x47C++0x3
line.long 0x0 "CIU_TST_ECO_CTRL,Test ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0x500++0xB
line.long 0x0 "CIU_GPS_GPIO_MASK,GPS GPIO MASK"
hexmask.long 0x0 0.--31. 1. "GPIO2GPS_PPS_MASK,gpio to gps pps mask. '1' is to enable the gpio bit as PPS. Only 1 bit can be set"
line.long 0x4 "CIU_GPS_SW_PERIOD,GPS SWITCH CHANNEL PERIOD"
hexmask.long.tbyte 0x4 0.--20. 1. "CH_SW_PERIOD,period for channel switch. default to 50 ms"
line.long 0x8 "CIU_GPS_SW_EARLY,GPS SWITCH CHANNEL EARLY"
hexmask.long.word 0x8 0.--15. 1. "CH_SW_EARLY_TIME,time offset from switch channel. default to 1 ms"
rgroup.long 0x50C++0x3
line.long 0x0 "CIU_GPS_TMR_RD,GPS TIMER READ"
hexmask.long.tbyte 0x0 0.--21. 1. "GPS_PPS_TMR_STATUS,gps pps timer status read"
group.long 0x97C++0x3
line.long 0x0 "CIU_LDO_ECO_CTRL,LDO ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0x998++0xB
line.long 0x0 "CIU_AXI_CLK_CTRL2,AXI clk bypass contrl2"
bitfld.long 0x0 9. "WLM_GPV_CG_BYPASS_EN,wlm_gpv_cg_bypass_en" "0,1"
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bitfld.long 0x0 8. "WLM_GPV_CG_BYPASS_VAL,wlm_gpv_cg_bypass_val" "0,1"
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bitfld.long 0x0 7. "WLM_S_WL_CG_BYPASS_EN,wlm_soc_wl_cg_bypass_en" "0,1"
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bitfld.long 0x0 6. "WLM_S_WL_CG_BYPASS_VAL,wlm_soc_wl_cg_bypass_val" "0,1"
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bitfld.long 0x0 5. "WLM_MCU1_64B_CG_BYPASS_EN,AXI Dynamic Clock gating Bypass for HMAC" "0,1"
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bitfld.long 0x0 4. "WLM_MCU1_64B_CG_BYPASS_VAL,AXI Clock gate enable value for HMAC if bypass is enable." "0,1"
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bitfld.long 0x0 3. "WLM_M_TBUS_CG_BYPASS_EN,AXI Dynamic Clock gating Bypass for BBUd SQU Testbus master" "0,1"
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bitfld.long 0x0 2. "WLM_M_TBUS_CG_BYPASS_VAL,AXI Clock gate enable value if bypass is enable." "0,1"
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bitfld.long 0x0 1. "WLM_M_WIP_CG_BYPASS_EN,AXI Dynamic Clock gating Bypass for WEU" "0,1"
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bitfld.long 0x0 0. "WLM_M_WIP_CG_BYPASS_VAL,AXI Clock gate enable value if bypass is enable." "0,1"
line.long 0x4 "CIU_FABRIC_TESTBUS_CTRL,fabric(scm. wlm) testbus select"
hexmask.long.byte 0x4 24.--29. 1. "WLM_LOW_TESTBUS_SEL,testbus select for smu1_nic_testbus[7:0]"
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hexmask.long.byte 0x4 16.--21. 1. "WLM_HIGH_TESTBUS_SEL,testbus select for smu1_nic_testbus[15:8]"
line.long 0x8 "CIU_FABRIC_CREQ_DLY_TIMER,fabric(scm. wlm) delay timer for c_req"
hexmask.long.word 0x8 20.--29. 1. "WLM_CREQ_DLY_TIMER,wlm delay timer for c_req"
group.long 0x9FC++0x7
line.long 0x0 "CIU_ABU_ECO_CTRL,ABU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "CIU1_AHB1_TO_CLEAR,AHB1 timeout logic clear register"
bitfld.long 0x4 2. "CPU1_ICODE_INV_ADDR_CLR,After the invalid address int happened on CPU1 icode bus the cpu1 will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the CPU1 Icode invalid addr logic to start recroding next.." "0,1"
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bitfld.long 0x4 1. "CPU1_DCODE_INV_ADDR_CLR,After the invalid address int happened on CPU1 dcode bus the cpu1 will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the CPU1 Dcode invalid addr logic to start recroding next.." "0,1"
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bitfld.long 0x4 0. "AHB1_TIMEOUT_CLEAR,After the timeout happened on AHB1 bus the cpu will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1 to clear the AHB1 timeout logic to start recroding next transaction. This is self clearing.." "0,1"
rgroup.long 0xA04++0x7
line.long 0x0 "CIU_ARB_TO_LAST_ADDR,AHB Timeout Last Address"
hexmask.long 0x0 0.--31. 1. "ADDRESS,Last AHB1 Address Right Before the Current Timeout"
line.long 0x4 "CIU_ARB_TO_CUR_ADDR,AHB Current Timeout Address"
hexmask.long 0x4 0.--31. 1. "ADDRESS,Current_TO_Addr"
group.long 0xA0C++0x3
line.long 0x0 "CIU_ARB_CTRL,AHB ARB Control"
bitfld.long 0x0 30.--31. "ARB_TIMEOUT_MODE,AHB1_TimeoutMode[1:0]" "0,1,2,3"
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bitfld.long 0x0 19. "AHB1_A2A_PROT_DIS,1 = Disable A2A Memory Protection from AHB1 side and allow AHB1 to A2A" "?,1: Disable A2A Memory Protection from AHB1 side and.."
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bitfld.long 0x0 18. "AHB1_CPU1_DMEM_PROT_DIS,1 = Disable CPU1 Dmem Memory Protection from AHB1 side and allow AHB1 to read/write Dmem" "?,1: Disable CPU1 Dmem Memory Protection from AHB1.."
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bitfld.long 0x0 17. "AHB1_CPU1_IMEM_PROT_DIS,1 = Disable CPU1 Imem Memory Protection from AHB1 side and allow AHB1 to read/write Imem" "?,1: Disable CPU1 Imem Memory Protection from AHB1.."
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bitfld.long 0x0 16. "AHB1_SMU1_MEM_PROT_DIS,Disable SMU1 Memory Protection from AHB2 side" "0,1"
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rbitfld.long 0x0 11.--13. "LAST_TO_MASTER_ID,Last_TO_Master_ID" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 8.--10. "CURRENT_TO_MASTER_ID,Current_TO_Master_ID" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 4.--7. 1. "LAST_TO_SLAVE_ID,Last_TO_Slave_ID"
newline
hexmask.long.byte 0x0 0.--3. 1. "CURRENT_TO_SLAVE_ID,Current_TO_Slave_ID"
group.long 0xA54++0x3
line.long 0x0 "CIU1_CPU1_ICODE_INV_ADDR_CTRL,CPU1 Icode invalid address access control"
bitfld.long 0x0 30.--31. "HADDR_ICOD_SEL,There are 3 haddr which can be observed by selecting this:" "0,1,2,3"
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hexmask.long.byte 0x0 8.--11. 1. "CUR_INV_ADDR_SLAVE_ID,Cur_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 4.--7. 1. "LAST_INV_ADDR_SLAVE_ID,Last_inv_addr_Slave_ID"
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hexmask.long.byte 0x0 0.--3. 1. "LAST2_INV_ADDR_SLAVE_ID,Last2_inv_addr_Slave_ID"
rgroup.long 0xA58++0x3
line.long 0x0 "CIU1_CPU1_ICODE_INV_ADDR,CPU1 Icode invalid address"
hexmask.long 0x0 0.--31. 1. "HADDR_INV_ADDR,based on CIU1_CPU1_ICODE_INV_ADDR_CTRL[31:30] the address status is observed in this register"
group.long 0xA5C++0x3
line.long 0x0 "CIU1_CPU1_DCODE_INV_ADDR_CTRL,CPU1 Dcode invalid address access control"
bitfld.long 0x0 30.--31. "HADDR_DCOD_SEL,There are 3 haddr which can be observed by selecting this:" "0,1,2,3"
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hexmask.long.byte 0x0 20.--23. 1. "CUR_INV_ADDR_MASTER_ID,Cur_inv_addr_master_ID"
newline
hexmask.long.byte 0x0 16.--19. 1. "LAST_INV_ADDR_MASTER_ID,Last_inv_addr_master_ID"
newline
hexmask.long.byte 0x0 12.--15. 1. "LAST2_INV_ADDR_MASTER_ID,Last2_inv_addr_master_ID"
newline
hexmask.long.byte 0x0 8.--11. 1. "CUR_INV_ADDR_SLAVE_ID,Cur_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 4.--7. 1. "LAST_INV_ADDR_SLAVE_ID,Last_inv_addr_Slave_ID"
newline
hexmask.long.byte 0x0 0.--3. 1. "LAST2_INV_ADDR_SLAVE_ID,Last2_inv_addr_Slave_ID"
rgroup.long 0xA60++0x3
line.long 0x0 "CIU1_CPU1_DCODE_INV_ADDR,CPU1 Dcode invalid address"
hexmask.long 0x0 0.--31. 1. "HADDR_INV_ADDR,based on CIU1_CPU1_DCODE_INV_ADDR_CTRL[31:30] the address status is observed in this register"
group.long 0xA64++0xF
line.long 0x0 "CIU1_AHB2AHB_BRIDGE_CTRL,AHB2AHB Bridge Control Register"
bitfld.long 0x0 1. "MCI_WL_A2A_PREFETCH_EN,MCI-WL ahb2ahb bridge pre-fetch hsel enable" "0,1"
newline
bitfld.long 0x0 0. "PREFETCH_HSEL_EN,ahb2ahb bridge pre-fetch hsel enable" "0,1"
line.long 0x4 "WL_RAACS_CTRL,RAACS control registers"
hexmask.long.word 0x4 19.--31. 1. "RAACS_IDLE_COUNTER_VALUE,IDLE time for which RAACS-FSM waits before shifting to next successive scaled clock."
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hexmask.long.word 0x4 5.--18. 1. "RAACS_WAIT_COUNTER_VALUE,initial IDLE-time for which RAACS FSM waits before starting to scale down the clock."
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bitfld.long 0x4 2.--4. "RAACS_CLK_SEL,defines the lowest clock to which RAACS will go down to during IDLE period (x/2; x/4; x/8; ... ;x/128) for the given test." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 1. "USE_RAACS_CLK_FOR_CPU,SW write 0 to use RAACS clock for CPU. SW write 1 to select clock gating based alternate implementation of RAACS clocking for CM3 CPU." "0,1"
newline
bitfld.long 0x4 0. "RAACS_EN,raacs en . S/W Write 1 to enable raacs block." "0,1"
line.long 0x8 "WL_RAACS_PERFORMANCE_STATISTICS,RAACS performance statistics counter."
hexmask.long 0x8 1.--27. 1. "RAACS_PERFORMANCE_STATISTICS,This counter is maintaining RAACS performance count. This counter will increment by one after every 1 us(1MHZ) when RAACS is in scaled clk state."
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bitfld.long 0x8 0. "PERFORMANCE_STATISTICS_CNT_EN,performance counter en. S/W write 1 to enable performance counter." "0,1"
line.long 0xC "CIU_AHB1_TSTBUS_SEL,AHB1 Control Signals testbus select"
bitfld.long 0xC 0. "AHB1_TSTBUS_SEL,Select AHB1 Arbiter Testbus for testing" "0,1"
group.long 0xA7C++0x3
line.long 0x0 "CIU_ARB_ECO_CTRL,ARB ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0xA88++0x3
line.long 0x0 "CIU_CPU_DYN_CLK_CTRL,Dynamic CPU Clock Control"
bitfld.long 0x0 29. "DYN_SYS_CTRL_DIS,Disable Dynamic SYS Clock Control Feature" "0,1"
newline
bitfld.long 0x0 28. "DYN_CPU1_CTRL_DIS,Disable Dynamic CPU1 Clock Control Feature" "0,1"
rgroup.long 0xA98++0x7
line.long 0x0 "CIU_CPU_DYN_CPUCLK_MONITOR,Dynamic ahb clock Monitor"
hexmask.long.byte 0x0 0.--3. 1. "DYN_CPU1_CLK_MON_T1,Dynamic CPU1 Clock Monitor T1"
line.long 0x4 "CIU_CPU_DYN_SYSCLK_MONITOR,Dynamic sysclk Monitor"
hexmask.long.byte 0x4 0.--3. 1. "DYN_SYSCLK_MON_T1,Dynamic System Clock Monitor T1"
group.long 0xAB0++0x3
line.long 0x0 "CIU_CPU_CPU1_CTRL,CPU1 control register"
bitfld.long 0x0 31. "CPU2_RESET_INT,cpu1 fw reset cpu2" "0,1"
newline
bitfld.long 0x0 29. "CPU3_RESET_INT,cpu1 fw reset cpu3" "0,1"
newline
bitfld.long 0x0 18. "CPU1_CPU3_MSG_SCHEME,CPU1 to CPU3 Message Scheme" "0,1"
newline
hexmask.long.byte 0x0 8.--15. 1. "CPU1_DBG_CTRL,cpu2 debug control"
group.long 0xAC0++0xB
line.long 0x0 "CIU_CPU_CPU1_ACCESS_CTRL,CPU1 access control register"
hexmask.long 0x0 0.--31. 1. "CPU1_ACCESS_CTRL,CPU1 will read CIU_CPU_CPU1_ACCESS_CRTL and set CIU_CPU1_ACCESS_CRTL bit. After writing the bit the CPU1 will check if the CIU_CPU_CPU1_ACCESS_CRTL bit is set or not. If set then CPU1 will access the resource (for e.g CSU)."
line.long 0x4 "CIU_CPU_CPU2_ACCESS_CTRL,CPU2 access control register"
hexmask.long 0x4 0.--31. 1. "CPU2_ACCESS_CTRL,CPU2 will read CIU_CPU_CPU2_ACCESS_CRTL and set CIU_CPU2_ACCESS_CRTL bit. After writing the bit the CPU2 will check if the CIU_CPU_CPU2_ACCESS_CRTL bit is set or not. If set then CPU2 will access the resource (for e.g CSU)."
line.long 0x8 "CIU_CPU_CPU3_ACCESS_CTRL,CPU3 access control register"
hexmask.long 0x8 0.--31. 1. "CPU3_ACCESS_CTRL,CPU3 will read CIU_CPU_CPU3_ACCESS_CRTL and set CIU_CPU3_ACCESS_CRTL bit. After writing the bit the CPU3 will check if the CIU_CPU_CPU3_ACCESS_CRTL bit is set or not. If set then CPU3 will access the resource (for e.g CSU)."
rgroup.long 0xACC++0x3
line.long 0x0 "CIU_CPU_CPU1_DBG_STAT1,CPU1 debug register1"
hexmask.long 0x0 0.--31. 1. "CPU1_RO_STATUS,cpu1 debug output"
group.long 0xAD8++0xB
line.long 0x0 "CIU_CPU1_CPU2_FW_DWLD_CTRL,CPUs FW dwld control register"
bitfld.long 0x0 31. "CHIP_INIT_DONE,After the FW is downloaded (serial or parallel) the CPU1 does the chip init and set this bit. It is used later by boot code in case the FW crash happen then it doesn't need to do chip init again" "0,1"
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hexmask.long.word 0x0 17.--30. 1. "CHIP_INIT_DONE_SKETCH,Sketch registers for Chip Init"
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bitfld.long 0x0 16. "CPU2_FW_DWLD_DONE,For the serial mode of FW download when CPU1 done with FW download for CPU2 also then it assert this bit. After this CPU2 can jump to it's ITCM to start execution" "0,1"
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hexmask.long.byte 0x0 9.--15. 1. "CPU2_FW_DWLD_SKETCH,Sketch registers for Chip Download"
newline
bitfld.long 0x0 8. "PARALLEL_DWLD,For the parallel mode of FW download CPU1 assert this bit to provide information to CPU2." "0,1"
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hexmask.long.byte 0x0 1.--7. 1. "PARALLEL_DWLD_SKETCH,SKETCH register for Parallel download"
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bitfld.long 0x0 0. "FW_DWLD_INFO_VALID,After writing the bit[8] and bit[16] the CPU1 writes valid bit to indicate to cpu2 that information is valid and ready to use. CPU2 polls this bit and once set take appropriate action based on bit[8] and bit[16]" "0,1"
line.long 0x4 "CIU_CPU_COMM0,CPU Communication reserved0"
hexmask.long 0x4 0.--31. 1. "CPU_COMM0,CPUs extra reserved communication reg to be used by FW"
line.long 0x8 "CIU_CPU_COMM1,CPU Communication reserved1"
hexmask.long 0x8 0.--31. 1. "CPU_COMM1,CPUs extra reserved communication reg to be used by FW"
group.long 0xB3C++0x3
line.long 0x0 "CIU_CPU_ECO_CTRL,CPU ECO control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0xB60++0x7
line.long 0x0 "CIU_RFU_CTRL,RFU Control and Status"
rbitfld.long 0x0 31. "RFU_TRX_RDY_5G_B,RFU5G channel B Rdy Status" "0,1"
newline
rbitfld.long 0x0 30. "RFU_TRX_RDY_5G_A,RFU5G channel A Rdy Status" "0,1"
newline
rbitfld.long 0x0 29. "RFU_TRX_RDY_2G_A,RFU2G channel A Rdy Status" "0,1"
newline
bitfld.long 0x0 3. "APB_EN_2G,Enable RFU2G APB Interface for Register Programming" "0,1"
newline
bitfld.long 0x0 2. "APB_DWORD_SEL,RFU APB DWORD Select" "0,1"
newline
bitfld.long 0x0 1. "APB_EN_5G,Enable RFU5G APB Interface for Register Programming" "0,1"
line.long 0x4 "CIU_RFU_EXTRA_PORT,RFU Extra Port Connection"
hexmask.long.byte 0x4 24.--27. 1. "SOC_RFU2G_EXTRA_B,SOC_RFU2G_EXTRA_B[3:0]"
newline
hexmask.long.byte 0x4 16.--23. 1. "SOC_RFU2G_EXTRA_A,SOC_RFU2G_EXTRA_A[7:0]"
newline
hexmask.long.byte 0x4 8.--15. 1. "SOC_RFU5G_EXTRA_B,SOC_RFU5G_EXTRA_B[7:0]"
newline
hexmask.long.byte 0x4 0.--7. 1. "SOC_RFU5G_EXTRA_A,SOC_RFU5G_EXTRA_A[7:0]"
group.long 0xB7C++0x3
line.long 0x0 "CIU_RFU_ECO_CTRL,RFU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0xC00++0x3
line.long 0x0 "CIU_MCI_EXTRA,MCI EXTRA Ports"
hexmask.long.byte 0x0 4.--7. 1. "CIU_MCI_EXTRA_IN,Extra Ports from MCI"
newline
hexmask.long.byte 0x0 0.--3. 1. "CIU_MCI_EXTRA_OUT,Extra Ports to MCI"
group.long 0xD00++0xB
line.long 0x0 "CIU_BBUD_CTRL,BBUD Control Register"
bitfld.long 0x0 16. "PTP_SYNC_PULSE_SEL,Mux select control to select between" "0,1"
newline
bitfld.long 0x0 8.--9. "PPS_IN_SEL,BBUD PPS input select" "0,1,2,3"
newline
bitfld.long 0x0 4. "APB_EN_BBU2,Enable BBUD2 APB Interface for Register Programming" "0,1"
newline
bitfld.long 0x0 2. "BBUD_SPEC_SEL,BBUD SPEC CLK select" "0,1"
newline
bitfld.long 0x0 1. "APB_DWORD_SEL,BBUD APB DWORD Select" "0,1"
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bitfld.long 0x0 0. "APB_EN_BBU1,Enable BBUD1 APB Interface for Register Programming" "0,1"
line.long 0x4 "CIU_BBUD_EXTRA_PORT,BBUD Extra Port Connection"
hexmask.long.byte 0x4 0.--7. 1. "SOC_BBUD_EXTRA,SOC_BBUD_EXTRA[7:0]"
line.long 0x8 "CIU_BBUD_PTP_INTR_CTRL,PTP Input capture interrupt control"
bitfld.long 0x8 7. "PTP_INPUTCAPTURE_EDGE_SEL,Select edge for generation of PTP interrupt" "0,1"
newline
bitfld.long 0x8 0. "PTP_INPUTCAPTURE_INTR_MASK,Mask control for ptp_inputcaptue interrupt generation" "0,1"
group.long 0xD7C++0x7
line.long 0x0 "CIU_BBUD_ECO_CTRL,BBUD ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
line.long 0x4 "CIU_AIU_CTRL,AIU Control Register"
hexmask.long.tbyte 0x4 8.--31. 1. "AIU_MCLK_NCO_STEP_SIZE,AIU NCO Step Size"
newline
bitfld.long 0x4 5. "AIU_MCLK_SEL,AIU MCLK" "0,1"
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bitfld.long 0x4 4. "AIU_MCLK_NCO_INPUT_SEL,AIU NCO Input" "0,1"
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bitfld.long 0x4 3. "AIU_MCLK_NCO_TYPE,NCO" "0,1"
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bitfld.long 0x4 2. "AIU_MCLK_NCO_EN,AIU_MCLK NCO" "0,1"
group.long 0xDFC++0x3
line.long 0x0 "CIU_AIU_ECO_CTRL,AIU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0xEFC++0x3
line.long 0x0 "CIU_CBU_ECO_CTRL,CBU ECO Control"
hexmask.long 0x0 0.--31. 1. "ECO_BITS,Reserved for ECOs"
group.long 0x1BF800++0x3
line.long 0x0 "CIU1_IMU_CPU1_WR_MSG_TO_CPU3,CPU1(WL) write message to CPU3(MCI) (0xAF0-0xAF4 IMU register access by CPU1)"
hexmask.long 0x0 0.--31. 1. "CPU1_WR_MSG_CPU3,Write cpu1 message data to CPU3 (push to FIFO)"
rgroup.long 0x1BF804++0x7
line.long 0x0 "CIU1_IMU_CPU1_RD_MSG_FROM_CPU3,cpu1 read message from CPU3"
hexmask.long 0x0 0.--31. 1. "CPU1_RD_MSG_CPU3,cpu1 read message data from CPU3 (pop from FIFO)"
line.long 0x4 "CIU1_IMU_CPU1_CPU3_MSG_FIFO_STATUS,cpu1 to CPU3 message FIFO status"
hexmask.long.byte 0x4 20.--23. 1. "CPU1_TO_CPU3_MSG_FIFO_RD_PTR,cpu1 to cpu3 msg fifo read pointer for debug"
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hexmask.long.byte 0x4 16.--19. 1. "CPU1_TO_CPU3_MSG_FIFO_WR_PTR,cpu1 to cpu3 msg fifo write pointer for debug"
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hexmask.long.byte 0x4 4.--8. 1. "CPU1_TO_CPU3_MSG_COUNT,cpu1_to_cpu3_msg_count"
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bitfld.long 0x4 3. "CPU1_TO_CPU3_MSG_FIFO_EMPTY,cpu1_to_cpu3_msg_fifo_empty" "0,1"
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bitfld.long 0x4 2. "CPU1_TO_CPU3_MSG_FIFO_FULL,cpu1_to_cpu3_msg_fifo_full (based upon FIFO depth)" "0,1"
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bitfld.long 0x4 1. "CPU1_TO_CPU3_MSG_FIFO_ALMOST_FULL,cpu1_to_cpu3_msg_fifo_almost_full (based upon FIFO watermark)" "0,1"
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bitfld.long 0x4 0. "CPU1_TO_CPU3_MSG_FIFO_LOCKED,cpu1_to_cpu3_msg_fifo_locked" "0,1"
group.long 0x1BF80C++0x3
line.long 0x0 "CIU1_IMU_CPU1_CPU3_MSG_FIFO_CNTL,cpu1 to CPU3 message FIFO control"
hexmask.long.byte 0x0 20.--23. 1. "CPU1_TO_CPU3_MSG_FIFO_FULL_WATERMARK,cpu1_to_cpu3 message fifo full watermark (space avail intr based upon it)"
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bitfld.long 0x0 17. "CPU1_WAIT_FOR_ACK,CPU1 Wait for Acknowledgment" "0,1"
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bitfld.long 0x0 16. "CPU1_TO_CPU3_MSG_FIFO_FLUSH,Writing 1 to this bit will flush cpu1_to_cpu3 message fifo" "0,1"
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bitfld.long 0x0 8. "CPU1_MSG_SP_AV_INT_CLR,Writing 1 to this bit will clear message space available interrupt to CPU1 (self clear bit)" "0,1"
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bitfld.long 0x0 0. "CPU1_MSG_RDY_INT_CLR,Writing 1 to this bit will clear message ready interrupt to CPU1 (self clear bit)" "0,1"
rgroup.long 0x1BF810++0x3
line.long 0x0 "CIU1_IMU_CPU3_RD_MSG_FROM_CPU1_VAL_DBG,CPU3 last message read (from cpu1)"
hexmask.long 0x0 0.--31. 1. "CPU3_RD_MSG,CPU3 last message read (from cpu1)"
group.long 0x1BF820++0x3
line.long 0x0 "CIU1_IMU_CPU3_WR_MSG_TO_CPU1,CPU3 write message to cpu1 (0xB04-0xB14 IMU register access by CPU3)"
hexmask.long 0x0 0.--31. 1. "CPU3_WR_MSG_CPU1,Write CPU3 message data to cpu1 (push to FIFO)"
rgroup.long 0x1BF824++0x7
line.long 0x0 "CIU1_IMU_CPU3_RD_MSG_FROM_CPU1,CPU3 read message from cpu1"
hexmask.long 0x0 0.--31. 1. "CPU3_RD_MSG_CPU1,CPU3 read message data from cpu1 (pop from FIFO)"
line.long 0x4 "CIU1_IMU_CPU3_CPU1_MSG_FIFO_STATUS,CPU3 to cpu1 message FIFO status"
hexmask.long.byte 0x4 20.--23. 1. "CPU3_TO_CPU1_MSG_FIFO_RD_PTR,cpu3 to cpu1 msg fifo read pointer for debug"
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hexmask.long.byte 0x4 16.--19. 1. "CPU3_TO_CPU1_MSG_FIFO_WR_PTR,cpu3 to cpu1 msg fifo write pointer for debug"
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hexmask.long.byte 0x4 4.--8. 1. "CPU3_TO_CPU1_MSG_COUNT,cpu3_to_cpu1_msg_count"
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bitfld.long 0x4 3. "CPU3_TO_CPU1_MSG_FIFO_EMPTY,cpu3_to_cpu1_msg_fifo_empty" "0,1"
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bitfld.long 0x4 2. "CPU3_TO_CPU1_MSG_FIFO_FULL,cpu3_to_cpu1_msg_fifo_full (based upon FIFO depth)" "0,1"
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bitfld.long 0x4 1. "CPU3_TO_CPU1_MSG_FIFO_ALMOST_FULL,cpu3_to_cpu1_msg_fifo_almost_full (based upon FIFO watermark)" "0,1"
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bitfld.long 0x4 0. "CPU3_TO_CPU1_MSG_FIFO_LOCKED,cpu3_to_cpu1_msg_fifo_locked" "0,1"
group.long 0x1BF82C++0x3
line.long 0x0 "CIU1_IMU_CPU3_CPU1_MSG_FIFO_CNTL,CPU3 to cpu1 message FIFO control"
hexmask.long.byte 0x0 20.--23. 1. "CPU3_TO_CPU1_MSG_FIFO_FULL_WATERMARK,cpu3_to_cpu1 message fifo full watermark (space avail intr based upon it)"
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bitfld.long 0x0 17. "CPU3_WAIT_FOR_ACK,CPU3 Wait for Acknowledgment" "0,1"
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bitfld.long 0x0 16. "CPU3_TO_CPU1_MSG_FIFO_FLUSH,Writing 1 to this bit will flush cpu3_to_cpu1 message fifo" "0,1"
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bitfld.long 0x0 8. "CPU3_MSG_SP_AV_INT_CLR,Writing 1 to this bit will clear message space available interrupt to CPU3 (self clear bit)" "0,1"
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bitfld.long 0x0 0. "CPU3_MSG_RDY_INT_CLR,Writing 1 to this bit will clear message ready interrupt to cpu3 (self clear bit)" "0,1"
rgroup.long 0x1BF830++0x3
line.long 0x0 "CIU1_IMU_CPU1_RD_MSG_FROM_CPU3_VAL_DBG,cpu1 last message read (from cpu3)"
hexmask.long 0x0 0.--31. 1. "CPU1_RD_MSG,cpu1 last message read (from cpu3)"
group.long 0x1BF834++0xF
line.long 0x0 "CIU_CPU1_CPU3_MSG_CTRL,CPU1_CPU3 message register"
bitfld.long 0x0 9. "CPU3_TO_CPU1_MSG_PROCESS_DONE,CPU3 Message for CPU1 has been read by CPU1 and executed. This is self clearing bit. The CPU1 writes 1 to indicate that message send by CPU3 is executed. This generates an Interrupt to CPU3 via CIU1." "0,1"
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bitfld.long 0x0 8. "CPU1_TO_CPU3_MSG_PROCESS_DONE,CPU1 Message for CPU3 has been read by CPU3 and executed. This is self clearing bit. The CPU3 writes 1 to indicate that message sent by CPU1 is executed. This generates an Interrupt to CPU1 via CIU1." "0,1"
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bitfld.long 0x0 1. "CPU3_TO_CPU1_MSG_RDY,CPU3 Message for CPU1 is ready. This is self clearing bit. The CPU3 writes 1 to indicate that message for CPU1 is ready. This generates an Interrupt to CPU1 via APU. This is old schema and we should use IMU based scheme." "0,1"
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bitfld.long 0x0 0. "CPU1_TO_CPU3_MSG_RDY,CPU1 Message for CPU3 is ready. This is self clearing bit. The CPU1 writes 1 to indicate that message for CPU3 is ready. This generates an Interrupt to CPU3 via APU. This is old schema and we should use IMU based scheme." "0,1"
line.long 0x4 "CIU1_CPU3_WAKEUP_CTRL,CIU1 register to wakeup CPU3"
bitfld.long 0x4 0. "CPU3_WAKEUP_CTRL,CPU3 Wakeup Control Register. S/W Write 1 to generate a wake up interrupt to CPU3.Clear by S/W once mci_wl_wakeup_done[1] interrupt is received from CPU3." "0,1"
line.long 0x8 "CIU1_CPU1_WAKEUP_DONE,Wakeup done Control Register to CPU3"
hexmask.long.byte 0x8 0.--7. 1. "CPU1_WAKEUP_DONE,CPU1 Wakeup is done . This bit is set to 1 by S/W when CPU3 wakesup CPU1.This is self clearing bit. This generates an interrupt to CPU3 via wl_mci_wakeup_done[7:0] signal."
line.long 0xC "CIU1_CPU3_NS_GP_INT,Non Secure region GP interrupt to CPU3"
bitfld.long 0xC 0.--1. "CPU1_CPU3_GP_NS_INT,General Purpose interrupt to CPU3 from non secure registers" "0,1,2,3"
group.long 0x1BF8FC++0x3
line.long 0x0 "CIU_IMU_ECO_BITS,IMU ECO Control"
hexmask.long.word 0x0 0.--15. 1. "ECO_BITS,Reserved for ECOs"
tree.end
tree.end
tree "WWDT (Windowed Watchdog Timer)"
base ad:0x4000E000
group.long 0x0++0x7
line.long 0x0 "MOD,Mode"
bitfld.long 0x0 5. "LOCK,Lock" "0: No Lock,1: Lock"
bitfld.long 0x0 4. "WDPROTECT,Watchdog Update Mode" "0: Flexible,1: Threshold"
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eventfld.long 0x0 3. "WDINT,Warning Interrupt Flag" "0: No flag.,1: Flag. The Watchdog interrupt flag is set when.."
bitfld.long 0x0 2. "WDTOF,Watchdog Timeout Flag" "0: Clear.,1: Reset. Causes a chip reset if WDRESET = 1."
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bitfld.long 0x0 1. "WDRESET,Watchdog Reset Enable" "0: Interrupt. A Watchdog timeout will not cause a..,1: Reset. A Watchdog timeout will cause a chip reset."
bitfld.long 0x0 0. "WDEN,Watchdog Enable" "0: Stop. The Watchdog timer is stopped.,1: Run. The Watchdog timer is running."
line.long 0x4 "TC,Timer Constant"
hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Watchdog Timeout Value"
wgroup.long 0x8++0x3
line.long 0x0 "FEED,Feed Sequence"
hexmask.long.byte 0x0 0.--7. 1. "FEED,Feed Value"
rgroup.long 0xC++0x3
line.long 0x0 "TV,Timer Value"
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Timer Value"
group.long 0x14++0x7
line.long 0x0 "WARNINT,Warning Interrupt Compare Value"
hexmask.long.word 0x0 0.--9. 1. "WARNINT,Watchdog Warning Interrupt Compare Value"
line.long 0x4 "WINDOW,Window Compare Value"
hexmask.long.tbyte 0x4 0.--23. 1. "WINDOW,Watchdog Window Value."
tree.end
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AUTOINDENT.OFF
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