47003 lines
2.8 MiB
47003 lines
2.8 MiB
; --------------------------------------------------------------------------------
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; @Title: TMS320F2838xx On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, NEJ, KRZ
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; @Changelog: 2020-05-28 KWI
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; 2024-08-21 NEJ
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; 2024-10-16 KRZ
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; @Manufacturer: TI - Texas Instruments
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; @Doc: Generated (TRACE32, build: 173544.), based on: f2838*.xml (CCS 12.8.0)
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; @Core: C28x, Cortex-M4
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; @Chip: F28384D, F28386D, F28386S, F28388D, F28388S, F28384S
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertms320f2838xx.per 18468 2024-10-16 15:47:50Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base d:0x0
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sif (CORENAME()=="CORTEXM4")
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tree.close "Core Registers (Cortex-M4)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "ADC (Analog to Digital Converter)"
|
|
base d:0x0
|
|
tree "ADCA"
|
|
base d:0x7400
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x0 13. "ADCBSY,ADC Busy" "0,1"
|
|
hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel"
|
|
bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down" "0,1"
|
|
bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position" "0,1"
|
|
line.word 0x1 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x1 7. "SIGNALMODE,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x1 6. "RESOLUTION,SOC Conversion Resolution" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "PRESCALE,ADC Clock Prescaler"
|
|
line.word 0x2 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x2 15. "BURSTEN,SOC Burst Mode Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "BURSTSIZE,SOC Burst Size Select"
|
|
hexmask.word.byte 0x2 0.--5. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word 0x5++0x1
|
|
line.word 0x0 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word 0x6++0xB
|
|
line.word 0x0 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
line.word 0x1 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x1 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 13. "INT2E,ADCINT2 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select"
|
|
bitfld.word 0x1 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 5. "INT1E,ADCINT1 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x1 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select"
|
|
line.word 0x2 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x2 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 13. "INT4E,ADCINT4 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select"
|
|
bitfld.word 0x2 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 5. "INT3E,ADCINT3 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select"
|
|
line.word 0x3 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
hexmask.word.byte 0x3 5.--9. 1. "RRPOINTER,Round Robin Pointer"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SOCPRIORITY,SOC Priority"
|
|
line.word 0x4 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x4 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x4 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
line.word 0x5 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x5 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x5 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word 0xD++0x1
|
|
line.word 0x0 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word 0xE++0x1
|
|
line.word 0x0 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long 0x10++0x3F
|
|
line.long 0x0 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "TRIGSEL,SOC0 Trigger Source Select"
|
|
hexmask.long.byte 0x0 15.--18. 1. "CHSEL,SOC0 Channel Select"
|
|
hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
line.long 0x2 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
hexmask.long.byte 0x2 20.--25. 1. "TRIGSEL,SOC1 Trigger Source Select"
|
|
hexmask.long.byte 0x2 15.--18. 1. "CHSEL,SOC1 Channel Select"
|
|
hexmask.long.word 0x2 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
line.long 0x4 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
hexmask.long.byte 0x4 20.--25. 1. "TRIGSEL,SOC2 Trigger Source Select"
|
|
hexmask.long.byte 0x4 15.--18. 1. "CHSEL,SOC2 Channel Select"
|
|
hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
line.long 0x6 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
hexmask.long.byte 0x6 20.--25. 1. "TRIGSEL,SOC3 Trigger Source Select"
|
|
hexmask.long.byte 0x6 15.--18. 1. "CHSEL,SOC3 Channel Select"
|
|
hexmask.long.word 0x6 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
line.long 0x8 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
hexmask.long.byte 0x8 20.--25. 1. "TRIGSEL,SOC4 Trigger Source Select"
|
|
hexmask.long.byte 0x8 15.--18. 1. "CHSEL,SOC4 Channel Select"
|
|
hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
line.long 0xA "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
hexmask.long.byte 0xA 20.--25. 1. "TRIGSEL,SOC5 Trigger Source Select"
|
|
hexmask.long.byte 0xA 15.--18. 1. "CHSEL,SOC5 Channel Select"
|
|
hexmask.long.word 0xA 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
line.long 0xC "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
hexmask.long.byte 0xC 20.--25. 1. "TRIGSEL,SOC6 Trigger Source Select"
|
|
hexmask.long.byte 0xC 15.--18. 1. "CHSEL,SOC6 Channel Select"
|
|
hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
line.long 0xE "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
hexmask.long.byte 0xE 20.--25. 1. "TRIGSEL,SOC7 Trigger Source Select"
|
|
hexmask.long.byte 0xE 15.--18. 1. "CHSEL,SOC7 Channel Select"
|
|
hexmask.long.word 0xE 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
line.long 0x10 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
hexmask.long.byte 0x10 20.--25. 1. "TRIGSEL,SOC8 Trigger Source Select"
|
|
hexmask.long.byte 0x10 15.--18. 1. "CHSEL,SOC8 Channel Select"
|
|
hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
line.long 0x12 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
hexmask.long.byte 0x12 20.--25. 1. "TRIGSEL,SOC9 Trigger Source Select"
|
|
hexmask.long.byte 0x12 15.--18. 1. "CHSEL,SOC9 Channel Select"
|
|
hexmask.long.word 0x12 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
line.long 0x14 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
hexmask.long.byte 0x14 20.--25. 1. "TRIGSEL,SOC10 Trigger Source Select"
|
|
hexmask.long.byte 0x14 15.--18. 1. "CHSEL,SOC10 Channel Select"
|
|
hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
line.long 0x16 "ADCSOC11CTL,ADC SOC11 Control Register"
|
|
hexmask.long.byte 0x16 20.--25. 1. "TRIGSEL,SOC11 Trigger Source Select"
|
|
hexmask.long.byte 0x16 15.--18. 1. "CHSEL,SOC11 Channel Select"
|
|
hexmask.long.word 0x16 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
line.long 0x18 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
hexmask.long.byte 0x18 20.--25. 1. "TRIGSEL,SOC12 Trigger Source Select"
|
|
hexmask.long.byte 0x18 15.--18. 1. "CHSEL,SOC12 Channel Select"
|
|
hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
line.long 0x1A "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
hexmask.long.byte 0x1A 20.--25. 1. "TRIGSEL,SOC13 Trigger Source Select"
|
|
hexmask.long.byte 0x1A 15.--18. 1. "CHSEL,SOC13 Channel Select"
|
|
hexmask.long.word 0x1A 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
line.long 0x1C "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
hexmask.long.byte 0x1C 20.--25. 1. "TRIGSEL,SOC14 Trigger Source Select"
|
|
hexmask.long.byte 0x1C 15.--18. 1. "CHSEL,SOC14 Channel Select"
|
|
hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
line.long 0x1E "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
hexmask.long.byte 0x1E 20.--25. 1. "TRIGSEL,SOC15 Trigger Source Select"
|
|
hexmask.long.byte 0x1E 15.--18. 1. "CHSEL,SOC15 Channel Select"
|
|
hexmask.long.word 0x1E 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word 0x32++0x5
|
|
line.word 0x0 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear" "0,1"
|
|
line.word 0x2 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x2 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable" "0,1"
|
|
line.word 0x4 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x4 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
|
|
rgroup.word 0x39++0x3
|
|
line.word 0x0 "ADCCOUNTER,ADC Counter Register"
|
|
hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
|
|
line.word 0x1 "ADCREV,ADC Revision Register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TYPE,ADC Type"
|
|
group.word 0x3B++0x1
|
|
line.word 0x0 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration"
|
|
rgroup.word 0x41++0x1
|
|
line.word 0x0 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word 0x42++0x3
|
|
line.word 0x0 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Reference"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
|
|
line.long 0x2 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration"
|
|
rgroup.word 0x49++0x1
|
|
line.word 0x0 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word 0x4A++0x3
|
|
line.word 0x0 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Reference"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
line.long 0x2 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration"
|
|
rgroup.word 0x51++0x1
|
|
line.word 0x0 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word 0x52++0x3
|
|
line.word 0x0 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Reference"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
line.long 0x2 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word 0x58++0x1
|
|
line.word 0x0 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration"
|
|
rgroup.word 0x59++0x1
|
|
line.word 0x0 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word 0x5A++0x3
|
|
line.word 0x0 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Reference"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
line.long 0x2 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word 0x6F++0x1
|
|
line.word 0x0 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
hexmask.word 0x0 0.--15. 1. "DELAY,Delay from ADCSOC fall edge to early interrupt generation."
|
|
group.long 0x70++0x17
|
|
line.long 0x0 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0"
|
|
line.long 0x2 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32"
|
|
line.long 0x4 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
hexmask.long 0x4 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64"
|
|
line.long 0x6 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
hexmask.long 0x6 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96"
|
|
line.long 0x8 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
hexmask.long 0x8 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128"
|
|
line.long 0xA "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
hexmask.long 0xA 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160"
|
|
tree.end
|
|
tree "ADCA_RESULT"
|
|
base d:0xB00
|
|
rgroup.word 0x0++0x1F
|
|
line.word 0x0 "ADCRESULT0,ADC Result 0 Register"
|
|
hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x1 "ADCRESULT1,ADC Result 1 Register"
|
|
hexmask.word 0x1 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x2 "ADCRESULT2,ADC Result 2 Register"
|
|
hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x3 "ADCRESULT3,ADC Result 3 Register"
|
|
hexmask.word 0x3 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x4 "ADCRESULT4,ADC Result 4 Register"
|
|
hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x5 "ADCRESULT5,ADC Result 5 Register"
|
|
hexmask.word 0x5 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x6 "ADCRESULT6,ADC Result 6 Register"
|
|
hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x7 "ADCRESULT7,ADC Result 7 Register"
|
|
hexmask.word 0x7 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x8 "ADCRESULT8,ADC Result 8 Register"
|
|
hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x9 "ADCRESULT9,ADC Result 9 Register"
|
|
hexmask.word 0x9 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xA "ADCRESULT10,ADC Result 10 Register"
|
|
hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xB "ADCRESULT11,ADC Result 11 Register"
|
|
hexmask.word 0xB 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xC "ADCRESULT12,ADC Result 12 Register"
|
|
hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xD "ADCRESULT13,ADC Result 13 Register"
|
|
hexmask.word 0xD 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xE "ADCRESULT14,ADC Result 14 Register"
|
|
hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xF "ADCRESULT15,ADC Result 15 Register"
|
|
hexmask.word 0xF 0.--15. 1. "RESULT,ADC Result"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x2 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x2 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x4 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x6 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long.word 0x6 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x6 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
tree.end
|
|
tree "ADCB"
|
|
base d:0x7480
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x0 13. "ADCBSY,ADC Busy" "0,1"
|
|
hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel"
|
|
bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down" "0,1"
|
|
bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position" "0,1"
|
|
line.word 0x1 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x1 7. "SIGNALMODE,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x1 6. "RESOLUTION,SOC Conversion Resolution" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "PRESCALE,ADC Clock Prescaler"
|
|
line.word 0x2 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x2 15. "BURSTEN,SOC Burst Mode Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "BURSTSIZE,SOC Burst Size Select"
|
|
hexmask.word.byte 0x2 0.--5. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word 0x5++0x1
|
|
line.word 0x0 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word 0x6++0xB
|
|
line.word 0x0 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
line.word 0x1 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x1 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 13. "INT2E,ADCINT2 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select"
|
|
bitfld.word 0x1 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 5. "INT1E,ADCINT1 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x1 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select"
|
|
line.word 0x2 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x2 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 13. "INT4E,ADCINT4 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select"
|
|
bitfld.word 0x2 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 5. "INT3E,ADCINT3 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select"
|
|
line.word 0x3 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
hexmask.word.byte 0x3 5.--9. 1. "RRPOINTER,Round Robin Pointer"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SOCPRIORITY,SOC Priority"
|
|
line.word 0x4 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x4 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x4 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
line.word 0x5 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x5 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x5 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word 0xD++0x1
|
|
line.word 0x0 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word 0xE++0x1
|
|
line.word 0x0 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long 0x10++0x3F
|
|
line.long 0x0 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "TRIGSEL,SOC0 Trigger Source Select"
|
|
hexmask.long.byte 0x0 15.--18. 1. "CHSEL,SOC0 Channel Select"
|
|
hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
line.long 0x2 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
hexmask.long.byte 0x2 20.--25. 1. "TRIGSEL,SOC1 Trigger Source Select"
|
|
hexmask.long.byte 0x2 15.--18. 1. "CHSEL,SOC1 Channel Select"
|
|
hexmask.long.word 0x2 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
line.long 0x4 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
hexmask.long.byte 0x4 20.--25. 1. "TRIGSEL,SOC2 Trigger Source Select"
|
|
hexmask.long.byte 0x4 15.--18. 1. "CHSEL,SOC2 Channel Select"
|
|
hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
line.long 0x6 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
hexmask.long.byte 0x6 20.--25. 1. "TRIGSEL,SOC3 Trigger Source Select"
|
|
hexmask.long.byte 0x6 15.--18. 1. "CHSEL,SOC3 Channel Select"
|
|
hexmask.long.word 0x6 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
line.long 0x8 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
hexmask.long.byte 0x8 20.--25. 1. "TRIGSEL,SOC4 Trigger Source Select"
|
|
hexmask.long.byte 0x8 15.--18. 1. "CHSEL,SOC4 Channel Select"
|
|
hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
line.long 0xA "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
hexmask.long.byte 0xA 20.--25. 1. "TRIGSEL,SOC5 Trigger Source Select"
|
|
hexmask.long.byte 0xA 15.--18. 1. "CHSEL,SOC5 Channel Select"
|
|
hexmask.long.word 0xA 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
line.long 0xC "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
hexmask.long.byte 0xC 20.--25. 1. "TRIGSEL,SOC6 Trigger Source Select"
|
|
hexmask.long.byte 0xC 15.--18. 1. "CHSEL,SOC6 Channel Select"
|
|
hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
line.long 0xE "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
hexmask.long.byte 0xE 20.--25. 1. "TRIGSEL,SOC7 Trigger Source Select"
|
|
hexmask.long.byte 0xE 15.--18. 1. "CHSEL,SOC7 Channel Select"
|
|
hexmask.long.word 0xE 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
line.long 0x10 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
hexmask.long.byte 0x10 20.--25. 1. "TRIGSEL,SOC8 Trigger Source Select"
|
|
hexmask.long.byte 0x10 15.--18. 1. "CHSEL,SOC8 Channel Select"
|
|
hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
line.long 0x12 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
hexmask.long.byte 0x12 20.--25. 1. "TRIGSEL,SOC9 Trigger Source Select"
|
|
hexmask.long.byte 0x12 15.--18. 1. "CHSEL,SOC9 Channel Select"
|
|
hexmask.long.word 0x12 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
line.long 0x14 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
hexmask.long.byte 0x14 20.--25. 1. "TRIGSEL,SOC10 Trigger Source Select"
|
|
hexmask.long.byte 0x14 15.--18. 1. "CHSEL,SOC10 Channel Select"
|
|
hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
line.long 0x16 "ADCSOC11CTL,ADC SOC11 Control Register"
|
|
hexmask.long.byte 0x16 20.--25. 1. "TRIGSEL,SOC11 Trigger Source Select"
|
|
hexmask.long.byte 0x16 15.--18. 1. "CHSEL,SOC11 Channel Select"
|
|
hexmask.long.word 0x16 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
line.long 0x18 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
hexmask.long.byte 0x18 20.--25. 1. "TRIGSEL,SOC12 Trigger Source Select"
|
|
hexmask.long.byte 0x18 15.--18. 1. "CHSEL,SOC12 Channel Select"
|
|
hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
line.long 0x1A "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
hexmask.long.byte 0x1A 20.--25. 1. "TRIGSEL,SOC13 Trigger Source Select"
|
|
hexmask.long.byte 0x1A 15.--18. 1. "CHSEL,SOC13 Channel Select"
|
|
hexmask.long.word 0x1A 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
line.long 0x1C "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
hexmask.long.byte 0x1C 20.--25. 1. "TRIGSEL,SOC14 Trigger Source Select"
|
|
hexmask.long.byte 0x1C 15.--18. 1. "CHSEL,SOC14 Channel Select"
|
|
hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
line.long 0x1E "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
hexmask.long.byte 0x1E 20.--25. 1. "TRIGSEL,SOC15 Trigger Source Select"
|
|
hexmask.long.byte 0x1E 15.--18. 1. "CHSEL,SOC15 Channel Select"
|
|
hexmask.long.word 0x1E 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word 0x32++0x5
|
|
line.word 0x0 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear" "0,1"
|
|
line.word 0x2 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x2 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable" "0,1"
|
|
line.word 0x4 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x4 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
|
|
rgroup.word 0x39++0x3
|
|
line.word 0x0 "ADCCOUNTER,ADC Counter Register"
|
|
hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
|
|
line.word 0x1 "ADCREV,ADC Revision Register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TYPE,ADC Type"
|
|
group.word 0x3B++0x1
|
|
line.word 0x0 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration"
|
|
rgroup.word 0x41++0x1
|
|
line.word 0x0 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word 0x42++0x3
|
|
line.word 0x0 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Reference"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
|
|
line.long 0x2 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration"
|
|
rgroup.word 0x49++0x1
|
|
line.word 0x0 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word 0x4A++0x3
|
|
line.word 0x0 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Reference"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
line.long 0x2 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration"
|
|
rgroup.word 0x51++0x1
|
|
line.word 0x0 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word 0x52++0x3
|
|
line.word 0x0 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Reference"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
line.long 0x2 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word 0x58++0x1
|
|
line.word 0x0 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration"
|
|
rgroup.word 0x59++0x1
|
|
line.word 0x0 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word 0x5A++0x3
|
|
line.word 0x0 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Reference"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
line.long 0x2 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word 0x6F++0x1
|
|
line.word 0x0 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
hexmask.word 0x0 0.--15. 1. "DELAY,Delay from ADCSOC fall edge to early interrupt generation."
|
|
group.long 0x70++0x17
|
|
line.long 0x0 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0"
|
|
line.long 0x2 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32"
|
|
line.long 0x4 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
hexmask.long 0x4 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64"
|
|
line.long 0x6 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
hexmask.long 0x6 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96"
|
|
line.long 0x8 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
hexmask.long 0x8 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128"
|
|
line.long 0xA "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
hexmask.long 0xA 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160"
|
|
tree.end
|
|
tree "ADCB_RESULT"
|
|
base d:0xB20
|
|
rgroup.word 0x0++0x1F
|
|
line.word 0x0 "ADCRESULT0,ADC Result 0 Register"
|
|
hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x1 "ADCRESULT1,ADC Result 1 Register"
|
|
hexmask.word 0x1 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x2 "ADCRESULT2,ADC Result 2 Register"
|
|
hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x3 "ADCRESULT3,ADC Result 3 Register"
|
|
hexmask.word 0x3 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x4 "ADCRESULT4,ADC Result 4 Register"
|
|
hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x5 "ADCRESULT5,ADC Result 5 Register"
|
|
hexmask.word 0x5 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x6 "ADCRESULT6,ADC Result 6 Register"
|
|
hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x7 "ADCRESULT7,ADC Result 7 Register"
|
|
hexmask.word 0x7 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x8 "ADCRESULT8,ADC Result 8 Register"
|
|
hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x9 "ADCRESULT9,ADC Result 9 Register"
|
|
hexmask.word 0x9 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xA "ADCRESULT10,ADC Result 10 Register"
|
|
hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xB "ADCRESULT11,ADC Result 11 Register"
|
|
hexmask.word 0xB 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xC "ADCRESULT12,ADC Result 12 Register"
|
|
hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xD "ADCRESULT13,ADC Result 13 Register"
|
|
hexmask.word 0xD 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xE "ADCRESULT14,ADC Result 14 Register"
|
|
hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xF "ADCRESULT15,ADC Result 15 Register"
|
|
hexmask.word 0xF 0.--15. 1. "RESULT,ADC Result"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x2 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x2 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x4 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x6 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long.word 0x6 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x6 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
tree.end
|
|
tree "ADCC"
|
|
base d:0x7500
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x0 13. "ADCBSY,ADC Busy" "0,1"
|
|
hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel"
|
|
bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down" "0,1"
|
|
bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position" "0,1"
|
|
line.word 0x1 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x1 7. "SIGNALMODE,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x1 6. "RESOLUTION,SOC Conversion Resolution" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "PRESCALE,ADC Clock Prescaler"
|
|
line.word 0x2 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x2 15. "BURSTEN,SOC Burst Mode Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "BURSTSIZE,SOC Burst Size Select"
|
|
hexmask.word.byte 0x2 0.--5. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word 0x5++0x1
|
|
line.word 0x0 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word 0x6++0xB
|
|
line.word 0x0 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
line.word 0x1 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x1 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 13. "INT2E,ADCINT2 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select"
|
|
bitfld.word 0x1 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 5. "INT1E,ADCINT1 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x1 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select"
|
|
line.word 0x2 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x2 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 13. "INT4E,ADCINT4 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select"
|
|
bitfld.word 0x2 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 5. "INT3E,ADCINT3 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select"
|
|
line.word 0x3 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
hexmask.word.byte 0x3 5.--9. 1. "RRPOINTER,Round Robin Pointer"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SOCPRIORITY,SOC Priority"
|
|
line.word 0x4 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x4 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x4 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
line.word 0x5 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x5 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x5 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word 0xD++0x1
|
|
line.word 0x0 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word 0xE++0x1
|
|
line.word 0x0 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long 0x10++0x3F
|
|
line.long 0x0 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "TRIGSEL,SOC0 Trigger Source Select"
|
|
hexmask.long.byte 0x0 15.--18. 1. "CHSEL,SOC0 Channel Select"
|
|
hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
line.long 0x2 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
hexmask.long.byte 0x2 20.--25. 1. "TRIGSEL,SOC1 Trigger Source Select"
|
|
hexmask.long.byte 0x2 15.--18. 1. "CHSEL,SOC1 Channel Select"
|
|
hexmask.long.word 0x2 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
line.long 0x4 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
hexmask.long.byte 0x4 20.--25. 1. "TRIGSEL,SOC2 Trigger Source Select"
|
|
hexmask.long.byte 0x4 15.--18. 1. "CHSEL,SOC2 Channel Select"
|
|
hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
line.long 0x6 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
hexmask.long.byte 0x6 20.--25. 1. "TRIGSEL,SOC3 Trigger Source Select"
|
|
hexmask.long.byte 0x6 15.--18. 1. "CHSEL,SOC3 Channel Select"
|
|
hexmask.long.word 0x6 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
line.long 0x8 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
hexmask.long.byte 0x8 20.--25. 1. "TRIGSEL,SOC4 Trigger Source Select"
|
|
hexmask.long.byte 0x8 15.--18. 1. "CHSEL,SOC4 Channel Select"
|
|
hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
line.long 0xA "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
hexmask.long.byte 0xA 20.--25. 1. "TRIGSEL,SOC5 Trigger Source Select"
|
|
hexmask.long.byte 0xA 15.--18. 1. "CHSEL,SOC5 Channel Select"
|
|
hexmask.long.word 0xA 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
line.long 0xC "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
hexmask.long.byte 0xC 20.--25. 1. "TRIGSEL,SOC6 Trigger Source Select"
|
|
hexmask.long.byte 0xC 15.--18. 1. "CHSEL,SOC6 Channel Select"
|
|
hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
line.long 0xE "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
hexmask.long.byte 0xE 20.--25. 1. "TRIGSEL,SOC7 Trigger Source Select"
|
|
hexmask.long.byte 0xE 15.--18. 1. "CHSEL,SOC7 Channel Select"
|
|
hexmask.long.word 0xE 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
line.long 0x10 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
hexmask.long.byte 0x10 20.--25. 1. "TRIGSEL,SOC8 Trigger Source Select"
|
|
hexmask.long.byte 0x10 15.--18. 1. "CHSEL,SOC8 Channel Select"
|
|
hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
line.long 0x12 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
hexmask.long.byte 0x12 20.--25. 1. "TRIGSEL,SOC9 Trigger Source Select"
|
|
hexmask.long.byte 0x12 15.--18. 1. "CHSEL,SOC9 Channel Select"
|
|
hexmask.long.word 0x12 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
line.long 0x14 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
hexmask.long.byte 0x14 20.--25. 1. "TRIGSEL,SOC10 Trigger Source Select"
|
|
hexmask.long.byte 0x14 15.--18. 1. "CHSEL,SOC10 Channel Select"
|
|
hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
line.long 0x16 "ADCSOC11CTL,ADC SOC11 Control Register"
|
|
hexmask.long.byte 0x16 20.--25. 1. "TRIGSEL,SOC11 Trigger Source Select"
|
|
hexmask.long.byte 0x16 15.--18. 1. "CHSEL,SOC11 Channel Select"
|
|
hexmask.long.word 0x16 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
line.long 0x18 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
hexmask.long.byte 0x18 20.--25. 1. "TRIGSEL,SOC12 Trigger Source Select"
|
|
hexmask.long.byte 0x18 15.--18. 1. "CHSEL,SOC12 Channel Select"
|
|
hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
line.long 0x1A "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
hexmask.long.byte 0x1A 20.--25. 1. "TRIGSEL,SOC13 Trigger Source Select"
|
|
hexmask.long.byte 0x1A 15.--18. 1. "CHSEL,SOC13 Channel Select"
|
|
hexmask.long.word 0x1A 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
line.long 0x1C "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
hexmask.long.byte 0x1C 20.--25. 1. "TRIGSEL,SOC14 Trigger Source Select"
|
|
hexmask.long.byte 0x1C 15.--18. 1. "CHSEL,SOC14 Channel Select"
|
|
hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
line.long 0x1E "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
hexmask.long.byte 0x1E 20.--25. 1. "TRIGSEL,SOC15 Trigger Source Select"
|
|
hexmask.long.byte 0x1E 15.--18. 1. "CHSEL,SOC15 Channel Select"
|
|
hexmask.long.word 0x1E 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word 0x32++0x5
|
|
line.word 0x0 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear" "0,1"
|
|
line.word 0x2 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x2 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable" "0,1"
|
|
line.word 0x4 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x4 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
|
|
rgroup.word 0x39++0x3
|
|
line.word 0x0 "ADCCOUNTER,ADC Counter Register"
|
|
hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
|
|
line.word 0x1 "ADCREV,ADC Revision Register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TYPE,ADC Type"
|
|
group.word 0x3B++0x1
|
|
line.word 0x0 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration"
|
|
rgroup.word 0x41++0x1
|
|
line.word 0x0 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word 0x42++0x3
|
|
line.word 0x0 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Reference"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
|
|
line.long 0x2 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration"
|
|
rgroup.word 0x49++0x1
|
|
line.word 0x0 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word 0x4A++0x3
|
|
line.word 0x0 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Reference"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
line.long 0x2 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration"
|
|
rgroup.word 0x51++0x1
|
|
line.word 0x0 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word 0x52++0x3
|
|
line.word 0x0 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Reference"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
line.long 0x2 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word 0x58++0x1
|
|
line.word 0x0 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration"
|
|
rgroup.word 0x59++0x1
|
|
line.word 0x0 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word 0x5A++0x3
|
|
line.word 0x0 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Reference"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
line.long 0x2 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word 0x6F++0x1
|
|
line.word 0x0 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
hexmask.word 0x0 0.--15. 1. "DELAY,Delay from ADCSOC fall edge to early interrupt generation."
|
|
group.long 0x70++0x17
|
|
line.long 0x0 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0"
|
|
line.long 0x2 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32"
|
|
line.long 0x4 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
hexmask.long 0x4 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64"
|
|
line.long 0x6 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
hexmask.long 0x6 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96"
|
|
line.long 0x8 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
hexmask.long 0x8 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128"
|
|
line.long 0xA "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
hexmask.long 0xA 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160"
|
|
tree.end
|
|
tree "ADCC_RESULT"
|
|
base d:0xB40
|
|
rgroup.word 0x0++0x1F
|
|
line.word 0x0 "ADCRESULT0,ADC Result 0 Register"
|
|
hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x1 "ADCRESULT1,ADC Result 1 Register"
|
|
hexmask.word 0x1 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x2 "ADCRESULT2,ADC Result 2 Register"
|
|
hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x3 "ADCRESULT3,ADC Result 3 Register"
|
|
hexmask.word 0x3 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x4 "ADCRESULT4,ADC Result 4 Register"
|
|
hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x5 "ADCRESULT5,ADC Result 5 Register"
|
|
hexmask.word 0x5 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x6 "ADCRESULT6,ADC Result 6 Register"
|
|
hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x7 "ADCRESULT7,ADC Result 7 Register"
|
|
hexmask.word 0x7 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x8 "ADCRESULT8,ADC Result 8 Register"
|
|
hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x9 "ADCRESULT9,ADC Result 9 Register"
|
|
hexmask.word 0x9 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xA "ADCRESULT10,ADC Result 10 Register"
|
|
hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xB "ADCRESULT11,ADC Result 11 Register"
|
|
hexmask.word 0xB 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xC "ADCRESULT12,ADC Result 12 Register"
|
|
hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xD "ADCRESULT13,ADC Result 13 Register"
|
|
hexmask.word 0xD 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xE "ADCRESULT14,ADC Result 14 Register"
|
|
hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xF "ADCRESULT15,ADC Result 15 Register"
|
|
hexmask.word 0xF 0.--15. 1. "RESULT,ADC Result"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x2 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x2 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x4 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x6 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long.word 0x6 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x6 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
tree.end
|
|
tree "ADCD"
|
|
base d:0x7580
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x0 13. "ADCBSY,ADC Busy" "0,1"
|
|
hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel"
|
|
bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down" "0,1"
|
|
bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position" "0,1"
|
|
line.word 0x1 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x1 7. "SIGNALMODE,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x1 6. "RESOLUTION,SOC Conversion Resolution" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "PRESCALE,ADC Clock Prescaler"
|
|
line.word 0x2 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x2 15. "BURSTEN,SOC Burst Mode Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "BURSTSIZE,SOC Burst Size Select"
|
|
hexmask.word.byte 0x2 0.--5. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word 0x5++0x1
|
|
line.word 0x0 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word 0x6++0xB
|
|
line.word 0x0 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
line.word 0x1 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x1 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 13. "INT2E,ADCINT2 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select"
|
|
bitfld.word 0x1 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x1 5. "INT1E,ADCINT1 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x1 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select"
|
|
line.word 0x2 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x2 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 13. "INT4E,ADCINT4 Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select"
|
|
bitfld.word 0x2 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x2 5. "INT3E,ADCINT3 Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select"
|
|
line.word 0x3 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
hexmask.word.byte 0x3 5.--9. 1. "RRPOINTER,Round Robin Pointer"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SOCPRIORITY,SOC Priority"
|
|
line.word 0x4 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x4 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x4 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
line.word 0x5 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x5 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x5 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x5 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word 0xD++0x1
|
|
line.word 0x0 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word 0xE++0x1
|
|
line.word 0x0 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long 0x10++0x3F
|
|
line.long 0x0 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "TRIGSEL,SOC0 Trigger Source Select"
|
|
hexmask.long.byte 0x0 15.--18. 1. "CHSEL,SOC0 Channel Select"
|
|
hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
line.long 0x2 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
hexmask.long.byte 0x2 20.--25. 1. "TRIGSEL,SOC1 Trigger Source Select"
|
|
hexmask.long.byte 0x2 15.--18. 1. "CHSEL,SOC1 Channel Select"
|
|
hexmask.long.word 0x2 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
line.long 0x4 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
hexmask.long.byte 0x4 20.--25. 1. "TRIGSEL,SOC2 Trigger Source Select"
|
|
hexmask.long.byte 0x4 15.--18. 1. "CHSEL,SOC2 Channel Select"
|
|
hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
line.long 0x6 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
hexmask.long.byte 0x6 20.--25. 1. "TRIGSEL,SOC3 Trigger Source Select"
|
|
hexmask.long.byte 0x6 15.--18. 1. "CHSEL,SOC3 Channel Select"
|
|
hexmask.long.word 0x6 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
line.long 0x8 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
hexmask.long.byte 0x8 20.--25. 1. "TRIGSEL,SOC4 Trigger Source Select"
|
|
hexmask.long.byte 0x8 15.--18. 1. "CHSEL,SOC4 Channel Select"
|
|
hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
line.long 0xA "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
hexmask.long.byte 0xA 20.--25. 1. "TRIGSEL,SOC5 Trigger Source Select"
|
|
hexmask.long.byte 0xA 15.--18. 1. "CHSEL,SOC5 Channel Select"
|
|
hexmask.long.word 0xA 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
line.long 0xC "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
hexmask.long.byte 0xC 20.--25. 1. "TRIGSEL,SOC6 Trigger Source Select"
|
|
hexmask.long.byte 0xC 15.--18. 1. "CHSEL,SOC6 Channel Select"
|
|
hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
line.long 0xE "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
hexmask.long.byte 0xE 20.--25. 1. "TRIGSEL,SOC7 Trigger Source Select"
|
|
hexmask.long.byte 0xE 15.--18. 1. "CHSEL,SOC7 Channel Select"
|
|
hexmask.long.word 0xE 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
line.long 0x10 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
hexmask.long.byte 0x10 20.--25. 1. "TRIGSEL,SOC8 Trigger Source Select"
|
|
hexmask.long.byte 0x10 15.--18. 1. "CHSEL,SOC8 Channel Select"
|
|
hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
line.long 0x12 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
hexmask.long.byte 0x12 20.--25. 1. "TRIGSEL,SOC9 Trigger Source Select"
|
|
hexmask.long.byte 0x12 15.--18. 1. "CHSEL,SOC9 Channel Select"
|
|
hexmask.long.word 0x12 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
line.long 0x14 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
hexmask.long.byte 0x14 20.--25. 1. "TRIGSEL,SOC10 Trigger Source Select"
|
|
hexmask.long.byte 0x14 15.--18. 1. "CHSEL,SOC10 Channel Select"
|
|
hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
line.long 0x16 "ADCSOC11CTL,ADC SOC11 Control Register"
|
|
hexmask.long.byte 0x16 20.--25. 1. "TRIGSEL,SOC11 Trigger Source Select"
|
|
hexmask.long.byte 0x16 15.--18. 1. "CHSEL,SOC11 Channel Select"
|
|
hexmask.long.word 0x16 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
line.long 0x18 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
hexmask.long.byte 0x18 20.--25. 1. "TRIGSEL,SOC12 Trigger Source Select"
|
|
hexmask.long.byte 0x18 15.--18. 1. "CHSEL,SOC12 Channel Select"
|
|
hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
line.long 0x1A "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
hexmask.long.byte 0x1A 20.--25. 1. "TRIGSEL,SOC13 Trigger Source Select"
|
|
hexmask.long.byte 0x1A 15.--18. 1. "CHSEL,SOC13 Channel Select"
|
|
hexmask.long.word 0x1A 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
line.long 0x1C "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
hexmask.long.byte 0x1C 20.--25. 1. "TRIGSEL,SOC14 Trigger Source Select"
|
|
hexmask.long.byte 0x1C 15.--18. 1. "CHSEL,SOC14 Channel Select"
|
|
hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
line.long 0x1E "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
hexmask.long.byte 0x1E 20.--25. 1. "TRIGSEL,SOC15 Trigger Source Select"
|
|
hexmask.long.byte 0x1E 15.--18. 1. "CHSEL,SOC15 Channel Select"
|
|
hexmask.long.word 0x1E 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word 0x30++0x1
|
|
line.word 0x0 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word 0x32++0x5
|
|
line.word 0x0 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear" "0,1"
|
|
line.word 0x2 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x2 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x2 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x2 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x2 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable" "0,1"
|
|
line.word 0x4 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x4 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x4 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
|
|
rgroup.word 0x39++0x3
|
|
line.word 0x0 "ADCCOUNTER,ADC Counter Register"
|
|
hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
|
|
line.word 0x1 "ADCREV,ADC Revision Register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TYPE,ADC Type"
|
|
group.word 0x3B++0x1
|
|
line.word 0x0 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration"
|
|
rgroup.word 0x41++0x1
|
|
line.word 0x0 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word 0x42++0x3
|
|
line.word 0x0 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Reference"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
|
|
line.long 0x2 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration"
|
|
rgroup.word 0x49++0x1
|
|
line.word 0x0 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word 0x4A++0x3
|
|
line.word 0x0 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Reference"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
line.long 0x2 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration"
|
|
rgroup.word 0x51++0x1
|
|
line.word 0x0 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word 0x52++0x3
|
|
line.word 0x0 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Reference"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
line.long 0x2 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word 0x58++0x1
|
|
line.word 0x0 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x0 5. "CBCEN,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration"
|
|
rgroup.word 0x59++0x1
|
|
line.word 0x0 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word 0x5A++0x3
|
|
line.word 0x0 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
line.word 0x1 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
hexmask.word 0x1 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Reference"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
line.long 0x2 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long.word 0x2 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x2 16. "LSIGN,Low Limit Sign Bit" "0,1"
|
|
hexmask.long.word 0x2 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word 0x6F++0x1
|
|
line.word 0x0 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
hexmask.word 0x0 0.--15. 1. "DELAY,Delay from ADCSOC fall edge to early interrupt generation."
|
|
group.long 0x70++0x17
|
|
line.long 0x0 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0"
|
|
line.long 0x2 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32"
|
|
line.long 0x4 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
hexmask.long 0x4 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64"
|
|
line.long 0x6 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
hexmask.long 0x6 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96"
|
|
line.long 0x8 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
hexmask.long 0x8 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128"
|
|
line.long 0xA "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
hexmask.long 0xA 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160"
|
|
tree.end
|
|
tree "ADCD_RESULT"
|
|
base d:0xB60
|
|
rgroup.word 0x0++0x1F
|
|
line.word 0x0 "ADCRESULT0,ADC Result 0 Register"
|
|
hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x1 "ADCRESULT1,ADC Result 1 Register"
|
|
hexmask.word 0x1 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x2 "ADCRESULT2,ADC Result 2 Register"
|
|
hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x3 "ADCRESULT3,ADC Result 3 Register"
|
|
hexmask.word 0x3 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x4 "ADCRESULT4,ADC Result 4 Register"
|
|
hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x5 "ADCRESULT5,ADC Result 5 Register"
|
|
hexmask.word 0x5 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x6 "ADCRESULT6,ADC Result 6 Register"
|
|
hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x7 "ADCRESULT7,ADC Result 7 Register"
|
|
hexmask.word 0x7 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x8 "ADCRESULT8,ADC Result 8 Register"
|
|
hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0x9 "ADCRESULT9,ADC Result 9 Register"
|
|
hexmask.word 0x9 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xA "ADCRESULT10,ADC Result 10 Register"
|
|
hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xB "ADCRESULT11,ADC Result 11 Register"
|
|
hexmask.word 0xB 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xC "ADCRESULT12,ADC Result 12 Register"
|
|
hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xD "ADCRESULT13,ADC Result 13 Register"
|
|
hexmask.word 0xD 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xE "ADCRESULT14,ADC Result 14 Register"
|
|
hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result"
|
|
line.word 0xF "ADCRESULT15,ADC Result 15 Register"
|
|
hexmask.word 0xF 0.--15. 1. "RESULT,ADC Result"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x2 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x2 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x4 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
line.long 0x6 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long.word 0x6 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long.word 0x6 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
tree.end
|
|
tree "ANALOGSS (Analog Subsystem)"
|
|
base d:0x5D700
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "INTOSC1TRIM,Internal Oscillator 1 Trim Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "VALFINETRIM,Oscillator Value Fine Trim Bits"
|
|
line.long 0x2 "INTOSC2TRIM,Internal Oscillator 2 Trim Register"
|
|
hexmask.long.word 0x2 0.--11. 1. "VALFINETRIM,Oscillator Value Fine Trim Bits"
|
|
group.word 0x26++0x1
|
|
line.word 0x0 "TSNSCTL,Temperature Sensor Control Register"
|
|
bitfld.word 0x0 0. "ENABLE,Temperature Sensor Enable" "0,1"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "LOCK,Lock Register"
|
|
bitfld.long 0x0 3. "TSNSCTL,Temperature Sensor Control Register Lock" "0,1"
|
|
group.long 0x36++0xF
|
|
line.long 0x0 "ANAREFTRIMA,Analog Reference Trim A Register"
|
|
hexmask.long.byte 0x0 11.--15. 1. "IREFTRIM,Reference Current Trim"
|
|
hexmask.long.byte 0x0 6.--10. 1. "BGSLOPETRIM,Bandgap Slope Trim"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BGVALTRIM,Bandgap Value Trim"
|
|
line.long 0x2 "ANAREFTRIMB,Analog Reference Trim B Register"
|
|
hexmask.long.byte 0x2 11.--15. 1. "IREFTRIM,Reference Current Trim"
|
|
hexmask.long.byte 0x2 6.--10. 1. "BGSLOPETRIM,Bandgap Slope Trim"
|
|
hexmask.long.byte 0x2 0.--5. 1. "BGVALTRIM,Bandgap Value Trim"
|
|
line.long 0x4 "ANAREFTRIMC,Analog Reference Trim C Register"
|
|
hexmask.long.byte 0x4 11.--15. 1. "IREFTRIM,Reference Current Trim"
|
|
hexmask.long.byte 0x4 6.--10. 1. "BGSLOPETRIM,Bandgap Slope Trim"
|
|
hexmask.long.byte 0x4 0.--5. 1. "BGVALTRIM,Bandgap Value Trim"
|
|
line.long 0x6 "ANAREFTRIMD,Analog Reference Trim D Register"
|
|
hexmask.long.byte 0x6 11.--15. 1. "IREFTRIM,Reference Current Trim"
|
|
hexmask.long.byte 0x6 6.--10. 1. "BGSLOPETRIM,Bandgap Slope Trim"
|
|
hexmask.long.byte 0x6 0.--5. 1. "BGVALTRIM,Bandgap Value Trim"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "AES (Advance Encryption Standard Accelerator)"
|
|
base d:0x0
|
|
tree "AES"
|
|
base d:0x4004A000
|
|
group.long 0x0++0x6F
|
|
line.long 0x0 "AES_KEY2_6,XTS Second Key or CBC-MAC Third Key"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,AES_KEY2[223:192] / AES_KEY3[95:64]"
|
|
line.long 0x4 "AES_KEY2_7,XTS Second Key or CBC-MAC Third Key"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,AES_KEY2[255:224] / AES_KEY3[127:96]"
|
|
line.long 0x8 "AES_KEY2_4,XTS/CCM Second Key or CBC-MAC Third Key"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,AES_KEY2[159:128] / AES_KEY3[31:0]"
|
|
line.long 0xC "AES_KEY2_5,XTS Second Key or CBC-MAC Third Key"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,AES_KEY2[191:160] / AES_KEY3[63:32]"
|
|
line.long 0x10 "AES_KEY2_2,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
hexmask.long 0x10 0.--31. 1. "KEY,AES_KEY2/AES_GHASH_H[95:64]"
|
|
line.long 0x14 "AES_KEY2_3,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
hexmask.long 0x14 0.--31. 1. "KEY,AES_KEY2/AES_GHASH_H[127:96]"
|
|
line.long 0x18 "AES_KEY2_0,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
hexmask.long 0x18 0.--31. 1. "KEY,AES_KEY2/AES_GHASH_H[31:0]"
|
|
line.long 0x1C "AES_KEY2_1,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
hexmask.long 0x1C 0.--31. 1. "KEY,AES_KEY2/AES_GHASH_H[63:32]"
|
|
line.long 0x20 "AES_KEY1_6,Key"
|
|
hexmask.long 0x20 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x24 "AES_KEY1_7,Key"
|
|
hexmask.long 0x24 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x28 "AES_KEY1_4,Key"
|
|
hexmask.long 0x28 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x2C "AES_KEY1_5,Key"
|
|
hexmask.long 0x2C 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x30 "AES_KEY1_2,Key"
|
|
hexmask.long 0x30 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x34 "AES_KEY1_3,Key"
|
|
hexmask.long 0x34 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x38 "AES_KEY1_0,Key"
|
|
hexmask.long 0x38 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x3C "AES_KEY1_1,Key"
|
|
hexmask.long 0x3C 0.--31. 1. "KEY,Key Data"
|
|
line.long 0x40 "AES_IV_IN_OUT_0,Initialization Vector 0"
|
|
hexmask.long 0x40 0.--31. 1. "DATA,Initialization Vector Input"
|
|
line.long 0x44 "AES_IV_IN_OUT_1,Initialization Vector 1"
|
|
hexmask.long 0x44 0.--31. 1. "DATA,Initialization Vector Input"
|
|
line.long 0x48 "AES_IV_IN_OUT_2,Initialization Vector 2"
|
|
hexmask.long 0x48 0.--31. 1. "DATA,Initialization Vector Input"
|
|
line.long 0x4C "AES_IV_IN_OUT_3,Initialization Vector 3"
|
|
hexmask.long 0x4C 0.--31. 1. "DATA,Initialization Vector Input"
|
|
line.long 0x50 "AES_CTRL,Input/Output Buffer Control and Mode Selection"
|
|
rbitfld.long 0x50 31. "CTXTRDY,Context Data Registers Ready" "0,1"
|
|
rbitfld.long 0x50 30. "SVCTXTRDY,AES TAG/IV Block(s) Ready" "0,1"
|
|
bitfld.long 0x50 29. "SAVE_CONTEXT,TAG or Result IV Save" "0,1"
|
|
newline
|
|
bitfld.long 0x50 22.--24. "CCM_M,Length of the authentication field for CCM operations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x50 19.--21. "CCM_L,Width of the length field for CCM operations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x50 18. "CCM,AES-CCM Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x50 16.--17. "GCM,AES-GCM Mode Enable" "0,1,2,3"
|
|
bitfld.long 0x50 15. "CBCMAC,AES-CBC MAC Enable" "0,1"
|
|
bitfld.long 0x50 14. "F9,AES f9 Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x50 13. "F8,AES f8 Mode Enable" "0,1"
|
|
bitfld.long 0x50 11.--12. "XTS,AES-XTS Operation Enable" "0,1,2,3"
|
|
bitfld.long 0x50 10. "CFB,Full block AES cipher feedback mode (CFB128) Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x50 9. "ICM,AES Integer Counter Mode (ICM) Enable" "0,1"
|
|
bitfld.long 0x50 7.--8. "CTR_WIDTH,AES-CTR Mode Counter Width" "0,1,2,3"
|
|
bitfld.long 0x50 6. "CTR,Counter Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x50 5. "MODE,ECB/CBC Mode" "0,1"
|
|
bitfld.long 0x50 3.--4. "KEY_SIZE,Key Size" "0,1,2,3"
|
|
bitfld.long 0x50 2. "DIRECTION,Encryption/Decryption Selection" "0,1"
|
|
newline
|
|
rbitfld.long 0x50 1. "INPUT_READY,Input Ready Status" "0,1"
|
|
rbitfld.long 0x50 0. "OUTPUT_READY,Output Ready Status" "0,1"
|
|
line.long 0x54 "AES_C_LENGTH_0,Crypto Data Length 0"
|
|
hexmask.long 0x54 0.--31. 1. "LENGTH,Cryptographic data length in bytes"
|
|
line.long 0x58 "AES_C_LENGTH_1,Crypto Data Length 1"
|
|
hexmask.long 0x58 0.--31. 1. "LENGTH,Cryptographic data length in bytes for all modes."
|
|
line.long 0x5C "AES_AUTH_LENGTH,AAD Data Length"
|
|
hexmask.long 0x5C 0.--31. 1. "AUTH,Authentication Data Length"
|
|
line.long 0x60 "AES_DATA_IN_OUT_0,Data Word 0"
|
|
hexmask.long 0x60 0.--31. 1. "DATA,Secure Data RW"
|
|
line.long 0x64 "AES_DATA_IN_OUT_1,Data Word 1"
|
|
hexmask.long 0x64 0.--31. 1. "DATA,Secure Data RW"
|
|
line.long 0x68 "AES_DATA_IN_OUT_2,Data Word 2"
|
|
hexmask.long 0x68 0.--31. 1. "DATA,Secure Data RW"
|
|
line.long 0x6C "AES_DATA_IN_OUT_3,Data Word 3"
|
|
hexmask.long 0x6C 0.--31. 1. "DATA,Secure Data RW"
|
|
rgroup.long 0x70++0x13
|
|
line.long 0x0 "AES_TAG_OUT_0,Hash Result 0"
|
|
hexmask.long 0x0 0.--31. 1. "HASH,Hash Result"
|
|
line.long 0x4 "AES_TAG_OUT_1,Hash Result 1"
|
|
hexmask.long 0x4 0.--31. 1. "HASH,Hash Result"
|
|
line.long 0x8 "AES_TAG_OUT_2,Hash Result 2"
|
|
hexmask.long 0x8 0.--31. 1. "HASH,Hash Result"
|
|
line.long 0xC "AES_TAG_OUT_3,Hash Result 3"
|
|
hexmask.long 0xC 0.--31. 1. "HASH,Hash Result"
|
|
line.long 0x10 "AES_REV,Module Revision Number"
|
|
hexmask.long 0x10 0.--31. 1. "REVISION,Revision number"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "AES_SYSCONFIG,System Configuration"
|
|
bitfld.long 0x0 9. "MAP_CONTEXT_OUT_ON_DATA_OUT,Map Context Out on Data Out Enable" "0,1"
|
|
bitfld.long 0x0 8. "DMA_REQ_CONTEXT_OUT_EN,DMA Request Context Out Enable" "0,1"
|
|
bitfld.long 0x0 7. "DMA_REQ_CONTEXT_IN_EN,DMA Request Context In Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DMA_REQ_DATA_OUT_EN,DMA Request Data Out Enable" "0,1"
|
|
bitfld.long 0x0 5. "DMA_REQ_DATA_IN_EN,DMA Request Data In Enable" "0,1"
|
|
bitfld.long 0x0 2.--3. "SIDLE,Slave Idle Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "SOFTRESET,Soft Reset" "0,1"
|
|
bitfld.long 0x0 0. "AUTOIDLE,autoidle" "0,1"
|
|
rgroup.long 0x88++0x7
|
|
line.long 0x0 "AES_SYSSTATUS,Reset Status"
|
|
bitfld.long 0x0 0. "RESETDONE,Reset Done" "0,1"
|
|
line.long 0x4 "AES_IRQSTATUS,Interrupt Status"
|
|
bitfld.long 0x4 3. "CONTEXT_OUT,Context Output Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DATA_OUT,Data Out Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "DATA_IN,Data In Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CONTEXT_IN,Context In Interrupt Status" "0,1"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "AES_IRQENABLE,Interrupt Enable"
|
|
bitfld.long 0x0 3. "CONTEXT_OUT,Context Out Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "DATA_OUT,Data Out Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "DATA_IN,Data In Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CONTEXT_IN,Context In Interrupt Enable" "0,1"
|
|
line.long 0x4 "AES_DIRTY_BITS,Accessed / Dirty Bits"
|
|
bitfld.long 0x4 1. "S_DIRTY,AES Dirty Bit" "0,1"
|
|
bitfld.long 0x4 0. "S_ACCESS,AES Access Bit" "0,1"
|
|
tree.end
|
|
tree "AES_SS"
|
|
base d:0x4004AC00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AESDMAINTEN,DMA Done Interrupt enable register"
|
|
bitfld.long 0x0 3. "DMADONECTXOUT,Enable bit for DMADONECTXOUT" "0,1"
|
|
bitfld.long 0x0 2. "DMADONEDOUT,Enable bit for DMADONEDOUT" "0,1"
|
|
bitfld.long 0x0 1. "DMADONEDIN,Enable bit for DMADONEDIN" "0,1"
|
|
bitfld.long 0x0 0. "DMADONECTXIN,Enable bit for DMADONECTXIN" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "AESDMASTATUS,DMA Done Interrupt status register"
|
|
bitfld.long 0x0 3. "DMADONECTXOUT,Status bit for DMADONECTXOUT" "0,1"
|
|
bitfld.long 0x0 2. "DMADONEDOUT,Status bit for DMADONEDOUT" "0,1"
|
|
bitfld.long 0x0 1. "DMADONEDIN,Status bit for DMADONEDIN" "0,1"
|
|
bitfld.long 0x0 0. "DMADONECTXIN,Status bit for DMADONECTXIN" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "AESDMASTATUSCLR,DMA Done Interrupt status clear register"
|
|
bitfld.long 0x0 3. "DMADONECTXOUT,Clear bit for AESDMASTSTAUS.DMADONECTXOUT" "0,1"
|
|
bitfld.long 0x0 2. "DMADONEDOUT,Clear bit for AESDMASTSTAUS.DMADONEDOUT" "0,1"
|
|
bitfld.long 0x0 1. "DMADONEDIN,Clear bit for AESDMASTSTAUS.DMADONEDIN" "0,1"
|
|
bitfld.long 0x0 0. "DMADONECTXIN,Clear bit for AESDMASTSTAUS.DMADONECTXIN" "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "BGCRC (Background CRC-32)"
|
|
base d:0x6340
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "BGCRC_EN,BGCRC Enable"
|
|
rbitfld.long 0x0 31. "RUN_STS,CRC module activity monitor" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "START,Start Bit used to Kick-off CRC calculations"
|
|
line.long 0x2 "BGCRC_CTRL1,BGCRC Control register 1"
|
|
hexmask.long.byte 0x2 16.--19. 1. "NMIDIS,NMI disable configuration"
|
|
bitfld.long 0x2 4. "FREE_SOFT,emulation control bit" "0,1"
|
|
line.long 0x4 "BGCRC_CTRL2,BGCRC Control register 2"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SCRUB_MODE,Scrub mode configuration"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TEST_HALT,TEST_HALT configuration"
|
|
hexmask.long.word 0x4 0.--9. 1. "BLOCK_SIZE,block size for memory check"
|
|
line.long 0x6 "BGCRC_START_ADDR,Start address for the BGCRC check"
|
|
hexmask.long 0x6 0.--31. 1. "START_ADDRESS,Start address"
|
|
line.long 0x8 "BGCRC_SEED,Seed for CRC calculation"
|
|
hexmask.long 0x8 0.--31. 1. "SEED,Initial CRC value"
|
|
group.long 0xE++0x3
|
|
line.long 0x0 "BGCRC_GOLDEN,Golden CRC to be compared against"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_VALUE,Expected CRC value"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "BGCRC_RESULT,CRC calculated"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_VALUE,CRC result register"
|
|
line.long 0x2 "BGCRC_CURR_ADDR,Current address regsiter"
|
|
hexmask.long 0x2 0.--31. 1. "CURRENT_ADDR,Current address from where the data is fetched."
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "BGCRC_WD_CFG,BGCRC windowed watchdog configuration"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WDDIS,CRC Watchdog disable"
|
|
line.long 0x2 "BGCRC_WD_MIN,BGCRC windowed watchdog min value"
|
|
hexmask.long 0x2 0.--31. 1. "MINVAL,Minimum value configuration for CRC windowed watchdog"
|
|
line.long 0x4 "BGCRC_WD_MAX,BGCRC windowed watchdog max value"
|
|
hexmask.long 0x4 0.--31. 1. "MAXVAL,Maximum value configuration for CRC windowed watchdog"
|
|
rgroup.long 0x22++0x3
|
|
line.long 0x0 "BGCRC_WD_CNT,BGCRC windowed watchdog count"
|
|
hexmask.long 0x0 0.--31. 1. "WD_CNT,CRC windowed watchdog counter value"
|
|
rgroup.long 0x2A++0x3
|
|
line.long 0x0 "BGCRC_NMIFLG,BGCRC NMI flag register"
|
|
bitfld.long 0x0 6. "WD_OVERFLOW,CRC/scrubbing did not complete within BGCRC_WD_MAX" "0,1"
|
|
bitfld.long 0x0 5. "WD_UNDERFLOW,CRC/scrubbing completed before BGCRC_WD_MIN" "0,1"
|
|
bitfld.long 0x0 4. "CORRECTABLE_ERR,Correctable ECC error obtained during memory data read." "0,1"
|
|
bitfld.long 0x0 3. "UNCORRECTABLE_ERR,Uncorrectable error obtained during memory data read." "0,1"
|
|
bitfld.long 0x0 2. "CRC_FAIL,CRC computation failed" "0,1"
|
|
group.long 0x2C++0x7
|
|
line.long 0x0 "BGCRC_NMICLR,BGCRC NMI flag clear register"
|
|
bitfld.long 0x0 6. "WD_OVERFLOW,WD_OVERFLOW NMI flag clear" "0,1"
|
|
bitfld.long 0x0 5. "WD_UNDERFLOW,WD_UNDERFLOW NMI flag clear" "0,1"
|
|
bitfld.long 0x0 4. "CORRECTABLE_ERR,CORRECTABLE_ERR NMI flag clear" "0,1"
|
|
bitfld.long 0x0 3. "UNCORRECTABLE_ERR,UNCORRECTABLE_ERR NMI flag clear" "0,1"
|
|
bitfld.long 0x0 2. "CRC_FAIL,CRC_FAIL NMI flag clear" "0,1"
|
|
line.long 0x2 "BGCRC_NMIFRC,BGCRC NMI flag force register"
|
|
bitfld.long 0x2 6. "WD_OVERFLOW,WD_OVERFLOW NMI force" "0,1"
|
|
bitfld.long 0x2 5. "WD_UNDERFLOW,WD_UNDERFLOW NMI force" "0,1"
|
|
bitfld.long 0x2 4. "CORRECTABLE_ERR,CORRECTABLE_ERR NMI force" "0,1"
|
|
bitfld.long 0x2 3. "UNCORRECTABLE_ERR,UNCORRECTABLE_ERR NMI force" "0,1"
|
|
bitfld.long 0x2 2. "CRC_FAIL,CRC_FAIL NMI force" "0,1"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "BGCRC_INTEN,Interrupt enable"
|
|
bitfld.long 0x0 6. "WD_OVERFLOW,WD_OVERFLOW interrupt enable register" "0,1"
|
|
bitfld.long 0x0 5. "WD_UNDERFLOW,WD_UNDERFLOW interrupt enable register" "0,1"
|
|
bitfld.long 0x0 4. "CORRECTABLE_ERR,CORRECTABLE_ERR interrupt enable register" "0,1"
|
|
bitfld.long 0x0 3. "UNCORRECTABLE_ERR,UNCORRECTABLE_ERR interrupt enable register" "0,1"
|
|
bitfld.long 0x0 2. "CRC_FAIL,CRC_FAIL interrupt enable register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TEST_DONE,TEST_DONE interrupt enable register" "0,1"
|
|
rgroup.long 0x36++0x3
|
|
line.long 0x0 "BGCRC_INTFLG,Interrupt flag"
|
|
bitfld.long 0x0 6. "WD_OVERFLOW,CRC/scrubbing did not complete within BGCRC_WD_MAX" "0,1"
|
|
bitfld.long 0x0 5. "WD_UNDERFLOW,CRC/scrubbing completed before BGCRC_WD_MIN" "0,1"
|
|
bitfld.long 0x0 4. "CORRECTABLE_ERR,Correctable ECC error obtained during memory data read." "0,1"
|
|
bitfld.long 0x0 3. "UNCORRECTABLE_ERR,Uncorrectable error obtained during memory data read." "0,1"
|
|
bitfld.long 0x0 2. "CRC_FAIL,CRC computation failed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TEST_DONE,TEST_DONE Interrupt status flag" "0,1"
|
|
bitfld.long 0x0 0. "INT,Global Interrupt status flag" "0,1"
|
|
group.long 0x38++0xF
|
|
line.long 0x0 "BGCRC_INTCLR,Interrupt flag clear"
|
|
bitfld.long 0x0 6. "WD_OVERFLOW,WD_OVERFLOW interrupt clear" "0,1"
|
|
bitfld.long 0x0 5. "WD_UNDERFLOW,WD_UNDERFLOW interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "CORRECTABLE_ERR,CORRECTABLE_ERR interrupt clear" "0,1"
|
|
bitfld.long 0x0 3. "UNCORRECTABLE_ERR,UNCORRECTABLE_ERR interrupt clear" "0,1"
|
|
bitfld.long 0x0 2. "CRC_FAIL,CRC_FAIL interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TEST_DONE,TEST_DONE Interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "INT,Global Interrupt clear" "0,1"
|
|
line.long 0x2 "BGCRC_INTFRC,Interrupt flag force"
|
|
bitfld.long 0x2 6. "WD_OVERFLOW,WD_OVERFLOW interrupt force" "0,1"
|
|
bitfld.long 0x2 5. "WD_UNDERFLOW,WD_UNDERFLOW interrupt force" "0,1"
|
|
bitfld.long 0x2 4. "CORRECTABLE_ERR,CORRECTABLE_ERR interrupt force" "0,1"
|
|
bitfld.long 0x2 3. "UNCORRECTABLE_ERR,UNCORRECTABLE_ERR interrupt force" "0,1"
|
|
bitfld.long 0x2 2. "CRC_FAIL,CRC_FAIL interrupt force" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "TEST_DONE,TEST_DONE Interrupt force" "0,1"
|
|
line.long 0x4 "BGCRC_LOCK,BGCRC register map lockconfiguration"
|
|
bitfld.long 0x4 29. "BGCRC_INTFRC,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 26. "BGCRC_INTEN,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 23. "BGCRC_NMIFRC,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 16. "BGCRC_WD_MAX,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 15. "BGCRC_WD_MIN,Register lock configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "BGCRC_WD_CFG,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 7. "BGCRC_GOLDEN,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 4. "BGCRC_SEED,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 3. "BGCRC_START_ADDR,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 2. "BGCRC_CTRL2,Register lock configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "BGCRC_CTRL1,Register lock configuration" "0,1"
|
|
bitfld.long 0x4 0. "BGCRC_EN,Register lock configuration" "0,1"
|
|
line.long 0x6 "BGCRC_COMMIT,BGCRC register map commit configuration"
|
|
bitfld.long 0x6 29. "BGCRC_INTFRC,Register lock committed" "0,1"
|
|
bitfld.long 0x6 26. "BGCRC_INTEN,Register lock committed" "0,1"
|
|
bitfld.long 0x6 23. "BGCRC_NMIFRC,Register lock committed" "0,1"
|
|
bitfld.long 0x6 16. "BGCRC_WD_MAX,Register lock committed" "0,1"
|
|
bitfld.long 0x6 15. "BGCRC_WD_MIN,Register lock committed" "0,1"
|
|
newline
|
|
bitfld.long 0x6 14. "BGCRC_WD_CFG,Register lock committed" "0,1"
|
|
bitfld.long 0x6 7. "BGCRC_GOLDEN,Register lock committed" "0,1"
|
|
bitfld.long 0x6 4. "BGCRC_SEED,Register lock committed" "0,1"
|
|
bitfld.long 0x6 3. "BGCRC_START_ADDR,Register lock committed" "0,1"
|
|
bitfld.long 0x6 2. "BGCRC_CTRL2,Register lock committed" "0,1"
|
|
newline
|
|
bitfld.long 0x6 1. "BGCRC_CTRL1,Register lock committed" "0,1"
|
|
bitfld.long 0x6 0. "BGCRC_EN,Register lock committed" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM"))
|
|
tree "CAN (Controller Area Network)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "CANA"
|
|
base d:0x48000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CAN_CTL,CAN Control Register"
|
|
bitfld.long 0x0 20. "DE3,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 19. "DE2,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 18. "DE1,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 17. "IE1,Interrupt line 1 Enable Disabled" "0,1"
|
|
rbitfld.long 0x0 16. "INITDBG,Debug Mode Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SWR,SW Reset Enable" "0,1"
|
|
hexmask.long.byte 0x0 10.--13. 1. "PMD,Parity on/off"
|
|
bitfld.long 0x0 9. "ABO,Auto-Bus-On Enable" "0,1"
|
|
bitfld.long 0x0 8. "IDS,Interruption Debug Support Enable" "0,1"
|
|
bitfld.long 0x0 7. "Test,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x0 5. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x0 3. "EIE,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "SIE,Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "IE0,Interrupt line 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Init,Initialization" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "CAN_ES,Error and Status Register"
|
|
bitfld.long 0x0 8. "PER,Parity Error Detected" "0,1"
|
|
bitfld.long 0x0 7. "BOff,Bus-Off State" "0,1"
|
|
bitfld.long 0x0 6. "EWarn,Warning State" "0,1"
|
|
bitfld.long 0x0 5. "EPass,Error Passive State" "0,1"
|
|
bitfld.long 0x0 4. "RxOk,Reception status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TxOk,Transmission status" "0,1"
|
|
bitfld.long 0x0 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x4 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CAN_BTR,Bit Timing Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRPE,Baud Rate Prescaler Extension"
|
|
bitfld.long 0x0 12.--14. "TSEG2,Time segment" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSEG1,Time segment"
|
|
bitfld.long 0x0 6.--7. "SJW,Synchronization Jump Width" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BRP,Baud Rate Prescaler"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CAN_INT,Interrupt Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INT1ID,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x0 0.--15. 1. "INT0ID,Interrupt Identifier"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CAN_TEST,Test Register"
|
|
bitfld.long 0x0 9. "RDA,RAM Direct Access Enable:" "0,1"
|
|
bitfld.long 0x0 8. "EXL,External Loopback Mode" "0,1"
|
|
rbitfld.long 0x0 7. "RX,CANRX Pin Status" "0,1"
|
|
bitfld.long 0x0 5.--6. "TX,CANTX Pin Control" "0,1,2,3"
|
|
bitfld.long 0x0 4. "LBACK,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SILENT,Silent Mode" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CAN_PERR,CAN Parity Error Code Register"
|
|
bitfld.long 0x0 8.--10. "WORD_NUM,Word Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CAN_RAM_INIT,CAN RAM Initialization Register"
|
|
rbitfld.long 0x0 5. "RAM_INIT_DONE,CAN RAM initialization complete" "0,1"
|
|
bitfld.long 0x0 4. "CAN_RAM_INIT,Initialize CAN Mailbox RAM" "0,1"
|
|
bitfld.long 0x0 3. "KEY3,KEY3" "0,1"
|
|
bitfld.long 0x0 2. "KEY2,KEY2" "0,1"
|
|
bitfld.long 0x0 1. "KEY1,KEY1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "KEY0,KEY0" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CAN_GLB_INT_EN,CAN Global Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for CANINT0" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "CAN_GLB_INT_FLG,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for CANINT0" "0,1"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CAN_GLB_INT_CLR,CAN Global Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for CANINT0" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CAN_ABOTR,Auto-Bus-On Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "ABO_Time,Auto-Bus-On Timer"
|
|
rgroup.long 0x84++0x7
|
|
line.long 0x0 "CAN_TXRQ_X,CAN Transmission Request Register"
|
|
bitfld.long 0x0 2.--3. "TxRqstReg2,Transmit Request Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TxRqstReg1,Transmit Request Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_TXRQ_21,CAN Transmission Request 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "TxRqst,Transmission Request Bits"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x0 "CAN_NDAT_X,CAN New Data Register"
|
|
bitfld.long 0x0 2.--3. "NewDatReg2,New Data Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "NewDatReg1,New Data Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_NDAT_21,CAN New Data 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "NewDat,New Data Bits"
|
|
rgroup.long 0xAC++0x7
|
|
line.long 0x0 "CAN_IPEN_X,CAN Interrupt Pending Register"
|
|
bitfld.long 0x0 2.--3. "IntPndReg2,Interrupt Pending Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IntPndReg1,Interrupt Pending Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_IPEN_21,CAN Interrupt Pending 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "IntPnd,Interrupt Pending"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "CAN_MVAL_X,CAN Message Valid Register"
|
|
bitfld.long 0x0 2.--3. "MsgValReg2,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MsgValReg1,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_MVAL_21,CAN Message Valid 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "MsgValReg,Message Valid Bits"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "CAN_IP_MUX21,CAN Interrupt Multiplexer 2_1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IntMux,Interrupt Mux"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "CAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXRQST,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,`"
|
|
line.long 0xC "CAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x0 "CAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TxRqst,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0xC "CAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CAN_IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x0 15. "IF3Upd,IF3 Update Data" "0,1"
|
|
rbitfld.long 0x0 12. "IF3SDB,IF3 Status of Data B read access" "0,1"
|
|
rbitfld.long 0x0 11. "IF3SDA,IF3 Status of Data A read access" "0,1"
|
|
rbitfld.long 0x0 10. "IF3SC,IF3 Status of Control bits read access" "0,1"
|
|
rbitfld.long 0x0 9. "IF3SA,IF3 Status of Arbitration data read access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "IF3SM,IF3 Status of Mask data read access" "0,1"
|
|
bitfld.long 0x0 4. "Data_B,Data B read observation" "0,1"
|
|
bitfld.long 0x0 3. "Data_A,Data A read observation" "0,1"
|
|
bitfld.long 0x0 2. "Ctrl,Ctrl read observation" "0,1"
|
|
bitfld.long 0x0 1. "Arb,Arbitration data read observation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Mask,Mask data read observation" "0,1"
|
|
rgroup.long 0x144++0x13
|
|
line.long 0x0 "CAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x0 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x0 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x0 0.--28. 1. "Msk,Mask"
|
|
line.long 0x4 "CAN_IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x4 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x4 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x4 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0x8 "CAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x8 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0x8 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0x8 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0x8 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0x8 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0x8 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DLC,Data length code"
|
|
line.long 0xC "CAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x10 "CAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "CAN_IF3UPD,IF3 Update Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "IF3UpdEn,IF3 Update Enabled"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "CANB"
|
|
base d:0x4A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CAN_CTL,CAN Control Register"
|
|
bitfld.long 0x0 20. "DE3,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 19. "DE2,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 18. "DE1,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 17. "IE1,Interrupt line 1 Enable Disabled" "0,1"
|
|
rbitfld.long 0x0 16. "INITDBG,Debug Mode Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SWR,SW Reset Enable" "0,1"
|
|
hexmask.long.byte 0x0 10.--13. 1. "PMD,Parity on/off"
|
|
bitfld.long 0x0 9. "ABO,Auto-Bus-On Enable" "0,1"
|
|
bitfld.long 0x0 8. "IDS,Interruption Debug Support Enable" "0,1"
|
|
bitfld.long 0x0 7. "Test,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x0 5. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x0 3. "EIE,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "SIE,Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "IE0,Interrupt line 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Init,Initialization" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "CAN_ES,Error and Status Register"
|
|
bitfld.long 0x0 8. "PER,Parity Error Detected" "0,1"
|
|
bitfld.long 0x0 7. "BOff,Bus-Off State" "0,1"
|
|
bitfld.long 0x0 6. "EWarn,Warning State" "0,1"
|
|
bitfld.long 0x0 5. "EPass,Error Passive State" "0,1"
|
|
bitfld.long 0x0 4. "RxOk,Reception status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TxOk,Transmission status" "0,1"
|
|
bitfld.long 0x0 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x4 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CAN_BTR,Bit Timing Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRPE,Baud Rate Prescaler Extension"
|
|
bitfld.long 0x0 12.--14. "TSEG2,Time segment" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSEG1,Time segment"
|
|
bitfld.long 0x0 6.--7. "SJW,Synchronization Jump Width" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BRP,Baud Rate Prescaler"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CAN_INT,Interrupt Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INT1ID,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x0 0.--15. 1. "INT0ID,Interrupt Identifier"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CAN_TEST,Test Register"
|
|
bitfld.long 0x0 9. "RDA,RAM Direct Access Enable:" "0,1"
|
|
bitfld.long 0x0 8. "EXL,External Loopback Mode" "0,1"
|
|
rbitfld.long 0x0 7. "RX,CANRX Pin Status" "0,1"
|
|
bitfld.long 0x0 5.--6. "TX,CANTX Pin Control" "0,1,2,3"
|
|
bitfld.long 0x0 4. "LBACK,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SILENT,Silent Mode" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CAN_PERR,CAN Parity Error Code Register"
|
|
bitfld.long 0x0 8.--10. "WORD_NUM,Word Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CAN_RAM_INIT,CAN RAM Initialization Register"
|
|
rbitfld.long 0x0 5. "RAM_INIT_DONE,CAN RAM initialization complete" "0,1"
|
|
bitfld.long 0x0 4. "CAN_RAM_INIT,Initialize CAN Mailbox RAM" "0,1"
|
|
bitfld.long 0x0 3. "KEY3,KEY3" "0,1"
|
|
bitfld.long 0x0 2. "KEY2,KEY2" "0,1"
|
|
bitfld.long 0x0 1. "KEY1,KEY1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "KEY0,KEY0" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CAN_GLB_INT_EN,CAN Global Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for CANINT0" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "CAN_GLB_INT_FLG,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for CANINT0" "0,1"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CAN_GLB_INT_CLR,CAN Global Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for CANINT0" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CAN_ABOTR,Auto-Bus-On Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "ABO_Time,Auto-Bus-On Timer"
|
|
rgroup.long 0x84++0x7
|
|
line.long 0x0 "CAN_TXRQ_X,CAN Transmission Request Register"
|
|
bitfld.long 0x0 2.--3. "TxRqstReg2,Transmit Request Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TxRqstReg1,Transmit Request Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_TXRQ_21,CAN Transmission Request 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "TxRqst,Transmission Request Bits"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x0 "CAN_NDAT_X,CAN New Data Register"
|
|
bitfld.long 0x0 2.--3. "NewDatReg2,New Data Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "NewDatReg1,New Data Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_NDAT_21,CAN New Data 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "NewDat,New Data Bits"
|
|
rgroup.long 0xAC++0x7
|
|
line.long 0x0 "CAN_IPEN_X,CAN Interrupt Pending Register"
|
|
bitfld.long 0x0 2.--3. "IntPndReg2,Interrupt Pending Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IntPndReg1,Interrupt Pending Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_IPEN_21,CAN Interrupt Pending 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "IntPnd,Interrupt Pending"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "CAN_MVAL_X,CAN Message Valid Register"
|
|
bitfld.long 0x0 2.--3. "MsgValReg2,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MsgValReg1,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_MVAL_21,CAN Message Valid 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "MsgValReg,Message Valid Bits"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "CAN_IP_MUX21,CAN Interrupt Multiplexer 2_1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IntMux,Interrupt Mux"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "CAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXRQST,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,`"
|
|
line.long 0xC "CAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x0 "CAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TxRqst,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0xC "CAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CAN_IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x0 15. "IF3Upd,IF3 Update Data" "0,1"
|
|
rbitfld.long 0x0 12. "IF3SDB,IF3 Status of Data B read access" "0,1"
|
|
rbitfld.long 0x0 11. "IF3SDA,IF3 Status of Data A read access" "0,1"
|
|
rbitfld.long 0x0 10. "IF3SC,IF3 Status of Control bits read access" "0,1"
|
|
rbitfld.long 0x0 9. "IF3SA,IF3 Status of Arbitration data read access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "IF3SM,IF3 Status of Mask data read access" "0,1"
|
|
bitfld.long 0x0 4. "Data_B,Data B read observation" "0,1"
|
|
bitfld.long 0x0 3. "Data_A,Data A read observation" "0,1"
|
|
bitfld.long 0x0 2. "Ctrl,Ctrl read observation" "0,1"
|
|
bitfld.long 0x0 1. "Arb,Arbitration data read observation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Mask,Mask data read observation" "0,1"
|
|
rgroup.long 0x144++0x13
|
|
line.long 0x0 "CAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x0 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x0 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x0 0.--28. 1. "Msk,Mask"
|
|
line.long 0x4 "CAN_IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x4 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x4 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x4 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0x8 "CAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x8 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0x8 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0x8 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0x8 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0x8 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0x8 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DLC,Data length code"
|
|
line.long 0xC "CAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x10 "CAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "CAN_IF3UPD,IF3 Update Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "IF3UpdEn,IF3 Update Enabled"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "CANA"
|
|
base d:0x40070000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CAN_CTL,CAN Control Register"
|
|
bitfld.long 0x0 20. "DE3,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 19. "DE2,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 18. "DE1,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 17. "IE1,Interrupt line 1 Enable Disabled" "0,1"
|
|
rbitfld.long 0x0 16. "INITDBG,Debug Mode Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SWR,SW Reset Enable" "0,1"
|
|
hexmask.long.byte 0x0 10.--13. 1. "PMD,Parity on/off"
|
|
bitfld.long 0x0 9. "ABO,Auto-Bus-On Enable" "0,1"
|
|
bitfld.long 0x0 8. "IDS,Interruption Debug Support Enable" "0,1"
|
|
bitfld.long 0x0 7. "Test,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x0 5. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x0 3. "EIE,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "SIE,Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "IE0,Interrupt line 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Init,Initialization" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "CAN_ES,Error and Status Register"
|
|
bitfld.long 0x0 8. "PER,Parity Error Detected" "0,1"
|
|
bitfld.long 0x0 7. "BOff,Bus-Off State" "0,1"
|
|
bitfld.long 0x0 6. "EWarn,Warning State" "0,1"
|
|
bitfld.long 0x0 5. "EPass,Error Passive State" "0,1"
|
|
bitfld.long 0x0 4. "RxOk,Reception status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TxOk,Transmission status" "0,1"
|
|
bitfld.long 0x0 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x4 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CAN_BTR,Bit Timing Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRPE,Baud Rate Prescaler Extension"
|
|
bitfld.long 0x0 12.--14. "TSEG2,Time segment" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSEG1,Time segment"
|
|
bitfld.long 0x0 6.--7. "SJW,Synchronization Jump Width" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BRP,Baud Rate Prescaler"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CAN_INT,Interrupt Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INT1ID,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x0 0.--15. 1. "INT0ID,Interrupt Identifier"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CAN_TEST,Test Register"
|
|
bitfld.long 0x0 9. "RDA,RAM Direct Access Enable:" "0,1"
|
|
bitfld.long 0x0 8. "EXL,External Loopback Mode" "0,1"
|
|
rbitfld.long 0x0 7. "RX,CANRX Pin Status" "0,1"
|
|
bitfld.long 0x0 5.--6. "TX,CANTX Pin Control" "0,1,2,3"
|
|
bitfld.long 0x0 4. "LBACK,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SILENT,Silent Mode" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CAN_PERR,CAN Parity Error Code Register"
|
|
bitfld.long 0x0 8.--10. "WORD_NUM,Word Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CAN_RAM_INIT,CAN RAM Initialization Register"
|
|
rbitfld.long 0x0 5. "RAM_INIT_DONE,CAN RAM initialization complete" "0,1"
|
|
bitfld.long 0x0 4. "CAN_RAM_INIT,Initialize CAN Mailbox RAM" "0,1"
|
|
bitfld.long 0x0 3. "KEY3,KEY3" "0,1"
|
|
bitfld.long 0x0 2. "KEY2,KEY2" "0,1"
|
|
bitfld.long 0x0 1. "KEY1,KEY1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "KEY0,KEY0" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CAN_GLB_INT_EN,CAN Global Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for CANINT0" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "CAN_GLB_INT_FLG,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for CANINT0" "0,1"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CAN_GLB_INT_CLR,CAN Global Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for CANINT0" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CAN_ABOTR,Auto-Bus-On Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "ABO_Time,Auto-Bus-On Timer"
|
|
rgroup.long 0x84++0x7
|
|
line.long 0x0 "CAN_TXRQ_X,CAN Transmission Request Register"
|
|
bitfld.long 0x0 2.--3. "TxRqstReg2,Transmit Request Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TxRqstReg1,Transmit Request Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_TXRQ_21,CAN Transmission Request 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "TxRqst,Transmission Request Bits"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x0 "CAN_NDAT_X,CAN New Data Register"
|
|
bitfld.long 0x0 2.--3. "NewDatReg2,New Data Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "NewDatReg1,New Data Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_NDAT_21,CAN New Data 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "NewDat,New Data Bits"
|
|
rgroup.long 0xAC++0x7
|
|
line.long 0x0 "CAN_IPEN_X,CAN Interrupt Pending Register"
|
|
bitfld.long 0x0 2.--3. "IntPndReg2,Interrupt Pending Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IntPndReg1,Interrupt Pending Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_IPEN_21,CAN Interrupt Pending 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "IntPnd,Interrupt Pending"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "CAN_MVAL_X,CAN Message Valid Register"
|
|
bitfld.long 0x0 2.--3. "MsgValReg2,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MsgValReg1,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_MVAL_21,CAN Message Valid 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "MsgValReg,Message Valid Bits"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "CAN_IP_MUX21,CAN Interrupt Multiplexer 2_1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IntMux,Interrupt Mux"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "CAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXRQST,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,`"
|
|
line.long 0xC "CAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x0 "CAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TxRqst,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0xC "CAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CAN_IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x0 15. "IF3Upd,IF3 Update Data" "0,1"
|
|
rbitfld.long 0x0 12. "IF3SDB,IF3 Status of Data B read access" "0,1"
|
|
rbitfld.long 0x0 11. "IF3SDA,IF3 Status of Data A read access" "0,1"
|
|
rbitfld.long 0x0 10. "IF3SC,IF3 Status of Control bits read access" "0,1"
|
|
rbitfld.long 0x0 9. "IF3SA,IF3 Status of Arbitration data read access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "IF3SM,IF3 Status of Mask data read access" "0,1"
|
|
bitfld.long 0x0 4. "Data_B,Data B read observation" "0,1"
|
|
bitfld.long 0x0 3. "Data_A,Data A read observation" "0,1"
|
|
bitfld.long 0x0 2. "Ctrl,Ctrl read observation" "0,1"
|
|
bitfld.long 0x0 1. "Arb,Arbitration data read observation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Mask,Mask data read observation" "0,1"
|
|
rgroup.long 0x144++0x13
|
|
line.long 0x0 "CAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x0 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x0 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x0 0.--28. 1. "Msk,Mask"
|
|
line.long 0x4 "CAN_IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x4 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x4 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x4 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0x8 "CAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x8 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0x8 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0x8 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0x8 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0x8 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0x8 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DLC,Data length code"
|
|
line.long 0xC "CAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x10 "CAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "CAN_IF3UPD,IF3 Update Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "IF3UpdEn,IF3 Update Enabled"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "CANB"
|
|
base d:0x40074000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CAN_CTL,CAN Control Register"
|
|
bitfld.long 0x0 20. "DE3,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 19. "DE2,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 18. "DE1,Enable DMA request line" "0,1"
|
|
bitfld.long 0x0 17. "IE1,Interrupt line 1 Enable Disabled" "0,1"
|
|
rbitfld.long 0x0 16. "INITDBG,Debug Mode Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SWR,SW Reset Enable" "0,1"
|
|
hexmask.long.byte 0x0 10.--13. 1. "PMD,Parity on/off"
|
|
bitfld.long 0x0 9. "ABO,Auto-Bus-On Enable" "0,1"
|
|
bitfld.long 0x0 8. "IDS,Interruption Debug Support Enable" "0,1"
|
|
bitfld.long 0x0 7. "Test,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x0 5. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x0 3. "EIE,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "SIE,Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "IE0,Interrupt line 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Init,Initialization" "0,1"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "CAN_ES,Error and Status Register"
|
|
bitfld.long 0x0 8. "PER,Parity Error Detected" "0,1"
|
|
bitfld.long 0x0 7. "BOff,Bus-Off State" "0,1"
|
|
bitfld.long 0x0 6. "EWarn,Warning State" "0,1"
|
|
bitfld.long 0x0 5. "EPass,Error Passive State" "0,1"
|
|
bitfld.long 0x0 4. "RxOk,Reception status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TxOk,Transmission status" "0,1"
|
|
bitfld.long 0x0 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x4 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CAN_BTR,Bit Timing Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BRPE,Baud Rate Prescaler Extension"
|
|
bitfld.long 0x0 12.--14. "TSEG2,Time segment" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSEG1,Time segment"
|
|
bitfld.long 0x0 6.--7. "SJW,Synchronization Jump Width" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BRP,Baud Rate Prescaler"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CAN_INT,Interrupt Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INT1ID,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x0 0.--15. 1. "INT0ID,Interrupt Identifier"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CAN_TEST,Test Register"
|
|
bitfld.long 0x0 9. "RDA,RAM Direct Access Enable:" "0,1"
|
|
bitfld.long 0x0 8. "EXL,External Loopback Mode" "0,1"
|
|
rbitfld.long 0x0 7. "RX,CANRX Pin Status" "0,1"
|
|
bitfld.long 0x0 5.--6. "TX,CANTX Pin Control" "0,1,2,3"
|
|
bitfld.long 0x0 4. "LBACK,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SILENT,Silent Mode" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CAN_PERR,CAN Parity Error Code Register"
|
|
bitfld.long 0x0 8.--10. "WORD_NUM,Word Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CAN_RAM_INIT,CAN RAM Initialization Register"
|
|
rbitfld.long 0x0 5. "RAM_INIT_DONE,CAN RAM initialization complete" "0,1"
|
|
bitfld.long 0x0 4. "CAN_RAM_INIT,Initialize CAN Mailbox RAM" "0,1"
|
|
bitfld.long 0x0 3. "KEY3,KEY3" "0,1"
|
|
bitfld.long 0x0 2. "KEY2,KEY2" "0,1"
|
|
bitfld.long 0x0 1. "KEY1,KEY1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "KEY0,KEY0" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CAN_GLB_INT_EN,CAN Global Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for CANINT0" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "CAN_GLB_INT_FLG,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for CANINT0" "0,1"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CAN_GLB_INT_CLR,CAN Global Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for CANINT1" "0,1"
|
|
bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for CANINT0" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CAN_ABOTR,Auto-Bus-On Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "ABO_Time,Auto-Bus-On Timer"
|
|
rgroup.long 0x84++0x7
|
|
line.long 0x0 "CAN_TXRQ_X,CAN Transmission Request Register"
|
|
bitfld.long 0x0 2.--3. "TxRqstReg2,Transmit Request Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TxRqstReg1,Transmit Request Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_TXRQ_21,CAN Transmission Request 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "TxRqst,Transmission Request Bits"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x0 "CAN_NDAT_X,CAN New Data Register"
|
|
bitfld.long 0x0 2.--3. "NewDatReg2,New Data Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "NewDatReg1,New Data Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_NDAT_21,CAN New Data 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "NewDat,New Data Bits"
|
|
rgroup.long 0xAC++0x7
|
|
line.long 0x0 "CAN_IPEN_X,CAN Interrupt Pending Register"
|
|
bitfld.long 0x0 2.--3. "IntPndReg2,Interrupt Pending Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IntPndReg1,Interrupt Pending Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_IPEN_21,CAN Interrupt Pending 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "IntPnd,Interrupt Pending"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "CAN_MVAL_X,CAN Message Valid Register"
|
|
bitfld.long 0x0 2.--3. "MsgValReg2,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MsgValReg1,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x4 "CAN_MVAL_21,CAN Message Valid 2_1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "MsgValReg,Message Valid Bits"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "CAN_IP_MUX21,CAN Interrupt Multiplexer 2_1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IntMux,Interrupt Mux"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "CAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXRQST,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,`"
|
|
line.long 0xC "CAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x120++0x17
|
|
line.long 0x0 "CAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x0 23. "DIR,Write/Read Direction" "0,1"
|
|
bitfld.long 0x0 22. "Mask,Access Mask Bits" "0,1"
|
|
bitfld.long 0x0 21. "Arb,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x0 20. "Control,Access Control Bits" "0,1"
|
|
bitfld.long 0x0 19. "ClrIntPnd,Clear Interrupt Pending Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TxRqst,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "DATA_A,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x0 16. "DATA_B,Access Data Bytes 4-7" "0,1"
|
|
rbitfld.long 0x0 15. "Busy,Busy Flag" "0,1"
|
|
bitfld.long 0x0 14. "DMAactive,DMA Status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MSG_NUM,Message Number"
|
|
line.long 0x4 "CAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x4 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x4 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "Msk,Identifier Mask"
|
|
line.long 0x8 "CAN_IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x8 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x8 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x8 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x8 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0xC "CAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0xC 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0xC 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0xC 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0xC 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0xC 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0xC 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DLC,Data length code"
|
|
line.long 0x10 "CAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x14 "CAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x14 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x14 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CAN_IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x0 15. "IF3Upd,IF3 Update Data" "0,1"
|
|
rbitfld.long 0x0 12. "IF3SDB,IF3 Status of Data B read access" "0,1"
|
|
rbitfld.long 0x0 11. "IF3SDA,IF3 Status of Data A read access" "0,1"
|
|
rbitfld.long 0x0 10. "IF3SC,IF3 Status of Control bits read access" "0,1"
|
|
rbitfld.long 0x0 9. "IF3SA,IF3 Status of Arbitration data read access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "IF3SM,IF3 Status of Mask data read access" "0,1"
|
|
bitfld.long 0x0 4. "Data_B,Data B read observation" "0,1"
|
|
bitfld.long 0x0 3. "Data_A,Data A read observation" "0,1"
|
|
bitfld.long 0x0 2. "Ctrl,Ctrl read observation" "0,1"
|
|
bitfld.long 0x0 1. "Arb,Arbitration data read observation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "Mask,Mask data read observation" "0,1"
|
|
rgroup.long 0x144++0x13
|
|
line.long 0x0 "CAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x0 31. "MXtd,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x0 30. "MDir,Mask Message Direction" "0,1"
|
|
hexmask.long 0x0 0.--28. 1. "Msk,Mask"
|
|
line.long 0x4 "CAN_IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x4 31. "MsgVal,Message Valid" "0,1"
|
|
bitfld.long 0x4 30. "Xtd,Extended Identifier" "0,1"
|
|
bitfld.long 0x4 29. "Dir,Message Direction" "0,1"
|
|
hexmask.long 0x4 0.--28. 1. "ID,Message Identifier"
|
|
line.long 0x8 "CAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x8 15. "NewDat,New Data" "0,1"
|
|
bitfld.long 0x8 14. "MsgLst,Message Lost" "0,1"
|
|
bitfld.long 0x8 13. "IntPnd,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "UMask,Use Acceptance Mask" "0,1"
|
|
bitfld.long 0x8 11. "TxIE,Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RxIE,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 9. "RmtEn,Remote Enable" "0,1"
|
|
bitfld.long 0x8 8. "TxRqst,Transmit Request" "0,1"
|
|
bitfld.long 0x8 7. "EoB,End of Block" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DLC,Data length code"
|
|
line.long 0xC "CAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "Data_0,Data Byte 0"
|
|
line.long 0x10 "CAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long.byte 0x10 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long.byte 0x10 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long.byte 0x10 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "CAN_IF3UPD,IF3 Update Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "IF3UpdEn,IF3 Update Enabled"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838?D"))
|
|
tree "CLA (Control Law Accelerator)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "CPU1Cla1Regs"
|
|
base d:0x1400
|
|
group.word 0x0++0xF
|
|
line.word 0x0 "MVECT1,Task Interrupt Vector"
|
|
hexmask.word 0x0 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x1 "MVECT2,Task Interrupt Vector"
|
|
hexmask.word 0x1 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x2 "MVECT3,Task Interrupt Vector"
|
|
hexmask.word 0x2 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x3 "MVECT4,Task Interrupt Vector"
|
|
hexmask.word 0x3 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x4 "MVECT5,Task Interrupt Vector"
|
|
hexmask.word 0x4 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x5 "MVECT6,Task Interrupt Vector"
|
|
hexmask.word 0x5 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x6 "MVECT7,Task Interrupt Vector"
|
|
hexmask.word 0x6 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x7 "MVECT8,Task Interrupt Vector"
|
|
hexmask.word 0x7 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "MCTL,Control Register"
|
|
bitfld.word 0x0 2. "IACKE,IACK enable" "0,1"
|
|
bitfld.word 0x0 1. "SOFTRESET,Soft Reset" "0,1"
|
|
bitfld.word 0x0 0. "HARDRESET,Hard Reset" "0,1"
|
|
rgroup.word 0x1B++0x1
|
|
line.word 0x0 "_MVECTBGRNDACTIVE,Active register for MVECTBGRND."
|
|
hexmask.word 0x0 0.--15. 1. "i16,Active register for the Background Task Vector"
|
|
group.word 0x1C++0x7
|
|
line.word 0x0 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x0 7. "TASK8,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 6. "TASK7,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 5. "TASK6,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 4. "TASK5,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 3. "TASK4,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 2. "TASK3,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 1. "TASK2,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 0. "TASK1,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
line.word 0x1 "_MSTSBGRND,Status register for the back ground task."
|
|
bitfld.word 0x1 2. "BGOVF,background task harware trigger overflow." "0,1"
|
|
rbitfld.word 0x1 1. "_BGINTM,Indicates whether background task can be interrupted." "0,1"
|
|
rbitfld.word 0x1 0. "RUN,Background task run status bit." "0,1"
|
|
line.word 0x2 "_MCTLBGRND,Control register for the back ground task."
|
|
bitfld.word 0x2 15. "BGEN,Enable background task" "0,1"
|
|
bitfld.word 0x2 1. "TRIGEN,Background task hardware trigger enable" "0,1"
|
|
bitfld.word 0x2 0. "BGSTART,Background task start bit" "0,1"
|
|
line.word 0x3 "_MVECTBGRND,Vector for the back ground task."
|
|
hexmask.word 0x3 0.--15. 1. "i16,Background task vector"
|
|
rgroup.word 0x20++0x3
|
|
line.word 0x0 "MIFR,Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "INT8,Task 8 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Task 7 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Task 6 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Task 5 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Task 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Task 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Task 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Task 1 Interrupt Flag" "0,1"
|
|
line.word 0x1 "MIOVF,Interrupt Overflow Flag Register"
|
|
bitfld.word 0x1 7. "INT8,Task 8 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Task 7 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Task 6 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Task 5 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Task 4 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Task 3 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Task 2 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Task 1 Interrupt Overflow Flag" "0,1"
|
|
group.word 0x22++0x7
|
|
line.word 0x0 "MIFRC,Interrupt Force Register"
|
|
bitfld.word 0x0 7. "INT8,Task 8 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Task 7 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Task 6 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Task 5 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Task 4 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Task 3 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Task 2 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Task 1 Interrupt Force" "0,1"
|
|
line.word 0x1 "MICLR,Interrupt Flag Clear Register"
|
|
bitfld.word 0x1 7. "INT8,Task 8 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Task 7 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Task 6 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Task 5 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Task 4 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Task 3 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Task 2 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Task 1 Interrupt Flag Clear" "0,1"
|
|
line.word 0x2 "MICLROVF,Interrupt Overflow Flag Clear Register"
|
|
bitfld.word 0x2 7. "INT8,Task 8 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 6. "INT7,Task 7 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 5. "INT6,Task 6 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 4. "INT5,Task 5 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 3. "INT4,Task 4 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 2. "INT3,Task 3 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 1. "INT2,Task 2 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 0. "INT1,Task 1 Interrupt Overflow Flag Clear" "0,1"
|
|
line.word 0x3 "MIER,Interrupt Enable Register"
|
|
bitfld.word 0x3 7. "INT8,Task 8 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 6. "INT7,Task 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 5. "INT6,Task 6 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 4. "INT5,Task 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 3. "INT4,Task 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 2. "INT3,Task 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 1. "INT2,Task 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 0. "INT1,Task 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x26++0x7
|
|
line.word 0x0 "MIRUN,Interrupt Run Status Register"
|
|
bitfld.word 0x0 7. "INT8,Task 8 Run Status" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Task 7 Run Status" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Task 6 Run Status" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Task 5 Run Status" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Task 4 Run Status" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Task 3 Run Status" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Task 2 Run Status" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Task 1 Run Status" "0,1"
|
|
line.word 0x2 "_MPC,CLA Program Counter"
|
|
hexmask.word 0x2 0.--15. 1. "_MPC,Points to the instruction"
|
|
line.word 0x4 "_MAR0,CLA Auxiliary Register 0"
|
|
hexmask.word 0x4 0.--15. 1. "_MAR0,CLA Auxillary Register 0"
|
|
line.word 0x5 "_MAR1,CLA Auxiliary Register 1"
|
|
hexmask.word 0x5 0.--15. 1. "_MAR1,CLA Auxillary Register 1"
|
|
rgroup.long 0x2E++0x13
|
|
line.long 0x0 "_MSTF,CLA Floating-Point Status Register"
|
|
hexmask.long.word 0x0 12.--27. 1. "_RPC,Return PC"
|
|
bitfld.long 0x0 11. "MEALLOW,MEALLOW Status" "0,1"
|
|
bitfld.long 0x0 9. "RNDF32,Round 32-bit Floating-Point Mode" "0,1"
|
|
bitfld.long 0x0 6. "TF,Test Flag" "0,1"
|
|
bitfld.long 0x0 3. "ZF,Zero Float Flag" "0,1"
|
|
bitfld.long 0x0 2. "NF,Negative Float Flag" "0,1"
|
|
bitfld.long 0x0 1. "LUF,Latched Underflow Flag" "0,1"
|
|
bitfld.long 0x0 0. "LVF,Latched Overflow Flag" "0,1"
|
|
line.long 0x2 "_MR0,CLA Floating-Point Result Register 0"
|
|
hexmask.long 0x2 0.--31. 1. "i32,CLA Result Register 0"
|
|
line.long 0x6 "_MR1,CLA Floating-Point Result Register 1"
|
|
hexmask.long 0x6 0.--31. 1. "i32,CLA Result Register 1"
|
|
line.long 0xA "_MR2,CLA Floating-Point Result Register 2"
|
|
hexmask.long 0xA 0.--31. 1. "i32,CLA Result Register 2"
|
|
line.long 0xE "_MR3,CLA Floating-Point Result Register 3"
|
|
hexmask.long 0xE 0.--31. 1. "i32,CLA Result Register 3"
|
|
group.word 0x42++0x1
|
|
line.word 0x0 "_MPSACTL,CLA PSA Control Register"
|
|
bitfld.word 0x0 6.--7. "MPSA2CFG,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x0 5. "MPSA2CLEAR,PSA2 Clear" "0,1"
|
|
bitfld.word 0x0 4. "MPSA1CLEAR,PSA1 clear" "0,1"
|
|
bitfld.word 0x0 3. "MDWDBCYC,DWDB logging into PSA2 is on every cycle." "0,1"
|
|
bitfld.word 0x0 2. "MDWDBSTART,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x0 1. "MPABCYC,PAB logging into PSA1 is on every cycle or when PAB changes." "0,1"
|
|
bitfld.word 0x0 0. "MPABSTART,Start logging PAB onto PSA1" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "_MPSA1,CLA PSA1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "i32,PSA1"
|
|
line.long 0x2 "_MPSA2,CLA PSA2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "i32,PSA2"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "CPU1_CLA1"
|
|
base d:0x1400
|
|
group.word 0x0++0xF
|
|
line.word 0x0 "MVECT1,Task 1 vector"
|
|
line.word 0x1 "MVECT2,Task 2 vector"
|
|
line.word 0x2 "MVECT3,Task 3 vector"
|
|
line.word 0x3 "MVECT4,Task 4 vector"
|
|
line.word 0x4 "MVECT5,Task 5 vector"
|
|
line.word 0x5 "MVECT6,Task 6 vector"
|
|
line.word 0x6 "MVECT7,Task 7 vector"
|
|
line.word 0x7 "MVECT8,Task 8 vector"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "MCTL,CLA control"
|
|
bitfld.word 0x0 2. "IACKE,IACK enable" "0,1"
|
|
bitfld.word 0x0 1. "SOFTRESET,Soft reset" "0,1"
|
|
bitfld.word 0x0 0. "HARDRESET,Hard reset" "0,1"
|
|
line.word 0x1 "MMEMCFG,CLA memory configuration"
|
|
bitfld.word 0x1 8.--10. "RAMnCPUE,Data RAM CPU Access Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x1 4.--6. "RAMnE,Data RAM Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x1 0. "PROGE,Program memory enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "MPISRCSEL1,CLA interrupt source select 1"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PERINT8SEL,Task 8 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PERINT7SEL,Task 7 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "PERINT6SEL,Task 6 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PERINT5SEL,Task 5 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "PERINT4SEL,Task 4 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PERINT3SEL,Task 3 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PERINT2SEL,Task 2 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PERINT1SEL,Task 1 Peripheral Interrupt Input Select"
|
|
line.long 0x2 "MPISRCSEL2,CLA interrupt source select 2"
|
|
hexmask.long.byte 0x2 28.--31. 1. "PERINT16SEL,Task 16 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "PERINT15SEL,Task 15 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "PERINT14SEL,Task 14 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "PERINT13SEL,Task 13 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "PERINT12SEL,Task 12 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "PERINT11SEL,Task 11 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "PERINT10SEL,Task 10 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "PERINT9SEL,Task 9 Peripheral Interrupt Input Select"
|
|
rgroup.word 0x1B++0x1
|
|
line.word 0x0 "MVECTBGRNDACTIVE,Active register for MVECTBGRND"
|
|
hexmask.word 0x0 0.--15. 1. "i16,Active register for the Background Task Vector"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x0 7. "TASK8,Configure Software Interrupt or End of Task 8 interrupt" "0,1"
|
|
bitfld.word 0x0 6. "TASK7,Configure Software Interrupt or End of Task 7 interrupt" "0,1"
|
|
bitfld.word 0x0 5. "TASK6,Configure Software Interrupt or End of Task 6 interrupt" "0,1"
|
|
bitfld.word 0x0 4. "TASK5,Configure Software Interrupt or End of Task 5 interrupt" "0,1"
|
|
bitfld.word 0x0 3. "TASK4,Configure Software Interrupt or End of Task 4 interrupt" "0,1"
|
|
bitfld.word 0x0 2. "TASK3,Configure Software Interrupt or End of Task 3 interrupt" "0,1"
|
|
bitfld.word 0x0 1. "TASK2,Configure Software Interrupt or End of Task 2 interrupt" "0,1"
|
|
bitfld.word 0x0 0. "TASK1,Configure Software Interrupt or End of Task 1 interrupt" "0,1"
|
|
rgroup.word 0x1D++0x1
|
|
line.word 0x0 "MSTSBGRND,Status register for the background task"
|
|
bitfld.word 0x0 2. "BGOVF,Background task hardware trigger overflow" "0,1"
|
|
bitfld.word 0x0 1. "BGINTM,Indicates whether background task can be interrupted" "0,1"
|
|
bitfld.word 0x0 0. "RUN,Background task run status bit" "0,1"
|
|
group.word 0x1E++0x3
|
|
line.word 0x0 "MCTLBGRND,Control register for the background task"
|
|
bitfld.word 0x0 15. "BGEN,Enable Background task" "0,1"
|
|
bitfld.word 0x0 1. "TRIGEN,Background task hardware trigger enable" "0,1"
|
|
bitfld.word 0x0 0. "BGSTART,Background task start bit" "0,1"
|
|
line.word 0x1 "MVECTBGRND,Vector for the background task"
|
|
hexmask.word 0x1 0.--15. 1. "i16,Background task vector"
|
|
rgroup.word 0x20++0x3
|
|
line.word 0x0 "MIFR,CLA interrupt flag"
|
|
bitfld.word 0x0 7. "INT8,Interrupt 8 flag bit" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Interrupt 7 flag bit" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Interrupt 6 flag bit" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Interrupt 5 flag bit" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Interrupt 4 flag bit" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Interrupt 3 flag bit" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Interrupt 2 flag bit" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Interrupt 1 flag bit" "0,1"
|
|
line.word 0x1 "MIOVF,CLA interrupt overflow flag"
|
|
bitfld.word 0x1 7. "INT8,Interrupt 8 overflow bit" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Interrupt 7 overflow bit" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Interrupt 6 overflow bit" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Interrupt 5 overflow bit" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Interrupt 4 overflow bit" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Interrupt 3 overflow bit" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Interrupt 2 overflow bit" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Interrupt 1 overflow bit" "0,1"
|
|
group.word 0x22++0xF
|
|
line.word 0x0 "MIFRC,CLA interrupt force"
|
|
bitfld.word 0x0 7. "INT8,Interrupt 8 force bit" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Interrupt 7 force bit" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Interrupt 6 force bit" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Interrupt 5 force bit" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Interrupt 4 force bit" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Interrupt 3 force bit" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Interrupt 2 force bit" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Interrupt 1 force bit" "0,1"
|
|
line.word 0x1 "MICLR,CLA interrupt flag clear"
|
|
bitfld.word 0x1 7. "INT8,Interrupt 8 clear bit" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Interrupt 7 clear bit" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Interrupt 6 clear bit" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Interrupt 5 clear bit" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Interrupt 4 clear bit" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Interrupt 3 clear bit" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Interrupt 2 clear bit" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Interrupt 1 clear bit" "0,1"
|
|
line.word 0x2 "MICLROVF,CLA interrupt overflow flag clear"
|
|
bitfld.word 0x2 7. "INT8,Interrupt 8 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 6. "INT7,Interrupt 7 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 5. "INT6,Interrupt 6 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 4. "INT5,Interrupt 5 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 3. "INT4,Interrupt 4 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 2. "INT3,Interrupt 3 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 1. "INT2,Interrupt 2 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 0. "INT1,Interrupt 1 overflow clear bit" "0,1"
|
|
line.word 0x3 "MIER,CLA interrupt enable"
|
|
bitfld.word 0x3 7. "INT8,Interrupt 8 enable bit" "0,1"
|
|
bitfld.word 0x3 6. "INT7,Interrupt 7 enable bit" "0,1"
|
|
bitfld.word 0x3 5. "INT6,Interrupt 6 enable bit" "0,1"
|
|
bitfld.word 0x3 4. "INT5,Interrupt 5 enable bit" "0,1"
|
|
bitfld.word 0x3 3. "INT4,Interrupt 4 enable bit" "0,1"
|
|
bitfld.word 0x3 2. "INT3,Interrupt 3 enable bit" "0,1"
|
|
bitfld.word 0x3 1. "INT2,Interrupt 2 enable bit" "0,1"
|
|
bitfld.word 0x3 0. "INT1,Interrupt 1 enable bit" "0,1"
|
|
line.word 0x4 "MIRUN,CLA interrupt run status"
|
|
bitfld.word 0x4 7. "INT8,Interrupt 8 run status" "0,1"
|
|
bitfld.word 0x4 6. "INT7,Interrupt 7 run status" "0,1"
|
|
bitfld.word 0x4 5. "INT6,Interrupt 6 run status" "0,1"
|
|
bitfld.word 0x4 4. "INT5,Interrupt 5 run status" "0,1"
|
|
bitfld.word 0x4 3. "INT4,Interrupt 4 run status" "0,1"
|
|
bitfld.word 0x4 2. "INT3,Interrupt 3 run status" "0,1"
|
|
bitfld.word 0x4 1. "INT2,Interrupt 2 run status" "0,1"
|
|
bitfld.word 0x4 0. "INT1,Interrupt 1 run status" "0,1"
|
|
line.word 0x6 "MPC,CLA program counter"
|
|
line.word 0x8 "MAR0,CLA auxiliary register 0"
|
|
line.word 0x9 "MAR1,CLA auxiliary register 1"
|
|
rgroup.long 0x2E++0x3
|
|
line.long 0x0 "MSTF,CLA floating-point status register"
|
|
hexmask.long.word 0x0 12.--27. 1. "RPC,Return PC"
|
|
bitfld.long 0x0 11. "MEALLOW,Protected write" "0,1"
|
|
bitfld.long 0x0 9. "RND32,Rounding mode" "0,1"
|
|
bitfld.long 0x0 6. "TF,Test flag" "0,1"
|
|
bitfld.long 0x0 3. "ZF,Zero flag" "0,1"
|
|
bitfld.long 0x0 2. "NF,Negative flag" "0,1"
|
|
bitfld.long 0x0 1. "LUF,Underflow flag" "0,1"
|
|
bitfld.long 0x0 0. "LVF,Overflow flag" "0,1"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "MR0,CLA result register 0"
|
|
line.long 0x4 "MR1,CLA result register 1"
|
|
line.long 0x8 "MR2,CLA result register 2"
|
|
line.long 0xC "MR3,CLA result register 3"
|
|
group.word 0x40++0x5
|
|
line.word 0x0 "MDEBUGCTL,CLA Debug Control Register"
|
|
rbitfld.word 0x0 2. "DEBUGSTOP,Debug stop bit" "0,1"
|
|
bitfld.word 0x0 1. "SSE,Single Step Enable bit" "0,1"
|
|
bitfld.word 0x0 0. "ONESHOT,One Shot Mode bit" "0,1"
|
|
line.word 0x1 "MDEBUGSS,CLA Debug Step Register"
|
|
bitfld.word 0x1 1. "RUN,Run bit" "0,1"
|
|
bitfld.word 0x1 0. "SS,Single Step Command bit" "0,1"
|
|
line.word 0x2 "MPSACTL,PSA Control Register"
|
|
bitfld.word 0x2 6.--7. "MPSA2CFG,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x2 5. "MPSA2CLEAR,PSA2 Clear" "0,1"
|
|
bitfld.word 0x2 4. "MPSA1CLEAR,PSA1 Clear" "0,1"
|
|
bitfld.word 0x2 3. "MDWDBCYC,DWDB logging into PSA2 is on every cycle" "0,1"
|
|
bitfld.word 0x2 2. "MDWDBSTART,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x2 1. "MPABCYC,PAB logging into PSA1 is on every cycle or when PAB changes" "0,1"
|
|
bitfld.word 0x2 0. "MPABSTART,Start logging PAB onto PSA1" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "MPSA1,CLA PSA1 Register"
|
|
line.long 0x2 "MPSA2,CLA PSA2 Register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "ClaOnlyRegs"
|
|
base d:0xC00
|
|
rgroup.word 0x80++0x1
|
|
line.word 0x0 "_MVECTBGRNDACTIVE,Active register for MVECTBGRND."
|
|
hexmask.word 0x0 0.--15. 1. "i16,Active register for the Background Task Vector"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "_MPSACTL,CLA PSA Control Register"
|
|
bitfld.word 0x0 6.--7. "MPSA2CFG,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x0 5. "MPSA2CLEAR,PSA2 Clear" "0,1"
|
|
bitfld.word 0x0 4. "MPSA1CLEAR,PSA1 clear" "0,1"
|
|
bitfld.word 0x0 3. "MDWDBCYC,DWDB logging into PSA2 is on every cycle." "0,1"
|
|
bitfld.word 0x0 2. "MDWDBSTART,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x0 1. "MPABCYC,PAB logging into PSA1 is on every cycle or when PAB changes." "0,1"
|
|
bitfld.word 0x0 0. "MPABSTART,Start logging PAB onto PSA1" "0,1"
|
|
group.long 0xC2++0x7
|
|
line.long 0x0 "_MPSA1,CLA PSA1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "i32,PSA1"
|
|
line.long 0x2 "_MPSA2,CLA PSA2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "i32,PSA2"
|
|
group.word 0xE0++0x3
|
|
line.word 0x0 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x0 7. "TASK8,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 6. "TASK7,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 5. "TASK6,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 4. "TASK5,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 3. "TASK4,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 2. "TASK3,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 1. "TASK2,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 0. "TASK1,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
line.word 0x2 "SOFTINTFRC,CLA Software Interrupt Force Register"
|
|
bitfld.word 0x2 7. "TASK8,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 6. "TASK7,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 5. "TASK6,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 4. "TASK5,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 3. "TASK4,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 2. "TASK3,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 1. "TASK2,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x2 0. "TASK1,Force CLA software interrupt for the corresponding task." "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838?D"))
|
|
tree "CPU2_CLA1"
|
|
base d:0x1400
|
|
group.word 0x0++0xF
|
|
line.word 0x0 "MVECT1,Task 1 vector"
|
|
line.word 0x1 "MVECT2,Task 2 vector"
|
|
line.word 0x2 "MVECT3,Task 3 vector"
|
|
line.word 0x3 "MVECT4,Task 4 vector"
|
|
line.word 0x4 "MVECT5,Task 5 vector"
|
|
line.word 0x5 "MVECT6,Task 6 vector"
|
|
line.word 0x6 "MVECT7,Task 7 vector"
|
|
line.word 0x7 "MVECT8,Task 8 vector"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "MCTL,CLA control"
|
|
bitfld.word 0x0 2. "IACKE,IACK enable" "0,1"
|
|
bitfld.word 0x0 1. "SOFTRESET,Soft reset" "0,1"
|
|
bitfld.word 0x0 0. "HARDRESET,Hard reset" "0,1"
|
|
line.word 0x1 "MMEMCFG,CLA memory configuration"
|
|
bitfld.word 0x1 8.--10. "RAMnCPUE,Data RAM CPU Access Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x1 4.--6. "RAMnE,Data RAM Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x1 0. "PROGE,Program memory enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "MPISRCSEL1,CLA interrupt source select 1"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PERINT8SEL,Task 8 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PERINT7SEL,Task 7 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "PERINT6SEL,Task 6 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PERINT5SEL,Task 5 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "PERINT4SEL,Task 4 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PERINT3SEL,Task 3 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PERINT2SEL,Task 2 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PERINT1SEL,Task 1 Peripheral Interrupt Input Select"
|
|
line.long 0x2 "MPISRCSEL2,CLA interrupt source select 2"
|
|
hexmask.long.byte 0x2 28.--31. 1. "PERINT16SEL,Task 16 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "PERINT15SEL,Task 15 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "PERINT14SEL,Task 14 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "PERINT13SEL,Task 13 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "PERINT12SEL,Task 12 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "PERINT11SEL,Task 11 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "PERINT10SEL,Task 10 Peripheral Interrupt Input Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "PERINT9SEL,Task 9 Peripheral Interrupt Input Select"
|
|
rgroup.word 0x1B++0x1
|
|
line.word 0x0 "MVECTBGRNDACTIVE,Active register for MVECTBGRND"
|
|
hexmask.word 0x0 0.--15. 1. "i16,Active register for the Background Task Vector"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x0 7. "TASK8,Configure Software Interrupt or End of Task 8 interrupt" "0,1"
|
|
bitfld.word 0x0 6. "TASK7,Configure Software Interrupt or End of Task 7 interrupt" "0,1"
|
|
bitfld.word 0x0 5. "TASK6,Configure Software Interrupt or End of Task 6 interrupt" "0,1"
|
|
bitfld.word 0x0 4. "TASK5,Configure Software Interrupt or End of Task 5 interrupt" "0,1"
|
|
bitfld.word 0x0 3. "TASK4,Configure Software Interrupt or End of Task 4 interrupt" "0,1"
|
|
bitfld.word 0x0 2. "TASK3,Configure Software Interrupt or End of Task 3 interrupt" "0,1"
|
|
bitfld.word 0x0 1. "TASK2,Configure Software Interrupt or End of Task 2 interrupt" "0,1"
|
|
bitfld.word 0x0 0. "TASK1,Configure Software Interrupt or End of Task 1 interrupt" "0,1"
|
|
rgroup.word 0x1D++0x1
|
|
line.word 0x0 "MSTSBGRND,Status register for the background task"
|
|
bitfld.word 0x0 2. "BGOVF,Background task hardware trigger overflow" "0,1"
|
|
bitfld.word 0x0 1. "BGINTM,Indicates whether background task can be interrupted" "0,1"
|
|
bitfld.word 0x0 0. "RUN,Background task run status bit" "0,1"
|
|
group.word 0x1E++0x3
|
|
line.word 0x0 "MCTLBGRND,Control register for the background task"
|
|
bitfld.word 0x0 15. "BGEN,Enable Background task" "0,1"
|
|
bitfld.word 0x0 1. "TRIGEN,Background task hardware trigger enable" "0,1"
|
|
bitfld.word 0x0 0. "BGSTART,Background task start bit" "0,1"
|
|
line.word 0x1 "MVECTBGRND,Vector for the background task"
|
|
hexmask.word 0x1 0.--15. 1. "i16,Background task vector"
|
|
rgroup.word 0x20++0x3
|
|
line.word 0x0 "MIFR,CLA interrupt flag"
|
|
bitfld.word 0x0 7. "INT8,Interrupt 8 flag bit" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Interrupt 7 flag bit" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Interrupt 6 flag bit" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Interrupt 5 flag bit" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Interrupt 4 flag bit" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Interrupt 3 flag bit" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Interrupt 2 flag bit" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Interrupt 1 flag bit" "0,1"
|
|
line.word 0x1 "MIOVF,CLA interrupt overflow flag"
|
|
bitfld.word 0x1 7. "INT8,Interrupt 8 overflow bit" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Interrupt 7 overflow bit" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Interrupt 6 overflow bit" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Interrupt 5 overflow bit" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Interrupt 4 overflow bit" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Interrupt 3 overflow bit" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Interrupt 2 overflow bit" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Interrupt 1 overflow bit" "0,1"
|
|
group.word 0x22++0xF
|
|
line.word 0x0 "MIFRC,CLA interrupt force"
|
|
bitfld.word 0x0 7. "INT8,Interrupt 8 force bit" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Interrupt 7 force bit" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Interrupt 6 force bit" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Interrupt 5 force bit" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Interrupt 4 force bit" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Interrupt 3 force bit" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Interrupt 2 force bit" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Interrupt 1 force bit" "0,1"
|
|
line.word 0x1 "MICLR,CLA interrupt flag clear"
|
|
bitfld.word 0x1 7. "INT8,Interrupt 8 clear bit" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Interrupt 7 clear bit" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Interrupt 6 clear bit" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Interrupt 5 clear bit" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Interrupt 4 clear bit" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Interrupt 3 clear bit" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Interrupt 2 clear bit" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Interrupt 1 clear bit" "0,1"
|
|
line.word 0x2 "MICLROVF,CLA interrupt overflow flag clear"
|
|
bitfld.word 0x2 7. "INT8,Interrupt 8 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 6. "INT7,Interrupt 7 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 5. "INT6,Interrupt 6 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 4. "INT5,Interrupt 5 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 3. "INT4,Interrupt 4 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 2. "INT3,Interrupt 3 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 1. "INT2,Interrupt 2 overflow clear bit" "0,1"
|
|
bitfld.word 0x2 0. "INT1,Interrupt 1 overflow clear bit" "0,1"
|
|
line.word 0x3 "MIER,CLA interrupt enable"
|
|
bitfld.word 0x3 7. "INT8,Interrupt 8 enable bit" "0,1"
|
|
bitfld.word 0x3 6. "INT7,Interrupt 7 enable bit" "0,1"
|
|
bitfld.word 0x3 5. "INT6,Interrupt 6 enable bit" "0,1"
|
|
bitfld.word 0x3 4. "INT5,Interrupt 5 enable bit" "0,1"
|
|
bitfld.word 0x3 3. "INT4,Interrupt 4 enable bit" "0,1"
|
|
bitfld.word 0x3 2. "INT3,Interrupt 3 enable bit" "0,1"
|
|
bitfld.word 0x3 1. "INT2,Interrupt 2 enable bit" "0,1"
|
|
bitfld.word 0x3 0. "INT1,Interrupt 1 enable bit" "0,1"
|
|
line.word 0x4 "MIRUN,CLA interrupt run status"
|
|
bitfld.word 0x4 7. "INT8,Interrupt 8 run status" "0,1"
|
|
bitfld.word 0x4 6. "INT7,Interrupt 7 run status" "0,1"
|
|
bitfld.word 0x4 5. "INT6,Interrupt 6 run status" "0,1"
|
|
bitfld.word 0x4 4. "INT5,Interrupt 5 run status" "0,1"
|
|
bitfld.word 0x4 3. "INT4,Interrupt 4 run status" "0,1"
|
|
bitfld.word 0x4 2. "INT3,Interrupt 3 run status" "0,1"
|
|
bitfld.word 0x4 1. "INT2,Interrupt 2 run status" "0,1"
|
|
bitfld.word 0x4 0. "INT1,Interrupt 1 run status" "0,1"
|
|
line.word 0x6 "MPC,CLA program counter"
|
|
line.word 0x8 "MAR0,CLA auxiliary register 0"
|
|
line.word 0x9 "MAR1,CLA auxiliary register 1"
|
|
rgroup.long 0x2E++0x3
|
|
line.long 0x0 "MSTF,CLA floating-point status register"
|
|
hexmask.long.word 0x0 12.--27. 1. "RPC,Return PC"
|
|
bitfld.long 0x0 11. "MEALLOW,Protected write" "0,1"
|
|
bitfld.long 0x0 9. "RND32,Rounding mode" "0,1"
|
|
bitfld.long 0x0 6. "TF,Test flag" "0,1"
|
|
bitfld.long 0x0 3. "ZF,Zero flag" "0,1"
|
|
bitfld.long 0x0 2. "NF,Negative flag" "0,1"
|
|
bitfld.long 0x0 1. "LUF,Underflow flag" "0,1"
|
|
bitfld.long 0x0 0. "LVF,Overflow flag" "0,1"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "MR0,CLA result register 0"
|
|
line.long 0x4 "MR1,CLA result register 1"
|
|
line.long 0x8 "MR2,CLA result register 2"
|
|
line.long 0xC "MR3,CLA result register 3"
|
|
group.word 0x40++0x5
|
|
line.word 0x0 "MDEBUGCTL,CLA Debug Control Register"
|
|
rbitfld.word 0x0 2. "DEBUGSTOP,Debug stop bit" "0,1"
|
|
bitfld.word 0x0 1. "SSE,Single Step Enable bit" "0,1"
|
|
bitfld.word 0x0 0. "ONESHOT,One Shot Mode bit" "0,1"
|
|
line.word 0x1 "MDEBUGSS,CLA Debug Step Register"
|
|
bitfld.word 0x1 1. "RUN,Run bit" "0,1"
|
|
bitfld.word 0x1 0. "SS,Single Step Command bit" "0,1"
|
|
line.word 0x2 "MPSACTL,PSA Control Register"
|
|
bitfld.word 0x2 6.--7. "MPSA2CFG,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x2 5. "MPSA2CLEAR,PSA2 Clear" "0,1"
|
|
bitfld.word 0x2 4. "MPSA1CLEAR,PSA1 Clear" "0,1"
|
|
bitfld.word 0x2 3. "MDWDBCYC,DWDB logging into PSA2 is on every cycle" "0,1"
|
|
bitfld.word 0x2 2. "MDWDBSTART,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x2 1. "MPABCYC,PAB logging into PSA1 is on every cycle or when PAB changes" "0,1"
|
|
bitfld.word 0x2 0. "MPABSTART,Start logging PAB onto PSA1" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "MPSA1,CLA PSA1 Register"
|
|
line.long 0x2 "MPSA2,CLA PSA2 Register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838?D"))
|
|
tree "CPU2Cla1Regs"
|
|
base d:0x1400
|
|
group.word 0x0++0xF
|
|
line.word 0x0 "MVECT1,Task Interrupt Vector"
|
|
hexmask.word 0x0 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x1 "MVECT2,Task Interrupt Vector"
|
|
hexmask.word 0x1 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x2 "MVECT3,Task Interrupt Vector"
|
|
hexmask.word 0x2 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x3 "MVECT4,Task Interrupt Vector"
|
|
hexmask.word 0x3 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x4 "MVECT5,Task Interrupt Vector"
|
|
hexmask.word 0x4 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x5 "MVECT6,Task Interrupt Vector"
|
|
hexmask.word 0x5 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x6 "MVECT7,Task Interrupt Vector"
|
|
hexmask.word 0x6 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
line.word 0x7 "MVECT8,Task Interrupt Vector"
|
|
hexmask.word 0x7 0.--15. 1. "MVECT,Offset of the first instruction"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "MCTL,Control Register"
|
|
bitfld.word 0x0 2. "IACKE,IACK enable" "0,1"
|
|
bitfld.word 0x0 1. "SOFTRESET,Soft Reset" "0,1"
|
|
bitfld.word 0x0 0. "HARDRESET,Hard Reset" "0,1"
|
|
rgroup.word 0x1B++0x1
|
|
line.word 0x0 "_MVECTBGRNDACTIVE,Active register for MVECTBGRND."
|
|
hexmask.word 0x0 0.--15. 1. "i16,Active register for the Background Task Vector"
|
|
group.word 0x1C++0x7
|
|
line.word 0x0 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x0 7. "TASK8,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 6. "TASK7,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 5. "TASK6,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 4. "TASK5,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 3. "TASK4,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 2. "TASK3,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 1. "TASK2,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x0 0. "TASK1,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
line.word 0x1 "_MSTSBGRND,Status register for the back ground task."
|
|
bitfld.word 0x1 2. "BGOVF,background task harware trigger overflow." "0,1"
|
|
rbitfld.word 0x1 1. "_BGINTM,Indicates whether background task can be interrupted." "0,1"
|
|
rbitfld.word 0x1 0. "RUN,Background task run status bit." "0,1"
|
|
line.word 0x2 "_MCTLBGRND,Control register for the back ground task."
|
|
bitfld.word 0x2 15. "BGEN,Enable background task" "0,1"
|
|
bitfld.word 0x2 1. "TRIGEN,Background task hardware trigger enable" "0,1"
|
|
bitfld.word 0x2 0. "BGSTART,Background task start bit" "0,1"
|
|
line.word 0x3 "_MVECTBGRND,Vector for the back ground task."
|
|
hexmask.word 0x3 0.--15. 1. "i16,Background task vector"
|
|
rgroup.word 0x20++0x3
|
|
line.word 0x0 "MIFR,Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "INT8,Task 8 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Task 7 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Task 6 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Task 5 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Task 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Task 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Task 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Task 1 Interrupt Flag" "0,1"
|
|
line.word 0x1 "MIOVF,Interrupt Overflow Flag Register"
|
|
bitfld.word 0x1 7. "INT8,Task 8 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Task 7 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Task 6 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Task 5 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Task 4 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Task 3 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Task 2 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Task 1 Interrupt Overflow Flag" "0,1"
|
|
group.word 0x22++0x7
|
|
line.word 0x0 "MIFRC,Interrupt Force Register"
|
|
bitfld.word 0x0 7. "INT8,Task 8 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Task 7 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Task 6 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Task 5 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Task 4 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Task 3 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Task 2 Interrupt Force" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Task 1 Interrupt Force" "0,1"
|
|
line.word 0x1 "MICLR,Interrupt Flag Clear Register"
|
|
bitfld.word 0x1 7. "INT8,Task 8 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 6. "INT7,Task 7 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 5. "INT6,Task 6 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 4. "INT5,Task 5 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 3. "INT4,Task 4 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 2. "INT3,Task 3 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 1. "INT2,Task 2 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 0. "INT1,Task 1 Interrupt Flag Clear" "0,1"
|
|
line.word 0x2 "MICLROVF,Interrupt Overflow Flag Clear Register"
|
|
bitfld.word 0x2 7. "INT8,Task 8 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 6. "INT7,Task 7 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 5. "INT6,Task 6 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 4. "INT5,Task 5 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 3. "INT4,Task 4 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 2. "INT3,Task 3 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 1. "INT2,Task 2 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x2 0. "INT1,Task 1 Interrupt Overflow Flag Clear" "0,1"
|
|
line.word 0x3 "MIER,Interrupt Enable Register"
|
|
bitfld.word 0x3 7. "INT8,Task 8 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 6. "INT7,Task 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 5. "INT6,Task 6 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 4. "INT5,Task 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 3. "INT4,Task 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 2. "INT3,Task 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 1. "INT2,Task 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x3 0. "INT1,Task 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x26++0x7
|
|
line.word 0x0 "MIRUN,Interrupt Run Status Register"
|
|
bitfld.word 0x0 7. "INT8,Task 8 Run Status" "0,1"
|
|
bitfld.word 0x0 6. "INT7,Task 7 Run Status" "0,1"
|
|
bitfld.word 0x0 5. "INT6,Task 6 Run Status" "0,1"
|
|
bitfld.word 0x0 4. "INT5,Task 5 Run Status" "0,1"
|
|
bitfld.word 0x0 3. "INT4,Task 4 Run Status" "0,1"
|
|
bitfld.word 0x0 2. "INT3,Task 3 Run Status" "0,1"
|
|
bitfld.word 0x0 1. "INT2,Task 2 Run Status" "0,1"
|
|
bitfld.word 0x0 0. "INT1,Task 1 Run Status" "0,1"
|
|
line.word 0x2 "_MPC,CLA Program Counter"
|
|
hexmask.word 0x2 0.--15. 1. "_MPC,Points to the instruction"
|
|
line.word 0x4 "_MAR0,CLA Auxiliary Register 0"
|
|
hexmask.word 0x4 0.--15. 1. "_MAR0,CLA Auxillary Register 0"
|
|
line.word 0x5 "_MAR1,CLA Auxiliary Register 1"
|
|
hexmask.word 0x5 0.--15. 1. "_MAR1,CLA Auxillary Register 1"
|
|
rgroup.long 0x2E++0x13
|
|
line.long 0x0 "_MSTF,CLA Floating-Point Status Register"
|
|
hexmask.long.word 0x0 12.--27. 1. "_RPC,Return PC"
|
|
bitfld.long 0x0 11. "MEALLOW,MEALLOW Status" "0,1"
|
|
bitfld.long 0x0 9. "RNDF32,Round 32-bit Floating-Point Mode" "0,1"
|
|
bitfld.long 0x0 6. "TF,Test Flag" "0,1"
|
|
bitfld.long 0x0 3. "ZF,Zero Float Flag" "0,1"
|
|
bitfld.long 0x0 2. "NF,Negative Float Flag" "0,1"
|
|
bitfld.long 0x0 1. "LUF,Latched Underflow Flag" "0,1"
|
|
bitfld.long 0x0 0. "LVF,Latched Overflow Flag" "0,1"
|
|
line.long 0x2 "_MR0,CLA Floating-Point Result Register 0"
|
|
hexmask.long 0x2 0.--31. 1. "i32,CLA Result Register 0"
|
|
line.long 0x6 "_MR1,CLA Floating-Point Result Register 1"
|
|
hexmask.long 0x6 0.--31. 1. "i32,CLA Result Register 1"
|
|
line.long 0xA "_MR2,CLA Floating-Point Result Register 2"
|
|
hexmask.long 0xA 0.--31. 1. "i32,CLA Result Register 2"
|
|
line.long 0xE "_MR3,CLA Floating-Point Result Register 3"
|
|
hexmask.long 0xE 0.--31. 1. "i32,CLA Result Register 3"
|
|
group.word 0x42++0x1
|
|
line.word 0x0 "_MPSACTL,CLA PSA Control Register"
|
|
bitfld.word 0x0 6.--7. "MPSA2CFG,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x0 5. "MPSA2CLEAR,PSA2 Clear" "0,1"
|
|
bitfld.word 0x0 4. "MPSA1CLEAR,PSA1 clear" "0,1"
|
|
bitfld.word 0x0 3. "MDWDBCYC,DWDB logging into PSA2 is on every cycle." "0,1"
|
|
bitfld.word 0x0 2. "MDWDBSTART,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x0 1. "MPABCYC,PAB logging into PSA1 is on every cycle or when PAB changes." "0,1"
|
|
bitfld.word 0x0 0. "MPABSTART,Start logging PAB onto PSA1" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "_MPSA1,CLA PSA1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "i32,PSA1"
|
|
line.long 0x2 "_MPSA2,CLA PSA2 Register"
|
|
hexmask.long 0x2 0.--31. 1. "i32,PSA2"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F28388?")||cpuis("F28388?-CM")||cpuis("F28386?*")||cpuis("F28386?-CM"))
|
|
tree "CLB (Configurable Logic Block)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb1LogicCfgRegs"
|
|
base d:0x3000
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb1LogicCtrlRegs"
|
|
base d:0x3100
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb1DataExchRegs"
|
|
base d:0x3180
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb2LogicCfgRegs"
|
|
base d:0x3200
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb2LogicCtrlRegs"
|
|
base d:0x3300
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb2DataExchRegs"
|
|
base d:0x3380
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb3LogicCfgRegs"
|
|
base d:0x3400
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb3LogicCtrlRegs"
|
|
base d:0x3500
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb3DataExchRegs"
|
|
base d:0x3580
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb4LogicCfgRegs"
|
|
base d:0x3600
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb4LogicCtrlRegs"
|
|
base d:0x3700
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb4DataExchRegs"
|
|
base d:0x3780
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb5LogicCfgRegs"
|
|
base d:0x3800
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb5LogicCtrlRegs"
|
|
base d:0x3900
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb5DataExchRegs"
|
|
base d:0x3980
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb6LogicCfgRegs"
|
|
base d:0x3A00
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb6LogicCtrlRegs"
|
|
base d:0x3B00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb6DataExchRegs"
|
|
base d:0x3B80
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb7LogicCfgRegs"
|
|
base d:0x3C00
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb7LogicCtrlRegs"
|
|
base d:0x3D00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb7DataExchRegs"
|
|
base d:0x3D80
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb8LogicCfgRegs"
|
|
base d:0x3E00
|
|
group.long 0x2++0x97
|
|
line.long 0x0 "CLB_COUNT_RESET,Counter Block RESET"
|
|
hexmask.long.byte 0x0 10.--14. 1. "SEL_2,Count Reset Select 2"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SEL_1,Count Reset Select 1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL_0,Count Reset Select 0"
|
|
line.long 0x2 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
hexmask.long.byte 0x2 10.--14. 1. "SEL_2,Counter mode 1 select 2"
|
|
hexmask.long.byte 0x2 5.--9. 1. "SEL_1,Counter mode 1 select 1"
|
|
hexmask.long.byte 0x2 0.--4. 1. "SEL_0,Counter mode 1 select 0"
|
|
line.long 0x4 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
hexmask.long.byte 0x4 10.--14. 1. "SEL_2,Counter mode 0 select 2"
|
|
hexmask.long.byte 0x4 5.--9. 1. "SEL_1,Counter mode 0 select 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SEL_0,Counter mode 0 select 0"
|
|
line.long 0x6 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
hexmask.long.byte 0x6 10.--14. 1. "SEL_2,Counter event select 2"
|
|
hexmask.long.byte 0x6 5.--9. 1. "SEL_1,Counter event select 1"
|
|
hexmask.long.byte 0x6 0.--4. 1. "SEL_0,Counter event select 0"
|
|
line.long 0x8 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
hexmask.long.byte 0x8 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0xA "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
hexmask.long.byte 0xA 10.--14. 1. "SEL_2,FSM EXT_IN0 select input for unit 2"
|
|
hexmask.long.byte 0xA 5.--9. 1. "SEL_1,FSM EXT_IN0 select input for unit 1"
|
|
hexmask.long.byte 0xA 0.--4. 1. "SEL_0,FSM EXT_IN0 select input for unit 0"
|
|
line.long 0xC "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
hexmask.long.byte 0xC 10.--14. 1. "SEL_2,FSM EXT_IN1 select input for unit 2"
|
|
hexmask.long.byte 0xC 5.--9. 1. "SEL_1,FSM EXT_IN1 select input for unit 1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SEL_0,FSM EXT_IN1 select input for unit 0"
|
|
line.long 0xE "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
hexmask.long.byte 0xE 10.--14. 1. "SEL_2,FSM extra ext input select 2"
|
|
hexmask.long.byte 0xE 5.--9. 1. "SEL_1,FSM extra ext input select 1"
|
|
hexmask.long.byte 0xE 0.--4. 1. "SEL_0,FSM extra ext input select 0"
|
|
line.long 0x10 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
hexmask.long.byte 0x10 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x10 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x10 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x12 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
hexmask.long.byte 0x12 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x12 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x12 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x14 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
|
|
hexmask.long.byte 0x14 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x14 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x14 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x16 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
|
|
hexmask.long.byte 0x16 10.--14. 1. "SEL_2,Select inputs for unit 2"
|
|
hexmask.long.byte 0x16 5.--9. 1. "SEL_1,Select inputs for unit 1"
|
|
hexmask.long.byte 0x16 0.--4. 1. "SEL_0,Select inputs for unit 0"
|
|
line.long 0x1A "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
|
|
hexmask.long.word 0x1A 16.--31. 1. "FN1,FSM LUT output function for unit 1"
|
|
hexmask.long.word 0x1A 0.--15. 1. "FN0,FSM LUT output function for unit 0"
|
|
line.long 0x1C "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FN1,FSM LUT output function for unit 2"
|
|
line.long 0x1E "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
|
|
hexmask.long.word 0x1E 16.--31. 1. "FN1,LUT4 output function for unit 1"
|
|
hexmask.long.word 0x1E 0.--15. 1. "FN0,LUT4 output function for unit 0"
|
|
line.long 0x20 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
|
|
hexmask.long.word 0x20 0.--15. 1. "FN1,LUT4 output function for unit 2"
|
|
line.long 0x22 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
|
|
hexmask.long.word 0x22 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x22 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x24 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
|
|
hexmask.long.word 0x24 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x24 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x26 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
|
|
hexmask.long.word 0x26 16.--31. 1. "S1,FSM next state function for S1"
|
|
hexmask.long.word 0x26 0.--15. 1. "S0,FSM next state function for S0"
|
|
line.long 0x28 "CLB_MISC_CONTROL,Static controls for Ctr.FSM"
|
|
bitfld.long 0x28 26. "COUNT2_LFSR_EN,Enable LFSR mode for Counter 2" "0,1"
|
|
bitfld.long 0x28 25. "COUNT1_LFSR_EN,Enable LFSR mode for Counter 1" "0,1"
|
|
bitfld.long 0x28 24. "COUNT0_LFSR_EN,Enable LFSR mode for Counter 0" "0,1"
|
|
bitfld.long 0x28 23. "COUNT2_MATCH2_TAP_EN,Match2 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 22. "COUNT1_MATCH2_TAP_EN,Match2 Tap Enable for Counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 21. "COUNT0_MATCH2_TAP_EN,Match2 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 20. "COUNT2_MATCH1_TAP_EN,Match1 Tap Enable for Counter 2" "0,1"
|
|
bitfld.long 0x28 19. "COUNT1_MATCH1_TAP_EN,Match1 Tap Enable for Counter 1" "0,1"
|
|
bitfld.long 0x28 18. "COUNT0_MATCH1_TAP_EN,Match1 Tap Enable for Counter 0" "0,1"
|
|
bitfld.long 0x28 17. "FSM_EXTRA_SEL1_2,FSM extra_sel1 for 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "FSM_EXTRA_SEL0_2,FSM extra_sel0 for 2" "0,1"
|
|
bitfld.long 0x28 15. "FSM_EXTRA_SEL1_1,FSM extra_sel1 for 1" "0,1"
|
|
bitfld.long 0x28 14. "FSM_EXTRA_SEL0_1,FSM extra_sel0 for 1" "0,1"
|
|
bitfld.long 0x28 13. "FSM_EXTRA_SEL1_0,FSM extra_sel1 for 0" "0,1"
|
|
bitfld.long 0x28 12. "FSM_EXTRA_SEL0_0,FSM extra_sel0 for 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "COUNT_SERIALIZER_2,Serializer enable 2" "0,1"
|
|
bitfld.long 0x28 10. "COUNT_SERIALIZER_1,Serializer enable 1" "0,1"
|
|
bitfld.long 0x28 9. "COUNT_SERIALIZER_0,Serializer enable 0" "0,1"
|
|
bitfld.long 0x28 8. "COUNT_EVENT_CTRL_2,Event control for counter 2" "0,1"
|
|
bitfld.long 0x28 7. "COUNT_DIR_2,Direction for counter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "COUNT_ADD_SHIFT_2,Add/Shift for counter 2" "0,1"
|
|
bitfld.long 0x28 5. "COUNT_EVENT_CTRL_1,Event control for counter 1" "0,1"
|
|
bitfld.long 0x28 4. "COUNT_DIR_1,Direction for counter 1" "0,1"
|
|
bitfld.long 0x28 3. "COUNT_ADD_SHIFT_1,Add/Shift for counter 1" "0,1"
|
|
bitfld.long 0x28 2. "COUNT_EVENT_CTRL_0,Event control for counter 0" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COUNT_DIR_0,Direction for counter 0" "0,1"
|
|
bitfld.long 0x28 0. "COUNT_ADD_SHIFT_0,Add/Shift for counter 0" "0,1"
|
|
line.long 0x2A "CLB_OUTPUT_LUT_0,Inp Sel. LUT fns for Out0"
|
|
hexmask.long.byte 0x2A 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2A 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2A 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2A 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2C "CLB_OUTPUT_LUT_1,Inp Sel. LUT fns for Out1"
|
|
hexmask.long.byte 0x2C 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2C 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2C 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x2E "CLB_OUTPUT_LUT_2,Inp Sel. LUT fns for Out2"
|
|
hexmask.long.byte 0x2E 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x2E 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x2E 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x2E 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x30 "CLB_OUTPUT_LUT_3,Inp Sel. LUT fns for Out3"
|
|
hexmask.long.byte 0x30 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x30 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x30 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x30 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x32 "CLB_OUTPUT_LUT_4,Inp Sel. LUT fns for Out4"
|
|
hexmask.long.byte 0x32 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x32 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x32 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x32 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x34 "CLB_OUTPUT_LUT_5,Inp Sel. LUT fns for Out5"
|
|
hexmask.long.byte 0x34 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x34 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x34 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x34 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x36 "CLB_OUTPUT_LUT_6,Inp Sel. LUT fns for Out6"
|
|
hexmask.long.byte 0x36 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x36 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x36 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x36 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x38 "CLB_OUTPUT_LUT_7,Inp Sel. LUT fns for Out7"
|
|
hexmask.long.byte 0x38 15.--22. 1. "FN,Output function for output LUT"
|
|
hexmask.long.byte 0x38 10.--14. 1. "IN2,Select value for IN2 of output LUT"
|
|
hexmask.long.byte 0x38 5.--9. 1. "IN1,Select value for IN1 of output LUT"
|
|
hexmask.long.byte 0x38 0.--4. 1. "IN0,Select value for IN0 of output LUT"
|
|
line.long 0x3A "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
|
|
bitfld.long 0x3A 23. "ALT_EVENT3_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 22. "ALT_EVENT2_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 21. "ALT_EVENT1_SEL,Event Select 3" "0,1"
|
|
bitfld.long 0x3A 20. "ALT_EVENT0_SEL,Event Select 3" "0,1"
|
|
hexmask.long.byte 0x3A 15.--19. 1. "EVENT3_SEL,Event Select 3"
|
|
newline
|
|
hexmask.long.byte 0x3A 10.--14. 1. "EVENT2_SEL,Event Select 2"
|
|
hexmask.long.byte 0x3A 5.--9. 1. "EVENT1_SEL,Event Select 1"
|
|
hexmask.long.byte 0x3A 0.--4. 1. "EVENT0_SEL,Event Select 0"
|
|
line.long 0x3C "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
|
|
hexmask.long.byte 0x3C 26.--30. 1. "COUNT2_MATCH2,Match2 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 21.--25. 1. "COUNT1_MATCH2,Match2 tap select for Counter 1"
|
|
hexmask.long.byte 0x3C 16.--20. 1. "COUNT0_MATCH2,Match2 tap select for Counter 0"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "COUNT2_MATCH1,Match1 tap select for Counter 2"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "COUNT1_MATCH1,Match1 tap select for Counter 1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--4. 1. "COUNT0_MATCH1,Match1 tap select for Counter 0"
|
|
line.long 0x3E "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
|
|
bitfld.long 0x3E 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x3E 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x3E 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x3E 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x3E 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x3E 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3E 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x3E 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x40 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
|
|
bitfld.long 0x40 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x40 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x40 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x40 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x40 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x40 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x40 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x40 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x42 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x42 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x42 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x42 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x42 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x42 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x42 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x42 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x42 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x44 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x44 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x44 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x44 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x44 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x44 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x44 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x44 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x46 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x46 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x46 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x46 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x46 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x46 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x46 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x46 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x46 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x48 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x48 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x48 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x48 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x48 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x48 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x48 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x48 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4A "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x4A 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4A 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4A 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4A 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4A 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4A 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4A 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4A 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
line.long 0x4C "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x4C 14. "ASYNC_COND_EN,Enable for conditioning" "0,1"
|
|
bitfld.long 0x4C 13. "SEL_RAW_IN,Select Input for" "0,1"
|
|
bitfld.long 0x4C 12. "HW_RLS_CTRL_SEL,Select HW for release control" "0,1"
|
|
bitfld.long 0x4C 11. "HW_GATING_CTRL_SEL,Select HW for gating control" "0,1"
|
|
bitfld.long 0x4C 8.--10. "SEL_RELEASE_CTRL,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4C 5.--7. "SEL_GATING_CTRL,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4C 3.--4. "LEVEL_3_SEL,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 1.--2. "LEVEL_2_SEL,Level 2 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x4C 0. "LEVEL_1_SEL,Level 1 Mux Select" "0,1"
|
|
group.word 0x50++0x3
|
|
line.word 0x0 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x0 1. "BLKEN,Block Register write" "0,1"
|
|
bitfld.word 0x0 0. "SPIEN,Enable CLB SPI Buffer feature" "0,1"
|
|
line.word 0x1 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
hexmask.word.byte 0x1 8.--12. 1. "SHIFT,Shift value select"
|
|
hexmask.word.byte 0x1 0.--4. 1. "STRB,Select value for strobe"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb8LogicCtrlRegs"
|
|
base d:0x3F00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x0 4. "PIPELINE_EN,Enable input pipelining" "0,1"
|
|
bitfld.word 0x0 3. "NMI_EN,NMI output enable" "0,1"
|
|
bitfld.word 0x0 2. "STOP,Debug stop control" "0,1"
|
|
bitfld.word 0x0 1. "GLOBAL_EN,Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "LOAD_EN,Load Enable" "0,1"
|
|
group.long 0x2++0x2F
|
|
line.long 0x0 "CLB_LOAD_ADDR,Indirect address"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADDR,Indirect Address"
|
|
line.long 0x2 "CLB_LOAD_DATA,Data for indirect loads"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,Data for indirect write"
|
|
line.long 0x4 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x4 31. "PIPE7,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x4 30. "PIPE6,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x4 29. "PIPE5,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x4 28. "PIPE4,Enable pipeline 4" "0,1"
|
|
bitfld.long 0x4 27. "PIPE3,Enable pipeline 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PIPE2,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x4 25. "PIPE1,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x4 24. "PIPE0,Enable pipeline 0" "0,1"
|
|
bitfld.long 0x4 23. "SYNC7,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x4 22. "SYNC6,Synchronizer control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SYNC5,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x4 20. "SYNC4,Synchronizer control 4" "0,1"
|
|
bitfld.long 0x4 19. "SYNC3,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x4 18. "SYNC2,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x4 17. "SYNC1,Synchronizer control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "SYNC0,Synchronizer control 0" "0,1"
|
|
bitfld.long 0x4 14.--15. "FIN7,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "FIN6,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "FIN5,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "FIN4,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FIN3,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "FIN2,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "FIN1,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "FIN0,Input filter control 0" "0,1,2,3"
|
|
line.long 0x6 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x6 31. "SW_GATING_CTRL_7,Software gating control 7" "0,1"
|
|
bitfld.long 0x6 30. "SW_GATING_CTRL_6,Software gating control 6" "0,1"
|
|
bitfld.long 0x6 29. "SW_GATING_CTRL_5,Software gating control 5" "0,1"
|
|
bitfld.long 0x6 28. "SW_GATING_CTRL_4,Software gating control 4" "0,1"
|
|
bitfld.long 0x6 27. "SW_GATING_CTRL_3,Software gating control 3" "0,1"
|
|
newline
|
|
bitfld.long 0x6 26. "SW_GATING_CTRL_2,Software gating control 2" "0,1"
|
|
bitfld.long 0x6 25. "SW_GATING_CTRL_1,Software gating control 1" "0,1"
|
|
bitfld.long 0x6 24. "SW_GATING_CTRL_0,Software gating control 0" "0,1"
|
|
bitfld.long 0x6 23. "SW_RLS_CTRL_7,Software release control 7" "0,1"
|
|
bitfld.long 0x6 22. "SW_RLS_CTRL_6,Software release control 6" "0,1"
|
|
newline
|
|
bitfld.long 0x6 21. "SW_RLS_CTRL_5,Software release control 5" "0,1"
|
|
bitfld.long 0x6 20. "SW_RLS_CTRL_4,Software release control 4" "0,1"
|
|
bitfld.long 0x6 19. "SW_RLS_CTRL_3,Software release control 3" "0,1"
|
|
bitfld.long 0x6 18. "SW_RLS_CTRL_2,Software release control 2" "0,1"
|
|
bitfld.long 0x6 17. "SW_RLS_CTRL_1,Software release control 1" "0,1"
|
|
newline
|
|
bitfld.long 0x6 16. "SW_RLS_CTRL_0,Software release control 0" "0,1"
|
|
bitfld.long 0x6 7. "SEL_GP_IN_7,Select GP register 7" "0,1"
|
|
bitfld.long 0x6 6. "SEL_GP_IN_6,Select GP register 6" "0,1"
|
|
bitfld.long 0x6 5. "SEL_GP_IN_5,Select GP register 5" "0,1"
|
|
bitfld.long 0x6 4. "SEL_GP_IN_4,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SEL_GP_IN_3,Select GP register 3" "0,1"
|
|
bitfld.long 0x6 2. "SEL_GP_IN_2,Select GP register 2" "0,1"
|
|
bitfld.long 0x6 1. "SEL_GP_IN_1,Select GP register 1" "0,1"
|
|
bitfld.long 0x6 0. "SEL_GP_IN_0,Select GP register 0" "0,1"
|
|
line.long 0x8 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x8 31. "MISC_INPUT_SEL_3,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 30. "MISC_INPUT_SEL_2,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 29. "MISC_INPUT_SEL_1,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x8 28. "MISC_INPUT_SEL_0,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0x8 15.--19. 1. "LCL_MUX_SEL_IN_3,Local Mux select 3"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "LCL_MUX_SEL_IN_2,Local Mux select 2"
|
|
hexmask.long.byte 0x8 5.--9. 1. "LCL_MUX_SEL_IN_1,Local Mux select 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LCL_MUX_SEL_IN_0,Local Mux select 0"
|
|
line.long 0xA "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0xA 31. "MISC_INPUT_SEL_7,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 30. "MISC_INPUT_SEL_6,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 29. "MISC_INPUT_SEL_5,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0xA 28. "MISC_INPUT_SEL_4,Select MISC_INPUT" "0,1"
|
|
hexmask.long.byte 0xA 15.--19. 1. "LCL_MUX_SEL_IN_7,Local Mux select 7"
|
|
newline
|
|
hexmask.long.byte 0xA 10.--14. 1. "LCL_MUX_SEL_IN_6,Local Mux select 6"
|
|
hexmask.long.byte 0xA 5.--9. 1. "LCL_MUX_SEL_IN_5,Local Mux select 5"
|
|
hexmask.long.byte 0xA 0.--4. 1. "LCL_MUX_SEL_IN_4,Local Mux select 4"
|
|
line.long 0xC "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long.byte 0xC 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PULL,Data pointer for pull"
|
|
line.long 0xE "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long.byte 0xE 0.--7. 1. "REG,General Purpose bit register"
|
|
line.long 0x10 "CLB_OUT_EN,CELL output enable register"
|
|
hexmask.long 0x10 0.--31. 1. "OUTEN,CLB output enable"
|
|
line.long 0x12 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x12 21.--27. 1. "GLBL_MUX_SEL_IN_3,Global Mux select 3"
|
|
hexmask.long.byte 0x12 14.--20. 1. "GLBL_MUX_SEL_IN_2,Global Mux select 2"
|
|
hexmask.long.byte 0x12 7.--13. 1. "GLBL_MUX_SEL_IN_1,Global Mux select 1"
|
|
hexmask.long.byte 0x12 0.--6. 1. "GLBL_MUX_SEL_IN_0,Global Mux select 0"
|
|
line.long 0x14 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
hexmask.long.byte 0x14 21.--27. 1. "GLBL_MUX_SEL_IN_7,Global Mux select 7"
|
|
hexmask.long.byte 0x14 14.--20. 1. "GLBL_MUX_SEL_IN_6,Global Mux select 6"
|
|
hexmask.long.byte 0x14 7.--13. 1. "GLBL_MUX_SEL_IN_5,Global Mux select 5"
|
|
hexmask.long.byte 0x14 0.--6. 1. "GLBL_MUX_SEL_IN_4,Global Mux select 4"
|
|
line.long 0x16 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long.word 0x16 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
hexmask.long.byte 0x16 2.--5. 1. "TAP,TAP Select value"
|
|
bitfld.long 0x16 1. "STRB,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x16 0. "CLKEN,Enable the prescale clock generator" "0,1"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
hexmask.word.byte 0x0 0.--5. 1. "TAG,Interrupt tag"
|
|
group.long 0x22++0x3
|
|
line.long 0x0 "CLB_LOCK,Lock control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x0 0. "LOCK,LOCK enable" "0,1"
|
|
group.word 0x24++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
hexmask.word.byte 0x0 0.--4. 1. "READ_PTR,HLC instruction read pointer"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x0 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long 0x2E++0x3
|
|
line.long 0x0 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long.byte 0x0 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long 0x30++0x1F
|
|
line.long 0x0 "CLB_DBG_R0,R0 of High level Controller"
|
|
hexmask.long 0x0 0.--31. 1. "DBG,CLB_DBG_R0"
|
|
line.long 0x2 "CLB_DBG_R1,R1 of High level Controller"
|
|
hexmask.long 0x2 0.--31. 1. "DBG,CLB_DBG_R1"
|
|
line.long 0x4 "CLB_DBG_R2,R2 of High level Controller"
|
|
hexmask.long 0x4 0.--31. 1. "DBG,CLB_DBG_R2"
|
|
line.long 0x6 "CLB_DBG_R3,R3 of High level Controller"
|
|
hexmask.long 0x6 0.--31. 1. "DBG,CLB_DBG_R3"
|
|
line.long 0x8 "CLB_DBG_C0,Count of Unit 0"
|
|
hexmask.long 0x8 0.--31. 1. "DBG,CLB_DBG_C0"
|
|
line.long 0xA "CLB_DBG_C1,Count of Unit 1"
|
|
hexmask.long 0xA 0.--31. 1. "DBG,CLB_DBG_C1"
|
|
line.long 0xC "CLB_DBG_C2,Count of Unit 2"
|
|
hexmask.long 0xC 0.--31. 1. "DBG,CLB_DBG_C2"
|
|
line.long 0xE "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0xE 31. "OUT7,CELL Output 7" "0,1"
|
|
bitfld.long 0xE 30. "OUT6,CELL Output 6" "0,1"
|
|
bitfld.long 0xE 29. "OUT5,CELL Output 5" "0,1"
|
|
bitfld.long 0xE 28. "OUT4,CELL Output 4" "0,1"
|
|
bitfld.long 0xE 27. "OUT3,CELL Output 3" "0,1"
|
|
newline
|
|
bitfld.long 0xE 26. "OUT2,CELL Output 2" "0,1"
|
|
bitfld.long 0xE 25. "OUT1,CELL Output 1" "0,1"
|
|
bitfld.long 0xE 24. "OUT0,CELL Output 0" "0,1"
|
|
bitfld.long 0xE 23. "LUT42_OUT,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0xE 22. "FSM2_LUTOUT,FSM_LUT_OUT UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "FSM2_S1,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 20. "FSM2_S0,FSM_S0 UNIT 2" "0,1"
|
|
bitfld.long 0xE 19. "COUNT2_MATCH1,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0xE 18. "COUNT2_ZERO,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0xE 17. "COUNT2_MATCH2,COUNT_MATCH2 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0xE 15. "LUT41_OUT,LUT4_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 14. "FSM1_LUTOUT,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0xE 13. "FSM1_S1,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0xE 12. "FSM1_S0,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0xE 11. "COUNT1_MATCH1,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0xE 10. "COUNT1_ZERO,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0xE 9. "COUNT1_MATCH2,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0xE 7. "LUT40_OUT,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 6. "FSM0_LUTOUT,FSM_LUT_OUT UNIT 0" "0,1"
|
|
bitfld.long 0xE 5. "FSM0_S1,FSM_S1 UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0xE 4. "FSM0_S0,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0xE 3. "COUNT0_MATCH1,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0xE 2. "COUNT0_ZERO,COUNT_ZERO UNIT 0" "0,1"
|
|
bitfld.long 0xE 1. "COUNT0_MATCH2,COUNT_MATCH2 UNIT 0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "Clb8DataExchRegs"
|
|
base d:0x3F80
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PUSH,FIFO TO System From CLB"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
hexmask.long 0x0 0.--31. 1. "PULL,FIFO From system TO CLB"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "CM (Connectivity Manager)"
|
|
base d:0x0
|
|
tree "CMSYSCTL"
|
|
base d:0x400FC000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CMPCLKCR0,CM Peripheral clock gating register 0."
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x0 12. "USB,USB Clock gating Bit" "0,1"
|
|
bitfld.long 0x0 8. "I2C0,I2C0 Clock gating Bit" "0,1"
|
|
bitfld.long 0x0 4. "SSI0,SSI0 Clock gating Bit" "0,1"
|
|
bitfld.long 0x0 0. "UART0,UART0 Clock gating Bit" "0,1"
|
|
line.long 0x4 "CMPCLKCR1,CM Peripheral clock gating register 1."
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x4 8. "MCAN_A,MCAN_A Clock gating Bit" "0,1"
|
|
bitfld.long 0x4 5. "CAN_B,CAN_B Clock gating Bit" "0,1"
|
|
bitfld.long 0x4 4. "CAN_A,CAN_A Clock gating Bit" "0,1"
|
|
bitfld.long 0x4 2. "ETHERCAT,ETHERCAT Clock gating Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ETHERNET,ETHERNET Clock gating Bit" "0,1"
|
|
line.long 0x8 "CMPCLKCR2,CM Peripheral clock gating register 2."
|
|
hexmask.long.word 0x8 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x8 8. "GCRC,GCRC Clock gating Bit" "0,1"
|
|
bitfld.long 0x8 6. "AESIP,AESIP Clock gating Bit" "0,1"
|
|
bitfld.long 0x8 4. "UDMA,UDMA Clock gating Bit" "0,1"
|
|
bitfld.long 0x8 2. "CPUTIMER2,CPUTIMER2 Clock gating Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CPUTIMER1,CPUTIMER1 Clock gating Bit" "0,1"
|
|
bitfld.long 0x8 0. "CPUTIMER0,CPUTIMER0 Clock gating Bit" "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "CMSOFTPRESET0,CM Software Peripheral Reset register 0"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x0 12. "USB,USB Soft reset bit" "0,1"
|
|
bitfld.long 0x0 8. "I2C0,I2C0 Soft reset bit" "0,1"
|
|
bitfld.long 0x0 4. "SSI0,SSI0 Soft reset bit" "0,1"
|
|
bitfld.long 0x0 0. "UART0,UART0 Soft reset bit" "0,1"
|
|
line.long 0x4 "CMSOFTPRESET1,CM Software Peripheral Reset register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x4 8. "MCAN_A,MCAN_A Soft reset bit" "0,1"
|
|
bitfld.long 0x4 5. "CAN_B,CAN_B Soft reset bit" "0,1"
|
|
bitfld.long 0x4 4. "CAN_A,CAN_A Soft reset bit" "0,1"
|
|
bitfld.long 0x4 2. "ETHERCAT,ETHERCAT Soft reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ETHERNET,ETHERNET Soft reset bit" "0,1"
|
|
line.long 0x8 "CMSOFTPRESET2,CM Software Peripheral Reset register 2"
|
|
hexmask.long.word 0x8 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x8 8. "GCRC,GCRC Soft reset bit" "0,1"
|
|
bitfld.long 0x8 6. "AESIP,AESIP Soft reset bit" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CMCLKSTOPREQ0,Peripheral Clock Stop Request Register 0"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key field"
|
|
line.long 0x4 "CMCLKSTOPREQ1,Peripheral Clock Stop Request Register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x4 8. "MCAN_A,MCAN_A Clock Stop Request Bit" "0,1"
|
|
line.long 0x8 "CMCLKSTOPREQ2,Peripheral Clock Stop Request Register 2"
|
|
hexmask.long.word 0x8 16.--31. 1. "KEY,Key field"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CMCLKSTOPACK0,Peripheral Clock Stop Ackonwledge Register 0"
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "CMCLKSTOPACK1,Peripheral Clock Stop Ackonwledge Register 1"
|
|
bitfld.long 0x0 8. "MCAN_A,MCAN_A Clock Stop Ack Bit" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "CMCLKSTOPACK2,Peripheral Clock Stop Ackonwledge Register 2"
|
|
rgroup.long 0xE0++0x3
|
|
line.long 0x0 "MCANWAKESTATUS,MCAN Wake Status Register"
|
|
bitfld.long 0x0 0. "WAKE,MCAN Wake Status" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "MCANWAKESTATUSCLR,MCAN Wake Status Clear Register"
|
|
bitfld.long 0x0 0. "WAKE,Cear bit for MCANWAKESTATUS.WAKE bit" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CMECATCTL,CM etherCAT control register"
|
|
bitfld.long 0x0 0. "I2CLOOPBACK,Loopback I2C port of etherCAT IP to CM I2C." "0,1"
|
|
rgroup.long 0x1F4++0x3
|
|
line.long 0x0 "PALLOCATESTS,Status of PALLOCATE register."
|
|
bitfld.long 0x0 4. "MCAN_A,Status of PALLOCATE.MCAN_A bit" "0,1"
|
|
bitfld.long 0x0 3. "CAN_B,Status of PALLOCATE.CAN_B bit" "0,1"
|
|
bitfld.long 0x0 2. "CAN_A,Status of PALLOCATE.CAN_A bit" "0,1"
|
|
bitfld.long 0x0 1. "ETHERCAT,Status of PALLOCATE.ETHERCAT bit" "0,1"
|
|
bitfld.long 0x0 0. "USB,Status of PALLOCATE.USB bit" "0,1"
|
|
group.long 0x1F8++0x3
|
|
line.long 0x0 "CMRESCCLR,CM Reset Cause Status Clear Register"
|
|
bitfld.long 0x0 19. "CMEOLRESETn,CMEOLRESETn status flag clear" "0,1"
|
|
bitfld.long 0x0 18. "CMNMIWDRSTn,CMNMIWDRSTn status flag clear" "0,1"
|
|
bitfld.long 0x0 17. "CMSYSRESETREQ,CMSYSRESETREQ status flag clear" "0,1"
|
|
bitfld.long 0x0 16. "CMVECTRESETn,CMVECTRESETn status flag clear" "0,1"
|
|
bitfld.long 0x0 9. "CPU1_SIMRESET_XRSn,CPU1_SIMRESET_XRSn status flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CMRSTCTLRESETREQ,CMRSTCTLRESETREQ status flag clear" "0,1"
|
|
bitfld.long 0x0 7. "CPU1SIMRESET_CPURSn,CPU1SIMRESET_CPURSn status flag clear" "0,1"
|
|
bitfld.long 0x0 6. "ECAT_RESET_OUT,ECAT_RESET_OUT status flag clear" "0,1"
|
|
bitfld.long 0x0 5. "CPU1SCCRESETn,CPU1SCCRESETn status flag clear" "0,1"
|
|
bitfld.long 0x0 4. "CPU1SYSRSN,CPU1SYSRSN status flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU1NMIWDRSn,CPU1NMIWDRSn status flag clear" "0,1"
|
|
bitfld.long 0x0 2. "CPU1WDRSn,CPU1WDRSn status flag clear" "0,1"
|
|
bitfld.long 0x0 1. "XRSn,XRSn status flag clear" "0,1"
|
|
bitfld.long 0x0 0. "PORESETn,PORESETn status flag clear" "0,1"
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "CMRESC,CM Reset Cause Status Register"
|
|
bitfld.long 0x0 19. "CMEOLRESETn,CMEOLRESETn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 18. "CMNMIWDRSTn,CMNMIWDRSTn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 17. "CMSYSRESETREQ,CMSYSRESETREQ caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 16. "CMVECTRESETn,CMVECTRESETn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 9. "CPU1_SIMRESET_XRSn,CPU1_SIMRESET_XRSn caused the reset of CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CMRSTCTL_RESETREQ,CMRSTCTL_RESETREQ caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 7. "CPU1_SIMRESET_CPURSn,CPU1_SIMRESET_CPURSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 6. "ECAT_RESET_OUT,ECAT_RESET_OUT caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 5. "CPU1_SCCRESETn,CPU1_SCCRESETn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 4. "CPU1_SYSRSN,CPU1_SYSRSN caused the reset of CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU1_NMIWDRSn,CPU1_NMIWDRSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 2. "CPU1_WDRSn,CPU1_WDRSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 1. "XRSn,XRSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x0 0. "PORESETn,PORESETn caused the reset of CM" "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CMSYSCTLLOCK,Locks the configuration registers of CM System control"
|
|
bitfld.long 0x0 0. "LOCK,Locks the configuration registers of CM System Control" "0,1"
|
|
tree.end
|
|
tree "CSFR"
|
|
base d:0xE000E000
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x0 "MMSR,MemManage Fault Status Register"
|
|
bitfld.byte 0x0 7. "MMARVALID,MemManage Fault Address Register (MMFAR) valid flag" "0,1"
|
|
bitfld.byte 0x0 4. "MSTKERR,MemManage fault on stacking for exception entry" "0,1"
|
|
bitfld.byte 0x0 3. "MUNSTKERR,MemManage fault on unstacking for a return from exception" "0,1"
|
|
bitfld.byte 0x0 1. "DACCVIOL,Data access violation flag" "0,1"
|
|
bitfld.byte 0x0 0. "IACCVIOL,Instruction access violation flag" "0,1"
|
|
line.byte 0x1 "BFSR,BusFault Status Register"
|
|
bitfld.byte 0x1 7. "BFARVALID,BusFault Address Register (BFAR) valid flag" "0,1"
|
|
bitfld.byte 0x1 4. "STKERR,BusFault on stacking for exception entry" "0,1"
|
|
bitfld.byte 0x1 3. "UNSTKERR,BusFault on unstacking for a return from exception" "0,1"
|
|
bitfld.byte 0x1 2. "IMPRECISERR,Imprecise data bus error" "0,1"
|
|
bitfld.byte 0x1 1. "PRECISERR,Precise data bus error" "0,1"
|
|
bitfld.byte 0x1 0. "IBUSERR,Instruction bus error" "0,1"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x0 "UFSR,UsageFault Status Register"
|
|
bitfld.word 0x0 9. "DIVBYZERO,Divide by zero UsageFault" "0,1"
|
|
bitfld.word 0x0 8. "UNALIGNED,Unaligned access UsageFault" "0,1"
|
|
bitfld.word 0x0 3. "NOCP,No coprocessor UsageFault" "0,1"
|
|
bitfld.word 0x0 2. "INVPC,Invalid PC load UsageFault" "0,1"
|
|
bitfld.word 0x0 1. "INVSTATE,Invalid state UsageFault" "0,1"
|
|
bitfld.word 0x0 0. "UNDEFINSTR,Undefined instruction UsageFault" "0,1"
|
|
tree.end
|
|
tree "DIAGERRORLOG"
|
|
base d:0x400FE800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DIAGERRFLG,Error Flag Register"
|
|
bitfld.long 0x0 3. "CWRERROR,Diagnostics Correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 2. "CRDERROR,Diagnostics Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "UCWRERROR,Diagnostics Uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "UCRDERROR,Diagnostics Uncorrectable Read Error Flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DIAGERRCLR,Error Flag Clear Register"
|
|
bitfld.long 0x0 3. "CWRERROR,Clear diagnostics correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 2. "CRDERROR,Clear diagnostics correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "UCWRERROR,Clear diagnostics uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "UCRDERROR,Clear diagnostics uncorrectable Read Error Flag" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DIAGERRADDR,Read Error Address"
|
|
hexmask.long 0x0 0.--31. 1. "EADDR,Diagnostics Error address register"
|
|
tree.end
|
|
tree "ERRORLOG"
|
|
base d:0x400FE400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "UCERRFLG,Uncorrectable Error Flag Register"
|
|
bitfld.long 0x0 7. "EMACMEMRDERR,EMAC IP RAM Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 6. "EtherCATMEMRDERR,EtherCAT IP RAM Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 5. "uDMAWRERR,uDMA Uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 4. "uDMARDERR,uDMA Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 2. "EMACRDERR,EMAC Uncorrectable Read Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M4WRERR,M4 Uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "M4RDERR,M4 Uncorrectable Read Error Flag" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "UCERRSET,Uncorrectable Error Flag Set Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x0 7. "EMACMEMRDERR,EMAC IP RAM Uncorrectable Read Error Flag set" "0,1"
|
|
bitfld.long 0x0 6. "EtherCATMEMRDERR,EtherCAT IP RAM Uncorrectable Read Error Flag set" "0,1"
|
|
bitfld.long 0x0 5. "uDMAWRERR,uDMA Uncorrectable Write Error Flag Set" "0,1"
|
|
bitfld.long 0x0 4. "uDMARDERR,uDMA Uncorrectable Read Error Flag Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EMACRDERR,EMAC Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 1. "M4WRERR,M4 Uncorrectable Write Error Flag Set" "0,1"
|
|
bitfld.long 0x0 0. "M4RDERR,M4 Uncorrectable Read Error Flag Set" "0,1"
|
|
line.long 0x4 "UCERRCLR,Uncorrectable Error Flag Clear Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x4 7. "EMACMEMRDERR,EMAC IP RAM Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 6. "EtherCATMEMRDERR,EtherCAT IP RAM Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 5. "uDMAWRERR,uDMA Uncorrectable Write Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 4. "uDMARDERR,uDMA Uncorrectable Read Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EMACRDERR,EMAC Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 1. "M4WRERR,M4 Uncorrectable Write Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 0. "M4RDERR,M4 Uncorrectable Read Error Flag Clear" "0,1"
|
|
rgroup.long 0xC++0x13
|
|
line.long 0x0 "UCM4EADDR,Uncorrectable M4 Error Address"
|
|
hexmask.long 0x0 0.--31. 1. "UCM4EADDR,Uncorrectable M4 error address register."
|
|
line.long 0x4 "UCEMACEADDR,Uncorrectable EMAC Error Address"
|
|
hexmask.long 0x4 0.--31. 1. "UCEMACEADDR,Uncorrectable EMAC error address register."
|
|
line.long 0x8 "UCuDMAEADDR,Uncorrectable uDMA Error Address"
|
|
hexmask.long 0x8 0.--31. 1. "UCuDMAEADDR,Uncorrectable uDMA error address register."
|
|
line.long 0xC "UCEtherCATMEMREADDR,Uncorrectable EtherCAT IP RAM Read Error Address"
|
|
hexmask.long 0xC 0.--31. 1. "UCEtherCATMEMREADDR,Uncorrectable EtherCAT IP RAM read error address register."
|
|
line.long 0x10 "UCEMACMEMREADDR,Uncorrectable EMAC IP RAM Read Error Address"
|
|
hexmask.long 0x10 0.--31. 1. "UCEMACMEMREADDR,Uncorrectable EMAC IP RAM read error address register."
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "BUSFAULTFLG,BusFault Flag register"
|
|
bitfld.long 0x0 2. "EMACBUSFAULT,EMAC busfault Flag" "0,1"
|
|
bitfld.long 0x0 1. "UDMABUSFAULT,UDMA busfault Flag" "0,1"
|
|
bitfld.long 0x0 0. "M4BUSFAULT,M4 busfault Flag" "0,1"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "BUSFAULTCLR,BusFault Flag clear register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x0 2. "EMACBUSFAULT,EMAC busfault Flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "UDMABUSFAULT,UDMA busfault Flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "M4BUSFAULT,M4 busfault Flag Clear" "0,1"
|
|
rgroup.long 0x58++0xB
|
|
line.long 0x0 "M4BUSFAULTADDR,M4 busfault address"
|
|
hexmask.long 0x0 0.--31. 1. "M4BUSFAULTADDRESS,M4 busfault address"
|
|
line.long 0x4 "uDMABUSFAULTADDR,uDMA busfault address"
|
|
hexmask.long 0x4 0.--31. 1. "UDMABUSFAULTADDRESS,UDMA busfault address"
|
|
line.long 0x8 "EMACBUSFAULTADDR,EMAC busfault address"
|
|
hexmask.long 0x8 0.--31. 1. "EMACBUSFAULTADDRESS,EMAC busfault address"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "CERRFLG,Correctable Error Flag Register"
|
|
bitfld.long 0x0 5. "uDMAWRERR,uDMA Correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 4. "uDMARDERR,uDMA Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 2. "EMACRDERR,EMAC Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "M4WRERR,M4 Correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "M4RDERR,M4 Correctable Read Error Flag" "0,1"
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "CERRSET,Correctable Error Flag Set Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x0 5. "uDMAWRERR,uDMA Correctable Write Error Flag Set" "0,1"
|
|
bitfld.long 0x0 4. "uDMARDERR,uDMA Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 2. "EMACRDERR,EMAC Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 1. "M4WRERR,M4 Correctable Write Error Flag Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M4RDERR,M4 Correctable Read Error Flag Set" "0,1"
|
|
line.long 0x4 "CERRCLR,Correctable Error Flag Clear Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x4 5. "uDMAWRERR,uDMA Correctable Write Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 4. "uDMARDERR,uDMA Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 2. "EMACRDERR,EMAC Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x4 1. "M4WRERR,M4 Correctable Write Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "M4RDERR,M4 Correctable Read Error Flag Clear" "0,1"
|
|
rgroup.long 0x8C++0xB
|
|
line.long 0x0 "CM4EADDR,Correctable M4 Error Address"
|
|
hexmask.long 0x0 0.--31. 1. "CM4EADDR,Correctable M4 error address register."
|
|
line.long 0x4 "CEMACEADDR,Correctable EMAC Error Address"
|
|
hexmask.long 0x4 0.--31. 1. "CEMACEADDR,Correctable EMAC error address register."
|
|
line.long 0x8 "CuDMAEADDR,Correctable uDMA Error Address"
|
|
hexmask.long 0x8 0.--31. 1. "CuDMAEADDR,Correctable uDMA error address register."
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "CERRCNT,Correctable Error Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "CERRCNT,Correctable error count."
|
|
line.long 0x4 "CERRTHRES,Correctable Error Threshold Value Register"
|
|
hexmask.long 0x4 0.--31. 1. "CERRTHRES,Correctable error threshold."
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "CEINTFLG,Correctable Error Interrupt Flag Status Register"
|
|
bitfld.long 0x0 0. "CEINTFLAG,Total corrected error count exceeded threshold flag." "0,1"
|
|
group.long 0xCC++0xB
|
|
line.long 0x0 "CEINTSET,Correctable Error Interrupt Flag Set Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x0 0. "CEINTSET,Total corrected error count exceeded flag set." "0,1"
|
|
line.long 0x4 "CEINTCLR,Correctable Error Interrupt Flag Clear Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x4 0. "CEINTCLR,M4 Corrected Error Threshold Exceeded Error Clear." "0,1"
|
|
line.long 0x8 "CEINTEN,Correctable Error Interrupt Enable Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x8 0. "CEINTEN,M4 Correctable Error Interrupt Enable." "0,1"
|
|
tree.end
|
|
tree "MEMINITANDTEST"
|
|
base d:0x400FE000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CxLOCK,C RAM Config Lock Register"
|
|
bitfld.long 0x0 1. "LOCK_C1,C1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_C0,C0 RAM Lock bits" "0,1"
|
|
line.long 0x4 "CxTEST,C RAM TEST Register"
|
|
bitfld.long 0x4 2.--3. "TEST_C1,Selects the different modes for C1 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "TEST_C0,Selects the different modes for C0 RAM" "0,1,2,3"
|
|
line.long 0x8 "CxINIT,C RAM Init Register"
|
|
bitfld.long 0x8 1. "INIT_C1,RAM Initialization control for C1 RAM." "0,1"
|
|
bitfld.long 0x8 0. "INIT_C0,RAM Initialization control for C0 RAM." "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CxINITDONE,C RAM Initialization Status Register"
|
|
bitfld.long 0x0 1. "INITDONE_C1,RAM Initialization status for C1 RAM." "0,1"
|
|
bitfld.long 0x0 0. "INITDONE_C0,RAM Initialization status for C0 RAM." "0,1"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "CMMSGxLOCK,CM Messae RAM Config Lock Register"
|
|
bitfld.long 0x0 3. "LOCK_CMTOCPU2MSGRAM1,Message RAM CMTOCPU2MSGRAM1 Lock bits" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_CMTOCPU2MSGRAM0,Message RAM CMTOCPU2MSGRAM0 Lock bits" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_CMTOCPU1MSGRAM1,Message RAM CMTOCPU1MSGRAM1 Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_CMTOCPU1MSGRAM0,Message RAM CMTOCPU1MSGRAM0 Lock bits" "0,1"
|
|
line.long 0x4 "CMMSGxTEST,CM Messae RAM TEST Register"
|
|
bitfld.long 0x4 6.--7. "TEST_CMTOCPU2MSGRAM1,Selects the different modes for Message RAM CMTOCPU2MSGRAM1" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "TEST_CMTOCPU2MSGRAM0,Selects the different modes for Message RAM CMTOCPU2MSGRAM0" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "TEST_CMTOCPU1MSGRAM1,Selects the different modes for Message RAM CMTOCPU1MSGRAM1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "TEST_CMTOCPU1MSGRAM0,Selects the different modes for Message RAM CMTOCPU1MSGRAM0" "0,1,2,3"
|
|
line.long 0x8 "CMMSGxINIT,CM Messae RAM Init Register"
|
|
bitfld.long 0x8 3. "INIT_CMTOCPU2MSGRAM1,RAM Initialization control for Message RAM CMTOCPU2MSGRAM1" "0,1"
|
|
bitfld.long 0x8 2. "INIT_CMTOCPU2MSGRAM0,RAM Initialization control for Message RAM CMTOCPU2MSGRAM0" "0,1"
|
|
bitfld.long 0x8 1. "INIT_CMTOCPU1MSGRAM1,RAM Initialization control for Message RAM CMTOCPU1MSGRAM1" "0,1"
|
|
bitfld.long 0x8 0. "INIT_CMTOCPU1MSGRAM0,RAM Initialization control for Message RAM CMTOCPU1MSGRAM0" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "CMMSGxINITDONE,CM Messae RAM Initialization Status Register"
|
|
bitfld.long 0x0 3. "INITDONE_CMTOCPU2MSGRAM1,RAM Initialization status for Message RAM CMTOCPU2MSGRAM1" "0,1"
|
|
bitfld.long 0x0 2. "INITDONE_CMTOCPU2MSGRAM0,RAM Initialization status for Message RAM CMTOCPU2MSGRAM0" "0,1"
|
|
bitfld.long 0x0 1. "INITDONE_CMTOCPU1MSGRAM1,RAM Initialization status for Message RAM CMTOCPU1MSGRAM1" "0,1"
|
|
bitfld.long 0x0 0. "INITDONE_CMTOCPU1MSGRAM0,RAM Initialization status for Message RAM CMTOCPU1MSGRAM0" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "SxGROUP1_LOCK,Group1 S and E RAM Config Lock Register"
|
|
bitfld.long 0x0 4. "LOCK_E0,E0 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 3. "LOCK_S3,S3 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_S2,S2 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_S1,S1 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LOCK_S0,S0 RAM Lock bits" "0,1"
|
|
line.long 0x4 "SxGROUP1_TEST,Group1 S and E RAM TEST Register"
|
|
bitfld.long 0x4 8.--9. "TEST_E0,Selects the different modes for E0 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "TEST_S3,Selects the different modes for S3 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "TEST_S2,Selects the different modes for S2 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "TEST_S1,Selects the different modes for S1 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "TEST_S0,Selects the different modes for S0 RAM" "0,1,2,3"
|
|
line.long 0x8 "SxGROUP1_INIT,Group1 S and E RAM Init Register"
|
|
bitfld.long 0x8 4. "INIT_E0,RAM Initialization control for E0 RAM." "0,1"
|
|
bitfld.long 0x8 3. "INIT_S3,RAM Initialization control for S3 RAM." "0,1"
|
|
bitfld.long 0x8 2. "INIT_S2,RAM Initialization control for S2 RAM." "0,1"
|
|
bitfld.long 0x8 1. "INIT_S1,RAM Initialization control for S1 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "INIT_S0,RAM Initialization control for S0 RAM." "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "SxGROUP1_INITDONE,Group1 S and E RAM Initialization Status Register"
|
|
bitfld.long 0x0 4. "INITDONE_E0,RAM Initialization status for E0 RAM." "0,1"
|
|
bitfld.long 0x0 3. "INITDONE_S3,RAM Initialization status for S3 RAM." "0,1"
|
|
bitfld.long 0x0 2. "INITDONE_S2,RAM Initialization status for S2 RAM." "0,1"
|
|
bitfld.long 0x0 1. "INITDONE_S1,RAM Initialization status for S1 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "INITDONE_S0,RAM Initialization status for S0 RAM." "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "ROM_LOCK,ROM Config Lock Register"
|
|
bitfld.long 0x0 0. "LOCK_BOOTROM,BOOTROM Lock bits" "0,1"
|
|
line.long 0x4 "ROM_TEST,ROM TEST Register"
|
|
bitfld.long 0x4 0.--1. "TEST_BOOTROM,Selects the different modes for BOOTROM" "0,1,2,3"
|
|
line.long 0x8 "ROM_FORCE_ERROR,ROM Force Error register"
|
|
bitfld.long 0x8 0. "FORCE_BOOTROM_ERROR,Force Bootrom Parity Error" "0,1"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "PERI_MEM_TEST_LOCK,Peripheral Memory Test Lock Register"
|
|
bitfld.long 0x0 0. "LOCK_PERI_MEM_TEST_CONTROL,PERI_MEM_TEST_CONTROL Lock bit" "0,1"
|
|
line.long 0x4 "PERI_MEM_TEST_CONTROL,Peripheral Memory Test control Register"
|
|
bitfld.long 0x4 5. "EtherCAT_MEM_FORCE_ERROR,Force Parity Error on EtherCAT RAM" "0,1"
|
|
bitfld.long 0x4 4. "EtherCAT_TEST_ENABLE,EtherCAT Test mode enable" "0,1"
|
|
bitfld.long 0x4 1. "EMAC_MEM_FORCE_ERROR,Force Parity Error on EMAC RAM" "0,1"
|
|
bitfld.long 0x4 0. "EMAC_TEST_ENABLE,EMAC Test mode enable" "0,1"
|
|
tree.end
|
|
tree "MPU (Memory Protection Unit)"
|
|
base d:0xE000E000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MPU_CONTROL_REG,MPU control regster"
|
|
bitfld.long 0x0 0. "ENABLE,Global Enable register" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ACC_VIO_INTEN,Access violation interrupt enable"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x0 0. "INTEN,Interrupt enable register" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "ACC_VIO_FLAGS,Access violation flag register"
|
|
bitfld.long 0x0 1. "WR,Write access violation flag" "0,1"
|
|
bitfld.long 0x0 0. "RD,Read access violation flag" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ACC_VIO_FLAGS_SET,Acesss violation set register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x0 1. "WR,Write access violation flag set" "0,1"
|
|
bitfld.long 0x0 0. "RD,Read access violation flag set" "0,1"
|
|
line.long 0x4 "ACC_VIO_FLAGS_CLR,Access violation clear register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x4 1. "WR,Write access violation flag clear" "0,1"
|
|
bitfld.long 0x4 0. "RD,Read access violation flag clear" "0,1"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "ACC_VIO_ADDR_REG,Access violation address register"
|
|
hexmask.long 0x0 0.--31. 1. "VIOLATION_ADDRESS,Access violation address register"
|
|
group.long 0x40++0x3F
|
|
line.long 0x0 "REGION0_STARTADDRESSS,Region 0 start address register"
|
|
hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address of Region 0"
|
|
line.long 0x4 "REGION0_CONFIG,Region 0 configuration register"
|
|
bitfld.long 0x4 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x4 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x4 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x4 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x4 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x4 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x4 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x4 8.--12. 1. "SIZE,Size of the region 0"
|
|
bitfld.long 0x4 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x8 "REGION1_STARTADDRESSS,Region 1 start address register"
|
|
hexmask.long 0x8 0.--31. 1. "START_ADDR,Start address of Region 1"
|
|
line.long 0xC "REGION1_CONFIG,Region 1 configuration register"
|
|
bitfld.long 0xC 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0xC 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0xC 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0xC 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0xC 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0xC 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0xC 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0xC 8.--12. 1. "SIZE,Size of the region 1"
|
|
bitfld.long 0xC 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x10 "REGION2_STARTADDRESSS,Region 2 start address register"
|
|
hexmask.long 0x10 0.--31. 1. "START_ADDR,Start address of Region 2"
|
|
line.long 0x14 "REGION2_CONFIG,Region 2 configuration register"
|
|
bitfld.long 0x14 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x14 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x14 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x14 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x14 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x14 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x14 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x14 8.--12. 1. "SIZE,Size of the region 2"
|
|
bitfld.long 0x14 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x18 "REGION3_STARTADDRESSS,Region 3 start address register"
|
|
hexmask.long 0x18 0.--31. 1. "START_ADDR,Start address of Region 3"
|
|
line.long 0x1C "REGION3_CONFIG,Region 3 configuration register"
|
|
bitfld.long 0x1C 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x1C 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x1C 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x1C 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x1C 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x1C 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x1C 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x1C 8.--12. 1. "SIZE,Size of the region 3"
|
|
bitfld.long 0x1C 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x20 "REGION4_STARTADDRESSS,Region 4 start address register"
|
|
hexmask.long 0x20 0.--31. 1. "START_ADDR,Start address of Region 4"
|
|
line.long 0x24 "REGION4_CONFIG,Region 4 configuration register"
|
|
bitfld.long 0x24 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x24 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x24 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x24 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x24 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x24 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x24 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x24 8.--12. 1. "SIZE,Size of the region 4"
|
|
bitfld.long 0x24 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x24 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x28 "REGION5_STARTADDRESSS,Region 5 start address register"
|
|
hexmask.long 0x28 0.--31. 1. "START_ADDR,Start address of Region 4"
|
|
line.long 0x2C "REGION5_CONFIG,Region 5 configuration register"
|
|
bitfld.long 0x2C 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x2C 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x2C 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x2C 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x2C 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x2C 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x2C 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "SIZE,Size of the region 5"
|
|
bitfld.long 0x2C 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x30 "REGION6_STARTADDRESSS,Region 6 start address register"
|
|
hexmask.long 0x30 0.--31. 1. "START_ADDR,Start address of Region 6"
|
|
line.long 0x34 "REGION6_CONFIG,Region 6 configuration register"
|
|
bitfld.long 0x34 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x34 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x34 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x34 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x34 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x34 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x34 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x34 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x34 8.--12. 1. "SIZE,Size of the region 6"
|
|
bitfld.long 0x34 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x34 0. "ENABLE,Region Enable bit" "0,1"
|
|
line.long 0x38 "REGION7_STARTADDRESSS,Region 7 start address register"
|
|
hexmask.long 0x38 0.--31. 1. "START_ADDR,Start address of Region 7"
|
|
line.long 0x3C "REGION7_CONFIG,Region 7 configuration register"
|
|
bitfld.long 0x3C 23. "SUBREGION7_DISABLE,Sub region 7 disable bit" "0,1"
|
|
bitfld.long 0x3C 22. "SUBREGION6_DISABLE,Sub region 6 disable bit" "0,1"
|
|
bitfld.long 0x3C 21. "SUBREGION5_DISABLE,Sub region 5 disable bit" "0,1"
|
|
bitfld.long 0x3C 20. "SUBREGION4_DISABLE,Sub region 4 disable bit" "0,1"
|
|
bitfld.long 0x3C 19. "SUBREGION3_DISABLE,Sub region 3 disable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 18. "SUBREGION2_DISABLE,Sub region 2 disable bit" "0,1"
|
|
bitfld.long 0x3C 17. "SUBREGION1_DISABLE,Sub region 1 disable bit" "0,1"
|
|
bitfld.long 0x3C 16. "SUBREGION0_DISABLE,Sub region 0 disable bit" "0,1"
|
|
hexmask.long.byte 0x3C 8.--12. 1. "SIZE,Size of the region 7"
|
|
bitfld.long 0x3C 4.--5. "PROT_TYPE,Access permission configuration bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 0. "ENABLE,Region Enable bit" "0,1"
|
|
tree.end
|
|
tree "NMI (Non-Maskable Interrupt)"
|
|
base d:0x40081000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CMNMICFG,CM NMI Configuration Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key protection"
|
|
bitfld.long 0x0 0. "NMIE,Global NMI Enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CMNMIFLG,CM NMI Flag Register"
|
|
bitfld.long 0x0 6. "ECATNMI,NMI from EtherCAT reset out" "0,1"
|
|
bitfld.long 0x0 5. "WWDNMI,CM WWD NMI flag" "0,1"
|
|
bitfld.long 0x0 4. "MCANUNCERR,MCAN Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.long 0x0 3. "FLUNCERR,Flash Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.long 0x0 2. "MEMUNCERR,RAM ROM Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.long 0x0 1. "CLOCKFAIL,Clock Fail Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "NMIINT,NMI Interrupt Flag" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CMNMIFLGCLR,CMNMI Flag Clear Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key protection"
|
|
bitfld.long 0x0 6. "ECATNMI,ECATNMI Flag Clear" "0,1"
|
|
bitfld.long 0x0 5. "WWDNMI,WWDNMI Flag Clear" "0,1"
|
|
bitfld.long 0x0 4. "MCANUNCERR,MCANUNCERR Flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "FLUNCERR,FLUNCERR Flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "MEMUNCERR,MEMUNCERR Flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CLOCKFAIL,CLOCKFAIL Flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "NMIINT,NMIINT Flag Clear" "0,1"
|
|
line.long 0x4 "CMNMIFLGFRC,CMNMI Flag Force Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Key protection"
|
|
bitfld.long 0x4 6. "ECATNMI,ECATNMI Flag Force" "0,1"
|
|
bitfld.long 0x4 5. "WWDNMI,WWDNMI Flag Force" "0,1"
|
|
bitfld.long 0x4 4. "MCANUNCERR,MCANUNCERR Flag Force" "0,1"
|
|
bitfld.long 0x4 3. "FLUNCERR,FLUNCERR Flag Force" "0,1"
|
|
bitfld.long 0x4 2. "MEMUNCERR,MEMUNCERR Flag Force" "0,1"
|
|
bitfld.long 0x4 1. "CLOCKFAIL,CLOCKFAIL Flag Force" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CMNMIWDCNT,CMNMI Watchdog Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NMIWDCNT,NMI Watchdog Counter"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CMNMIWDPRD,CMNMI Watchdog Period Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key protection"
|
|
hexmask.long.word 0x0 0.--15. 1. "NMIWDPRD,NMI Watchdog Period"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "CMNMISHDWFLG,CMNMI Shadow Flag Register"
|
|
bitfld.long 0x0 6. "ECATNMI,ECATNMI Shadow flag" "0,1"
|
|
bitfld.long 0x0 5. "WWDNMI,WWDNMI Shadow flag" "0,1"
|
|
bitfld.long 0x0 4. "MCANUNCERR,MCANUNCERR Shadow flag" "0,1"
|
|
bitfld.long 0x0 3. "FLUNCERR,FLUNCERR Shadow flag" "0,1"
|
|
bitfld.long 0x0 2. "MEMUNCERR,MEMUNCERR Shadow flag" "0,1"
|
|
bitfld.long 0x0 1. "CLOCKFAIL,CLOCKFAIL Shadow flag" "0,1"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base d:0xE000E000
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "NVIC_ISER0,NVIC Interrupt Set Enable Register 0"
|
|
bitfld.long 0x0 31. "SETENA31,Set INTR31 Enable" "0,1"
|
|
bitfld.long 0x0 30. "SETENA30,Set INTR30 Enable" "0,1"
|
|
bitfld.long 0x0 29. "SETENA29,Set INTR29 Enable" "0,1"
|
|
bitfld.long 0x0 28. "SETENA28,Set INTR28 Enable" "0,1"
|
|
bitfld.long 0x0 27. "SETENA27,Set INTR27 Enable" "0,1"
|
|
bitfld.long 0x0 26. "SETENA26,Set INTR26 Enable" "0,1"
|
|
bitfld.long 0x0 25. "SETENA25,Set INTR25 Enable" "0,1"
|
|
bitfld.long 0x0 24. "SETENA24,Set INTR24 Enable" "0,1"
|
|
bitfld.long 0x0 23. "SETENA23,Set INTR23 Enable" "0,1"
|
|
bitfld.long 0x0 22. "SETENA22,Set INTR22 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SETENA21,Set INTR21 Enable" "0,1"
|
|
bitfld.long 0x0 20. "SETENA20,Set INTR20 Enable" "0,1"
|
|
bitfld.long 0x0 19. "SETENA19,Set INTR19 Enable" "0,1"
|
|
bitfld.long 0x0 18. "SETENA18,Set INTR18 Enable" "0,1"
|
|
bitfld.long 0x0 17. "SETENA17,Set INTR17 Enable" "0,1"
|
|
bitfld.long 0x0 16. "SETENA16,Set INTR16 Enable" "0,1"
|
|
bitfld.long 0x0 15. "SETENA15,Set INTR15 Enable" "0,1"
|
|
bitfld.long 0x0 14. "SETENA14,Set INTR14 Enable" "0,1"
|
|
bitfld.long 0x0 13. "SETENA13,Set INTR13 Enable" "0,1"
|
|
bitfld.long 0x0 12. "SETENA12,Set INTR12 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETENA11,Set INTR11 Enable" "0,1"
|
|
bitfld.long 0x0 10. "SETENA10,Set INTR10 Enable" "0,1"
|
|
bitfld.long 0x0 9. "SETENA9,Set INTR9 Enable" "0,1"
|
|
bitfld.long 0x0 8. "SETENA8,Set INTR8 Enable" "0,1"
|
|
bitfld.long 0x0 7. "SETENA7,Set INTR7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "SETENA6,Set INTR6 Enable" "0,1"
|
|
bitfld.long 0x0 5. "SETENA5,Set INTR5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "SETENA4,Set INTR4 Enable" "0,1"
|
|
bitfld.long 0x0 3. "SETENA3,Set INTR3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "SETENA2,Set INTR2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SETENA1,Set INTR1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "SETENA0,Set INTR0 Enable" "0,1"
|
|
line.long 0x4 "NVIC_ISER1,NVIC Interrupt Set Enable Register 1"
|
|
bitfld.long 0x4 31. "SETENA63,Set INTR63 Enable" "0,1"
|
|
bitfld.long 0x4 30. "SETENA62,Set INTR62 Enable" "0,1"
|
|
bitfld.long 0x4 29. "SETENA61,Set INTR61 Enable" "0,1"
|
|
bitfld.long 0x4 28. "SETENA60,Set INTR60 Enable" "0,1"
|
|
bitfld.long 0x4 27. "SETENA59,Set INTR59 Enable" "0,1"
|
|
bitfld.long 0x4 26. "SETENA58,Set INTR58 Enable" "0,1"
|
|
bitfld.long 0x4 25. "SETENA57,Set INTR57 Enable" "0,1"
|
|
bitfld.long 0x4 24. "SETENA56,Set INTR56 Enable" "0,1"
|
|
bitfld.long 0x4 23. "SETENA55,Set INTR55 Enable" "0,1"
|
|
bitfld.long 0x4 22. "SETENA54,Set INTR54 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SETENA53,Set INTR53 Enable" "0,1"
|
|
bitfld.long 0x4 20. "SETENA52,Set INTR52 Enable" "0,1"
|
|
bitfld.long 0x4 19. "SETENA51,Set INTR51 Enable" "0,1"
|
|
bitfld.long 0x4 18. "SETENA50,Set INTR50 Enable" "0,1"
|
|
bitfld.long 0x4 17. "SETENA49,Set INTR49 Enable" "0,1"
|
|
bitfld.long 0x4 16. "SETENA48,Set INTR48 Enable" "0,1"
|
|
bitfld.long 0x4 15. "SETENA47,Set INTR47 Enable" "0,1"
|
|
bitfld.long 0x4 14. "SETENA46,Set INTR46 Enable" "0,1"
|
|
bitfld.long 0x4 13. "SETENA45,Set INTR45 Enable" "0,1"
|
|
bitfld.long 0x4 12. "SETENA44,Set INTR44 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SETENA43,Set INTR43 Enable" "0,1"
|
|
bitfld.long 0x4 10. "SETENA42,Set INTR42 Enable" "0,1"
|
|
bitfld.long 0x4 9. "SETENA41,Set INTR41 Enable" "0,1"
|
|
bitfld.long 0x4 8. "SETENA40,Set INTR40 Enable" "0,1"
|
|
bitfld.long 0x4 7. "SETENA39,Set INTR39 Enable" "0,1"
|
|
bitfld.long 0x4 6. "SETENA38,Set INTR38 Enable" "0,1"
|
|
bitfld.long 0x4 5. "SETENA37,Set INTR37 Enable" "0,1"
|
|
bitfld.long 0x4 4. "SETENA36,Set INTR36 Enable" "0,1"
|
|
bitfld.long 0x4 3. "SETENA35,Set INTR35 Enable" "0,1"
|
|
bitfld.long 0x4 2. "SETENA34,Set INTR34 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SETENA33,Set INTR33 Enable" "0,1"
|
|
bitfld.long 0x4 0. "SETENA32,Set INTR32 Enable" "0,1"
|
|
group.long 0x180++0x7
|
|
line.long 0x0 "NVIC_ICER0,NVIC Interrupt Clear Enable Register 0"
|
|
bitfld.long 0x0 31. "CLRENA31,Clear INTR31 Enable" "0,1"
|
|
bitfld.long 0x0 30. "CLRENA30,Clear INTR30 Enable" "0,1"
|
|
bitfld.long 0x0 29. "CLRENA29,Clear INTR29 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CLRENA28,Clear INTR28 Enable" "0,1"
|
|
bitfld.long 0x0 27. "CLRENA27,Clear INTR27 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CLRENA26,Clear INTR26 Enable" "0,1"
|
|
bitfld.long 0x0 25. "CLRENA25,Clear INTR25 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CLRENA24,Clear INTR24 Enable" "0,1"
|
|
bitfld.long 0x0 23. "CLRENA23,Clear INTR23 Enable" "0,1"
|
|
bitfld.long 0x0 22. "CLRENA22,Clear INTR22 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CLRENA21,Clear INTR21 Enable" "0,1"
|
|
bitfld.long 0x0 20. "CLRENA20,Clear INTR20 Enable" "0,1"
|
|
bitfld.long 0x0 19. "CLRENA19,Clear INTR19 Enable" "0,1"
|
|
bitfld.long 0x0 18. "CLRENA18,Clear INTR18 Enable" "0,1"
|
|
bitfld.long 0x0 17. "CLRENA17,Clear INTR17 Enable" "0,1"
|
|
bitfld.long 0x0 16. "CLRENA16,Clear INTR16 Enable" "0,1"
|
|
bitfld.long 0x0 15. "CLRENA15,Clear INTR15 Enable" "0,1"
|
|
bitfld.long 0x0 14. "CLRENA14,Clear INTR14 Enable" "0,1"
|
|
bitfld.long 0x0 13. "CLRENA13,Clear INTR13 Enable" "0,1"
|
|
bitfld.long 0x0 12. "CLRENA12,Clear INTR12 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CLRENA11,Clear INTR11 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CLRENA10,Clear INTR10 Enable" "0,1"
|
|
bitfld.long 0x0 9. "CLRENA9,Clear INTR9 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CLRENA8,Clear INTR8 Enable" "0,1"
|
|
bitfld.long 0x0 7. "CLRENA7,Clear INTR7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "CLRENA6,Clear INTR6 Enable" "0,1"
|
|
bitfld.long 0x0 5. "CLRENA5,Clear INTR5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "CLRENA4,Clear INTR4 Enable" "0,1"
|
|
bitfld.long 0x0 3. "CLRENA3,Clear INTR3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "CLRENA2,Clear INTR2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLRENA1,Clear INTR1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "CLRENA0,Clear INTR0 Enable" "0,1"
|
|
line.long 0x4 "NVIC_ICER1,NVIC Interrupt Clear Enable Register 1"
|
|
bitfld.long 0x4 31. "CLRENA63,Clear INTR63 Enable" "0,1"
|
|
bitfld.long 0x4 30. "CLRENA62,Clear INTR62 Enable" "0,1"
|
|
bitfld.long 0x4 29. "CLRENA61,Clear INTR61 Enable" "0,1"
|
|
bitfld.long 0x4 28. "CLRENA60,Clear INTR60 Enable" "0,1"
|
|
bitfld.long 0x4 27. "CLRENA59,Clear INTR59 Enable" "0,1"
|
|
bitfld.long 0x4 26. "CLRENA58,Clear INTR58 Enable" "0,1"
|
|
bitfld.long 0x4 25. "CLRENA57,Clear INTR57 Enable" "0,1"
|
|
bitfld.long 0x4 24. "CLRENA56,Clear INTR56 Enable" "0,1"
|
|
bitfld.long 0x4 23. "CLRENA55,Clear INTR55 Enable" "0,1"
|
|
bitfld.long 0x4 22. "CLRENA54,Clear INTR54 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CLRENA53,Clear INTR53 Enable" "0,1"
|
|
bitfld.long 0x4 20. "CLRENA52,Clear INTR52 Enable" "0,1"
|
|
bitfld.long 0x4 19. "CLRENA51,Clear INTR51 Enable" "0,1"
|
|
bitfld.long 0x4 18. "CLRENA50,Clear INTR50 Enable" "0,1"
|
|
bitfld.long 0x4 17. "CLRENA49,Clear INTR49 Enable" "0,1"
|
|
bitfld.long 0x4 16. "CLRENA48,Clear INTR48 Enable" "0,1"
|
|
bitfld.long 0x4 15. "CLRENA47,Clear INTR47 Enable" "0,1"
|
|
bitfld.long 0x4 14. "CLRENA46,Clear INTR46 Enable" "0,1"
|
|
bitfld.long 0x4 13. "CLRENA45,Clear INTR45 Enable" "0,1"
|
|
bitfld.long 0x4 12. "CLRENA44,Clear INTR44 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CLRENA43,Clear INTR43 Enable" "0,1"
|
|
bitfld.long 0x4 10. "CLRENA42,Clear INTR42 Enable" "0,1"
|
|
bitfld.long 0x4 9. "CLRENA41,Clear INTR41 Enable" "0,1"
|
|
bitfld.long 0x4 8. "CLRENA40,Clear INTR40 Enable" "0,1"
|
|
bitfld.long 0x4 7. "CLRENA39,Clear INTR39 Enable" "0,1"
|
|
bitfld.long 0x4 6. "CLRENA38,Clear INTR38 Enable" "0,1"
|
|
bitfld.long 0x4 5. "CLRENA37,Clear INTR37 Enable" "0,1"
|
|
bitfld.long 0x4 4. "CLRENA36,Clear INTR36 Enable" "0,1"
|
|
bitfld.long 0x4 3. "CLRENA35,Clear INTR35 Enable" "0,1"
|
|
bitfld.long 0x4 2. "CLRENA34,Clear INTR34 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLRENA33,Clear INTR33 Enable" "0,1"
|
|
bitfld.long 0x4 0. "CLRENA32,Clear INTR32 Enable" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "NVIC_ISPR0,NVIC Interrupt Set Pending Register 0"
|
|
bitfld.long 0x0 31. "SETPEND31,Set INTR31 Pending" "0,1"
|
|
bitfld.long 0x0 30. "SETPEND30,Set INTR30 Pending" "0,1"
|
|
bitfld.long 0x0 29. "SETPEND29,Set INTR29 Pending" "0,1"
|
|
bitfld.long 0x0 28. "SETPEND28,Set INTR28 Pending" "0,1"
|
|
bitfld.long 0x0 27. "SETPEND27,Set INTR27 Pending" "0,1"
|
|
bitfld.long 0x0 26. "SETPEND26,Set INTR26 Pending" "0,1"
|
|
bitfld.long 0x0 25. "SETPEND25,Set INTR25 Pending" "0,1"
|
|
bitfld.long 0x0 24. "SETPEND24,Set INTR24 Pending" "0,1"
|
|
bitfld.long 0x0 23. "SETPEND23,Set INTR23 Pending" "0,1"
|
|
bitfld.long 0x0 22. "SETPEND22,Set INTR22 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SETPEND21,Set INTR21 Pending" "0,1"
|
|
bitfld.long 0x0 20. "SETPEND20,Set INTR20 Pending" "0,1"
|
|
bitfld.long 0x0 19. "SETPEND19,Set INTR19 Pending" "0,1"
|
|
bitfld.long 0x0 18. "SETPEND18,Set INTR18 Pending" "0,1"
|
|
bitfld.long 0x0 17. "SETPEND17,Set INTR17 Pending" "0,1"
|
|
bitfld.long 0x0 16. "SETPEND16,Set INTR16 Pending" "0,1"
|
|
bitfld.long 0x0 15. "SETPEND15,Set INTR15 Pending" "0,1"
|
|
bitfld.long 0x0 14. "SETPEND14,Set INTR14 Pending" "0,1"
|
|
bitfld.long 0x0 13. "SETPEND13,Set INTR13 Pending" "0,1"
|
|
bitfld.long 0x0 12. "SETPEND12,Set INTR12 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETPEND11,Set INTR11 Pending" "0,1"
|
|
bitfld.long 0x0 10. "SETPEND10,Set INTR10 Pending" "0,1"
|
|
bitfld.long 0x0 9. "SETPEND9,Set INTR9 Pending" "0,1"
|
|
bitfld.long 0x0 8. "SETPEND8,Set INTR8 Pending" "0,1"
|
|
bitfld.long 0x0 7. "SETPEND7,Set INTR7 Pending" "0,1"
|
|
bitfld.long 0x0 6. "SETPEND6,Set INTR6 Pending" "0,1"
|
|
bitfld.long 0x0 5. "SETPEND5,Set INTR5 Pending" "0,1"
|
|
bitfld.long 0x0 4. "SETPEND4,Set INTR4 Pending" "0,1"
|
|
bitfld.long 0x0 3. "SETPEND3,Set INTR3 Pending" "0,1"
|
|
bitfld.long 0x0 2. "SETPEND2,Set INTR2 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SETPEND1,Set INTR1 Pending" "0,1"
|
|
bitfld.long 0x0 0. "SETPEND0,Set INTR0 Pending" "0,1"
|
|
line.long 0x4 "NVIC_ISPR1,NVIC Interrupt Set Pending Register 1"
|
|
bitfld.long 0x4 31. "SETPEND63,Set INTR63 Pending" "0,1"
|
|
bitfld.long 0x4 30. "SETPEND62,Set INTR62 Pending" "0,1"
|
|
bitfld.long 0x4 29. "SETPEND61,Set INTR61 Pending" "0,1"
|
|
bitfld.long 0x4 28. "SETPEND60,Set INTR60 Pending" "0,1"
|
|
bitfld.long 0x4 27. "SETPEND59,Set INTR59 Pending" "0,1"
|
|
bitfld.long 0x4 26. "SETPEND58,Set INTR58 Pending" "0,1"
|
|
bitfld.long 0x4 25. "SETPEND57,Set INTR57 Pending" "0,1"
|
|
bitfld.long 0x4 24. "SETPEND56,Set INTR56 Pending" "0,1"
|
|
bitfld.long 0x4 23. "SETPEND55,Set INTR55 Pending" "0,1"
|
|
bitfld.long 0x4 22. "SETPEND54,Set INTR54 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SETPEND53,Set INTR53 Pending" "0,1"
|
|
bitfld.long 0x4 20. "SETPEND52,Set INTR52 Pending" "0,1"
|
|
bitfld.long 0x4 19. "SETPEND51,Set INTR51 Pending" "0,1"
|
|
bitfld.long 0x4 18. "SETPEND50,Set INTR50 Pending" "0,1"
|
|
bitfld.long 0x4 17. "SETPEND49,Set INTR49 Pending" "0,1"
|
|
bitfld.long 0x4 16. "SETPEND48,Set INTR48 Pending" "0,1"
|
|
bitfld.long 0x4 15. "SETPEND47,Set INTR47 Pending" "0,1"
|
|
bitfld.long 0x4 14. "SETPEND46,Set INTR46 Pending" "0,1"
|
|
bitfld.long 0x4 13. "SETPEND45,Set INTR45 Pending" "0,1"
|
|
bitfld.long 0x4 12. "SETPEND44,Set INTR44 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SETPEND43,Set INTR43 Pending" "0,1"
|
|
bitfld.long 0x4 10. "SETPEND42,Set INTR42 Pending" "0,1"
|
|
bitfld.long 0x4 9. "SETPEND41,Set INTR41 Pending" "0,1"
|
|
bitfld.long 0x4 8. "SETPEND40,Set INTR40 Pending" "0,1"
|
|
bitfld.long 0x4 7. "SETPEND39,Set INTR39 Pending" "0,1"
|
|
bitfld.long 0x4 6. "SETPEND38,Set INTR38 Pending" "0,1"
|
|
bitfld.long 0x4 5. "SETPEND37,Set INTR37 Pending" "0,1"
|
|
bitfld.long 0x4 4. "SETPEND36,Set INTR36 Pending" "0,1"
|
|
bitfld.long 0x4 3. "SETPEND35,Set INTR35 Pending" "0,1"
|
|
bitfld.long 0x4 2. "SETPEND34,Set INTR34 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SETPEND33,Set INTR33 Pending" "0,1"
|
|
bitfld.long 0x4 0. "SETPEND32,Set INTR32 Pending" "0,1"
|
|
line.long 0x8 "NVIC_ISPR2,NVIC Interrupt Set Pending Register 2"
|
|
bitfld.long 0x8 31. "SETPEND95,Set INTR95 Pending" "0,1"
|
|
bitfld.long 0x8 30. "SETPEND94,Set INTR94 Pending" "0,1"
|
|
bitfld.long 0x8 29. "SETPEND93,Set INTR93 Pending" "0,1"
|
|
bitfld.long 0x8 28. "SETPEND92,Set INTR92 Pending" "0,1"
|
|
bitfld.long 0x8 27. "SETPEND91,Set INTR91 Pending" "0,1"
|
|
bitfld.long 0x8 26. "SETPEND90,Set INTR90 Pending" "0,1"
|
|
bitfld.long 0x8 25. "SETPEND89,Set INTR89 Pending" "0,1"
|
|
bitfld.long 0x8 24. "SETPEND88,Set INTR88 Pending" "0,1"
|
|
bitfld.long 0x8 23. "SETPEND87,Set INTR87 Pending" "0,1"
|
|
bitfld.long 0x8 22. "SETPEND86,Set INTR86 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "SETPEND85,Set INTR85 Pending" "0,1"
|
|
bitfld.long 0x8 20. "SETPEND84,Set INTR84 Pending" "0,1"
|
|
bitfld.long 0x8 19. "SETPEND83,Set INTR83 Pending" "0,1"
|
|
bitfld.long 0x8 18. "SETPEND82,Set INTR82 Pending" "0,1"
|
|
bitfld.long 0x8 17. "SETPEND81,Set INTR81 Pending" "0,1"
|
|
bitfld.long 0x8 16. "SETPEND80,Set INTR80 Pending" "0,1"
|
|
bitfld.long 0x8 15. "SETPEND79,Set INTR79 Pending" "0,1"
|
|
bitfld.long 0x8 14. "SETPEND78,Set INTR78 Pending" "0,1"
|
|
bitfld.long 0x8 13. "SETPEND77,Set INTR77 Pending" "0,1"
|
|
bitfld.long 0x8 12. "SETPEND76,Set INTR76 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SETPEND75,Set INTR75 Pending" "0,1"
|
|
bitfld.long 0x8 10. "SETPEND74,Set INTR74 Pending" "0,1"
|
|
bitfld.long 0x8 9. "SETPEND73,Set INTR73 Pending" "0,1"
|
|
bitfld.long 0x8 8. "SETPEND72,Set INTR72 Pending" "0,1"
|
|
bitfld.long 0x8 7. "SETPEND71,Set INTR71 Pending" "0,1"
|
|
bitfld.long 0x8 6. "SETPEND70,Set INTR70 Pending" "0,1"
|
|
bitfld.long 0x8 5. "SETPEND69,Set INTR69 Pending" "0,1"
|
|
bitfld.long 0x8 4. "SETPEND68,Set INTR68 Pending" "0,1"
|
|
bitfld.long 0x8 3. "SETPEND67,Set INTR67 Pending" "0,1"
|
|
bitfld.long 0x8 2. "SETPEND66,Set INTR66 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SETPEND65,Set INTR65 Pending" "0,1"
|
|
bitfld.long 0x8 0. "SETPEND64,Set INTR64 Pending" "0,1"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "NVIC_ICPR0,NVIC Interrupt Clear Pending Register 0"
|
|
bitfld.long 0x0 31. "CLRPEND31,Clear INTR31 Pending" "0,1"
|
|
bitfld.long 0x0 30. "CLRPEND30,Clear INTR30 Pending" "0,1"
|
|
bitfld.long 0x0 29. "CLRPEND29,Clear INTR29 Pending" "0,1"
|
|
bitfld.long 0x0 28. "CLRPEND28,Clear INTR28 Pending" "0,1"
|
|
bitfld.long 0x0 27. "CLRPEND27,Clear INTR27 Pending" "0,1"
|
|
bitfld.long 0x0 26. "CLRPEND26,Clear INTR26 Pending" "0,1"
|
|
bitfld.long 0x0 25. "CLRPEND25,Clear INTR25 Pending" "0,1"
|
|
bitfld.long 0x0 24. "CLRPEND24,Clear INTR24 Pending" "0,1"
|
|
bitfld.long 0x0 23. "CLRPEND23,Clear INTR23 Pending" "0,1"
|
|
bitfld.long 0x0 22. "CLRPEND22,Clear INTR22 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CLRPEND21,Clear INTR21 Pending" "0,1"
|
|
bitfld.long 0x0 20. "CLRPEND20,Clear INTR20 Pending" "0,1"
|
|
bitfld.long 0x0 19. "CLRPEND19,Clear INTR19 Pending" "0,1"
|
|
bitfld.long 0x0 18. "CLRPEND18,Clear INTR18 Pending" "0,1"
|
|
bitfld.long 0x0 17. "CLRPEND17,Clear INTR17 Pending" "0,1"
|
|
bitfld.long 0x0 16. "CLRPEND16,Clear INTR16 Pending" "0,1"
|
|
bitfld.long 0x0 15. "CLRPEND15,Clear INTR15 Pending" "0,1"
|
|
bitfld.long 0x0 14. "CLRPEND14,Clear INTR14 Pending" "0,1"
|
|
bitfld.long 0x0 13. "CLRPEND13,Clear INTR13 Pending" "0,1"
|
|
bitfld.long 0x0 12. "CLRPEND12,Clear INTR12 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CLRPEND11,Clear INTR11 Pending" "0,1"
|
|
bitfld.long 0x0 10. "CLRPEND10,Clear INTR10 Pending" "0,1"
|
|
bitfld.long 0x0 9. "CLRPEND9,Clear INTR9 Pending" "0,1"
|
|
bitfld.long 0x0 8. "CLRPEND8,Clear INTR8 Pending" "0,1"
|
|
bitfld.long 0x0 7. "CLRPEND7,Clear INTR7 Pending" "0,1"
|
|
bitfld.long 0x0 6. "CLRPEND6,Clear INTR6 Pending" "0,1"
|
|
bitfld.long 0x0 5. "CLRPEND5,Clear INTR5 Pending" "0,1"
|
|
bitfld.long 0x0 4. "CLRPEND4,Clear INTR4 Pending" "0,1"
|
|
bitfld.long 0x0 3. "CLRPEND3,Clear INTR3 Pending" "0,1"
|
|
bitfld.long 0x0 2. "CLRPEND2,Clear INTR2 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLRPEND1,Clear INTR1 Pending" "0,1"
|
|
bitfld.long 0x0 0. "CLRPEND0,Clear INTR0 Pending" "0,1"
|
|
line.long 0x4 "NVIC_ICPR1,NVIC Interrupt Clear Pending Register 1"
|
|
bitfld.long 0x4 31. "CLRPEND63,Clear INTR63 Pending" "0,1"
|
|
bitfld.long 0x4 30. "CLRPEND62,Clear INTR62 Pending" "0,1"
|
|
bitfld.long 0x4 29. "CLRPEND61,Clear INTR61 Pending" "0,1"
|
|
bitfld.long 0x4 28. "CLRPEND60,Clear INTR60 Pending" "0,1"
|
|
bitfld.long 0x4 27. "CLRPEND59,Clear INTR59 Pending" "0,1"
|
|
bitfld.long 0x4 26. "CLRPEND58,Clear INTR58 Pending" "0,1"
|
|
bitfld.long 0x4 25. "CLRPEND57,Clear INTR57 Pending" "0,1"
|
|
bitfld.long 0x4 24. "CLRPEND56,Clear INTR56 Pending" "0,1"
|
|
bitfld.long 0x4 23. "CLRPEND55,Clear INTR55 Pending" "0,1"
|
|
bitfld.long 0x4 22. "CLRPEND54,Clear INTR54 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CLRPEND53,Clear INTR53 Pending" "0,1"
|
|
bitfld.long 0x4 20. "CLRPEND52,Clear INTR52 Pending" "0,1"
|
|
bitfld.long 0x4 19. "CLRPEND51,Clear INTR51 Pending" "0,1"
|
|
bitfld.long 0x4 18. "CLRPEND50,Clear INTR50 Pending" "0,1"
|
|
bitfld.long 0x4 17. "CLRPEND49,Clear INTR49 Pending" "0,1"
|
|
bitfld.long 0x4 16. "CLRPEND48,Clear INTR48 Pending" "0,1"
|
|
bitfld.long 0x4 15. "CLRPEND47,Clear INTR47 Pending" "0,1"
|
|
bitfld.long 0x4 14. "CLRPEND46,Clear INTR46 Pending" "0,1"
|
|
bitfld.long 0x4 13. "CLRPEND45,Clear INTR45 Pending" "0,1"
|
|
bitfld.long 0x4 12. "CLRPEND44,Clear INTR44 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CLRPEND43,Clear INTR43 Pending" "0,1"
|
|
bitfld.long 0x4 10. "CLRPEND42,Clear INTR42 Pending" "0,1"
|
|
bitfld.long 0x4 9. "CLRPEND41,Clear INTR41 Pending" "0,1"
|
|
bitfld.long 0x4 8. "CLRPEND40,Clear INTR40 Pending" "0,1"
|
|
bitfld.long 0x4 7. "CLRPEND39,Clear INTR39 Pending" "0,1"
|
|
bitfld.long 0x4 6. "CLRPEND38,Clear INTR38 Pending" "0,1"
|
|
bitfld.long 0x4 5. "CLRPEND37,Clear INTR37 Pending" "0,1"
|
|
bitfld.long 0x4 4. "CLRPEND36,Clear INTR36 Pending" "0,1"
|
|
bitfld.long 0x4 3. "CLRPEND35,Clear INTR35 Pending" "0,1"
|
|
bitfld.long 0x4 2. "CLRPEND34,Clear INTR34 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLRPEND33,Clear INTR33 Pending" "0,1"
|
|
bitfld.long 0x4 0. "CLRPEND32,Clear INTR32 Pending" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "NVIC_IABR0,NVIC Interrupt Active Bit Register 0"
|
|
bitfld.long 0x0 31. "ACTIVE31,INTR31 Active" "0,1"
|
|
bitfld.long 0x0 30. "ACTIVE30,INTR30 Active" "0,1"
|
|
bitfld.long 0x0 29. "ACTIVE29,INTR29 Active" "0,1"
|
|
bitfld.long 0x0 28. "ACTIVE28,INTR28 Active" "0,1"
|
|
bitfld.long 0x0 27. "ACTIVE27,INTR27 Active" "0,1"
|
|
bitfld.long 0x0 26. "ACTIVE26,INTR26 Active" "0,1"
|
|
bitfld.long 0x0 25. "ACTIVE25,INTR25 Active" "0,1"
|
|
bitfld.long 0x0 24. "ACTIVE24,INTR24 Active" "0,1"
|
|
bitfld.long 0x0 23. "ACTIVE23,INTR23 Active" "0,1"
|
|
bitfld.long 0x0 22. "ACTIVE22,INTR22 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ACTIVE21,INTR21 Active" "0,1"
|
|
bitfld.long 0x0 20. "ACTIVE20,INTR20 Active" "0,1"
|
|
bitfld.long 0x0 19. "ACTIVE19,INTR19 Active" "0,1"
|
|
bitfld.long 0x0 18. "ACTIVE18,INTR18 Active" "0,1"
|
|
bitfld.long 0x0 17. "ACTIVE17,INTR17 Active" "0,1"
|
|
bitfld.long 0x0 16. "ACTIVE16,INTR16 Active" "0,1"
|
|
bitfld.long 0x0 15. "ACTIVE15,INTR15 Active" "0,1"
|
|
bitfld.long 0x0 14. "ACTIVE14,INTR14 Active" "0,1"
|
|
bitfld.long 0x0 13. "ACTIVE13,INTR13 Active" "0,1"
|
|
bitfld.long 0x0 12. "ACTIVE12,INTR12 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ACTIVE11,INTR11 Active" "0,1"
|
|
bitfld.long 0x0 10. "ACTIVE10,INTR10 Active" "0,1"
|
|
bitfld.long 0x0 9. "ACTIVE9,INTR9 Active" "0,1"
|
|
bitfld.long 0x0 8. "ACTIVE8,INTR8 Active" "0,1"
|
|
bitfld.long 0x0 7. "ACTIVE7,INTR7 Active" "0,1"
|
|
bitfld.long 0x0 6. "ACTIVE6,INTR6 Active" "0,1"
|
|
bitfld.long 0x0 5. "ACTIVE5,INTR5 Active" "0,1"
|
|
bitfld.long 0x0 4. "ACTIVE4,INTR4 Active" "0,1"
|
|
bitfld.long 0x0 3. "ACTIVE3,INTR3 Active" "0,1"
|
|
bitfld.long 0x0 2. "ACTIVE2,INTR2 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ACTIVE1,INTR1 Active" "0,1"
|
|
bitfld.long 0x0 0. "ACTIVE0,INTR0 Active" "0,1"
|
|
line.long 0x4 "NVIC_IABR1,NVIC Interrupt Active Bit Register 1"
|
|
bitfld.long 0x4 31. "ACTIVE63,INTR63 Active" "0,1"
|
|
bitfld.long 0x4 30. "ACTIVE62,INTR62 Active" "0,1"
|
|
bitfld.long 0x4 29. "ACTIVE61,INTR61 Active" "0,1"
|
|
bitfld.long 0x4 28. "ACTIVE60,INTR60 Active" "0,1"
|
|
bitfld.long 0x4 27. "ACTIVE59,INTR59 Active" "0,1"
|
|
bitfld.long 0x4 26. "ACTIVE58,INTR58 Active" "0,1"
|
|
bitfld.long 0x4 25. "ACTIVE57,INTR57 Active" "0,1"
|
|
bitfld.long 0x4 24. "ACTIVE56,INTR56 Active" "0,1"
|
|
bitfld.long 0x4 23. "ACTIVE55,INTR55 Active" "0,1"
|
|
bitfld.long 0x4 22. "ACTIVE54,INTR54 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ACTIVE53,INTR53 Active" "0,1"
|
|
bitfld.long 0x4 20. "ACTIVE52,INTR52 Active" "0,1"
|
|
bitfld.long 0x4 19. "ACTIVE51,INTR51 Active" "0,1"
|
|
bitfld.long 0x4 18. "ACTIVE50,INTR50 Active" "0,1"
|
|
bitfld.long 0x4 17. "ACTIVE49,INTR49 Active" "0,1"
|
|
bitfld.long 0x4 16. "ACTIVE48,INTR48 Active" "0,1"
|
|
bitfld.long 0x4 15. "ACTIVE47,INTR47 Active" "0,1"
|
|
bitfld.long 0x4 14. "ACTIVE46,INTR46 Active" "0,1"
|
|
bitfld.long 0x4 13. "ACTIVE45,INTR45 Active" "0,1"
|
|
bitfld.long 0x4 12. "ACTIVE44,INTR44 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ACTIVE43,INTR43 Active" "0,1"
|
|
bitfld.long 0x4 10. "ACTIVE42,INTR42 Active" "0,1"
|
|
bitfld.long 0x4 9. "ACTIVE41,INTR41 Active" "0,1"
|
|
bitfld.long 0x4 8. "ACTIVE40,INTR40 Active" "0,1"
|
|
bitfld.long 0x4 7. "ACTIVE39,INTR39 Active" "0,1"
|
|
bitfld.long 0x4 6. "ACTIVE38,INTR38 Active" "0,1"
|
|
bitfld.long 0x4 5. "ACTIVE37,INTR37 Active" "0,1"
|
|
bitfld.long 0x4 4. "ACTIVE36,INTR36 Active" "0,1"
|
|
bitfld.long 0x4 3. "ACTIVE35,INTR35 Active" "0,1"
|
|
bitfld.long 0x4 2. "ACTIVE34,INTR34 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ACTIVE33,INTR33 Active" "0,1"
|
|
bitfld.long 0x4 0. "ACTIVE32,INTR32 Active" "0,1"
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "NVIC_IPR0,NVIC Interrupt Priority Register 0"
|
|
bitfld.long 0x0 29.--31. "PRI_3,Priority byte offset 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 21.--23. "PRI_2,Priority byte offset 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 13.--15. "PRI_1,Priority byte offset 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5.--7. "PRI_0,Priority byte offset 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "NVIC_IPR1,NVIC Interrupt Priority Register 1"
|
|
bitfld.long 0x4 29.--31. "PRI_7,Priority byte offset 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 21.--23. "PRI_6,Priority byte offset 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 13.--15. "PRI_5,Priority byte offset 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 5.--7. "PRI_4,Priority byte offset 4" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "NVIC_IPR2,NVIC Interrupt Priority Register 2"
|
|
bitfld.long 0x8 29.--31. "PRI_11,Priority byte offset 11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 21.--23. "PRI_10,Priority byte offset 10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 13.--15. "PRI_9,Priority byte offset 9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 5.--7. "PRI_8,Priority byte offset 8" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "NVIC_IPR3,NVIC Interrupt Priority Register 3"
|
|
bitfld.long 0xC 29.--31. "PRI_15,Priority byte offset 15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 21.--23. "PRI_14,Priority byte offset 14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 13.--15. "PRI_13,Priority byte offset 13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 5.--7. "PRI_12,Priority byte offset 12" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "NVIC_IPR4,NVIC Interrupt Priority Register 4"
|
|
bitfld.long 0x10 29.--31. "PRI_19,Priority byte offset 19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 21.--23. "PRI_18,Priority byte offset 18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 13.--15. "PRI_17,Priority byte offset 17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 5.--7. "PRI_16,Priority byte offset 16" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "NVIC_IPR5,NVIC Interrupt Priority Register 5"
|
|
bitfld.long 0x14 29.--31. "PRI_23,Priority byte offset 23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "PRI_22,Priority byte offset 22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 13.--15. "PRI_21,Priority byte offset 21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 5.--7. "PRI_20,Priority byte offset 20" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "NVIC_IPR6,NVIC Interrupt Priority Register 6"
|
|
bitfld.long 0x18 29.--31. "PRI_27,Priority byte offset 27" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "PRI_26,Priority byte offset 26" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 13.--15. "PRI_25,Priority byte offset 25" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 5.--7. "PRI_24,Priority byte offset 24" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "NVIC_IPR7,NVIC Interrupt Priority Register 7"
|
|
bitfld.long 0x1C 29.--31. "PRI_31,Priority byte offset 31" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 21.--23. "PRI_30,Priority byte offset 30" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 13.--15. "PRI_29,Priority byte offset 29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 5.--7. "PRI_28,Priority byte offset 28" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "NVIC_IPR8,NVIC Interrupt Priority Register 8"
|
|
bitfld.long 0x20 29.--31. "PRI_35,Priority byte offset 35" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 21.--23. "PRI_34,Priority byte offset 34" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 13.--15. "PRI_33,Priority byte offset 33" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 5.--7. "PRI_32,Priority byte offset 32" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "NVIC_IPR9,NVIC Interrupt Priority Register 9"
|
|
bitfld.long 0x24 29.--31. "PRI_39,Priority byte offset 39" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 21.--23. "PRI_38,Priority byte offset 38" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 13.--15. "PRI_37,Priority byte offset 37" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 5.--7. "PRI_36,Priority byte offset 36" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "NVIC_IPR10,NVIC Interrupt Priority Register 10"
|
|
bitfld.long 0x28 29.--31. "PRI_43,Priority byte offset 43" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 21.--23. "PRI_42,Priority byte offset 42" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 13.--15. "PRI_41,Priority byte offset 41" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 5.--7. "PRI_40,Priority byte offset 40" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "NVIC_IPR11,NVIC Interrupt Priority Register 11"
|
|
bitfld.long 0x2C 29.--31. "PRI_47,Priority byte offset 47" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 21.--23. "PRI_46,Priority byte offset 46" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 13.--15. "PRI_45,Priority byte offset 45" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 5.--7. "PRI_44,Priority byte offset 44" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "NVIC_IPR12,NVIC Interrupt Priority Register 12"
|
|
bitfld.long 0x30 29.--31. "PRI_51,Priority byte offset 51" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x30 21.--23. "PRI_50,Priority byte offset 50" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x30 13.--15. "PRI_49,Priority byte offset 49" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x30 5.--7. "PRI_48,Priority byte offset 48" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "NVIC_IPR13,NVIC Interrupt Priority Register 13"
|
|
bitfld.long 0x34 29.--31. "PRI_55,Priority byte offset 55" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 21.--23. "PRI_54,Priority byte offset 54" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 13.--15. "PRI_53,Priority byte offset 53" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 5.--7. "PRI_52,Priority byte offset 52" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "NVIC_IPR14,NVIC Interrupt Priority Register 14"
|
|
bitfld.long 0x38 29.--31. "PRI_59,Priority byte offset 59" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 21.--23. "PRI_58,Priority byte offset 58" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 13.--15. "PRI_57,Priority byte offset 57" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 5.--7. "PRI_56,Priority byte offset 56" "0,1,2,3,4,5,6,7"
|
|
line.long 0x3C "NVIC_IPR15,NVIC Interrupt Priority Register 15"
|
|
bitfld.long 0x3C 29.--31. "PRI_63,Priority byte offset 63" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3C 21.--23. "PRI_62,Priority byte offset 62" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3C 13.--15. "PRI_61,Priority byte offset 61" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x3C 5.--7. "PRI_60,Priority byte offset 60" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF00++0x3
|
|
line.long 0x0 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Software Trigger Interrupt Register."
|
|
tree.end
|
|
tree "SCB"
|
|
base d:0xE000E000
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x0 8. "DISFPCA,Disables automatic update of CONTROL.FPCA." "0,1"
|
|
bitfld.long 0x0 2. "DISFOLD,Disables IT folding." "0,1"
|
|
bitfld.long 0x0 1. "DISDEFWBUF,Disable write buffer on default memory map." "0,1"
|
|
bitfld.long 0x0 0. "DISMCYCINT,Disable interruption of load/store multiple instruction." "0,1"
|
|
rgroup.long 0xD00++0x3
|
|
line.long 0x0 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "Implementer,Implementer"
|
|
hexmask.long.byte 0x0 20.--23. 1. "Variant,Variant"
|
|
hexmask.long.byte 0x0 16.--19. 1. "Constant,Constant"
|
|
hexmask.long.word 0x0 4.--15. 1. "PartNo,PartNo"
|
|
hexmask.long.byte 0x0 0.--3. 1. "Revision,Revision"
|
|
group.long 0xD04++0x2B
|
|
line.long 0x0 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x0 31. "NMIPENDSET,NMI set-pending bit." "0,1"
|
|
bitfld.long 0x0 28. "PENDSVSET,PendSV set-pending bit." "0,1"
|
|
bitfld.long 0x0 27. "PENDSVCLR,PendSV clear-pending bit." "0,1"
|
|
bitfld.long 0x0 26. "PENDSTSET,SysTick exception set-pending bit." "0,1"
|
|
bitfld.long 0x0 25. "PENDSTCLR,SysTick exception clear-pending bit" "0,1"
|
|
rbitfld.long 0x0 22. "ISRPENDING,Interrupt pending flag" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Exception number of highest priority pending exception."
|
|
rbitfld.long 0x0 11. "RETTOBASE,Indicates presence of preempted active exceptions." "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Active exception number"
|
|
line.long 0x4 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x4 7.--31. 1. "TBLOFF,Vector table offset."
|
|
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "VECTKEY,Vector Key."
|
|
rbitfld.long 0x8 15. "ENDIANNESS,Data endianness bit" "0,1"
|
|
bitfld.long 0x8 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2. "SYSRESETREQ,System reset request bit" "0,1"
|
|
bitfld.long 0x8 1. "VECTCLRACTIVE,Reserved for Debug use." "0,1"
|
|
bitfld.long 0x8 0. "VECTRESET,CPU Reset" "0,1"
|
|
line.long 0xC "SCR,System Control Register"
|
|
bitfld.long 0xC 1. "SLEEPONEXIT,sleep-on-exit when returning from Handler mode." "0,1"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 9. "STKALIGN,Indicates stack alignment on exception entry." "0,1"
|
|
bitfld.long 0x10 8. "BFHFNMIGN,Ignore data BusFaults caused by load and store instructions." "0,1"
|
|
bitfld.long 0x10 4. "DIV_0_TRP,faulting/halting on DIV by 0 exception." "0,1"
|
|
bitfld.long 0x10 3. "UNALIGN_TRP,Enables unaligned access traps." "0,1"
|
|
bitfld.long 0x10 1. "USERSETMPEND,Enables unprivileged software access to the STIR." "0,1"
|
|
bitfld.long 0x10 0. "NONBASETHRDENA,Indicates how the processor enters Thread mode" "0,1"
|
|
line.long 0x14 "SHPR1,System Handler Priority Register 1"
|
|
bitfld.long 0x14 21.--23. "PRI_6,Priority of system handler 6 UsageFault" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 13.--15. "PRI_5,Priority of system handler 5 BusFault" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 5.--7. "PRI_4,Priority of system handler 4 MemManage" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x18 29.--31. "PRI_11,Priority of system handler 11 SVCall" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x1C 29.--31. "PRI_15,Priority of system handler 15 SysTick exception" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 21.--23. "PRI_14,Priority of system handler 14 PendSV" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "SHCSRS,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. "USGFAULTENA,UsageFault enable bit" "0,1"
|
|
bitfld.long 0x20 17. "BUSFAULTENA,BusFault enable bit" "0,1"
|
|
bitfld.long 0x20 16. "MEMFAULTENA,MemManage enable bit" "0,1"
|
|
bitfld.long 0x20 15. "SVCALLPENDED,SVCall pending bit" "0,1"
|
|
bitfld.long 0x20 14. "BUSFAULTPENDED,BusFault exception pending bit" "0,1"
|
|
bitfld.long 0x20 13. "MEMFAULTPENDED,MemManage exception pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 12. "USGFAULTPENDED,UsageFault exception pending bit" "0,1"
|
|
rbitfld.long 0x20 11. "SYSTICKACT,SysTick exception active bit" "0,1"
|
|
rbitfld.long 0x20 10. "PENDSVACT,PendSV exception active bit" "0,1"
|
|
rbitfld.long 0x20 8. "MONITORACT,Debug monitor active bit" "0,1"
|
|
rbitfld.long 0x20 7. "SVCALLACT,SVCall active bit" "0,1"
|
|
rbitfld.long 0x20 3. "USGFAULTACT,UsageFault exception active bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x20 1. "BUSFAULTACT,BusFault exception active bit" "0,1"
|
|
rbitfld.long 0x20 0. "MEMFAULTACT,MemManage exception active bit" "0,1"
|
|
line.long 0x24 "CFSR,Configurable Fault Status Register"
|
|
bitfld.long 0x24 25. "DIVBYZERO,Divide by zero UsageFault" "0,1"
|
|
bitfld.long 0x24 24. "UNALIGNED,Unaligned access UsageFault" "0,1"
|
|
bitfld.long 0x24 19. "NOCP,No coprocessor UsageFault" "0,1"
|
|
bitfld.long 0x24 18. "INVPC,Invalid PC load UsageFault" "0,1"
|
|
bitfld.long 0x24 17. "INVSTATE,Invalid state UsageFault" "0,1"
|
|
bitfld.long 0x24 16. "UNDEFINSTR,Undefined instruction UsageFault" "0,1"
|
|
newline
|
|
bitfld.long 0x24 15. "BFARVALID,BusFault Address Register (BFAR) valid flag" "0,1"
|
|
bitfld.long 0x24 12. "STKERR,BusFault on stacking for exception entry" "0,1"
|
|
bitfld.long 0x24 11. "UNSTKERR,BusFault on unstacking for a return from exception" "0,1"
|
|
bitfld.long 0x24 10. "IMPRECISERR,Imprecise data bus error" "0,1"
|
|
bitfld.long 0x24 9. "PRECISERR,Precise data bus error" "0,1"
|
|
bitfld.long 0x24 8. "IBUSERR,Instruction bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "MMARVALID,MemManage Fault Address Register (MMFAR) valid flag" "0,1"
|
|
bitfld.long 0x24 4. "MSTKERR,MemManage fault on stacking for exception entry" "0,1"
|
|
bitfld.long 0x24 3. "MUNSTKERR,MemManage fault on unstacking for a return from exception" "0,1"
|
|
bitfld.long 0x24 1. "DACCVIOL,Data access violation flag" "0,1"
|
|
bitfld.long 0x24 0. "IACCVIOL,Instruction access violation flag" "0,1"
|
|
line.long 0x28 "HFSR,HardFault Status Register"
|
|
bitfld.long 0x28 31. "DEBUGEVT,Indicates a forced DEBUG event fault" "0,1"
|
|
bitfld.long 0x28 30. "FORCED,Indicates a forced hard fault" "0,1"
|
|
bitfld.long 0x28 1. "VECTTBL,BusFault on a vector table read." "0,1"
|
|
group.long 0xD34++0xB
|
|
line.long 0x0 "MMFAR,MemManage Fault Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDRESS,Address of the location that generated the MemManage fault"
|
|
line.long 0x4 "BFAR,BusFault Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,Address of the location that generated the BusFault"
|
|
line.long 0x8 "AFSR,Auxiliary Fault Status Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDRESS,The bits map to the AUXFAULT input signals."
|
|
tree.end
|
|
tree "SYSTICK (System Timer)"
|
|
base d:0xE000E000
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "SYST_CSR,Privileged a SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,timer counted to 0 since last read." "0,1"
|
|
bitfld.long 0x0 2. "CLKSOURCE,Indicates the clock source" "0,1"
|
|
bitfld.long 0x0 1. "TICKINT,Enables SysTick exception request" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Enables the counter" "0,1"
|
|
line.long 0x4 "SYST_RVR,Privileged Unknown SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Counter reload value"
|
|
line.long 0x8 "SYST_CVR,Privileged Unknown SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current counter value"
|
|
line.long 0xC "SYST_CALIB,Privileged -a SysTick Calibration Value Register"
|
|
bitfld.long 0xC 31. "NOREF,Device provides a reference clock to the processor" "0,1"
|
|
bitfld.long 0xC 30. "SKEW,Indicates whether the TENMS value is exact" "0,1"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "TENMS,Current counter value"
|
|
tree.end
|
|
base d:0x0
|
|
tree "TIMER (32-Bit CM CPU Timers 0/1/2)"
|
|
tree "TIMER0"
|
|
base d:0x40084000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIM,Timer counter register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Timer counter"
|
|
line.long 0x4 "PRD,Timer period register"
|
|
hexmask.long 0x4 0.--31. 1. "PRD,Timer Period"
|
|
line.long 0x8 "TCR,Timer control register"
|
|
bitfld.long 0x8 15. "TIF,Timer Intrerrupt Flag" "0,1"
|
|
bitfld.long 0x8 14. "TIE,Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 11. "FREE,Free run enable" "0,1"
|
|
bitfld.long 0x8 10. "SOFT,SOFT stop enable" "0,1"
|
|
bitfld.long 0x8 5. "TRB,Timer Reload Bit" "0,1"
|
|
bitfld.long 0x8 4. "TSS,Timer Stop Status" "0,1"
|
|
line.long 0xC "TPR,Timer prescaler register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "PSCH,Prescaler Counter high"
|
|
hexmask.long.byte 0xC 16.--23. 1. "TDDRH,Timer Divide Down Register High"
|
|
hexmask.long.byte 0xC 8.--15. 1. "PSCL,Prescaler Counter low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TDDRL,Timer Divide Down Register Low"
|
|
tree.end
|
|
tree "TIMER1"
|
|
base d:0x40084010
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIM,Timer counter register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Timer counter"
|
|
line.long 0x4 "PRD,Timer period register"
|
|
hexmask.long 0x4 0.--31. 1. "PRD,Timer Period"
|
|
line.long 0x8 "TCR,Timer control register"
|
|
bitfld.long 0x8 15. "TIF,Timer Intrerrupt Flag" "0,1"
|
|
bitfld.long 0x8 14. "TIE,Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 11. "FREE,Free run enable" "0,1"
|
|
bitfld.long 0x8 10. "SOFT,SOFT stop enable" "0,1"
|
|
bitfld.long 0x8 5. "TRB,Timer Reload Bit" "0,1"
|
|
bitfld.long 0x8 4. "TSS,Timer Stop Status" "0,1"
|
|
line.long 0xC "TPR,Timer prescaler register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "PSCH,Prescaler Counter high"
|
|
hexmask.long.byte 0xC 16.--23. 1. "TDDRH,Timer Divide Down Register High"
|
|
hexmask.long.byte 0xC 8.--15. 1. "PSCL,Prescaler Counter low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TDDRL,Timer Divide Down Register Low"
|
|
tree.end
|
|
tree "TIMER2"
|
|
base d:0x40084020
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TIM,Timer counter register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Timer counter"
|
|
line.long 0x4 "PRD,Timer period register"
|
|
hexmask.long 0x4 0.--31. 1. "PRD,Timer Period"
|
|
line.long 0x8 "TCR,Timer control register"
|
|
bitfld.long 0x8 15. "TIF,Timer Intrerrupt Flag" "0,1"
|
|
bitfld.long 0x8 14. "TIE,Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 11. "FREE,Free run enable" "0,1"
|
|
bitfld.long 0x8 10. "SOFT,SOFT stop enable" "0,1"
|
|
bitfld.long 0x8 5. "TRB,Timer Reload Bit" "0,1"
|
|
bitfld.long 0x8 4. "TSS,Timer Stop Status" "0,1"
|
|
line.long 0xC "TPR,Timer prescaler register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "PSCH,Prescaler Counter high"
|
|
hexmask.long.byte 0xC 16.--23. 1. "TDDRH,Timer Divide Down Register High"
|
|
hexmask.long.byte 0xC 8.--15. 1. "PSCL,Prescaler Counter low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TDDRL,Timer Divide Down Register Low"
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base d:0x40080000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SCSR,System Control and Status Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
hexmask.long.word 0x0 3.--15. 1. "rsvd,Reserved"
|
|
rbitfld.long 0x0 1. "WDENINT,WD Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WDOVERRIDE,WD Override for WDDIS bit" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "WDCNTR,Watchdog Counter Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "rsvd,Reserved"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WDCNTR,WD Counter"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "WDKEY,Watchdog Reset Key Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "rsvd,Reserved"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WDKEY,WD KEY"
|
|
line.long 0x4 "WDCR,Watchdog Control Register"
|
|
hexmask.long.tbyte 0x4 12.--31. 1. "rsvd,Reserved"
|
|
hexmask.long.byte 0x4 8.--11. 1. "WDPRECLKDIV,WD Pre Clock Divider"
|
|
bitfld.long 0x4 7. "WDFLG,WD Reset Status Flag" "0,1"
|
|
bitfld.long 0x4 6. "WDDIS,WD Disable" "0,1"
|
|
bitfld.long 0x4 3.--5. "WDCHK,WD Check Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "WDPS,WD Clock Prescalar" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "WDWCR,Watchdog Windowed Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "KEY,KEY field"
|
|
hexmask.long.byte 0x8 9.--15. 1. "rsvd,Reserved"
|
|
rbitfld.long 0x8 8. "FIRSTKEY,First Key Detect Flag" "0,1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MIN,WD Min Threshold setting for Windowed Watchdog functionality"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "CMPSS (Comparator Subsystems)"
|
|
base d:0x0
|
|
tree "CMPSS1"
|
|
base d:0x5C80
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS2"
|
|
base d:0x5CA0
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS3"
|
|
base d:0x5CC0
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS4"
|
|
base d:0x5CE0
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS5"
|
|
base d:0x5D00
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS6"
|
|
base d:0x5D20
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS7"
|
|
base d:0x5D40
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "CMPSS8"
|
|
base d:0x5D60
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x0 15. "COMPDACE,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASYNCLEN,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x0 10.--11. "CTRIPLSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 9. "COMPLINV,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSOURCE,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x0 6. "ASYNCHEN,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "CTRIPHSEL,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 1. "COMPHINV,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSOURCE,High Comparator Source Select" "0,1"
|
|
line.word 0x1 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x1 0.--2. "COMPHYS,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x0 9. "COMPLLATCH,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 8. "COMPLSTS,Low Comparator Status" "0,1"
|
|
bitfld.word 0x0 1. "COMPHLATCH,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x0 0. "COMPHSTS,High Comparator Status" "0,1"
|
|
group.word 0x3++0x5
|
|
line.word 0x0 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x0 10. "LSYNCCLREN,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 9. "LLATCHCLR,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "HSYNCCLREN,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x0 1. "HLATCHCLR,High Comparator Latched Status Clear" "0,1"
|
|
line.word 0x1 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x1 14.--15. "FREESOFT,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x1 12. "BLANKEN,EPWMBLANK Enable" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "BLANKSOURCE,EPWMBLANK Source Select"
|
|
bitfld.word 0x1 7. "SWLOADSEL,Software Load Select" "0,1"
|
|
bitfld.word 0x1 6. "RAMPLOADSEL,Ramp Load Select" "0,1"
|
|
bitfld.word 0x1 5. "SELREF,DAC Reference Select" "0,1"
|
|
hexmask.word.byte 0x1 1.--4. 1. "RAMPSOURCE,Ramp Generator Source Control"
|
|
bitfld.word 0x1 0. "DACSOURCE,DAC Source Control" "0,1"
|
|
line.word 0x3 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x3 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x7++0x3
|
|
line.word 0x0 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
hexmask.word 0x1 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Active"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp Maximum Reference Shadow"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Active"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp Decrement Value Shadow"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RAMPSTS,CMPSS Ramp Status Register"
|
|
hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp Value"
|
|
group.word 0x12++0x1
|
|
line.word 0x0 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word 0x13++0x3
|
|
line.word 0x0 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x0 0.--11. 1. "DACVAL,DAC Value Control"
|
|
line.word 0x1 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x1 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word 0x15++0xB
|
|
line.word 0x0 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x0 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
line.word 0x1 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x5 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x5 3. "CTRIP,CTRIP Lock" "0,1"
|
|
bitfld.word 0x5 2. "DACCTL,DACCTL Lock" "0,1"
|
|
bitfld.word 0x5 1. "COMPHYSCTL,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x5 0. "COMPCTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "DAC (Buffered Digital to Analog Converter)"
|
|
base d:0x0
|
|
tree "DACA"
|
|
base d:0x5C00
|
|
rgroup.word 0x0++0x1
|
|
line.word 0x0 "DACREV,DAC Revision Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REV,DAC Revision Register"
|
|
group.word 0x1++0x1
|
|
line.word 0x0 "DACCTL,DAC Control Register"
|
|
hexmask.word.byte 0x0 4.--7. 1. "SYNCSEL,DAC EPWMSYNCPER Select"
|
|
bitfld.word 0x0 2. "LOADMODE,DACVALA Load Mode" "0,1"
|
|
bitfld.word 0x0 0. "DACREFSEL,DAC Reference Select" "0,1"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "DACVALA,DAC Value Register - Active"
|
|
hexmask.word 0x0 0.--11. 1. "DACVALA,DAC Active Output Code"
|
|
group.word 0x3++0x7
|
|
line.word 0x0 "DACVALS,DAC Value Register - Shadow"
|
|
hexmask.word 0x0 0.--11. 1. "DACVALS,DAC Shadow Output Code"
|
|
line.word 0x1 "DACOUTEN,DAC Output Enable Register"
|
|
bitfld.word 0x1 0. "DACOUTEN,DAC Output Code" "0,1"
|
|
line.word 0x2 "DACLOCK,DAC Lock Register"
|
|
hexmask.word.byte 0x2 12.--15. 1. "KEY,DAC Register Lock Key"
|
|
bitfld.word 0x2 2. "DACOUTEN,DAC Output Enable Register Lock" "0,1"
|
|
bitfld.word 0x2 1. "DACVAL,DAC Value Register Lock" "0,1"
|
|
bitfld.word 0x2 0. "DACCTL,DAC Control Register Lock" "0,1"
|
|
line.word 0x3 "DACTRIM,DAC Trim Register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim"
|
|
tree.end
|
|
tree "DACB"
|
|
base d:0x5C10
|
|
rgroup.word 0x0++0x1
|
|
line.word 0x0 "DACREV,DAC Revision Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REV,DAC Revision Register"
|
|
group.word 0x1++0x1
|
|
line.word 0x0 "DACCTL,DAC Control Register"
|
|
hexmask.word.byte 0x0 4.--7. 1. "SYNCSEL,DAC EPWMSYNCPER Select"
|
|
bitfld.word 0x0 2. "LOADMODE,DACVALA Load Mode" "0,1"
|
|
bitfld.word 0x0 0. "DACREFSEL,DAC Reference Select" "0,1"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "DACVALA,DAC Value Register - Active"
|
|
hexmask.word 0x0 0.--11. 1. "DACVALA,DAC Active Output Code"
|
|
group.word 0x3++0x7
|
|
line.word 0x0 "DACVALS,DAC Value Register - Shadow"
|
|
hexmask.word 0x0 0.--11. 1. "DACVALS,DAC Shadow Output Code"
|
|
line.word 0x1 "DACOUTEN,DAC Output Enable Register"
|
|
bitfld.word 0x1 0. "DACOUTEN,DAC Output Code" "0,1"
|
|
line.word 0x2 "DACLOCK,DAC Lock Register"
|
|
hexmask.word.byte 0x2 12.--15. 1. "KEY,DAC Register Lock Key"
|
|
bitfld.word 0x2 2. "DACOUTEN,DAC Output Enable Register Lock" "0,1"
|
|
bitfld.word 0x2 1. "DACVAL,DAC Value Register Lock" "0,1"
|
|
bitfld.word 0x2 0. "DACCTL,DAC Control Register Lock" "0,1"
|
|
line.word 0x3 "DACTRIM,DAC Trim Register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim"
|
|
tree.end
|
|
tree "DACC"
|
|
base d:0x5C20
|
|
rgroup.word 0x0++0x1
|
|
line.word 0x0 "DACREV,DAC Revision Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REV,DAC Revision Register"
|
|
group.word 0x1++0x1
|
|
line.word 0x0 "DACCTL,DAC Control Register"
|
|
hexmask.word.byte 0x0 4.--7. 1. "SYNCSEL,DAC EPWMSYNCPER Select"
|
|
bitfld.word 0x0 2. "LOADMODE,DACVALA Load Mode" "0,1"
|
|
bitfld.word 0x0 0. "DACREFSEL,DAC Reference Select" "0,1"
|
|
rgroup.word 0x2++0x1
|
|
line.word 0x0 "DACVALA,DAC Value Register - Active"
|
|
hexmask.word 0x0 0.--11. 1. "DACVALA,DAC Active Output Code"
|
|
group.word 0x3++0x7
|
|
line.word 0x0 "DACVALS,DAC Value Register - Shadow"
|
|
hexmask.word 0x0 0.--11. 1. "DACVALS,DAC Shadow Output Code"
|
|
line.word 0x1 "DACOUTEN,DAC Output Enable Register"
|
|
bitfld.word 0x1 0. "DACOUTEN,DAC Output Code" "0,1"
|
|
line.word 0x2 "DACLOCK,DAC Lock Register"
|
|
hexmask.word.byte 0x2 12.--15. 1. "KEY,DAC Register Lock Key"
|
|
bitfld.word 0x2 2. "DACOUTEN,DAC Output Enable Register Lock" "0,1"
|
|
bitfld.word 0x2 1. "DACVAL,DAC Value Register Lock" "0,1"
|
|
bitfld.word 0x2 0. "DACCTL,DAC Control Register Lock" "0,1"
|
|
line.word 0x3 "DACTRIM,DAC Trim Register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim"
|
|
tree.end
|
|
tree.end
|
|
tree "DCC (Dual-Clock Comparator)"
|
|
base d:0x0
|
|
tree "DCC0"
|
|
base d:0x5E700
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters. Clears the error signal."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,DONE Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single-Shot Enable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,Error Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,DCC Enable"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to Clock Source 0."
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,Seed Value for Counter 0"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to Clock Source 0."
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED,Seed Value for Valid Duration Counter 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to Clock Source 1."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,Seed Value for Counter 1"
|
|
line.long 0xC "DCCSTATUS,Specifies the status of the DCC Module."
|
|
bitfld.long 0xC 1. "DONE,Single-Shot Done Flag" "0,1"
|
|
bitfld.long 0xC 0. "ERR,Error Flag" "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to Clock Source 0."
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,Current Value of Counter 0"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to Clock Source 0."
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,Current Value of Valid 0"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to Clock Source 1."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,Current Value of Counter 1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSRC1,Selects the clock source for Counter 1."
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY,Enables or Disables Clock Source Selection for COUNT1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,Clock Source Select for Counter 1"
|
|
line.long 0x4 "DCCCLKSRC0,Selects the clock source for Counter 0."
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY,Enables or Disables Clock Source Selection for COUNT0"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,Clock Source Select for Counter 0"
|
|
tree.end
|
|
tree "DCC1"
|
|
base d:0x5E740
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters. Clears the error signal."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,DONE Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single-Shot Enable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,Error Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,DCC Enable"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to Clock Source 0."
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,Seed Value for Counter 0"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to Clock Source 0."
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED,Seed Value for Valid Duration Counter 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to Clock Source 1."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,Seed Value for Counter 1"
|
|
line.long 0xC "DCCSTATUS,Specifies the status of the DCC Module."
|
|
bitfld.long 0xC 1. "DONE,Single-Shot Done Flag" "0,1"
|
|
bitfld.long 0xC 0. "ERR,Error Flag" "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to Clock Source 0."
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,Current Value of Counter 0"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to Clock Source 0."
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,Current Value of Valid 0"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to Clock Source 1."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,Current Value of Counter 1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSRC1,Selects the clock source for Counter 1."
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY,Enables or Disables Clock Source Selection for COUNT1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,Clock Source Select for Counter 1"
|
|
line.long 0x4 "DCCCLKSRC0,Selects the clock source for Counter 0."
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY,Enables or Disables Clock Source Selection for COUNT0"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,Clock Source Select for Counter 0"
|
|
tree.end
|
|
tree "DCC2"
|
|
base d:0x5E780
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters. Clears the error signal."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONEENA,DONE Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single-Shot Enable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,Error Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,DCC Enable"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to Clock Source 0."
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,Seed Value for Counter 0"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to Clock Source 0."
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED,Seed Value for Valid Duration Counter 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to Clock Source 1."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,Seed Value for Counter 1"
|
|
line.long 0xC "DCCSTATUS,Specifies the status of the DCC Module."
|
|
bitfld.long 0xC 1. "DONE,Single-Shot Done Flag" "0,1"
|
|
bitfld.long 0xC 0. "ERR,Error Flag" "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to Clock Source 0."
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,Current Value of Counter 0"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to Clock Source 0."
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,Current Value of Valid 0"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to Clock Source 1."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,Current Value of Counter 1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSRC1,Selects the clock source for Counter 1."
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY,Enables or Disables Clock Source Selection for COUNT1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,Clock Source Select for Counter 1"
|
|
line.long 0x4 "DCCCLKSRC0,Selects the clock source for Counter 0."
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY,Enables or Disables Clock Source Selection for COUNT0"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,Clock Source Select for Counter 0"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM"))
|
|
tree "DCSM (Dual Code Security Module)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "DCSM_Common"
|
|
base d:0x5F0C0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLSEM,Flash Wrapper Semaphore Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Semaphore Key"
|
|
bitfld.long 0x0 0.--1. "SEM,Flash Semaphore Bit" "0,1,2,3"
|
|
rgroup.long 0x8++0x1B
|
|
line.long 0x0 "SECTSTAT1,Flash Sectors Status Register 1"
|
|
bitfld.long 0x0 26.--27. "STATUS_SECT13,Zone Status flash CPU1 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "STATUS_SECT12,Zone Status flash CPU1 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "STATUS_SECT11,Zone Status flash CPU1 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "STATUS_SECT10,Zone Status flash CPU1 BANK Sector 10" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "STATUS_SECT9,Zone Status flash CPU1 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "STATUS_SECT8,Zone Status flash CPU1 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "STATUS_SECT7,Zone Status flash CPU1 BANK Sector 7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "STATUS_SECT6,Zone Status flash CPU1 BANK Sector 6" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "STATUS_SECT5,Zone Status flash CPU1 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "STATUS_SECT4,Zone Status flash CPU1 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "STATUS_SECT3,Zone Status flash CPU1 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "STATUS_SECT2,Zone Status flash CPU1 BANK Sector 2" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "STATUS_SECT1,Zone Status flash CPU1 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "STATUS_SECT0,Zone Status flash CPU1 BANK Sector 0" "0,1,2,3"
|
|
line.long 0x2 "SECTSTAT2,Flash Sectors Status Register 2"
|
|
bitfld.long 0x2 26.--27. "STATUS_SECT13,Zone Status flash CM BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "STATUS_SECT12,Zone Status flash CM BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "STATUS_SECT11,Zone Status flash CM BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "STATUS_SECT10,Zone Status flash CM BANK Sector 10" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "STATUS_SECT9,Zone Status flash CM BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "STATUS_SECT8,Zone Status flash CM BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "STATUS_SECT7,Zone Status flash CM BANK Sector 7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 12.--13. "STATUS_SECT6,Zone Status flash CM BANK Sector 6" "0,1,2,3"
|
|
bitfld.long 0x2 10.--11. "STATUS_SECT5,Zone Status flash CM BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "STATUS_SECT4,Zone Status flash CM BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "STATUS_SECT3,Zone Status flash CM BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "STATUS_SECT2,Zone Status flash CM BANK Sector 2" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "STATUS_SECT1,Zone Status flash CM BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "STATUS_SECT0,Zone Status flash CM BANK Sector 0" "0,1,2,3"
|
|
line.long 0x4 "SECTSTAT3,Flash Sectors Status Register 3"
|
|
bitfld.long 0x4 26.--27. "STATUS_SECT13,Zone Status flash CPU2 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "STATUS_SECT12,Zone Status flash CPU2 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "STATUS_SECT11,Zone Status flash CPU2 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "STATUS_SECT10,Zone Status flash CPU2 BANK Sector 10" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "STATUS_SECT9,Zone Status flash CPU2 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "STATUS_SECT8,Zone Status flash CPU2 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "STATUS_SECT7,Zone Status flash CPU2 BANK Sector 7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STATUS_SECT6,Zone Status flash CPU2 BANK Sector 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "STATUS_SECT5,Zone Status flash CPU2 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "STATUS_SECT4,Zone Status flash CPU2 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "STATUS_SECT3,Zone Status flash CPU2 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "STATUS_SECT2,Zone Status flash CPU2 BANK Sector 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "STATUS_SECT1,Zone Status flash CPU2 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "STATUS_SECT0,Zone Status flash CPU2 BANK Sector 0" "0,1,2,3"
|
|
line.long 0x8 "RAMSTAT1,RAM Status Register 1"
|
|
bitfld.long 0x8 18.--19. "STATUS_RAM9,Zone Status RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "STATUS_RAM8,Zone Status RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "STATUS_RAM7,Zone Status RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "STATUS_RAM6,Zone Status RAM CPU1.LS6" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "STATUS_RAM5,Zone Status RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "STATUS_RAM4,Zone Status RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "STATUS_RAM3,Zone Status RAM CPU1.LS3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "STATUS_RAM2,Zone Status RAM CPU1.LS2" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "STATUS_RAM1,Zone Status RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "STATUS_RAM0,Zone Status RAM CPU1.LS0" "0,1,2,3"
|
|
line.long 0xA "RAMSTAT2,RAM Status Register 2"
|
|
bitfld.long 0xA 30.--31. "STATUS_RAM15,Zone Status RAM CPU2 to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "STATUS_RAM14,Zone Status RAM CPU2 to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "STATUS_RAM13,Zone Status RAM CPU1 to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "STATUS_RAM12,Zone Status RAM CPU1 to CPU2 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "STATUS_RAM11,Zone Status RAM CM to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "STATUS_RAM10,Zone Status RAM CM to CPU2 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "STATUS_RAM9,Zone Status RAM CPU2 to CM MSG RAM 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 16.--17. "STATUS_RAM8,Zone Status RAM CPU2 to CM MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "STATUS_RAM7,Zone Status RAM CM to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "STATUS_RAM6,Zone Status RAM CM to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "STATUS_RAM5,Zone Status RAM CPU1 to CM MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "STATUS_RAM4,Zone Status RAM CPU1 to CM MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "STATUS_RAM1,Zone Status RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "STATUS_RAM0,Zone Status RAM CM.C0" "0,1,2,3"
|
|
line.long 0xC "RAMSTAT3,RAM Status Register 3"
|
|
bitfld.long 0xC 18.--19. "STATUS_RAM9,Zone Status RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "STATUS_RAM8,Zone Status RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "STATUS_RAM7,Zone Status RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "STATUS_RAM6,Zone Status RAM CPU2.LS6" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "STATUS_RAM5,Zone Status RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "STATUS_RAM4,Zone Status RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "STATUS_RAM3,Zone Status RAM CPU2.LS3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "STATUS_RAM2,Zone Status RAM CPU2.LS2" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "STATUS_RAM1,Zone Status RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "STATUS_RAM0,Zone Status RAM CPU2.LS0" "0,1,2,3"
|
|
line.long 0x10 "SECERRSTAT,Security Error Status Register"
|
|
bitfld.long 0x10 0. "ERR,Security Configuration load Error Status" "0,1"
|
|
group.long 0x1A++0x7
|
|
line.long 0x0 "SECERRCLR,Security Error Clear Register"
|
|
bitfld.long 0x0 0. "ERR,Clear Security Configuration Load Error Status Bit" "0,1"
|
|
line.long 0x2 "SECERRFRC,Security Error Force Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "KEY,Valid Register Write Key"
|
|
bitfld.long 0x2 0. "ERR,Set Security Configuration Load Error Status Bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "DCSM_Z1"
|
|
base d:0x5F000
|
|
rgroup.long 0x0++0x1F
|
|
line.long 0x0 "Z1_LINKPOINTER,Zone 1 Link Pointer"
|
|
hexmask.long.word 0x0 0.--13. 1. "LINKPOINTER,Zone1 LINK Pointer"
|
|
line.long 0x2 "Z1_OTPSECLOCK,Zone 1 OTP Secure Lock"
|
|
hexmask.long.byte 0x2 8.--11. 1. "CRCLOCK,Zone1 CRC Lock."
|
|
hexmask.long.byte 0x2 4.--7. 1. "PSWDLOCK,Zone1 Password Lock."
|
|
bitfld.long 0x2 0. "JTAGLOCK,JTAG Lock Status" "0,1"
|
|
line.long 0x4 "Z1_JLM_ENABLE,Zone 1 JTAGLOCK Enable Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "Z1_JLM_ENABLE,Zone1 JLM_ENABLE register."
|
|
line.long 0x6 "Z1_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long.word 0x6 0.--13. 1. "Z1_LINKPOINTERERR,Error to Resolve Z1 Link pointer from OTP loaded values"
|
|
line.long 0x8 "Z1_GPREG1,Zone 1 General Purpose Register-1"
|
|
hexmask.long 0x8 0.--31. 1. "GPREG1,General Purpose Register-1"
|
|
line.long 0xA "Z1_GPREG2,Zone 1 General Purpose Register-2"
|
|
hexmask.long 0xA 0.--31. 1. "GPREG2,General Purpose Register-2"
|
|
line.long 0xC "Z1_GPREG3,Zone 1 General Purpose Register-3"
|
|
hexmask.long 0xC 0.--31. 1. "GPREG3,General Purpose Register-3"
|
|
line.long 0xE "Z1_GPREG4,Zone 1 General Purpose Register-4"
|
|
hexmask.long 0xE 0.--31. 1. "GPREG4,General Purpose Register-4"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Z1_CSMKEY0,Zone 1 CSM Key 0"
|
|
hexmask.long 0x0 0.--31. 1. "Z1_CSMKEY0,Word0 to unlock Zone1 should match Z1_CSMPSWD0."
|
|
line.long 0x2 "Z1_CSMKEY1,Zone 1 CSM Key 1"
|
|
hexmask.long 0x2 0.--31. 1. "Z1_CSMKEY1,Word1 to unlock Zone1 should match Z1_CSMPSWD1"
|
|
line.long 0x4 "Z1_CSMKEY2,Zone 1 CSM Key 2"
|
|
hexmask.long 0x4 0.--31. 1. "Z1_CSMKEY2,Word2 to unlock Zone1 should match Z1_CSMPSWD2"
|
|
line.long 0x6 "Z1_CSMKEY3,Zone 1 CSM Key 3"
|
|
hexmask.long 0x6 0.--31. 1. "Z1_CSMKEY3,Word3 to unlock Zone1 should match Z1_CSMPSWD3"
|
|
line.long 0x8 "Z1_CR,Zone 1 CSM Control Register"
|
|
bitfld.long 0x8 31. "FORCESEC,Force Secure" "0,1"
|
|
rbitfld.long 0x8 22. "ARMED,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x8 21. "UNSECURE,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x8 20. "ALLONE,CSMPSWD All Ones" "0,1"
|
|
rbitfld.long 0x8 19. "ALLZERO,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long 0x1A++0x43
|
|
line.long 0x0 "Z1_GRABSECT1R,Zone 1 Grab Flash Status Register 1"
|
|
bitfld.long 0x0 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
line.long 0x2 "Z1_GRABSECT2R,Zone 1 Grab Flash Status Register 2"
|
|
bitfld.long 0x2 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
line.long 0x4 "Z1_GRABSECT3R,Zone 1 Grab Flash Status Register 3"
|
|
bitfld.long 0x4 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
line.long 0x6 "Z1_GRABRAM1R,Zone 1 Grab RAM Status Register 1"
|
|
bitfld.long 0x6 18.--19. "GRAB_RAM9,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GRAB_RAM8,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GRAB_RAM7,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GRAB_RAM6,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
bitfld.long 0x6 10.--11. "GRAB_RAM5,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 8.--9. "GRAB_RAM4,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GRAB_RAM3,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GRAB_RAM2,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GRAB_RAM1,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GRAB_RAM0,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
line.long 0x8 "Z1_GRABRAM2R,Zone 1 Grab RAM Status Register 2"
|
|
bitfld.long 0x8 30.--31. "GRAB_RAM15,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GRAB_RAM14,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GRAB_RAM13,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GRAB_RAM12,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GRAB_RAM11,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "GRAB_RAM10,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GRAB_RAM9,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GRAB_RAM8,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GRAB_RAM7,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GRAB_RAM6,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GRAB_RAM5,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GRAB_RAM4,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GRAB_RAM1,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GRAB_RAM0,Grab RAM CM.C0" "0,1,2,3"
|
|
line.long 0xA "Z1_GRABRAM3R,Zone 1 Grab RAM Status Register 3"
|
|
bitfld.long 0xA 18.--19. "GRAB_RAM9,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "GRAB_RAM8,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GRAB_RAM7,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GRAB_RAM6,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "GRAB_RAM5,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 8.--9. "GRAB_RAM4,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GRAB_RAM3,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GRAB_RAM2,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GRAB_RAM1,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GRAB_RAM0,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
line.long 0xC "Z1_EXEONLYSECT1R,Zone 1 Execute Only Flash Status Register 1"
|
|
bitfld.long 0xC 29. "EXEONLY_CM_SECT13,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 28. "EXEONLY_CM_SECT12,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 27. "EXEONLY_CM_SECT11,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 26. "EXEONLY_CM_SECT10,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 25. "EXEONLY_CM_SECT9,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "EXEONLY_CM_SECT8,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 23. "EXEONLY_CM_SECT7,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 22. "EXEONLY_CM_SECT6,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 21. "EXEONLY_CM_SECT5,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 20. "EXEONLY_CM_SECT4,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "EXEONLY_CM_SECT3,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 18. "EXEONLY_CM_SECT2,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 17. "EXEONLY_CM_SECT1,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 16. "EXEONLY_CM_SECT0,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 13. "EXEONLY_CPU1_SECT13,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "EXEONLY_CPU1_SECT12,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 11. "EXEONLY_CPU1_SECT11,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 10. "EXEONLY_CPU1_SECT10,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 9. "EXEONLY_CPU1_SECT9,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 8. "EXEONLY_CPU1_SECT8,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "EXEONLY_CPU1_SECT7,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 6. "EXEONLY_CPU1_SECT6,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 5. "EXEONLY_CPU1_SECT5,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 4. "EXEONLY_CPU1_SECT4,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 3. "EXEONLY_CPU1_SECT3,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EXEONLY_CPU1_SECT2,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 1. "EXEONLY_CPU1_SECT1,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 0. "EXEONLY_CPU1_SECT0,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
line.long 0xE "Z1_EXEONLYSECT2R,Zone 1 Execute Only Flash Status Register 2"
|
|
bitfld.long 0xE 13. "EXEONLY_CPU2_SECT13,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 12. "EXEONLY_CPU2_SECT12,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 11. "EXEONLY_CPU2_SECT11,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 10. "EXEONLY_CPU2_SECT10,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 9. "EXEONLY_CPU2_SECT9,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xE 8. "EXEONLY_CPU2_SECT8,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 7. "EXEONLY_CPU2_SECT7,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 6. "EXEONLY_CPU2_SECT6,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 5. "EXEONLY_CPU2_SECT5,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 4. "EXEONLY_CPU2_SECT4,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xE 3. "EXEONLY_CPU2_SECT3,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 2. "EXEONLY_CPU2_SECT2,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 1. "EXEONLY_CPU2_SECT1,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 0. "EXEONLY_CPU2_SECT0,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
line.long 0x10 "Z1_EXEONLYRAM1R,Zone 1 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x10 31. "EXEONLY_RAM31,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x10 30. "EXEONLY_RAM30,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x10 29. "EXEONLY_RAM29,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x10 28. "EXEONLY_RAM28,Execute-Only RAM CPU2.LS3" "0,1"
|
|
bitfld.long 0x10 27. "EXEONLY_RAM27,Execute-Only RAM CPU2.LS4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 26. "EXEONLY_RAM26,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x10 25. "EXEONLY_RAM25,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x10 24. "EXEONLY_RAM24,Execute-Only RAM CPU2.LS7" "0,1"
|
|
bitfld.long 0x10 23. "EXEONLY_RAM23,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x10 22. "EXEONLY_RAM22,Execute-Only RAM CPU2.D1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "EXEONLY_RAM17,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x10 16. "EXEONLY_RAM16,Execute-Only RAM on CM.C0" "0,1"
|
|
bitfld.long 0x10 9. "EXEONLY_RAM9,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x10 8. "EXEONLY_RAM8,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x10 7. "EXEONLY_RAM7,Execute-Only RAM CPU1.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "EXEONLY_RAM6,Execute-Only RAM CPU1.LS6" "0,1"
|
|
bitfld.long 0x10 5. "EXEONLY_RAM5,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x10 4. "EXEONLY_RAM4,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x10 3. "EXEONLY_RAM3,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x10 2. "EXEONLY_RAM2,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "EXEONLY_RAM1,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x10 0. "EXEONLY_RAM0,Execute-Only RAM CPU1.LS0" "0,1"
|
|
line.long 0x14 "Z1_JTAGKEY0,JTAG Unlock Key Register 0"
|
|
hexmask.long 0x14 0.--31. 1. "KEY0,JTAGKEY Bits 31:0"
|
|
line.long 0x16 "Z1_JTAGKEY1,JTAG Unlock Key Register 1"
|
|
hexmask.long 0x16 0.--31. 1. "KEY1,JTAGKEY Bits 63:32"
|
|
line.long 0x18 "Z1_JTAGKEY2,JTAG Unlock Key Register 2"
|
|
hexmask.long 0x18 0.--31. 1. "KEY2,JTAGKEY Bits 95:64"
|
|
line.long 0x1A "Z1_JTAGKEY3,JTAG Unlock Key Register 3"
|
|
hexmask.long 0x1A 0.--31. 1. "KEY3,JTAGKEY Bits 127:96"
|
|
line.long 0x1C "Z1_CMACKEY0,Secure Boot CMAC Key Status Register 0"
|
|
hexmask.long 0x1C 0.--31. 1. "KEY0,CMACKEY Bits 31:0"
|
|
line.long 0x1E "Z1_CMACKEY1,Secure Boot CMAC Key Status Register 1"
|
|
hexmask.long 0x1E 0.--31. 1. "KEY1,CMACKEY Bits 63:32"
|
|
line.long 0x20 "Z1_CMACKEY2,Secure Boot CMAC Key Status Register 2"
|
|
hexmask.long 0x20 0.--31. 1. "KEY2,CMACKEY Bits 95:64"
|
|
line.long 0x22 "Z1_CMACKEY3,Secure Boot CMAC Key Status Register 3"
|
|
hexmask.long 0x22 0.--31. 1. "KEY3,CMACKEY Bits 127:96"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "DCSM_Z2"
|
|
base d:0x5F080
|
|
rgroup.long 0x0++0x1B
|
|
line.long 0x0 "Z2_LINKPOINTER,Zone 2 Link Pointer"
|
|
hexmask.long.word 0x0 0.--13. 1. "LINKPOINTER,Zone2 LINK Pointer"
|
|
line.long 0x2 "Z2_OTPSECLOCK,Zone 2 OTP Secure Lock"
|
|
hexmask.long.byte 0x2 8.--11. 1. "CRCLOCK,Zone2 CRC Lock."
|
|
hexmask.long.byte 0x2 4.--7. 1. "PSWDLOCK,Zone2 Password Lock."
|
|
bitfld.long 0x2 0. "JTAGLOCK,JTAG Lock Status" "0,1"
|
|
line.long 0x6 "Z2_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long.word 0x6 0.--13. 1. "Z2_LINKPOINTERERR,Error to Resolve Z2 Link pointer from OTP loaded values"
|
|
line.long 0x8 "Z2_GPREG1,Zone 2 General Purpose Register-1"
|
|
hexmask.long 0x8 0.--31. 1. "GPREG1,General Purpose Register-1"
|
|
line.long 0xA "Z2_GPREG2,Zone 2 General Purpose Register-2"
|
|
hexmask.long 0xA 0.--31. 1. "GPREG2,General Purpose Register-2"
|
|
line.long 0xC "Z2_GPREG3,Zone 2 General Purpose Register-3"
|
|
hexmask.long 0xC 0.--31. 1. "GPREG3,General Purpose Register-3"
|
|
line.long 0xE "Z2_GPREG4,Zone 2 General Purpose Register-4"
|
|
hexmask.long 0xE 0.--31. 1. "GPREG4,General Purpose Register-4"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Z2_CSMKEY0,Zone 2 CSM Key 0"
|
|
hexmask.long 0x0 0.--31. 1. "Z2_CSMKEY0,Word0 to unlock Zone2 should match Z2_CSMPSWD0."
|
|
line.long 0x2 "Z2_CSMKEY1,Zone 2 CSM Key 1"
|
|
hexmask.long 0x2 0.--31. 1. "Z2_CSMKEY1,Word1 to unlock Zone2 should match Z2_CSMPSWD1"
|
|
line.long 0x4 "Z2_CSMKEY2,Zone 2 CSM Key 2"
|
|
hexmask.long 0x4 0.--31. 1. "Z2_CSMKEY2,Word2 to unlock Zone2 should match Z2_CSMPSWD2"
|
|
line.long 0x6 "Z2_CSMKEY3,Zone 2 CSM Key 3"
|
|
hexmask.long 0x6 0.--31. 1. "Z2_CSMKEY3,Word3 to unlock Zone2 should match Z2_CSMPSWD3"
|
|
line.long 0x8 "Z2_CR,Zone 2 CSM Control Register"
|
|
bitfld.long 0x8 31. "FORCESEC,Force Secure" "0,1"
|
|
rbitfld.long 0x8 22. "ARMED,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x8 21. "UNSECURE,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x8 20. "ALLONE,CSMPSWD All Ones" "0,1"
|
|
rbitfld.long 0x8 19. "ALLZERO,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long 0x1A++0x23
|
|
line.long 0x0 "Z2_GRABSECT1R,Zone 2 Grab Flash Status Register 1"
|
|
bitfld.long 0x0 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
line.long 0x2 "Z2_GRABSECT2R,Zone 2 Grab Flash Status Register 2"
|
|
bitfld.long 0x2 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
line.long 0x4 "Z2_GRABSECT3R,Zone 2 Grab Flash Status Register 3"
|
|
bitfld.long 0x4 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
line.long 0x6 "Z2_GRABRAM1R,Zone 2 Grab RAM Status Register 1"
|
|
bitfld.long 0x6 18.--19. "GRAB_RAM9,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GRAB_RAM8,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GRAB_RAM7,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GRAB_RAM6,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
bitfld.long 0x6 10.--11. "GRAB_RAM5,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 8.--9. "GRAB_RAM4,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GRAB_RAM3,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GRAB_RAM2,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GRAB_RAM1,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GRAB_RAM0,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
line.long 0x8 "Z2_GRABRAM2R,Zone 2 Grab RAM Status Register 2"
|
|
bitfld.long 0x8 30.--31. "GRAB_RAM15,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GRAB_RAM14,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GRAB_RAM13,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GRAB_RAM12,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GRAB_RAM11,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "GRAB_RAM10,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GRAB_RAM9,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GRAB_RAM8,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GRAB_RAM7,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GRAB_RAM6,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GRAB_RAM5,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GRAB_RAM4,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GRAB_RAM1,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GRAB_RAM0,Grab RAM CM.C0" "0,1,2,3"
|
|
line.long 0xA "Z2_GRABRAM3R,Zone 2 Grab RAM Status Register 3"
|
|
bitfld.long 0xA 18.--19. "GRAB_RAM9,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "GRAB_RAM8,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GRAB_RAM7,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GRAB_RAM6,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "GRAB_RAM5,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 8.--9. "GRAB_RAM4,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GRAB_RAM3,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GRAB_RAM2,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GRAB_RAM1,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GRAB_RAM0,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
line.long 0xC "Z2_EXEONLYSECT1R,Zone 2 Execute Only Flash Status Register 1"
|
|
bitfld.long 0xC 29. "EXEONLY_CM_SECT13,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 28. "EXEONLY_CM_SECT12,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 27. "EXEONLY_CM_SECT11,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 26. "EXEONLY_CM_SECT10,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 25. "EXEONLY_CM_SECT9,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "EXEONLY_CM_SECT8,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 23. "EXEONLY_CM_SECT7,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 22. "EXEONLY_CM_SECT6,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 21. "EXEONLY_CM_SECT5,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 20. "EXEONLY_CM_SECT4,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "EXEONLY_CM_SECT3,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 18. "EXEONLY_CM_SECT2,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 17. "EXEONLY_CM_SECT1,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 16. "EXEONLY_CM_SECT0,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0xC 13. "EXEONLY_CPU1_SECT13,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "EXEONLY_CPU1_SECT12,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 11. "EXEONLY_CPU1_SECT11,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 10. "EXEONLY_CPU1_SECT10,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 9. "EXEONLY_CPU1_SECT9,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 8. "EXEONLY_CPU1_SECT8,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "EXEONLY_CPU1_SECT7,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 6. "EXEONLY_CPU1_SECT6,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 5. "EXEONLY_CPU1_SECT5,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 4. "EXEONLY_CPU1_SECT4,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 3. "EXEONLY_CPU1_SECT3,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "EXEONLY_CPU1_SECT2,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 1. "EXEONLY_CPU1_SECT1,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0xC 0. "EXEONLY_CPU1_SECT0,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
line.long 0xE "Z2_EXEONLYSECT2R,Zone 2 Execute Only Flash Status Register 2"
|
|
bitfld.long 0xE 13. "EXEONLY_CPU2_SECT13,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 12. "EXEONLY_CPU2_SECT12,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 11. "EXEONLY_CPU2_SECT11,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 10. "EXEONLY_CPU2_SECT10,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 9. "EXEONLY_CPU2_SECT9,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xE 8. "EXEONLY_CPU2_SECT8,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 7. "EXEONLY_CPU2_SECT7,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 6. "EXEONLY_CPU2_SECT6,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 5. "EXEONLY_CPU2_SECT5,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 4. "EXEONLY_CPU2_SECT4,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0xE 3. "EXEONLY_CPU2_SECT3,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 2. "EXEONLY_CPU2_SECT2,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 1. "EXEONLY_CPU2_SECT1,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0xE 0. "EXEONLY_CPU2_SECT0,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
line.long 0x10 "Z2_EXEONLYRAM1R,Zone 2 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x10 31. "EXEONLY_RAM31,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x10 30. "EXEONLY_RAM30,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x10 29. "EXEONLY_RAM29,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x10 28. "EXEONLY_RAM28,Execute-Only RAM CPU2.LS3" "0,1"
|
|
bitfld.long 0x10 27. "EXEONLY_RAM27,Execute-Only RAM CPU2.LS4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 26. "EXEONLY_RAM26,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x10 25. "EXEONLY_RAM25,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x10 24. "EXEONLY_RAM24,Execute-Only RAM CPU2.LS7" "0,1"
|
|
bitfld.long 0x10 23. "EXEONLY_RAM23,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x10 22. "EXEONLY_RAM22,Execute-Only RAM CPU2.D1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "EXEONLY_RAM17,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x10 16. "EXEONLY_RAM16,Execute-Only RAM on CM.C0" "0,1"
|
|
bitfld.long 0x10 9. "EXEONLY_RAM9,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x10 8. "EXEONLY_RAM8,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x10 7. "EXEONLY_RAM7,Execute-Only RAM CPU1.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "EXEONLY_RAM6,Execute-Only RAM CPU1.LS6" "0,1"
|
|
bitfld.long 0x10 5. "EXEONLY_RAM5,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x10 4. "EXEONLY_RAM4,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x10 3. "EXEONLY_RAM3,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x10 2. "EXEONLY_RAM2,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "EXEONLY_RAM1,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x10 0. "EXEONLY_RAM0,Execute-Only RAM CPU1.LS0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "DCSM_Common"
|
|
base d:0x40085180
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLSEM,Flash Wrapper Semaphore Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Semaphore Key"
|
|
bitfld.long 0x0 0.--1. "SEM,Flash Semaphore Bit" "0,1,2,3"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "SECTSTAT1,Flash Sectors Status Register 1"
|
|
bitfld.long 0x0 26.--27. "STATUS_SECT13,Zone Status flash CPU1 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "STATUS_SECT12,Zone Status flash CPU1 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "STATUS_SECT11,Zone Status flash CPU1 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "STATUS_SECT10,Zone Status flash CPU1 BANK Sector 10" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "STATUS_SECT9,Zone Status flash CPU1 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "STATUS_SECT8,Zone Status flash CPU1 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "STATUS_SECT7,Zone Status flash CPU1 BANK Sector 7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "STATUS_SECT6,Zone Status flash CPU1 BANK Sector 6" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "STATUS_SECT5,Zone Status flash CPU1 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "STATUS_SECT4,Zone Status flash CPU1 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "STATUS_SECT3,Zone Status flash CPU1 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "STATUS_SECT2,Zone Status flash CPU1 BANK Sector 2" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "STATUS_SECT1,Zone Status flash CPU1 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "STATUS_SECT0,Zone Status flash CPU1 BANK Sector 0" "0,1,2,3"
|
|
line.long 0x4 "SECTSTAT2,Flash Sectors Status Register 2"
|
|
bitfld.long 0x4 26.--27. "STATUS_SECT13,Zone Status flash CM BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "STATUS_SECT12,Zone Status flash CM BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "STATUS_SECT11,Zone Status flash CM BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "STATUS_SECT10,Zone Status flash CM BANK Sector 10" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "STATUS_SECT9,Zone Status flash CM BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "STATUS_SECT8,Zone Status flash CM BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "STATUS_SECT7,Zone Status flash CM BANK Sector 7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STATUS_SECT6,Zone Status flash CM BANK Sector 6" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "STATUS_SECT5,Zone Status flash CM BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "STATUS_SECT4,Zone Status flash CM BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "STATUS_SECT3,Zone Status flash CM BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "STATUS_SECT2,Zone Status flash CM BANK Sector 2" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "STATUS_SECT1,Zone Status flash CM BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "STATUS_SECT0,Zone Status flash CM BANK Sector 0" "0,1,2,3"
|
|
line.long 0x8 "SECTSTAT3,Flash Sectors Status Register 3"
|
|
bitfld.long 0x8 26.--27. "STATUS_SECT13,Zone Status flash CPU2 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "STATUS_SECT12,Zone Status flash CPU2 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "STATUS_SECT11,Zone Status flash CPU2 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "STATUS_SECT10,Zone Status flash CPU2 BANK Sector 10" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "STATUS_SECT9,Zone Status flash CPU2 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "STATUS_SECT8,Zone Status flash CPU2 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "STATUS_SECT7,Zone Status flash CPU2 BANK Sector 7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12.--13. "STATUS_SECT6,Zone Status flash CPU2 BANK Sector 6" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "STATUS_SECT5,Zone Status flash CPU2 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "STATUS_SECT4,Zone Status flash CPU2 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "STATUS_SECT3,Zone Status flash CPU2 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "STATUS_SECT2,Zone Status flash CPU2 BANK Sector 2" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "STATUS_SECT1,Zone Status flash CPU2 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "STATUS_SECT0,Zone Status flash CPU2 BANK Sector 0" "0,1,2,3"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "RAMSTAT1,RAM Status Register 1"
|
|
bitfld.long 0x0 18.--19. "STATUS_RAM9,Zone Status RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "STATUS_RAM8,Zone Status RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "STATUS_RAM7,Zone Status RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "STATUS_RAM6,Zone Status RAM CPU1.LS6" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "STATUS_RAM5,Zone Status RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "STATUS_RAM4,Zone Status RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "STATUS_RAM3,Zone Status RAM CPU1.LS3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "STATUS_RAM2,Zone Status RAM CPU1.LS2" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "STATUS_RAM1,Zone Status RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "STATUS_RAM0,Zone Status RAM CPU1.LS0" "0,1,2,3"
|
|
line.long 0x4 "RAMSTAT2,RAM Status Register 2"
|
|
bitfld.long 0x4 30.--31. "STATUS_RAM15,Zone Status RAM CPU2 to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "STATUS_RAM14,Zone Status RAM CPU2 to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "STATUS_RAM13,Zone Status RAM CPU1 to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "STATUS_RAM12,Zone Status RAM CPU1 to CPU2 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "STATUS_RAM11,Zone Status RAM CM to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "STATUS_RAM10,Zone Status RAM CM to CPU2 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "STATUS_RAM9,Zone Status RAM CPU2 to CM MSG RAM 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "STATUS_RAM8,Zone Status RAM CPU2 to CM MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "STATUS_RAM7,Zone Status RAM CM to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "STATUS_RAM6,Zone Status RAM CM to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "STATUS_RAM5,Zone Status RAM CPU1 to CM MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "STATUS_RAM4,Zone Status RAM CPU1 to CM MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "STATUS_RAM1,Zone Status RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "STATUS_RAM0,Zone Status RAM CM.C0" "0,1,2,3"
|
|
line.long 0x8 "RAMSTAT3,RAM Status Register 3"
|
|
bitfld.long 0x8 18.--19. "STATUS_RAM9,Zone Status RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "STATUS_RAM8,Zone Status RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "STATUS_RAM7,Zone Status RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "STATUS_RAM6,Zone Status RAM CPU2.LS6" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "STATUS_RAM5,Zone Status RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "STATUS_RAM4,Zone Status RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "STATUS_RAM3,Zone Status RAM CPU2.LS3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "STATUS_RAM2,Zone Status RAM CPU2.LS2" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "STATUS_RAM1,Zone Status RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "STATUS_RAM0,Zone Status RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SECERRSTAT,Security Error Status Register"
|
|
bitfld.long 0x0 0. "ERR,Security Configuration load Error Status" "0,1"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "SECERRCLR,Security Error Clear Register"
|
|
bitfld.long 0x0 0. "ERR,Clear Security Configuration Load Error Status Bit" "0,1"
|
|
line.long 0x4 "SECERRFRC,Security Error Force Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,Valid Register Write Key"
|
|
bitfld.long 0x4 0. "ERR,Set Security Configuration Load Error Status Bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "DCSM_Z1"
|
|
base d:0x40085000
|
|
rgroup.long 0x0++0x1F
|
|
line.long 0x0 "Z1_LINKPOINTER,Zone 1 Link Pointer"
|
|
hexmask.long.word 0x0 0.--13. 1. "LINKPOINTER,Zone1 LINK Pointer"
|
|
line.long 0x4 "Z1_OTPSECLOCK,Zone 1 OTP Secure Lock"
|
|
hexmask.long.byte 0x4 8.--11. 1. "CRCLOCK,Zone1 CRC Lock."
|
|
hexmask.long.byte 0x4 4.--7. 1. "PSWDLOCK,Zone1 Password Lock."
|
|
bitfld.long 0x4 0. "JTAGLOCK,JTAG Lock Status" "0,1"
|
|
line.long 0x8 "Z1_JLM_ENABLE,Zone 1 JTAGLOCK Enable Register"
|
|
hexmask.long.byte 0x8 0.--3. 1. "Z1_JLM_ENABLE,Zone1 JLM_ENABLE register."
|
|
line.long 0xC "Z1_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long.word 0xC 0.--13. 1. "Z1_LINKPOINTERERR,Error to Resolve Z1 Link pointer from OTP loaded values"
|
|
line.long 0x10 "Z1_GPREG1,Zone 1 General Purpose Register-1"
|
|
hexmask.long 0x10 0.--31. 1. "GPREG1,General Purpose Register-1"
|
|
line.long 0x14 "Z1_GPREG2,Zone 1 General Purpose Register-2"
|
|
hexmask.long 0x14 0.--31. 1. "GPREG2,General Purpose Register-2"
|
|
line.long 0x18 "Z1_GPREG3,Zone 1 General Purpose Register-3"
|
|
hexmask.long 0x18 0.--31. 1. "GPREG3,General Purpose Register-3"
|
|
line.long 0x1C "Z1_GPREG4,Zone 1 General Purpose Register-4"
|
|
hexmask.long 0x1C 0.--31. 1. "GPREG4,General Purpose Register-4"
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "Z1_CSMKEY0,Zone 1 CSM Key 0"
|
|
hexmask.long 0x0 0.--31. 1. "Z1_CSMKEY0,Word0 to unlock Zone1 should match Z1_CSMPSWD0."
|
|
line.long 0x4 "Z1_CSMKEY1,Zone 1 CSM Key 1"
|
|
hexmask.long 0x4 0.--31. 1. "Z1_CSMKEY1,Word1 to unlock Zone1 should match Z1_CSMPSWD1"
|
|
line.long 0x8 "Z1_CSMKEY2,Zone 1 CSM Key 2"
|
|
hexmask.long 0x8 0.--31. 1. "Z1_CSMKEY2,Word2 to unlock Zone1 should match Z1_CSMPSWD2"
|
|
line.long 0xC "Z1_CSMKEY3,Zone 1 CSM Key 3"
|
|
hexmask.long 0xC 0.--31. 1. "Z1_CSMKEY3,Word3 to unlock Zone1 should match Z1_CSMPSWD3"
|
|
line.long 0x10 "Z1_CR,Zone 1 CSM Control Register"
|
|
bitfld.long 0x10 31. "FORCESEC,Force Secure" "0,1"
|
|
rbitfld.long 0x10 22. "ARMED,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x10 21. "UNSECURE,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x10 20. "ALLONE,CSMPSWD All Ones" "0,1"
|
|
rbitfld.long 0x10 19. "ALLZERO,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long 0x34++0x23
|
|
line.long 0x0 "Z1_GRABSECT1R,Zone 1 Grab Flash Status Register 1"
|
|
bitfld.long 0x0 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
line.long 0x4 "Z1_GRABSECT2R,Zone 1 Grab Flash Status Register 2"
|
|
bitfld.long 0x4 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
line.long 0x8 "Z1_GRABSECT3R,Zone 1 Grab Flash Status Register 3"
|
|
bitfld.long 0x8 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
line.long 0xC "Z1_GRABRAM1R,Zone 1 Grab RAM Status Register 1"
|
|
bitfld.long 0xC 18.--19. "GRAB_RAM9,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "GRAB_RAM8,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "GRAB_RAM7,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "GRAB_RAM6,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "GRAB_RAM5,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "GRAB_RAM4,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "GRAB_RAM3,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "GRAB_RAM2,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "GRAB_RAM1,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "GRAB_RAM0,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
line.long 0x10 "Z1_GRABRAM2R,Zone 1 Grab RAM Status Register 2"
|
|
bitfld.long 0x10 30.--31. "GRAB_RAM15,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "GRAB_RAM14,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "GRAB_RAM13,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "GRAB_RAM12,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "GRAB_RAM11,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 20.--21. "GRAB_RAM10,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "GRAB_RAM9,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "GRAB_RAM8,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "GRAB_RAM7,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "GRAB_RAM6,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "GRAB_RAM5,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "GRAB_RAM4,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "GRAB_RAM1,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "GRAB_RAM0,Grab RAM CM.C0" "0,1,2,3"
|
|
line.long 0x14 "Z1_GRABRAM3R,Zone 1 Grab RAM Status Register 3"
|
|
bitfld.long 0x14 18.--19. "GRAB_RAM9,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "GRAB_RAM8,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "GRAB_RAM7,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "GRAB_RAM6,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "GRAB_RAM5,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "GRAB_RAM4,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "GRAB_RAM3,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "GRAB_RAM2,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "GRAB_RAM1,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "GRAB_RAM0,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
line.long 0x18 "Z1_EXEONLYSECT1R,Zone 1 Execute Only Flash Status Register 1"
|
|
bitfld.long 0x18 29. "EXEONLY_CM_SECT13,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 28. "EXEONLY_CM_SECT12,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 27. "EXEONLY_CM_SECT11,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 26. "EXEONLY_CM_SECT10,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 25. "EXEONLY_CM_SECT9,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "EXEONLY_CM_SECT8,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 23. "EXEONLY_CM_SECT7,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 22. "EXEONLY_CM_SECT6,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 21. "EXEONLY_CM_SECT5,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 20. "EXEONLY_CM_SECT4,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "EXEONLY_CM_SECT3,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 18. "EXEONLY_CM_SECT2,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 17. "EXEONLY_CM_SECT1,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 16. "EXEONLY_CM_SECT0,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 13. "EXEONLY_CPU1_SECT13,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "EXEONLY_CPU1_SECT12,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 11. "EXEONLY_CPU1_SECT11,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 10. "EXEONLY_CPU1_SECT10,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 9. "EXEONLY_CPU1_SECT9,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 8. "EXEONLY_CPU1_SECT8,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "EXEONLY_CPU1_SECT7,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 6. "EXEONLY_CPU1_SECT6,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 5. "EXEONLY_CPU1_SECT5,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 4. "EXEONLY_CPU1_SECT4,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 3. "EXEONLY_CPU1_SECT3,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "EXEONLY_CPU1_SECT2,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 1. "EXEONLY_CPU1_SECT1,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 0. "EXEONLY_CPU1_SECT0,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
line.long 0x1C "Z1_EXEONLYSECT2R,Zone 1 Execute Only Flash Status Register 2"
|
|
bitfld.long 0x1C 13. "EXEONLY_CPU2_SECT13,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 12. "EXEONLY_CPU2_SECT12,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 11. "EXEONLY_CPU2_SECT11,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 10. "EXEONLY_CPU2_SECT10,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 9. "EXEONLY_CPU2_SECT9,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "EXEONLY_CPU2_SECT8,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 7. "EXEONLY_CPU2_SECT7,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 6. "EXEONLY_CPU2_SECT6,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 5. "EXEONLY_CPU2_SECT5,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 4. "EXEONLY_CPU2_SECT4,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "EXEONLY_CPU2_SECT3,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 2. "EXEONLY_CPU2_SECT2,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 1. "EXEONLY_CPU2_SECT1,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 0. "EXEONLY_CPU2_SECT0,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
line.long 0x20 "Z1_EXEONLYRAM1R,Zone 1 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x20 31. "EXEONLY_RAM31,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x20 30. "EXEONLY_RAM30,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x20 29. "EXEONLY_RAM29,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x20 28. "EXEONLY_RAM28,Execute-Only RAM CPU2.LS3" "0,1"
|
|
bitfld.long 0x20 27. "EXEONLY_RAM27,Execute-Only RAM CPU2.LS4" "0,1"
|
|
newline
|
|
bitfld.long 0x20 26. "EXEONLY_RAM26,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x20 25. "EXEONLY_RAM25,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x20 24. "EXEONLY_RAM24,Execute-Only RAM CPU2.LS7" "0,1"
|
|
bitfld.long 0x20 23. "EXEONLY_RAM23,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x20 22. "EXEONLY_RAM22,Execute-Only RAM CPU2.D1" "0,1"
|
|
newline
|
|
bitfld.long 0x20 17. "EXEONLY_RAM17,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x20 16. "EXEONLY_RAM16,Execute-Only RAM on CM.C0" "0,1"
|
|
bitfld.long 0x20 9. "EXEONLY_RAM9,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x20 8. "EXEONLY_RAM8,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x20 7. "EXEONLY_RAM7,Execute-Only RAM CPU1.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "EXEONLY_RAM6,Execute-Only RAM CPU1.LS6" "0,1"
|
|
bitfld.long 0x20 5. "EXEONLY_RAM5,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x20 4. "EXEONLY_RAM4,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x20 3. "EXEONLY_RAM3,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x20 2. "EXEONLY_RAM2,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "EXEONLY_RAM1,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x20 0. "EXEONLY_RAM0,Execute-Only RAM CPU1.LS0" "0,1"
|
|
rgroup.long 0x5C++0x1F
|
|
line.long 0x0 "Z1_JTAGKEY0,JTAG Unlock Key Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY0,JTAGKEY Bits 31:0"
|
|
line.long 0x4 "Z1_JTAGKEY1,JTAG Unlock Key Register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY1,JTAGKEY Bits 63:32"
|
|
line.long 0x8 "Z1_JTAGKEY2,JTAG Unlock Key Register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY2,JTAGKEY Bits 95:64"
|
|
line.long 0xC "Z1_JTAGKEY3,JTAG Unlock Key Register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY3,JTAGKEY Bits 127:96"
|
|
line.long 0x10 "Z1_CMACKEY0,Secure Boot CMAC Key Status Register 0"
|
|
hexmask.long 0x10 0.--31. 1. "KEY0,CMACKEY Bits 31:0"
|
|
line.long 0x14 "Z1_CMACKEY1,Secure Boot CMAC Key Status Register 1"
|
|
hexmask.long 0x14 0.--31. 1. "KEY1,CMACKEY Bits 63:32"
|
|
line.long 0x18 "Z1_CMACKEY2,Secure Boot CMAC Key Status Register 2"
|
|
hexmask.long 0x18 0.--31. 1. "KEY2,CMACKEY Bits 95:64"
|
|
line.long 0x1C "Z1_CMACKEY3,Secure Boot CMAC Key Status Register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "KEY3,CMACKEY Bits 127:96"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "DCSM_Z2"
|
|
base d:0x40085100
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Z2_LINKPOINTER,Zone 2 Link Pointer"
|
|
hexmask.long.word 0x0 0.--13. 1. "LINKPOINTER,Zone2 LINK Pointer"
|
|
line.long 0x4 "Z2_OTPSECLOCK,Zone 2 OTP Secure Lock"
|
|
hexmask.long.byte 0x4 8.--11. 1. "CRCLOCK,Zone2 CRC Lock."
|
|
hexmask.long.byte 0x4 4.--7. 1. "PSWDLOCK,Zone2 Password Lock."
|
|
bitfld.long 0x4 0. "JTAGLOCK,JTAG Lock Status" "0,1"
|
|
rgroup.long 0xC++0x13
|
|
line.long 0x0 "Z2_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long.word 0x0 0.--13. 1. "Z2_LINKPOINTERERR,Error to Resolve Z2 Link pointer from OTP loaded values"
|
|
line.long 0x4 "Z2_GPREG1,Zone 2 General Purpose Register-1"
|
|
hexmask.long 0x4 0.--31. 1. "GPREG1,General Purpose Register-1"
|
|
line.long 0x8 "Z2_GPREG2,Zone 2 General Purpose Register-2"
|
|
hexmask.long 0x8 0.--31. 1. "GPREG2,General Purpose Register-2"
|
|
line.long 0xC "Z2_GPREG3,Zone 2 General Purpose Register-3"
|
|
hexmask.long 0xC 0.--31. 1. "GPREG3,General Purpose Register-3"
|
|
line.long 0x10 "Z2_GPREG4,Zone 2 General Purpose Register-4"
|
|
hexmask.long 0x10 0.--31. 1. "GPREG4,General Purpose Register-4"
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "Z2_CSMKEY0,Zone 2 CSM Key 0"
|
|
hexmask.long 0x0 0.--31. 1. "Z2_CSMKEY0,Word0 to unlock Zone2 should match Z2_CSMPSWD0."
|
|
line.long 0x4 "Z2_CSMKEY1,Zone 2 CSM Key 1"
|
|
hexmask.long 0x4 0.--31. 1. "Z2_CSMKEY1,Word1 to unlock Zone2 should match Z2_CSMPSWD1"
|
|
line.long 0x8 "Z2_CSMKEY2,Zone 2 CSM Key 2"
|
|
hexmask.long 0x8 0.--31. 1. "Z2_CSMKEY2,Word2 to unlock Zone2 should match Z2_CSMPSWD2"
|
|
line.long 0xC "Z2_CSMKEY3,Zone 2 CSM Key 3"
|
|
hexmask.long 0xC 0.--31. 1. "Z2_CSMKEY3,Word3 to unlock Zone2 should match Z2_CSMPSWD3"
|
|
line.long 0x10 "Z2_CR,Zone 2 CSM Control Register"
|
|
bitfld.long 0x10 31. "FORCESEC,Force Secure" "0,1"
|
|
rbitfld.long 0x10 22. "ARMED,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x10 21. "UNSECURE,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x10 20. "ALLONE,CSMPSWD All Ones" "0,1"
|
|
rbitfld.long 0x10 19. "ALLZERO,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long 0x34++0x23
|
|
line.long 0x0 "Z2_GRABSECT1R,Zone 2 Grab Flash Status Register 1"
|
|
bitfld.long 0x0 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
line.long 0x4 "Z2_GRABSECT2R,Zone 2 Grab Flash Status Register 2"
|
|
bitfld.long 0x4 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
line.long 0x8 "Z2_GRABSECT3R,Zone 2 Grab Flash Status Register 3"
|
|
bitfld.long 0x8 26.--27. "GRAB_SECT13,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GRAB_SECT12,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GRAB_SECT11,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GRAB_SECT10,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GRAB_SECT9,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "GRAB_SECT8,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GRAB_SECT7,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GRAB_SECT6,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "GRAB_SECT5,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GRAB_SECT4,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "GRAB_SECT3,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GRAB_SECT2,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GRAB_SECT1,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GRAB_SECT0,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
line.long 0xC "Z2_GRABRAM1R,Zone 2 Grab RAM Status Register 1"
|
|
bitfld.long 0xC 18.--19. "GRAB_RAM9,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "GRAB_RAM8,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "GRAB_RAM7,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "GRAB_RAM6,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "GRAB_RAM5,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "GRAB_RAM4,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "GRAB_RAM3,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "GRAB_RAM2,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "GRAB_RAM1,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "GRAB_RAM0,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
line.long 0x10 "Z2_GRABRAM2R,Zone 2 Grab RAM Status Register 2"
|
|
bitfld.long 0x10 30.--31. "GRAB_RAM15,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "GRAB_RAM14,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "GRAB_RAM13,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "GRAB_RAM12,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "GRAB_RAM11,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 20.--21. "GRAB_RAM10,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "GRAB_RAM9,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "GRAB_RAM8,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "GRAB_RAM7,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "GRAB_RAM6,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--11. "GRAB_RAM5,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "GRAB_RAM4,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "GRAB_RAM1,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "GRAB_RAM0,Grab RAM CM.C0" "0,1,2,3"
|
|
line.long 0x14 "Z2_GRABRAM3R,Zone 2 Grab RAM Status Register 3"
|
|
bitfld.long 0x14 18.--19. "GRAB_RAM9,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "GRAB_RAM8,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "GRAB_RAM7,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "GRAB_RAM6,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "GRAB_RAM5,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "GRAB_RAM4,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "GRAB_RAM3,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "GRAB_RAM2,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "GRAB_RAM1,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "GRAB_RAM0,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
line.long 0x18 "Z2_EXEONLYSECT1R,Zone 2 Execute Only Flash Status Register 1"
|
|
bitfld.long 0x18 29. "EXEONLY_CM_SECT13,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 28. "EXEONLY_CM_SECT12,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 27. "EXEONLY_CM_SECT11,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 26. "EXEONLY_CM_SECT10,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 25. "EXEONLY_CM_SECT9,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "EXEONLY_CM_SECT8,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 23. "EXEONLY_CM_SECT7,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 22. "EXEONLY_CM_SECT6,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 21. "EXEONLY_CM_SECT5,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 20. "EXEONLY_CM_SECT4,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "EXEONLY_CM_SECT3,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 18. "EXEONLY_CM_SECT2,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 17. "EXEONLY_CM_SECT1,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 16. "EXEONLY_CM_SECT0,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0x18 13. "EXEONLY_CPU1_SECT13,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "EXEONLY_CPU1_SECT12,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 11. "EXEONLY_CPU1_SECT11,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 10. "EXEONLY_CPU1_SECT10,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 9. "EXEONLY_CPU1_SECT9,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 8. "EXEONLY_CPU1_SECT8,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "EXEONLY_CPU1_SECT7,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 6. "EXEONLY_CPU1_SECT6,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 5. "EXEONLY_CPU1_SECT5,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 4. "EXEONLY_CPU1_SECT4,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 3. "EXEONLY_CPU1_SECT3,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "EXEONLY_CPU1_SECT2,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 1. "EXEONLY_CPU1_SECT1,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x18 0. "EXEONLY_CPU1_SECT0,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
line.long 0x1C "Z2_EXEONLYSECT2R,Zone 2 Execute Only Flash Status Register 2"
|
|
bitfld.long 0x1C 13. "EXEONLY_CPU2_SECT13,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 12. "EXEONLY_CPU2_SECT12,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 11. "EXEONLY_CPU2_SECT11,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 10. "EXEONLY_CPU2_SECT10,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 9. "EXEONLY_CPU2_SECT9,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "EXEONLY_CPU2_SECT8,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 7. "EXEONLY_CPU2_SECT7,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 6. "EXEONLY_CPU2_SECT6,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 5. "EXEONLY_CPU2_SECT5,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 4. "EXEONLY_CPU2_SECT4,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "EXEONLY_CPU2_SECT3,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 2. "EXEONLY_CPU2_SECT2,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 1. "EXEONLY_CPU2_SECT1,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x1C 0. "EXEONLY_CPU2_SECT0,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
line.long 0x20 "Z2_EXEONLYRAM1R,Zone 2 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x20 31. "EXEONLY_RAM31,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x20 30. "EXEONLY_RAM30,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x20 29. "EXEONLY_RAM29,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x20 28. "EXEONLY_RAM28,Execute-Only RAM CPU2.LS3" "0,1"
|
|
bitfld.long 0x20 27. "EXEONLY_RAM27,Execute-Only RAM CPU2.LS4" "0,1"
|
|
newline
|
|
bitfld.long 0x20 26. "EXEONLY_RAM26,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x20 25. "EXEONLY_RAM25,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x20 24. "EXEONLY_RAM24,Execute-Only RAM CPU2.LS7" "0,1"
|
|
bitfld.long 0x20 23. "EXEONLY_RAM23,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x20 22. "EXEONLY_RAM22,Execute-Only RAM CPU2.D1" "0,1"
|
|
newline
|
|
bitfld.long 0x20 17. "EXEONLY_RAM17,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x20 16. "EXEONLY_RAM16,Execute-Only RAM on CM.C0" "0,1"
|
|
bitfld.long 0x20 9. "EXEONLY_RAM9,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x20 8. "EXEONLY_RAM8,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x20 7. "EXEONLY_RAM7,Execute-Only RAM CPU1.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "EXEONLY_RAM6,Execute-Only RAM CPU1.LS6" "0,1"
|
|
bitfld.long 0x20 5. "EXEONLY_RAM5,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x20 4. "EXEONLY_RAM4,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x20 3. "EXEONLY_RAM3,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x20 2. "EXEONLY_RAM2,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "EXEONLY_RAM1,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x20 0. "EXEONLY_RAM0,Execute-Only RAM CPU1.LS0" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "DMA (Direct Memory Access)"
|
|
base d:0x0
|
|
tree "DMA_CHANNEL1"
|
|
base d:0x1020
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "MODE,Mode Register"
|
|
bitfld.word 0x0 15. "CHINTE,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x0 14. "DATASIZE,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x0 11. "CONTINUOUS,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x0 10. "ONESHOT,One Shot Mode Bit" "0,1"
|
|
bitfld.word 0x0 9. "CHINTMODE,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x0 8. "PERINTE,Peripheral Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "OVRINTE,Overflow Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "PERINTSEL,Peripheral Interrupt and Sync Select"
|
|
line.word 0x1 "CONTROL,Control Register"
|
|
rbitfld.word 0x1 14. "OVRFLG,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x1 13. "RUNSTS,Run Status Bit" "0,1"
|
|
rbitfld.word 0x1 12. "BURSTSTS,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x1 11. "TRANSFERSTS,Transfer Status Bit" "0,1"
|
|
rbitfld.word 0x1 8. "PERINTFLG,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x1 7. "ERRCLR,Error Clear Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "PERINTCLR,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x1 3. "PERINTFRC,Interrupt Force Bit" "0,1"
|
|
bitfld.word 0x1 2. "SOFTRESET,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x1 1. "HALT,Halt Bit" "0,1"
|
|
bitfld.word 0x1 0. "RUN,Run Bit" "0,1"
|
|
line.word 0x2 "BURST_SIZE,Burst Size Register"
|
|
hexmask.word.byte 0x2 0.--4. 1. "BURSTSIZE,Burst Transfer Size"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "BURST_COUNT,Burst Count Register"
|
|
hexmask.word.byte 0x0 0.--4. 1. "BURSTCOUNT,Burst Transfer Size"
|
|
group.word 0x4++0x17
|
|
line.word 0x0 "SRC_BURST_STEP,Source Burst Step Register"
|
|
hexmask.word 0x0 0.--15. 1. "SRCBURSTSTEP,Source post-increment/decrement step size of a burst"
|
|
line.word 0x1 "DST_BURST_STEP,Destination Burst Step Register"
|
|
hexmask.word 0x1 0.--15. 1. "DSTBURSTSTEP,Destination post-increment/decrement step size of a burst"
|
|
line.word 0x2 "TRANSFER_SIZE,Transfer Size Register"
|
|
hexmask.word 0x2 0.--15. 1. "TRANSFERSIZE,These bits specify the number of bursts to transfer:"
|
|
line.word 0x3 "TRANSFER_COUNT,Transfer Count Register"
|
|
hexmask.word 0x3 0.--15. 1. "TRANSFERCOUNT,These bits specify the current transfer counter value:"
|
|
line.word 0x4 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
hexmask.word 0x4 0.--15. 1. "SRCTRANSFERSTEP,Source post-increment/decrement step size of a transfer"
|
|
line.word 0x5 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
hexmask.word 0x5 0.--15. 1. "DSTTRANSFERSTEP,Destination post-increment/decrement step size of a transfer"
|
|
line.word 0x6 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
hexmask.word 0x6 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0x7 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
hexmask.word 0x7 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0x8 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
hexmask.word 0x8 0.--15. 1. "WRAPSTEP,Source post-increment/decrement step size for a wrap"
|
|
line.word 0x9 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
hexmask.word 0x9 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0xA "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
hexmask.word 0xA 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0xB "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
hexmask.word 0xB 0.--15. 1. "WRAPSTEP,Destination post-increment/decrement step size for a wrap"
|
|
group.long 0x10++0x1F
|
|
line.long 0x0 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
hexmask.long 0x0 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x2 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
hexmask.long 0x2 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x4 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
hexmask.long 0x4 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x6 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
hexmask.long 0x6 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x8 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
hexmask.long 0x8 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xA "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0xC "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
hexmask.long 0xC 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xE "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
hexmask.long 0xE 0.--31. 1. "ADDR,32-bit address value"
|
|
tree.end
|
|
tree "DMA_CHANNEL2"
|
|
base d:0x1040
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "MODE,Mode Register"
|
|
bitfld.word 0x0 15. "CHINTE,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x0 14. "DATASIZE,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x0 11. "CONTINUOUS,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x0 10. "ONESHOT,One Shot Mode Bit" "0,1"
|
|
bitfld.word 0x0 9. "CHINTMODE,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x0 8. "PERINTE,Peripheral Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "OVRINTE,Overflow Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "PERINTSEL,Peripheral Interrupt and Sync Select"
|
|
line.word 0x1 "CONTROL,Control Register"
|
|
rbitfld.word 0x1 14. "OVRFLG,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x1 13. "RUNSTS,Run Status Bit" "0,1"
|
|
rbitfld.word 0x1 12. "BURSTSTS,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x1 11. "TRANSFERSTS,Transfer Status Bit" "0,1"
|
|
rbitfld.word 0x1 8. "PERINTFLG,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x1 7. "ERRCLR,Error Clear Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "PERINTCLR,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x1 3. "PERINTFRC,Interrupt Force Bit" "0,1"
|
|
bitfld.word 0x1 2. "SOFTRESET,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x1 1. "HALT,Halt Bit" "0,1"
|
|
bitfld.word 0x1 0. "RUN,Run Bit" "0,1"
|
|
line.word 0x2 "BURST_SIZE,Burst Size Register"
|
|
hexmask.word.byte 0x2 0.--4. 1. "BURSTSIZE,Burst Transfer Size"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "BURST_COUNT,Burst Count Register"
|
|
hexmask.word.byte 0x0 0.--4. 1. "BURSTCOUNT,Burst Transfer Size"
|
|
group.word 0x4++0x17
|
|
line.word 0x0 "SRC_BURST_STEP,Source Burst Step Register"
|
|
hexmask.word 0x0 0.--15. 1. "SRCBURSTSTEP,Source post-increment/decrement step size of a burst"
|
|
line.word 0x1 "DST_BURST_STEP,Destination Burst Step Register"
|
|
hexmask.word 0x1 0.--15. 1. "DSTBURSTSTEP,Destination post-increment/decrement step size of a burst"
|
|
line.word 0x2 "TRANSFER_SIZE,Transfer Size Register"
|
|
hexmask.word 0x2 0.--15. 1. "TRANSFERSIZE,These bits specify the number of bursts to transfer:"
|
|
line.word 0x3 "TRANSFER_COUNT,Transfer Count Register"
|
|
hexmask.word 0x3 0.--15. 1. "TRANSFERCOUNT,These bits specify the current transfer counter value:"
|
|
line.word 0x4 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
hexmask.word 0x4 0.--15. 1. "SRCTRANSFERSTEP,Source post-increment/decrement step size of a transfer"
|
|
line.word 0x5 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
hexmask.word 0x5 0.--15. 1. "DSTTRANSFERSTEP,Destination post-increment/decrement step size of a transfer"
|
|
line.word 0x6 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
hexmask.word 0x6 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0x7 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
hexmask.word 0x7 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0x8 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
hexmask.word 0x8 0.--15. 1. "WRAPSTEP,Source post-increment/decrement step size for a wrap"
|
|
line.word 0x9 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
hexmask.word 0x9 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0xA "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
hexmask.word 0xA 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0xB "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
hexmask.word 0xB 0.--15. 1. "WRAPSTEP,Destination post-increment/decrement step size for a wrap"
|
|
group.long 0x10++0x1F
|
|
line.long 0x0 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
hexmask.long 0x0 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x2 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
hexmask.long 0x2 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x4 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
hexmask.long 0x4 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x6 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
hexmask.long 0x6 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x8 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
hexmask.long 0x8 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xA "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0xC "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
hexmask.long 0xC 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xE "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
hexmask.long 0xE 0.--31. 1. "ADDR,32-bit address value"
|
|
tree.end
|
|
tree "DMA_CHANNEL3"
|
|
base d:0x1060
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "MODE,Mode Register"
|
|
bitfld.word 0x0 15. "CHINTE,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x0 14. "DATASIZE,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x0 11. "CONTINUOUS,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x0 10. "ONESHOT,One Shot Mode Bit" "0,1"
|
|
bitfld.word 0x0 9. "CHINTMODE,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x0 8. "PERINTE,Peripheral Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "OVRINTE,Overflow Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "PERINTSEL,Peripheral Interrupt and Sync Select"
|
|
line.word 0x1 "CONTROL,Control Register"
|
|
rbitfld.word 0x1 14. "OVRFLG,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x1 13. "RUNSTS,Run Status Bit" "0,1"
|
|
rbitfld.word 0x1 12. "BURSTSTS,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x1 11. "TRANSFERSTS,Transfer Status Bit" "0,1"
|
|
rbitfld.word 0x1 8. "PERINTFLG,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x1 7. "ERRCLR,Error Clear Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "PERINTCLR,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x1 3. "PERINTFRC,Interrupt Force Bit" "0,1"
|
|
bitfld.word 0x1 2. "SOFTRESET,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x1 1. "HALT,Halt Bit" "0,1"
|
|
bitfld.word 0x1 0. "RUN,Run Bit" "0,1"
|
|
line.word 0x2 "BURST_SIZE,Burst Size Register"
|
|
hexmask.word.byte 0x2 0.--4. 1. "BURSTSIZE,Burst Transfer Size"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "BURST_COUNT,Burst Count Register"
|
|
hexmask.word.byte 0x0 0.--4. 1. "BURSTCOUNT,Burst Transfer Size"
|
|
group.word 0x4++0x17
|
|
line.word 0x0 "SRC_BURST_STEP,Source Burst Step Register"
|
|
hexmask.word 0x0 0.--15. 1. "SRCBURSTSTEP,Source post-increment/decrement step size of a burst"
|
|
line.word 0x1 "DST_BURST_STEP,Destination Burst Step Register"
|
|
hexmask.word 0x1 0.--15. 1. "DSTBURSTSTEP,Destination post-increment/decrement step size of a burst"
|
|
line.word 0x2 "TRANSFER_SIZE,Transfer Size Register"
|
|
hexmask.word 0x2 0.--15. 1. "TRANSFERSIZE,These bits specify the number of bursts to transfer:"
|
|
line.word 0x3 "TRANSFER_COUNT,Transfer Count Register"
|
|
hexmask.word 0x3 0.--15. 1. "TRANSFERCOUNT,These bits specify the current transfer counter value:"
|
|
line.word 0x4 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
hexmask.word 0x4 0.--15. 1. "SRCTRANSFERSTEP,Source post-increment/decrement step size of a transfer"
|
|
line.word 0x5 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
hexmask.word 0x5 0.--15. 1. "DSTTRANSFERSTEP,Destination post-increment/decrement step size of a transfer"
|
|
line.word 0x6 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
hexmask.word 0x6 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0x7 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
hexmask.word 0x7 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0x8 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
hexmask.word 0x8 0.--15. 1. "WRAPSTEP,Source post-increment/decrement step size for a wrap"
|
|
line.word 0x9 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
hexmask.word 0x9 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0xA "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
hexmask.word 0xA 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0xB "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
hexmask.word 0xB 0.--15. 1. "WRAPSTEP,Destination post-increment/decrement step size for a wrap"
|
|
group.long 0x10++0x1F
|
|
line.long 0x0 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
hexmask.long 0x0 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x2 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
hexmask.long 0x2 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x4 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
hexmask.long 0x4 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x6 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
hexmask.long 0x6 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x8 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
hexmask.long 0x8 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xA "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0xC "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
hexmask.long 0xC 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xE "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
hexmask.long 0xE 0.--31. 1. "ADDR,32-bit address value"
|
|
tree.end
|
|
tree "DMA_CHANNEL4"
|
|
base d:0x1080
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "MODE,Mode Register"
|
|
bitfld.word 0x0 15. "CHINTE,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x0 14. "DATASIZE,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x0 11. "CONTINUOUS,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x0 10. "ONESHOT,One Shot Mode Bit" "0,1"
|
|
bitfld.word 0x0 9. "CHINTMODE,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x0 8. "PERINTE,Peripheral Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "OVRINTE,Overflow Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "PERINTSEL,Peripheral Interrupt and Sync Select"
|
|
line.word 0x1 "CONTROL,Control Register"
|
|
rbitfld.word 0x1 14. "OVRFLG,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x1 13. "RUNSTS,Run Status Bit" "0,1"
|
|
rbitfld.word 0x1 12. "BURSTSTS,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x1 11. "TRANSFERSTS,Transfer Status Bit" "0,1"
|
|
rbitfld.word 0x1 8. "PERINTFLG,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x1 7. "ERRCLR,Error Clear Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "PERINTCLR,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x1 3. "PERINTFRC,Interrupt Force Bit" "0,1"
|
|
bitfld.word 0x1 2. "SOFTRESET,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x1 1. "HALT,Halt Bit" "0,1"
|
|
bitfld.word 0x1 0. "RUN,Run Bit" "0,1"
|
|
line.word 0x2 "BURST_SIZE,Burst Size Register"
|
|
hexmask.word.byte 0x2 0.--4. 1. "BURSTSIZE,Burst Transfer Size"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "BURST_COUNT,Burst Count Register"
|
|
hexmask.word.byte 0x0 0.--4. 1. "BURSTCOUNT,Burst Transfer Size"
|
|
group.word 0x4++0x17
|
|
line.word 0x0 "SRC_BURST_STEP,Source Burst Step Register"
|
|
hexmask.word 0x0 0.--15. 1. "SRCBURSTSTEP,Source post-increment/decrement step size of a burst"
|
|
line.word 0x1 "DST_BURST_STEP,Destination Burst Step Register"
|
|
hexmask.word 0x1 0.--15. 1. "DSTBURSTSTEP,Destination post-increment/decrement step size of a burst"
|
|
line.word 0x2 "TRANSFER_SIZE,Transfer Size Register"
|
|
hexmask.word 0x2 0.--15. 1. "TRANSFERSIZE,These bits specify the number of bursts to transfer:"
|
|
line.word 0x3 "TRANSFER_COUNT,Transfer Count Register"
|
|
hexmask.word 0x3 0.--15. 1. "TRANSFERCOUNT,These bits specify the current transfer counter value:"
|
|
line.word 0x4 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
hexmask.word 0x4 0.--15. 1. "SRCTRANSFERSTEP,Source post-increment/decrement step size of a transfer"
|
|
line.word 0x5 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
hexmask.word 0x5 0.--15. 1. "DSTTRANSFERSTEP,Destination post-increment/decrement step size of a transfer"
|
|
line.word 0x6 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
hexmask.word 0x6 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0x7 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
hexmask.word 0x7 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0x8 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
hexmask.word 0x8 0.--15. 1. "WRAPSTEP,Source post-increment/decrement step size for a wrap"
|
|
line.word 0x9 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
hexmask.word 0x9 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0xA "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
hexmask.word 0xA 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0xB "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
hexmask.word 0xB 0.--15. 1. "WRAPSTEP,Destination post-increment/decrement step size for a wrap"
|
|
group.long 0x10++0x1F
|
|
line.long 0x0 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
hexmask.long 0x0 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x2 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
hexmask.long 0x2 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x4 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
hexmask.long 0x4 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x6 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
hexmask.long 0x6 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x8 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
hexmask.long 0x8 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xA "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0xC "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
hexmask.long 0xC 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xE "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
hexmask.long 0xE 0.--31. 1. "ADDR,32-bit address value"
|
|
tree.end
|
|
tree "DMA_CHANNEL5"
|
|
base d:0x10A0
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "MODE,Mode Register"
|
|
bitfld.word 0x0 15. "CHINTE,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x0 14. "DATASIZE,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x0 11. "CONTINUOUS,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x0 10. "ONESHOT,One Shot Mode Bit" "0,1"
|
|
bitfld.word 0x0 9. "CHINTMODE,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x0 8. "PERINTE,Peripheral Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "OVRINTE,Overflow Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "PERINTSEL,Peripheral Interrupt and Sync Select"
|
|
line.word 0x1 "CONTROL,Control Register"
|
|
rbitfld.word 0x1 14. "OVRFLG,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x1 13. "RUNSTS,Run Status Bit" "0,1"
|
|
rbitfld.word 0x1 12. "BURSTSTS,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x1 11. "TRANSFERSTS,Transfer Status Bit" "0,1"
|
|
rbitfld.word 0x1 8. "PERINTFLG,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x1 7. "ERRCLR,Error Clear Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "PERINTCLR,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x1 3. "PERINTFRC,Interrupt Force Bit" "0,1"
|
|
bitfld.word 0x1 2. "SOFTRESET,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x1 1. "HALT,Halt Bit" "0,1"
|
|
bitfld.word 0x1 0. "RUN,Run Bit" "0,1"
|
|
line.word 0x2 "BURST_SIZE,Burst Size Register"
|
|
hexmask.word.byte 0x2 0.--4. 1. "BURSTSIZE,Burst Transfer Size"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "BURST_COUNT,Burst Count Register"
|
|
hexmask.word.byte 0x0 0.--4. 1. "BURSTCOUNT,Burst Transfer Size"
|
|
group.word 0x4++0x17
|
|
line.word 0x0 "SRC_BURST_STEP,Source Burst Step Register"
|
|
hexmask.word 0x0 0.--15. 1. "SRCBURSTSTEP,Source post-increment/decrement step size of a burst"
|
|
line.word 0x1 "DST_BURST_STEP,Destination Burst Step Register"
|
|
hexmask.word 0x1 0.--15. 1. "DSTBURSTSTEP,Destination post-increment/decrement step size of a burst"
|
|
line.word 0x2 "TRANSFER_SIZE,Transfer Size Register"
|
|
hexmask.word 0x2 0.--15. 1. "TRANSFERSIZE,These bits specify the number of bursts to transfer:"
|
|
line.word 0x3 "TRANSFER_COUNT,Transfer Count Register"
|
|
hexmask.word 0x3 0.--15. 1. "TRANSFERCOUNT,These bits specify the current transfer counter value:"
|
|
line.word 0x4 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
hexmask.word 0x4 0.--15. 1. "SRCTRANSFERSTEP,Source post-increment/decrement step size of a transfer"
|
|
line.word 0x5 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
hexmask.word 0x5 0.--15. 1. "DSTTRANSFERSTEP,Destination post-increment/decrement step size of a transfer"
|
|
line.word 0x6 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
hexmask.word 0x6 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0x7 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
hexmask.word 0x7 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0x8 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
hexmask.word 0x8 0.--15. 1. "WRAPSTEP,Source post-increment/decrement step size for a wrap"
|
|
line.word 0x9 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
hexmask.word 0x9 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0xA "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
hexmask.word 0xA 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0xB "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
hexmask.word 0xB 0.--15. 1. "WRAPSTEP,Destination post-increment/decrement step size for a wrap"
|
|
group.long 0x10++0x1F
|
|
line.long 0x0 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
hexmask.long 0x0 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x2 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
hexmask.long 0x2 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x4 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
hexmask.long 0x4 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x6 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
hexmask.long 0x6 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x8 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
hexmask.long 0x8 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xA "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0xC "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
hexmask.long 0xC 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xE "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
hexmask.long 0xE 0.--31. 1. "ADDR,32-bit address value"
|
|
tree.end
|
|
tree "DMA_CHANNEL6"
|
|
base d:0x10C0
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "MODE,Mode Register"
|
|
bitfld.word 0x0 15. "CHINTE,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x0 14. "DATASIZE,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x0 11. "CONTINUOUS,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x0 10. "ONESHOT,One Shot Mode Bit" "0,1"
|
|
bitfld.word 0x0 9. "CHINTMODE,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x0 8. "PERINTE,Peripheral Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "OVRINTE,Overflow Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "PERINTSEL,Peripheral Interrupt and Sync Select"
|
|
line.word 0x1 "CONTROL,Control Register"
|
|
rbitfld.word 0x1 14. "OVRFLG,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x1 13. "RUNSTS,Run Status Bit" "0,1"
|
|
rbitfld.word 0x1 12. "BURSTSTS,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x1 11. "TRANSFERSTS,Transfer Status Bit" "0,1"
|
|
rbitfld.word 0x1 8. "PERINTFLG,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x1 7. "ERRCLR,Error Clear Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "PERINTCLR,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x1 3. "PERINTFRC,Interrupt Force Bit" "0,1"
|
|
bitfld.word 0x1 2. "SOFTRESET,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x1 1. "HALT,Halt Bit" "0,1"
|
|
bitfld.word 0x1 0. "RUN,Run Bit" "0,1"
|
|
line.word 0x2 "BURST_SIZE,Burst Size Register"
|
|
hexmask.word.byte 0x2 0.--4. 1. "BURSTSIZE,Burst Transfer Size"
|
|
rgroup.word 0x3++0x1
|
|
line.word 0x0 "BURST_COUNT,Burst Count Register"
|
|
hexmask.word.byte 0x0 0.--4. 1. "BURSTCOUNT,Burst Transfer Size"
|
|
group.word 0x4++0x17
|
|
line.word 0x0 "SRC_BURST_STEP,Source Burst Step Register"
|
|
hexmask.word 0x0 0.--15. 1. "SRCBURSTSTEP,Source post-increment/decrement step size of a burst"
|
|
line.word 0x1 "DST_BURST_STEP,Destination Burst Step Register"
|
|
hexmask.word 0x1 0.--15. 1. "DSTBURSTSTEP,Destination post-increment/decrement step size of a burst"
|
|
line.word 0x2 "TRANSFER_SIZE,Transfer Size Register"
|
|
hexmask.word 0x2 0.--15. 1. "TRANSFERSIZE,These bits specify the number of bursts to transfer:"
|
|
line.word 0x3 "TRANSFER_COUNT,Transfer Count Register"
|
|
hexmask.word 0x3 0.--15. 1. "TRANSFERCOUNT,These bits specify the current transfer counter value:"
|
|
line.word 0x4 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
hexmask.word 0x4 0.--15. 1. "SRCTRANSFERSTEP,Source post-increment/decrement step size of a transfer"
|
|
line.word 0x5 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
hexmask.word 0x5 0.--15. 1. "DSTTRANSFERSTEP,Destination post-increment/decrement step size of a transfer"
|
|
line.word 0x6 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
hexmask.word 0x6 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0x7 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
hexmask.word 0x7 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0x8 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
hexmask.word 0x8 0.--15. 1. "WRAPSTEP,Source post-increment/decrement step size for a wrap"
|
|
line.word 0x9 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
hexmask.word 0x9 0.--15. 1. "WRAPSIZE,Number of bursts to transfer before wrapping"
|
|
line.word 0xA "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
hexmask.word 0xA 0.--15. 1. "WRAPSIZE,These bits indicate the current wrap counter value:"
|
|
line.word 0xB "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
hexmask.word 0xB 0.--15. 1. "WRAPSTEP,Destination post-increment/decrement step size for a wrap"
|
|
group.long 0x10++0x1F
|
|
line.long 0x0 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
hexmask.long 0x0 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x2 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
hexmask.long 0x2 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x4 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
hexmask.long 0x4 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0x6 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
hexmask.long 0x6 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0x8 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
hexmask.long 0x8 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xA "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDR,32-bit address value"
|
|
line.long 0xC "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
hexmask.long 0xC 0.--31. 1. "BEGADDR,32-bit address value"
|
|
line.long 0xE "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
hexmask.long 0xE 0.--31. 1. "ADDR,32-bit address value"
|
|
tree.end
|
|
tree "DMA_COMMON"
|
|
base d:0x1000
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "DMACTRL,DMA Control Register"
|
|
bitfld.word 0x0 1. "PRIORITYRESET,Priority Reset Bit" "0,1"
|
|
bitfld.word 0x0 0. "HARDRESET,Hard Reset Bit" "0,1"
|
|
line.word 0x1 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x1 15. "FREE,Debug Mode Bit" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "PRIORITYCTRL1,Priority Control 1 Register"
|
|
bitfld.word 0x0 0. "CH1PRIORITY,Ch1 Priority Bit" "0,1"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PRIORITYSTAT,Priority Status Register"
|
|
bitfld.word 0x0 4.--6. "ACTIVESTS_SHADOW,Active Channel Status Shadow Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 0.--2. "ACTIVESTS,Active Channel Status Bits" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "ECAP (Enhanced Capture)"
|
|
base d:0x0
|
|
tree "ECAP1"
|
|
base d:0x5200
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree "ECAP2"
|
|
base d:0x5240
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree "ECAP3"
|
|
base d:0x5280
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree "ECAP4"
|
|
base d:0x52C0
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree "ECAP5"
|
|
base d:0x5300
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree "ECAP6"
|
|
base d:0x5340
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree "ECAP7"
|
|
base d:0x5380
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter"
|
|
hexmask.long 0x0 0.--31. 1. "TSCTR,Time Stamp Counter"
|
|
line.long 0x2 "CTRPHS,Counter Phase Offset Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "CTRPHS,Counter phase"
|
|
line.long 0x4 "CAP1,Capture 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "CAP1,Capture 1"
|
|
line.long 0x6 "CAP2,Capture 2 Register"
|
|
hexmask.long 0x6 0.--31. 1. "CAP2,Capture 2"
|
|
line.long 0x8 "CAP3,Capture 3 Register"
|
|
hexmask.long 0x8 0.--31. 1. "CAP3,Capture 3"
|
|
line.long 0xA "CAP4,Capture 4 Register"
|
|
hexmask.long 0xA 0.--31. 1. "CAP4,Capture 4"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "ECCTL0,Capture Control Register 0"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INPUTSEL,INPUT source select"
|
|
group.word 0x14++0x5
|
|
line.word 0x0 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select"
|
|
bitfld.word 0x0 8. "CAPLDEN,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
|
|
bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
|
|
bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
|
|
line.word 0x1 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x1 14.--15. "MODCNTRSTS,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x1 12.--13. "DMAEVTSEL,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x1 11. "CTRFILTRESET,Reset event filter modulus counter and interrupt flags." "0,1"
|
|
bitfld.word 0x1 10. "APWMPOL,APWM output polarity select" "0,1"
|
|
bitfld.word 0x1 9. "CAP_APWM,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x1 8. "SWSYNC,SW forced counter sync" "0,1"
|
|
bitfld.word 0x1 6.--7. "SYNCO_SEL,Sync-out mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x1 5. "SYNCI_EN,Counter sync-in select" "0,1"
|
|
bitfld.word 0x1 4. "TSCTRSTOP,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x1 3. "REARM,One-shot re-arm" "0,1"
|
|
bitfld.word 0x1 1.--2. "STOP_WRAP,Stop value for one-shot Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x1 0. "CONT_ONESHT,Continuous or one-shot" "0,1"
|
|
line.word 0x2 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x2 7. "CTR_EQ_CMP,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "CTR_EQ_PRD,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 5. "CTROVF,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Flag" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x0 7. "CTR_CMP,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 6. "CTR_PRD,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear" "0,1"
|
|
bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear" "0,1"
|
|
line.word 0x1 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x1 7. "CTR_CMP,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 6. "CTR_PRD,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x1 5. "CTROVF,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x1 4. "CEVT4,Capture Event 4 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 3. "CEVT3,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 2. "CEVT2,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x1 1. "CEVT1,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "ECAPSYNCINSEL,SYNC source select register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEL,SYNCIN source select"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "EMAC (Ethernet Media Access Controller)"
|
|
base d:0x0
|
|
tree "ETHERNET"
|
|
base d:0x400C0000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MAC_Configuration,"
|
|
line.long 0x4 "MAC_Ext_Configuration,"
|
|
line.long 0x8 "MAC_Packet_Filter,"
|
|
line.long 0xC "MAC_Watchdog_Timeout,"
|
|
line.long 0x10 "MAC_Hash_Table_Reg0,"
|
|
line.long 0x14 "MAC_Hash_Table_Reg1,"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "MAC_VLAN_Tag_Ctrl,"
|
|
line.long 0x4 "MAC_VLAN_Tag_Data,"
|
|
line.long 0x8 "MAC_VLAN_Hash_Table,"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "MAC_VLAN_Incl,"
|
|
line.long 0x4 "MAC_Inner_VLAN_Incl,"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "MAC_Q0_Tx_Flow_Ctrl,"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "MAC_Rx_Flow_Ctrl,"
|
|
line.long 0x4 "MAC_RxQ_Ctrl4,"
|
|
group.long 0xA0++0xB
|
|
line.long 0x0 "MAC_RxQ_Ctrl0,"
|
|
line.long 0x4 "MAC_RxQ_Ctrl1,"
|
|
line.long 0x8 "MAC_RxQ_Ctrl2,"
|
|
group.long 0xB0++0xB
|
|
line.long 0x0 "MAC_Interrupt_Status,"
|
|
line.long 0x4 "MAC_Interrupt_Enable,"
|
|
line.long 0x8 "MAC_Rx_Tx_Status,"
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "MAC_PMT_Control_Status,"
|
|
line.long 0x4 "MAC_RWK_Packet_Filter,"
|
|
group.long 0xD0++0xF
|
|
line.long 0x0 "MAC_LPI_Control_Status,"
|
|
line.long 0x4 "MAC_LPI_Timers_Control,"
|
|
line.long 0x8 "MAC_LPI_Entry_Timer,"
|
|
line.long 0xC "MAC_1US_Tic_Counter,"
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "MAC_Version,"
|
|
line.long 0x4 "MAC_Debug,"
|
|
group.long 0x11C++0xF
|
|
line.long 0x0 "MAC_HW_Feature0,"
|
|
line.long 0x4 "MAC_HW_Feature1,"
|
|
line.long 0x8 "MAC_HW_Feature2,"
|
|
line.long 0xC "MAC_HW_Feature3,"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "MAC_MDIO_Address,"
|
|
line.long 0x4 "MAC_MDIO_Data,"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "MAC_ARP_Address,"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "MAC_CSR_SW_Ctrl,"
|
|
group.long 0x238++0x3
|
|
line.long 0x0 "MAC_Ext_Cfg1,"
|
|
group.long 0x300++0x3F
|
|
line.long 0x0 "MAC_Address0_High,"
|
|
line.long 0x4 "MAC_Address0_Low,"
|
|
line.long 0x8 "MAC_Address1_High,"
|
|
line.long 0xC "MAC_Address1_Low,"
|
|
line.long 0x10 "MAC_Address2_High,"
|
|
line.long 0x14 "MAC_Address2_Low,"
|
|
line.long 0x18 "MAC_Address3_High,"
|
|
line.long 0x1C "MAC_Address3_Low,"
|
|
line.long 0x20 "MAC_Address4_High,"
|
|
line.long 0x24 "MAC_Address4_Low,"
|
|
line.long 0x28 "MAC_Address5_High,"
|
|
line.long 0x2C "MAC_Address5_Low,"
|
|
line.long 0x30 "MAC_Address6_High,"
|
|
line.long 0x34 "MAC_Address6_Low,"
|
|
line.long 0x38 "MAC_Address7_High,"
|
|
line.long 0x3C "MAC_Address7_Low,"
|
|
group.long 0x700++0x7B
|
|
line.long 0x0 "MMC_Control,"
|
|
line.long 0x4 "MMC_Rx_Interrupt,"
|
|
line.long 0x8 "MMC_Tx_Interrupt,"
|
|
line.long 0xC "MMC_Rx_Interrupt_Mask,"
|
|
line.long 0x10 "MMC_Tx_Interrupt_Mask,"
|
|
line.long 0x14 "Tx_Octet_Count_Good_Bad,"
|
|
line.long 0x18 "Tx_Packet_Count_Good_Bad,"
|
|
line.long 0x1C "Tx_Broadcast_Packets_Good,"
|
|
line.long 0x20 "Tx_Multicast_Packets_Good,"
|
|
line.long 0x24 "Tx_64Octets_Packets_Good_Bad,"
|
|
line.long 0x28 "Tx_65To127Octets_Packets_Good_Bad,"
|
|
line.long 0x2C "Tx_128To255Octets_Packets_Good_Bad,"
|
|
line.long 0x30 "Tx_256To511Octets_Packets_Good_Bad,"
|
|
line.long 0x34 "Tx_512To1023Octets_Packets_Good_Bad,"
|
|
line.long 0x38 "Tx_1024ToMaxOctets_Packets_Good_Bad,"
|
|
line.long 0x3C "Tx_Unicast_Packets_Good_Bad,"
|
|
line.long 0x40 "Tx_Multicast_Packets_Good_Bad,"
|
|
line.long 0x44 "Tx_Broadcast_Packets_Good_Bad,"
|
|
line.long 0x48 "Tx_Underflow_Error_Packets,"
|
|
line.long 0x4C "Tx_Single_Collision_Good_Packets,"
|
|
line.long 0x50 "Tx_Multiple_Collision_Good_Packets,"
|
|
line.long 0x54 "Tx_Deferred_Packets,"
|
|
line.long 0x58 "Tx_Late_Collision_Packets,"
|
|
line.long 0x5C "Tx_Excessive_Collision_Packets,"
|
|
line.long 0x60 "Tx_Carrier_Error_Packets,"
|
|
line.long 0x64 "Tx_Octet_Count_Good,"
|
|
line.long 0x68 "Tx_Packet_Count_Good,"
|
|
line.long 0x6C "Tx_Excessive_Deferral_Error,"
|
|
line.long 0x70 "Tx_Pause_Packets,"
|
|
line.long 0x74 "Tx_VLAN_Packets_Good,"
|
|
line.long 0x78 "Tx_OSize_Packets_Good,"
|
|
group.long 0x780++0x67
|
|
line.long 0x0 "Rx_Packets_Count_Good_Bad,"
|
|
line.long 0x4 "Rx_Octet_Count_Good_Bad,"
|
|
line.long 0x8 "Rx_Octet_Count_Good,"
|
|
line.long 0xC "Rx_Broadcast_Packets_Good,"
|
|
line.long 0x10 "Rx_Multicast_Packets_Good,"
|
|
line.long 0x14 "Rx_CRC_Error_Packets,"
|
|
line.long 0x18 "Rx_Alignment_Error_Packets,"
|
|
line.long 0x1C "Rx_Runt_Error_Packets,"
|
|
line.long 0x20 "Rx_Jabber_Error_Packets,"
|
|
line.long 0x24 "Rx_Undersize_Packets_Good,"
|
|
line.long 0x28 "Rx_Oversize_Packets_Good,"
|
|
line.long 0x2C "Rx_64Octets_Packets_Good_Bad,"
|
|
line.long 0x30 "Rx_65To127Octets_Packets_Good_Bad,"
|
|
line.long 0x34 "Rx_128To255Octets_Packets_Good_Bad,"
|
|
line.long 0x38 "Rx_256To511Octets_Packets_Good_Bad,"
|
|
line.long 0x3C "Rx_512To1023Octets_Packets_Good_Bad,"
|
|
line.long 0x40 "Rx_1024ToMaxOctets_Packets_Good_Bad,"
|
|
line.long 0x44 "Rx_Unicast_Packets_Good,"
|
|
line.long 0x48 "Rx_Length_Error_Packets,"
|
|
line.long 0x4C "Rx_Out_Of_Range_Type_Packets,"
|
|
line.long 0x50 "Rx_Pause_Packets,"
|
|
line.long 0x54 "Rx_FIFO_Overflow_Packets,"
|
|
line.long 0x58 "Rx_VLAN_Packets_Good_Bad,"
|
|
line.long 0x5C "Rx_Watchdog_Error_Packets,"
|
|
line.long 0x60 "Rx_Receive_Error_Packets,"
|
|
line.long 0x64 "Rx_Control_Packets_Good,"
|
|
group.long 0x7EC++0xF
|
|
line.long 0x0 "Tx_LPI_USEC_Cntr,"
|
|
line.long 0x4 "Tx_LPI_Tran_Cntr,"
|
|
line.long 0x8 "Rx_LPI_USEC_Cntr,"
|
|
line.long 0xC "Rx_LPI_Tran_Cntr,"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "MMC_IPC_Rx_Interrupt_Mask,"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "MMC_IPC_Rx_Interrupt,"
|
|
group.long 0x810++0x37
|
|
line.long 0x0 "RxIPv4_Good_Packets,"
|
|
line.long 0x4 "RxIPv4_Header_Error_Packets,"
|
|
line.long 0x8 "RxIPv4_No_Payload_Packets,"
|
|
line.long 0xC "RxIPv4_Fragmented_Packets,"
|
|
line.long 0x10 "RxIPv4_UDP_Checksum_Disabled_Packets,"
|
|
line.long 0x14 "RxIPv6_Good_Packets,"
|
|
line.long 0x18 "RxIPv6_Header_Error_Packets,"
|
|
line.long 0x1C "RxIPv6_No_Payload_Packets,"
|
|
line.long 0x20 "RxUDP_Good_Packets,"
|
|
line.long 0x24 "RxUDP_Error_Packets,"
|
|
line.long 0x28 "RxTCP_Good_Packets,"
|
|
line.long 0x2C "RxTCP_Error_Packets,"
|
|
line.long 0x30 "RxICMP_Good_Packets,"
|
|
line.long 0x34 "RxICMP_Error_Packets,"
|
|
group.long 0x850++0x37
|
|
line.long 0x0 "RxIPv4_Good_Octets,"
|
|
line.long 0x4 "RxIPv4_Header_Error_Octets,"
|
|
line.long 0x8 "RxIPv4_No_Payload_Octets,"
|
|
line.long 0xC "RxIPv4_Fragmented_Octets,"
|
|
line.long 0x10 "RxIPv4_UDP_Checksum_Disable_Octets,"
|
|
line.long 0x14 "RxIPv6_Good_Octets,"
|
|
line.long 0x18 "RxIPv6_Header_Error_Octets,"
|
|
line.long 0x1C "RxIPv6_No_Payload_Octets,"
|
|
line.long 0x20 "RxUDP_Good_Octets,"
|
|
line.long 0x24 "RxUDP_Error_Octets,"
|
|
line.long 0x28 "RxTCP_Good_Octets,"
|
|
line.long 0x2C "RxTCP_Error_Octets,"
|
|
line.long 0x30 "RxICMP_Good_Octets,"
|
|
line.long 0x34 "RxICMP_Error_Octets,"
|
|
group.long 0x900++0x7
|
|
line.long 0x0 "MAC_L3_L4_Control0,"
|
|
line.long 0x4 "MAC_Layer4_Address0,"
|
|
group.long 0x910++0xF
|
|
line.long 0x0 "MAC_Layer3_Addr0_Reg0,"
|
|
line.long 0x4 "MAC_Layer3_Addr1_Reg0,"
|
|
line.long 0x8 "MAC_Layer3_Addr2_Reg0,"
|
|
line.long 0xC "MAC_Layer3_Addr3_Reg0,"
|
|
group.long 0x930++0x7
|
|
line.long 0x0 "MAC_L3_L4_Control1,"
|
|
line.long 0x4 "MAC_Layer4_Address1,"
|
|
group.long 0x940++0xF
|
|
line.long 0x0 "MAC_Layer3_Addr0_Reg1,"
|
|
line.long 0x4 "MAC_Layer3_Addr1_Reg1,"
|
|
line.long 0x8 "MAC_Layer3_Addr2_Reg1,"
|
|
line.long 0xC "MAC_Layer3_Addr3_Reg1,"
|
|
group.long 0x960++0x7
|
|
line.long 0x0 "MAC_L3_L4_Control2,"
|
|
line.long 0x4 "MAC_Layer4_Address2,"
|
|
group.long 0x970++0xF
|
|
line.long 0x0 "MAC_Layer3_Addr0_Reg2,"
|
|
line.long 0x4 "MAC_Layer3_Addr1_Reg2,"
|
|
line.long 0x8 "MAC_Layer3_Addr2_Reg2,"
|
|
line.long 0xC "MAC_Layer3_Addr3_Reg2,"
|
|
group.long 0x990++0x7
|
|
line.long 0x0 "MAC_L3_L4_Control3,"
|
|
line.long 0x4 "MAC_Layer4_Address3,"
|
|
group.long 0x9A0++0xF
|
|
line.long 0x0 "MAC_Layer3_Addr0_Reg3,"
|
|
line.long 0x4 "MAC_Layer3_Addr1_Reg3,"
|
|
line.long 0x8 "MAC_Layer3_Addr2_Reg3,"
|
|
line.long 0xC "MAC_Layer3_Addr3_Reg3,"
|
|
group.long 0xB00++0x23
|
|
line.long 0x0 "MAC_Timestamp_Control,"
|
|
line.long 0x4 "MAC_Sub_Second_Increment,"
|
|
line.long 0x8 "MAC_System_Time_Seconds,"
|
|
line.long 0xC "MAC_System_Time_Nanoseconds,"
|
|
line.long 0x10 "MAC_System_Time_Seconds_Update,"
|
|
line.long 0x14 "MAC_System_Time_Nanoseconds_Update,"
|
|
line.long 0x18 "MAC_Timestamp_Addend,"
|
|
line.long 0x1C "MAC_System_Time_Higher_Word_Seconds,"
|
|
line.long 0x20 "MAC_Timestamp_Status,"
|
|
group.long 0xB30++0x7
|
|
line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,"
|
|
line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,"
|
|
group.long 0xB40++0x3
|
|
line.long 0x0 "MAC_Auxiliary_Control,"
|
|
group.long 0xB48++0x1F
|
|
line.long 0x0 "MAC_Auxiliary_Timestamp_Nanoseconds,"
|
|
line.long 0x4 "MAC_Auxiliary_Timestamp_Seconds,"
|
|
line.long 0x8 "MAC_Timestamp_Ingress_Asym_Corr,"
|
|
line.long 0xC "MAC_Timestamp_Egress_Asym_Corr,"
|
|
line.long 0x10 "MAC_Timestamp_Ingress_Corr_Nanosecond,"
|
|
line.long 0x14 "MAC_Timestamp_Egress_Corr_Nanosecond,"
|
|
line.long 0x18 "MAC_Timestamp_Ingress_Corr_Subnanosec,"
|
|
line.long 0x1C "MAC_Timestamp_Egress_Corr_Subnanosec,"
|
|
group.long 0xB70++0x3
|
|
line.long 0x0 "MAC_PPS_Control,"
|
|
group.long 0xB80++0x1F
|
|
line.long 0x0 "MAC_PPS0_Target_Time_Seconds,"
|
|
line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,"
|
|
line.long 0x8 "MAC_PPS0_Interval,"
|
|
line.long 0xC "MAC_PPS0_Width,"
|
|
line.long 0x10 "MAC_PPS1_Target_Time_Seconds,"
|
|
line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,"
|
|
line.long 0x18 "MAC_PPS1_Interval,"
|
|
line.long 0x1C "MAC_PPS1_Width,"
|
|
group.long 0xBC0++0x13
|
|
line.long 0x0 "MAC_PTO_Control,"
|
|
line.long 0x4 "MAC_Source_Port_Identity0,"
|
|
line.long 0x8 "MAC_Source_Port_Identity1,"
|
|
line.long 0xC "MAC_Source_Port_Identity2,"
|
|
line.long 0x10 "MAC_Log_Message_Interval,"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MTL_Operation_Mode,"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "MTL_DBG_CTL,"
|
|
line.long 0x4 "MTL_DBG_STS,"
|
|
line.long 0x8 "MTL_FIFO_Debug_Data,"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MTL_Interrupt_Status,"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MTL_RxQ_DMA_Map0,"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MTL_TxQ0_Operation_Mode,"
|
|
line.long 0x4 "MTL_TxQ0_Underflow,"
|
|
line.long 0x8 "MTL_TxQ0_Debug,"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "MTL_TxQ0_ETS_Status,"
|
|
line.long 0x4 "MTL_TxQ0_Quantum_Weight,"
|
|
group.long 0x2C++0x13
|
|
line.long 0x0 "MTL_Q0_Interrupt_Control_Status,"
|
|
line.long 0x4 "MTL_RxQ0_Operation_Mode,"
|
|
line.long 0x8 "MTL_RxQ0_Missed_Packet_Overflow_Cnt,"
|
|
line.long 0xC "MTL_RxQ0_Debug,"
|
|
line.long 0x10 "MTL_RxQ0_Control,"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MTL_TxQ1_Operation_Mode,"
|
|
line.long 0x4 "MTL_TxQ1_Underflow,"
|
|
line.long 0x8 "MTL_TxQ1_Debug,"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "MTL_TxQ1_ETS_Status,"
|
|
line.long 0x4 "MTL_TxQ1_Quantum_Weight,"
|
|
group.long 0x2C++0x13
|
|
line.long 0x0 "MTL_Q1_Interrupt_Control_Status,"
|
|
line.long 0x4 "MTL_RxQ1_Operation_Mode,"
|
|
line.long 0x8 "MTL_RxQ1_Missed_Packet_Overflow_Cnt,"
|
|
line.long 0xC "MTL_RxQ1_Debug,"
|
|
line.long 0x10 "MTL_RxQ1_Control,"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "DMA_Mode,"
|
|
line.long 0x4 "DMA_SysBus_Mode,"
|
|
line.long 0x8 "DMA_Interrupt_Status,"
|
|
line.long 0xC "DMA_Debug_Status0,"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DMA_CH0_Control,"
|
|
line.long 0x4 "DMA_CH0_Tx_Control,"
|
|
line.long 0x8 "DMA_CH0_Rx_Control,"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DMA_CH0_TxDesc_List_Address,"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "DMA_CH0_RxDesc_List_Address,"
|
|
line.long 0x4 "DMA_CH0_TxDesc_Tail_Pointer,"
|
|
group.long 0x28++0x13
|
|
line.long 0x0 "DMA_CH0_RxDesc_Tail_Pointer,"
|
|
line.long 0x4 "DMA_CH0_TxDesc_Ring_Length,"
|
|
line.long 0x8 "DMA_CH0_RxDesc_Ring_Length,"
|
|
line.long 0xC "DMA_CH0_Interrupt_Enable,"
|
|
line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DMA_CH0_Current_App_TxDesc,"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DMA_CH0_Current_App_RxDesc,"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DMA_CH0_Current_App_TxBuffer,"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "DMA_CH0_Current_App_RxBuffer,"
|
|
line.long 0x4 "DMA_CH0_Status,"
|
|
line.long 0x8 "DMA_CH0_Miss_Frame_Cnt,"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DMA_CH0_RX_ERI_Cnt,"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DMA_CH1_Control,"
|
|
line.long 0x4 "DMA_CH1_Tx_Control,"
|
|
line.long 0x8 "DMA_CH1_Rx_Control,"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DMA_CH1_TxDesc_List_Address,"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "DMA_CH1_RxDesc_List_Address,"
|
|
line.long 0x4 "DMA_CH1_TxDesc_Tail_Pointer,"
|
|
group.long 0x28++0x13
|
|
line.long 0x0 "DMA_CH1_RxDesc_Tail_Pointer,"
|
|
line.long 0x4 "DMA_CH1_TxDesc_Ring_Length,"
|
|
line.long 0x8 "DMA_CH1_RxDesc_Ring_Length,"
|
|
line.long 0xC "DMA_CH1_Interrupt_Enable,"
|
|
line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DMA_CH1_Current_App_TxDesc,"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DMA_CH1_Current_App_RxDesc,"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DMA_CH1_Current_App_TxBuffer,"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "DMA_CH1_Current_App_RxBuffer,"
|
|
line.long 0x4 "DMA_CH1_Status,"
|
|
line.long 0x8 "DMA_CH1_Miss_Frame_Cnt,"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DMA_CH1_RX_ERI_Cnt,"
|
|
tree.end
|
|
tree "ETHERNETSS"
|
|
base d:0x400C2000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ETHERNETSS_IPREVNUM,IP Revision Number"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IP_REV_MAJOR,Major IP Revision Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "IP_REV_MINOR,Minor IP Revision Number"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "ETHERNETSS_CTRLSTS,Control Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x0 8.--9. "FLOW_CTRL_EN,Back-pressure enable per receive queue." "0,1,2,3"
|
|
bitfld.long 0x0 7. "CLK_SRC_SEL,Internal Clock Selection" "0,1"
|
|
rbitfld.long 0x0 4. "CLK_LM,MII Loop-back mode clock select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PHY_INTF_SEL,PHY Type Selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "ETHERNETSS_PTPTSTRIGSEL0,PTP Trigger-0 select"
|
|
hexmask.long.byte 0x4 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
hexmask.long.byte 0x4 0.--4. 1. "PTP_AUX_TS_TRIG_SEL0,Trigger select for Auxillary TS capture - 0"
|
|
line.long 0x8 "ETHERNETSS_PTPTSTRIGSEL1,PTP Trigger-1 select"
|
|
hexmask.long.byte 0x8 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
hexmask.long.byte 0x8 0.--4. 1. "PTP_AUX_TS_TRIG_SEL1,Trigger select for Auxillary TS capture - 1"
|
|
line.long 0xC "ETHERNETSS_PTPTSSWTRIG0,PTP SW Trigger-0"
|
|
bitfld.long 0xC 0. "PTP_AUX_TS_SW_TRIG0,SW trigger for AUX TS capture for trigger-0" "0,1"
|
|
line.long 0x10 "ETHERNETSS_PTPTSSWTRIG1,PTP SW Trigger-1"
|
|
bitfld.long 0x10 0. "PTP_AUX_TS_SW_TRIG1,SW trigger for AUX TS capture for trigger-1" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "ETHERNETSS_PTPPPSR0,PTP PPS-0 Read"
|
|
bitfld.long 0x0 0. "PTP_PPS_R0,Registered value of Pulse Per Second-0" "0,1"
|
|
line.long 0x4 "ETHERNETSS_PTPPPSR1,PTP PPS-1 Read"
|
|
bitfld.long 0x4 0. "PTP_PPS_R1,Registered value of Pulse Per Second-1" "0,1"
|
|
line.long 0x8 "ETHERNETSS_PTP_TSRL,PTP timestamp read lower 32 bits"
|
|
hexmask.long 0x8 0.--31. 1. "TSR_L,Time-stamp o/p from the EQOS Low"
|
|
line.long 0xC "ETHERNETSS_PTP_TSRH,PTP timestamp read upper 32 bits"
|
|
hexmask.long 0xC 0.--31. 1. "TSR_H,Time-stamp o/p from the EQOS High"
|
|
group.long 0x28++0xB
|
|
line.long 0x0 "ETHERNETSS_PTP_TSWL,External Timestamp write lower 32 bits"
|
|
hexmask.long 0x0 0.--31. 1. "TSW_L,Time-stamp i/p from external to EQOS"
|
|
line.long 0x4 "ETHERNETSS_PTP_TSWH,External Timestamp write upper 32 bits"
|
|
hexmask.long 0x4 0.--31. 1. "TSW_H,Time-stamp i/p from external to EQOS"
|
|
line.long 0x8 "ETHERNETSS_REVMII_CTRL,RevMII Phy Address controls"
|
|
hexmask.long.byte 0x8 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
hexmask.long.byte 0x8 8.--12. 1. "REVMII_REMOTE_PHY_ADDR,RevMII Remote Register Space offset"
|
|
hexmask.long.byte 0x8 0.--4. 1. "REVMII_CORE_PHY_ADDR,RevMII Core Register Space offset"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "EMIF (External Memory Interface)"
|
|
base d:0x0
|
|
tree "EMIF1"
|
|
base d:0x47000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RCSR,Revision Code and Status Register"
|
|
bitfld.long 0x0 31. "BE,EMIF endian mode." "0,1"
|
|
bitfld.long 0x0 30. "FR,EMIF is running in full rate or half rate." "0,1"
|
|
hexmask.long.word 0x0 16.--29. 1. "MODULE_ID,EMIF module ID."
|
|
hexmask.long.byte 0x0 8.--15. 1. "MAJOR_REVISION,Major Revision."
|
|
hexmask.long.byte 0x0 0.--7. 1. "MINOR_REVISION,Minor Revision."
|
|
group.long 0x2++0x1B
|
|
line.long 0x0 "ASYNC_WCCR,Async Wait Cycle Config Register"
|
|
bitfld.long 0x0 28. "WP0,Polarity for EMxWAIT." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MAX_EXT_WAIT,Maximum Extended Wait cycles."
|
|
line.long 0x2 "SDRAM_CR,SDRAM (EMxCS0n) Config Register"
|
|
bitfld.long 0x2 31. "SR,Self Refresh." "0,1"
|
|
bitfld.long 0x2 30. "PD,Power Down." "0,1"
|
|
bitfld.long 0x2 29. "PDWR,Perform refreshes during Power Down." "0,1"
|
|
bitfld.long 0x2 14. "NM,Narrow Mode." "0,1"
|
|
bitfld.long 0x2 9.--11. "CL,CAS Latency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x2 8. "BIT_11_9_LOCK,Bits 11 to 9 are writable only if this bit is set." "0,1"
|
|
bitfld.long 0x2 4.--6. "IBANK,Internal Bank setup of SDRAM devices." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2 0.--2. "PAGESIGE,Page Size." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SDRAM_RCR,SDRAM Refresh Control Register"
|
|
hexmask.long.word 0x4 0.--12. 1. "REFRESH_RATE,Refresh Rate."
|
|
line.long 0x6 "ASYNC_CS2_CR,Async 1 (EMxCS2n) Config Register"
|
|
bitfld.long 0x6 31. "SS,Select Strobe mode." "0,1"
|
|
bitfld.long 0x6 30. "EW,Extend Wait mode." "0,1"
|
|
hexmask.long.byte 0x6 26.--29. 1. "W_SETUP,Write Strobe Setup cycles."
|
|
hexmask.long.byte 0x6 20.--25. 1. "W_STROBE,Write Strobe Duration cycles."
|
|
bitfld.long 0x6 17.--19. "W_HOLD,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x6 13.--16. 1. "R_SETUP,Read Strobe Setup cycles."
|
|
hexmask.long.byte 0x6 7.--12. 1. "R_STROBE,Read Strobe Duration cycles."
|
|
bitfld.long 0x6 4.--6. "R_HOLD,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x6 2.--3. "TA,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "ASIZE,Asynchronous Memory Size." "0,1,2,3"
|
|
line.long 0x8 "ASYNC_CS3_CR,Async 2 (EMxCS3n) Config Register"
|
|
bitfld.long 0x8 31. "SS,Select Strobe mode." "0,1"
|
|
bitfld.long 0x8 30. "EW,Extend Wait mode." "0,1"
|
|
hexmask.long.byte 0x8 26.--29. 1. "W_SETUP,Write Strobe Setup cycles."
|
|
hexmask.long.byte 0x8 20.--25. 1. "W_STROBE,Write Strobe Duration cycles."
|
|
bitfld.long 0x8 17.--19. "W_HOLD,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 13.--16. 1. "R_SETUP,Read Strobe Setup cycles."
|
|
hexmask.long.byte 0x8 7.--12. 1. "R_STROBE,Read Strobe Duration cycles."
|
|
bitfld.long 0x8 4.--6. "R_HOLD,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. "TA,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "ASIZE,Asynchronous Memory Size." "0,1,2,3"
|
|
line.long 0xA "ASYNC_CS4_CR,Async 3 (EMxCS4n) Config Register"
|
|
bitfld.long 0xA 31. "SS,Select Strobe mode." "0,1"
|
|
bitfld.long 0xA 30. "EW,Extend Wait mode." "0,1"
|
|
hexmask.long.byte 0xA 26.--29. 1. "W_SETUP,Write Strobe Setup cycles."
|
|
hexmask.long.byte 0xA 20.--25. 1. "W_STROBE,Write Strobe Duration cycles."
|
|
bitfld.long 0xA 17.--19. "W_HOLD,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xA 13.--16. 1. "R_SETUP,Read Strobe Setup cycles."
|
|
hexmask.long.byte 0xA 7.--12. 1. "R_STROBE,Read Strobe Duration cycles."
|
|
bitfld.long 0xA 4.--6. "R_HOLD,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xA 2.--3. "TA,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "ASIZE,Asynchronous Memory Size." "0,1,2,3"
|
|
line.long 0xE "SDRAM_TR,SDRAM Timing Register"
|
|
hexmask.long.byte 0xE 27.--31. 1. "T_RFC,Refresh/Load Mode to Refresh/Activate timing"
|
|
bitfld.long 0xE 24.--26. "T_RP,Precharge to Activate/Refresh timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xE 20.--22. "T_RCD,Activate to Read/Write timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xE 16.--18. "T_WR,Last Write to Precharge timing." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xE 12.--15. 1. "T_RAS,Activate to Precharge timing."
|
|
newline
|
|
hexmask.long.byte 0xE 8.--11. 1. "T_RC,Activate to Activate timing ."
|
|
bitfld.long 0xE 4.--6. "T_RRD,Activate to Activate timing for different bank." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "TOTAL_SDRAM_AR,Total SDRAM Accesses Register"
|
|
hexmask.long 0x0 0.--31. 1. "TOTAL_SDRAM_AR,Total number of accesses to SDRAM from master side"
|
|
line.long 0x2 "TOTAL_SDRAM_ACTR,Total SDRAM Activate Register"
|
|
hexmask.long 0x2 0.--31. 1. "TOTAL_SDRAM_ACTR,Number of SDRAM accesses which required an activate command."
|
|
group.long 0x1E++0x13
|
|
line.long 0x0 "SDR_EXT_TMNG,SDRAM SR/PD Exit Timing Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "T_XS,Self Refresh exit to new command timing."
|
|
line.long 0x2 "INT_RAW,Interrupt Raw Register"
|
|
hexmask.long.byte 0x2 2.--5. 1. "WR,Wait Rise."
|
|
bitfld.long 0x2 1. "LT,Line Trap." "0,1"
|
|
bitfld.long 0x2 0. "AT,Asynchronous Timeout." "0,1"
|
|
line.long 0x4 "INT_MSK,Interrupt Masked Register"
|
|
hexmask.long.byte 0x4 2.--5. 1. "WR_MASKED,Wait Rise."
|
|
bitfld.long 0x4 1. "LT_MASKED,Line Trap." "0,1"
|
|
bitfld.long 0x4 0. "AT_MASKED,Asynchronous Timeout." "0,1"
|
|
line.long 0x6 "INT_MSK_SET,Interrupt Mask Set Register"
|
|
hexmask.long.byte 0x6 2.--5. 1. "WR_MASK_SET,Wait Rise."
|
|
bitfld.long 0x6 1. "LT_MASK_SET,Line Trap." "0,1"
|
|
bitfld.long 0x6 0. "AT_MASK_SET,Asynchronous Timeout." "0,1"
|
|
line.long 0x8 "INT_MSK_CLR,Interrupt Mask Clear Register"
|
|
hexmask.long.byte 0x8 2.--5. 1. "WR_MASK_CLR,Wait Rise."
|
|
bitfld.long 0x8 1. "LT_MASK_CLR,Line Trap." "0,1"
|
|
bitfld.long 0x8 0. "AT_MASK_CLR,Asynchronous Timeout." "0,1"
|
|
tree.end
|
|
tree "EMIF1_CONFIG"
|
|
base d:0x5F4C0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "EMIF1LOCK,EMIF1 Config Lock Register"
|
|
bitfld.long 0x0 0. "LOCK_EMIF1,EMIF1 access protection and master select fields lock bit" "0,1"
|
|
line.long 0x2 "EMIF1COMMIT,EMIF1 Config Lock Commit Register"
|
|
bitfld.long 0x2 0. "COMMIT_EMIF1,EMIF1 access protection and master select permanent lock" "0,1"
|
|
line.long 0x4 "EMIF1MSEL,EMIF1 Master Sel Register"
|
|
hexmask.long 0x4 4.--31. 1. "KEY,KEY to enable the write into MSEL_EMIF1 bits"
|
|
bitfld.long 0x4 0.--1. "MSEL_EMIF1,Master Select for EMIF1." "0,1,2,3"
|
|
line.long 0x8 "EMIF1ACCPROT0,EMIF1 Config Register 0"
|
|
bitfld.long 0x8 2. "DMAWRPROT_EMIF1,DMA WR Protection For EMIF1" "0,1"
|
|
bitfld.long 0x8 1. "CPUWRPROT_EMIF1,CPU WR Protection For EMIF1" "0,1"
|
|
bitfld.long 0x8 0. "FETCHPROT_EMIF1,Fetch Protection For EMIF1" "0,1"
|
|
tree.end
|
|
tree "EMIF2"
|
|
base d:0x47800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RCSR,Revision Code and Status Register"
|
|
bitfld.long 0x0 31. "BE,EMIF endian mode." "0,1"
|
|
bitfld.long 0x0 30. "FR,EMIF is running in full rate or half rate." "0,1"
|
|
hexmask.long.word 0x0 16.--29. 1. "MODULE_ID,EMIF module ID."
|
|
hexmask.long.byte 0x0 8.--15. 1. "MAJOR_REVISION,Major Revision."
|
|
hexmask.long.byte 0x0 0.--7. 1. "MINOR_REVISION,Minor Revision."
|
|
group.long 0x2++0x1B
|
|
line.long 0x0 "ASYNC_WCCR,Async Wait Cycle Config Register"
|
|
bitfld.long 0x0 28. "WP0,Polarity for EMxWAIT." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MAX_EXT_WAIT,Maximum Extended Wait cycles."
|
|
line.long 0x2 "SDRAM_CR,SDRAM (EMxCS0n) Config Register"
|
|
bitfld.long 0x2 31. "SR,Self Refresh." "0,1"
|
|
bitfld.long 0x2 30. "PD,Power Down." "0,1"
|
|
bitfld.long 0x2 29. "PDWR,Perform refreshes during Power Down." "0,1"
|
|
bitfld.long 0x2 14. "NM,Narrow Mode." "0,1"
|
|
bitfld.long 0x2 9.--11. "CL,CAS Latency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x2 8. "BIT_11_9_LOCK,Bits 11 to 9 are writable only if this bit is set." "0,1"
|
|
bitfld.long 0x2 4.--6. "IBANK,Internal Bank setup of SDRAM devices." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2 0.--2. "PAGESIGE,Page Size." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SDRAM_RCR,SDRAM Refresh Control Register"
|
|
hexmask.long.word 0x4 0.--12. 1. "REFRESH_RATE,Refresh Rate."
|
|
line.long 0x6 "ASYNC_CS2_CR,Async 1 (EMxCS2n) Config Register"
|
|
bitfld.long 0x6 31. "SS,Select Strobe mode." "0,1"
|
|
bitfld.long 0x6 30. "EW,Extend Wait mode." "0,1"
|
|
hexmask.long.byte 0x6 26.--29. 1. "W_SETUP,Write Strobe Setup cycles."
|
|
hexmask.long.byte 0x6 20.--25. 1. "W_STROBE,Write Strobe Duration cycles."
|
|
bitfld.long 0x6 17.--19. "W_HOLD,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x6 13.--16. 1. "R_SETUP,Read Strobe Setup cycles."
|
|
hexmask.long.byte 0x6 7.--12. 1. "R_STROBE,Read Strobe Duration cycles."
|
|
bitfld.long 0x6 4.--6. "R_HOLD,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x6 2.--3. "TA,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "ASIZE,Asynchronous Memory Size." "0,1,2,3"
|
|
line.long 0x8 "ASYNC_CS3_CR,Async 2 (EMxCS3n) Config Register"
|
|
bitfld.long 0x8 31. "SS,Select Strobe mode." "0,1"
|
|
bitfld.long 0x8 30. "EW,Extend Wait mode." "0,1"
|
|
hexmask.long.byte 0x8 26.--29. 1. "W_SETUP,Write Strobe Setup cycles."
|
|
hexmask.long.byte 0x8 20.--25. 1. "W_STROBE,Write Strobe Duration cycles."
|
|
bitfld.long 0x8 17.--19. "W_HOLD,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 13.--16. 1. "R_SETUP,Read Strobe Setup cycles."
|
|
hexmask.long.byte 0x8 7.--12. 1. "R_STROBE,Read Strobe Duration cycles."
|
|
bitfld.long 0x8 4.--6. "R_HOLD,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. "TA,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "ASIZE,Asynchronous Memory Size." "0,1,2,3"
|
|
line.long 0xA "ASYNC_CS4_CR,Async 3 (EMxCS4n) Config Register"
|
|
bitfld.long 0xA 31. "SS,Select Strobe mode." "0,1"
|
|
bitfld.long 0xA 30. "EW,Extend Wait mode." "0,1"
|
|
hexmask.long.byte 0xA 26.--29. 1. "W_SETUP,Write Strobe Setup cycles."
|
|
hexmask.long.byte 0xA 20.--25. 1. "W_STROBE,Write Strobe Duration cycles."
|
|
bitfld.long 0xA 17.--19. "W_HOLD,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xA 13.--16. 1. "R_SETUP,Read Strobe Setup cycles."
|
|
hexmask.long.byte 0xA 7.--12. 1. "R_STROBE,Read Strobe Duration cycles."
|
|
bitfld.long 0xA 4.--6. "R_HOLD,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xA 2.--3. "TA,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "ASIZE,Asynchronous Memory Size." "0,1,2,3"
|
|
line.long 0xE "SDRAM_TR,SDRAM Timing Register"
|
|
hexmask.long.byte 0xE 27.--31. 1. "T_RFC,Refresh/Load Mode to Refresh/Activate timing"
|
|
bitfld.long 0xE 24.--26. "T_RP,Precharge to Activate/Refresh timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xE 20.--22. "T_RCD,Activate to Read/Write timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xE 16.--18. "T_WR,Last Write to Precharge timing." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xE 12.--15. 1. "T_RAS,Activate to Precharge timing."
|
|
newline
|
|
hexmask.long.byte 0xE 8.--11. 1. "T_RC,Activate to Activate timing ."
|
|
bitfld.long 0xE 4.--6. "T_RRD,Activate to Activate timing for different bank." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "TOTAL_SDRAM_AR,Total SDRAM Accesses Register"
|
|
hexmask.long 0x0 0.--31. 1. "TOTAL_SDRAM_AR,Total number of accesses to SDRAM from master side"
|
|
line.long 0x2 "TOTAL_SDRAM_ACTR,Total SDRAM Activate Register"
|
|
hexmask.long 0x2 0.--31. 1. "TOTAL_SDRAM_ACTR,Number of SDRAM accesses which required an activate command."
|
|
group.long 0x1E++0x13
|
|
line.long 0x0 "SDR_EXT_TMNG,SDRAM SR/PD Exit Timing Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "T_XS,Self Refresh exit to new command timing."
|
|
line.long 0x2 "INT_RAW,Interrupt Raw Register"
|
|
hexmask.long.byte 0x2 2.--5. 1. "WR,Wait Rise."
|
|
bitfld.long 0x2 1. "LT,Line Trap." "0,1"
|
|
bitfld.long 0x2 0. "AT,Asynchronous Timeout." "0,1"
|
|
line.long 0x4 "INT_MSK,Interrupt Masked Register"
|
|
hexmask.long.byte 0x4 2.--5. 1. "WR_MASKED,Wait Rise."
|
|
bitfld.long 0x4 1. "LT_MASKED,Line Trap." "0,1"
|
|
bitfld.long 0x4 0. "AT_MASKED,Asynchronous Timeout." "0,1"
|
|
line.long 0x6 "INT_MSK_SET,Interrupt Mask Set Register"
|
|
hexmask.long.byte 0x6 2.--5. 1. "WR_MASK_SET,Wait Rise."
|
|
bitfld.long 0x6 1. "LT_MASK_SET,Line Trap." "0,1"
|
|
bitfld.long 0x6 0. "AT_MASK_SET,Asynchronous Timeout." "0,1"
|
|
line.long 0x8 "INT_MSK_CLR,Interrupt Mask Clear Register"
|
|
hexmask.long.byte 0x8 2.--5. 1. "WR_MASK_CLR,Wait Rise."
|
|
bitfld.long 0x8 1. "LT_MASK_CLR,Line Trap." "0,1"
|
|
bitfld.long 0x8 0. "AT_MASK_CLR,Asynchronous Timeout." "0,1"
|
|
tree.end
|
|
tree "EMIF2_CONFIG"
|
|
base d:0x5F4E0
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "EMIF2LOCK,EMIF2 Config Lock Register"
|
|
bitfld.long 0x0 0. "LOCK_EMIF2,EMIF2 access protection and master select permanent lock" "0,1"
|
|
line.long 0x2 "EMIF2COMMIT,EMIF2 Config Lock Commit Register"
|
|
bitfld.long 0x2 0. "COMMIT_EMIF2,EMIF2 access protection and master select permanent lock" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "EMIF2ACCPROT0,EMIF2 Config Register 0"
|
|
bitfld.long 0x0 1. "CPUWRPROT_EMIF2,CPU WR Protection For EMIF2" "0,1"
|
|
bitfld.long 0x0 0. "FETCHPROT_EMIF2,Fetch Protection For EMIF2" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "EPWM (Enhanced Pulse Width Modulator)"
|
|
base d:0x0
|
|
tree "EPWM1"
|
|
base d:0x4000
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
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rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
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bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
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rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
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|
newline
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
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line.word 0x1 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
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bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
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rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
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|
newline
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bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
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bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
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bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
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group.word 0xC7++0x5
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line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
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rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
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bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
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bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
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bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
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newline
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bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
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bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
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line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
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bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
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bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
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rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
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bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
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bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
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line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
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hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
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rgroup.word 0xCA++0x1
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line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
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hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
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group.word 0xCB++0x1
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line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
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hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
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rgroup.word 0xCC++0x1
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line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
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hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
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rgroup.word 0xCF++0x1
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line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
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hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
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group.word 0xD2++0x7
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line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
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bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
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newline
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bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
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newline
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bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
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line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
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bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
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newline
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bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
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newline
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bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
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line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
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bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
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newline
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bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
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newline
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bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
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bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
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line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
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bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
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newline
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bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
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newline
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bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
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bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
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group.long 0xFA++0x3
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line.long 0x0 "EPWMLOCK,EPWM Lock Register"
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hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
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bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
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bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
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bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
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bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
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bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
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rgroup.word 0xFD++0x3
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line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
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hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
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line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
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hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
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tree.end
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tree "EPWM2"
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base d:0x4100
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group.word 0x0++0x11
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line.word 0x0 "TBCTL,Time Base Control Register"
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bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
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bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
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bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
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bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
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newline
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bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
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bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
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line.word 0x1 "TBCTL2,Time Base Control Register 2"
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bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
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bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
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bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
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line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
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hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
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line.word 0x4 "TBCTR,Time Base Counter Register"
|
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hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
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line.word 0x5 "TBSTS,Time Base Status Register"
|
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bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
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bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
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rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
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line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
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bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
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bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
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bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
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bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
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bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
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bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
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newline
|
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bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
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line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
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hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
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bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
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line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
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bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
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rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
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rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
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bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
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bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
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bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
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|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
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hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
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line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
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hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
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line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
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hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
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hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
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group.word 0x62++0x3
|
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line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
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group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
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hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
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line.long 0x2 "CMPB,Compare B Register"
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hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
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hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
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group.word 0x6F++0x3
|
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line.word 0x0 "CMPC,Counter Compare C Register"
|
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hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
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line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
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group.word 0x74++0x1
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line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
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bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
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group.word 0x77++0x1
|
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line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
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hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
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group.word 0x80++0xB
|
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line.word 0x0 "TZSEL,Trip Zone Select Register"
|
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bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
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bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
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bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
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bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
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bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
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bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
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bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
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bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
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bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
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bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
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bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
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bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
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newline
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
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bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
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bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
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bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
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line.word 0x4 "TZCTL,Trip Zone Control Register"
|
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bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
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bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
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bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
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bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
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bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
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bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
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line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
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bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
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bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM3"
|
|
base d:0x4200
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
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|
newline
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bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
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|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
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|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
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bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
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bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
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group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
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|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
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bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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|
newline
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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line.word 0x4 "TZFRC,Trip Zone Force Register"
|
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bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
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bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
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bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word 0xA4++0x3
|
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line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
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bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
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bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
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bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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newline
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word 0xA8++0x1
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line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
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group.word 0xAA++0xB
|
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line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
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line.word 0x2 "ETFRC,Event Trigger Force Register"
|
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bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
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bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
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line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
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hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
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hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
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line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
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hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
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hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
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hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
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hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
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line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
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bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
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bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
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bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
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bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
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line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
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hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
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hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
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hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
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group.word 0xC0++0x1
|
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line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
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hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
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hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
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hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
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group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
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|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
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|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
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|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM4"
|
|
base d:0x4300
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
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bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
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bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM5"
|
|
base d:0x4400
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
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|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
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|
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
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bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
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hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
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hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
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hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
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|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
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|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
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|
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
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bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
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bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
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|
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bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
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|
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bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
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|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
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|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM6"
|
|
base d:0x4500
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM7"
|
|
base d:0x4600
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
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|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
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bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
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bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
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line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
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line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
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hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
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line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
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|
line.long 0x0 "TBPHS,Time Base Phase High"
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hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
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group.word 0x62++0x3
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line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
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hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
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line.word 0x1 "TBPRD,Time Base Period Register"
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hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
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group.long 0x6A++0x7
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|
line.long 0x0 "CMPA,Counter Compare A Register"
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hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
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hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
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hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word 0x6F++0x3
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line.word 0x0 "CMPC,Counter Compare C Register"
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hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
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line.word 0x2 "CMPD,Counter Compare D Register"
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hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
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group.word 0x74++0x1
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line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
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bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
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hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
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|
group.word 0x80++0xB
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line.word 0x0 "TZSEL,Trip Zone Select Register"
|
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bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
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bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
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|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
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|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
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|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
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|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
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|
newline
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bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
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|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
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|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
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|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
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|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
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bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
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|
newline
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
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bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
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|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
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bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
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|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
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line.word 0x4 "TZCTL,Trip Zone Control Register"
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bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
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bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
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bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
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bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
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line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
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bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
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bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
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bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
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bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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group.word 0x8D++0x1
|
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line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
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bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
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rgroup.word 0x93++0x5
|
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line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
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bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
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bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM8"
|
|
base d:0x4700
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
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|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
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|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
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bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
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|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
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|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word 0x8D++0x1
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line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
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bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word 0x93++0x5
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line.word 0x0 "TZFLG,Trip Zone Flag Register"
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bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
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bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
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bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
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line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
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bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
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bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
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bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
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line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
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bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
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bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
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bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word 0x97++0x7
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line.word 0x0 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
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bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
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bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
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bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
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line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
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bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
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bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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line.word 0x4 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
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bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word 0xA4++0x3
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line.word 0x0 "ETSEL,Event Trigger Selection Register"
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bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
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bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
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bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
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bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word 0xA8++0x1
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line.word 0x0 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
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group.word 0xAA++0xB
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line.word 0x0 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
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line.word 0x2 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
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bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
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bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
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line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
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hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
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line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
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hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
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hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
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hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
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line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
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line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
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hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
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hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
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hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
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group.word 0xC0++0x1
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line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
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hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
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hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
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hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
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hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
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group.word 0xC3++0x3
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line.word 0x0 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
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rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
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line.word 0x1 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
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bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
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rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
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bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
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bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
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bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
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group.word 0xC7++0x5
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line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
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rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
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bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
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bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
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bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
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bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
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bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
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line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
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bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
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bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
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rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
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bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
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bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
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line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
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line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
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group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word 0xCC++0x1
|
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line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
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hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
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bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
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|
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bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
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bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
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|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM9"
|
|
base d:0x4800
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
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bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
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line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
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rgroup.word 0xCA++0x1
|
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line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
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group.word 0xCB++0x1
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line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word 0xCC++0x1
|
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line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
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hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
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group.word 0xD2++0x7
|
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line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
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bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
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bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
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bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM10"
|
|
base d:0x4900
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
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bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
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bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
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bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
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|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
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bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
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bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
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line.word 0x1 "HRPWR,HRPWM Power Register"
|
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bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
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group.word 0x26++0x3
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line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
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hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
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line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
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bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
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group.word 0x2D++0x3
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line.word 0x0 "HRPCTL,High Resolution Period Control Register"
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bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
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bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
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bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
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line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
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hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
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group.word 0x34++0x3
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line.word 0x0 "GLDCTL,Global PWM Load Control Register"
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rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
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hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
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bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
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line.word 0x1 "GLDCFG,Global PWM Load Config Register"
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bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
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bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
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bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
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bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
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bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
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bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
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bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
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bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
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bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
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bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
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bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
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group.long 0x38++0x3
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line.long 0x0 "EPWMXLINK,EPWMx Link Register"
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hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
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hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
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hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
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hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
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hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
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hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
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group.word 0x40++0x7
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line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
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bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
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bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
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line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
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bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
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bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
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bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
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line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
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bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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group.word 0x47++0x3
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line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
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bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
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bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
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bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
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bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
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bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
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line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
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bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
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bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
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group.word 0x50++0x7
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line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
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line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
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line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
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hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
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line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
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group.long 0x60++0x3
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line.long 0x0 "TBPHS,Time Base Phase High"
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hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word 0x62++0x3
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line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
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hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
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line.word 0x1 "TBPRD,Time Base Period Register"
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hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
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group.long 0x6A++0x7
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line.long 0x0 "CMPA,Counter Compare A Register"
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hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
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line.long 0x2 "CMPB,Compare B Register"
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hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
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hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word 0x6F++0x3
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line.word 0x0 "CMPC,Counter Compare C Register"
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hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
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line.word 0x2 "CMPD,Counter Compare D Register"
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hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
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group.word 0x74++0x1
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line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
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bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
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bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
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group.word 0x77++0x1
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line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
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hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
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group.word 0x80++0xB
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line.word 0x0 "TZSEL,Trip Zone Select Register"
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bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
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bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
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bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
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bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
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bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
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bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
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bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
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bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
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bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
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bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
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bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
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bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
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newline
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
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bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
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bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
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bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
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line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
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bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
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line.word 0x4 "TZCTL,Trip Zone Control Register"
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bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
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bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
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bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
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bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
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line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
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bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
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bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word 0x8D++0x1
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line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
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bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
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bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
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bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
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group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
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bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
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newline
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bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM11"
|
|
base d:0x4A00
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
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bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
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|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word 0x8D++0x1
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|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word 0x93++0x5
|
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line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
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bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
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bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
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bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
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bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
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bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
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line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word 0x97++0x7
|
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line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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|
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|
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
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bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
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|
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
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bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
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newline
|
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word 0xA8++0x1
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line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
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line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
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hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
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line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
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hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
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hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
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hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
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hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
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hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
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hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
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hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
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group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
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|
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
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|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
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|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
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bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM12"
|
|
base d:0x4B00
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
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bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
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|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
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bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
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bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
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bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM13"
|
|
base d:0x4C00
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
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|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
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group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
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|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
|
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
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|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
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group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
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bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
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bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
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bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
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bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
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bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
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bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
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bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
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bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word 0xA8++0x1
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line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
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bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
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group.word 0xAA++0xB
|
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line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
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line.word 0x2 "ETFRC,Event Trigger Force Register"
|
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bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
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bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
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line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
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hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
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hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
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line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
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hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
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hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
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hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
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hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
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line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
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hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
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group.word 0xC0++0x1
|
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line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
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hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
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hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
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hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
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hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
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group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
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|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
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|
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
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bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
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|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
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bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
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group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
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bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
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bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
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bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
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line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
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rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
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line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
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|
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bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
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|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
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|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM14"
|
|
base d:0x4D00
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
|
group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
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|
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bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
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|
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
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bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
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line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
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bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
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bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
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line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
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bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
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bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word 0x8D++0x1
|
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line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
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|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
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|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
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bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
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|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
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|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
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|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
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|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
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line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
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bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
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bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
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bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word 0x97++0x7
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line.word 0x0 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
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bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
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bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
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bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
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bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
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line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
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bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
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|
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bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
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line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
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bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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line.word 0x4 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
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bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word 0xA4++0x3
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line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
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bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
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bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
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bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
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rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
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bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
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newline
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word 0xA8++0x1
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line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
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group.word 0xAA++0xB
|
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line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
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bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
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bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
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bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
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line.word 0x2 "ETFRC,Event Trigger Force Register"
|
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bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
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hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
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line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
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hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
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hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
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|
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
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|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM15"
|
|
base d:0x4E00
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
|
|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
|
|
line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
|
|
bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
|
|
line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
|
|
hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
|
|
bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
|
|
group.word 0x18++0x3
|
|
line.word 0x0 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
|
|
bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
|
|
line.word 0x1 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
|
|
rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
|
|
hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
line.word 0x1 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
|
|
group.word 0x26++0x3
|
|
line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word 0x2D++0x3
|
|
line.word 0x0 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
|
|
line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
|
|
hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
|
|
bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
|
|
line.word 0x1 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
|
|
bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
|
|
bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EPWMXLINK,EPWMx Link Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
|
|
group.word 0x40++0x7
|
|
line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
|
|
bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
|
|
line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word 0x47++0x3
|
|
line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word 0x50++0x7
|
|
line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
|
|
line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
|
|
line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
|
|
line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TBPHS,Time Base Phase High"
|
|
hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word 0x62++0x3
|
|
line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
|
|
hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
|
|
line.word 0x1 "TBPRD,Time Base Period Register"
|
|
hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
|
|
group.long 0x6A++0x7
|
|
line.long 0x0 "CMPA,Counter Compare A Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
line.long 0x2 "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word 0x6F++0x3
|
|
line.word 0x0 "CMPC,Counter Compare C Register"
|
|
hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
|
line.word 0x2 "CMPD,Counter Compare D Register"
|
|
hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
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group.word 0x74++0x1
|
|
line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
|
line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
|
group.word 0x80++0xB
|
|
line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
|
bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
|
|
newline
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|
bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
|
|
newline
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
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|
bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
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bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
newline
|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word 0x97++0x7
|
|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
line.word 0x4 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
|
bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
newline
|
|
rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
|
hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
newline
|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree "EPWM16"
|
|
base d:0x4F00
|
|
group.word 0x0++0x11
|
|
line.word 0x0 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 6. "SWFSYNC,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x0 3. "PRDLD,Active Period Load" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "PHSEN,Phase Load Enable" "0,1"
|
|
bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode" "0,1,2,3"
|
|
line.word 0x1 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x1 14.--15. "PRDLDSYNC,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x1 7. "OSHTSYNC,One shot sync" "0,1"
|
|
bitfld.word 0x1 6. "OSHTSYNCMODE,One shot sync mode" "0,1"
|
|
line.word 0x3 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
hexmask.word.byte 0x3 0.--4. 1. "SEL,EPWMxSYNCI source select"
|
|
line.word 0x4 "TBCTR,Time Base Counter Register"
|
|
hexmask.word 0x4 0.--15. 1. "TBCTR,Counter Value"
|
|
line.word 0x5 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x5 2. "CTRMAX,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x5 1. "SYNCI,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x5 0. "CTRDIR,Counter Direction Status" "0,1"
|
|
line.word 0x6 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x6 6. "DCBEVT1EN,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 5. "DCAEVT1EN,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x6 4. "CMPDEN,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x6 3. "CMPCEN,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
bitfld.word 0x6 2. "CMPBEN,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x6 1. "ZEROEN,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "SWEN,EPWMxSYNCO Software Force Enable" "0,1"
|
|
line.word 0x7 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x7 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x7 0. "OSSFRCEN,One Shot Sync Force Enable" "0,1"
|
|
line.word 0x8 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x8 12.--13. "LOADBSYNC,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x8 10.--11. "LOADASYNC,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x8 9. "SHDWBFULL,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x8 8. "SHDWAFULL,Compare A Shadow Register Full Status" "0,1"
|
|
bitfld.word 0x8 6. "SHDWBMODE,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x8 4. "SHDWAMODE,Compare A Register Block Operating Mode" "0,1"
|
|
newline
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bitfld.word 0x8 2.--3. "LOADBMODE,Active Compare B Load" "0,1,2,3"
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bitfld.word 0x8 0.--1. "LOADAMODE,Active Compare A Load" "0,1,2,3"
|
|
line.word 0x9 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x9 12.--13. "LOADDSYNC,Active Compare D Load on SYNC" "0,1,2,3"
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bitfld.word 0x9 10.--11. "LOADCSYNC,Active Compare C Load on SYNC" "0,1,2,3"
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|
bitfld.word 0x9 6. "SHDWDMODE,Compare D Block Operating Mode" "0,1"
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|
bitfld.word 0x9 4. "SHDWCMODE,Compare C Block Operating Mode" "0,1"
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|
bitfld.word 0x9 2.--3. "LOADDMODE,Active Compare D load" "0,1,2,3"
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|
bitfld.word 0x9 0.--1. "LOADCMODE,Active Compare C Load" "0,1,2,3"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "DBCTL,Dead-Band Generator Control Register"
|
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bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable" "0,1"
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bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control" "0,1"
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bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control" "0,1,2,3"
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bitfld.word 0x0 11. "SHDWDBFEDMODE,DBFED Block Operating Mode" "0,1"
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|
bitfld.word 0x0 10. "SHDWDBREDMODE,DBRED Block Operating Mode" "0,1"
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bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load Mode" "0,1,2,3"
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|
newline
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bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load Mode" "0,1,2,3"
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bitfld.word 0x0 4.--5. "IN_MODE,Dead Band Input Select Mode Control" "0,1,2,3"
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bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3"
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bitfld.word 0x0 0.--1. "OUT_MODE,Dead Band Output Mode Control" "0,1,2,3"
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line.word 0x1 "DBCTL2,Dead-Band Generator Control Register 2"
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bitfld.word 0x1 2. "SHDWDBCTLMODE,DBCTL Load mode Select" "0,1"
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bitfld.word 0x1 0.--1. "LOADDBCTLMODE,DBCTL Load from Shadow Mode Select" "0,1,2,3"
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group.word 0x10++0x3
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line.word 0x0 "AQCTL,Action Qualifier Control Register"
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bitfld.word 0x0 10.--11. "LDAQBSYNC,AQCTLB Register Load on SYNC" "0,1,2,3"
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bitfld.word 0x0 8.--9. "LDAQASYNC,AQCTLA Register Load on SYNC" "0,1,2,3"
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bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Operating Mode" "0,1"
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bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifer A Operating Mode" "0,1"
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bitfld.word 0x0 2.--3. "LDAQBMODE,Action Qualifier B Load Select" "0,1,2,3"
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bitfld.word 0x0 0.--1. "LDAQAMODE,Action Qualifier A Load Select" "0,1,2,3"
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line.word 0x1 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
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hexmask.word.byte 0x1 4.--7. 1. "T2SEL,T2 Event Source Select Bits"
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hexmask.word.byte 0x1 0.--3. 1. "T1SEL,T1 Event Source Select Bits"
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group.word 0x14++0x1
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line.word 0x0 "PCCTL,PWM Chopper Control Register"
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bitfld.word 0x0 8.--10. "CHPDUTY,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 5.--7. "CHPFREQ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
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hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-shot pulse width"
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bitfld.word 0x0 0. "CHPEN,PWM chopping enable" "0,1"
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group.word 0x18++0x3
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line.word 0x0 "VCAPCTL,Valley Capture Control Register"
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bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Select" "0,1"
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bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 2.--4. "TRIGSEL,Capture Trigger Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start" "0,1"
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bitfld.word 0x0 0. "VCAPE,Valley Capture mode" "0,1"
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line.word 0x1 "VCNTCFG,Valley Counter Config Register"
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rbitfld.word 0x1 15. "STOPEDGESTS,Stop Edge Status Bit" "0,1"
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hexmask.word.byte 0x1 8.--11. 1. "STOPEDGE,Counter Start Edge Selection"
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rbitfld.word 0x1 7. "STARTEDGESTS,Start Edge Status Bit" "0,1"
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hexmask.word.byte 0x1 0.--3. 1. "STARTEDGE,Counter Start Edge Selection"
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group.word 0x20++0x3
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line.word 0x0 "HRCNFG,HRPWM Configuration Register"
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bitfld.word 0x0 11.--12. "HRLOADB,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x0 10. "CTLMODEB,ePWMxB Control Mode Select Bits" "0,1"
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bitfld.word 0x0 8.--9. "EDGMODEB,ePWMxB Edge Mode Select Bits" "0,1,2,3"
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bitfld.word 0x0 7. "SWAPAB,Swap EPWMA and EPWMB Outputs Bit" "0,1"
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bitfld.word 0x0 6. "AUTOCONV,Autoconversion Bit" "0,1"
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bitfld.word 0x0 5. "SELOUTB,EPWMB Output Selection Bit" "0,1"
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bitfld.word 0x0 3.--4. "HRLOAD,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x0 2. "CTLMODE,ePWMxA Control Mode Select Bits" "0,1"
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bitfld.word 0x0 0.--1. "EDGMODE,ePWMxA Edge Mode Select Bits" "0,1,2,3"
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line.word 0x1 "HRPWR,HRPWM Power Register"
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bitfld.word 0x1 15. "CALPWRON,Calibration Power On" "0,1"
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group.word 0x26++0x3
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line.word 0x0 "HRMSTEP,HRPWM MEP Step Register"
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hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
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line.word 0x1 "HRCNFG2,HRPWM Configuration 2 Register"
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bitfld.word 0x1 4.--5. "CTLMODEDBFED,DBFED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x1 2.--3. "CTLMODEDBRED,DBRED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x1 0.--1. "EDGMODEDB,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
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group.word 0x2D++0x3
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line.word 0x0 "HRPCTL,High Resolution Period Control Register"
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bitfld.word 0x0 4.--6. "PWMSYNCSELX,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable" "0,1"
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bitfld.word 0x0 1. "PWMSYNCSEL,EPWMSYNCPER Source Select" "0,1"
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bitfld.word 0x0 0. "HRPE,High Resolution Period Enable" "0,1"
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line.word 0x1 "TRREM,Translator High Resolution Remainder Register"
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hexmask.word 0x1 0.--10. 1. "TRREM,Translator Remainder Bits"
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group.word 0x34++0x3
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line.word 0x0 "GLDCTL,Global PWM Load Control Register"
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rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x0 5. "OSHTMODE,One Shot Load mode control bit" "0,1"
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hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Shadow to Active Global Load Pulse Selection"
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bitfld.word 0x0 0. "GLD,Global Shadow to Active load event control" "0,1"
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line.word 0x1 "GLDCFG,Global PWM Load Config Register"
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|
bitfld.word 0x1 10. "AQCSFRC,Global load event configuration for AQCSFRC" "0,1"
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bitfld.word 0x1 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB/B2" "0,1"
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bitfld.word 0x1 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA/A2" "0,1"
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bitfld.word 0x1 7. "DBCTL,Global load event configuration for DBCTL" "0,1"
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bitfld.word 0x1 6. "DBFED_DBFEDHR,Global load event configuration for DBFED:DBFEDHR" "0,1"
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bitfld.word 0x1 5. "DBRED_DBREDHR,Global load event configuration for DBRED:DBREDHR" "0,1"
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newline
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bitfld.word 0x1 4. "CMPD,Global load event configuration for CMPD" "0,1"
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bitfld.word 0x1 3. "CMPC,Global load event configuration for CMPC" "0,1"
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bitfld.word 0x1 2. "CMPB_CMPBHR,Global load event configuration for CMPB:CMPBHR" "0,1"
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bitfld.word 0x1 1. "CMPA_CMPAHR,Global load event configuration for CMPA:CMPAHR" "0,1"
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bitfld.word 0x1 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD:TBPRDHR" "0,1"
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group.long 0x38++0x3
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line.long 0x0 "EPWMXLINK,EPWMx Link Register"
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hexmask.long.byte 0x0 28.--31. 1. "GLDCTL2LINK,GLDCTL2 Link"
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hexmask.long.byte 0x0 16.--19. 1. "CMPDLINK,CMPD Link"
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hexmask.long.byte 0x0 12.--15. 1. "CMPCLINK,CMPC Link"
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hexmask.long.byte 0x0 8.--11. 1. "CMPBLINK,CMPB:CMPBHR Link"
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hexmask.long.byte 0x0 4.--7. 1. "CMPALINK,CMPA:CMPAHR Link"
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hexmask.long.byte 0x0 0.--3. 1. "TBPRDLINK,TBPRD:TBPRDHR Link"
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group.word 0x40++0x7
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line.word 0x0 "AQCTLA,Action Qualifier Control Register For Output A"
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bitfld.word 0x0 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x0 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x0 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x0 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
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bitfld.word 0x0 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x0 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
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line.word 0x1 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
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bitfld.word 0x1 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x1 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x1 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x1 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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line.word 0x2 "AQCTLB,Action Qualifier Control Register For Output B"
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bitfld.word 0x2 10.--11. "CBD,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x2 8.--9. "CBU,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x2 6.--7. "CAD,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x2 4.--5. "CAU,Action Counter = Compare A Up" "0,1,2,3"
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bitfld.word 0x2 2.--3. "PRD,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x2 0.--1. "ZRO,Action Counter = Zero" "0,1,2,3"
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line.word 0x3 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
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bitfld.word 0x3 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x3 4.--5. "T2U,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x3 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x3 0.--1. "T1U,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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group.word 0x47++0x3
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line.word 0x0 "AQSFRC,Action Qualifier Software Force Register"
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bitfld.word 0x0 6.--7. "RLDCSF,Reload from Shadow Options" "0,1,2,3"
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bitfld.word 0x0 5. "OTSFB,One-time SW Force A Output" "0,1"
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bitfld.word 0x0 3.--4. "ACTSFB,Action when One-time SW Force B Invoked" "0,1,2,3"
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bitfld.word 0x0 2. "OTSFA,One-time SW Force A Output" "0,1"
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bitfld.word 0x0 0.--1. "ACTSFA,Action when One-time SW Force A Invoked" "0,1,2,3"
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line.word 0x2 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
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bitfld.word 0x2 2.--3. "CSFB,Continuous Software Force on output B" "0,1,2,3"
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bitfld.word 0x2 0.--1. "CSFA,Continuous Software Force on output A" "0,1,2,3"
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group.word 0x50++0x7
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line.word 0x0 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
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hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,DBREDHR High Resolution Bits"
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line.word 0x1 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x1 0.--13. 1. "DBRED,Rising edge delay value"
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line.word 0x2 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
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hexmask.word.byte 0x2 9.--15. 1. "DBFEDHR,DBFEDHR High Resolution Bits"
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line.word 0x3 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x3 0.--13. 1. "DBFED,Falling edge delay value"
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group.long 0x60++0x3
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line.long 0x0 "TBPHS,Time Base Phase High"
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hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word 0x62++0x3
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line.word 0x0 "TBPRDHR,Time Base Period High Resolution Register"
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hexmask.word 0x0 0.--15. 1. "TBPRDHR,High res Time base period register"
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line.word 0x1 "TBPRD,Time Base Period Register"
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hexmask.word 0x1 0.--15. 1. "TBPRD,Time base period register"
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group.long 0x6A++0x7
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line.long 0x0 "CMPA,Counter Compare A Register"
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hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
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line.long 0x2 "CMPB,Compare B Register"
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hexmask.long.word 0x2 16.--31. 1. "CMPB,Compare B Register"
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hexmask.long.word 0x2 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word 0x6F++0x3
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line.word 0x0 "CMPC,Counter Compare C Register"
|
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hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register"
|
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line.word 0x2 "CMPD,Counter Compare D Register"
|
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hexmask.word 0x2 0.--15. 1. "CMPD,Compare D Register"
|
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group.word 0x74++0x1
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line.word 0x0 "GLDCTL2,Global PWM Load Control Register 2"
|
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bitfld.word 0x0 1. "GFRCLD,Force reload event in one shot mode" "0,1"
|
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bitfld.word 0x0 0. "OSHTLD,Enable reload event in one shot mode" "0,1"
|
|
group.word 0x77++0x1
|
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line.word 0x0 "SWVDELVAL,Software Valley Mode Delay Register"
|
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hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software programmed Valley Delay Value"
|
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group.word 0x80++0xB
|
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line.word 0x0 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x0 15. "DCBEVT1,One-shot DCBEVT1 select" "0,1"
|
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bitfld.word 0x0 14. "DCAEVT1,One-shot DCAEVT1 select" "0,1"
|
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bitfld.word 0x0 13. "OSHT6,One-shot TZ6 select" "0,1"
|
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bitfld.word 0x0 12. "OSHT5,One-shot TZ5 select" "0,1"
|
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bitfld.word 0x0 11. "OSHT4,One-shot TZ4 select" "0,1"
|
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bitfld.word 0x0 10. "OSHT3,One-shot TZ3 select" "0,1"
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|
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bitfld.word 0x0 9. "OSHT2,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x0 8. "OSHT1,One-shot TZ1 select" "0,1"
|
|
bitfld.word 0x0 7. "DCBEVT2,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 6. "DCAEVT2,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x0 5. "CBC6,TZ6 CBC select" "0,1"
|
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bitfld.word 0x0 4. "CBC5,TZ5 CBC select" "0,1"
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|
newline
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bitfld.word 0x0 3. "CBC4,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x0 2. "CBC3,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x0 1. "CBC2,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x0 0. "CBC1,TZ1 CBC select" "0,1"
|
|
line.word 0x2 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x2 9.--11. "DCBEVT2,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6.--8. "DCBEVT1,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 3.--5. "DCAEVT2,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0.--2. "DCAEVT1,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x4 10.--11. "DCBEVT2,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 8.--9. "DCBEVT1,EPWMxB action on DCBEVT1" "0,1,2,3"
|
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bitfld.word 0x4 6.--7. "DCAEVT2,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x4 4.--5. "DCAEVT1,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
bitfld.word 0x4 2.--3. "TZB,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x4 0.--1. "TZA,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
line.word 0x5 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x5 15. "ETZE,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x5 9.--11. "TZBD,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 6.--8. "TZBU,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 3.--5. "TZAD,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x5 0.--2. "TZAU,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x6 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x6 9.--11. "DCAEVT2D,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 6.--8. "DCAEVT2U,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--5. "DCAEVT1D,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 0.--2. "DCAEVT1U,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
line.word 0x7 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x7 9.--11. "DCBEVT2D,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 6.--8. "DCBEVT2U,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 3.--5. "DCBEVT1D,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x7 0.--2. "DCBEVT1U,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word 0x8D++0x1
|
|
line.word 0x0 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Int Enable" "0,1"
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|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Int Enable" "0,1"
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|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word 0x93++0x5
|
|
line.word 0x0 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x0 6. "DCBEVT2,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,Digital Compare A Event 1 Flag" "0,1"
|
|
bitfld.word 0x0 2. "OST,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x0 1. "CBC,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x0 0. "INT,Global Int Status Flag" "0,1"
|
|
line.word 0x1 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Latched Status Flag for CBC6 Trip Latch" "0,1"
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|
bitfld.word 0x1 4. "CBC5,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
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bitfld.word 0x1 1. "CBC2,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
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bitfld.word 0x2 1. "OST2,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x2 0. "OST1,Latched Status Flag for OST1 Trip Latch" "0,1"
|
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group.word 0x97++0x7
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|
line.word 0x0 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x0 6. "DCBEVT2,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "DCBEVT1,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "DCAEVT2,DCAEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "DCAEVT1,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "OST,One-Shot Flag Clear" "0,1"
|
|
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|
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bitfld.word 0x0 1. "CBC,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1"
|
|
line.word 0x1 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x1 7. "DCBEVT2,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 6. "DCAEVT2,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x1 5. "CBC6,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x1 4. "CBC5,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
bitfld.word 0x1 3. "CBC4,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x1 2. "CBC3,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x1 1. "CBC2,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x1 0. "CBC1,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
line.word 0x2 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x2 7. "DCBEVT1,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 6. "DCAEVT1,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x2 5. "OST6,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x2 4. "OST5,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
bitfld.word 0x2 3. "OST4,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x2 2. "OST3,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
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bitfld.word 0x2 1. "OST2,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
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bitfld.word 0x2 0. "OST1,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
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line.word 0x4 "TZFRC,Trip Zone Force Register"
|
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bitfld.word 0x4 6. "DCBEVT2,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x4 5. "DCBEVT1,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x4 4. "DCAEVT2,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x4 3. "DCAEVT1,Force Digital Compare A Event 1" "0,1"
|
|
bitfld.word 0x4 2. "OST,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x4 1. "CBC,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word 0xA4++0x3
|
|
line.word 0x0 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x0 15. "SOCBEN,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x0 12.--14. "SOCBSEL,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 11. "SOCAEN,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x0 8.--10. "SOCASEL,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Select" "0,1"
|
|
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|
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bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x0 3. "INTEN,EPWMxINTn Enable" "0,1"
|
|
bitfld.word 0x0 0.--2. "INTSEL,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x2 14.--15. "SOCBCNT,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x2 12.--13. "SOCBPRD,EPWMxSOCB Period Select" "0,1,2,3"
|
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rbitfld.word 0x2 10.--11. "SOCACNT,EPWMxSOCA Counter Register" "0,1,2,3"
|
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bitfld.word 0x2 8.--9. "SOCAPRD,EPWMxSOCA Period Select" "0,1,2,3"
|
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bitfld.word 0x2 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x2 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
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|
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rbitfld.word 0x2 2.--3. "INTCNT,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x2 0.--1. "INTPRD,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word 0xA8++0x1
|
|
line.word 0x0 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Flag" "0,1"
|
|
group.word 0xAA++0xB
|
|
line.word 0x0 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x0 3. "SOCB,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x0 2. "SOCA,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x0 0. "INT,EPWMxINTn Clear" "0,1"
|
|
line.word 0x2 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x2 3. "SOCB,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x2 2. "SOCA,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x2 0. "INT,EPWMxINTn Force" "0,1"
|
|
line.word 0x4 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
hexmask.word.byte 0x4 4.--7. 1. "INTCNT2,EPWMxINTn Counter Register"
|
|
hexmask.word.byte 0x4 0.--3. 1. "INTPRD2,EPWMxINTn Period Select"
|
|
line.word 0x6 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
hexmask.word.byte 0x6 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter Register"
|
|
hexmask.word.byte 0x6 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period Select"
|
|
hexmask.word.byte 0x6 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter Register"
|
|
hexmask.word.byte 0x6 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period Select"
|
|
line.word 0x8 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x8 15. "SOCBINITEN,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 14. "SOCAINITEN,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 13. "INTINITEN,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x8 12. "SOCBINITFRC,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 11. "SOCAINITFRC,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x8 10. "INTINITFRC,EPWMxINT Counter Initialization Force" "0,1"
|
|
line.word 0xA "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
hexmask.word.byte 0xA 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter Initialization Bits"
|
|
hexmask.word.byte 0xA 0.--3. 1. "INTINIT,EPWMxINT Counter Initialization Bits"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low COMP Input Select"
|
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hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High COMP Input Select"
|
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hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low COMP Input Select"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High COMP Input Select"
|
|
group.word 0xC3++0x3
|
|
line.word 0x0 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
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|
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bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal" "0,1"
|
|
line.word 0x1 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x1 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x1 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 12. "EVT2LATSEL,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x1 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 8. "EVT2SRCSEL,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x1 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
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|
|
bitfld.word 0x1 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x1 4. "EVT1LATSEL,DCBEVT1 Latched signal select" "0,1"
|
|
bitfld.word 0x1 3. "EVT1SYNCE,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x1 2. "EVT1SOCE,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x1 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x1 0. "EVT1SRCSEL,DCBEVT1 Source Signal" "0,1"
|
|
group.word 0xC7++0x5
|
|
line.word 0x0 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select" "0,1"
|
|
bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion" "0,1"
|
|
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|
|
bitfld.word 0x0 2. "BLANKE,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select" "0,1,2,3"
|
|
line.word 0x1 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x1 15. "CAPMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 14. "CAPCLR,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x1 13. "CAPSTS,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x1 1. "SHDWMODE,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x1 0. "CAPE,Counter Capture Enable" "0,1"
|
|
line.word 0x2 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
hexmask.word 0x2 0.--15. 1. "DCFOFFSET,Blanking Offset"
|
|
rgroup.word 0xCA++0x1
|
|
line.word 0x0 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter"
|
|
group.word 0xCB++0x1
|
|
line.word 0x0 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word 0xCC++0x1
|
|
line.word 0x0 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word 0xCF++0x1
|
|
line.word 0x0 "DCCAP,Digital Compare Counter Capture Register"
|
|
hexmask.word 0x0 0.--15. 1. "DCCAP,Time Base Counter Capture Register"
|
|
group.word 0xD2++0x7
|
|
line.word 0x0 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x0 14. "TRIPINPUT15,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 13. "TRIPINPUT14,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 11. "TRIPINPUT12,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 10. "TRIPINPUT11,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 9. "TRIPINPUT10,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 8. "TRIPINPUT9,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
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|
|
bitfld.word 0x0 7. "TRIPINPUT8,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 6. "TRIPINPUT7,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 5. "TRIPINPUT6,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 4. "TRIPINPUT5,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 3. "TRIPINPUT4,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 2. "TRIPINPUT3,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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|
|
bitfld.word 0x0 1. "TRIPINPUT2,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x0 0. "TRIPINPUT1,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
line.word 0x1 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x1 14. "TRIPINPUT15,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 13. "TRIPINPUT14,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 11. "TRIPINPUT12,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 10. "TRIPINPUT11,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 9. "TRIPINPUT10,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 8. "TRIPINPUT9,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
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|
|
bitfld.word 0x1 7. "TRIPINPUT8,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 6. "TRIPINPUT7,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 5. "TRIPINPUT6,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 4. "TRIPINPUT5,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 3. "TRIPINPUT4,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 2. "TRIPINPUT3,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
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|
|
bitfld.word 0x1 1. "TRIPINPUT2,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x1 0. "TRIPINPUT1,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
line.word 0x2 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x2 14. "TRIPINPUT15,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 13. "TRIPINPUT14,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 11. "TRIPINPUT12,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 10. "TRIPINPUT11,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 9. "TRIPINPUT10,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 8. "TRIPINPUT9,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "TRIPINPUT8,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 6. "TRIPINPUT7,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 5. "TRIPINPUT6,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 4. "TRIPINPUT5,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 3. "TRIPINPUT4,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 2. "TRIPINPUT3,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "TRIPINPUT2,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x2 0. "TRIPINPUT1,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
line.word 0x3 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x3 14. "TRIPINPUT15,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 13. "TRIPINPUT14,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 11. "TRIPINPUT12,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 10. "TRIPINPUT11,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 9. "TRIPINPUT10,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 8. "TRIPINPUT9,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 7. "TRIPINPUT8,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 6. "TRIPINPUT7,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 5. "TRIPINPUT6,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 4. "TRIPINPUT5,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 3. "TRIPINPUT4,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 2. "TRIPINPUT3,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x3 1. "TRIPINPUT2,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x3 0. "TRIPINPUT1,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long 0xFA++0x3
|
|
line.long 0x0 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x0 4. "DCLOCK,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x0 3. "TZCLRLOCK,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x0 2. "TZCFGLOCK,TripZone Register Set Lock" "0,1"
|
|
bitfld.long 0x0 1. "GLLOCK,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x0 0. "HRLOCK,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word 0xFD++0x3
|
|
line.word 0x0 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware programmed Valley Delay Value"
|
|
line.word 0x1 "VCNTVAL,Hardware Valley Counter Register"
|
|
hexmask.word 0x1 0.--15. 1. "VCNTVAL,Valley Counter Value"
|
|
tree.end
|
|
tree.end
|
|
tree "EQEP (Enhanced Quadrature Encoder Pulse)"
|
|
base d:0x0
|
|
tree "EQEP1"
|
|
base d:0x5100
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "QPOSCNT,Position Counter"
|
|
hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter"
|
|
line.long 0x2 "QPOSINIT,Position Counter Init"
|
|
hexmask.long 0x2 0.--31. 1. "QPOSINIT,Position Counter Init"
|
|
line.long 0x4 "QPOSMAX,Maximum Position Count"
|
|
hexmask.long 0x4 0.--31. 1. "QPOSMAX,Maximum Position Count"
|
|
line.long 0x6 "QPOSCMP,Position Compare"
|
|
hexmask.long 0x6 0.--31. 1. "QPOSCMP,Position Compare"
|
|
rgroup.long 0x8++0xB
|
|
line.long 0x0 "QPOSILAT,Index Position Latch"
|
|
hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch"
|
|
line.long 0x2 "QPOSSLAT,Strobe Position Latch"
|
|
hexmask.long 0x2 0.--31. 1. "QPOSSLAT,Strobe Position Latch"
|
|
line.long 0x4 "QPOSLAT,Position Latch"
|
|
hexmask.long 0x4 0.--31. 1. "QPOSLAT,Position Latch"
|
|
group.long 0xE++0x7
|
|
line.long 0x0 "QUTMR,QEP Unit Timer"
|
|
hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer"
|
|
line.long 0x2 "QUPRD,QEP Unit Period"
|
|
hexmask.long 0x2 0.--31. 1. "QUPRD,QEP Unit Period"
|
|
group.word 0x12++0xD
|
|
line.word 0x0 "QWDTMR,QEP Watchdog Timer"
|
|
hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer"
|
|
line.word 0x1 "QWDPRD,QEP Watchdog Period"
|
|
hexmask.word 0x1 0.--15. 1. "QWDPRD,QEP Watchdog Period"
|
|
line.word 0x2 "QDECCTL,Quadrature Decoder Control"
|
|
bitfld.word 0x2 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
|
|
bitfld.word 0x2 13. "SOEN,Sync output-enable" "0,1"
|
|
bitfld.word 0x2 12. "SPSEL,Sync output pin selection" "0,1"
|
|
bitfld.word 0x2 11. "XCR,External Clock Rate" "0,1"
|
|
bitfld.word 0x2 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
|
|
bitfld.word 0x2 9. "IGATE,Index pulse gating option" "0,1"
|
|
bitfld.word 0x2 8. "QAP,QEPA input polarity" "0,1"
|
|
bitfld.word 0x2 7. "QBP,QEPB input polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "QIP,QEPI input polarity" "0,1"
|
|
bitfld.word 0x2 5. "QSP,QEPS input polarity" "0,1"
|
|
bitfld.word 0x2 0. "QIDIRE,Qep Index Direction Enhancement enable" "0,1"
|
|
line.word 0x3 "QEPCTL,QEP Control"
|
|
bitfld.word 0x3 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x3 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
|
|
bitfld.word 0x3 10.--11. "SEI,Strobe event init" "0,1,2,3"
|
|
bitfld.word 0x3 8.--9. "IEI,Index event init of position count" "0,1,2,3"
|
|
bitfld.word 0x3 7. "SWI,Software init position counter" "0,1"
|
|
bitfld.word 0x3 6. "SEL,Strobe event latch" "0,1"
|
|
bitfld.word 0x3 4.--5. "IEL,Index event latch" "0,1,2,3"
|
|
bitfld.word 0x3 3. "QPEN,Quadrature postotion counter enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 2. "QCLM,QEP capture latch mode" "0,1"
|
|
bitfld.word 0x3 1. "UTE,QEP unit timer enable" "0,1"
|
|
bitfld.word 0x3 0. "WDE,QEP watchdog enable" "0,1"
|
|
line.word 0x4 "QCAPCTL,Qaudrature Capture Control"
|
|
bitfld.word 0x4 15. "CEN,Enable eQEP capture" "0,1"
|
|
bitfld.word 0x4 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x4 0.--3. 1. "UPPS,Unit position event prescaler"
|
|
line.word 0x5 "QPOSCTL,Position Compare Control"
|
|
bitfld.word 0x5 15. "PCSHDW,Position compare of shadow enable" "0,1"
|
|
bitfld.word 0x5 14. "PCLOAD,Position compare of shadow load" "0,1"
|
|
bitfld.word 0x5 13. "PCPOL,Polarity of sync output" "0,1"
|
|
bitfld.word 0x5 12. "PCE,Position compare enable/disable" "0,1"
|
|
hexmask.word 0x5 0.--11. 1. "PCSPW,Position compare sync pulse width"
|
|
line.word 0x6 "QEINT,QEP Interrupt Control"
|
|
bitfld.word 0x6 12. "QMAE,QMA error interrupt enable" "0,1"
|
|
bitfld.word 0x6 11. "UTO,Unit time out interrupt enable" "0,1"
|
|
bitfld.word 0x6 10. "IEL,Index event latch interrupt enable" "0,1"
|
|
bitfld.word 0x6 9. "SEL,Strobe event latch interrupt enable" "0,1"
|
|
bitfld.word 0x6 8. "PCM,Position-compare match interrupt enable" "0,1"
|
|
bitfld.word 0x6 7. "PCR,Position-compare ready interrupt enable" "0,1"
|
|
bitfld.word 0x6 6. "PCO,Position counter overflow interrupt enable" "0,1"
|
|
bitfld.word 0x6 5. "PCU,Position counter underflow interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 4. "WTO,Watchdog time out interrupt enable" "0,1"
|
|
bitfld.word 0x6 3. "QDC,Quadrature direction change interrupt enable" "0,1"
|
|
bitfld.word 0x6 2. "QPE,Quadrature phase error interrupt enable" "0,1"
|
|
bitfld.word 0x6 1. "PCE,Position counter error interrupt enable" "0,1"
|
|
rgroup.word 0x19++0x1
|
|
line.word 0x0 "QFLG,QEP Interrupt Flag"
|
|
bitfld.word 0x0 12. "QMAE,QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1"
|
|
group.word 0x1A++0x9
|
|
line.word 0x0 "QCLR,QEP Interrupt Clear"
|
|
bitfld.word 0x0 12. "QMAE,Clear QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1"
|
|
line.word 0x1 "QFRC,QEP Interrupt Force"
|
|
bitfld.word 0x1 12. "QMAE,Force QMA error interrupt" "0,1"
|
|
bitfld.word 0x1 11. "UTO,Force unit time out interrupt" "0,1"
|
|
bitfld.word 0x1 10. "IEL,Force index event latch interrupt" "0,1"
|
|
bitfld.word 0x1 9. "SEL,Force strobe event latch interrupt" "0,1"
|
|
bitfld.word 0x1 8. "PCM,Force position-compare match interrupt" "0,1"
|
|
bitfld.word 0x1 7. "PCR,Force position-compare ready interrupt" "0,1"
|
|
bitfld.word 0x1 6. "PCO,Force position counter overflow interrupt" "0,1"
|
|
bitfld.word 0x1 5. "PCU,Force position counter underflow interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "WTO,Force watchdog time out interrupt" "0,1"
|
|
bitfld.word 0x1 3. "QDC,Force quadrature direction change interrupt" "0,1"
|
|
bitfld.word 0x1 2. "PHE,Force quadrature phase error interrupt" "0,1"
|
|
bitfld.word 0x1 1. "PCE,Force position counter error interrupt" "0,1"
|
|
line.word 0x2 "QEPSTS,QEP Status"
|
|
bitfld.word 0x2 7. "UPEVNT,Unit position event flag" "0,1"
|
|
rbitfld.word 0x2 6. "FIDF,The first index marker" "0,1"
|
|
rbitfld.word 0x2 5. "QDF,Quadrature direction flag" "0,1"
|
|
rbitfld.word 0x2 4. "QDLF,eQEP direction latch flag" "0,1"
|
|
bitfld.word 0x2 3. "COEF,Capture overflow error flag" "0,1"
|
|
bitfld.word 0x2 2. "CDEF,Capture direction error flag" "0,1"
|
|
bitfld.word 0x2 1. "FIMF,First index marker flag" "0,1"
|
|
rbitfld.word 0x2 0. "PCEF,Position counter error flag." "0,1"
|
|
line.word 0x3 "QCTMR,QEP Capture Timer"
|
|
hexmask.word 0x3 0.--15. 1. "QCTMR,This register provides time base for edge capture unit."
|
|
line.word 0x4 "QCPRD,QEP Capture Period"
|
|
hexmask.word 0x4 0.--15. 1. "QCPRD,Period count value between eQEP position events"
|
|
rgroup.word 0x1F++0x3
|
|
line.word 0x0 "QCTMRLAT,QEP Capture Latch"
|
|
hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer latch value"
|
|
line.word 0x1 "QCPRDLAT,QEP Capture Period Latch"
|
|
hexmask.word 0x1 0.--15. 1. "QCPRDLAT,eQEP capture period latch value"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "REV,QEP Revision Number"
|
|
bitfld.long 0x0 3.--5. "MINOR,Minor Revision Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "MAJOR,Major Revision Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x32++0xB
|
|
line.long 0x0 "QEPSTROBESEL,QEP Strobe select register"
|
|
bitfld.long 0x0 0.--1. "STROBESEL,QMA Mode Select" "0,1,2,3"
|
|
line.long 0x2 "QMACTRL,QMA Control register"
|
|
bitfld.long 0x2 0.--2. "MODE,QMA Mode Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QEPSRCSEL,QEP Source Select Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "QEPSSEL,QEPS Source select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "QEPISEL,QEPI Source select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "QEPBSEL,QEPB Source select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "QEPASEL,QEPA Source select"
|
|
tree.end
|
|
tree "EQEP2"
|
|
base d:0x5140
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "QPOSCNT,Position Counter"
|
|
hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter"
|
|
line.long 0x2 "QPOSINIT,Position Counter Init"
|
|
hexmask.long 0x2 0.--31. 1. "QPOSINIT,Position Counter Init"
|
|
line.long 0x4 "QPOSMAX,Maximum Position Count"
|
|
hexmask.long 0x4 0.--31. 1. "QPOSMAX,Maximum Position Count"
|
|
line.long 0x6 "QPOSCMP,Position Compare"
|
|
hexmask.long 0x6 0.--31. 1. "QPOSCMP,Position Compare"
|
|
rgroup.long 0x8++0xB
|
|
line.long 0x0 "QPOSILAT,Index Position Latch"
|
|
hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch"
|
|
line.long 0x2 "QPOSSLAT,Strobe Position Latch"
|
|
hexmask.long 0x2 0.--31. 1. "QPOSSLAT,Strobe Position Latch"
|
|
line.long 0x4 "QPOSLAT,Position Latch"
|
|
hexmask.long 0x4 0.--31. 1. "QPOSLAT,Position Latch"
|
|
group.long 0xE++0x7
|
|
line.long 0x0 "QUTMR,QEP Unit Timer"
|
|
hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer"
|
|
line.long 0x2 "QUPRD,QEP Unit Period"
|
|
hexmask.long 0x2 0.--31. 1. "QUPRD,QEP Unit Period"
|
|
group.word 0x12++0xD
|
|
line.word 0x0 "QWDTMR,QEP Watchdog Timer"
|
|
hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer"
|
|
line.word 0x1 "QWDPRD,QEP Watchdog Period"
|
|
hexmask.word 0x1 0.--15. 1. "QWDPRD,QEP Watchdog Period"
|
|
line.word 0x2 "QDECCTL,Quadrature Decoder Control"
|
|
bitfld.word 0x2 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
|
|
bitfld.word 0x2 13. "SOEN,Sync output-enable" "0,1"
|
|
bitfld.word 0x2 12. "SPSEL,Sync output pin selection" "0,1"
|
|
bitfld.word 0x2 11. "XCR,External Clock Rate" "0,1"
|
|
bitfld.word 0x2 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
|
|
bitfld.word 0x2 9. "IGATE,Index pulse gating option" "0,1"
|
|
bitfld.word 0x2 8. "QAP,QEPA input polarity" "0,1"
|
|
bitfld.word 0x2 7. "QBP,QEPB input polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "QIP,QEPI input polarity" "0,1"
|
|
bitfld.word 0x2 5. "QSP,QEPS input polarity" "0,1"
|
|
bitfld.word 0x2 0. "QIDIRE,Qep Index Direction Enhancement enable" "0,1"
|
|
line.word 0x3 "QEPCTL,QEP Control"
|
|
bitfld.word 0x3 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x3 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
|
|
bitfld.word 0x3 10.--11. "SEI,Strobe event init" "0,1,2,3"
|
|
bitfld.word 0x3 8.--9. "IEI,Index event init of position count" "0,1,2,3"
|
|
bitfld.word 0x3 7. "SWI,Software init position counter" "0,1"
|
|
bitfld.word 0x3 6. "SEL,Strobe event latch" "0,1"
|
|
bitfld.word 0x3 4.--5. "IEL,Index event latch" "0,1,2,3"
|
|
bitfld.word 0x3 3. "QPEN,Quadrature postotion counter enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 2. "QCLM,QEP capture latch mode" "0,1"
|
|
bitfld.word 0x3 1. "UTE,QEP unit timer enable" "0,1"
|
|
bitfld.word 0x3 0. "WDE,QEP watchdog enable" "0,1"
|
|
line.word 0x4 "QCAPCTL,Qaudrature Capture Control"
|
|
bitfld.word 0x4 15. "CEN,Enable eQEP capture" "0,1"
|
|
bitfld.word 0x4 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x4 0.--3. 1. "UPPS,Unit position event prescaler"
|
|
line.word 0x5 "QPOSCTL,Position Compare Control"
|
|
bitfld.word 0x5 15. "PCSHDW,Position compare of shadow enable" "0,1"
|
|
bitfld.word 0x5 14. "PCLOAD,Position compare of shadow load" "0,1"
|
|
bitfld.word 0x5 13. "PCPOL,Polarity of sync output" "0,1"
|
|
bitfld.word 0x5 12. "PCE,Position compare enable/disable" "0,1"
|
|
hexmask.word 0x5 0.--11. 1. "PCSPW,Position compare sync pulse width"
|
|
line.word 0x6 "QEINT,QEP Interrupt Control"
|
|
bitfld.word 0x6 12. "QMAE,QMA error interrupt enable" "0,1"
|
|
bitfld.word 0x6 11. "UTO,Unit time out interrupt enable" "0,1"
|
|
bitfld.word 0x6 10. "IEL,Index event latch interrupt enable" "0,1"
|
|
bitfld.word 0x6 9. "SEL,Strobe event latch interrupt enable" "0,1"
|
|
bitfld.word 0x6 8. "PCM,Position-compare match interrupt enable" "0,1"
|
|
bitfld.word 0x6 7. "PCR,Position-compare ready interrupt enable" "0,1"
|
|
bitfld.word 0x6 6. "PCO,Position counter overflow interrupt enable" "0,1"
|
|
bitfld.word 0x6 5. "PCU,Position counter underflow interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 4. "WTO,Watchdog time out interrupt enable" "0,1"
|
|
bitfld.word 0x6 3. "QDC,Quadrature direction change interrupt enable" "0,1"
|
|
bitfld.word 0x6 2. "QPE,Quadrature phase error interrupt enable" "0,1"
|
|
bitfld.word 0x6 1. "PCE,Position counter error interrupt enable" "0,1"
|
|
rgroup.word 0x19++0x1
|
|
line.word 0x0 "QFLG,QEP Interrupt Flag"
|
|
bitfld.word 0x0 12. "QMAE,QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1"
|
|
group.word 0x1A++0x9
|
|
line.word 0x0 "QCLR,QEP Interrupt Clear"
|
|
bitfld.word 0x0 12. "QMAE,Clear QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1"
|
|
line.word 0x1 "QFRC,QEP Interrupt Force"
|
|
bitfld.word 0x1 12. "QMAE,Force QMA error interrupt" "0,1"
|
|
bitfld.word 0x1 11. "UTO,Force unit time out interrupt" "0,1"
|
|
bitfld.word 0x1 10. "IEL,Force index event latch interrupt" "0,1"
|
|
bitfld.word 0x1 9. "SEL,Force strobe event latch interrupt" "0,1"
|
|
bitfld.word 0x1 8. "PCM,Force position-compare match interrupt" "0,1"
|
|
bitfld.word 0x1 7. "PCR,Force position-compare ready interrupt" "0,1"
|
|
bitfld.word 0x1 6. "PCO,Force position counter overflow interrupt" "0,1"
|
|
bitfld.word 0x1 5. "PCU,Force position counter underflow interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "WTO,Force watchdog time out interrupt" "0,1"
|
|
bitfld.word 0x1 3. "QDC,Force quadrature direction change interrupt" "0,1"
|
|
bitfld.word 0x1 2. "PHE,Force quadrature phase error interrupt" "0,1"
|
|
bitfld.word 0x1 1. "PCE,Force position counter error interrupt" "0,1"
|
|
line.word 0x2 "QEPSTS,QEP Status"
|
|
bitfld.word 0x2 7. "UPEVNT,Unit position event flag" "0,1"
|
|
rbitfld.word 0x2 6. "FIDF,The first index marker" "0,1"
|
|
rbitfld.word 0x2 5. "QDF,Quadrature direction flag" "0,1"
|
|
rbitfld.word 0x2 4. "QDLF,eQEP direction latch flag" "0,1"
|
|
bitfld.word 0x2 3. "COEF,Capture overflow error flag" "0,1"
|
|
bitfld.word 0x2 2. "CDEF,Capture direction error flag" "0,1"
|
|
bitfld.word 0x2 1. "FIMF,First index marker flag" "0,1"
|
|
rbitfld.word 0x2 0. "PCEF,Position counter error flag." "0,1"
|
|
line.word 0x3 "QCTMR,QEP Capture Timer"
|
|
hexmask.word 0x3 0.--15. 1. "QCTMR,This register provides time base for edge capture unit."
|
|
line.word 0x4 "QCPRD,QEP Capture Period"
|
|
hexmask.word 0x4 0.--15. 1. "QCPRD,Period count value between eQEP position events"
|
|
rgroup.word 0x1F++0x3
|
|
line.word 0x0 "QCTMRLAT,QEP Capture Latch"
|
|
hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer latch value"
|
|
line.word 0x1 "QCPRDLAT,QEP Capture Period Latch"
|
|
hexmask.word 0x1 0.--15. 1. "QCPRDLAT,eQEP capture period latch value"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "REV,QEP Revision Number"
|
|
bitfld.long 0x0 3.--5. "MINOR,Minor Revision Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "MAJOR,Major Revision Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x32++0xB
|
|
line.long 0x0 "QEPSTROBESEL,QEP Strobe select register"
|
|
bitfld.long 0x0 0.--1. "STROBESEL,QMA Mode Select" "0,1,2,3"
|
|
line.long 0x2 "QMACTRL,QMA Control register"
|
|
bitfld.long 0x2 0.--2. "MODE,QMA Mode Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QEPSRCSEL,QEP Source Select Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "QEPSSEL,QEPS Source select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "QEPISEL,QEPI Source select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "QEPBSEL,QEPB Source select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "QEPASEL,QEPA Source select"
|
|
tree.end
|
|
tree "EQEP3"
|
|
base d:0x5180
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "QPOSCNT,Position Counter"
|
|
hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter"
|
|
line.long 0x2 "QPOSINIT,Position Counter Init"
|
|
hexmask.long 0x2 0.--31. 1. "QPOSINIT,Position Counter Init"
|
|
line.long 0x4 "QPOSMAX,Maximum Position Count"
|
|
hexmask.long 0x4 0.--31. 1. "QPOSMAX,Maximum Position Count"
|
|
line.long 0x6 "QPOSCMP,Position Compare"
|
|
hexmask.long 0x6 0.--31. 1. "QPOSCMP,Position Compare"
|
|
rgroup.long 0x8++0xB
|
|
line.long 0x0 "QPOSILAT,Index Position Latch"
|
|
hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch"
|
|
line.long 0x2 "QPOSSLAT,Strobe Position Latch"
|
|
hexmask.long 0x2 0.--31. 1. "QPOSSLAT,Strobe Position Latch"
|
|
line.long 0x4 "QPOSLAT,Position Latch"
|
|
hexmask.long 0x4 0.--31. 1. "QPOSLAT,Position Latch"
|
|
group.long 0xE++0x7
|
|
line.long 0x0 "QUTMR,QEP Unit Timer"
|
|
hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer"
|
|
line.long 0x2 "QUPRD,QEP Unit Period"
|
|
hexmask.long 0x2 0.--31. 1. "QUPRD,QEP Unit Period"
|
|
group.word 0x12++0xD
|
|
line.word 0x0 "QWDTMR,QEP Watchdog Timer"
|
|
hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer"
|
|
line.word 0x1 "QWDPRD,QEP Watchdog Period"
|
|
hexmask.word 0x1 0.--15. 1. "QWDPRD,QEP Watchdog Period"
|
|
line.word 0x2 "QDECCTL,Quadrature Decoder Control"
|
|
bitfld.word 0x2 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
|
|
bitfld.word 0x2 13. "SOEN,Sync output-enable" "0,1"
|
|
bitfld.word 0x2 12. "SPSEL,Sync output pin selection" "0,1"
|
|
bitfld.word 0x2 11. "XCR,External Clock Rate" "0,1"
|
|
bitfld.word 0x2 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
|
|
bitfld.word 0x2 9. "IGATE,Index pulse gating option" "0,1"
|
|
bitfld.word 0x2 8. "QAP,QEPA input polarity" "0,1"
|
|
bitfld.word 0x2 7. "QBP,QEPB input polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "QIP,QEPI input polarity" "0,1"
|
|
bitfld.word 0x2 5. "QSP,QEPS input polarity" "0,1"
|
|
bitfld.word 0x2 0. "QIDIRE,Qep Index Direction Enhancement enable" "0,1"
|
|
line.word 0x3 "QEPCTL,QEP Control"
|
|
bitfld.word 0x3 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x3 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
|
|
bitfld.word 0x3 10.--11. "SEI,Strobe event init" "0,1,2,3"
|
|
bitfld.word 0x3 8.--9. "IEI,Index event init of position count" "0,1,2,3"
|
|
bitfld.word 0x3 7. "SWI,Software init position counter" "0,1"
|
|
bitfld.word 0x3 6. "SEL,Strobe event latch" "0,1"
|
|
bitfld.word 0x3 4.--5. "IEL,Index event latch" "0,1,2,3"
|
|
bitfld.word 0x3 3. "QPEN,Quadrature postotion counter enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 2. "QCLM,QEP capture latch mode" "0,1"
|
|
bitfld.word 0x3 1. "UTE,QEP unit timer enable" "0,1"
|
|
bitfld.word 0x3 0. "WDE,QEP watchdog enable" "0,1"
|
|
line.word 0x4 "QCAPCTL,Qaudrature Capture Control"
|
|
bitfld.word 0x4 15. "CEN,Enable eQEP capture" "0,1"
|
|
bitfld.word 0x4 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x4 0.--3. 1. "UPPS,Unit position event prescaler"
|
|
line.word 0x5 "QPOSCTL,Position Compare Control"
|
|
bitfld.word 0x5 15. "PCSHDW,Position compare of shadow enable" "0,1"
|
|
bitfld.word 0x5 14. "PCLOAD,Position compare of shadow load" "0,1"
|
|
bitfld.word 0x5 13. "PCPOL,Polarity of sync output" "0,1"
|
|
bitfld.word 0x5 12. "PCE,Position compare enable/disable" "0,1"
|
|
hexmask.word 0x5 0.--11. 1. "PCSPW,Position compare sync pulse width"
|
|
line.word 0x6 "QEINT,QEP Interrupt Control"
|
|
bitfld.word 0x6 12. "QMAE,QMA error interrupt enable" "0,1"
|
|
bitfld.word 0x6 11. "UTO,Unit time out interrupt enable" "0,1"
|
|
bitfld.word 0x6 10. "IEL,Index event latch interrupt enable" "0,1"
|
|
bitfld.word 0x6 9. "SEL,Strobe event latch interrupt enable" "0,1"
|
|
bitfld.word 0x6 8. "PCM,Position-compare match interrupt enable" "0,1"
|
|
bitfld.word 0x6 7. "PCR,Position-compare ready interrupt enable" "0,1"
|
|
bitfld.word 0x6 6. "PCO,Position counter overflow interrupt enable" "0,1"
|
|
bitfld.word 0x6 5. "PCU,Position counter underflow interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 4. "WTO,Watchdog time out interrupt enable" "0,1"
|
|
bitfld.word 0x6 3. "QDC,Quadrature direction change interrupt enable" "0,1"
|
|
bitfld.word 0x6 2. "QPE,Quadrature phase error interrupt enable" "0,1"
|
|
bitfld.word 0x6 1. "PCE,Position counter error interrupt enable" "0,1"
|
|
rgroup.word 0x19++0x1
|
|
line.word 0x0 "QFLG,QEP Interrupt Flag"
|
|
bitfld.word 0x0 12. "QMAE,QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1"
|
|
group.word 0x1A++0x9
|
|
line.word 0x0 "QCLR,QEP Interrupt Clear"
|
|
bitfld.word 0x0 12. "QMAE,Clear QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
|
|
bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1"
|
|
bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1"
|
|
line.word 0x1 "QFRC,QEP Interrupt Force"
|
|
bitfld.word 0x1 12. "QMAE,Force QMA error interrupt" "0,1"
|
|
bitfld.word 0x1 11. "UTO,Force unit time out interrupt" "0,1"
|
|
bitfld.word 0x1 10. "IEL,Force index event latch interrupt" "0,1"
|
|
bitfld.word 0x1 9. "SEL,Force strobe event latch interrupt" "0,1"
|
|
bitfld.word 0x1 8. "PCM,Force position-compare match interrupt" "0,1"
|
|
bitfld.word 0x1 7. "PCR,Force position-compare ready interrupt" "0,1"
|
|
bitfld.word 0x1 6. "PCO,Force position counter overflow interrupt" "0,1"
|
|
bitfld.word 0x1 5. "PCU,Force position counter underflow interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x1 4. "WTO,Force watchdog time out interrupt" "0,1"
|
|
bitfld.word 0x1 3. "QDC,Force quadrature direction change interrupt" "0,1"
|
|
bitfld.word 0x1 2. "PHE,Force quadrature phase error interrupt" "0,1"
|
|
bitfld.word 0x1 1. "PCE,Force position counter error interrupt" "0,1"
|
|
line.word 0x2 "QEPSTS,QEP Status"
|
|
bitfld.word 0x2 7. "UPEVNT,Unit position event flag" "0,1"
|
|
rbitfld.word 0x2 6. "FIDF,The first index marker" "0,1"
|
|
rbitfld.word 0x2 5. "QDF,Quadrature direction flag" "0,1"
|
|
rbitfld.word 0x2 4. "QDLF,eQEP direction latch flag" "0,1"
|
|
bitfld.word 0x2 3. "COEF,Capture overflow error flag" "0,1"
|
|
bitfld.word 0x2 2. "CDEF,Capture direction error flag" "0,1"
|
|
bitfld.word 0x2 1. "FIMF,First index marker flag" "0,1"
|
|
rbitfld.word 0x2 0. "PCEF,Position counter error flag." "0,1"
|
|
line.word 0x3 "QCTMR,QEP Capture Timer"
|
|
hexmask.word 0x3 0.--15. 1. "QCTMR,This register provides time base for edge capture unit."
|
|
line.word 0x4 "QCPRD,QEP Capture Period"
|
|
hexmask.word 0x4 0.--15. 1. "QCPRD,Period count value between eQEP position events"
|
|
rgroup.word 0x1F++0x3
|
|
line.word 0x0 "QCTMRLAT,QEP Capture Latch"
|
|
hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer latch value"
|
|
line.word 0x1 "QCPRDLAT,QEP Capture Period Latch"
|
|
hexmask.word 0x1 0.--15. 1. "QCPRDLAT,eQEP capture period latch value"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "REV,QEP Revision Number"
|
|
bitfld.long 0x0 3.--5. "MINOR,Minor Revision Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "MAJOR,Major Revision Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x32++0xB
|
|
line.long 0x0 "QEPSTROBESEL,QEP Strobe select register"
|
|
bitfld.long 0x0 0.--1. "STROBESEL,QMA Mode Select" "0,1,2,3"
|
|
line.long 0x2 "QMACTRL,QMA Control register"
|
|
bitfld.long 0x2 0.--2. "MODE,QMA Mode Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QEPSRCSEL,QEP Source Select Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "QEPSSEL,QEPS Source select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "QEPISEL,QEPI Source select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "QEPBSEL,QEPB Source select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "QEPASEL,QEPA Source select"
|
|
tree.end
|
|
tree.end
|
|
tree "ERAD (Embedded Real-time Analysis and Diagnostic)"
|
|
base d:0x0
|
|
tree "ERAD_COUNTER"
|
|
tree "ERAD_COUNTER1"
|
|
base d:0x5E980
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x0 11. "CNT_INP_SEL_EN,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x0 10. "RST_EN,Enable Reset" "0,1"
|
|
bitfld.word 0x0 8. "START_STOP_CUMULATIVE,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x0 7. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x0 6. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "RST_ON_MATCH,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x0 3. "EVENT_MODE,Event mode bit" "0,1"
|
|
bitfld.word 0x0 2. "START_STOP_MODE,Start_stop mode bit" "0,1"
|
|
rgroup.word 0x1++0x1
|
|
line.word 0x0 "CTM_STATUS,Counter Status Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "STATUS,Status bits"
|
|
hexmask.word 0x0 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 1. "OVERFLOW,Counter Overflowed" "0,1"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,Counter Event Fired bits" "0,1"
|
|
group.long 0x2++0xB
|
|
line.long 0x0 "CTM_REF,Counter Reference Register"
|
|
hexmask.long 0x0 0.--31. 1. "REF,The counter reference register"
|
|
line.long 0x2 "CTM_COUNT,Counter Current Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "COUNT,The counter value register"
|
|
line.long 0x4 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
hexmask.long 0x4 0.--31. 1. "MAX_COUNT,The maximum recorded counter value."
|
|
group.word 0x8++0x7
|
|
line.word 0x0 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
hexmask.word.byte 0x0 8.--14. 1. "STA_INP_SEL,Counter Sart Input Select"
|
|
hexmask.word.byte 0x0 0.--6. 1. "CNT_INP_SEL,Counter Input Select"
|
|
line.word 0x1 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x1 1. "OVERFLOW_CLEAR,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x1 0. "EVENT_CLEAR,Clear EVENT_FIRED" "0,1"
|
|
line.word 0x2 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
hexmask.word.byte 0x2 8.--14. 1. "RST_INP_SEL,Counter Reset input Select"
|
|
hexmask.word.byte 0x2 0.--6. 1. "STO_INP_SEL,Counter Stop Input Select"
|
|
line.word 0x3 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x3 13. "RST_INP_SYNCH,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 12. "RST_INP_INV,Reset input Invert" "0,1"
|
|
bitfld.word 0x3 9. "STO_INP_SYNCH,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 8. "STO_INP_INV,Stop input Invert" "0,1"
|
|
bitfld.word 0x3 5. "STA_INP_SYNCH,Start input synchronizer enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 4. "STA_INP_INV,Start input Invert" "0,1"
|
|
bitfld.word 0x3 1. "CTM_INP_SYNCH,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 0. "CTM_INP_INV,Counter Input Invert" "0,1"
|
|
tree.end
|
|
tree "ERAD_COUNTER2"
|
|
base d:0x5E990
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x0 11. "CNT_INP_SEL_EN,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x0 10. "RST_EN,Enable Reset" "0,1"
|
|
bitfld.word 0x0 8. "START_STOP_CUMULATIVE,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x0 7. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x0 6. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "RST_ON_MATCH,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x0 3. "EVENT_MODE,Event mode bit" "0,1"
|
|
bitfld.word 0x0 2. "START_STOP_MODE,Start_stop mode bit" "0,1"
|
|
rgroup.word 0x1++0x1
|
|
line.word 0x0 "CTM_STATUS,Counter Status Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "STATUS,Status bits"
|
|
hexmask.word 0x0 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 1. "OVERFLOW,Counter Overflowed" "0,1"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,Counter Event Fired bits" "0,1"
|
|
group.long 0x2++0xB
|
|
line.long 0x0 "CTM_REF,Counter Reference Register"
|
|
hexmask.long 0x0 0.--31. 1. "REF,The counter reference register"
|
|
line.long 0x2 "CTM_COUNT,Counter Current Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "COUNT,The counter value register"
|
|
line.long 0x4 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
hexmask.long 0x4 0.--31. 1. "MAX_COUNT,The maximum recorded counter value."
|
|
group.word 0x8++0x7
|
|
line.word 0x0 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
hexmask.word.byte 0x0 8.--14. 1. "STA_INP_SEL,Counter Sart Input Select"
|
|
hexmask.word.byte 0x0 0.--6. 1. "CNT_INP_SEL,Counter Input Select"
|
|
line.word 0x1 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x1 1. "OVERFLOW_CLEAR,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x1 0. "EVENT_CLEAR,Clear EVENT_FIRED" "0,1"
|
|
line.word 0x2 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
hexmask.word.byte 0x2 8.--14. 1. "RST_INP_SEL,Counter Reset input Select"
|
|
hexmask.word.byte 0x2 0.--6. 1. "STO_INP_SEL,Counter Stop Input Select"
|
|
line.word 0x3 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x3 13. "RST_INP_SYNCH,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 12. "RST_INP_INV,Reset input Invert" "0,1"
|
|
bitfld.word 0x3 9. "STO_INP_SYNCH,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 8. "STO_INP_INV,Stop input Invert" "0,1"
|
|
bitfld.word 0x3 5. "STA_INP_SYNCH,Start input synchronizer enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 4. "STA_INP_INV,Start input Invert" "0,1"
|
|
bitfld.word 0x3 1. "CTM_INP_SYNCH,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 0. "CTM_INP_INV,Counter Input Invert" "0,1"
|
|
tree.end
|
|
tree "ERAD_COUNTER3"
|
|
base d:0x5E9A0
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x0 11. "CNT_INP_SEL_EN,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x0 10. "RST_EN,Enable Reset" "0,1"
|
|
bitfld.word 0x0 8. "START_STOP_CUMULATIVE,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x0 7. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x0 6. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "RST_ON_MATCH,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x0 3. "EVENT_MODE,Event mode bit" "0,1"
|
|
bitfld.word 0x0 2. "START_STOP_MODE,Start_stop mode bit" "0,1"
|
|
rgroup.word 0x1++0x1
|
|
line.word 0x0 "CTM_STATUS,Counter Status Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "STATUS,Status bits"
|
|
hexmask.word 0x0 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 1. "OVERFLOW,Counter Overflowed" "0,1"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,Counter Event Fired bits" "0,1"
|
|
group.long 0x2++0xB
|
|
line.long 0x0 "CTM_REF,Counter Reference Register"
|
|
hexmask.long 0x0 0.--31. 1. "REF,The counter reference register"
|
|
line.long 0x2 "CTM_COUNT,Counter Current Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "COUNT,The counter value register"
|
|
line.long 0x4 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
hexmask.long 0x4 0.--31. 1. "MAX_COUNT,The maximum recorded counter value."
|
|
group.word 0x8++0x7
|
|
line.word 0x0 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
hexmask.word.byte 0x0 8.--14. 1. "STA_INP_SEL,Counter Sart Input Select"
|
|
hexmask.word.byte 0x0 0.--6. 1. "CNT_INP_SEL,Counter Input Select"
|
|
line.word 0x1 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x1 1. "OVERFLOW_CLEAR,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x1 0. "EVENT_CLEAR,Clear EVENT_FIRED" "0,1"
|
|
line.word 0x2 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
hexmask.word.byte 0x2 8.--14. 1. "RST_INP_SEL,Counter Reset input Select"
|
|
hexmask.word.byte 0x2 0.--6. 1. "STO_INP_SEL,Counter Stop Input Select"
|
|
line.word 0x3 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x3 13. "RST_INP_SYNCH,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 12. "RST_INP_INV,Reset input Invert" "0,1"
|
|
bitfld.word 0x3 9. "STO_INP_SYNCH,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 8. "STO_INP_INV,Stop input Invert" "0,1"
|
|
bitfld.word 0x3 5. "STA_INP_SYNCH,Start input synchronizer enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 4. "STA_INP_INV,Start input Invert" "0,1"
|
|
bitfld.word 0x3 1. "CTM_INP_SYNCH,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 0. "CTM_INP_INV,Counter Input Invert" "0,1"
|
|
tree.end
|
|
tree "ERAD_COUNTER4"
|
|
base d:0x5E9B0
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x0 11. "CNT_INP_SEL_EN,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x0 10. "RST_EN,Enable Reset" "0,1"
|
|
bitfld.word 0x0 8. "START_STOP_CUMULATIVE,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x0 7. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x0 6. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "RST_ON_MATCH,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x0 3. "EVENT_MODE,Event mode bit" "0,1"
|
|
bitfld.word 0x0 2. "START_STOP_MODE,Start_stop mode bit" "0,1"
|
|
rgroup.word 0x1++0x1
|
|
line.word 0x0 "CTM_STATUS,Counter Status Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "STATUS,Status bits"
|
|
hexmask.word 0x0 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 1. "OVERFLOW,Counter Overflowed" "0,1"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,Counter Event Fired bits" "0,1"
|
|
group.long 0x2++0xB
|
|
line.long 0x0 "CTM_REF,Counter Reference Register"
|
|
hexmask.long 0x0 0.--31. 1. "REF,The counter reference register"
|
|
line.long 0x2 "CTM_COUNT,Counter Current Value Register"
|
|
hexmask.long 0x2 0.--31. 1. "COUNT,The counter value register"
|
|
line.long 0x4 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
hexmask.long 0x4 0.--31. 1. "MAX_COUNT,The maximum recorded counter value."
|
|
group.word 0x8++0x7
|
|
line.word 0x0 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
hexmask.word.byte 0x0 8.--14. 1. "STA_INP_SEL,Counter Sart Input Select"
|
|
hexmask.word.byte 0x0 0.--6. 1. "CNT_INP_SEL,Counter Input Select"
|
|
line.word 0x1 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x1 1. "OVERFLOW_CLEAR,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x1 0. "EVENT_CLEAR,Clear EVENT_FIRED" "0,1"
|
|
line.word 0x2 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
hexmask.word.byte 0x2 8.--14. 1. "RST_INP_SEL,Counter Reset input Select"
|
|
hexmask.word.byte 0x2 0.--6. 1. "STO_INP_SEL,Counter Stop Input Select"
|
|
line.word 0x3 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x3 13. "RST_INP_SYNCH,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 12. "RST_INP_INV,Reset input Invert" "0,1"
|
|
bitfld.word 0x3 9. "STO_INP_SYNCH,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 8. "STO_INP_INV,Stop input Invert" "0,1"
|
|
bitfld.word 0x3 5. "STA_INP_SYNCH,Start input synchronizer enable" "0,1"
|
|
newline
|
|
bitfld.word 0x3 4. "STA_INP_INV,Start input Invert" "0,1"
|
|
bitfld.word 0x3 1. "CTM_INP_SYNCH,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x3 0. "CTM_INP_INV,Counter Input Invert" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "ERAD_CRC"
|
|
tree "ERAD_CRC1"
|
|
base d:0x5EA10
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC2"
|
|
base d:0x5EA20
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC3"
|
|
base d:0x5EA30
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC4"
|
|
base d:0x5EA40
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC5"
|
|
base d:0x5EA50
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC6"
|
|
base d:0x5EA60
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC7"
|
|
base d:0x5EA70
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree "ERAD_CRC8"
|
|
base d:0x5EA80
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CRC_CURRENT,CRC_CURRENT"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_CURRENT,Current CRC Computed Value"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CRC_SEED,CRC_SEED"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_SEED,CRC Seed Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
hexmask.word.byte 0x0 0.--4. 1. "CRC_QUALIFIER,CRC Qualifier Register"
|
|
tree.end
|
|
tree.end
|
|
tree "ERAD_CRC_GLOBAL"
|
|
base d:0x5EA00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CRC_GLOBAL_CTRL,CRC_GLOBAL_CRTL"
|
|
bitfld.word 0x0 15. "CRC8_EN,Enable CRC Module 8" "0,1"
|
|
bitfld.word 0x0 14. "CRC7_EN,Enable CRC Module 7" "0,1"
|
|
bitfld.word 0x0 13. "CRC6_EN,Enable CRC Module 6" "0,1"
|
|
bitfld.word 0x0 12. "CRC5_EN,Enable CRC Module 5" "0,1"
|
|
bitfld.word 0x0 11. "CRC4_EN,Enable CRC Module 4" "0,1"
|
|
bitfld.word 0x0 10. "CRC3_EN,Enable CRC Module 3" "0,1"
|
|
bitfld.word 0x0 9. "CRC2_EN,Enable CRC Module 2" "0,1"
|
|
bitfld.word 0x0 8. "CRC1_EN,Enable CRC Module 1" "0,1"
|
|
bitfld.word 0x0 7. "CRC8_INIT,Initialize CRC Module 8" "0,1"
|
|
bitfld.word 0x0 6. "CRC7_INIT,Initialize CRC Module 7" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "CRC6_INIT,Initialize CRC Module 6" "0,1"
|
|
bitfld.word 0x0 4. "CRC5_INIT,Initialize CRC Module 5" "0,1"
|
|
bitfld.word 0x0 3. "CRC4_INIT,Initialize CRC Module 4" "0,1"
|
|
bitfld.word 0x0 2. "CRC3_INIT,Initialize CRC Module 3" "0,1"
|
|
bitfld.word 0x0 1. "CRC2_INIT,Initialize CRC Module 2" "0,1"
|
|
bitfld.word 0x0 0. "CRC1_INIT,Initialize CRC Module 1" "0,1"
|
|
tree.end
|
|
tree "ERAD_GLOBAL"
|
|
base d:0x5E800
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x0 "GLBL_EVENT_STAT,Global Event Status Register"
|
|
bitfld.word 0x0 11. "CTM4,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x0 10. "CTM3,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x0 9. "CTM2,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x0 8. "CTM1,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x0 7. "HWBP8,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x0 6. "HWBP7,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x0 5. "HWBP6,Bus Comparator Module Event Status" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "HWBP5,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x0 3. "HWBP4,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x0 2. "HWBP3,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x0 1. "HWBP2,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x0 0. "HWBP1,Bus Comparator Module Event Status" "0,1"
|
|
line.word 0x2 "GLBL_HALT_STAT,Global Halt Status Register"
|
|
bitfld.word 0x2 11. "CTM4,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x2 10. "CTM3,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x2 9. "CTM2,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x2 8. "CTM1,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x2 7. "HWBP8,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x2 6. "HWBP7,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x2 5. "HWBP6,Bus Comparator Module Halt Status" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "HWBP5,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x2 3. "HWBP4,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x2 2. "HWBP3,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x2 1. "HWBP2,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x2 0. "HWBP1,Bus Comparator Module Halt Status" "0,1"
|
|
group.word 0x4++0x7
|
|
line.word 0x0 "GLBL_ENABLE,Global Enable Register"
|
|
bitfld.word 0x0 11. "CTM4,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x0 10. "CTM3,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x0 9. "CTM2,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x0 8. "CTM1,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x0 7. "HWBP8,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x0 6. "HWBP7,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x0 5. "HWBP6,Bus Comparator Module Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "HWBP5,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x0 3. "HWBP4,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x0 2. "HWBP3,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x0 1. "HWBP2,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x0 0. "HWBP1,Bus Comparator Module Global Enable" "0,1"
|
|
line.word 0x2 "GLBL_CTM_RESET,Global Counter Reset"
|
|
bitfld.word 0x2 3. "CTM4,Global Reset for the counters" "0,1"
|
|
bitfld.word 0x2 2. "CTM3,Global Reset for the counters" "0,1"
|
|
bitfld.word 0x2 1. "CTM2,Global Reset for the counters" "0,1"
|
|
bitfld.word 0x2 0. "CTM1,Global Reset for the counters" "0,1"
|
|
line.word 0x4 "GLBL_NMI_CTL,Global Debug NMI control"
|
|
bitfld.word 0x4 11. "CTM4,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 10. "CTM3,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 9. "CTM2,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 8. "CTM1,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 7. "HWBP8,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 6. "HWBP7,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 5. "HWBP6,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 4. "HWBP5,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 3. "HWBP4,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 2. "HWBP3,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 1. "HWBP2,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x4 0. "HWBP1,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
line.word 0x6 "GLBL_OWNER,Global Ownership"
|
|
bitfld.word 0x6 0.--1. "OWNER,Global Ownership Bits" "0,1,2,3"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "GLBL_EVENT_AND_MASK,Global Bus Comparator Event AND Mask Register"
|
|
bitfld.long 0x0 31. "MASK4_HWBP8,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 30. "MASK4_HWBP7,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 29. "MASK4_HWBP6,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 28. "MASK4_HWBP5,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 27. "MASK4_HWBP4,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 26. "MASK4_HWBP3,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 25. "MASK4_HWBP2,Bus Comparator AND Event Mask4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MASK4_HWBP1,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x0 23. "MASK3_HWBP8,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 22. "MASK3_HWBP7,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 21. "MASK3_HWBP6,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 20. "MASK3_HWBP5,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 19. "MASK3_HWBP4,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 18. "MASK3_HWBP3,Bus Comparator AND Event Mask3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MASK3_HWBP2,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 16. "MASK3_HWBP1,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x0 15. "MASK2_HWBP8,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 14. "MASK2_HWBP7,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 13. "MASK2_HWBP6,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 12. "MASK2_HWBP5,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 11. "MASK2_HWBP4,Bus Comparator AND Event Mask2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MASK2_HWBP3,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 9. "MASK2_HWBP2,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 8. "MASK2_HWBP1,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x0 7. "MASK1_HWBP8,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x0 6. "MASK1_HWBP7,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x0 5. "MASK1_HWBP6,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x0 4. "MASK1_HWBP5,Bus Comparator AND Event Mask1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MASK1_HWBP4,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x0 2. "MASK1_HWBP3,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x0 1. "MASK1_HWBP2,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x0 0. "MASK1_HWBP1,Bus Comparator AND Event Mask1" "0,1"
|
|
line.long 0x2 "GLBL_EVENT_OR_MASK,Global Bus Comparator Event OR Mask Register"
|
|
bitfld.long 0x2 31. "MASK4_HWBP8,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 30. "MASK4_HWBP7,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 29. "MASK4_HWBP6,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 28. "MASK4_HWBP5,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 27. "MASK4_HWBP4,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 26. "MASK4_HWBP3,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 25. "MASK4_HWBP2,Bus Comparator OR Event Mask4" "0,1"
|
|
newline
|
|
bitfld.long 0x2 24. "MASK4_HWBP1,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x2 23. "MASK3_HWBP8,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 22. "MASK3_HWBP7,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 21. "MASK3_HWBP6,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 20. "MASK3_HWBP5,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 19. "MASK3_HWBP4,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 18. "MASK3_HWBP3,Bus Comparator OR Event Mask3" "0,1"
|
|
newline
|
|
bitfld.long 0x2 17. "MASK3_HWBP2,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 16. "MASK3_HWBP1,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x2 15. "MASK2_HWBP8,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 14. "MASK2_HWBP7,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 13. "MASK2_HWBP6,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 12. "MASK2_HWBP5,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 11. "MASK2_HWBP4,Bus Comparator OR Event Mask2" "0,1"
|
|
newline
|
|
bitfld.long 0x2 10. "MASK2_HWBP3,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 9. "MASK2_HWBP2,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 8. "MASK2_HWBP1,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x2 7. "MASK1_HWBP8,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x2 6. "MASK1_HWBP7,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x2 5. "MASK1_HWBP6,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x2 4. "MASK1_HWBP5,Bus Comparator OR Event Mask1" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "MASK1_HWBP4,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x2 2. "MASK1_HWBP3,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x2 1. "MASK1_HWBP2,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x2 0. "MASK1_HWBP1,Bus Comparator OR Event Mask1" "0,1"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "GLBL_AND_EVENT_INT_MASK,Global AND Event Interrupt Mask Register"
|
|
bitfld.word 0x0 3. "RTOSINT_MASK4,RTOSINT generation mask for global AND events" "0,1"
|
|
bitfld.word 0x0 2. "RTOSINT_MASK3,RTOSINT generation mask for global AND events" "0,1"
|
|
bitfld.word 0x0 1. "RTOSINT_MASK2,RTOSINT generation mask for global AND events" "0,1"
|
|
bitfld.word 0x0 0. "RTOSINT_MASK1,RTOSINT generation mask for global AND events" "0,1"
|
|
line.word 0x2 "GLBL_OR_EVENT_INT_MASK,Global OR Event Interrupt Mask Register"
|
|
bitfld.word 0x2 3. "RTOSINT_MASK4,RTOSINT generation mask for global OR events" "0,1"
|
|
bitfld.word 0x2 2. "RTOSINT_MASK3,RTOSINT generation mask for global OR events" "0,1"
|
|
bitfld.word 0x2 1. "RTOSINT_MASK2,RTOSINT generation mask for global OR events" "0,1"
|
|
bitfld.word 0x2 0. "RTOSINT_MASK1,RTOSINT generation mask for global OR events" "0,1"
|
|
tree.end
|
|
base d:0x0
|
|
tree "ERAD_HWBP"
|
|
tree "ERAD_HWBP1"
|
|
base d:0x5E900
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP2"
|
|
base d:0x5E908
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP3"
|
|
base d:0x5E910
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP4"
|
|
base d:0x5E918
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP5"
|
|
base d:0x5E920
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP6"
|
|
base d:0x5E928
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP7"
|
|
base d:0x5E930
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree "ERAD_HWBP8"
|
|
base d:0x5E938
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HWBP_MASK,HWBP Mask Register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Address mask register"
|
|
line.long 0x2 "HWBP_REF,HWBP Reference Register"
|
|
hexmask.long 0x2 0.--31. 1. "REF,Address reference register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x0 0. "EVENT_CLR,Event Clear register" "0,1"
|
|
line.word 0x2 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x2 7.--9. "COMP_MODE,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 6. "RTOSINT,RTOSINT bit" "0,1"
|
|
bitfld.word 0x2 5. "STOP,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
hexmask.word.byte 0x2 1.--4. 1. "BUS_SEL,Bus select bits"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x0 14.--15. "STATUS,Status bits" "0,1,2,3"
|
|
hexmask.word.byte 0x0 8.--13. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x0 0. "EVENT_FIRED,HWBP Event Fired bits" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F28388?")||cpuis("F28388?-CM"))
|
|
tree "ESC (EtherCAT Slave Controller)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "ESCSS_CONFIG"
|
|
base d:0x57F00
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "ESCSS_CONFIG_LOCK,EtherCATSS Configuration Lock"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x0 4. "IO_CONFIG_ENABLE,Locking the IO Configuration" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_ENABLE,Locking writes to ECATSS" "0,1"
|
|
line.long 0x2 "ESCSS_MISC_IO_CONFIG,RESET_IN. EEPROM IO connections select"
|
|
hexmask.long.byte 0x2 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x2 1. "EEPROM_I2C_IO_EN,Enables the EEPROM I2C IOPAD connection" "0,1"
|
|
bitfld.long 0x2 0. "RESETIN_GPIO_EN,Enabled ResetIN from GPIO" "0,1"
|
|
line.long 0x4 "ESCSS_PHY_IO_CONFIG,Control Register of ESCSS"
|
|
hexmask.long.byte 0x4 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x4 6. "TX_CLK_AUTO_COMP,Selects TX_CLK IO to do Auto compensation" "0,1"
|
|
bitfld.long 0x4 4.--5. "PHY_INTF_IOPAD_SEL,IO Combination select for PHY Interface" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "PHY_PORT_CNT,Number of PHY port counts" "0,1,2,3"
|
|
line.long 0x6 "ESCSS_SYNC_IO_CONFIG,SYNC Signals IO configurations"
|
|
hexmask.long.byte 0x6 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x6 7. "SYNC1_GPIO_EN,SYNC1 connection to OUT pad enabled" "0,1"
|
|
bitfld.long 0x6 4.--5. "SYNC1_IOPAD_SEL,SYNC1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x6 3. "SYNC0_GPIO_EN,SYNC0 connection to OUT pad enabled" "0,1"
|
|
bitfld.long 0x6 0.--1. "SYNC0_IOPAD_SEL,SYNC0 IO PAD select option" "0,1,2,3"
|
|
line.long 0x8 "ESCSS_LATCH_IO_CONFIG,LATCH inputs IO pad select"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x8 7. "LATCH1_GPIO_EN,LATCH1 connection to IN pad enabled" "0,1"
|
|
bitfld.long 0x8 4.--5. "LATCH1_IOPAD_SEL,LATCH1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x8 3. "LATCH0_GPIO_EN,LATCH0 connection to IN pad enabled" "0,1"
|
|
bitfld.long 0x8 0.--1. "LATCH0_IOPAD_SEL,LATCH0 IO PAD select option" "0,1,2,3"
|
|
line.long 0xA "ESCSS_GPIN_SEL,GPIN Select between IO PAD and tieoff"
|
|
hexmask.long 0xA 0.--31. 1. "GPIN_SEL,Enable for GPI Connection to IO pad."
|
|
line.long 0xC "ESCSS_GPIN_IOPAD_SEL,GPIN IO pad Select"
|
|
hexmask.long 0xC 0.--31. 1. "GPIN_IOPAD_SEL,Selection per GPIO for one of the two IOPAD locations."
|
|
line.long 0xE "ESCSS_GPOUT_SEL,GPOUT IO pad connect select"
|
|
hexmask.long 0xE 0.--31. 1. "GPOUT_SEL,GPO selection between register or GPIO pad."
|
|
line.long 0x10 "ESCSS_GPOUT_IOPAD_SEL,GPOUT IO pad select"
|
|
hexmask.long 0x10 0.--31. 1. "GPOUT_IOPAD_SEL,Selection per GPIO for one of the two IOPAD locations."
|
|
line.long 0x12 "ESCSS_LED_CONFIG,Selection of LED o/p connect to IO pad"
|
|
bitfld.long 0x12 14.--15. "RUN_IOPAD_SEL,RUN LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x12 12.--13. "ERR_IOPAD_SEL,ERROR LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x12 10.--11. "STATE_IOPAD_SEL,STATE LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x12 8.--9. "LINKACT1_IOPAD_SEL,LINKACT1 LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x12 6.--7. "LINKACT0_IOPAD_SEL,LINKACT0 LED IO PAD select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x12 4. "RUN,GPIO enable for RUN LED" "0,1"
|
|
bitfld.long 0x12 3. "ERR,GPIO enable for ERR LED" "0,1"
|
|
bitfld.long 0x12 2. "STATE,GPIO enable for STATE LED" "0,1"
|
|
bitfld.long 0x12 1. "LINKACT1,GPIO enable for LINKACT1 LED" "0,1"
|
|
bitfld.long 0x12 0. "LINKACT0,GPIO enable for LINKACT0 LED" "0,1"
|
|
line.long 0x14 "ESCSS_MISC_CONFIG,Miscelleneous Configuration"
|
|
hexmask.long.byte 0x14 6.--10. 1. "PHY_ADDR,PHY Address Offset"
|
|
bitfld.long 0x14 5. "PDI_EMULATION,PDI Emulation enable" "0,1"
|
|
bitfld.long 0x14 4. "EEPROM_SIZE,EEPROM Size bound select" "0,1"
|
|
bitfld.long 0x14 2.--3. "TX1_SHIFT_CONFIG,TX Shift configuration for Port1" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "TX0_SHIFT_CONFIG,TX Shift configuration for Port0" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "ESCSS"
|
|
base d:0x57E00
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "ESCSS_IPREVNUM,IP Revision Number"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IP_REV_MAJOR,Major IP Revision Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "IP_REV_MINOR,Minor IP Revision Number"
|
|
line.long 0x2 "ESCSS_INTR_RIS,EtherCATSS Interrupt Raw Status"
|
|
bitfld.long 0x2 5. "MASTER_RESET_RIS,ECAT RESET RIS" "0,1"
|
|
bitfld.long 0x2 4. "TIMEOUT_ERR_RIS,PDI bus Timeout Error RIS" "0,1"
|
|
bitfld.long 0x2 3. "DMA_DONE_RIS,DMA Done RIS" "0,1"
|
|
newline
|
|
bitfld.long 0x2 2. "IRQ_RIS,EtherCATSS IRQ RIS" "0,1"
|
|
bitfld.long 0x2 1. "SYNC1_RIS,SYNC1 feature RIS" "0,1"
|
|
bitfld.long 0x2 0. "SYNC0_RIS,SYNC0 feature RIS" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "ESCSS_INTR_MASK,EtherCATSS Interrupt Mask"
|
|
bitfld.long 0x0 5. "MASTER_RESET_MASK,EtherCAT Master Reset Mask" "0,1"
|
|
bitfld.long 0x0 4. "TIMEOUT_ERR_MASK,PDI Access Timeout Error Mask" "0,1"
|
|
bitfld.long 0x0 3. "DMA_DONE_MASK,DMA Done Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IRQ_MASK,EtherCATSS IRQ Mask" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1_MASK,SYNC1 feature Mask" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0_MASK,SYNC0 feature Mask" "0,1"
|
|
rgroup.long 0x6++0x3
|
|
line.long 0x0 "ESCSS_INTR_MIS,EtherCATSS Masked Interrupt Status"
|
|
bitfld.long 0x0 5. "MASTER_RESET_MIS,EtherCAT Master Reset MIS" "0,1"
|
|
bitfld.long 0x0 4. "TIMEOUT_ERR_MIS,PDI bus Timeout Error MIS" "0,1"
|
|
bitfld.long 0x0 3. "DMA_DONE_MIS,DMA Done MIS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IRQ_MIS,EtherCATSS IRQ MIS" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1_MIS,SYNC1 feature MIS" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0_MIS,SYNC0 feature MIS" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "ESCSS_INTR_CLR,EtherCATSS Interrupt Clear"
|
|
bitfld.long 0x0 5. "MASTER_RESET_CLR,EtherCAT Master Reset Clear" "0,1"
|
|
bitfld.long 0x0 4. "TIMEOUT_ERR_CLR,PDI Access Timeout Error Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMA_DONE_CLR,DMA Done Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IRQ_CLR,EtherCATSS IRQ Clear" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1_CLR,SYNC1 feature Clear" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0_CLR,SYNC0 feature Clear" "0,1"
|
|
line.long 0x2 "ESCSS_INTR_SET,EtherCATSS Interrupt Set to emulate"
|
|
hexmask.long.byte 0x2 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x2 5. "MASTER_RESET_SET,EtherCAT Master Reset Emulate" "0,1"
|
|
bitfld.long 0x2 4. "TIMEOUT_ERR_SET,PDI Access Timeout Error Set Emulate" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "DMA_DONE_SET,DMA Done Set Emulate" "0,1"
|
|
bitfld.long 0x2 2. "IRQ_SET,EtherCATSS IRQ Set Emulate" "0,1"
|
|
bitfld.long 0x2 1. "SYNC1_SET,SYNC1 Set Emulate" "0,1"
|
|
newline
|
|
bitfld.long 0x2 0. "SYNC0_SET,SYNC0 Set Emulate" "0,1"
|
|
line.long 0x4 "ESCSS_LATCH_SEL,Select for Latch0/1 inputs and LATCHIN input"
|
|
hexmask.long.byte 0x4 8.--12. 1. "LATCH1_SELECT,LATCH1 Inputs mux select"
|
|
hexmask.long.byte 0x4 0.--4. 1. "LATCH0_SELECT,LATCH0 Inputs mux select"
|
|
line.long 0x6 "ESCSS_ACCESS_CTRL,PDI interface access control config."
|
|
hexmask.long.word 0x6 16.--27. 1. "TIMEOUT_COUNT,Max timecount programmed and count while enabled."
|
|
bitfld.long 0x6 10. "ENABLE_PARALLEL_PORT_ACCESS,Parallel port access enable" "0,1"
|
|
bitfld.long 0x6 9. "ENABLE_DEBUG_ACCESS,Debug access enable" "0,1"
|
|
newline
|
|
bitfld.long 0x6 7. "EN_TIMEOUT,PDI Timeout enable" "0,1"
|
|
hexmask.long.byte 0x6 0.--6. 1. "WAIT_STATES,Minimum Wait States for VBUS Bridge"
|
|
line.long 0x8 "ESCSS_GPIN_DAT,GPIN data capture for debug and override"
|
|
hexmask.long 0x8 0.--31. 1. "GPIN_DAT,Registered GPI data driving EtherCAT GPI input"
|
|
line.long 0xA "ESCSS_GPIN_PIPE,GPIN pipeline select"
|
|
hexmask.long 0xA 0.--31. 1. "GPI_PIPE,GPI IO inputs pipeline enable."
|
|
line.long 0xC "ESCSS_GPIN_GRP_CAP_SEL,GPIN pipe group capture trigger"
|
|
bitfld.long 0xC 12.--14. "GPI_GRP_CAP_SEL3,GPI31-24 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "GPI_GRP_CAP_SEL2,GPI23-16 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "GPI_GRP_CAP_SEL1,GPI15-8 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "GPI_GRP_CAP_SEL0,GPI7-0 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x16++0x3
|
|
line.long 0x0 "ESCSS_GPOUT_DAT,GPOUT data capture for debug and override"
|
|
hexmask.long 0x0 0.--31. 1. "GPOUT_DAT,Registered GPO data from EtherCAT o/p"
|
|
group.long 0x18++0x17
|
|
line.long 0x0 "ESCSS_GPOUT_PIPE,GPOUT pipeline select"
|
|
hexmask.long 0x0 0.--31. 1. "GPO_PIPE,GPO output pipeline enable."
|
|
line.long 0x2 "ESCSS_GPOUT_GRP_CAP_SEL,GPOUT pipe group capture trigger"
|
|
bitfld.long 0x2 12.--13. "GPO_GRP_CAP_SEL3,GPO31-24 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPO_GRP_CAP_SEL2,GPO23-16 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPO_GRP_CAP_SEL1,GPO15-8 capture trigger select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 0.--1. "GPO_GRP_CAP_SEL0,GPO7-0 capture trigger select" "0,1,2,3"
|
|
line.long 0x4 "ESCSS_MEM_TEST,Memory Test Control"
|
|
rbitfld.long 0x4 1. "MEM_INIT_DONE,Memory Init done status" "0,1"
|
|
bitfld.long 0x4 0. "INITIATE_MEM_INIT,Initialize memory init" "0,1"
|
|
line.long 0x6 "ESCSS_RESET_DEST_CONFIG,ResetOut impact or destination config"
|
|
hexmask.long.byte 0x6 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x6 7. "DEVICE_RESET_EN,Enables RESET_OUT to impact the device reset" "0,1"
|
|
bitfld.long 0x6 2. "CPU_INT_EN,CPU Interrupt enable for ResetOut" "0,1"
|
|
newline
|
|
bitfld.long 0x6 1. "CPU_NMI_EN,CPU NMI enable for ResetOut" "0,1"
|
|
bitfld.long 0x6 0. "CPU_RESET_EN,CPU reset enable for ResetOut" "0,1"
|
|
line.long 0x8 "ESCSS_SYNC0_CONFIG,SYNC0 Configuration for various triggers"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x8 4. "uDMA_TRIG_EN,Connects the SYNC0 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x8 3. "CM4_NVIC_EN,Connects the SYNC0 to CM4 NVIC Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "C28x_DMA_EN,Connects the SYNC0 to C28x DMA Trigger" "0,1"
|
|
bitfld.long 0x8 1. "CLA_INT_EN,Connects the SYNC0 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x8 0. "C28x_PIE_EN,Connects the SYNC0 to C28x PIE Interrupt" "0,1"
|
|
line.long 0xA "ESCSS_SYNC1_CONFIG,SYNC1 Configuration for various triggers"
|
|
hexmask.long.byte 0xA 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0xA 4. "uDMA_TRIG_EN,Connects the SYNC1 to uDMA Trigger" "0,1"
|
|
bitfld.long 0xA 3. "CM4_NVIC_EN,Connects the SYNC1 to CM4 NVIC Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xA 2. "C28x_DMA_EN,Connects the SYNC1 to C28x DMA Trigger" "0,1"
|
|
bitfld.long 0xA 1. "CLA_INT_EN,Connects the SYNC1 to CLA Interrupt" "0,1"
|
|
bitfld.long 0xA 0. "C28x_PIE_EN,Connects the SYNC1 to C28x PIE Interrupt" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "ESCSS"
|
|
base d:0x400AFC00
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "ESCSS_IPREVNUM,IP Revision Number"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IP_REV_MAJOR,Major IP Revision Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "IP_REV_MINOR,Minor IP Revision Number"
|
|
line.long 0x4 "ESCSS_INTR_RIS,EtherCATSS Interrupt Raw Status"
|
|
bitfld.long 0x4 5. "MASTER_RESET_RIS,ECAT RESET RIS" "0,1"
|
|
bitfld.long 0x4 4. "TIMEOUT_ERR_RIS,PDI bus Timeout Error RIS" "0,1"
|
|
bitfld.long 0x4 3. "DMA_DONE_RIS,DMA Done RIS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "IRQ_RIS,EtherCATSS IRQ RIS" "0,1"
|
|
bitfld.long 0x4 1. "SYNC1_RIS,SYNC1 feature RIS" "0,1"
|
|
bitfld.long 0x4 0. "SYNC0_RIS,SYNC0 feature RIS" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ESCSS_INTR_MASK,EtherCATSS Interrupt Mask"
|
|
bitfld.long 0x0 5. "MASTER_RESET_MASK,EtherCAT Master Reset Mask" "0,1"
|
|
bitfld.long 0x0 4. "TIMEOUT_ERR_MASK,PDI Access Timeout Error Mask" "0,1"
|
|
bitfld.long 0x0 3. "DMA_DONE_MASK,DMA Done Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IRQ_MASK,EtherCATSS IRQ Mask" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1_MASK,SYNC1 feature Mask" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0_MASK,SYNC0 feature Mask" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "ESCSS_INTR_MIS,EtherCATSS Masked Interrupt Status"
|
|
bitfld.long 0x0 5. "MASTER_RESET_MIS,EtherCAT Master Reset MIS" "0,1"
|
|
bitfld.long 0x0 4. "TIMEOUT_ERR_MIS,PDI bus Timeout Error MIS" "0,1"
|
|
bitfld.long 0x0 3. "DMA_DONE_MIS,DMA Done MIS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IRQ_MIS,EtherCATSS IRQ MIS" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1_MIS,SYNC1 feature MIS" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0_MIS,SYNC0 feature MIS" "0,1"
|
|
group.long 0x10++0x1B
|
|
line.long 0x0 "ESCSS_INTR_CLR,EtherCATSS Interrupt Clear"
|
|
bitfld.long 0x0 5. "MASTER_RESET_CLR,EtherCAT Master Reset Clear" "0,1"
|
|
bitfld.long 0x0 4. "TIMEOUT_ERR_CLR,PDI Access Timeout Error Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMA_DONE_CLR,DMA Done Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IRQ_CLR,EtherCATSS IRQ Clear" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1_CLR,SYNC1 feature Clear" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0_CLR,SYNC0 feature Clear" "0,1"
|
|
line.long 0x4 "ESCSS_INTR_SET,EtherCATSS Interrupt Set to emulate"
|
|
hexmask.long.byte 0x4 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x4 5. "MASTER_RESET_SET,EtherCAT Master Reset Emulate" "0,1"
|
|
bitfld.long 0x4 4. "TIMEOUT_ERR_SET,PDI Access Timeout Error Set Emulate" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMA_DONE_SET,DMA Done Set Emulate" "0,1"
|
|
bitfld.long 0x4 2. "IRQ_SET,EtherCATSS IRQ Set Emulate" "0,1"
|
|
bitfld.long 0x4 1. "SYNC1_SET,SYNC1 Set Emulate" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SYNC0_SET,SYNC0 Set Emulate" "0,1"
|
|
line.long 0x8 "ESCSS_LATCH_SEL,Select for Latch0/1 inputs and LATCHIN input"
|
|
hexmask.long.byte 0x8 8.--12. 1. "LATCH1_SELECT,LATCH1 Inputs mux select"
|
|
hexmask.long.byte 0x8 0.--4. 1. "LATCH0_SELECT,LATCH0 Inputs mux select"
|
|
line.long 0xC "ESCSS_ACCESS_CTRL,PDI interface access control config."
|
|
hexmask.long.word 0xC 16.--27. 1. "TIMEOUT_COUNT,Max timecount programmed and count while enabled."
|
|
bitfld.long 0xC 10. "ENABLE_PARALLEL_PORT_ACCESS,Parallel port access enable" "0,1"
|
|
bitfld.long 0xC 9. "ENABLE_DEBUG_ACCESS,Debug access enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "EN_TIMEOUT,PDI Timeout enable" "0,1"
|
|
hexmask.long.byte 0xC 0.--6. 1. "WAIT_STATES,Minimum Wait States for VBUS Bridge"
|
|
line.long 0x10 "ESCSS_GPIN_DAT,GPIN data capture for debug and override"
|
|
hexmask.long 0x10 0.--31. 1. "GPIN_DAT,Registered GPI data driving EtherCAT GPI input"
|
|
line.long 0x14 "ESCSS_GPIN_PIPE,GPIN pipeline select"
|
|
hexmask.long 0x14 0.--31. 1. "GPI_PIPE,GPI IO inputs pipeline enable."
|
|
line.long 0x18 "ESCSS_GPIN_GRP_CAP_SEL,GPIN pipe group capture trigger"
|
|
bitfld.long 0x18 12.--14. "GPI_GRP_CAP_SEL3,GPI31-24 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 8.--10. "GPI_GRP_CAP_SEL2,GPI23-16 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 4.--6. "GPI_GRP_CAP_SEL1,GPI15-8 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "GPI_GRP_CAP_SEL0,GPI7-0 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "ESCSS_GPOUT_DAT,GPOUT data capture for debug and override"
|
|
hexmask.long 0x0 0.--31. 1. "GPOUT_DAT,Registered GPO data from EtherCAT o/p"
|
|
group.long 0x30++0x17
|
|
line.long 0x0 "ESCSS_GPOUT_PIPE,GPOUT pipeline select"
|
|
hexmask.long 0x0 0.--31. 1. "GPO_PIPE,GPO output pipeline enable."
|
|
line.long 0x4 "ESCSS_GPOUT_GRP_CAP_SEL,GPOUT pipe group capture trigger"
|
|
bitfld.long 0x4 12.--13. "GPO_GRP_CAP_SEL3,GPO31-24 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "GPO_GRP_CAP_SEL2,GPO23-16 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "GPO_GRP_CAP_SEL1,GPO15-8 capture trigger select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "GPO_GRP_CAP_SEL0,GPO7-0 capture trigger select" "0,1,2,3"
|
|
line.long 0x8 "ESCSS_MEM_TEST,Memory Test Control"
|
|
rbitfld.long 0x8 1. "MEM_INIT_DONE,Memory Init done status" "0,1"
|
|
bitfld.long 0x8 0. "INITIATE_MEM_INIT,Initialize memory init" "0,1"
|
|
line.long 0xC "ESCSS_RESET_DEST_CONFIG,ResetOut impact or destination config"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0xC 7. "DEVICE_RESET_EN,Enables RESET_OUT to impact the device reset" "0,1"
|
|
bitfld.long 0xC 2. "CPU_INT_EN,CPU Interrupt enable for ResetOut" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CPU_NMI_EN,CPU NMI enable for ResetOut" "0,1"
|
|
bitfld.long 0xC 0. "CPU_RESET_EN,CPU reset enable for ResetOut" "0,1"
|
|
line.long 0x10 "ESCSS_SYNC0_CONFIG,SYNC0 Configuration for various triggers"
|
|
hexmask.long.byte 0x10 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x10 4. "uDMA_TRIG_EN,Connects the SYNC0 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x10 3. "CM4_NVIC_EN,Connects the SYNC0 to CM4 NVIC Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "C28x_DMA_EN,Connects the SYNC0 to C28x DMA Trigger" "0,1"
|
|
bitfld.long 0x10 1. "CLA_INT_EN,Connects the SYNC0 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x10 0. "C28x_PIE_EN,Connects the SYNC0 to C28x PIE Interrupt" "0,1"
|
|
line.long 0x14 "ESCSS_SYNC1_CONFIG,SYNC1 Configuration for various triggers"
|
|
hexmask.long.byte 0x14 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x14 4. "uDMA_TRIG_EN,Connects the SYNC1 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x14 3. "CM4_NVIC_EN,Connects the SYNC1 to CM4 NVIC Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "C28x_DMA_EN,Connects the SYNC1 to C28x DMA Trigger" "0,1"
|
|
bitfld.long 0x14 1. "CLA_INT_EN,Connects the SYNC1 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x14 0. "C28x_PIE_EN,Connects the SYNC1 to C28x PIE Interrupt" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "ESCSS_CONFIG"
|
|
base d:0x400AFE00
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "ESCSS_CONFIG_LOCK,EtherCATSS Configuration Lock"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x0 4. "IO_CONFIG_ENABLE,Locking the IO Configuration" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_ENABLE,Locking writes to ECATSS" "0,1"
|
|
line.long 0x4 "ESCSS_MISC_IO_CONFIG,RESET_IN. EEPROM IO connections select"
|
|
hexmask.long.byte 0x4 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x4 1. "EEPROM_I2C_IO_EN,Enables the EEPROM I2C IOPAD connection" "0,1"
|
|
bitfld.long 0x4 0. "RESETIN_GPIO_EN,Enabled ResetIN from GPIO" "0,1"
|
|
line.long 0x8 "ESCSS_PHY_IO_CONFIG,Control Register of ESCSS"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x8 6. "TX_CLK_AUTO_COMP,Selects TX_CLK IO to do Auto compensation" "0,1"
|
|
bitfld.long 0x8 4.--5. "PHY_INTF_IOPAD_SEL,IO Combination select for PHY Interface" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "PHY_PORT_CNT,Number of PHY port counts" "0,1,2,3"
|
|
line.long 0xC "ESCSS_SYNC_IO_CONFIG,SYNC Signals IO configurations"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0xC 7. "SYNC1_GPIO_EN,SYNC1 connection to OUT pad enabled" "0,1"
|
|
bitfld.long 0xC 4.--5. "SYNC1_IOPAD_SEL,SYNC1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0xC 3. "SYNC0_GPIO_EN,SYNC0 connection to OUT pad enabled" "0,1"
|
|
bitfld.long 0xC 0.--1. "SYNC0_IOPAD_SEL,SYNC0 IO PAD select option" "0,1,2,3"
|
|
line.long 0x10 "ESCSS_LATCH_IO_CONFIG,LATCH inputs IO pad select"
|
|
hexmask.long.byte 0x10 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x10 7. "LATCH1_GPIO_EN,LATCH1 connection to IN pad enabled" "0,1"
|
|
bitfld.long 0x10 4.--5. "LATCH1_IOPAD_SEL,LATCH1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x10 3. "LATCH0_GPIO_EN,LATCH0 connection to IN pad enabled" "0,1"
|
|
bitfld.long 0x10 0.--1. "LATCH0_IOPAD_SEL,LATCH0 IO PAD select option" "0,1,2,3"
|
|
line.long 0x14 "ESCSS_GPIN_SEL,GPIN Select between IO PAD and tieoff"
|
|
hexmask.long 0x14 0.--31. 1. "GPIN_SEL,Enable for GPI Connection to IO pad."
|
|
line.long 0x18 "ESCSS_GPIN_IOPAD_SEL,GPIN IO pad Select"
|
|
hexmask.long 0x18 0.--31. 1. "GPIN_IOPAD_SEL,Selection per GPIO for one of the two IOPAD locations."
|
|
line.long 0x1C "ESCSS_GPOUT_SEL,GPOUT IO pad connect select"
|
|
hexmask.long 0x1C 0.--31. 1. "GPOUT_SEL,GPO selection between register or GPIO pad."
|
|
line.long 0x20 "ESCSS_GPOUT_IOPAD_SEL,GPOUT IO pad select"
|
|
hexmask.long 0x20 0.--31. 1. "GPOUT_IOPAD_SEL,Selection per GPIO for one of the two IOPAD locations."
|
|
line.long 0x24 "ESCSS_LED_CONFIG,Selection of LED o/p connect to IO pad"
|
|
bitfld.long 0x24 14.--15. "RUN_IOPAD_SEL,RUN LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x24 12.--13. "ERR_IOPAD_SEL,ERROR LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x24 10.--11. "STATE_IOPAD_SEL,STATE LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x24 8.--9. "LINKACT1_IOPAD_SEL,LINKACT1 LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x24 6.--7. "LINKACT0_IOPAD_SEL,LINKACT0 LED IO PAD select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x24 4. "RUN,GPIO enable for RUN LED" "0,1"
|
|
bitfld.long 0x24 3. "ERR,GPIO enable for ERR LED" "0,1"
|
|
bitfld.long 0x24 2. "STATE,GPIO enable for STATE LED" "0,1"
|
|
bitfld.long 0x24 1. "LINKACT1,GPIO enable for LINKACT1 LED" "0,1"
|
|
bitfld.long 0x24 0. "LINKACT0,GPIO enable for LINKACT0 LED" "0,1"
|
|
line.long 0x28 "ESCSS_MISC_CONFIG,Miscelleneous Configuration"
|
|
hexmask.long.byte 0x28 6.--10. 1. "PHY_ADDR,PHY Address Offset"
|
|
bitfld.long 0x28 5. "PDI_EMULATION,PDI Emulation enable" "0,1"
|
|
bitfld.long 0x28 4. "EEPROM_SIZE,EEPROM Size bound select" "0,1"
|
|
bitfld.long 0x28 2.--3. "TX1_SHIFT_CONFIG,TX Shift configuration for Port1" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. "TX0_SHIFT_CONFIG,TX Shift configuration for Port0" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM"))
|
|
tree "FLASH (Flash Module)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "FLASHCTRL"
|
|
base d:0x5F800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FRDCNTL,Flash Read Control Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RWAIT,Random Read Waitstate"
|
|
group.long 0x1E++0x7
|
|
line.long 0x0 "FBAC,Flash Bank Access Control Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "VREADST,VREAD Setup Time Count"
|
|
line.long 0x2 "FBFALLBACK,Flash Bank Fallback Power Register"
|
|
bitfld.long 0x2 0.--1. "BNKPWR0,Bank Power Mode" "0,1,2,3"
|
|
rgroup.long 0x22++0x3
|
|
line.long 0x0 "FBPRDY,Flash Bank Pump Ready Register"
|
|
bitfld.long 0x0 15. "PUMPRDY,Flash Pump Active Power Mode" "0,1"
|
|
bitfld.long 0x0 0. "BANKRDY,Flash Bank Active Power State" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "FPAC1,Flash Pump Access Control Register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "PSLEEP,Pump Sleep Down Count"
|
|
bitfld.long 0x0 0. "PMPPWR,Charge Pump Fallback Power Mode" "0,1"
|
|
rgroup.long 0x2A++0x3
|
|
line.long 0x0 "FMSTAT,Flash Module Status Register"
|
|
bitfld.long 0x0 12. "PGV,Program verify" "0,1"
|
|
bitfld.long 0x0 10. "EV,Erase verify" "0,1"
|
|
bitfld.long 0x0 8. "Busy,Busy Bit." "0,1"
|
|
bitfld.long 0x0 7. "ERS,Erase Active." "0,1"
|
|
bitfld.long 0x0 6. "PGM,Program Active." "0,1"
|
|
bitfld.long 0x0 5. "INVDAT,Invalid Data." "0,1"
|
|
bitfld.long 0x0 4. "CSTAT,Command Status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VOLTSTAT,Core Voltage Status." "0,1"
|
|
bitfld.long 0x0 2. "ESUSP,Erase Suspend." "0,1"
|
|
bitfld.long 0x0 1. "PSUSP,Program Suspend." "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "FRD_INTF_CTRL,Flash Read Interface Control Register"
|
|
bitfld.long 0x0 1. "DATA_CACHE_EN,Data Cache Enable" "0,1"
|
|
bitfld.long 0x0 0. "PREFETCH_EN,Prefetch Enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "FLASHECC"
|
|
base d:0x5FB00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "ECC_ENABLE,ECC Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable ECC"
|
|
line.long 0x2 "SINGLE_ERR_ADDR_LOW,Single Error Address Low"
|
|
hexmask.long 0x2 0.--31. 1. "ERR_ADDR_L,Lower 64 bit Single Bit Error Address"
|
|
line.long 0x4 "SINGLE_ERR_ADDR_HIGH,Single Error Address High"
|
|
hexmask.long 0x4 0.--31. 1. "ERR_ADDR_H,Upper 64 bit Single Bit Error Address"
|
|
line.long 0x6 "UNC_ERR_ADDR_LOW,Uncorrectable Error Address Low"
|
|
hexmask.long 0x6 0.--31. 1. "UNC_ERR_ADDR_L,Lower 64 bit Uncorrectable Error Address"
|
|
line.long 0x8 "UNC_ERR_ADDR_HIGH,Uncorrectable Error Address High"
|
|
hexmask.long 0x8 0.--31. 1. "UNC_ERR_ADDR_H,Upper 64 bit Uncorrectable Error Address"
|
|
rgroup.long 0xA++0x7
|
|
line.long 0x0 "ERR_STATUS,Error Status"
|
|
bitfld.long 0x0 18. "UNC_ERR_H,Upper 64 bits Uncorrectable error occurred" "0,1"
|
|
bitfld.long 0x0 17. "FAIL_1_H,Upper 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
bitfld.long 0x0 16. "FAIL_0_H,Upper 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
bitfld.long 0x0 2. "UNC_ERR_L,Lower 64 bits Uncorrectable error occurred" "0,1"
|
|
bitfld.long 0x0 1. "FAIL_1_L,Lower 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FAIL_0_L,Lower 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
line.long 0x2 "ERR_POS,Error Position"
|
|
bitfld.long 0x2 24. "ERR_TYPE_H,Error Type in upper 64 bits" "0,1"
|
|
hexmask.long.byte 0x2 16.--21. 1. "ERR_POS_H,Bit Position of Single bit Error in upper 64 bits"
|
|
bitfld.long 0x2 8. "ERR_TYPE_L,Error Type in lower 64 bits" "0,1"
|
|
hexmask.long.byte 0x2 0.--5. 1. "ERR_POS_L,Bit Position of Single bit Error in lower 64 bits"
|
|
group.long 0xE++0xB
|
|
line.long 0x0 "ERR_STATUS_CLR,Error Status Clear"
|
|
bitfld.long 0x0 18. "UNC_ERR_H_CLR,Upper 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
bitfld.long 0x0 17. "FAIL_1_H_CLR,Upper 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
bitfld.long 0x0 16. "FAIL_0_H_CLR,Upper 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
bitfld.long 0x0 2. "UNC_ERR_L_CLR,Lower 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
bitfld.long 0x0 1. "FAIL_1_L_CLR,Lower 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FAIL_0_L_CLR,Lower 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
line.long 0x2 "ERR_CNT,Error Control"
|
|
hexmask.long.word 0x2 0.--15. 1. "ERR_CNT,Error counter"
|
|
line.long 0x4 "ERR_THRESHOLD,Error Threshold"
|
|
hexmask.long.word 0x4 0.--15. 1. "ERR_THRESHOLD,Error Threshold"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "ERR_INTFLG,Error Interrupt Flag"
|
|
bitfld.long 0x0 1. "UNC_ERR_INTFLG,Uncorrectable Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "SINGLE_ERR_INTFLG,Single Error Interrupt Flag" "0,1"
|
|
group.long 0x16++0x17
|
|
line.long 0x0 "ERR_INTCLR,Error Interrupt Flag Clear"
|
|
bitfld.long 0x0 1. "UNC_ERR_INTCLR,Uncorrectable Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "SINGLE_ERR_INTCLR,Single Error Interrupt Flag Clear" "0,1"
|
|
line.long 0x2 "FDATAH_TEST,Data High Test"
|
|
hexmask.long 0x2 0.--31. 1. "FDATAH,Data High Test"
|
|
line.long 0x4 "FDATAL_TEST,Data Low Test"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAL,Data Low Test"
|
|
line.long 0x6 "FADDR_TEST,ECC Test Address"
|
|
hexmask.long.byte 0x6 16.--21. 1. "ADDRH,ECC Address High"
|
|
hexmask.long.word 0x6 3.--15. 1. "ADDRL,ECC Address Low"
|
|
line.long 0x8 "FECC_TEST,ECC Test Address"
|
|
hexmask.long.byte 0x8 0.--7. 1. "ECC,ECC Control Bits"
|
|
line.long 0xA "FECC_CTRL,ECC Control"
|
|
bitfld.long 0xA 2. "DO_ECC_CALC,Enable ECC Calculation" "0,1"
|
|
bitfld.long 0xA 1. "ECC_SELECT,ECC Bit Select" "0,1"
|
|
bitfld.long 0xA 0. "ECC_TEST_EN,Enable ECC Test Logic" "0,1"
|
|
rgroup.long 0x22++0xB
|
|
line.long 0x0 "FOUTH_TEST,Test Data Out High"
|
|
hexmask.long 0x0 0.--31. 1. "DATAOUTH,Test Data Out High"
|
|
line.long 0x2 "FOUTL_TEST,Test Data Out Low"
|
|
hexmask.long 0x2 0.--31. 1. "DATAOUTL,Test Data Out Low"
|
|
line.long 0x4 "FECC_STATUS,ECC Status"
|
|
bitfld.long 0x4 8. "ERR_TYPE,Holds Bit Position of 8 Check Bits of Error" "0,1"
|
|
hexmask.long.byte 0x4 2.--7. 1. "DATA_ERR_POS,Holds Bit Position of Error"
|
|
bitfld.long 0x4 1. "UNC_ERR,Test Result is Uncorrectable Error" "0,1"
|
|
bitfld.long 0x4 0. "SINGLE_ERR,Test Result is Single Bit Error" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "FLASHCTRL"
|
|
base d:0x400FA000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FRDCNTL,Flash Read Control Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RWAIT,Random Read Waitstate"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "FBAC,Flash Bank Access Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "BAGP,Bank Active Grace Period"
|
|
line.long 0x4 "FBFALLBACK,Flash Bank Fallback Power Register"
|
|
bitfld.long 0x4 0.--1. "BNKPWR0,Bank Power Mode of BANK0" "0,1,2,3"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "FBPRDY,Flash Bank Pump Ready Register"
|
|
bitfld.long 0x0 15. "PUMPRDY,Flash Pump Active Power Mode" "0,1"
|
|
bitfld.long 0x0 0. "BANKRDY,Flash Bank Active Power State" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "FPAC1,Flash Pump Access Control Register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "PSLEEP,Pump Sleep Down Count"
|
|
bitfld.long 0x0 0. "PMPPWR,Charge Pump Fallback Power Mode" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "FMSTAT,Flash Module Status Register"
|
|
bitfld.long 0x0 14. "ILA,Illegal Address" "0,1"
|
|
bitfld.long 0x0 12. "PGV,Program verify" "0,1"
|
|
bitfld.long 0x0 11. "PCV,Precondition verify" "0,1"
|
|
bitfld.long 0x0 10. "EV,Erase verify" "0,1"
|
|
bitfld.long 0x0 8. "Busy,Busy Bit." "0,1"
|
|
bitfld.long 0x0 7. "ERS,Erase Active." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "PGM,Program Active." "0,1"
|
|
bitfld.long 0x0 5. "INVDAT,Invalid Data." "0,1"
|
|
bitfld.long 0x0 4. "CSTAT,Command Status." "0,1"
|
|
bitfld.long 0x0 3. "VOLTSTAT,Core Voltage Status." "0,1"
|
|
group.long 0x2FC++0x7
|
|
line.long 0x0 "FRD_INTF_CTRL_LOCK,Lock register for FLASH_CTRL_REGS (Not including FRD_INTF_CTRL_LOCK )."
|
|
hexmask.long 0x0 0.--31. 1. "LOCK,Lock register for FRD_INTF_CTRL registers."
|
|
line.long 0x4 "FRD_INTF_CTRL,Flash Read Interface Control Register"
|
|
bitfld.long 0x4 1. "DATA_CACHE_EN,Data Cache Enable" "0,1"
|
|
bitfld.long 0x4 0. "PROG_CACHE_EN,Program Cache Enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "FLASHECC"
|
|
base d:0x400FA600
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "ECC_ENABLE,ECC Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable ECC"
|
|
line.long 0x4 "SINGLE_ERR_ADDR_LOW,Single Error Address Low"
|
|
hexmask.long 0x4 0.--31. 1. "ERR_ADDR_L,Lower 64 bit Single Bit Error Address"
|
|
line.long 0x8 "SINGLE_ERR_ADDR_HIGH,Single Error Address High"
|
|
hexmask.long 0x8 0.--31. 1. "ERR_ADDR_H,Upper 64 bit Single Bit Error Address"
|
|
line.long 0xC "UNC_ERR_ADDR_LOW,Uncorrectable Error Address Low"
|
|
hexmask.long 0xC 0.--31. 1. "UNC_ERR_ADDR_L,Lower 64 bit Uncorrectable Error Address"
|
|
line.long 0x10 "UNC_ERR_ADDR_HIGH,Uncorrectable Error Address High"
|
|
hexmask.long 0x10 0.--31. 1. "UNC_ERR_ADDR_H,Upper 64 bit Uncorrectable Error Address"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "ERR_STATUS,Error Status"
|
|
bitfld.long 0x0 18. "UNC_ERR_H,Upper 64 bits Uncorrectable error occurred" "0,1"
|
|
bitfld.long 0x0 17. "FAIL_1_H,Upper 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
bitfld.long 0x0 16. "FAIL_0_H,Upper 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
bitfld.long 0x0 2. "UNC_ERR_L,Lower 64 bits Uncorrectable error occurred" "0,1"
|
|
bitfld.long 0x0 1. "FAIL_1_L,Lower 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FAIL_0_L,Lower 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "ERR_POS,Error Position"
|
|
bitfld.long 0x0 24. "ERR_TYPE_H,Error Type in upper 64 bits" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "ERR_POS_H,Bit Position of Single bit Error in upper 64 bits"
|
|
bitfld.long 0x0 8. "ERR_TYPE_L,Error Type in lower 64 bits" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "ERR_POS_L,Bit Position of Single bit Error in lower 64 bits"
|
|
line.long 0x4 "ERR_STATUS_CLR,Error Status Clear"
|
|
bitfld.long 0x4 18. "UNC_ERR_H_CLR,Upper 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
bitfld.long 0x4 17. "FAIL_1_H_CLR,Upper 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
bitfld.long 0x4 16. "FAIL_0_H_CLR,Upper 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
bitfld.long 0x4 2. "UNC_ERR_L_CLR,Lower 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
bitfld.long 0x4 1. "FAIL_1_L_CLR,Lower 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FAIL_0_L_CLR,Lower 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
line.long 0x8 "ERR_CNT,Error Control"
|
|
hexmask.long.word 0x8 0.--15. 1. "ERR_CNT,Error counter"
|
|
line.long 0xC "ERR_THRESHOLD,Error Threshold"
|
|
hexmask.long.word 0xC 0.--15. 1. "ERR_THRESHOLD,Error Threshold"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "ERR_INTFLG,Error Interrupt Flag"
|
|
bitfld.long 0x0 1. "UNC_ERR_INTFLG,Uncorrectable Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "SINGLE_ERR_INTFLG,Single Error Interrupt Flag" "0,1"
|
|
group.long 0x2C++0x17
|
|
line.long 0x0 "ERR_INTCLR,Error Interrupt Flag Clear"
|
|
bitfld.long 0x0 1. "UNC_ERR_INTCLR,Uncorrectable Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "SINGLE_ERR_INTCLR,Single Error Interrupt Flag Clear" "0,1"
|
|
line.long 0x4 "FDATAH_TEST,Data High Test"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAH,Data High Test"
|
|
line.long 0x8 "FDATAL_TEST,Data Low Test"
|
|
hexmask.long 0x8 0.--31. 1. "FDATAL,Data Low Test"
|
|
line.long 0xC "FADDR_TEST,ECC Test Address"
|
|
hexmask.long.byte 0xC 16.--21. 1. "ADDRH,ECC Address High"
|
|
hexmask.long.word 0xC 3.--15. 1. "ADDRL,ECC Address Low"
|
|
line.long 0x10 "FECC_TEST,ECC Test Address"
|
|
hexmask.long.byte 0x10 0.--7. 1. "ECC,ECC Control Bits"
|
|
line.long 0x14 "FECC_CTRL,ECC Control"
|
|
bitfld.long 0x14 2. "DO_ECC_CALC,Enable ECC Calculation" "0,1"
|
|
bitfld.long 0x14 1. "ECC_SELECT,ECC Bit Select" "0,1"
|
|
bitfld.long 0x14 0. "ECC_TEST_EN,Enable ECC Test Logic" "0,1"
|
|
rgroup.long 0x44++0xB
|
|
line.long 0x0 "FOUTH_TEST,Test Data Out High"
|
|
hexmask.long 0x0 0.--31. 1. "DATAOUTH,Test Data Out High"
|
|
line.long 0x4 "FOUTL_TEST,Test Data Out Low"
|
|
hexmask.long 0x4 0.--31. 1. "DATAOUTL,Test Data Out Low"
|
|
line.long 0x8 "FECC_STATUS,ECC Status"
|
|
bitfld.long 0x8 8. "ERR_TYPE,Holds Bit Position of 8 Check Bits of Error" "0,1"
|
|
hexmask.long.byte 0x8 2.--7. 1. "DATA_ERR_POS,Holds Bit Position of Error"
|
|
bitfld.long 0x8 1. "UNC_ERR,Test Result is Uncorrectable Error" "0,1"
|
|
bitfld.long 0x8 0. "SINGLE_ERR,Test Result is Single Bit Error" "0,1"
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "FLASH_ECC_REGS_LOCK,Lock register for FLASH_ECC_REGS (Not including FLASH_ECC_REGS_LOCK )."
|
|
hexmask.long 0x0 0.--31. 1. "LOCK,Lock bit for FLASH_ECC_REGS registers."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "FPU (FPU Registers)"
|
|
base d:0xF00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RB,Repeat Block Register"
|
|
bitfld.long 0x0 31. "RAS,Repeat block shadow active" "0,1"
|
|
bitfld.long 0x0 30. "RA,Repeat block active" "0,1"
|
|
hexmask.long.byte 0x0 23.--29. 1. "RSIZE,Repeat block size"
|
|
hexmask.long.byte 0x0 16.--22. 1. "RE,Repeat block end"
|
|
hexmask.long.word 0x0 0.--15. 1. "RC,Repeat count"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "STF,Floating-Point Status Register"
|
|
bitfld.long 0x0 31. "SHDWS,Shadow mode status" "0,1"
|
|
bitfld.long 0x0 9. "RND32,Rounding mode" "0,1"
|
|
bitfld.long 0x0 6. "TF,Test flag" "0,1"
|
|
bitfld.long 0x0 5. "ZI,Zero integer flag" "0,1"
|
|
bitfld.long 0x0 4. "NI,Negative integer flag" "0,1"
|
|
bitfld.long 0x0 3. "ZF,Zero float flag" "0,1"
|
|
bitfld.long 0x0 2. "NF,Negative flaot flag" "0,1"
|
|
bitfld.long 0x0 1. "LUF,Latched underflow" "0,1"
|
|
bitfld.long 0x0 0. "LVF,Latched overflow" "0,1"
|
|
group.long 0x10++0x3F
|
|
line.long 0x0 "R0L,"
|
|
line.long 0x2 "R0H,"
|
|
line.long 0x4 "R1L,"
|
|
line.long 0x6 "R1H,"
|
|
line.long 0x8 "R2L,"
|
|
line.long 0xA "R2H,"
|
|
line.long 0xC "R3L,"
|
|
line.long 0xE "R3H,"
|
|
line.long 0x10 "R4L,"
|
|
line.long 0x12 "R4H,"
|
|
line.long 0x14 "R5L,"
|
|
line.long 0x16 "R5H,"
|
|
line.long 0x18 "R6L,"
|
|
line.long 0x1A "R6H,"
|
|
line.long 0x1C "R7L,"
|
|
line.long 0x1E "R7H,"
|
|
tree.end
|
|
tree "FSI (Fast Serial Interface)"
|
|
base d:0x0
|
|
tree "FSIRxA"
|
|
base d:0x6680
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxB"
|
|
base d:0x6780
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxC"
|
|
base d:0x6880
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxD"
|
|
base d:0x6980
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxE"
|
|
base d:0x6A80
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxF"
|
|
base d:0x6B80
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxG"
|
|
base d:0x6C80
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSIRxH"
|
|
base d:0x6D80
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset" "0,1"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to be Received"
|
|
bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "RX_FRAME_INFO,Receive frame control register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type"
|
|
line.word 0x1 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word.byte 0x1 8.--15. 1. "USER_DATA,Received User Data"
|
|
hexmask.word.byte 0x1 1.--4. 1. "FRAME_TAG,Received Frame Tag"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
rgroup.word 0xA++0x3
|
|
line.word 0x0 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag" "0,1"
|
|
line.word 0x1 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word.byte 0x1 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word.byte 0x1 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word 0xC++0x5
|
|
line.word 0x0 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "PING_FRAME,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
line.word 0x1 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x1 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 13. "DATA_TAG_MATCH,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 12. "PING_TAG_MATCH,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x1 11. "DATA_FRAME,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "FRAME_OVERRUN,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "PING_FRAME,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "ERR_FRAME,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x1 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "EOF_ERR,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "TYPE_ERR,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "CRC_ERR,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force" "0,1"
|
|
line.word 0x2 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
hexmask.word.byte 0x2 0.--3. 1. "BUF_PTR_LOAD,Load value for receive buffer pointer"
|
|
rgroup.word 0xF++0x1
|
|
line.word 0x0 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Available Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset" "0,1"
|
|
group.long 0x12++0x3
|
|
line.long 0x0 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word 0x17++0x1
|
|
line.word 0x0 "RX_PING_TAG,Receive ping tag register"
|
|
hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Ping Frame Tag"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_REF,PING Watchdog Counter Reference Value"
|
|
rgroup.long 0x1A++0x3
|
|
line.long 0x0 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value"
|
|
group.word 0x1C++0x5
|
|
line.word 0x0 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
line.word 0x1 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x1 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x1 2. "INT2_EN_CRC_ERR,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x1 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
line.word 0x2 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "RX_ECC_VAL,Receive ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x0 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x0 0. "SBE,Single Bit Error Detected" "0,1"
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference"
|
|
line.word 0x1 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x1 9. "BROADCAST_EN,Broadcast Enable" "0,1"
|
|
bitfld.word 0x1 8. "CMP_EN,Ping Tag Compare Enable" "0,1"
|
|
hexmask.word.byte 0x1 4.--7. 1. "TAG_MASK,Ping Tag Mask"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG_REF,Ping Tag Reference"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1"
|
|
hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0"
|
|
hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status" "0,1"
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "RX_BUF_BASE,Base address for receive data buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSITxA"
|
|
base d:0x6600
|
|
group.word 0x0++0xD
|
|
line.word 0x0 "TX_MASTER_CTRL,Transmit master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 1. "FLUSH,Flush Operation Start" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset" "0,1"
|
|
line.word 0x2 "TX_CLK_CTRL,Transmit clock control register"
|
|
hexmask.word.byte 0x2 2.--9. 1. "PRESCALE_VAL,Prescale value"
|
|
bitfld.word 0x2 1. "CLK_EN,Clock Divider Enable" "0,1"
|
|
bitfld.word 0x2 0. "CLK_RST,Soft Reset for the Clock Divider" "0,1"
|
|
line.word 0x4 "TX_OPER_CTRL_LO,Transmit operation control register low"
|
|
bitfld.word 0x4 9. "TDM_ENABLE,Transmit TDM Mode Enable" "0,1"
|
|
bitfld.word 0x4 8. "SEL_PLLCLK,Input Clock Select" "0,1"
|
|
bitfld.word 0x4 7. "PING_TO_MODE,Ping Counter Reset Mode Select" "0,1"
|
|
bitfld.word 0x4 6. "SW_CRC,CRC Source Select" "0,1"
|
|
bitfld.word 0x4 3.--5. "START_MODE,Transmission Start Mode Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x4 2. "SPI_MODE,SPI Mode Select" "0,1"
|
|
bitfld.word 0x4 0.--1. "DATA_WIDTH,Transmit Data width" "0,1,2,3"
|
|
line.word 0x5 "TX_OPER_CTRL_HI,Transmit operation control register high"
|
|
hexmask.word.byte 0x5 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select"
|
|
bitfld.word 0x5 6. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x5 5. "FORCE_ERR,Error Frame Force" "0,1"
|
|
line.word 0x6 "TX_FRAME_CTRL,Transmit frame control register"
|
|
bitfld.word 0x6 15. "START,Start Transmission" "0,1"
|
|
hexmask.word.byte 0x6 4.--7. 1. "N_WORDS,Number of Words to be Transmitted"
|
|
hexmask.word.byte 0x6 0.--3. 1. "FRAME_TYPE,Transmit Frame Type"
|
|
line.word 0x7 "TX_FRAME_TAG_UDATA,Transmit frame tag and user data register"
|
|
hexmask.word.byte 0x7 8.--15. 1. "USER_DATA,User Data"
|
|
hexmask.word.byte 0x7 0.--3. 1. "FRAME_TAG,Frame Tag"
|
|
line.word 0x8 "TX_BUF_PTR_LOAD,Transmit buffer pointer control load register"
|
|
hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Force Load"
|
|
rgroup.word 0x9++0x1
|
|
line.word 0x0 "TX_BUF_PTR_STS,Transmit buffer pointer control status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Remaining Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0xA++0x3
|
|
line.word 0x0 "TX_PING_CTRL,Transmit ping control register"
|
|
hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select"
|
|
bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable" "0,1"
|
|
bitfld.word 0x0 1. "TIMER_EN,Ping Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset" "0,1"
|
|
line.word 0x1 "TX_PING_TAG,Transmit ping tag register"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG,Ping Frame Tag"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TX_PING_TO_REF,Transmit ping timeout counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference"
|
|
rgroup.long 0xE++0x3
|
|
line.long 0x0 "TX_PING_TO_CNT,Transmit ping timeout current count"
|
|
hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter"
|
|
group.word 0x10++0x5
|
|
line.word 0x0 "TX_INT_CTRL,Transmit interrupt event control register"
|
|
bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable Ping Timer Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
line.word 0x1 "TX_DMA_CTRL,Transmit DMA event control register"
|
|
bitfld.word 0x1 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
line.word 0x2 "TX_LOCK_CTRL,Transmit lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "TX_EVT_STS,Transmit event and error status flag register"
|
|
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag" "0,1"
|
|
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
group.word 0x16++0x5
|
|
line.word 0x0 "TX_EVT_CLR,Transmit event and error clear register"
|
|
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
line.word 0x1 "TX_EVT_FRC,Transmit event and error flag force register"
|
|
bitfld.word 0x1 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force" "0,1"
|
|
bitfld.word 0x1 2. "BUF_OVERRUN,Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "BUF_UNDERRUN,Buffer Underrun Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
line.word 0x2 "TX_USER_CRC,Transmit user-defined CRC register"
|
|
hexmask.word.byte 0x2 0.--7. 1. "USER_CRC,User-defined CRC"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "TX_ECC_DATA,Transmit ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
rgroup.word 0x22++0x1
|
|
line.word 0x0 "TX_ECC_VAL,Transmit ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "TX_BUF_BASE,Base address for transmit buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address"
|
|
tree.end
|
|
tree "FSITxB"
|
|
base d:0x6700
|
|
group.word 0x0++0xD
|
|
line.word 0x0 "TX_MASTER_CTRL,Transmit master control register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x0 1. "FLUSH,Flush Operation Start" "0,1"
|
|
bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset" "0,1"
|
|
line.word 0x2 "TX_CLK_CTRL,Transmit clock control register"
|
|
hexmask.word.byte 0x2 2.--9. 1. "PRESCALE_VAL,Prescale value"
|
|
bitfld.word 0x2 1. "CLK_EN,Clock Divider Enable" "0,1"
|
|
bitfld.word 0x2 0. "CLK_RST,Soft Reset for the Clock Divider" "0,1"
|
|
line.word 0x4 "TX_OPER_CTRL_LO,Transmit operation control register low"
|
|
bitfld.word 0x4 9. "TDM_ENABLE,Transmit TDM Mode Enable" "0,1"
|
|
bitfld.word 0x4 8. "SEL_PLLCLK,Input Clock Select" "0,1"
|
|
bitfld.word 0x4 7. "PING_TO_MODE,Ping Counter Reset Mode Select" "0,1"
|
|
bitfld.word 0x4 6. "SW_CRC,CRC Source Select" "0,1"
|
|
bitfld.word 0x4 3.--5. "START_MODE,Transmission Start Mode Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x4 2. "SPI_MODE,SPI Mode Select" "0,1"
|
|
bitfld.word 0x4 0.--1. "DATA_WIDTH,Transmit Data width" "0,1,2,3"
|
|
line.word 0x5 "TX_OPER_CTRL_HI,Transmit operation control register high"
|
|
hexmask.word.byte 0x5 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select"
|
|
bitfld.word 0x5 6. "ECC_SEL,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x5 5. "FORCE_ERR,Error Frame Force" "0,1"
|
|
line.word 0x6 "TX_FRAME_CTRL,Transmit frame control register"
|
|
bitfld.word 0x6 15. "START,Start Transmission" "0,1"
|
|
hexmask.word.byte 0x6 4.--7. 1. "N_WORDS,Number of Words to be Transmitted"
|
|
hexmask.word.byte 0x6 0.--3. 1. "FRAME_TYPE,Transmit Frame Type"
|
|
line.word 0x7 "TX_FRAME_TAG_UDATA,Transmit frame tag and user data register"
|
|
hexmask.word.byte 0x7 8.--15. 1. "USER_DATA,User Data"
|
|
hexmask.word.byte 0x7 0.--3. 1. "FRAME_TAG,Frame Tag"
|
|
line.word 0x8 "TX_BUF_PTR_LOAD,Transmit buffer pointer control load register"
|
|
hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Force Load"
|
|
rgroup.word 0x9++0x1
|
|
line.word 0x0 "TX_BUF_PTR_STS,Transmit buffer pointer control status register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Remaining Words in Buffer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index"
|
|
group.word 0xA++0x3
|
|
line.word 0x0 "TX_PING_CTRL,Transmit ping control register"
|
|
hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select"
|
|
bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable" "0,1"
|
|
bitfld.word 0x0 1. "TIMER_EN,Ping Counter Enable" "0,1"
|
|
bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset" "0,1"
|
|
line.word 0x1 "TX_PING_TAG,Transmit ping tag register"
|
|
hexmask.word.byte 0x1 0.--3. 1. "TAG,Ping Frame Tag"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TX_PING_TO_REF,Transmit ping timeout counter reference"
|
|
hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference"
|
|
rgroup.long 0xE++0x3
|
|
line.long 0x0 "TX_PING_TO_CNT,Transmit ping timeout current count"
|
|
hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter"
|
|
group.word 0x10++0x5
|
|
line.word 0x0 "TX_INT_CTRL,Transmit interrupt event control register"
|
|
bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable Ping Timer Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1" "0,1"
|
|
line.word 0x1 "TX_DMA_CTRL,Transmit DMA event control register"
|
|
bitfld.word 0x1 0. "DMA_EVT_EN,DMA Event Enable" "0,1"
|
|
line.word 0x2 "TX_LOCK_CTRL,Transmit lock control register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x2 0. "LOCK,Control Register Lock Enable" "0,1"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "TX_EVT_STS,Transmit event and error status flag register"
|
|
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag" "0,1"
|
|
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag" "0,1"
|
|
group.word 0x16++0x5
|
|
line.word 0x0 "TX_EVT_CLR,Transmit event and error clear register"
|
|
bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear" "0,1"
|
|
line.word 0x1 "TX_EVT_FRC,Transmit event and error flag force register"
|
|
bitfld.word 0x1 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force" "0,1"
|
|
bitfld.word 0x1 2. "BUF_OVERRUN,Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "BUF_UNDERRUN,Buffer Underrun Flag Force" "0,1"
|
|
bitfld.word 0x1 0. "FRAME_DONE,Frame Done Flag Force" "0,1"
|
|
line.word 0x2 "TX_USER_CRC,Transmit user-defined CRC register"
|
|
hexmask.word.byte 0x2 0.--7. 1. "USER_CRC,User-defined CRC"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "TX_ECC_DATA,Transmit ECC data register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
rgroup.word 0x22++0x1
|
|
line.word 0x0 "TX_ECC_VAL,Transmit ECC value register"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "TX_BUF_BASE,Base address for transmit buffer"
|
|
hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "GCRC (Generic Cyclic Redundancy Check)"
|
|
base d:0x40040000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CRCCTRL,CRC Control Register"
|
|
bitfld.long 0x0 8.--9. "DATATYPE,Defines the DATATYPE of the element of the data array." "0,1,2,3"
|
|
bitfld.long 0x0 7. "BITREVERSE,Enables the DATAIN bus to the CRC engine to be bit reversed." "0,1"
|
|
bitfld.long 0x0 6. "ENDIANNESS,Defines the endianness of the data stream." "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "POLYSIZE,CRC polynomial order"
|
|
line.long 0x4 "CRCPOLY,CRC Polynomial Register"
|
|
hexmask.long 0x4 0.--31. 1. "POLY,CRC polynomial"
|
|
line.long 0x8 "CRCDATAMASK,CRC Data Mask Register"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DATAMASK,Number of bits to be masked"
|
|
line.long 0xC "CRCDATAIN,CRC Data Input Register"
|
|
hexmask.long 0xC 0.--31. 1. "DATAIN,CRC data input"
|
|
line.long 0x10 "CRCDATAOUT,CRC Data Output Register"
|
|
hexmask.long 0x10 0.--31. 1. "DATA,CRC DATAOUT"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CRCDATATRANS,CRC Transformed Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATAIN,Transformed data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM"))
|
|
tree "GPIO (General-Purpose Input/Output)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "GPIOCTRL"
|
|
base d:0x7C00
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "GPACTRL,GPIO A Qualification Sampling Period Control (GPIO0 to 31)"
|
|
hexmask.long.byte 0x0 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO24 to GPIO31"
|
|
hexmask.long.byte 0x0 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO16 to GPIO23"
|
|
hexmask.long.byte 0x0 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO8 to GPIO15"
|
|
hexmask.long.byte 0x0 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO0 to GPIO7"
|
|
line.long 0x2 "GPAQSEL1,GPIO A Qualifier Select 1 Register (GPIO0 to 15)"
|
|
bitfld.long 0x2 30.--31. "GPIO15,Select input qualification type for GPIO15" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "GPIO14,Select input qualification type for GPIO14" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "GPIO13,Select input qualification type for GPIO13" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GPIO12,Select input qualification type for GPIO12" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GPIO11,Select input qualification type for GPIO11" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GPIO10,Select input qualification type for GPIO10" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GPIO9,Select input qualification type for GPIO9" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "GPIO8,Select input qualification type for GPIO8" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GPIO7,Select input qualification type for GPIO7" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GPIO6,Select input qualification type for GPIO6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 10.--11. "GPIO5,Select input qualification type for GPIO5" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPIO4,Select input qualification type for GPIO4" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "GPIO3,Select input qualification type for GPIO3" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPIO2,Select input qualification type for GPIO2" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GPIO1,Select input qualification type for GPIO1" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GPIO0,Select input qualification type for GPIO0" "0,1,2,3"
|
|
line.long 0x4 "GPAQSEL2,GPIO A Qualifier Select 2 Register (GPIO16 to 31)"
|
|
bitfld.long 0x4 30.--31. "GPIO31,Select input qualification type for GPIO31" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "GPIO30,Select input qualification type for GPIO30" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "GPIO29,Select input qualification type for GPIO29" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "GPIO28,Select input qualification type for GPIO28" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "GPIO27,Select input qualification type for GPIO27" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "GPIO26,Select input qualification type for GPIO26" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "GPIO25,Select input qualification type for GPIO25" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "GPIO24,Select input qualification type for GPIO24" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "GPIO23,Select input qualification type for GPIO23" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "GPIO22,Select input qualification type for GPIO22" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "GPIO21,Select input qualification type for GPIO21" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "GPIO20,Select input qualification type for GPIO20" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "GPIO19,Select input qualification type for GPIO19" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "GPIO18,Select input qualification type for GPIO18" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "GPIO17,Select input qualification type for GPIO17" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "GPIO16,Select input qualification type for GPIO16" "0,1,2,3"
|
|
line.long 0x6 "GPAMUX1,GPIO A Mux 1 Register (GPIO0 to 15)"
|
|
bitfld.long 0x6 30.--31. "GPIO15,Defines pin-muxing selection for GPIO15" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "GPIO14,Defines pin-muxing selection for GPIO14" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "GPIO13,Defines pin-muxing selection for GPIO13" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "GPIO12,Defines pin-muxing selection for GPIO12" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "GPIO11,Defines pin-muxing selection for GPIO11" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "GPIO10,Defines pin-muxing selection for GPIO10" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "GPIO9,Defines pin-muxing selection for GPIO9" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GPIO8,Defines pin-muxing selection for GPIO8" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GPIO7,Defines pin-muxing selection for GPIO7" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GPIO6,Defines pin-muxing selection for GPIO6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 10.--11. "GPIO5,Defines pin-muxing selection for GPIO5" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "GPIO4,Defines pin-muxing selection for GPIO4" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GPIO3,Defines pin-muxing selection for GPIO3" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GPIO2,Defines pin-muxing selection for GPIO2" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GPIO1,Defines pin-muxing selection for GPIO1" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GPIO0,Defines pin-muxing selection for GPIO0" "0,1,2,3"
|
|
line.long 0x8 "GPAMUX2,GPIO A Mux 2 Register (GPIO16 to 31)"
|
|
bitfld.long 0x8 30.--31. "GPIO31,Defines pin-muxing selection for GPIO31" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GPIO30,Defines pin-muxing selection for GPIO30" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GPIO29,Defines pin-muxing selection for GPIO29" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GPIO28,Defines pin-muxing selection for GPIO28" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GPIO27,Defines pin-muxing selection for GPIO27" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GPIO26,Defines pin-muxing selection for GPIO26" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GPIO25,Defines pin-muxing selection for GPIO25" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GPIO24,Defines pin-muxing selection for GPIO24" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GPIO23,Defines pin-muxing selection for GPIO23" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GPIO22,Defines pin-muxing selection for GPIO22" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GPIO21,Defines pin-muxing selection for GPIO21" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GPIO20,Defines pin-muxing selection for GPIO20" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "GPIO19,Defines pin-muxing selection for GPIO19" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GPIO18,Defines pin-muxing selection for GPIO18" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GPIO17,Defines pin-muxing selection for GPIO17" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GPIO16,Defines pin-muxing selection for GPIO16" "0,1,2,3"
|
|
line.long 0xA "GPADIR,GPIO A Direction Register (GPIO0 to 31)"
|
|
bitfld.long 0xA 31. "GPIO31,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 30. "GPIO30,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 29. "GPIO29,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 28. "GPIO28,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 27. "GPIO27,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 26. "GPIO26,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 25. "GPIO25,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 24. "GPIO24,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 23. "GPIO23,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 22. "GPIO22,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xA 21. "GPIO21,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 20. "GPIO20,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 19. "GPIO19,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 18. "GPIO18,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 17. "GPIO17,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 16. "GPIO16,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 15. "GPIO15,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 14. "GPIO14,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 13. "GPIO13,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 12. "GPIO12,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xA 11. "GPIO11,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 10. "GPIO10,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 9. "GPIO9,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 8. "GPIO8,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 7. "GPIO7,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 6. "GPIO6,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 5. "GPIO5,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 4. "GPIO4,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 3. "GPIO3,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 2. "GPIO2,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xA 1. "GPIO1,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xA 0. "GPIO0,Defines direction for this pin in GPIO mode" "0,1"
|
|
line.long 0xC "GPAPUD,GPIO A Pull Up Disable Register (GPIO0 to 31)"
|
|
bitfld.long 0xC 31. "GPIO31,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 30. "GPIO30,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 29. "GPIO29,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 28. "GPIO28,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 27. "GPIO27,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 26. "GPIO26,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 25. "GPIO25,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 24. "GPIO24,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 23. "GPIO23,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 22. "GPIO22,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "GPIO21,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 20. "GPIO20,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 19. "GPIO19,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 18. "GPIO18,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 17. "GPIO17,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 16. "GPIO16,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 15. "GPIO15,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 14. "GPIO14,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 13. "GPIO13,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 12. "GPIO12,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "GPIO11,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 10. "GPIO10,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 9. "GPIO9,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 8. "GPIO8,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 7. "GPIO7,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 6. "GPIO6,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 5. "GPIO5,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 4. "GPIO4,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 3. "GPIO3,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 2. "GPIO2,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GPIO1,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0xC 0. "GPIO0,Pull-Up Disable control for this pin" "0,1"
|
|
line.long 0x10 "GPAINV,GPIO A Input Polarity Invert Registers (GPIO0 to 31)"
|
|
bitfld.long 0x10 31. "GPIO31,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO30,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO29,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO28,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO27,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO26,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO25,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO24,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO23,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO22,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "GPIO21,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO20,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 19. "GPIO19,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO18,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO17,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO16,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO15,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO14,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO13,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO12,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "GPIO11,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO10,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO9,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO8,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 7. "GPIO7,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO6,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO5,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO4,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO3,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO2,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GPIO1,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO0,Input inversion control for this pin" "0,1"
|
|
line.long 0x12 "GPAODR,GPIO A Open Drain Output Register (GPIO0 to GPIO31)"
|
|
bitfld.long 0x12 31. "GPIO31,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 30. "GPIO30,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 29. "GPIO29,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 28. "GPIO28,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 27. "GPIO27,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 26. "GPIO26,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 25. "GPIO25,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 24. "GPIO24,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 23. "GPIO23,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 22. "GPIO22,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x12 21. "GPIO21,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 20. "GPIO20,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 19. "GPIO19,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 18. "GPIO18,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 17. "GPIO17,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 16. "GPIO16,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 15. "GPIO15,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 14. "GPIO14,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 13. "GPIO13,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 12. "GPIO12,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x12 11. "GPIO11,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 10. "GPIO10,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 9. "GPIO9,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 8. "GPIO8,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 7. "GPIO7,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 6. "GPIO6,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 5. "GPIO5,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 4. "GPIO4,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 3. "GPIO3,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 2. "GPIO2,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x12 1. "GPIO1,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x12 0. "GPIO0,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "GPAGMUX1,GPIO A Peripheral Group Mux (GPIO0 to 15)"
|
|
bitfld.long 0x0 30.--31. "GPIO15,Defines pin-muxing selection for GPIO15" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "GPIO14,Defines pin-muxing selection for GPIO14" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "GPIO13,Defines pin-muxing selection for GPIO13" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GPIO12,Defines pin-muxing selection for GPIO12" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GPIO11,Defines pin-muxing selection for GPIO11" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GPIO10,Defines pin-muxing selection for GPIO10" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GPIO9,Defines pin-muxing selection for GPIO9" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "GPIO8,Defines pin-muxing selection for GPIO8" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GPIO7,Defines pin-muxing selection for GPIO7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GPIO6,Defines pin-muxing selection for GPIO6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "GPIO5,Defines pin-muxing selection for GPIO5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GPIO4,Defines pin-muxing selection for GPIO4" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "GPIO3,Defines pin-muxing selection for GPIO3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GPIO2,Defines pin-muxing selection for GPIO2" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GPIO1,Defines pin-muxing selection for GPIO1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GPIO0,Defines pin-muxing selection for GPIO0" "0,1,2,3"
|
|
line.long 0x2 "GPAGMUX2,GPIO A Peripheral Group Mux (GPIO16 to 31)"
|
|
bitfld.long 0x2 30.--31. "GPIO31,Defines pin-muxing selection for GPIO31" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "GPIO30,Defines pin-muxing selection for GPIO30" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "GPIO29,Defines pin-muxing selection for GPIO29" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GPIO28,Defines pin-muxing selection for GPIO28" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GPIO27,Defines pin-muxing selection for GPIO27" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GPIO26,Defines pin-muxing selection for GPIO26" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GPIO25,Defines pin-muxing selection for GPIO25" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "GPIO24,Defines pin-muxing selection for GPIO24" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GPIO23,Defines pin-muxing selection for GPIO23" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GPIO22,Defines pin-muxing selection for GPIO22" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 10.--11. "GPIO21,Defines pin-muxing selection for GPIO21" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPIO20,Defines pin-muxing selection for GPIO20" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "GPIO19,Defines pin-muxing selection for GPIO19" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPIO18,Defines pin-muxing selection for GPIO18" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GPIO17,Defines pin-muxing selection for GPIO17" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GPIO16,Defines pin-muxing selection for GPIO16" "0,1,2,3"
|
|
group.long 0x28++0xF
|
|
line.long 0x0 "GPACSEL1,GPIO A Core Select Register (GPIO0 to 7)"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GPIO7,GPIO7 Master CPU Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "GPIO6,GPIO6 Master CPU Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "GPIO5,GPIO5 Master CPU Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GPIO4,GPIO4 Master CPU Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "GPIO3,GPIO3 Master CPU Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GPIO2,GPIO2 Master CPU Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GPIO1,GPIO1 Master CPU Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GPIO0,GPIO0 Master CPU Select"
|
|
line.long 0x2 "GPACSEL2,GPIO A Core Select Register (GPIO8 to 15)"
|
|
hexmask.long.byte 0x2 28.--31. 1. "GPIO15,GPIO15 Master CPU Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "GPIO14,GPIO14 Master CPU Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "GPIO13,GPIO13 Master CPU Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "GPIO12,GPIO12 Master CPU Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "GPIO11,GPIO11 Master CPU Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "GPIO10,GPIO10 Master CPU Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "GPIO9,GPIO9 Master CPU Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "GPIO8,GPIO8 Master CPU Select"
|
|
line.long 0x4 "GPACSEL3,GPIO A Core Select Register (GPIO16 to 23)"
|
|
hexmask.long.byte 0x4 28.--31. 1. "GPIO23,GPIO23 Master CPU Select"
|
|
hexmask.long.byte 0x4 24.--27. 1. "GPIO22,GPIO22 Master CPU Select"
|
|
hexmask.long.byte 0x4 20.--23. 1. "GPIO21,GPIO21 Master CPU Select"
|
|
hexmask.long.byte 0x4 16.--19. 1. "GPIO20,GPIO20 Master CPU Select"
|
|
hexmask.long.byte 0x4 12.--15. 1. "GPIO19,GPIO19 Master CPU Select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "GPIO18,GPIO18 Master CPU Select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GPIO17,GPIO17 Master CPU Select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GPIO16,GPIO16 Master CPU Select"
|
|
line.long 0x6 "GPACSEL4,GPIO A Core Select Register (GPIO24 to 31)"
|
|
hexmask.long.byte 0x6 28.--31. 1. "GPIO31,GPIO31 Master CPU Select"
|
|
hexmask.long.byte 0x6 24.--27. 1. "GPIO30,GPIO30 Master CPU Select"
|
|
hexmask.long.byte 0x6 20.--23. 1. "GPIO29,GPIO29 Master CPU Select"
|
|
hexmask.long.byte 0x6 16.--19. 1. "GPIO28,GPIO28 Master CPU Select"
|
|
hexmask.long.byte 0x6 12.--15. 1. "GPIO27,GPIO27 Master CPU Select"
|
|
hexmask.long.byte 0x6 8.--11. 1. "GPIO26,GPIO26 Master CPU Select"
|
|
hexmask.long.byte 0x6 4.--7. 1. "GPIO25,GPIO25 Master CPU Select"
|
|
hexmask.long.byte 0x6 0.--3. 1. "GPIO24,GPIO24 Master CPU Select"
|
|
group.long 0x3C++0x2F
|
|
line.long 0x0 "GPALOCK,GPIO A Lock Configuration Register (GPIO0 to 31)"
|
|
bitfld.long 0x0 31. "GPIO31,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO30,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO29,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO28,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO27,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO26,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO25,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO24,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO23,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO22,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO21,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO20,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 19. "GPIO19,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO18,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO17,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO16,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO15,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO14,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO13,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO12,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO11,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO10,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO9,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO8,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 7. "GPIO7,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO6,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO5,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO4,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO3,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO2,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO1,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO0,Configuration Lock bit for this pin" "0,1"
|
|
line.long 0x2 "GPACR,GPIO A Lock Commit Register (GPIO0 to 31)"
|
|
bitfld.long 0x2 31. "GPIO31,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 30. "GPIO30,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 29. "GPIO29,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 28. "GPIO28,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 27. "GPIO27,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 26. "GPIO26,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 25. "GPIO25,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 24. "GPIO24,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 23. "GPIO23,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 22. "GPIO22,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 21. "GPIO21,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 20. "GPIO20,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 19. "GPIO19,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 18. "GPIO18,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 17. "GPIO17,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 16. "GPIO16,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 15. "GPIO15,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 14. "GPIO14,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 13. "GPIO13,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 12. "GPIO12,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "GPIO11,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 10. "GPIO10,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 9. "GPIO9,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 8. "GPIO8,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 7. "GPIO7,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO6,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO5,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO4,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO3,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO2,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "GPIO1,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO0,Configuration lock commit bit for this pin" "0,1"
|
|
line.long 0x4 "GPBCTRL,GPIO B Qualification Sampling Period Control (GPIO32 to 63)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO56 to GPIO63"
|
|
hexmask.long.byte 0x4 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO48 to GPIO55"
|
|
hexmask.long.byte 0x4 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO40 to GPIO47"
|
|
hexmask.long.byte 0x4 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO32 to GPIO39"
|
|
line.long 0x6 "GPBQSEL1,GPIO B Qualifier Select 1 Register (GPIO32 to 47)"
|
|
bitfld.long 0x6 30.--31. "GPIO47,Select input qualification type for GPIO47" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "GPIO46,Select input qualification type for GPIO46" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "GPIO45,Select input qualification type for GPIO45" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "GPIO44,Select input qualification type for GPIO44" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "GPIO43,Select input qualification type for GPIO43" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "GPIO42,Select input qualification type for GPIO42" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "GPIO41,Select input qualification type for GPIO41" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GPIO40,Select input qualification type for GPIO40" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GPIO39,Select input qualification type for GPIO39" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GPIO38,Select input qualification type for GPIO38" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 10.--11. "GPIO37,Select input qualification type for GPIO37" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "GPIO36,Select input qualification type for GPIO36" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GPIO35,Select input qualification type for GPIO35" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GPIO34,Select input qualification type for GPIO34" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GPIO33,Select input qualification type for GPIO33" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GPIO32,Select input qualification type for GPIO32" "0,1,2,3"
|
|
line.long 0x8 "GPBQSEL2,GPIO B Qualifier Select 2 Register (GPIO48 to 63)"
|
|
bitfld.long 0x8 30.--31. "GPIO63,Select input qualification type for GPIO63" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GPIO62,Select input qualification type for GPIO62" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GPIO61,Select input qualification type for GPIO61" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GPIO60,Select input qualification type for GPIO60" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GPIO59,Select input qualification type for GPIO59" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GPIO58,Select input qualification type for GPIO58" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GPIO57,Select input qualification type for GPIO57" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GPIO56,Select input qualification type for GPIO56" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GPIO55,Select input qualification type for GPIO55" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GPIO54,Select input qualification type for GPIO54" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GPIO53,Select input qualification type for GPIO53" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GPIO52,Select input qualification type for GPIO52" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "GPIO51,Select input qualification type for GPIO51" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GPIO50,Select input qualification type for GPIO50" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GPIO49,Select input qualification type for GPIO49" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GPIO48,Select input qualification type for GPIO48" "0,1,2,3"
|
|
line.long 0xA "GPBMUX1,GPIO B Mux 1 Register (GPIO32 to 47)"
|
|
bitfld.long 0xA 30.--31. "GPIO47,Defines pin-muxing selection for GPIO47" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "GPIO46,Defines pin-muxing selection for GPIO46" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "GPIO45,Defines pin-muxing selection for GPIO45" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "GPIO44,Defines pin-muxing selection for GPIO44" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "GPIO43,Defines pin-muxing selection for GPIO43" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "GPIO42,Defines pin-muxing selection for GPIO42" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "GPIO41,Defines pin-muxing selection for GPIO41" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "GPIO40,Defines pin-muxing selection for GPIO40" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GPIO39,Defines pin-muxing selection for GPIO39" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GPIO38,Defines pin-muxing selection for GPIO38" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 10.--11. "GPIO37,Defines pin-muxing selection for GPIO37" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "GPIO36,Defines pin-muxing selection for GPIO36" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GPIO35,Defines pin-muxing selection for GPIO35" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GPIO34,Defines pin-muxing selection for GPIO34" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GPIO33,Defines pin-muxing selection for GPIO33" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GPIO32,Defines pin-muxing selection for GPIO32" "0,1,2,3"
|
|
line.long 0xC "GPBMUX2,GPIO B Mux 2 Register (GPIO48 to 63)"
|
|
bitfld.long 0xC 30.--31. "GPIO63,Defines pin-muxing selection for GPIO63" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "GPIO62,Defines pin-muxing selection for GPIO62" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "GPIO61,Defines pin-muxing selection for GPIO61" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "GPIO60,Defines pin-muxing selection for GPIO60" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "GPIO59,Defines pin-muxing selection for GPIO59" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "GPIO58,Defines pin-muxing selection for GPIO58" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "GPIO57,Defines pin-muxing selection for GPIO57" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "GPIO56,Defines pin-muxing selection for GPIO56" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "GPIO55,Defines pin-muxing selection for GPIO55" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "GPIO54,Defines pin-muxing selection for GPIO54" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "GPIO53,Defines pin-muxing selection for GPIO53" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "GPIO52,Defines pin-muxing selection for GPIO52" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "GPIO51,Defines pin-muxing selection for GPIO51" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "GPIO50,Defines pin-muxing selection for GPIO50" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "GPIO49,Defines pin-muxing selection for GPIO49" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "GPIO48,Defines pin-muxing selection for GPIO48" "0,1,2,3"
|
|
line.long 0xE "GPBDIR,GPIO B Direction Register (GPIO32 to 63)"
|
|
bitfld.long 0xE 31. "GPIO63,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 30. "GPIO62,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 29. "GPIO61,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 28. "GPIO60,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 27. "GPIO59,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 26. "GPIO58,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 25. "GPIO57,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 24. "GPIO56,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 23. "GPIO55,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 22. "GPIO54,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "GPIO53,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 20. "GPIO52,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 19. "GPIO51,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 18. "GPIO50,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 17. "GPIO49,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 16. "GPIO48,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 15. "GPIO47,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 14. "GPIO46,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 13. "GPIO45,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 12. "GPIO44,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 11. "GPIO43,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 10. "GPIO42,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 9. "GPIO41,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 8. "GPIO40,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 7. "GPIO39,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 6. "GPIO38,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 5. "GPIO37,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 4. "GPIO36,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 3. "GPIO35,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 2. "GPIO34,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 1. "GPIO33,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 0. "GPIO32,Defines direction for this pin in GPIO mode" "0,1"
|
|
line.long 0x10 "GPBPUD,GPIO B Pull Up Disable Register (GPIO32 to 63)"
|
|
bitfld.long 0x10 31. "GPIO63,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO62,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO61,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO60,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO59,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO58,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO57,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO56,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO55,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO54,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "GPIO53,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO52,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 19. "GPIO51,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO50,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO49,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO48,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO47,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO46,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO45,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO44,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "GPIO43,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO42,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO41,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO40,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 7. "GPIO39,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO38,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO37,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO36,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO35,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO34,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GPIO33,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO32,Pull-Up Disable control for this pin" "0,1"
|
|
line.long 0x14 "GPBINV,GPIO B Input Polarity Invert Registers (GPIO32 to 63)"
|
|
bitfld.long 0x14 31. "GPIO63,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 30. "GPIO62,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 29. "GPIO61,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 28. "GPIO60,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 27. "GPIO59,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 26. "GPIO58,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 25. "GPIO57,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 24. "GPIO56,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 23. "GPIO55,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 22. "GPIO54,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "GPIO53,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 20. "GPIO52,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 19. "GPIO51,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 18. "GPIO50,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 17. "GPIO49,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 16. "GPIO48,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 15. "GPIO47,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 14. "GPIO46,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 13. "GPIO45,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 12. "GPIO44,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "GPIO43,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 10. "GPIO42,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 9. "GPIO41,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 8. "GPIO40,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 7. "GPIO39,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO38,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO37,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO36,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO35,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO34,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GPIO33,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO32,Input inversion control for this pin" "0,1"
|
|
line.long 0x16 "GPBODR,GPIO B Open Drain Output Register (GPIO32 to GPIO63)"
|
|
bitfld.long 0x16 31. "GPIO63,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 30. "GPIO62,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 29. "GPIO61,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 28. "GPIO60,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 27. "GPIO59,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 26. "GPIO58,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 25. "GPIO57,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 24. "GPIO56,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 23. "GPIO55,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 22. "GPIO54,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 21. "GPIO53,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 20. "GPIO52,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 19. "GPIO51,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 18. "GPIO50,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 17. "GPIO49,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 16. "GPIO48,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 15. "GPIO47,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 14. "GPIO46,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 13. "GPIO45,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 12. "GPIO44,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 11. "GPIO43,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 10. "GPIO42,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 9. "GPIO41,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 8. "GPIO40,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 7. "GPIO39,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 6. "GPIO38,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 5. "GPIO37,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 4. "GPIO36,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 3. "GPIO35,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 2. "GPIO34,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 1. "GPIO33,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 0. "GPIO32,Outpout Open-Drain control for this pin" "0,1"
|
|
line.long 0x18 "GPBAMSEL,GPIO B Analog Mode Select register (GPIO32 to GPIO63)"
|
|
bitfld.long 0x18 11. "GPIO43,Analog Mode select for this pin" "0,1"
|
|
bitfld.long 0x18 10. "GPIO42,Analog Mode select for this pin" "0,1"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "GPBGMUX1,GPIO B Peripheral Group Mux (GPIO32 to 47)"
|
|
bitfld.long 0x0 30.--31. "GPIO47,Defines pin-muxing selection for GPIO47" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "GPIO46,Defines pin-muxing selection for GPIO46" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "GPIO45,Defines pin-muxing selection for GPIO45" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GPIO44,Defines pin-muxing selection for GPIO44" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GPIO43,Defines pin-muxing selection for GPIO43" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GPIO42,Defines pin-muxing selection for GPIO42" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GPIO41,Defines pin-muxing selection for GPIO41" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "GPIO40,Defines pin-muxing selection for GPIO40" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GPIO39,Defines pin-muxing selection for GPIO39" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GPIO38,Defines pin-muxing selection for GPIO38" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "GPIO37,Defines pin-muxing selection for GPIO37" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GPIO36,Defines pin-muxing selection for GPIO36" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "GPIO35,Defines pin-muxing selection for GPIO35" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GPIO34,Defines pin-muxing selection for GPIO34" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GPIO33,Defines pin-muxing selection for GPIO33" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GPIO32,Defines pin-muxing selection for GPIO32" "0,1,2,3"
|
|
line.long 0x2 "GPBGMUX2,GPIO B Peripheral Group Mux (GPIO48 to 63)"
|
|
bitfld.long 0x2 30.--31. "GPIO63,Defines pin-muxing selection for GPIO63" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "GPIO62,Defines pin-muxing selection for GPIO62" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "GPIO61,Defines pin-muxing selection for GPIO61" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GPIO60,Defines pin-muxing selection for GPIO60" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GPIO59,Defines pin-muxing selection for GPIO59" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GPIO58,Defines pin-muxing selection for GPIO58" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GPIO57,Defines pin-muxing selection for GPIO57" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "GPIO56,Defines pin-muxing selection for GPIO56" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GPIO55,Defines pin-muxing selection for GPIO55" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GPIO54,Defines pin-muxing selection for GPIO54" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 10.--11. "GPIO53,Defines pin-muxing selection for GPIO53" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPIO52,Defines pin-muxing selection for GPIO52" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "GPIO51,Defines pin-muxing selection for GPIO51" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPIO50,Defines pin-muxing selection for GPIO50" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GPIO49,Defines pin-muxing selection for GPIO49" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GPIO48,Defines pin-muxing selection for GPIO48" "0,1,2,3"
|
|
group.long 0x68++0xF
|
|
line.long 0x0 "GPBCSEL1,GPIO B Core Select Register (GPIO32 to 39)"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GPIO39,GPIO39 Master CPU Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "GPIO38,GPIO38 Master CPU Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "GPIO37,GPIO37 Master CPU Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GPIO36,GPIO36 Master CPU Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "GPIO35,GPIO35 Master CPU Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GPIO34,GPIO34 Master CPU Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GPIO33,GPIO33 Master CPU Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GPIO32,GPIO32 Master CPU Select"
|
|
line.long 0x2 "GPBCSEL2,GPIO B Core Select Register (GPIO40 to 47)"
|
|
hexmask.long.byte 0x2 28.--31. 1. "GPIO47,GPIO47 Master CPU Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "GPIO46,GPIO46 Master CPU Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "GPIO45,GPIO45 Master CPU Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "GPIO44,GPIO44 Master CPU Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "GPIO43,GPIO43 Master CPU Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "GPIO42,GPIO42 Master CPU Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "GPIO41,GPIO41 Master CPU Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "GPIO40,GPIO40 Master CPU Select"
|
|
line.long 0x4 "GPBCSEL3,GPIO B Core Select Register (GPIO48 to 55)"
|
|
hexmask.long.byte 0x4 28.--31. 1. "GPIO55,GPIO55 Master CPU Select"
|
|
hexmask.long.byte 0x4 24.--27. 1. "GPIO54,GPIO54 Master CPU Select"
|
|
hexmask.long.byte 0x4 20.--23. 1. "GPIO53,GPIO53 Master CPU Select"
|
|
hexmask.long.byte 0x4 16.--19. 1. "GPIO52,GPIO52 Master CPU Select"
|
|
hexmask.long.byte 0x4 12.--15. 1. "GPIO51,GPIO51 Master CPU Select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "GPIO50,GPIO50 Master CPU Select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GPIO49,GPIO49 Master CPU Select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GPIO48,GPIO48 Master CPU Select"
|
|
line.long 0x6 "GPBCSEL4,GPIO B Core Select Register (GPIO56 to 63)"
|
|
hexmask.long.byte 0x6 28.--31. 1. "GPIO63,GPIO63 Master CPU Select"
|
|
hexmask.long.byte 0x6 24.--27. 1. "GPIO62,GPIO62 Master CPU Select"
|
|
hexmask.long.byte 0x6 20.--23. 1. "GPIO61,GPIO61 Master CPU Select"
|
|
hexmask.long.byte 0x6 16.--19. 1. "GPIO60,GPIO60 Master CPU Select"
|
|
hexmask.long.byte 0x6 12.--15. 1. "GPIO59,GPIO59 Master CPU Select"
|
|
hexmask.long.byte 0x6 8.--11. 1. "GPIO58,GPIO58 Master CPU Select"
|
|
hexmask.long.byte 0x6 4.--7. 1. "GPIO57,GPIO57 Master CPU Select"
|
|
hexmask.long.byte 0x6 0.--3. 1. "GPIO56,GPIO56 Master CPU Select"
|
|
group.long 0x7C++0x2B
|
|
line.long 0x0 "GPBLOCK,GPIO B Lock Configuration Register (GPIO32 to 63)"
|
|
bitfld.long 0x0 31. "GPIO63,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO62,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO61,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO60,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO59,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO58,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO57,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO56,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO55,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO54,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO53,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO52,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 19. "GPIO51,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO50,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO49,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO48,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO47,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO46,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO45,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO44,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO43,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO42,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO41,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO40,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 7. "GPIO39,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO38,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO37,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO36,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO35,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO34,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO33,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO32,Configuration Lock bit for this pin" "0,1"
|
|
line.long 0x2 "GPBCR,GPIO B Lock Commit Register (GPIO32 to 63)"
|
|
bitfld.long 0x2 31. "GPIO63,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 30. "GPIO62,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 29. "GPIO61,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 28. "GPIO60,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 27. "GPIO59,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 26. "GPIO58,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 25. "GPIO57,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 24. "GPIO56,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 23. "GPIO55,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 22. "GPIO54,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 21. "GPIO53,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 20. "GPIO52,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 19. "GPIO51,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 18. "GPIO50,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 17. "GPIO49,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 16. "GPIO48,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 15. "GPIO47,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 14. "GPIO46,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 13. "GPIO45,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 12. "GPIO44,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "GPIO43,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 10. "GPIO42,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 9. "GPIO41,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 8. "GPIO40,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 7. "GPIO39,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO38,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO37,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO36,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO35,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO34,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "GPIO33,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO32,Configuration lock commit bit for this pin" "0,1"
|
|
line.long 0x4 "GPCCTRL,GPIO C Qualification Sampling Period Control (GPIO64 to 95)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO88 to GPIO95"
|
|
hexmask.long.byte 0x4 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO80 to GPIO87"
|
|
hexmask.long.byte 0x4 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO72 to GPIO79"
|
|
hexmask.long.byte 0x4 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO64 to GPIO71"
|
|
line.long 0x6 "GPCQSEL1,GPIO C Qualifier Select 1 Register (GPIO64 to 79)"
|
|
bitfld.long 0x6 30.--31. "GPIO79,Select input qualification type for GPIO79" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "GPIO78,Select input qualification type for GPIO78" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "GPIO77,Select input qualification type for GPIO77" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "GPIO76,Select input qualification type for GPIO76" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "GPIO75,Select input qualification type for GPIO75" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "GPIO74,Select input qualification type for GPIO74" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "GPIO73,Select input qualification type for GPIO73" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GPIO72,Select input qualification type for GPIO72" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GPIO71,Select input qualification type for GPIO71" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GPIO70,Select input qualification type for GPIO70" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 10.--11. "GPIO69,Select input qualification type for GPIO69" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "GPIO68,Select input qualification type for GPIO68" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GPIO67,Select input qualification type for GPIO67" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GPIO66,Select input qualification type for GPIO66" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GPIO65,Select input qualification type for GPIO65" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GPIO64,Select input qualification type for GPIO64" "0,1,2,3"
|
|
line.long 0x8 "GPCQSEL2,GPIO C Qualifier Select 2 Register (GPIO80 to 95)"
|
|
bitfld.long 0x8 30.--31. "GPIO95,Select input qualification type for GPIO95" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GPIO94,Select input qualification type for GPIO94" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GPIO93,Select input qualification type for GPIO93" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GPIO92,Select input qualification type for GPIO92" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GPIO91,Select input qualification type for GPIO91" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GPIO90,Select input qualification type for GPIO90" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GPIO89,Select input qualification type for GPIO89" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GPIO88,Select input qualification type for GPIO88" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GPIO87,Select input qualification type for GPIO87" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GPIO86,Select input qualification type for GPIO86" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GPIO85,Select input qualification type for GPIO85" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GPIO84,Select input qualification type for GPIO84" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "GPIO83,Select input qualification type for GPIO83" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GPIO82,Select input qualification type for GPIO82" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GPIO81,Select input qualification type for GPIO81" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GPIO80,Select input qualification type for GPIO80" "0,1,2,3"
|
|
line.long 0xA "GPCMUX1,GPIO C Mux 1 Register (GPIO64 to 79)"
|
|
bitfld.long 0xA 30.--31. "GPIO79,Defines pin-muxing selection for GPIO79" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "GPIO78,Defines pin-muxing selection for GPIO78" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "GPIO77,Defines pin-muxing selection for GPIO77" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "GPIO76,Defines pin-muxing selection for GPIO76" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "GPIO75,Defines pin-muxing selection for GPIO75" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "GPIO74,Defines pin-muxing selection for GPIO74" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "GPIO73,Defines pin-muxing selection for GPIO73" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "GPIO72,Defines pin-muxing selection for GPIO72" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GPIO71,Defines pin-muxing selection for GPIO71" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GPIO70,Defines pin-muxing selection for GPIO70" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 10.--11. "GPIO69,Defines pin-muxing selection for GPIO69" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "GPIO68,Defines pin-muxing selection for GPIO68" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GPIO67,Defines pin-muxing selection for GPIO67" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GPIO66,Defines pin-muxing selection for GPIO66" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GPIO65,Defines pin-muxing selection for GPIO65" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GPIO64,Defines pin-muxing selection for GPIO64" "0,1,2,3"
|
|
line.long 0xC "GPCMUX2,GPIO C Mux 2 Register (GPIO80 to 95)"
|
|
bitfld.long 0xC 30.--31. "GPIO95,Defines pin-muxing selection for GPIO95" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "GPIO94,Defines pin-muxing selection for GPIO94" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "GPIO93,Defines pin-muxing selection for GPIO93" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "GPIO92,Defines pin-muxing selection for GPIO92" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "GPIO91,Defines pin-muxing selection for GPIO91" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "GPIO90,Defines pin-muxing selection for GPIO90" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "GPIO89,Defines pin-muxing selection for GPIO89" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "GPIO88,Defines pin-muxing selection for GPIO88" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "GPIO87,Defines pin-muxing selection for GPIO87" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "GPIO86,Defines pin-muxing selection for GPIO86" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "GPIO85,Defines pin-muxing selection for GPIO85" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "GPIO84,Defines pin-muxing selection for GPIO84" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "GPIO83,Defines pin-muxing selection for GPIO83" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "GPIO82,Defines pin-muxing selection for GPIO82" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "GPIO81,Defines pin-muxing selection for GPIO81" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "GPIO80,Defines pin-muxing selection for GPIO80" "0,1,2,3"
|
|
line.long 0xE "GPCDIR,GPIO C Direction Register (GPIO64 to 95)"
|
|
bitfld.long 0xE 31. "GPIO95,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 30. "GPIO94,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 29. "GPIO93,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 28. "GPIO92,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 27. "GPIO91,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 26. "GPIO90,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 25. "GPIO89,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 24. "GPIO88,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 23. "GPIO87,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 22. "GPIO86,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "GPIO85,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 20. "GPIO84,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 19. "GPIO83,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 18. "GPIO82,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 17. "GPIO81,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 16. "GPIO80,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 15. "GPIO79,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 14. "GPIO78,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 13. "GPIO77,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 12. "GPIO76,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 11. "GPIO75,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 10. "GPIO74,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 9. "GPIO73,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 8. "GPIO72,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 7. "GPIO71,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 6. "GPIO70,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 5. "GPIO69,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 4. "GPIO68,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 3. "GPIO67,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 2. "GPIO66,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 1. "GPIO65,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 0. "GPIO64,Defines direction for this pin in GPIO mode" "0,1"
|
|
line.long 0x10 "GPCPUD,GPIO C Pull Up Disable Register (GPIO64 to 95)"
|
|
bitfld.long 0x10 31. "GPIO95,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO94,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO93,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO92,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO91,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO90,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO89,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO88,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO87,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO86,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "GPIO85,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO84,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 19. "GPIO83,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO82,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO81,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO80,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO79,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO78,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO77,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO76,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "GPIO75,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO74,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO73,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO72,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 7. "GPIO71,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO70,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO69,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO68,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO67,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO66,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GPIO65,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO64,Pull-Up Disable control for this pin" "0,1"
|
|
line.long 0x14 "GPCINV,GPIO C Input Polarity Invert Registers (GPIO64 to 95)"
|
|
bitfld.long 0x14 31. "GPIO95,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 30. "GPIO94,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 29. "GPIO93,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 28. "GPIO92,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 27. "GPIO91,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 26. "GPIO90,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 25. "GPIO89,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 24. "GPIO88,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 23. "GPIO87,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 22. "GPIO86,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "GPIO85,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 20. "GPIO84,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 19. "GPIO83,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 18. "GPIO82,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 17. "GPIO81,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 16. "GPIO80,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 15. "GPIO79,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 14. "GPIO78,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 13. "GPIO77,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 12. "GPIO76,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "GPIO75,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 10. "GPIO74,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 9. "GPIO73,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 8. "GPIO72,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 7. "GPIO71,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO70,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO69,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO68,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO67,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO66,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GPIO65,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO64,Input inversion control for this pin" "0,1"
|
|
line.long 0x16 "GPCODR,GPIO C Open Drain Output Register (GPIO64 to GPIO95)"
|
|
bitfld.long 0x16 31. "GPIO95,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 30. "GPIO94,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 29. "GPIO93,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 28. "GPIO92,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 27. "GPIO91,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 26. "GPIO90,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 25. "GPIO89,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 24. "GPIO88,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 23. "GPIO87,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 22. "GPIO86,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 21. "GPIO85,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 20. "GPIO84,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 19. "GPIO83,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 18. "GPIO82,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 17. "GPIO81,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 16. "GPIO80,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 15. "GPIO79,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 14. "GPIO78,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 13. "GPIO77,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 12. "GPIO76,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 11. "GPIO75,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 10. "GPIO74,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 9. "GPIO73,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 8. "GPIO72,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 7. "GPIO71,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 6. "GPIO70,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 5. "GPIO69,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 4. "GPIO68,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 3. "GPIO67,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 2. "GPIO66,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 1. "GPIO65,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 0. "GPIO64,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "GPCGMUX1,GPIO C Peripheral Group Mux (GPIO64 to 79)"
|
|
bitfld.long 0x0 30.--31. "GPIO79,Defines pin-muxing selection for GPIO79" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "GPIO78,Defines pin-muxing selection for GPIO78" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "GPIO77,Defines pin-muxing selection for GPIO77" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GPIO76,Defines pin-muxing selection for GPIO76" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GPIO75,Defines pin-muxing selection for GPIO75" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GPIO74,Defines pin-muxing selection for GPIO74" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GPIO73,Defines pin-muxing selection for GPIO73" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "GPIO72,Defines pin-muxing selection for GPIO72" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GPIO71,Defines pin-muxing selection for GPIO71" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GPIO70,Defines pin-muxing selection for GPIO70" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "GPIO69,Defines pin-muxing selection for GPIO69" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GPIO68,Defines pin-muxing selection for GPIO68" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "GPIO67,Defines pin-muxing selection for GPIO67" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GPIO66,Defines pin-muxing selection for GPIO66" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GPIO65,Defines pin-muxing selection for GPIO65" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GPIO64,Defines pin-muxing selection for GPIO64" "0,1,2,3"
|
|
line.long 0x2 "GPCGMUX2,GPIO C Peripheral Group Mux (GPIO80 to 95)"
|
|
bitfld.long 0x2 30.--31. "GPIO95,Defines pin-muxing selection for GPIO95" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "GPIO94,Defines pin-muxing selection for GPIO94" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "GPIO93,Defines pin-muxing selection for GPIO93" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GPIO92,Defines pin-muxing selection for GPIO92" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GPIO91,Defines pin-muxing selection for GPIO91" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GPIO90,Defines pin-muxing selection for GPIO90" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GPIO89,Defines pin-muxing selection for GPIO89" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "GPIO88,Defines pin-muxing selection for GPIO88" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GPIO87,Defines pin-muxing selection for GPIO87" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GPIO86,Defines pin-muxing selection for GPIO86" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 10.--11. "GPIO85,Defines pin-muxing selection for GPIO85" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPIO84,Defines pin-muxing selection for GPIO84" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "GPIO83,Defines pin-muxing selection for GPIO83" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPIO82,Defines pin-muxing selection for GPIO82" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GPIO81,Defines pin-muxing selection for GPIO81" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GPIO80,Defines pin-muxing selection for GPIO80" "0,1,2,3"
|
|
group.long 0xA8++0xF
|
|
line.long 0x0 "GPCCSEL1,GPIO C Core Select Register (GPIO64 to 71)"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GPIO71,GPIO71 Master CPU Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "GPIO70,GPIO70 Master CPU Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "GPIO69,GPIO69 Master CPU Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GPIO68,GPIO68 Master CPU Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "GPIO67,GPIO67 Master CPU Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GPIO66,GPIO66 Master CPU Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GPIO65,GPIO65 Master CPU Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GPIO64,GPIO64 Master CPU Select"
|
|
line.long 0x2 "GPCCSEL2,GPIO C Core Select Register (GPIO72 to 79)"
|
|
hexmask.long.byte 0x2 28.--31. 1. "GPIO79,GPIO79 Master CPU Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "GPIO78,GPIO78 Master CPU Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "GPIO77,GPIO77 Master CPU Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "GPIO76,GPIO76 Master CPU Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "GPIO75,GPIO75 Master CPU Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "GPIO74,GPIO74 Master CPU Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "GPIO73,GPIO73 Master CPU Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "GPIO72,GPIO72 Master CPU Select"
|
|
line.long 0x4 "GPCCSEL3,GPIO C Core Select Register (GPIO80 to 87)"
|
|
hexmask.long.byte 0x4 28.--31. 1. "GPIO87,GPIO87 Master CPU Select"
|
|
hexmask.long.byte 0x4 24.--27. 1. "GPIO86,GPIO86 Master CPU Select"
|
|
hexmask.long.byte 0x4 20.--23. 1. "GPIO85,GPIO85 Master CPU Select"
|
|
hexmask.long.byte 0x4 16.--19. 1. "GPIO84,GPIO84 Master CPU Select"
|
|
hexmask.long.byte 0x4 12.--15. 1. "GPIO83,GPIO83 Master CPU Select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "GPIO82,GPIO82 Master CPU Select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GPIO81,GPIO81 Master CPU Select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GPIO80,GPIO80 Master CPU Select"
|
|
line.long 0x6 "GPCCSEL4,GPIO C Core Select Register (GPIO88 to 95)"
|
|
hexmask.long.byte 0x6 28.--31. 1. "GPIO95,GPIO95 Master CPU Select"
|
|
hexmask.long.byte 0x6 24.--27. 1. "GPIO94,GPIO94 Master CPU Select"
|
|
hexmask.long.byte 0x6 20.--23. 1. "GPIO93,GPIO93 Master CPU Select"
|
|
hexmask.long.byte 0x6 16.--19. 1. "GPIO92,GPIO92 Master CPU Select"
|
|
hexmask.long.byte 0x6 12.--15. 1. "GPIO91,GPIO91 Master CPU Select"
|
|
hexmask.long.byte 0x6 8.--11. 1. "GPIO90,GPIO90 Master CPU Select"
|
|
hexmask.long.byte 0x6 4.--7. 1. "GPIO89,GPIO89 Master CPU Select"
|
|
hexmask.long.byte 0x6 0.--3. 1. "GPIO88,GPIO88 Master CPU Select"
|
|
group.long 0xBC++0x2B
|
|
line.long 0x0 "GPCLOCK,GPIO C Lock Configuration Register (GPIO64 to 95)"
|
|
bitfld.long 0x0 31. "GPIO95,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO94,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO93,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO92,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO91,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO90,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO89,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO88,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO87,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO86,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO85,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO84,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 19. "GPIO83,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO82,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO81,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO80,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO79,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO78,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO77,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO76,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO75,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO74,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO73,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO72,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 7. "GPIO71,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO70,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO69,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO68,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO67,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO66,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO65,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO64,Configuration Lock bit for this pin" "0,1"
|
|
line.long 0x2 "GPCCR,GPIO C Lock Commit Register (GPIO64 to 95)"
|
|
bitfld.long 0x2 31. "GPIO95,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 30. "GPIO94,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 29. "GPIO93,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 28. "GPIO92,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 27. "GPIO91,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 26. "GPIO90,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 25. "GPIO89,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 24. "GPIO88,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 23. "GPIO87,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 22. "GPIO86,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 21. "GPIO85,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 20. "GPIO84,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 19. "GPIO83,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 18. "GPIO82,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 17. "GPIO81,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 16. "GPIO80,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 15. "GPIO79,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 14. "GPIO78,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 13. "GPIO77,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 12. "GPIO76,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "GPIO75,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 10. "GPIO74,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 9. "GPIO73,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 8. "GPIO72,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 7. "GPIO71,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO70,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO69,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO68,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO67,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO66,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "GPIO65,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO64,Configuration lock commit bit for this pin" "0,1"
|
|
line.long 0x4 "GPDCTRL,GPIO D Qualification Sampling Period Control (GPIO96 to 127)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO120 to GPIO127"
|
|
hexmask.long.byte 0x4 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO112 to GPIO119"
|
|
hexmask.long.byte 0x4 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO104 to GPIO111"
|
|
hexmask.long.byte 0x4 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO96 to GPIO103"
|
|
line.long 0x6 "GPDQSEL1,GPIO D Qualifier Select 1 Register (GPIO96 to 111)"
|
|
bitfld.long 0x6 30.--31. "GPIO111,Select input qualification type for GPIO111" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "GPIO110,Select input qualification type for GPIO110" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "GPIO109,Select input qualification type for GPIO109" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "GPIO108,Select input qualification type for GPIO108" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "GPIO107,Select input qualification type for GPIO107" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "GPIO106,Select input qualification type for GPIO106" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "GPIO105,Select input qualification type for GPIO105" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GPIO104,Select input qualification type for GPIO104" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GPIO103,Select input qualification type for GPIO103" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GPIO102,Select input qualification type for GPIO102" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 10.--11. "GPIO101,Select input qualification type for GPIO101" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "GPIO100,Select input qualification type for GPIO100" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GPIO99,Select input qualification type for GPIO99" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GPIO98,Select input qualification type for GPIO98" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GPIO97,Select input qualification type for GPIO97" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GPIO96,Select input qualification type for GPIO96" "0,1,2,3"
|
|
line.long 0x8 "GPDQSEL2,GPIO D Qualifier Select 2 Register (GPIO112 to 127)"
|
|
bitfld.long 0x8 30.--31. "GPIO127,Select input qualification type for GPIO127" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GPIO126,Select input qualification type for GPIO126" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GPIO125,Select input qualification type for GPIO125" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GPIO124,Select input qualification type for GPIO124" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GPIO123,Select input qualification type for GPIO123" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GPIO122,Select input qualification type for GPIO122" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GPIO121,Select input qualification type for GPIO121" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GPIO120,Select input qualification type for GPIO120" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GPIO119,Select input qualification type for GPIO119" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GPIO118,Select input qualification type for GPIO118" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GPIO117,Select input qualification type for GPIO117" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GPIO116,Select input qualification type for GPIO116" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "GPIO115,Select input qualification type for GPIO115" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GPIO114,Select input qualification type for GPIO114" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GPIO113,Select input qualification type for GPIO113" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GPIO112,Select input qualification type for GPIO112" "0,1,2,3"
|
|
line.long 0xA "GPDMUX1,GPIO D Mux 1 Register (GPIO96 to 111)"
|
|
bitfld.long 0xA 30.--31. "GPIO111,Defines pin-muxing selection for GPIO111" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "GPIO110,Defines pin-muxing selection for GPIO110" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "GPIO109,Defines pin-muxing selection for GPIO109" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "GPIO108,Defines pin-muxing selection for GPIO108" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "GPIO107,Defines pin-muxing selection for GPIO107" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "GPIO106,Defines pin-muxing selection for GPIO106" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "GPIO105,Defines pin-muxing selection for GPIO105" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "GPIO104,Defines pin-muxing selection for GPIO104" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GPIO103,Defines pin-muxing selection for GPIO103" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GPIO102,Defines pin-muxing selection for GPIO102" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 10.--11. "GPIO101,Defines pin-muxing selection for GPIO101" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "GPIO100,Defines pin-muxing selection for GPIO100" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GPIO99,Defines pin-muxing selection for GPIO99" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GPIO98,Defines pin-muxing selection for GPIO98" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GPIO97,Defines pin-muxing selection for GPIO97" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GPIO96,Defines pin-muxing selection for GPIO96" "0,1,2,3"
|
|
line.long 0xC "GPDMUX2,GPIO D Mux 2 Register (GPIO112 to 127)"
|
|
bitfld.long 0xC 30.--31. "GPIO127,Defines pin-muxing selection for GPIO127" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "GPIO126,Defines pin-muxing selection for GPIO126" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "GPIO125,Defines pin-muxing selection for GPIO125" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "GPIO124,Defines pin-muxing selection for GPIO124" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "GPIO123,Defines pin-muxing selection for GPIO123" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "GPIO122,Defines pin-muxing selection for GPIO122" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "GPIO121,Defines pin-muxing selection for GPIO121" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "GPIO120,Defines pin-muxing selection for GPIO120" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "GPIO119,Defines pin-muxing selection for GPIO119" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "GPIO118,Defines pin-muxing selection for GPIO118" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "GPIO117,Defines pin-muxing selection for GPIO117" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "GPIO116,Defines pin-muxing selection for GPIO116" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "GPIO115,Defines pin-muxing selection for GPIO115" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "GPIO114,Defines pin-muxing selection for GPIO114" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "GPIO113,Defines pin-muxing selection for GPIO113" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "GPIO112,Defines pin-muxing selection for GPIO112" "0,1,2,3"
|
|
line.long 0xE "GPDDIR,GPIO D Direction Register (GPIO96 to 127)"
|
|
bitfld.long 0xE 31. "GPIO127,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 30. "GPIO126,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 29. "GPIO125,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 28. "GPIO124,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 27. "GPIO123,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 26. "GPIO122,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 25. "GPIO121,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 24. "GPIO120,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 23. "GPIO119,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 22. "GPIO118,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "GPIO117,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 20. "GPIO116,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 19. "GPIO115,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 18. "GPIO114,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 17. "GPIO113,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 16. "GPIO112,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 15. "GPIO111,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 14. "GPIO110,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 13. "GPIO109,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 12. "GPIO108,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 11. "GPIO107,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 10. "GPIO106,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 9. "GPIO105,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 8. "GPIO104,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 7. "GPIO103,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 6. "GPIO102,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 5. "GPIO101,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 4. "GPIO100,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 3. "GPIO99,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 2. "GPIO98,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 1. "GPIO97,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 0. "GPIO96,Defines direction for this pin in GPIO mode" "0,1"
|
|
line.long 0x10 "GPDPUD,GPIO D Pull Up Disable Register (GPIO96 to 127)"
|
|
bitfld.long 0x10 31. "GPIO127,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO126,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO125,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO124,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO123,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO122,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO121,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO120,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO119,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO118,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "GPIO117,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO116,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 19. "GPIO115,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO114,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO113,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO112,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO111,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO110,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO109,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO108,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "GPIO107,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO106,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO105,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO104,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 7. "GPIO103,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO102,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO101,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO100,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO99,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO98,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GPIO97,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO96,Pull-Up Disable control for this pin" "0,1"
|
|
line.long 0x14 "GPDINV,GPIO D Input Polarity Invert Registers (GPIO96 to 127)"
|
|
bitfld.long 0x14 31. "GPIO127,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 30. "GPIO126,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 29. "GPIO125,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 28. "GPIO124,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 27. "GPIO123,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 26. "GPIO122,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 25. "GPIO121,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 24. "GPIO120,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 23. "GPIO119,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 22. "GPIO118,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "GPIO117,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 20. "GPIO116,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 19. "GPIO115,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 18. "GPIO114,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 17. "GPIO113,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 16. "GPIO112,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 15. "GPIO111,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 14. "GPIO110,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 13. "GPIO109,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 12. "GPIO108,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "GPIO107,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 10. "GPIO106,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 9. "GPIO105,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 8. "GPIO104,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 7. "GPIO103,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO102,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO101,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO100,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO99,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO98,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GPIO97,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO96,Input inversion control for this pin" "0,1"
|
|
line.long 0x16 "GPDODR,GPIO D Open Drain Output Register (GPIO96 to GPIO127)"
|
|
bitfld.long 0x16 31. "GPIO127,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 30. "GPIO126,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 29. "GPIO125,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 28. "GPIO124,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 27. "GPIO123,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 26. "GPIO122,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 25. "GPIO121,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 24. "GPIO120,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 23. "GPIO119,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 22. "GPIO118,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 21. "GPIO117,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 20. "GPIO116,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 19. "GPIO115,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 18. "GPIO114,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 17. "GPIO113,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 16. "GPIO112,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 15. "GPIO111,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 14. "GPIO110,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 13. "GPIO109,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 12. "GPIO108,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 11. "GPIO107,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 10. "GPIO106,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 9. "GPIO105,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 8. "GPIO104,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 7. "GPIO103,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 6. "GPIO102,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 5. "GPIO101,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 4. "GPIO100,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 3. "GPIO99,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 2. "GPIO98,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 1. "GPIO97,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 0. "GPIO96,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "GPDGMUX1,GPIO D Peripheral Group Mux (GPIO96 to 111)"
|
|
bitfld.long 0x0 30.--31. "GPIO111,Defines pin-muxing selection for GPIO111" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "GPIO110,Defines pin-muxing selection for GPIO110" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "GPIO109,Defines pin-muxing selection for GPIO109" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GPIO108,Defines pin-muxing selection for GPIO108" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GPIO107,Defines pin-muxing selection for GPIO107" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GPIO106,Defines pin-muxing selection for GPIO106" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GPIO105,Defines pin-muxing selection for GPIO105" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "GPIO104,Defines pin-muxing selection for GPIO104" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GPIO103,Defines pin-muxing selection for GPIO103" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GPIO102,Defines pin-muxing selection for GPIO102" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "GPIO101,Defines pin-muxing selection for GPIO101" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GPIO100,Defines pin-muxing selection for GPIO100" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "GPIO99,Defines pin-muxing selection for GPIO99" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GPIO98,Defines pin-muxing selection for GPIO98" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GPIO97,Defines pin-muxing selection for GPIO97" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GPIO96,Defines pin-muxing selection for GPIO96" "0,1,2,3"
|
|
line.long 0x2 "GPDGMUX2,GPIO D Peripheral Group Mux (GPIO112 to 127)"
|
|
bitfld.long 0x2 30.--31. "GPIO127,Defines pin-muxing selection for GPIO127" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "GPIO126,Defines pin-muxing selection for GPIO126" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "GPIO125,Defines pin-muxing selection for GPIO125" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GPIO124,Defines pin-muxing selection for GPIO124" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GPIO123,Defines pin-muxing selection for GPIO123" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GPIO122,Defines pin-muxing selection for GPIO122" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GPIO121,Defines pin-muxing selection for GPIO121" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "GPIO120,Defines pin-muxing selection for GPIO120" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GPIO119,Defines pin-muxing selection for GPIO119" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GPIO118,Defines pin-muxing selection for GPIO118" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 10.--11. "GPIO117,Defines pin-muxing selection for GPIO117" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPIO116,Defines pin-muxing selection for GPIO116" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "GPIO115,Defines pin-muxing selection for GPIO115" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPIO114,Defines pin-muxing selection for GPIO114" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GPIO113,Defines pin-muxing selection for GPIO113" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GPIO112,Defines pin-muxing selection for GPIO112" "0,1,2,3"
|
|
group.long 0xE8++0xF
|
|
line.long 0x0 "GPDCSEL1,GPIO D Core Select Register (GPIO96 to 103)"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GPIO103,GPIO103 Master CPU Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "GPIO102,GPIO102 Master CPU Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "GPIO101,GPIO101 Master CPU Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GPIO100,GPIO100 Master CPU Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "GPIO99,GPIO99 Master CPU Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GPIO98,GPIO98 Master CPU Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GPIO97,GPIO97 Master CPU Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GPIO96,GPIO96 Master CPU Select"
|
|
line.long 0x2 "GPDCSEL2,GPIO D Core Select Register (GPIO104 to 111)"
|
|
hexmask.long.byte 0x2 28.--31. 1. "GPIO111,GPIO111 Master CPU Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "GPIO110,GPIO110 Master CPU Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "GPIO109,GPIO109 Master CPU Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "GPIO108,GPIO108 Master CPU Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "GPIO107,GPIO107 Master CPU Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "GPIO106,GPIO106 Master CPU Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "GPIO105,GPIO105 Master CPU Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "GPIO104,GPIO104 Master CPU Select"
|
|
line.long 0x4 "GPDCSEL3,GPIO D Core Select Register (GPIO112 to 119)"
|
|
hexmask.long.byte 0x4 28.--31. 1. "GPIO119,GPIO119 Master CPU Select"
|
|
hexmask.long.byte 0x4 24.--27. 1. "GPIO118,GPIO118 Master CPU Select"
|
|
hexmask.long.byte 0x4 20.--23. 1. "GPIO117,GPIO117 Master CPU Select"
|
|
hexmask.long.byte 0x4 16.--19. 1. "GPIO116,GPIO116 Master CPU Select"
|
|
hexmask.long.byte 0x4 12.--15. 1. "GPIO115,GPIO115 Master CPU Select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "GPIO114,GPIO114 Master CPU Select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GPIO113,GPIO113 Master CPU Select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GPIO112,GPIO112 Master CPU Select"
|
|
line.long 0x6 "GPDCSEL4,GPIO D Core Select Register (GPIO120 to 127)"
|
|
hexmask.long.byte 0x6 28.--31. 1. "GPIO127,GPIO127 Master CPU Select"
|
|
hexmask.long.byte 0x6 24.--27. 1. "GPIO126,GPIO126 Master CPU Select"
|
|
hexmask.long.byte 0x6 20.--23. 1. "GPIO125,GPIO125 Master CPU Select"
|
|
hexmask.long.byte 0x6 16.--19. 1. "GPIO124,GPIO124 Master CPU Select"
|
|
hexmask.long.byte 0x6 12.--15. 1. "GPIO123,GPIO123 Master CPU Select"
|
|
hexmask.long.byte 0x6 8.--11. 1. "GPIO122,GPIO122 Master CPU Select"
|
|
hexmask.long.byte 0x6 4.--7. 1. "GPIO121,GPIO121 Master CPU Select"
|
|
hexmask.long.byte 0x6 0.--3. 1. "GPIO120,GPIO120 Master CPU Select"
|
|
group.long 0xFC++0x2B
|
|
line.long 0x0 "GPDLOCK,GPIO D Lock Configuration Register (GPIO96 to 127)"
|
|
bitfld.long 0x0 31. "GPIO127,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO126,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO125,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO124,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO123,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO122,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO121,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO120,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO119,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO118,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO117,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO116,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 19. "GPIO115,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO114,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO113,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO112,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO111,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO110,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO109,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO108,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO107,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO106,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO105,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO104,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 7. "GPIO103,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO102,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO101,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO100,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO99,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO98,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO97,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO96,Configuration Lock bit for this pin" "0,1"
|
|
line.long 0x2 "GPDCR,GPIO D Lock Commit Register (GPIO96 to 127)"
|
|
bitfld.long 0x2 31. "GPIO127,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 30. "GPIO126,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 29. "GPIO125,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 28. "GPIO124,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 27. "GPIO123,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 26. "GPIO122,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 25. "GPIO121,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 24. "GPIO120,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 23. "GPIO119,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 22. "GPIO118,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 21. "GPIO117,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 20. "GPIO116,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 19. "GPIO115,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 18. "GPIO114,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 17. "GPIO113,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 16. "GPIO112,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 15. "GPIO111,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 14. "GPIO110,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 13. "GPIO109,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 12. "GPIO108,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "GPIO107,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 10. "GPIO106,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 9. "GPIO105,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 8. "GPIO104,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 7. "GPIO103,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO102,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO101,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO100,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO99,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO98,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "GPIO97,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO96,Configuration lock commit bit for this pin" "0,1"
|
|
line.long 0x4 "GPECTRL,GPIO E Qualification Sampling Period Control (GPIO128 to 159)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO152 to GPIO159"
|
|
hexmask.long.byte 0x4 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO144 to GPIO151"
|
|
hexmask.long.byte 0x4 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO136 to GPIO143"
|
|
hexmask.long.byte 0x4 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO128 to GPIO135"
|
|
line.long 0x6 "GPEQSEL1,GPIO E Qualifier Select 1 Register (GPIO128 to 143)"
|
|
bitfld.long 0x6 30.--31. "GPIO143,Select input qualification type for GPIO143" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "GPIO142,Select input qualification type for GPIO142" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "GPIO141,Select input qualification type for GPIO141" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "GPIO140,Select input qualification type for GPIO140" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "GPIO139,Select input qualification type for GPIO139" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "GPIO138,Select input qualification type for GPIO138" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "GPIO137,Select input qualification type for GPIO137" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "GPIO136,Select input qualification type for GPIO136" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GPIO135,Select input qualification type for GPIO135" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GPIO134,Select input qualification type for GPIO134" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 10.--11. "GPIO133,Select input qualification type for GPIO133" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "GPIO132,Select input qualification type for GPIO132" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GPIO131,Select input qualification type for GPIO131" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GPIO130,Select input qualification type for GPIO130" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GPIO129,Select input qualification type for GPIO129" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GPIO128,Select input qualification type for GPIO128" "0,1,2,3"
|
|
line.long 0x8 "GPEQSEL2,GPIO E Qualifier Select 2 Register (GPIO144 to 159)"
|
|
bitfld.long 0x8 30.--31. "GPIO159,Select input qualification type for GPIO159" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "GPIO158,Select input qualification type for GPIO158" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "GPIO157,Select input qualification type for GPIO157" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "GPIO156,Select input qualification type for GPIO156" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "GPIO155,Select input qualification type for GPIO155" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "GPIO154,Select input qualification type for GPIO154" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "GPIO153,Select input qualification type for GPIO153" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "GPIO152,Select input qualification type for GPIO152" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "GPIO151,Select input qualification type for GPIO151" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "GPIO150,Select input qualification type for GPIO150" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GPIO149,Select input qualification type for GPIO149" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "GPIO148,Select input qualification type for GPIO148" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "GPIO147,Select input qualification type for GPIO147" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "GPIO146,Select input qualification type for GPIO146" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "GPIO145,Select input qualification type for GPIO145" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "GPIO144,Select input qualification type for GPIO144" "0,1,2,3"
|
|
line.long 0xA "GPEMUX1,GPIO E Mux 1 Register (GPIO128 to 143)"
|
|
bitfld.long 0xA 30.--31. "GPIO143,Defines pin-muxing selection for GPIO143" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "GPIO142,Defines pin-muxing selection for GPIO142" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "GPIO141,Defines pin-muxing selection for GPIO141" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "GPIO140,Defines pin-muxing selection for GPIO140" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "GPIO139,Defines pin-muxing selection for GPIO139" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "GPIO138,Defines pin-muxing selection for GPIO138" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "GPIO137,Defines pin-muxing selection for GPIO137" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "GPIO136,Defines pin-muxing selection for GPIO136" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GPIO135,Defines pin-muxing selection for GPIO135" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GPIO134,Defines pin-muxing selection for GPIO134" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 10.--11. "GPIO133,Defines pin-muxing selection for GPIO133" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "GPIO132,Defines pin-muxing selection for GPIO132" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GPIO131,Defines pin-muxing selection for GPIO131" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GPIO130,Defines pin-muxing selection for GPIO130" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GPIO129,Defines pin-muxing selection for GPIO129" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GPIO128,Defines pin-muxing selection for GPIO128" "0,1,2,3"
|
|
line.long 0xC "GPEMUX2,GPIO E Mux 2 Register (GPIO144 to 159)"
|
|
bitfld.long 0xC 30.--31. "GPIO159,Defines pin-muxing selection for GPIO159" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "GPIO158,Defines pin-muxing selection for GPIO158" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "GPIO157,Defines pin-muxing selection for GPIO157" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "GPIO156,Defines pin-muxing selection for GPIO156" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "GPIO155,Defines pin-muxing selection for GPIO155" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "GPIO154,Defines pin-muxing selection for GPIO154" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "GPIO153,Defines pin-muxing selection for GPIO153" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "GPIO152,Defines pin-muxing selection for GPIO152" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "GPIO151,Defines pin-muxing selection for GPIO151" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "GPIO150,Defines pin-muxing selection for GPIO150" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "GPIO149,Defines pin-muxing selection for GPIO149" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "GPIO148,Defines pin-muxing selection for GPIO148" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "GPIO147,Defines pin-muxing selection for GPIO147" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "GPIO146,Defines pin-muxing selection for GPIO146" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "GPIO145,Defines pin-muxing selection for GPIO145" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "GPIO144,Defines pin-muxing selection for GPIO144" "0,1,2,3"
|
|
line.long 0xE "GPEDIR,GPIO E Direction Register (GPIO128 to 159)"
|
|
bitfld.long 0xE 31. "GPIO159,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 30. "GPIO158,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 29. "GPIO157,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 28. "GPIO156,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 27. "GPIO155,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 26. "GPIO154,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 25. "GPIO153,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 24. "GPIO152,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 23. "GPIO151,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 22. "GPIO150,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 21. "GPIO149,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 20. "GPIO148,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 19. "GPIO147,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 18. "GPIO146,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 17. "GPIO145,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 16. "GPIO144,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 15. "GPIO143,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 14. "GPIO142,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 13. "GPIO141,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 12. "GPIO140,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 11. "GPIO139,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 10. "GPIO138,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 9. "GPIO137,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 8. "GPIO136,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 7. "GPIO135,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 6. "GPIO134,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 5. "GPIO133,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 4. "GPIO132,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 3. "GPIO131,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 2. "GPIO130,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0xE 1. "GPIO129,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 0. "GPIO128,Defines direction for this pin in GPIO mode" "0,1"
|
|
line.long 0x10 "GPEPUD,GPIO E Pull Up Disable Register (GPIO128 to 159)"
|
|
bitfld.long 0x10 31. "GPIO159,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO158,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO157,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO156,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO155,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO154,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO153,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO152,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO151,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO150,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "GPIO149,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO148,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 19. "GPIO147,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO146,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO145,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO144,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO143,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO142,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO141,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO140,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "GPIO139,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO138,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO137,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO136,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 7. "GPIO135,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO134,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO133,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO132,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO131,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO130,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GPIO129,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO128,Pull-Up Disable control for this pin" "0,1"
|
|
line.long 0x14 "GPEINV,GPIO E Input Polarity Invert Registers (GPIO128 to 159)"
|
|
bitfld.long 0x14 31. "GPIO159,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 30. "GPIO158,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 29. "GPIO157,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 28. "GPIO156,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 27. "GPIO155,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 26. "GPIO154,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 25. "GPIO153,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 24. "GPIO152,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 23. "GPIO151,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 22. "GPIO150,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "GPIO149,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 20. "GPIO148,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 19. "GPIO147,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 18. "GPIO146,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 17. "GPIO145,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 16. "GPIO144,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 15. "GPIO143,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 14. "GPIO142,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 13. "GPIO141,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 12. "GPIO140,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "GPIO139,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 10. "GPIO138,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 9. "GPIO137,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 8. "GPIO136,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 7. "GPIO135,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO134,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO133,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO132,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO131,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO130,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GPIO129,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO128,Input inversion control for this pin" "0,1"
|
|
line.long 0x16 "GPEODR,GPIO E Open Drain Output Register (GPIO128 to GPIO159)"
|
|
bitfld.long 0x16 31. "GPIO159,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 30. "GPIO158,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 29. "GPIO157,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 28. "GPIO156,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 27. "GPIO155,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 26. "GPIO154,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 25. "GPIO153,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 24. "GPIO152,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 23. "GPIO151,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 22. "GPIO150,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 21. "GPIO149,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 20. "GPIO148,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 19. "GPIO147,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 18. "GPIO146,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 17. "GPIO145,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 16. "GPIO144,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 15. "GPIO143,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 14. "GPIO142,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 13. "GPIO141,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 12. "GPIO140,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 11. "GPIO139,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 10. "GPIO138,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 9. "GPIO137,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 8. "GPIO136,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 7. "GPIO135,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 6. "GPIO134,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 5. "GPIO133,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 4. "GPIO132,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 3. "GPIO131,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 2. "GPIO130,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 1. "GPIO129,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 0. "GPIO128,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long 0x120++0x7
|
|
line.long 0x0 "GPEGMUX1,GPIO E Peripheral Group Mux (GPIO128 to 143)"
|
|
bitfld.long 0x0 30.--31. "GPIO143,Defines pin-muxing selection for GPIO143" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "GPIO142,Defines pin-muxing selection for GPIO142" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "GPIO141,Defines pin-muxing selection for GPIO141" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "GPIO140,Defines pin-muxing selection for GPIO140" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "GPIO139,Defines pin-muxing selection for GPIO139" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "GPIO138,Defines pin-muxing selection for GPIO138" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "GPIO137,Defines pin-muxing selection for GPIO137" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "GPIO136,Defines pin-muxing selection for GPIO136" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GPIO135,Defines pin-muxing selection for GPIO135" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GPIO134,Defines pin-muxing selection for GPIO134" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "GPIO133,Defines pin-muxing selection for GPIO133" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GPIO132,Defines pin-muxing selection for GPIO132" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "GPIO131,Defines pin-muxing selection for GPIO131" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GPIO130,Defines pin-muxing selection for GPIO130" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GPIO129,Defines pin-muxing selection for GPIO129" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GPIO128,Defines pin-muxing selection for GPIO128" "0,1,2,3"
|
|
line.long 0x2 "GPEGMUX2,GPIO E Peripheral Group Mux (GPIO144 to 159)"
|
|
bitfld.long 0x2 30.--31. "GPIO159,Defines pin-muxing selection for GPIO159" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "GPIO158,Defines pin-muxing selection for GPIO158" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "GPIO157,Defines pin-muxing selection for GPIO157" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "GPIO156,Defines pin-muxing selection for GPIO156" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "GPIO155,Defines pin-muxing selection for GPIO155" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "GPIO154,Defines pin-muxing selection for GPIO154" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "GPIO153,Defines pin-muxing selection for GPIO153" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "GPIO152,Defines pin-muxing selection for GPIO152" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "GPIO151,Defines pin-muxing selection for GPIO151" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "GPIO150,Defines pin-muxing selection for GPIO150" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 10.--11. "GPIO149,Defines pin-muxing selection for GPIO149" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "GPIO148,Defines pin-muxing selection for GPIO148" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "GPIO147,Defines pin-muxing selection for GPIO147" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "GPIO146,Defines pin-muxing selection for GPIO146" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "GPIO145,Defines pin-muxing selection for GPIO145" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "GPIO144,Defines pin-muxing selection for GPIO144" "0,1,2,3"
|
|
group.long 0x128++0xF
|
|
line.long 0x0 "GPECSEL1,GPIO E Core Select Register (GPIO128 to 135)"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GPIO135,GPIO135 Master CPU Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "GPIO134,GPIO134 Master CPU Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "GPIO133,GPIO133 Master CPU Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GPIO132,GPIO132 Master CPU Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "GPIO131,GPIO131 Master CPU Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GPIO130,GPIO130 Master CPU Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GPIO129,GPIO129 Master CPU Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GPIO128,GPIO128 Master CPU Select"
|
|
line.long 0x2 "GPECSEL2,GPIO E Core Select Register (GPIO136 to 143)"
|
|
hexmask.long.byte 0x2 28.--31. 1. "GPIO143,GPIO143 Master CPU Select"
|
|
hexmask.long.byte 0x2 24.--27. 1. "GPIO142,GPIO142 Master CPU Select"
|
|
hexmask.long.byte 0x2 20.--23. 1. "GPIO141,GPIO141 Master CPU Select"
|
|
hexmask.long.byte 0x2 16.--19. 1. "GPIO140,GPIO140 Master CPU Select"
|
|
hexmask.long.byte 0x2 12.--15. 1. "GPIO139,GPIO139 Master CPU Select"
|
|
hexmask.long.byte 0x2 8.--11. 1. "GPIO138,GPIO138 Master CPU Select"
|
|
hexmask.long.byte 0x2 4.--7. 1. "GPIO137,GPIO137 Master CPU Select"
|
|
hexmask.long.byte 0x2 0.--3. 1. "GPIO136,GPIO136 Master CPU Select"
|
|
line.long 0x4 "GPECSEL3,GPIO E Core Select Register (GPIO144 to 151)"
|
|
hexmask.long.byte 0x4 28.--31. 1. "GPIO151,GPIO151 Master CPU Select"
|
|
hexmask.long.byte 0x4 24.--27. 1. "GPIO150,GPIO150 Master CPU Select"
|
|
hexmask.long.byte 0x4 20.--23. 1. "GPIO149,GPIO149 Master CPU Select"
|
|
hexmask.long.byte 0x4 16.--19. 1. "GPIO148,GPIO148 Master CPU Select"
|
|
hexmask.long.byte 0x4 12.--15. 1. "GPIO147,GPIO147 Master CPU Select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "GPIO146,GPIO146 Master CPU Select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GPIO145,GPIO145 Master CPU Select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GPIO144,GPIO144 Master CPU Select"
|
|
line.long 0x6 "GPECSEL4,GPIO E Core Select Register (GPIO152 to 159)"
|
|
hexmask.long.byte 0x6 28.--31. 1. "GPIO159,GPIO159 Master CPU Select"
|
|
hexmask.long.byte 0x6 24.--27. 1. "GPIO158,GPIO158 Master CPU Select"
|
|
hexmask.long.byte 0x6 20.--23. 1. "GPIO157,GPIO157 Master CPU Select"
|
|
hexmask.long.byte 0x6 16.--19. 1. "GPIO156,GPIO156 Master CPU Select"
|
|
hexmask.long.byte 0x6 12.--15. 1. "GPIO155,GPIO155 Master CPU Select"
|
|
hexmask.long.byte 0x6 8.--11. 1. "GPIO154,GPIO154 Master CPU Select"
|
|
hexmask.long.byte 0x6 4.--7. 1. "GPIO153,GPIO153 Master CPU Select"
|
|
hexmask.long.byte 0x6 0.--3. 1. "GPIO152,GPIO152 Master CPU Select"
|
|
group.long 0x13C++0x23
|
|
line.long 0x0 "GPELOCK,GPIO E Lock Configuration Register (GPIO128 to 159)"
|
|
bitfld.long 0x0 31. "GPIO159,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO158,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO157,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO156,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO155,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO154,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO153,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO152,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO151,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO150,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "GPIO149,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO148,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 19. "GPIO147,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO146,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO145,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO144,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO143,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO142,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO141,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO140,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPIO139,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO138,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO137,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO136,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 7. "GPIO135,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO134,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO133,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO132,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO131,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO130,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO129,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO128,Configuration Lock bit for this pin" "0,1"
|
|
line.long 0x2 "GPECR,GPIO E Lock Commit Register (GPIO128 to 159)"
|
|
bitfld.long 0x2 31. "GPIO159,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 30. "GPIO158,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 29. "GPIO157,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 28. "GPIO156,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 27. "GPIO155,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 26. "GPIO154,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 25. "GPIO153,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 24. "GPIO152,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 23. "GPIO151,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 22. "GPIO150,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 21. "GPIO149,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 20. "GPIO148,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 19. "GPIO147,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 18. "GPIO146,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 17. "GPIO145,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 16. "GPIO144,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 15. "GPIO143,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 14. "GPIO142,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 13. "GPIO141,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 12. "GPIO140,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "GPIO139,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 10. "GPIO138,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 9. "GPIO137,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 8. "GPIO136,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 7. "GPIO135,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO134,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO133,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO132,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO131,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO130,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "GPIO129,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO128,Configuration lock commit bit for this pin" "0,1"
|
|
line.long 0x4 "GPFCTRL,GPIO F Qualification Sampling Period Control (GPIO160 to 168)"
|
|
hexmask.long.byte 0x4 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO168"
|
|
hexmask.long.byte 0x4 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO160 to GPIO167"
|
|
line.long 0x6 "GPFQSEL1,GPIO F Qualifier Select 1 Register (GPIO160 to 168)"
|
|
bitfld.long 0x6 16.--17. "GPIO168,Select input qualification type for GPIO168" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "GPIO167,Select input qualification type for GPIO167" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "GPIO166,Select input qualification type for GPIO166" "0,1,2,3"
|
|
bitfld.long 0x6 10.--11. "GPIO165,Select input qualification type for GPIO165" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "GPIO164,Select input qualification type for GPIO164" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "GPIO163,Select input qualification type for GPIO163" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "GPIO162,Select input qualification type for GPIO162" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "GPIO161,Select input qualification type for GPIO161" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "GPIO160,Select input qualification type for GPIO160" "0,1,2,3"
|
|
line.long 0xA "GPFMUX1,GPIO F Mux 1 Register (GPIO160 to 168)"
|
|
bitfld.long 0xA 16.--17. "GPIO168,Defines pin-muxing selection for GPIO168" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "GPIO167,Defines pin-muxing selection for GPIO167" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "GPIO166,Defines pin-muxing selection for GPIO166" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "GPIO165,Defines pin-muxing selection for GPIO165" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "GPIO164,Defines pin-muxing selection for GPIO164" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "GPIO163,Defines pin-muxing selection for GPIO163" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "GPIO162,Defines pin-muxing selection for GPIO162" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "GPIO161,Defines pin-muxing selection for GPIO161" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "GPIO160,Defines pin-muxing selection for GPIO160" "0,1,2,3"
|
|
line.long 0xE "GPFDIR,GPIO F Direction Register (GPIO160 to 168)"
|
|
bitfld.long 0xE 8. "GPIO168,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 7. "GPIO167,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 6. "GPIO166,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 5. "GPIO165,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 4. "GPIO164,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 3. "GPIO163,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 2. "GPIO162,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 1. "GPIO161,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0xE 0. "GPIO160,Defines direction for this pin in GPIO mode" "0,1"
|
|
line.long 0x10 "GPFPUD,GPIO F Pull Up Disable Register (GPIO160 to 168)"
|
|
bitfld.long 0x10 8. "GPIO168,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 7. "GPIO167,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO166,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO165,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO164,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO163,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO162,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 1. "GPIO161,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO160,Pull-Up Disable control for this pin" "0,1"
|
|
line.long 0x14 "GPFINV,GPIO F Input Polarity Invert Registers (GPIO160 to 168)"
|
|
bitfld.long 0x14 8. "GPIO168,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 7. "GPIO167,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO166,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO165,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO164,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO163,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO162,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 1. "GPIO161,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO160,Input inversion control for this pin" "0,1"
|
|
line.long 0x16 "GPFODR,GPIO F Open Drain Output Register (GPIO160 to GPIO168)"
|
|
bitfld.long 0x16 8. "GPIO168,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 7. "GPIO167,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 6. "GPIO166,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 5. "GPIO165,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 4. "GPIO164,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 3. "GPIO163,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 2. "GPIO162,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 1. "GPIO161,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x16 0. "GPIO160,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "GPFGMUX1,GPIO F Peripheral Group Mux (GPIO160 to 168)"
|
|
bitfld.long 0x0 16.--17. "GPIO168,Defines pin-muxing selection for GPIO168" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "GPIO167,Defines pin-muxing selection for GPIO167" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "GPIO166,Defines pin-muxing selection for GPIO166" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "GPIO165,Defines pin-muxing selection for GPIO165" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "GPIO164,Defines pin-muxing selection for GPIO164" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "GPIO163,Defines pin-muxing selection for GPIO163" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "GPIO162,Defines pin-muxing selection for GPIO162" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "GPIO161,Defines pin-muxing selection for GPIO161" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "GPIO160,Defines pin-muxing selection for GPIO160" "0,1,2,3"
|
|
group.long 0x168++0x7
|
|
line.long 0x0 "GPFCSEL1,GPIO F Core Select Register (GPIO160 to 167)"
|
|
hexmask.long.byte 0x0 28.--31. 1. "GPIO167,GPIO167 Master CPU Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "GPIO166,GPIO166 Master CPU Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "GPIO165,GPIO165 Master CPU Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GPIO164,GPIO164 Master CPU Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "GPIO163,GPIO163 Master CPU Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GPIO162,GPIO162 Master CPU Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GPIO161,GPIO161 Master CPU Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GPIO160,GPIO160 Master CPU Select"
|
|
line.long 0x2 "GPFCSEL2,GPIO F Core Select Register (GPIO168)"
|
|
hexmask.long.byte 0x2 0.--3. 1. "GPIO168,GPIO168 Master CPU Select"
|
|
group.long 0x17C++0x7
|
|
line.long 0x0 "GPFLOCK,GPIO F Lock Configuration Register (GPIO160 to 168)"
|
|
bitfld.long 0x0 8. "GPIO168,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 7. "GPIO167,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO166,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO165,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO164,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO163,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO162,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 1. "GPIO161,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO160,Configuration Lock bit for this pin" "0,1"
|
|
line.long 0x2 "GPFCR,GPIO F Lock Commit Register (GPIO160 to 168)"
|
|
bitfld.long 0x2 8. "GPIO168,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 7. "GPIO167,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO166,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO165,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO164,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO163,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO162,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 1. "GPIO161,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO160,Configuration lock commit bit for this pin" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "GPIODATA"
|
|
base d:0x7F00
|
|
group.long 0x0++0x5F
|
|
line.long 0x0 "GPADAT,GPIO A Data Register (GPIO0 to 31)"
|
|
bitfld.long 0x0 31. "GPIO31,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO30,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO29,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO28,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO27,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO26,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO25,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO24,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO23,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO22,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 21. "GPIO21,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO20,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GPIO19,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO18,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO17,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO16,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO15,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO14,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO13,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO12,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 11. "GPIO11,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO10,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO9,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO8,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO7,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO6,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO5,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO4,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO3,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO2,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 1. "GPIO1,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO0,Data Register for this pin" "0,1"
|
|
line.long 0x2 "GPASET,GPIO A Data Set Register (GPIO0 to 31)"
|
|
bitfld.long 0x2 31. "GPIO31,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 30. "GPIO30,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 29. "GPIO29,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 28. "GPIO28,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 27. "GPIO27,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 26. "GPIO26,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 25. "GPIO25,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 24. "GPIO24,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 23. "GPIO23,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 22. "GPIO22,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 21. "GPIO21,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 20. "GPIO20,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 19. "GPIO19,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 18. "GPIO18,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 17. "GPIO17,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 16. "GPIO16,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 15. "GPIO15,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 14. "GPIO14,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 13. "GPIO13,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 12. "GPIO12,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 11. "GPIO11,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 10. "GPIO10,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 9. "GPIO9,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 8. "GPIO8,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2 7. "GPIO7,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 6. "GPIO6,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 5. "GPIO5,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 4. "GPIO4,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 3. "GPIO3,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 2. "GPIO2,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 1. "GPIO1,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2 0. "GPIO0,Output Set bit for this pin" "0,1"
|
|
line.long 0x4 "GPACLEAR,GPIO A Data Clear Register (GPIO0 to 31)"
|
|
bitfld.long 0x4 31. "GPIO31,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 30. "GPIO30,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 29. "GPIO29,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 28. "GPIO28,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 27. "GPIO27,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 26. "GPIO26,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 25. "GPIO25,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 24. "GPIO24,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 23. "GPIO23,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 22. "GPIO22,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 21. "GPIO21,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 20. "GPIO20,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "GPIO19,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 18. "GPIO18,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 17. "GPIO17,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 16. "GPIO16,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 15. "GPIO15,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 14. "GPIO14,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 13. "GPIO13,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 12. "GPIO12,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 11. "GPIO11,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 10. "GPIO10,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 9. "GPIO9,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 8. "GPIO8,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO7,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 6. "GPIO6,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 5. "GPIO5,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 4. "GPIO4,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 3. "GPIO3,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 2. "GPIO2,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 1. "GPIO1,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x4 0. "GPIO0,Output Clear bit for this pin" "0,1"
|
|
line.long 0x6 "GPATOGGLE,GPIO A Data Toggle Register (GPIO0 to 31)"
|
|
bitfld.long 0x6 31. "GPIO31,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 30. "GPIO30,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 29. "GPIO29,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 28. "GPIO28,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 27. "GPIO27,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 26. "GPIO26,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 25. "GPIO25,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 24. "GPIO24,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 23. "GPIO23,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 22. "GPIO22,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 21. "GPIO21,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 20. "GPIO20,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x6 19. "GPIO19,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 18. "GPIO18,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 17. "GPIO17,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 16. "GPIO16,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 15. "GPIO15,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 14. "GPIO14,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 13. "GPIO13,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 12. "GPIO12,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 11. "GPIO11,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 10. "GPIO10,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 9. "GPIO9,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 8. "GPIO8,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x6 7. "GPIO7,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 6. "GPIO6,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 5. "GPIO5,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 4. "GPIO4,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 3. "GPIO3,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 2. "GPIO2,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 1. "GPIO1,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x6 0. "GPIO0,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x8 "GPBDAT,GPIO B Data Register (GPIO32 to 63)"
|
|
bitfld.long 0x8 31. "GPIO63,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 30. "GPIO62,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 29. "GPIO61,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 28. "GPIO60,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 27. "GPIO59,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 26. "GPIO58,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 25. "GPIO57,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 24. "GPIO56,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 23. "GPIO55,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 22. "GPIO54,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 21. "GPIO53,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 20. "GPIO52,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "GPIO51,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 18. "GPIO50,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 17. "GPIO49,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 16. "GPIO48,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 15. "GPIO47,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 14. "GPIO46,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 13. "GPIO45,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 12. "GPIO44,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 11. "GPIO43,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 10. "GPIO42,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 9. "GPIO41,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 8. "GPIO40,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "GPIO39,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 6. "GPIO38,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 5. "GPIO37,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 4. "GPIO36,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 3. "GPIO35,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 2. "GPIO34,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 1. "GPIO33,Data Register for this pin" "0,1"
|
|
bitfld.long 0x8 0. "GPIO32,Data Register for this pin" "0,1"
|
|
line.long 0xA "GPBSET,GPIO B Data Set Register (GPIO32 to 63)"
|
|
bitfld.long 0xA 31. "GPIO63,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 30. "GPIO62,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 29. "GPIO61,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 28. "GPIO60,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 27. "GPIO59,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 26. "GPIO58,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 25. "GPIO57,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 24. "GPIO56,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 23. "GPIO55,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 22. "GPIO54,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 21. "GPIO53,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 20. "GPIO52,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xA 19. "GPIO51,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 18. "GPIO50,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 17. "GPIO49,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 16. "GPIO48,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 15. "GPIO47,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 14. "GPIO46,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 13. "GPIO45,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 12. "GPIO44,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 11. "GPIO43,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 10. "GPIO42,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 9. "GPIO41,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 8. "GPIO40,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xA 7. "GPIO39,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 6. "GPIO38,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 5. "GPIO37,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 4. "GPIO36,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 3. "GPIO35,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 2. "GPIO34,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 1. "GPIO33,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0xA 0. "GPIO32,Output Set bit for this pin" "0,1"
|
|
line.long 0xC "GPBCLEAR,GPIO B Data Clear Register (GPIO32 to 63)"
|
|
bitfld.long 0xC 31. "GPIO63,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 30. "GPIO62,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 29. "GPIO61,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 28. "GPIO60,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 27. "GPIO59,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 26. "GPIO58,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 25. "GPIO57,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 24. "GPIO56,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 23. "GPIO55,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 22. "GPIO54,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 21. "GPIO53,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 20. "GPIO52,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "GPIO51,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 18. "GPIO50,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 17. "GPIO49,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 16. "GPIO48,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 15. "GPIO47,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 14. "GPIO46,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 13. "GPIO45,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 12. "GPIO44,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 11. "GPIO43,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 10. "GPIO42,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 9. "GPIO41,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 8. "GPIO40,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "GPIO39,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 6. "GPIO38,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 5. "GPIO37,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 4. "GPIO36,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 3. "GPIO35,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 2. "GPIO34,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 1. "GPIO33,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0xC 0. "GPIO32,Output Clear bit for this pin" "0,1"
|
|
line.long 0xE "GPBTOGGLE,GPIO B Data Toggle Register (GPIO32 to 63)"
|
|
bitfld.long 0xE 31. "GPIO63,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 30. "GPIO62,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 29. "GPIO61,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 28. "GPIO60,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 27. "GPIO59,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 26. "GPIO58,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 25. "GPIO57,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 24. "GPIO56,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 23. "GPIO55,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 22. "GPIO54,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 21. "GPIO53,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 20. "GPIO52,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xE 19. "GPIO51,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 18. "GPIO50,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 17. "GPIO49,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 16. "GPIO48,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 15. "GPIO47,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 14. "GPIO46,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 13. "GPIO45,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 12. "GPIO44,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 11. "GPIO43,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 10. "GPIO42,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 9. "GPIO41,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 8. "GPIO40,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xE 7. "GPIO39,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 6. "GPIO38,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 5. "GPIO37,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 4. "GPIO36,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 3. "GPIO35,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 2. "GPIO34,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 1. "GPIO33,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xE 0. "GPIO32,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x10 "GPCDAT,GPIO C Data Register (GPIO64 to 95)"
|
|
bitfld.long 0x10 31. "GPIO95,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO94,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO93,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO92,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO91,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO90,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO89,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO88,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO87,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO86,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 21. "GPIO85,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO84,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "GPIO83,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO82,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO81,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO80,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO79,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO78,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO77,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO76,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 11. "GPIO75,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO74,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO73,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO72,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "GPIO71,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO70,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO69,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO68,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO67,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO66,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 1. "GPIO65,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO64,Data Register for this pin" "0,1"
|
|
line.long 0x12 "GPCSET,GPIO C Data Set Register (GPIO64 to 95)"
|
|
bitfld.long 0x12 31. "GPIO95,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 30. "GPIO94,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 29. "GPIO93,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 28. "GPIO92,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 27. "GPIO91,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 26. "GPIO90,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 25. "GPIO89,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 24. "GPIO88,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 23. "GPIO87,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 22. "GPIO86,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 21. "GPIO85,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 20. "GPIO84,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x12 19. "GPIO83,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 18. "GPIO82,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 17. "GPIO81,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 16. "GPIO80,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 15. "GPIO79,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 14. "GPIO78,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 13. "GPIO77,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 12. "GPIO76,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 11. "GPIO75,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 10. "GPIO74,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 9. "GPIO73,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 8. "GPIO72,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x12 7. "GPIO71,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 6. "GPIO70,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 5. "GPIO69,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 4. "GPIO68,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 3. "GPIO67,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 2. "GPIO66,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 1. "GPIO65,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x12 0. "GPIO64,Output Set bit for this pin" "0,1"
|
|
line.long 0x14 "GPCCLEAR,GPIO C Data Clear Register (GPIO64 to 95)"
|
|
bitfld.long 0x14 31. "GPIO95,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 30. "GPIO94,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 29. "GPIO93,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 28. "GPIO92,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 27. "GPIO91,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 26. "GPIO90,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 25. "GPIO89,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 24. "GPIO88,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 23. "GPIO87,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 22. "GPIO86,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 21. "GPIO85,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 20. "GPIO84,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "GPIO83,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 18. "GPIO82,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 17. "GPIO81,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 16. "GPIO80,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 15. "GPIO79,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 14. "GPIO78,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 13. "GPIO77,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 12. "GPIO76,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 11. "GPIO75,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 10. "GPIO74,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 9. "GPIO73,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 8. "GPIO72,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "GPIO71,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO70,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO69,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO68,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO67,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO66,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 1. "GPIO65,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO64,Output Clear bit for this pin" "0,1"
|
|
line.long 0x16 "GPCTOGGLE,GPIO C Data Toggle Register (GPIO64 to 95)"
|
|
bitfld.long 0x16 31. "GPIO95,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 30. "GPIO94,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 29. "GPIO93,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 28. "GPIO92,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 27. "GPIO91,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 26. "GPIO90,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 25. "GPIO89,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 24. "GPIO88,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 23. "GPIO87,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 22. "GPIO86,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 21. "GPIO85,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 20. "GPIO84,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 19. "GPIO83,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 18. "GPIO82,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 17. "GPIO81,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 16. "GPIO80,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 15. "GPIO79,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 14. "GPIO78,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 13. "GPIO77,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 12. "GPIO76,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 11. "GPIO75,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 10. "GPIO74,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 9. "GPIO73,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 8. "GPIO72,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x16 7. "GPIO71,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 6. "GPIO70,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 5. "GPIO69,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 4. "GPIO68,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 3. "GPIO67,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 2. "GPIO66,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 1. "GPIO65,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x16 0. "GPIO64,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x18 "GPDDAT,GPIO D Data Register (GPIO96 to 127)"
|
|
bitfld.long 0x18 31. "GPIO127,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 30. "GPIO126,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 29. "GPIO125,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 28. "GPIO124,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 27. "GPIO123,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 26. "GPIO122,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 25. "GPIO121,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 24. "GPIO120,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 23. "GPIO119,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 22. "GPIO118,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 21. "GPIO117,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 20. "GPIO116,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "GPIO115,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 18. "GPIO114,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 17. "GPIO113,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 16. "GPIO112,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 15. "GPIO111,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 14. "GPIO110,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 13. "GPIO109,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 12. "GPIO108,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 11. "GPIO107,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 10. "GPIO106,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 9. "GPIO105,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 8. "GPIO104,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "GPIO103,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 6. "GPIO102,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 5. "GPIO101,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 4. "GPIO100,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 3. "GPIO99,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 2. "GPIO98,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 1. "GPIO97,Data Register for this pin" "0,1"
|
|
bitfld.long 0x18 0. "GPIO96,Data Register for this pin" "0,1"
|
|
line.long 0x1A "GPDSET,GPIO D Data Set Register (GPIO96 to 127)"
|
|
bitfld.long 0x1A 31. "GPIO127,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 30. "GPIO126,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 29. "GPIO125,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 28. "GPIO124,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 27. "GPIO123,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 26. "GPIO122,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 25. "GPIO121,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 24. "GPIO120,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 23. "GPIO119,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 22. "GPIO118,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 21. "GPIO117,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 20. "GPIO116,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1A 19. "GPIO115,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 18. "GPIO114,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 17. "GPIO113,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 16. "GPIO112,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 15. "GPIO111,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 14. "GPIO110,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 13. "GPIO109,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 12. "GPIO108,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 11. "GPIO107,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 10. "GPIO106,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 9. "GPIO105,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 8. "GPIO104,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1A 7. "GPIO103,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 6. "GPIO102,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 5. "GPIO101,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 4. "GPIO100,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 3. "GPIO99,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 2. "GPIO98,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 1. "GPIO97,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x1A 0. "GPIO96,Output Set bit for this pin" "0,1"
|
|
line.long 0x1C "GPDCLEAR,GPIO D Data Clear Register (GPIO96 to 127)"
|
|
bitfld.long 0x1C 31. "GPIO127,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 30. "GPIO126,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 29. "GPIO125,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 28. "GPIO124,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 27. "GPIO123,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 26. "GPIO122,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 25. "GPIO121,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 24. "GPIO120,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 23. "GPIO119,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 22. "GPIO118,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 21. "GPIO117,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 20. "GPIO116,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 19. "GPIO115,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 18. "GPIO114,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 17. "GPIO113,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 16. "GPIO112,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 15. "GPIO111,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 14. "GPIO110,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 13. "GPIO109,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 12. "GPIO108,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 11. "GPIO107,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 10. "GPIO106,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 9. "GPIO105,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 8. "GPIO104,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "GPIO103,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 6. "GPIO102,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 5. "GPIO101,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 4. "GPIO100,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 3. "GPIO99,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 2. "GPIO98,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 1. "GPIO97,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x1C 0. "GPIO96,Output Clear bit for this pin" "0,1"
|
|
line.long 0x1E "GPDTOGGLE,GPIO D Data Toggle Register (GPIO96 to 127)"
|
|
bitfld.long 0x1E 31. "GPIO127,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 30. "GPIO126,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 29. "GPIO125,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 28. "GPIO124,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 27. "GPIO123,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 26. "GPIO122,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 25. "GPIO121,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 24. "GPIO120,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 23. "GPIO119,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 22. "GPIO118,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 21. "GPIO117,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 20. "GPIO116,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1E 19. "GPIO115,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 18. "GPIO114,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 17. "GPIO113,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 16. "GPIO112,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 15. "GPIO111,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 14. "GPIO110,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 13. "GPIO109,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 12. "GPIO108,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 11. "GPIO107,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 10. "GPIO106,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 9. "GPIO105,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 8. "GPIO104,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1E 7. "GPIO103,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 6. "GPIO102,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 5. "GPIO101,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 4. "GPIO100,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 3. "GPIO99,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 2. "GPIO98,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 1. "GPIO97,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1E 0. "GPIO96,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x20 "GPEDAT,GPIO E Data Register (GPIO128 to 159)"
|
|
bitfld.long 0x20 31. "GPIO159,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 30. "GPIO158,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 29. "GPIO157,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 28. "GPIO156,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 27. "GPIO155,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 26. "GPIO154,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 25. "GPIO153,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 24. "GPIO152,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 23. "GPIO151,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 22. "GPIO150,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 21. "GPIO149,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 20. "GPIO148,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x20 19. "GPIO147,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 18. "GPIO146,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 17. "GPIO145,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 16. "GPIO144,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 15. "GPIO143,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 14. "GPIO142,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 13. "GPIO141,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 12. "GPIO140,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 11. "GPIO139,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 10. "GPIO138,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 9. "GPIO137,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 8. "GPIO136,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "GPIO135,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 6. "GPIO134,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 5. "GPIO133,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 4. "GPIO132,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 3. "GPIO131,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 2. "GPIO130,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 1. "GPIO129,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 0. "GPIO128,Data Register for this pin" "0,1"
|
|
line.long 0x22 "GPESET,GPIO E Data Set Register (GPIO128 to 159)"
|
|
bitfld.long 0x22 31. "GPIO159,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 30. "GPIO158,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 29. "GPIO157,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 28. "GPIO156,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 27. "GPIO155,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 26. "GPIO154,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 25. "GPIO153,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 24. "GPIO152,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 23. "GPIO151,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 22. "GPIO150,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 21. "GPIO149,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 20. "GPIO148,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x22 19. "GPIO147,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 18. "GPIO146,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 17. "GPIO145,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 16. "GPIO144,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 15. "GPIO143,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 14. "GPIO142,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 13. "GPIO141,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 12. "GPIO140,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 11. "GPIO139,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 10. "GPIO138,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 9. "GPIO137,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 8. "GPIO136,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x22 7. "GPIO135,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 6. "GPIO134,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 5. "GPIO133,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 4. "GPIO132,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 3. "GPIO131,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 2. "GPIO130,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 1. "GPIO129,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x22 0. "GPIO128,Output Set bit for this pin" "0,1"
|
|
line.long 0x24 "GPECLEAR,GPIO E Data Clear Register (GPIO128 to 159)"
|
|
bitfld.long 0x24 31. "GPIO159,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 30. "GPIO158,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 29. "GPIO157,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 28. "GPIO156,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 27. "GPIO155,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 26. "GPIO154,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 25. "GPIO153,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 24. "GPIO152,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 23. "GPIO151,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 22. "GPIO150,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 21. "GPIO149,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 20. "GPIO148,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x24 19. "GPIO147,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 18. "GPIO146,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 17. "GPIO145,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 16. "GPIO144,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 15. "GPIO143,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 14. "GPIO142,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 13. "GPIO141,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 12. "GPIO140,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 11. "GPIO139,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 10. "GPIO138,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 9. "GPIO137,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 8. "GPIO136,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "GPIO135,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 6. "GPIO134,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 5. "GPIO133,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 4. "GPIO132,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 3. "GPIO131,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 2. "GPIO130,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 1. "GPIO129,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x24 0. "GPIO128,Output Clear bit for this pin" "0,1"
|
|
line.long 0x26 "GPETOGGLE,GPIO E Data Toggle Register (GPIO128 to 159)"
|
|
bitfld.long 0x26 31. "GPIO159,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 30. "GPIO158,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 29. "GPIO157,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 28. "GPIO156,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 27. "GPIO155,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 26. "GPIO154,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 25. "GPIO153,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 24. "GPIO152,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 23. "GPIO151,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 22. "GPIO150,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 21. "GPIO149,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 20. "GPIO148,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x26 19. "GPIO147,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 18. "GPIO146,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 17. "GPIO145,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 16. "GPIO144,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 15. "GPIO143,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 14. "GPIO142,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 13. "GPIO141,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 12. "GPIO140,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 11. "GPIO139,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 10. "GPIO138,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 9. "GPIO137,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 8. "GPIO136,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x26 7. "GPIO135,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 6. "GPIO134,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 5. "GPIO133,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 4. "GPIO132,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 3. "GPIO131,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 2. "GPIO130,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 1. "GPIO129,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x26 0. "GPIO128,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x28 "GPFDAT,GPIO F Data Register (GPIO160 to 168)"
|
|
bitfld.long 0x28 8. "GPIO168,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 7. "GPIO167,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 6. "GPIO166,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 5. "GPIO165,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 4. "GPIO164,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 3. "GPIO163,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 2. "GPIO162,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 1. "GPIO161,Data Register for this pin" "0,1"
|
|
bitfld.long 0x28 0. "GPIO160,Data Register for this pin" "0,1"
|
|
line.long 0x2A "GPFSET,GPIO F Data Set Register (GPIO160 to 168)"
|
|
bitfld.long 0x2A 8. "GPIO168,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 7. "GPIO167,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 6. "GPIO166,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 5. "GPIO165,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 4. "GPIO164,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 3. "GPIO163,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 2. "GPIO162,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 1. "GPIO161,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x2A 0. "GPIO160,Output Set bit for this pin" "0,1"
|
|
line.long 0x2C "GPFCLEAR,GPIO F Data Clear Register (GPIO160 to 168)"
|
|
bitfld.long 0x2C 8. "GPIO168,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 7. "GPIO167,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 6. "GPIO166,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 5. "GPIO165,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 4. "GPIO164,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 3. "GPIO163,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 2. "GPIO162,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 1. "GPIO161,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x2C 0. "GPIO160,Output Clear bit for this pin" "0,1"
|
|
line.long 0x2E "GPFTOGGLE,GPIO F Data Toggle Register (GPIO160 to 168)"
|
|
bitfld.long 0x2E 8. "GPIO168,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 7. "GPIO167,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 6. "GPIO166,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 5. "GPIO165,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 4. "GPIO164,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 3. "GPIO163,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 2. "GPIO162,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 1. "GPIO161,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2E 0. "GPIO160,Output Toggle bit for this pin" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "GPIODATAREAD"
|
|
base d:0x7F80
|
|
rgroup.long 0x0++0x17
|
|
line.long 0x0 "GPADAT_R,GPIO A Data Read Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,GPADAT register value"
|
|
line.long 0x2 "GPBDAT_R,GPIO B Data Read Register"
|
|
hexmask.long 0x2 0.--31. 1. "DATA,GPBDAT register value"
|
|
line.long 0x4 "GPCDAT_R,GPIO C Data Read Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,GPCDAT register value"
|
|
line.long 0x6 "GPDDAT_R,GPIO D Data Read Register"
|
|
hexmask.long 0x6 0.--31. 1. "DATA,GPDDAT register value"
|
|
line.long 0x8 "GPEDAT_R,GPIO E Data Read Register"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,GPEDAT register value"
|
|
line.long 0xA "GPFDAT_R,GPIO F Data Read Register"
|
|
hexmask.long 0xA 0.--31. 1. "DATA,GPFDAT register value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "GPIODATA"
|
|
base d:0x40083000
|
|
group.long 0x0++0x5F
|
|
line.long 0x0 "GPADAT,GPIO A Data Register (GPIO0 to 31)"
|
|
bitfld.long 0x0 31. "GPIO31,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 30. "GPIO30,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 29. "GPIO29,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 28. "GPIO28,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 27. "GPIO27,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 26. "GPIO26,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 25. "GPIO25,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 24. "GPIO24,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 23. "GPIO23,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 22. "GPIO22,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 21. "GPIO21,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 20. "GPIO20,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GPIO19,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 18. "GPIO18,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 17. "GPIO17,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 16. "GPIO16,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 15. "GPIO15,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 14. "GPIO14,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 13. "GPIO13,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 12. "GPIO12,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 11. "GPIO11,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 10. "GPIO10,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 9. "GPIO9,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 8. "GPIO8,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPIO7,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 6. "GPIO6,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 5. "GPIO5,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 4. "GPIO4,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 3. "GPIO3,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 2. "GPIO2,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 1. "GPIO1,Data Register for this pin" "0,1"
|
|
bitfld.long 0x0 0. "GPIO0,Data Register for this pin" "0,1"
|
|
line.long 0x4 "GPASET,GPIO A Data Set Register (GPIO0 to 31)"
|
|
bitfld.long 0x4 31. "GPIO31,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 30. "GPIO30,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 29. "GPIO29,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 28. "GPIO28,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 27. "GPIO27,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 26. "GPIO26,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 25. "GPIO25,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 24. "GPIO24,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 23. "GPIO23,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 22. "GPIO22,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 21. "GPIO21,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 20. "GPIO20,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "GPIO19,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 18. "GPIO18,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 17. "GPIO17,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 16. "GPIO16,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 15. "GPIO15,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 14. "GPIO14,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 13. "GPIO13,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 12. "GPIO12,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 11. "GPIO11,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 10. "GPIO10,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 9. "GPIO9,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 8. "GPIO8,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO7,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 6. "GPIO6,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 5. "GPIO5,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 4. "GPIO4,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 3. "GPIO3,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 2. "GPIO2,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 1. "GPIO1,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x4 0. "GPIO0,Output Set bit for this pin" "0,1"
|
|
line.long 0x8 "GPACLEAR,GPIO A Data Clear Register (GPIO0 to 31)"
|
|
bitfld.long 0x8 31. "GPIO31,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 30. "GPIO30,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 29. "GPIO29,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 28. "GPIO28,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 27. "GPIO27,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 26. "GPIO26,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 25. "GPIO25,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 24. "GPIO24,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 23. "GPIO23,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 22. "GPIO22,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 21. "GPIO21,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 20. "GPIO20,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "GPIO19,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 18. "GPIO18,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 17. "GPIO17,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 16. "GPIO16,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 15. "GPIO15,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 14. "GPIO14,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 13. "GPIO13,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 12. "GPIO12,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 11. "GPIO11,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 10. "GPIO10,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 9. "GPIO9,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 8. "GPIO8,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "GPIO7,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 6. "GPIO6,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 5. "GPIO5,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 4. "GPIO4,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 3. "GPIO3,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 2. "GPIO2,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 1. "GPIO1,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x8 0. "GPIO0,Output Clear bit for this pin" "0,1"
|
|
line.long 0xC "GPATOGGLE,GPIO A Data Toggle Register (GPIO0 to 31)"
|
|
bitfld.long 0xC 31. "GPIO31,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 30. "GPIO30,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 29. "GPIO29,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 28. "GPIO28,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 27. "GPIO27,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 26. "GPIO26,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 25. "GPIO25,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 24. "GPIO24,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 23. "GPIO23,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 22. "GPIO22,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 21. "GPIO21,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 20. "GPIO20,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "GPIO19,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 18. "GPIO18,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 17. "GPIO17,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 16. "GPIO16,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 15. "GPIO15,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 14. "GPIO14,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 13. "GPIO13,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 12. "GPIO12,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 11. "GPIO11,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 10. "GPIO10,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 9. "GPIO9,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 8. "GPIO8,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "GPIO7,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 6. "GPIO6,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 5. "GPIO5,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 4. "GPIO4,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 3. "GPIO3,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 2. "GPIO2,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 1. "GPIO1,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0xC 0. "GPIO0,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x10 "GPBDAT,GPIO B Data Register (GPIO32 to 63)"
|
|
bitfld.long 0x10 31. "GPIO63,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 30. "GPIO62,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 29. "GPIO61,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 28. "GPIO60,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 27. "GPIO59,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 26. "GPIO58,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 25. "GPIO57,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 24. "GPIO56,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 23. "GPIO55,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 22. "GPIO54,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 21. "GPIO53,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 20. "GPIO52,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "GPIO51,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 18. "GPIO50,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 17. "GPIO49,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 16. "GPIO48,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 15. "GPIO47,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 14. "GPIO46,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 13. "GPIO45,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 12. "GPIO44,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 11. "GPIO43,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 10. "GPIO42,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 9. "GPIO41,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 8. "GPIO40,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "GPIO39,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 6. "GPIO38,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 5. "GPIO37,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 4. "GPIO36,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 3. "GPIO35,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 2. "GPIO34,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 1. "GPIO33,Data Register for this pin" "0,1"
|
|
bitfld.long 0x10 0. "GPIO32,Data Register for this pin" "0,1"
|
|
line.long 0x14 "GPBSET,GPIO B Data Set Register (GPIO32 to 63)"
|
|
bitfld.long 0x14 31. "GPIO63,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 30. "GPIO62,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 29. "GPIO61,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 28. "GPIO60,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 27. "GPIO59,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 26. "GPIO58,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 25. "GPIO57,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 24. "GPIO56,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 23. "GPIO55,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 22. "GPIO54,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 21. "GPIO53,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 20. "GPIO52,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "GPIO51,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 18. "GPIO50,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 17. "GPIO49,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 16. "GPIO48,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 15. "GPIO47,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 14. "GPIO46,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 13. "GPIO45,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 12. "GPIO44,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 11. "GPIO43,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 10. "GPIO42,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 9. "GPIO41,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 8. "GPIO40,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "GPIO39,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 6. "GPIO38,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 5. "GPIO37,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 4. "GPIO36,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 3. "GPIO35,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 2. "GPIO34,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 1. "GPIO33,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x14 0. "GPIO32,Output Set bit for this pin" "0,1"
|
|
line.long 0x18 "GPBCLEAR,GPIO B Data Clear Register (GPIO32 to 63)"
|
|
bitfld.long 0x18 31. "GPIO63,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 30. "GPIO62,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 29. "GPIO61,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 28. "GPIO60,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 27. "GPIO59,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 26. "GPIO58,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 25. "GPIO57,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 24. "GPIO56,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 23. "GPIO55,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 22. "GPIO54,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 21. "GPIO53,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 20. "GPIO52,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "GPIO51,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 18. "GPIO50,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 17. "GPIO49,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 16. "GPIO48,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 15. "GPIO47,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 14. "GPIO46,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 13. "GPIO45,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 12. "GPIO44,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 11. "GPIO43,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 10. "GPIO42,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 9. "GPIO41,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 8. "GPIO40,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "GPIO39,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 6. "GPIO38,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 5. "GPIO37,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 4. "GPIO36,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 3. "GPIO35,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 2. "GPIO34,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 1. "GPIO33,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x18 0. "GPIO32,Output Clear bit for this pin" "0,1"
|
|
line.long 0x1C "GPBTOGGLE,GPIO B Data Toggle Register (GPIO32 to 63)"
|
|
bitfld.long 0x1C 31. "GPIO63,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 30. "GPIO62,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 29. "GPIO61,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 28. "GPIO60,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 27. "GPIO59,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 26. "GPIO58,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 25. "GPIO57,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 24. "GPIO56,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 23. "GPIO55,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 22. "GPIO54,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 21. "GPIO53,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 20. "GPIO52,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 19. "GPIO51,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 18. "GPIO50,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 17. "GPIO49,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 16. "GPIO48,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 15. "GPIO47,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 14. "GPIO46,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 13. "GPIO45,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 12. "GPIO44,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 11. "GPIO43,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 10. "GPIO42,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 9. "GPIO41,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 8. "GPIO40,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "GPIO39,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 6. "GPIO38,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 5. "GPIO37,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 4. "GPIO36,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 3. "GPIO35,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 2. "GPIO34,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 1. "GPIO33,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x1C 0. "GPIO32,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x20 "GPCDAT,GPIO C Data Register (GPIO64 to 95)"
|
|
bitfld.long 0x20 31. "GPIO95,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 30. "GPIO94,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 29. "GPIO93,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 28. "GPIO92,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 27. "GPIO91,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 26. "GPIO90,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 25. "GPIO89,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 24. "GPIO88,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 23. "GPIO87,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 22. "GPIO86,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 21. "GPIO85,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 20. "GPIO84,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x20 19. "GPIO83,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 18. "GPIO82,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 17. "GPIO81,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 16. "GPIO80,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 15. "GPIO79,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 14. "GPIO78,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 13. "GPIO77,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 12. "GPIO76,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 11. "GPIO75,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 10. "GPIO74,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 9. "GPIO73,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 8. "GPIO72,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "GPIO71,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 6. "GPIO70,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 5. "GPIO69,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 4. "GPIO68,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 3. "GPIO67,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 2. "GPIO66,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 1. "GPIO65,Data Register for this pin" "0,1"
|
|
bitfld.long 0x20 0. "GPIO64,Data Register for this pin" "0,1"
|
|
line.long 0x24 "GPCSET,GPIO C Data Set Register (GPIO64 to 95)"
|
|
bitfld.long 0x24 31. "GPIO95,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 30. "GPIO94,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 29. "GPIO93,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 28. "GPIO92,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 27. "GPIO91,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 26. "GPIO90,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 25. "GPIO89,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 24. "GPIO88,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 23. "GPIO87,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 22. "GPIO86,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 21. "GPIO85,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 20. "GPIO84,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x24 19. "GPIO83,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 18. "GPIO82,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 17. "GPIO81,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 16. "GPIO80,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 15. "GPIO79,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 14. "GPIO78,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 13. "GPIO77,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 12. "GPIO76,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 11. "GPIO75,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 10. "GPIO74,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 9. "GPIO73,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 8. "GPIO72,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "GPIO71,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 6. "GPIO70,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 5. "GPIO69,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 4. "GPIO68,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 3. "GPIO67,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 2. "GPIO66,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 1. "GPIO65,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x24 0. "GPIO64,Output Set bit for this pin" "0,1"
|
|
line.long 0x28 "GPCCLEAR,GPIO C Data Clear Register (GPIO64 to 95)"
|
|
bitfld.long 0x28 31. "GPIO95,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 30. "GPIO94,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 29. "GPIO93,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 28. "GPIO92,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 27. "GPIO91,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 26. "GPIO90,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 25. "GPIO89,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 24. "GPIO88,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 23. "GPIO87,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 22. "GPIO86,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 21. "GPIO85,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 20. "GPIO84,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x28 19. "GPIO83,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 18. "GPIO82,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 17. "GPIO81,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 16. "GPIO80,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 15. "GPIO79,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 14. "GPIO78,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 13. "GPIO77,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 12. "GPIO76,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 11. "GPIO75,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 10. "GPIO74,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 9. "GPIO73,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 8. "GPIO72,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x28 7. "GPIO71,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 6. "GPIO70,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 5. "GPIO69,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 4. "GPIO68,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 3. "GPIO67,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 2. "GPIO66,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 1. "GPIO65,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x28 0. "GPIO64,Output Clear bit for this pin" "0,1"
|
|
line.long 0x2C "GPCTOGGLE,GPIO C Data Toggle Register (GPIO64 to 95)"
|
|
bitfld.long 0x2C 31. "GPIO95,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 30. "GPIO94,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 29. "GPIO93,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 28. "GPIO92,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 27. "GPIO91,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 26. "GPIO90,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 25. "GPIO89,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 24. "GPIO88,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 23. "GPIO87,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 22. "GPIO86,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 21. "GPIO85,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 20. "GPIO84,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 19. "GPIO83,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 18. "GPIO82,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 17. "GPIO81,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 16. "GPIO80,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 15. "GPIO79,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 14. "GPIO78,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 13. "GPIO77,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 12. "GPIO76,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 11. "GPIO75,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 10. "GPIO74,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 9. "GPIO73,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 8. "GPIO72,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 7. "GPIO71,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 6. "GPIO70,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 5. "GPIO69,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 4. "GPIO68,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 3. "GPIO67,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 2. "GPIO66,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 1. "GPIO65,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x2C 0. "GPIO64,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x30 "GPDDAT,GPIO D Data Register (GPIO96 to 127)"
|
|
bitfld.long 0x30 31. "GPIO127,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 30. "GPIO126,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 29. "GPIO125,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 28. "GPIO124,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 27. "GPIO123,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 26. "GPIO122,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 25. "GPIO121,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 24. "GPIO120,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 23. "GPIO119,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 22. "GPIO118,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 21. "GPIO117,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 20. "GPIO116,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x30 19. "GPIO115,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 18. "GPIO114,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 17. "GPIO113,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 16. "GPIO112,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 15. "GPIO111,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 14. "GPIO110,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 13. "GPIO109,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 12. "GPIO108,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 11. "GPIO107,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 10. "GPIO106,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 9. "GPIO105,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 8. "GPIO104,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x30 7. "GPIO103,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 6. "GPIO102,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 5. "GPIO101,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 4. "GPIO100,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 3. "GPIO99,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 2. "GPIO98,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 1. "GPIO97,Data Register for this pin" "0,1"
|
|
bitfld.long 0x30 0. "GPIO96,Data Register for this pin" "0,1"
|
|
line.long 0x34 "GPDSET,GPIO D Data Set Register (GPIO96 to 127)"
|
|
bitfld.long 0x34 31. "GPIO127,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 30. "GPIO126,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 29. "GPIO125,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 28. "GPIO124,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 27. "GPIO123,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 26. "GPIO122,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 25. "GPIO121,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 24. "GPIO120,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 23. "GPIO119,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 22. "GPIO118,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 21. "GPIO117,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 20. "GPIO116,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x34 19. "GPIO115,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 18. "GPIO114,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 17. "GPIO113,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 16. "GPIO112,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 15. "GPIO111,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 14. "GPIO110,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 13. "GPIO109,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 12. "GPIO108,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 11. "GPIO107,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 10. "GPIO106,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 9. "GPIO105,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 8. "GPIO104,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "GPIO103,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 6. "GPIO102,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 5. "GPIO101,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 4. "GPIO100,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 3. "GPIO99,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 2. "GPIO98,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 1. "GPIO97,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x34 0. "GPIO96,Output Set bit for this pin" "0,1"
|
|
line.long 0x38 "GPDCLEAR,GPIO D Data Clear Register (GPIO96 to 127)"
|
|
bitfld.long 0x38 31. "GPIO127,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 30. "GPIO126,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 29. "GPIO125,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 28. "GPIO124,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 27. "GPIO123,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 26. "GPIO122,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 25. "GPIO121,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 24. "GPIO120,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 23. "GPIO119,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 22. "GPIO118,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 21. "GPIO117,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 20. "GPIO116,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x38 19. "GPIO115,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 18. "GPIO114,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 17. "GPIO113,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 16. "GPIO112,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 15. "GPIO111,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 14. "GPIO110,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 13. "GPIO109,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 12. "GPIO108,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 11. "GPIO107,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 10. "GPIO106,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 9. "GPIO105,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 8. "GPIO104,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "GPIO103,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 6. "GPIO102,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 5. "GPIO101,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 4. "GPIO100,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 3. "GPIO99,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 2. "GPIO98,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 1. "GPIO97,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x38 0. "GPIO96,Output Clear bit for this pin" "0,1"
|
|
line.long 0x3C "GPDTOGGLE,GPIO D Data Toggle Register (GPIO96 to 127)"
|
|
bitfld.long 0x3C 31. "GPIO127,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 30. "GPIO126,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 29. "GPIO125,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 28. "GPIO124,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 27. "GPIO123,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 26. "GPIO122,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 25. "GPIO121,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 24. "GPIO120,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 23. "GPIO119,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 22. "GPIO118,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 21. "GPIO117,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 20. "GPIO116,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 19. "GPIO115,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 18. "GPIO114,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 17. "GPIO113,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 16. "GPIO112,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 15. "GPIO111,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 14. "GPIO110,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 13. "GPIO109,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 12. "GPIO108,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 11. "GPIO107,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 10. "GPIO106,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 9. "GPIO105,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 8. "GPIO104,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 7. "GPIO103,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 6. "GPIO102,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 5. "GPIO101,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 4. "GPIO100,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 3. "GPIO99,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 2. "GPIO98,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 1. "GPIO97,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x3C 0. "GPIO96,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x40 "GPEDAT,GPIO E Data Register (GPIO128 to 159)"
|
|
bitfld.long 0x40 31. "GPIO159,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 30. "GPIO158,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 29. "GPIO157,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 28. "GPIO156,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 27. "GPIO155,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 26. "GPIO154,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 25. "GPIO153,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 24. "GPIO152,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 23. "GPIO151,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 22. "GPIO150,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 21. "GPIO149,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 20. "GPIO148,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x40 19. "GPIO147,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 18. "GPIO146,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 17. "GPIO145,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 16. "GPIO144,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 15. "GPIO143,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 14. "GPIO142,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 13. "GPIO141,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 12. "GPIO140,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 11. "GPIO139,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 10. "GPIO138,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 9. "GPIO137,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 8. "GPIO136,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x40 7. "GPIO135,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 6. "GPIO134,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 5. "GPIO133,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 4. "GPIO132,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 3. "GPIO131,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 2. "GPIO130,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 1. "GPIO129,Data Register for this pin" "0,1"
|
|
bitfld.long 0x40 0. "GPIO128,Data Register for this pin" "0,1"
|
|
line.long 0x44 "GPESET,GPIO E Data Set Register (GPIO128 to 159)"
|
|
bitfld.long 0x44 31. "GPIO159,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 30. "GPIO158,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 29. "GPIO157,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 28. "GPIO156,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 27. "GPIO155,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 26. "GPIO154,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 25. "GPIO153,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 24. "GPIO152,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 23. "GPIO151,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 22. "GPIO150,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 21. "GPIO149,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 20. "GPIO148,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x44 19. "GPIO147,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 18. "GPIO146,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 17. "GPIO145,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 16. "GPIO144,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 15. "GPIO143,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 14. "GPIO142,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 13. "GPIO141,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 12. "GPIO140,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 11. "GPIO139,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 10. "GPIO138,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 9. "GPIO137,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 8. "GPIO136,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x44 7. "GPIO135,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 6. "GPIO134,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 5. "GPIO133,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 4. "GPIO132,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 3. "GPIO131,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 2. "GPIO130,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 1. "GPIO129,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x44 0. "GPIO128,Output Set bit for this pin" "0,1"
|
|
line.long 0x48 "GPECLEAR,GPIO E Data Clear Register (GPIO128 to 159)"
|
|
bitfld.long 0x48 31. "GPIO159,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 30. "GPIO158,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 29. "GPIO157,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 28. "GPIO156,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 27. "GPIO155,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 26. "GPIO154,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 25. "GPIO153,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 24. "GPIO152,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 23. "GPIO151,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 22. "GPIO150,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 21. "GPIO149,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 20. "GPIO148,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x48 19. "GPIO147,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 18. "GPIO146,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 17. "GPIO145,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 16. "GPIO144,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 15. "GPIO143,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 14. "GPIO142,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 13. "GPIO141,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 12. "GPIO140,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 11. "GPIO139,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 10. "GPIO138,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 9. "GPIO137,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 8. "GPIO136,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x48 7. "GPIO135,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 6. "GPIO134,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 5. "GPIO133,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 4. "GPIO132,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 3. "GPIO131,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 2. "GPIO130,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 1. "GPIO129,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x48 0. "GPIO128,Output Clear bit for this pin" "0,1"
|
|
line.long 0x4C "GPETOGGLE,GPIO E Data Toggle Register (GPIO128 to 159)"
|
|
bitfld.long 0x4C 31. "GPIO159,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 30. "GPIO158,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 29. "GPIO157,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 28. "GPIO156,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 27. "GPIO155,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 26. "GPIO154,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 25. "GPIO153,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 24. "GPIO152,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 23. "GPIO151,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 22. "GPIO150,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 21. "GPIO149,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 20. "GPIO148,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 19. "GPIO147,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 18. "GPIO146,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 17. "GPIO145,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 16. "GPIO144,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 15. "GPIO143,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 14. "GPIO142,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 13. "GPIO141,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 12. "GPIO140,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 11. "GPIO139,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 10. "GPIO138,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 9. "GPIO137,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 8. "GPIO136,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 7. "GPIO135,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 6. "GPIO134,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 5. "GPIO133,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 4. "GPIO132,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 3. "GPIO131,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 2. "GPIO130,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 1. "GPIO129,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x4C 0. "GPIO128,Output Toggle bit for this pin" "0,1"
|
|
line.long 0x50 "GPFDAT,GPIO F Data Register (GPIO160 to 191)"
|
|
bitfld.long 0x50 8. "GPIO168,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 7. "GPIO167,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 6. "GPIO166,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 5. "GPIO165,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 4. "GPIO164,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 3. "GPIO163,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 2. "GPIO162,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 1. "GPIO161,Data Register for this pin" "0,1"
|
|
bitfld.long 0x50 0. "GPIO160,Data Register for this pin" "0,1"
|
|
line.long 0x54 "GPFSET,GPIO F Data Set Register (GPIO160 to 191)"
|
|
bitfld.long 0x54 8. "GPIO168,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 7. "GPIO167,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 6. "GPIO166,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 5. "GPIO165,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 4. "GPIO164,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 3. "GPIO163,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 2. "GPIO162,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 1. "GPIO161,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x54 0. "GPIO160,Output Set bit for this pin" "0,1"
|
|
line.long 0x58 "GPFCLEAR,GPIO F Data Clear Register (GPIO160 to 191)"
|
|
bitfld.long 0x58 8. "GPIO168,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 7. "GPIO167,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 6. "GPIO166,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 5. "GPIO165,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 4. "GPIO164,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 3. "GPIO163,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 2. "GPIO162,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 1. "GPIO161,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x58 0. "GPIO160,Output Clear bit for this pin" "0,1"
|
|
line.long 0x5C "GPFTOGGLE,GPIO F Data Toggle Register (GPIO160 to 191)"
|
|
bitfld.long 0x5C 8. "GPIO168,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 7. "GPIO167,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 6. "GPIO166,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 5. "GPIO165,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 4. "GPIO164,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 3. "GPIO163,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 2. "GPIO162,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 1. "GPIO161,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x5C 0. "GPIO160,Output Toggle bit for this pin" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "GPIODATAREAD"
|
|
base d:0x40083100
|
|
rgroup.long 0x0++0x1F
|
|
line.long 0x0 "GPADAT_R,GPIO A Data Read Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,GPADAT register value"
|
|
line.long 0x4 "GPBDAT_R,GPIO B Data Read Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,GPBDAT register value"
|
|
line.long 0x8 "GPCDAT_R,GPIO C Data Read Register"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,GPCDAT register value"
|
|
line.long 0xC "GPDDAT_R,GPIO D Data Read Register"
|
|
hexmask.long 0xC 0.--31. 1. "DATA,GPDDAT register value"
|
|
line.long 0x10 "GPEDAT_R,GPIO E Data Read Register"
|
|
hexmask.long 0x10 0.--31. 1. "DATA,GPEDAT register value"
|
|
line.long 0x14 "GPFDAT_R,GPIO F Data Read Register"
|
|
hexmask.long 0x14 0.--31. 1. "DATA,GPFDAT register value"
|
|
line.long 0x18 "GPGDAT_R,GPIO G Data Read Register"
|
|
hexmask.long 0x18 0.--31. 1. "DATA,GPGDAT register value"
|
|
line.long 0x1C "GPHDAT_R,GPIO H Data Read Register"
|
|
hexmask.long 0x1C 0.--31. 1. "DATA,GPHDAT register value"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "HRCAP (High Resolution Capture)"
|
|
base d:0x0
|
|
tree "ECAP6_HRCAP"
|
|
base d:0x5360
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HRCTL,High-Res Control Register"
|
|
bitfld.long 0x0 5. "CALIBCONT,Continuous mode Calibration Select" "0,1"
|
|
rbitfld.long 0x0 4. "CALIBSTS,Calibration status" "0,1"
|
|
bitfld.long 0x0 3. "CALIBSTART,Calibration start" "0,1"
|
|
bitfld.long 0x0 2. "PRDSEL,Calibration Period Match" "0,1"
|
|
bitfld.long 0x0 1. "HRCLKE,High Resolution Clock Enable" "0,1"
|
|
bitfld.long 0x0 0. "HRE,High Resolution Enable" "0,1"
|
|
line.long 0x4 "HRINTEN,High-Res Calibration Interrupt Enable Register"
|
|
bitfld.long 0x4 2. "CALPRDCHKSTS,Calibration period check status enable" "0,1"
|
|
bitfld.long 0x4 1. "CALIBDONE,Calibration doe interrupt enable" "0,1"
|
|
rgroup.long 0x6++0x3
|
|
line.long 0x0 "HRFLG,High-Res Calibration Interrupt Flag Register"
|
|
bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bi" "0,1"
|
|
bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "HRCLR,High-Res Calibration Interrupt Clear Register"
|
|
bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag" "0,1"
|
|
line.long 0x2 "HRFRC,High-Res Calibration Interrupt Force Register"
|
|
bitfld.long 0x2 2. "CALPRDCHKSTS,Force Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x2 1. "CALIBDONE,Force Calibration Done Interrupt Flag Bit" "0,1"
|
|
line.long 0x4 "HRCALPRD,High-Res Calibration Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "PRD,Calibration period"
|
|
rgroup.long 0xE++0xF
|
|
line.long 0x0 "HRSYSCLKCTR,High-Res Calibration SYSCLK Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYCLK counter value"
|
|
line.long 0x2 "HRSYSCLKCAP,High-Res Calibration SYSCLK Capture Register"
|
|
hexmask.long 0x2 0.--31. 1. "HRSYSCLKCAP,Reads captured SYSCLK counter"
|
|
line.long 0x4 "HRCLKCTR,High-Res Calibration HRCLK Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "HRCLKCTR,Current HRCLK counter value"
|
|
line.long 0x6 "HRCLKCAP,High-Res Calibration HRCLK Capture Register"
|
|
hexmask.long 0x6 0.--31. 1. "HRCLKCAP,Reads captured HRCLK counter"
|
|
tree.end
|
|
tree "ECAP7_HRCAP"
|
|
base d:0x53A0
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "HRCTL,High-Res Control Register"
|
|
bitfld.long 0x0 5. "CALIBCONT,Continuous mode Calibration Select" "0,1"
|
|
rbitfld.long 0x0 4. "CALIBSTS,Calibration status" "0,1"
|
|
bitfld.long 0x0 3. "CALIBSTART,Calibration start" "0,1"
|
|
bitfld.long 0x0 2. "PRDSEL,Calibration Period Match" "0,1"
|
|
bitfld.long 0x0 1. "HRCLKE,High Resolution Clock Enable" "0,1"
|
|
bitfld.long 0x0 0. "HRE,High Resolution Enable" "0,1"
|
|
line.long 0x4 "HRINTEN,High-Res Calibration Interrupt Enable Register"
|
|
bitfld.long 0x4 2. "CALPRDCHKSTS,Calibration period check status enable" "0,1"
|
|
bitfld.long 0x4 1. "CALIBDONE,Calibration doe interrupt enable" "0,1"
|
|
rgroup.long 0x6++0x3
|
|
line.long 0x0 "HRFLG,High-Res Calibration Interrupt Flag Register"
|
|
bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bi" "0,1"
|
|
bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "HRCLR,High-Res Calibration Interrupt Clear Register"
|
|
bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag" "0,1"
|
|
line.long 0x2 "HRFRC,High-Res Calibration Interrupt Force Register"
|
|
bitfld.long 0x2 2. "CALPRDCHKSTS,Force Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x2 1. "CALIBDONE,Force Calibration Done Interrupt Flag Bit" "0,1"
|
|
line.long 0x4 "HRCALPRD,High-Res Calibration Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "PRD,Calibration period"
|
|
rgroup.long 0xE++0xF
|
|
line.long 0x0 "HRSYSCLKCTR,High-Res Calibration SYSCLK Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYCLK counter value"
|
|
line.long 0x2 "HRSYSCLKCAP,High-Res Calibration SYSCLK Capture Register"
|
|
hexmask.long 0x2 0.--31. 1. "HRSYSCLKCAP,Reads captured SYSCLK counter"
|
|
line.long 0x4 "HRCLKCTR,High-Res Calibration HRCLK Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "HRCLKCTR,Current HRCLK counter value"
|
|
line.long 0x6 "HRCLKCAP,High-Res Calibration HRCLK Capture Register"
|
|
hexmask.long 0x6 0.--31. 1. "HRCLKCAP,Reads captured HRCLK counter"
|
|
tree.end
|
|
tree.end
|
|
tree "HWBIST (Hardware Built-In Self-Test)"
|
|
base d:0x5E000
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CSTCGCR1,STC Global Control Register1"
|
|
hexmask.long 0x0 0.--31. 1. "MICROCFG,Micro Configuration"
|
|
group.long 0xC++0x2F
|
|
line.long 0x0 "CSTCGCR3,STC Global Control Register3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ILS,Interrupt Logging Start"
|
|
line.long 0x4 "CSTCGCR4,STC Global Control Register4"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BISTGO,BIST Start"
|
|
line.long 0x8 "CSTCGCR5,STC Global Control Register5"
|
|
bitfld.long 0x8 31. "SOFT_RESET,Soft reset to BIST controller" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "RESTART,Restart Enable"
|
|
line.long 0xC "CSTCGCR6,STC Global Control Register6"
|
|
bitfld.long 0xC 0.--1. "COV,COVERAGE" "0,1,2,3"
|
|
line.long 0x10 "CSTCGCR7,STC Global Control Register7"
|
|
bitfld.long 0x10 18.--19. "SCD,SHIFT_CLOCK_DIVISION" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "PST,PATTERN SET TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x10 12.--15. 1. "NP,NUM OF PIPELINE STAGES"
|
|
hexmask.long.byte 0x10 8.--11. 1. "DC,DEAD CYCLES"
|
|
hexmask.long.byte 0x10 0.--7. 1. "MCL,MAX CHAIN LENGTH"
|
|
line.long 0x14 "CSTCGCR8,STC Global Control Register8"
|
|
hexmask.long.word 0x14 0.--15. 1. "CPC,COMPARE PATTERN CNT"
|
|
line.long 0x18 "CSTCPCNT,STC Pattern Count Register"
|
|
hexmask.long.word 0x18 16.--31. 1. "PCNT_99,PATTERNS FOR 99% COVERAGE"
|
|
hexmask.long.word 0x18 0.--15. 1. "PCNT_95,PATTERNS FOR 95% COVERAGE"
|
|
line.long 0x1C "CSTCCONFIG,STC Registers Configuration Status"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "CFGDONE,Configuration done"
|
|
line.long 0x20 "CSTCSADDR,STC ROM Start Address"
|
|
hexmask.long.word 0x20 16.--31. 1. "SAMISR,MISR ROM Start Address"
|
|
hexmask.long.word 0x20 0.--15. 1. "SAPAT,PATTERN ROM Start Address"
|
|
line.long 0x24 "CSTCTEST,C28 HW BIST Test Register"
|
|
hexmask.long.tbyte 0x24 12.--31. 1. "TEST,TEST Bits"
|
|
hexmask.long.byte 0x24 8.--11. 1. "TEST_NMI,Test_NMI"
|
|
hexmask.long.byte 0x24 4.--7. 1. "TEST_CMP_FAIL,Test MISR compare fail"
|
|
hexmask.long.byte 0x24 0.--3. 1. "TEST_TO,Test_ Time_Out"
|
|
line.long 0x28 "CSTCRET,C28 Return PC Address"
|
|
hexmask.long 0x28 0.--31. 1. "RETADDR,Return Address"
|
|
line.long 0x2C "CSTCCRD,C28 Context Restore Done Register"
|
|
hexmask.long.byte 0x2C 0.--3. 1. "Restore_Done,Context Restone Done"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "CSTCGSTAT,STC Global Status Register"
|
|
bitfld.long 0x0 5. "TOFAIL,Time Out Failure" "0,1"
|
|
bitfld.long 0x0 4. "INTCMPF,Intermediate Comparison Failure" "0,1"
|
|
bitfld.long 0x0 3. "BISTFAIL,HW BIST Failure" "0,1"
|
|
bitfld.long 0x0 2. "NMI,Exit due to NMI" "0,1"
|
|
bitfld.long 0x0 1. "MACRODONE,Macro test slot Complete" "0,1"
|
|
bitfld.long 0x0 0. "BISTDONE,HW BIST Complete" "0,1"
|
|
rgroup.long 0x48++0x47
|
|
line.long 0x0 "CSTCCPCR,STC Current Pattern Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PATCNT,Current Pattern Count"
|
|
line.long 0x4 "CSTCCADDR,STC Current ROM Address Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "MISRADDR,Current MISR ROM Address"
|
|
hexmask.long.word 0x4 0.--15. 1. "PATADDR,Current Pattern ROM Address"
|
|
line.long 0x8 "CSTCMISR0,MISR Result Register 0"
|
|
hexmask.long 0x8 0.--31. 1. "MISR0,Final MISR Result[31:0]"
|
|
line.long 0xC "CSTCMISR1,MISR Result Register 1"
|
|
hexmask.long 0xC 0.--31. 1. "MISR1,Final MISR Result[63:32]"
|
|
line.long 0x10 "CSTCMISR2,MISR Result Register 2"
|
|
hexmask.long 0x10 0.--31. 1. "MISR2,Final MISR Result[95:64]"
|
|
line.long 0x14 "CSTCMISR3,MISR Result Register 3"
|
|
hexmask.long 0x14 0.--31. 1. "MISR3,Final MISR Result[127:96]"
|
|
line.long 0x18 "CSTCMISR4,MISR Result Register 4"
|
|
hexmask.long 0x18 0.--31. 1. "MISR4,Final MISR Result[159:128]"
|
|
line.long 0x1C "CSTCMISR5,MISR Result Register 5"
|
|
hexmask.long 0x1C 0.--31. 1. "MISR5,Final MISR Result[191:160]"
|
|
line.long 0x20 "CSTCMISR6,MISR Result Register 6"
|
|
hexmask.long 0x20 0.--31. 1. "MISR6,Final MISR Result[223:192]"
|
|
line.long 0x24 "CSTCMISR7,MISR Result Register 7"
|
|
hexmask.long 0x24 0.--31. 1. "MISR7,Final MISR Result[255:224]"
|
|
line.long 0x28 "CSTCMISR8,MISR Result Register 8"
|
|
hexmask.long 0x28 0.--31. 1. "MISR8,Final MISR Result[287:256]"
|
|
line.long 0x2C "CSTCMISR9,MISR Result Register 9"
|
|
hexmask.long 0x2C 0.--31. 1. "MISR9,Final MISR Result[319:288]"
|
|
line.long 0x30 "CSTCMISR10,MISR Result Register 10"
|
|
hexmask.long 0x30 0.--31. 1. "MISR10,Final MISR Result[351:320]"
|
|
line.long 0x34 "CSTCMISR11,MISR Result Register 11"
|
|
hexmask.long 0x34 0.--31. 1. "MISR11,Final MISR Result[383:352]"
|
|
line.long 0x38 "CSTCMISR12,MISR Result Register 12"
|
|
hexmask.long 0x38 0.--31. 1. "MISR12,Final MISR Result[415:384]"
|
|
line.long 0x3C "CSTCMISR13,MISR Result Register 13"
|
|
hexmask.long 0x3C 0.--31. 1. "MISR13,Final MISR Result[447:416]"
|
|
line.long 0x40 "CSTCMISR14,MISR Result Register 14"
|
|
hexmask.long 0x40 0.--31. 1. "MISR14,Final MISR Result[479:448]"
|
|
line.long 0x44 "CSTCMISR15,MISR Result Register 15"
|
|
hexmask.long 0x44 0.--31. 1. "MISR15,Final MISR Result[511:480]"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "CSTCSEM,STC Semaphore register"
|
|
bitfld.long 0x0 0.--1. "SEMAPHORE,Semaphore" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
base d:0x0
|
|
elif (cpuis("F2838??-CM"))
|
|
base d:0x40020000
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM"))
|
|
tree "I2C (Inter-Integrated Circuit Module)"
|
|
sif (cpuis("F2838??"))
|
|
tree "I2CA"
|
|
base d:0x7300
|
|
group.word 0x0++0xB
|
|
line.word 0x0 "I2COAR,I2C Own address"
|
|
hexmask.word 0x0 0.--9. 1. "OAR,I2C Own address"
|
|
line.word 0x1 "I2CIER,I2C Interrupt Enable"
|
|
bitfld.word 0x1 6. "AAS,Addressed as slave interrupt enable" "0,1"
|
|
bitfld.word 0x1 5. "SCD,Stop condition detected interrupt enable" "0,1"
|
|
bitfld.word 0x1 4. "XRDY,Transmit-data-ready interrupt enable" "0,1"
|
|
bitfld.word 0x1 3. "RRDY,Receive-data-ready interrupt enable" "0,1"
|
|
bitfld.word 0x1 2. "ARDY,Register-access-ready interrupt enable" "0,1"
|
|
bitfld.word 0x1 1. "NACK,No-acknowledgment interrupt enable" "0,1"
|
|
bitfld.word 0x1 0. "ARBL,Arbitration-lost interrupt enable" "0,1"
|
|
line.word 0x2 "I2CSTR,I2C Status"
|
|
bitfld.word 0x2 14. "SDIR,Slave direction bit" "0,1"
|
|
bitfld.word 0x2 13. "NACKSNT,NACK sent bit." "0,1"
|
|
rbitfld.word 0x2 12. "BB,Bus busy bit." "0,1"
|
|
rbitfld.word 0x2 11. "RSFULL,Receive shift register full bit." "0,1"
|
|
rbitfld.word 0x2 10. "XSMT,Transmit shift register empty bit." "0,1"
|
|
rbitfld.word 0x2 9. "AAS,Addressed-as-slave bit" "0,1"
|
|
rbitfld.word 0x2 8. "AD0,Address 0 bits" "0,1"
|
|
bitfld.word 0x2 6. "BYTESENT,Byte transmit over indication" "0,1"
|
|
bitfld.word 0x2 5. "SCD,Stop condition detected bit." "0,1"
|
|
newline
|
|
rbitfld.word 0x2 4. "XRDY,Transmit-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x2 3. "RRDY,Receive-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x2 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
|
|
bitfld.word 0x2 1. "NACK,No-acknowledgment interrupt flag bit." "0,1"
|
|
bitfld.word 0x2 0. "ARBL,Arbitration-lost interrupt flag bit" "0,1"
|
|
line.word 0x3 "I2CCLKL,I2C Clock low-time divider"
|
|
hexmask.word 0x3 0.--15. 1. "I2CCLKL,Clock low-time divide-down value."
|
|
line.word 0x4 "I2CCLKH,I2C Clock high-time divider"
|
|
hexmask.word 0x4 0.--15. 1. "I2CCLKH,Clock high-time divide-down value."
|
|
line.word 0x5 "I2CCNT,I2C Data count"
|
|
hexmask.word 0x5 0.--15. 1. "I2CCNT,Data count value."
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "I2CDRR,I2C Data receive"
|
|
hexmask.word.byte 0x0 0.--7. 1. "DATA,Receive data"
|
|
group.word 0x7++0xB
|
|
line.word 0x0 "I2CSAR,I2C Slave address"
|
|
hexmask.word 0x0 0.--9. 1. "SAR,Slave Address"
|
|
line.word 0x1 "I2CDXR,I2C Data Transmit"
|
|
hexmask.word.byte 0x1 0.--7. 1. "DATA,Transmit data"
|
|
line.word 0x2 "I2CMDR,I2C Mode"
|
|
bitfld.word 0x2 15. "NACKMOD,NACK mode bit" "0,1"
|
|
bitfld.word 0x2 14. "FREE,Debug Action" "0,1"
|
|
bitfld.word 0x2 13. "STT,START condition bit" "0,1"
|
|
bitfld.word 0x2 11. "STP,STOP Condition" "0,1"
|
|
bitfld.word 0x2 10. "MST,Master Mode" "0,1"
|
|
bitfld.word 0x2 9. "TRX,Transmitter Mode" "0,1"
|
|
bitfld.word 0x2 8. "XA,Expanded Address Mode" "0,1"
|
|
bitfld.word 0x2 7. "RM,Repeat Mode" "0,1"
|
|
bitfld.word 0x2 6. "DLB,Digital Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "IRS,I2C Module Reset" "0,1"
|
|
bitfld.word 0x2 4. "STB,START Byte Mode" "0,1"
|
|
bitfld.word 0x2 3. "FDF,Free Data Format" "0,1"
|
|
bitfld.word 0x2 0.--2. "BC,Bit count bits." "0,1,2,3,4,5,6,7"
|
|
line.word 0x3 "I2CISRC,I2C Interrupt Source"
|
|
hexmask.word.byte 0x3 8.--11. 1. "WRITE_ZEROS,Always write all 0s to this field"
|
|
rbitfld.word 0x3 0.--2. "INTCODE,Interrupt code bits." "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "I2CEMDR,I2C Extended Mode"
|
|
bitfld.word 0x4 1. "FCM,Forward Compatibility for Tx behav in Type1" "0,1"
|
|
bitfld.word 0x4 0. "BC,Backwards compatibility mode" "0,1"
|
|
line.word 0x5 "I2CPSC,I2C Prescaler"
|
|
hexmask.word.byte 0x5 0.--7. 1. "IPSC,I2C Prescaler Divide Down"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "I2CFFTX,I2C FIFO Transmit"
|
|
bitfld.word 0x0 14. "I2CFFEN,Transmit FIFO Enable" "0,1"
|
|
bitfld.word 0x0 13. "TXFFRST,Transmit FIFO Reset" "0,1"
|
|
hexmask.word.byte 0x0 8.--12. 1. "TXFFST,Transmit FIFO Status"
|
|
rbitfld.word 0x0 7. "TXFFINT,Transmit FIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "TXFFINTCLR,Transmit FIFO Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "TXFFIENA,Transmit FIFO Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXFFIL,Transmit FIFO Interrupt Level"
|
|
line.word 0x1 "I2CFFRX,I2C FIFO Receive"
|
|
bitfld.word 0x1 13. "RXFFRST,Receive FIFO Reset" "0,1"
|
|
hexmask.word.byte 0x1 8.--12. 1. "RXFFST,Receive FIFO Status"
|
|
rbitfld.word 0x1 7. "RXFFINT,Receive FIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x1 6. "RXFFINTCLR,Receive FIFO Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 5. "RXFFIENA,Receive FIFO Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--4. 1. "RXFFIL,Receive FIFO Interrupt Level"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "I2CB"
|
|
base d:0x7340
|
|
group.word 0x0++0xB
|
|
line.word 0x0 "I2COAR,I2C Own address"
|
|
hexmask.word 0x0 0.--9. 1. "OAR,I2C Own address"
|
|
line.word 0x1 "I2CIER,I2C Interrupt Enable"
|
|
bitfld.word 0x1 6. "AAS,Addressed as slave interrupt enable" "0,1"
|
|
bitfld.word 0x1 5. "SCD,Stop condition detected interrupt enable" "0,1"
|
|
bitfld.word 0x1 4. "XRDY,Transmit-data-ready interrupt enable" "0,1"
|
|
bitfld.word 0x1 3. "RRDY,Receive-data-ready interrupt enable" "0,1"
|
|
bitfld.word 0x1 2. "ARDY,Register-access-ready interrupt enable" "0,1"
|
|
bitfld.word 0x1 1. "NACK,No-acknowledgment interrupt enable" "0,1"
|
|
bitfld.word 0x1 0. "ARBL,Arbitration-lost interrupt enable" "0,1"
|
|
line.word 0x2 "I2CSTR,I2C Status"
|
|
bitfld.word 0x2 14. "SDIR,Slave direction bit" "0,1"
|
|
bitfld.word 0x2 13. "NACKSNT,NACK sent bit." "0,1"
|
|
rbitfld.word 0x2 12. "BB,Bus busy bit." "0,1"
|
|
rbitfld.word 0x2 11. "RSFULL,Receive shift register full bit." "0,1"
|
|
rbitfld.word 0x2 10. "XSMT,Transmit shift register empty bit." "0,1"
|
|
rbitfld.word 0x2 9. "AAS,Addressed-as-slave bit" "0,1"
|
|
rbitfld.word 0x2 8. "AD0,Address 0 bits" "0,1"
|
|
bitfld.word 0x2 6. "BYTESENT,Byte transmit over indication" "0,1"
|
|
bitfld.word 0x2 5. "SCD,Stop condition detected bit." "0,1"
|
|
newline
|
|
rbitfld.word 0x2 4. "XRDY,Transmit-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x2 3. "RRDY,Receive-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x2 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
|
|
bitfld.word 0x2 1. "NACK,No-acknowledgment interrupt flag bit." "0,1"
|
|
bitfld.word 0x2 0. "ARBL,Arbitration-lost interrupt flag bit" "0,1"
|
|
line.word 0x3 "I2CCLKL,I2C Clock low-time divider"
|
|
hexmask.word 0x3 0.--15. 1. "I2CCLKL,Clock low-time divide-down value."
|
|
line.word 0x4 "I2CCLKH,I2C Clock high-time divider"
|
|
hexmask.word 0x4 0.--15. 1. "I2CCLKH,Clock high-time divide-down value."
|
|
line.word 0x5 "I2CCNT,I2C Data count"
|
|
hexmask.word 0x5 0.--15. 1. "I2CCNT,Data count value."
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "I2CDRR,I2C Data receive"
|
|
hexmask.word.byte 0x0 0.--7. 1. "DATA,Receive data"
|
|
group.word 0x7++0xB
|
|
line.word 0x0 "I2CSAR,I2C Slave address"
|
|
hexmask.word 0x0 0.--9. 1. "SAR,Slave Address"
|
|
line.word 0x1 "I2CDXR,I2C Data Transmit"
|
|
hexmask.word.byte 0x1 0.--7. 1. "DATA,Transmit data"
|
|
line.word 0x2 "I2CMDR,I2C Mode"
|
|
bitfld.word 0x2 15. "NACKMOD,NACK mode bit" "0,1"
|
|
bitfld.word 0x2 14. "FREE,Debug Action" "0,1"
|
|
bitfld.word 0x2 13. "STT,START condition bit" "0,1"
|
|
bitfld.word 0x2 11. "STP,STOP Condition" "0,1"
|
|
bitfld.word 0x2 10. "MST,Master Mode" "0,1"
|
|
bitfld.word 0x2 9. "TRX,Transmitter Mode" "0,1"
|
|
bitfld.word 0x2 8. "XA,Expanded Address Mode" "0,1"
|
|
bitfld.word 0x2 7. "RM,Repeat Mode" "0,1"
|
|
bitfld.word 0x2 6. "DLB,Digital Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "IRS,I2C Module Reset" "0,1"
|
|
bitfld.word 0x2 4. "STB,START Byte Mode" "0,1"
|
|
bitfld.word 0x2 3. "FDF,Free Data Format" "0,1"
|
|
bitfld.word 0x2 0.--2. "BC,Bit count bits." "0,1,2,3,4,5,6,7"
|
|
line.word 0x3 "I2CISRC,I2C Interrupt Source"
|
|
hexmask.word.byte 0x3 8.--11. 1. "WRITE_ZEROS,Always write all 0s to this field"
|
|
rbitfld.word 0x3 0.--2. "INTCODE,Interrupt code bits." "0,1,2,3,4,5,6,7"
|
|
line.word 0x4 "I2CEMDR,I2C Extended Mode"
|
|
bitfld.word 0x4 1. "FCM,Forward Compatibility for Tx behav in Type1" "0,1"
|
|
bitfld.word 0x4 0. "BC,Backwards compatibility mode" "0,1"
|
|
line.word 0x5 "I2CPSC,I2C Prescaler"
|
|
hexmask.word.byte 0x5 0.--7. 1. "IPSC,I2C Prescaler Divide Down"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "I2CFFTX,I2C FIFO Transmit"
|
|
bitfld.word 0x0 14. "I2CFFEN,Transmit FIFO Enable" "0,1"
|
|
bitfld.word 0x0 13. "TXFFRST,Transmit FIFO Reset" "0,1"
|
|
hexmask.word.byte 0x0 8.--12. 1. "TXFFST,Transmit FIFO Status"
|
|
rbitfld.word 0x0 7. "TXFFINT,Transmit FIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 6. "TXFFINTCLR,Transmit FIFO Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x0 5. "TXFFIENA,Transmit FIFO Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXFFIL,Transmit FIFO Interrupt Level"
|
|
line.word 0x1 "I2CFFRX,I2C FIFO Receive"
|
|
bitfld.word 0x1 13. "RXFFRST,Receive FIFO Reset" "0,1"
|
|
hexmask.word.byte 0x1 8.--12. 1. "RXFFST,Receive FIFO Status"
|
|
rbitfld.word 0x1 7. "RXFFINT,Receive FIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x1 6. "RXFFINTCLR,Receive FIFO Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x1 5. "RXFFIENA,Receive FIFO Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--4. 1. "RXFFIL,Receive FIFO Interrupt Level"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2CMSA,I2C Master Slave Address"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SA,I2C Slave Address"
|
|
bitfld.long 0x0 0. "RS,Receive/Send" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CLKTO,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x0 6. "BUSBSY,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDLE,I2C Idle" "0,1"
|
|
bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0,1"
|
|
bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERROR,Error" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,I2C Busy" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "I2CMDR,I2C Master Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data transmitted/received"
|
|
line.long 0x4 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x4 16.--18. "PULSEL,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "HS,High-Speed Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period"
|
|
line.long 0x8 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x8 11. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 10. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 8. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ARBLOSTIM,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 6. "STOPIM,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "STARTIM,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 4. "NACKIM,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 2. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CLKIM,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 0. "IM,Master Interrupt Mask" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x0 11. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTRIS,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "STOPRIS,STOP Detection Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTRIS,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "NACKRIS,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRIS,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RIS,Master Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x4 11. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "TXMIS,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLOSTMIS,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 6. "STOPMIS,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "STARTMIS,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "NACKMIS,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMATXMIS,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DMARXMIS,Receive DMA Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLKMIS,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "MIS,Masked Interrupt Status" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x0 11. "RXFFIC,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "TXFEIC,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXIC,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "TXIC,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTIC,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "STOPIC,STOP Detection Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTIC,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKIC,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKIC,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "IC,Master Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x4 5. "SFE,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x4 4. "MFE,I2C Master Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPBK,I2C Loopback" "0,1"
|
|
line.long 0x8 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "SDA,I2C SDA Status" "0,1"
|
|
bitfld.long 0x0 0. "SCL,I2C SCL Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "I2CSOAR,I2C Slave Own Address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OAR,I2C Slave Own Address"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x0 4. "QCMDST,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x0 2. "FBR,First Byte Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TREQ,Transmit Request" "0,1"
|
|
bitfld.long 0x0 0. "RREQ,Receive Request" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "I2CSDR,I2C Slave Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data for Transfer"
|
|
line.long 0x4 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x4 8. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPIM,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "STARTIM,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAIM,Data Interrupt Mask" "0,1"
|
|
rgroup.long 0x810++0x7
|
|
line.long 0x0 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x0 8. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPRIS,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "STARTRIS,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATARIS,Data Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x4 8. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPMIS,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "STARTMIS,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAMIS,Data Masked Interrupt Status" "0,1"
|
|
group.long 0x818++0xB
|
|
line.long 0x0 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x0 8. "RXFFIC,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXFEIC,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXIC,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPIC,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "STARTIC,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATAIC,Data Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x8 1. "ACKOVAL,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x8 0. "ACKOEN,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long 0xF04++0x3
|
|
line.long 0x0 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x0 31. "RXASGNMT,RX Control Assignment" "0,1"
|
|
bitfld.long 0x0 30. "RXFLUSH,RX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMARXENA,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXTRIG,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "TXASGNMT,TX Control Assignment" "0,1"
|
|
bitfld.long 0x0 14. "TXFLUSH,TX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMATXENA,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xF08++0x3
|
|
line.long 0x0 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x0 18. "RXABVTRIG,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x0 17. "RXFF,RX FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXFE,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x0 2. "TXBLWTRIG,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFF,TX FIFO Full" "0,1"
|
|
bitfld.long 0x0 0. "TXFE,TX FIFO Empty" "0,1"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2CMSA,I2C Master Slave Address"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SA,I2C Slave Address"
|
|
bitfld.long 0x0 0. "RS,Receive/Send" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CLKTO,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x0 6. "BUSBSY,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDLE,I2C Idle" "0,1"
|
|
bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0,1"
|
|
bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERROR,Error" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,I2C Busy" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "I2CMDR,I2C Master Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data transmitted/received"
|
|
line.long 0x4 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x4 16.--18. "PULSEL,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "HS,High-Speed Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period"
|
|
line.long 0x8 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x8 11. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 10. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 8. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ARBLOSTIM,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 6. "STOPIM,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "STARTIM,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 4. "NACKIM,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 2. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CLKIM,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 0. "IM,Master Interrupt Mask" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x0 11. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTRIS,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "STOPRIS,STOP Detection Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTRIS,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "NACKRIS,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRIS,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RIS,Master Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x4 11. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "TXMIS,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLOSTMIS,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 6. "STOPMIS,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "STARTMIS,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "NACKMIS,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMATXMIS,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DMARXMIS,Receive DMA Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLKMIS,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "MIS,Masked Interrupt Status" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x0 11. "RXFFIC,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "TXFEIC,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXIC,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "TXIC,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTIC,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "STOPIC,STOP Detection Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTIC,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKIC,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKIC,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "IC,Master Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x4 5. "SFE,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x4 4. "MFE,I2C Master Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPBK,I2C Loopback" "0,1"
|
|
line.long 0x8 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "SDA,I2C SDA Status" "0,1"
|
|
bitfld.long 0x0 0. "SCL,I2C SCL Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "I2CSOAR,I2C Slave Own Address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OAR,I2C Slave Own Address"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x0 4. "QCMDST,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x0 2. "FBR,First Byte Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TREQ,Transmit Request" "0,1"
|
|
bitfld.long 0x0 0. "RREQ,Receive Request" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "I2CSDR,I2C Slave Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data for Transfer"
|
|
line.long 0x4 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x4 8. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPIM,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "STARTIM,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAIM,Data Interrupt Mask" "0,1"
|
|
rgroup.long 0x810++0x7
|
|
line.long 0x0 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x0 8. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPRIS,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "STARTRIS,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATARIS,Data Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x4 8. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPMIS,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "STARTMIS,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAMIS,Data Masked Interrupt Status" "0,1"
|
|
group.long 0x818++0xB
|
|
line.long 0x0 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x0 8. "RXFFIC,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXFEIC,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXIC,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPIC,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "STARTIC,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATAIC,Data Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x8 1. "ACKOVAL,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x8 0. "ACKOEN,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long 0xF04++0x3
|
|
line.long 0x0 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x0 31. "RXASGNMT,RX Control Assignment" "0,1"
|
|
bitfld.long 0x0 30. "RXFLUSH,RX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMARXENA,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXTRIG,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "TXASGNMT,TX Control Assignment" "0,1"
|
|
bitfld.long 0x0 14. "TXFLUSH,TX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMATXENA,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xF08++0x3
|
|
line.long 0x0 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x0 18. "RXABVTRIG,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x0 17. "RXFF,RX FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXFE,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x0 2. "TXBLWTRIG,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFF,TX FIFO Full" "0,1"
|
|
bitfld.long 0x0 0. "TXFE,TX FIFO Empty" "0,1"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2CMSA,I2C Master Slave Address"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SA,I2C Slave Address"
|
|
bitfld.long 0x0 0. "RS,Receive/Send" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CLKTO,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x0 6. "BUSBSY,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDLE,I2C Idle" "0,1"
|
|
bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0,1"
|
|
bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERROR,Error" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,I2C Busy" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "I2CMDR,I2C Master Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data transmitted/received"
|
|
line.long 0x4 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x4 16.--18. "PULSEL,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "HS,High-Speed Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period"
|
|
line.long 0x8 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x8 11. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 10. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 8. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ARBLOSTIM,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 6. "STOPIM,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "STARTIM,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 4. "NACKIM,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 2. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CLKIM,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 0. "IM,Master Interrupt Mask" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x0 11. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTRIS,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "STOPRIS,STOP Detection Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTRIS,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "NACKRIS,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRIS,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RIS,Master Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x4 11. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "TXMIS,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLOSTMIS,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 6. "STOPMIS,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "STARTMIS,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "NACKMIS,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMATXMIS,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DMARXMIS,Receive DMA Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLKMIS,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "MIS,Masked Interrupt Status" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x0 11. "RXFFIC,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "TXFEIC,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXIC,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "TXIC,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTIC,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "STOPIC,STOP Detection Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTIC,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKIC,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKIC,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "IC,Master Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x4 5. "SFE,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x4 4. "MFE,I2C Master Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPBK,I2C Loopback" "0,1"
|
|
line.long 0x8 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "SDA,I2C SDA Status" "0,1"
|
|
bitfld.long 0x0 0. "SCL,I2C SCL Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "I2CSOAR,I2C Slave Own Address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OAR,I2C Slave Own Address"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x0 4. "QCMDST,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x0 2. "FBR,First Byte Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TREQ,Transmit Request" "0,1"
|
|
bitfld.long 0x0 0. "RREQ,Receive Request" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "I2CSDR,I2C Slave Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data for Transfer"
|
|
line.long 0x4 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x4 8. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPIM,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "STARTIM,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAIM,Data Interrupt Mask" "0,1"
|
|
rgroup.long 0x810++0x7
|
|
line.long 0x0 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x0 8. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPRIS,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "STARTRIS,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATARIS,Data Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x4 8. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPMIS,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "STARTMIS,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAMIS,Data Masked Interrupt Status" "0,1"
|
|
group.long 0x818++0xB
|
|
line.long 0x0 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x0 8. "RXFFIC,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXFEIC,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXIC,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPIC,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "STARTIC,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATAIC,Data Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x8 1. "ACKOVAL,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x8 0. "ACKOEN,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long 0xF04++0x3
|
|
line.long 0x0 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x0 31. "RXASGNMT,RX Control Assignment" "0,1"
|
|
bitfld.long 0x0 30. "RXFLUSH,RX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMARXENA,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXTRIG,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "TXASGNMT,TX Control Assignment" "0,1"
|
|
bitfld.long 0x0 14. "TXFLUSH,TX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMATXENA,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xF08++0x3
|
|
line.long 0x0 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x0 18. "RXABVTRIG,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x0 17. "RXFF,RX FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXFE,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x0 2. "TXBLWTRIG,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFF,TX FIFO Full" "0,1"
|
|
bitfld.long 0x0 0. "TXFE,TX FIFO Empty" "0,1"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2CMSA,I2C Master Slave Address"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SA,I2C Slave Address"
|
|
bitfld.long 0x0 0. "RS,Receive/Send" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CLKTO,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x0 6. "BUSBSY,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDLE,I2C Idle" "0,1"
|
|
bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0,1"
|
|
bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERROR,Error" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,I2C Busy" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "I2CMDR,I2C Master Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data transmitted/received"
|
|
line.long 0x4 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x4 16.--18. "PULSEL,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "HS,High-Speed Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period"
|
|
line.long 0x8 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x8 11. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 10. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 8. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ARBLOSTIM,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 6. "STOPIM,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "STARTIM,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 4. "NACKIM,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 2. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CLKIM,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 0. "IM,Master Interrupt Mask" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x0 11. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTRIS,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "STOPRIS,STOP Detection Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTRIS,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "NACKRIS,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRIS,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RIS,Master Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x4 11. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "TXMIS,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLOSTMIS,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 6. "STOPMIS,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "STARTMIS,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "NACKMIS,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMATXMIS,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DMARXMIS,Receive DMA Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLKMIS,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "MIS,Masked Interrupt Status" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x0 11. "RXFFIC,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "TXFEIC,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXIC,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "TXIC,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTIC,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "STOPIC,STOP Detection Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTIC,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKIC,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKIC,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "IC,Master Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x4 5. "SFE,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x4 4. "MFE,I2C Master Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPBK,I2C Loopback" "0,1"
|
|
line.long 0x8 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "SDA,I2C SDA Status" "0,1"
|
|
bitfld.long 0x0 0. "SCL,I2C SCL Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "I2CSOAR,I2C Slave Own Address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OAR,I2C Slave Own Address"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x0 4. "QCMDST,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x0 2. "FBR,First Byte Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TREQ,Transmit Request" "0,1"
|
|
bitfld.long 0x0 0. "RREQ,Receive Request" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "I2CSDR,I2C Slave Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data for Transfer"
|
|
line.long 0x4 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x4 8. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPIM,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "STARTIM,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAIM,Data Interrupt Mask" "0,1"
|
|
rgroup.long 0x810++0x7
|
|
line.long 0x0 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x0 8. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPRIS,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "STARTRIS,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATARIS,Data Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x4 8. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPMIS,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "STARTMIS,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAMIS,Data Masked Interrupt Status" "0,1"
|
|
group.long 0x818++0xB
|
|
line.long 0x0 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x0 8. "RXFFIC,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXFEIC,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXIC,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPIC,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "STARTIC,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATAIC,Data Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x8 1. "ACKOVAL,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x8 0. "ACKOEN,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long 0xF04++0x3
|
|
line.long 0x0 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x0 31. "RXASGNMT,RX Control Assignment" "0,1"
|
|
bitfld.long 0x0 30. "RXFLUSH,RX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMARXENA,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXTRIG,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "TXASGNMT,TX Control Assignment" "0,1"
|
|
bitfld.long 0x0 14. "TXFLUSH,TX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMATXENA,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xF08++0x3
|
|
line.long 0x0 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x0 18. "RXABVTRIG,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x0 17. "RXFF,RX FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXFE,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x0 2. "TXBLWTRIG,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFF,TX FIFO Full" "0,1"
|
|
bitfld.long 0x0 0. "TXFE,TX FIFO Empty" "0,1"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2CMSA,I2C Master Slave Address"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SA,I2C Slave Address"
|
|
bitfld.long 0x0 0. "RS,Receive/Send" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CLKTO,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x0 6. "BUSBSY,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDLE,I2C Idle" "0,1"
|
|
bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0,1"
|
|
bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERROR,Error" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,I2C Busy" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "I2CMDR,I2C Master Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data transmitted/received"
|
|
line.long 0x4 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x4 16.--18. "PULSEL,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "HS,High-Speed Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period"
|
|
line.long 0x8 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x8 11. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 10. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 8. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ARBLOSTIM,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 6. "STOPIM,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "STARTIM,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 4. "NACKIM,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 2. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CLKIM,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 0. "IM,Master Interrupt Mask" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x0 11. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTRIS,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "STOPRIS,STOP Detection Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTRIS,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "NACKRIS,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRIS,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RIS,Master Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x4 11. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "TXMIS,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLOSTMIS,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 6. "STOPMIS,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "STARTMIS,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "NACKMIS,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMATXMIS,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DMARXMIS,Receive DMA Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLKMIS,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "MIS,Masked Interrupt Status" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x0 11. "RXFFIC,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "TXFEIC,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXIC,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "TXIC,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTIC,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "STOPIC,STOP Detection Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTIC,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKIC,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKIC,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "IC,Master Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x4 5. "SFE,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x4 4. "MFE,I2C Master Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPBK,I2C Loopback" "0,1"
|
|
line.long 0x8 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "SDA,I2C SDA Status" "0,1"
|
|
bitfld.long 0x0 0. "SCL,I2C SCL Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "I2CSOAR,I2C Slave Own Address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OAR,I2C Slave Own Address"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x0 4. "QCMDST,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x0 2. "FBR,First Byte Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TREQ,Transmit Request" "0,1"
|
|
bitfld.long 0x0 0. "RREQ,Receive Request" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "I2CSDR,I2C Slave Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data for Transfer"
|
|
line.long 0x4 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x4 8. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPIM,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "STARTIM,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAIM,Data Interrupt Mask" "0,1"
|
|
rgroup.long 0x810++0x7
|
|
line.long 0x0 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x0 8. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPRIS,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "STARTRIS,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATARIS,Data Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x4 8. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPMIS,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "STARTMIS,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAMIS,Data Masked Interrupt Status" "0,1"
|
|
group.long 0x818++0xB
|
|
line.long 0x0 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x0 8. "RXFFIC,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXFEIC,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXIC,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPIC,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "STARTIC,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATAIC,Data Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x8 1. "ACKOVAL,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x8 0. "ACKOEN,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long 0xF04++0x3
|
|
line.long 0x0 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x0 31. "RXASGNMT,RX Control Assignment" "0,1"
|
|
bitfld.long 0x0 30. "RXFLUSH,RX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMARXENA,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXTRIG,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "TXASGNMT,TX Control Assignment" "0,1"
|
|
bitfld.long 0x0 14. "TXFLUSH,TX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMATXENA,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xF08++0x3
|
|
line.long 0x0 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x0 18. "RXABVTRIG,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x0 17. "RXFF,RX FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXFE,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x0 2. "TXBLWTRIG,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFF,TX FIFO Full" "0,1"
|
|
bitfld.long 0x0 0. "TXFE,TX FIFO Empty" "0,1"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2CMSA,I2C Master Slave Address"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SA,I2C Slave Address"
|
|
bitfld.long 0x0 0. "RS,Receive/Send" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CLKTO,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x0 6. "BUSBSY,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDLE,I2C Idle" "0,1"
|
|
bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0,1"
|
|
bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERROR,Error" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,I2C Busy" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "I2CMDR,I2C Master Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data transmitted/received"
|
|
line.long 0x4 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x4 16.--18. "PULSEL,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "HS,High-Speed Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period"
|
|
line.long 0x8 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x8 11. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 10. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 8. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "ARBLOSTIM,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 6. "STOPIM,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "STARTIM,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 4. "NACKIM,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 2. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CLKIM,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x8 0. "IM,Master Interrupt Mask" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x0 11. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTRIS,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "STOPRIS,STOP Detection Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTRIS,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "NACKRIS,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRIS,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RIS,Master Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x4 11. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "TXMIS,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLOSTMIS,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 6. "STOPMIS,STOP Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "STARTMIS,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "NACKMIS,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DMATXMIS,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "DMARXMIS,Receive DMA Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CLKMIS,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "MIS,Masked Interrupt Status" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x0 11. "RXFFIC,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "TXFEIC,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXIC,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "TXIC,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ARBLOSTIC,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "STOPIC,STOP Detection Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTIC,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKIC,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKIC,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "IC,Master Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x4 5. "SFE,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x4 4. "MFE,I2C Master Function Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPBK,I2C Loopback" "0,1"
|
|
line.long 0x8 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "SDA,I2C SDA Status" "0,1"
|
|
bitfld.long 0x0 0. "SCL,I2C SCL Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "I2CSOAR,I2C Slave Own Address"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OAR,I2C Slave Own Address"
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x0 31. "ACTDMARX,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x0 30. "ACTDMATX,DMA TX Active Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x0 4. "QCMDST,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x0 2. "FBR,First Byte Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TREQ,Transmit Request" "0,1"
|
|
bitfld.long 0x0 0. "RREQ,Receive Request" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "I2CSDR,I2C Slave Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data for Transfer"
|
|
line.long 0x4 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x4 8. "RXFFIM,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXIM,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXIM,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPIM,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "STARTIM,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAIM,Data Interrupt Mask" "0,1"
|
|
rgroup.long 0x810++0x7
|
|
line.long 0x0 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x0 8. "RXFFRIS,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "TXFERIS,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXRIS,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPRIS,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "STARTRIS,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATARIS,Data Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x4 8. "RXFFMIS,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 7. "TXFEMIS,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXMIS,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "STOPMIS,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "STARTMIS,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATAMIS,Data Masked Interrupt Status" "0,1"
|
|
group.long 0x818++0xB
|
|
line.long 0x0 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x0 8. "RXFFIC,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXFEIC,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXIC,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 3. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STOPIC,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "STARTIC,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATAIC,Data Interrupt Clear" "0,1"
|
|
line.long 0x4 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x8 1. "ACKOVAL,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x8 0. "ACKOEN,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long 0xF04++0x3
|
|
line.long 0x0 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x0 31. "RXASGNMT,RX Control Assignment" "0,1"
|
|
bitfld.long 0x0 30. "RXFLUSH,RX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMARXENA,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x0 16.--18. "RXTRIG,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "TXASGNMT,TX Control Assignment" "0,1"
|
|
bitfld.long 0x0 14. "TXFLUSH,TX FIFO Flush" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMATXENA,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xF08++0x3
|
|
line.long 0x0 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x0 18. "RXABVTRIG,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x0 17. "RXFF,RX FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXFE,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x0 2. "TXBLWTRIG,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFF,TX FIFO Full" "0,1"
|
|
bitfld.long 0x0 0. "TXFE,TX FIFO Empty" "0,1"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x0 0. "HS,High-Speed Capable" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM")||cpuis("F2838?D")||cpuis("F2838?D-CM"))
|
|
tree "IPC (Interprocessor Communication)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "IpcCPU1toCM"
|
|
base d:0x5CE40
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CPU1TOCMIPCACK,CPU1TOCMIPCACK Register"
|
|
bitfld.long 0x0 31. "IPC31,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC28 bit" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC24 bit" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC23 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC20 bit" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC16 bit" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC14 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC12 bit" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC8 bit" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC5 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC4 bit" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long 0x2++0x3
|
|
line.long 0x0 "CMTOCPU1IPCSTS,CMTOCPU1IPCSTS Register"
|
|
bitfld.long 0x0 31. "IPC31,IPC31 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,IPC30 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,IPC29 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,IPC28 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,IPC27 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,IPC26 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,IPC25 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,IPC24 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,IPC23 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,IPC22 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,IPC21 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,IPC20 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,IPC19 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,IPC18 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,IPC17 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,IPC16 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,IPC15 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,IPC14 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,IPC13 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,IPC12 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,IPC11 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,IPC10 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,IPC9 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,IPC8 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,IPC7 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,IPC6 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,IPC5 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,IPC4 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,IPC3 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,IPC2 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,IPC1 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,IPC0 Request from CPU1 to CM" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "CPU1TOCMIPCSET,CPU1TOCMIPCSET Register"
|
|
bitfld.long 0x0 31. "IPC31,Set CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Set CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Set CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Set CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Set CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Set CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Set CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Set CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Set CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Set CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Set CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Set CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Set CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Set CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Set CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Set CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Set CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Set CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Set CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Set CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Set CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Set CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Set CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Set CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Set CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Set CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Set CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Set CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Set CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Set CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Set CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Set CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
line.long 0x2 "CPU1TOCMIPCCLR,CPU1TOCMIPCCLR Register"
|
|
bitfld.long 0x2 31. "IPC31,Clear CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x2 30. "IPC30,Clear CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x2 29. "IPC29,Clear CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x2 28. "IPC28,Clear CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x2 27. "IPC27,Clear CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x2 26. "IPC26,Clear CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x2 25. "IPC25,Clear CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x2 24. "IPC24,Clear CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x2 23. "IPC23,Clear CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 22. "IPC22,Clear CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x2 21. "IPC21,Clear CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x2 20. "IPC20,Clear CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x2 19. "IPC19,Clear CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x2 18. "IPC18,Clear CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x2 17. "IPC17,Clear CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x2 16. "IPC16,Clear CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x2 15. "IPC15,Clear CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x2 14. "IPC14,Clear CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 13. "IPC13,Clear CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x2 12. "IPC12,Clear CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x2 11. "IPC11,Clear CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x2 10. "IPC10,Clear CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x2 9. "IPC9,Clear CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x2 8. "IPC8,Clear CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x2 7. "IPC7,Clear CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x2 6. "IPC6,Clear CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x2 5. "IPC5,Clear CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 4. "IPC4,Clear CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x2 3. "IPC3,Clear CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x2 2. "IPC2,Clear CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x2 1. "IPC1,Clear CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x2 0. "IPC0,Clear CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long 0x8++0x17
|
|
line.long 0x0 "CPU1TOCMIPCFLG,CPU1TOCMIPCFLG Register"
|
|
bitfld.long 0x0 31. "IPC31,CM to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,CM to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,CM to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,CM to CPU1 IPC28 Flag Status" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,CM to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,CM to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,CM to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,CM to CPU1 IPC24 Flag Status" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,CM to CPU1 IPC23 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,CM to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,CM to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,CM to CPU1 IPC20 Flag Status" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,CM to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,CM to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,CM to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,CM to CPU1 IPC16 Flag Status" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,CM to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,CM to CPU1 IPC14 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,CM to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,CM to CPU1 IPC12 Flag Status" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,CM to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,CM to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,CM to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,CM to CPU1 IPC8 Flag Status" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,CM to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,CM to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,CM to CPU1 IPC5 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,CM to CPU1 IPC4 Flag Status" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,CM to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,CM to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,CM to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,CM to CPU1 IPC0 Flag Status" "0,1"
|
|
line.long 0x4 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,IPC Counter's lower 32-bit"
|
|
line.long 0x6 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
hexmask.long 0x6 0.--31. 1. "COUNT,IPC Counter's upper 32-bit"
|
|
line.long 0x8 "CPU1TOCMIPCSENDCOM,CPU1TOCMIPCSENDCOM Register"
|
|
hexmask.long 0x8 0.--31. 1. "COMMAND,Refelects the state of CPU1TOCMIPCSENDCOM register"
|
|
line.long 0xA "CPU1TOCMIPCSENDADDR,CPU1TOCMIPCSENDADDR Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDRESS,Refelects the state of CPU1TOCMIPCSENDADDR register"
|
|
line.long 0xC "CPU1TOCMIPCSENDDATA,CPU1TOCMIPCSENDDATA Register"
|
|
hexmask.long 0xC 0.--31. 1. "WDATA,Refelects the state of CPU1TOCMIPCSENDDATA register"
|
|
group.long 0x16++0x1B
|
|
line.long 0x0 "CMTOCPU1IPCREPLY,CMTOCPU1IPCREPLY Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,CM to CPU1 IPC Reply"
|
|
line.long 0x2 "CMTOCPU1IPCRECVCOM,CMTOCPU1IPCRECVCOM Register"
|
|
hexmask.long 0x2 0.--31. 1. "COMMAND,CM to CPU1 IPC Command"
|
|
line.long 0x4 "CMTOCPU1IPCRECVADDR,CMTOCPU1IPCRECVADDR Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,CM to CPU1 IPC Address"
|
|
line.long 0x6 "CMTOCPU1IPCRECVDATA,CMTOCPU1IPCRECVDATA Register"
|
|
hexmask.long 0x6 0.--31. 1. "WDATA,CM to CPU1 IPC Data"
|
|
line.long 0x8 "CPU1TOCMIPCREPLY,CPU1TOCMIPCREPLY Register"
|
|
hexmask.long 0x8 0.--31. 1. "RDATA,CPU1 to CM IPC Reply"
|
|
line.long 0xA "CMTOCPU1IPCBOOTSTS,CMTOCPU1IPCBOOTSTS Register"
|
|
hexmask.long 0xA 0.--31. 1. "BOOTSTS,CM to CPU1 IPC Boot Status"
|
|
line.long 0xC "CPU1TOCMIPCBOOTMODE,CPU1TOCMIPCBOOTMODE Register"
|
|
hexmask.long 0xC 0.--31. 1. "BOOTMODE,CPU1 to CM IPC Boot Mode."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "IpcCMtoCPU1"
|
|
base d:0x400FD000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CMTOCPU1IPCACK,CMTOCPU1IPCACK Register"
|
|
bitfld.long 0x0 31. "IPC31,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC28 bit" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC24 bit" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC23 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC20 bit" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC16 bit" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC14 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC12 bit" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC8 bit" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC5 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC4 bit" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CPU1TOCMIPCSTS,CPU1TOCMIPCSTS Register"
|
|
bitfld.long 0x0 31. "IPC31,IPC31 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,IPC30 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,IPC29 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,IPC28 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,IPC27 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,IPC26 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,IPC25 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,IPC24 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,IPC23 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,IPC22 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,IPC21 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,IPC20 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,IPC19 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,IPC18 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,IPC17 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,IPC16 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,IPC15 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,IPC14 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,IPC13 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,IPC12 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,IPC11 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,IPC10 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,IPC9 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,IPC8 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,IPC7 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,IPC6 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,IPC5 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,IPC4 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,IPC3 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,IPC2 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,IPC1 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,IPC0 Request from CPU1 to CM" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CMTOCPU1IPCSET,CMTOCPU1IPCSET Register"
|
|
bitfld.long 0x0 31. "IPC31,Set CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Set CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Set CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Set CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Set CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Set CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Set CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Set CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Set CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Set CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Set CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Set CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Set CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Set CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Set CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Set CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Set CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Set CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Set CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Set CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Set CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Set CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Set CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Set CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Set CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Set CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Set CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Set CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Set CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Set CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Set CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Set CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
line.long 0x4 "CMTOCPU1IPCCLR,CMTOCPU1IPCCLR Register"
|
|
bitfld.long 0x4 31. "IPC31,Clear CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x4 30. "IPC30,Clear CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x4 29. "IPC29,Clear CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x4 28. "IPC28,Clear CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x4 27. "IPC27,Clear CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x4 26. "IPC26,Clear CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x4 25. "IPC25,Clear CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x4 24. "IPC24,Clear CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x4 23. "IPC23,Clear CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "IPC22,Clear CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x4 21. "IPC21,Clear CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x4 20. "IPC20,Clear CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x4 19. "IPC19,Clear CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x4 18. "IPC18,Clear CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x4 17. "IPC17,Clear CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x4 16. "IPC16,Clear CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x4 15. "IPC15,Clear CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x4 14. "IPC14,Clear CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "IPC13,Clear CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x4 12. "IPC12,Clear CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x4 11. "IPC11,Clear CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x4 10. "IPC10,Clear CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x4 9. "IPC9,Clear CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x4 8. "IPC8,Clear CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x4 7. "IPC7,Clear CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x4 6. "IPC6,Clear CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x4 5. "IPC5,Clear CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "IPC4,Clear CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x4 3. "IPC3,Clear CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x4 2. "IPC2,Clear CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x4 1. "IPC1,Clear CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x4 0. "IPC0,Clear CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CMTOCPU1IPCFLG,CMTOCPU1IPCFLG Register"
|
|
bitfld.long 0x0 31. "IPC31,CM to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,CM to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,CM to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,CM to CPU1 IPC28 Flag Status" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,CM to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,CM to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,CM to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,CM to CPU1 IPC24 Flag Status" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,CM to CPU1 IPC23 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,CM to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,CM to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,CM to CPU1 IPC20 Flag Status" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,CM to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,CM to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,CM to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,CM to CPU1 IPC16 Flag Status" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,CM to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,CM to CPU1 IPC14 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,CM to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,CM to CPU1 IPC12 Flag Status" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,CM to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,CM to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,CM to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,CM to CPU1 IPC8 Flag Status" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,CM to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,CM to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,CM to CPU1 IPC5 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,CM to CPU1 IPC4 Flag Status" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,CM to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,CM to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,CM to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,CM to CPU1 IPC0 Flag Status" "0,1"
|
|
rgroup.long 0x18++0x13
|
|
line.long 0x0 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,IPC Counter's lower 32-bit"
|
|
line.long 0x4 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,IPC Counter's upper 32-bit"
|
|
line.long 0x8 "CPU1TOCMIPCRECVCOM,CPU1TOCMIPCRECVCOM Register"
|
|
hexmask.long 0x8 0.--31. 1. "COMMAND,Refelects the state of CPU1TOCMIPCSENDCOM register"
|
|
line.long 0xC "CPU1TOCMIPCRECVADDR,CPU1TOCMIPCRECVADDR Register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRESS,Refelects the state of CPU1TOCMIPCSENDADDR register"
|
|
line.long 0x10 "CPU1TOCMIPCRECVDATA,CPU1TOCMIPCRECVDATA Register"
|
|
hexmask.long 0x10 0.--31. 1. "WDATA,Refelects the state of CPU1TOCMIPCSENDDATA register"
|
|
group.long 0x2C++0x1F
|
|
line.long 0x0 "CMTOCPU1IPCREPLY,CMTOCPU1IPCREPLY Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,CM to CPU1 IPC Reply"
|
|
line.long 0x4 "CMTOCPU1IPCSENDCOM,CMTOCPU1IPCSENDCOM Register"
|
|
hexmask.long 0x4 0.--31. 1. "COMMAND,CM to CPU1 IPC Command"
|
|
line.long 0x8 "CMTOCPU1IPCSENDADDR,CMTOCPU1IPCSENDADDR Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDRESS,CM to CPU1 IPC Address"
|
|
line.long 0xC "CMTOCPU1IPCSENDDATA,CMTOCPU1IPCSENDDATA Register"
|
|
hexmask.long 0xC 0.--31. 1. "WDATA,CM to CPU1 IPC Data"
|
|
line.long 0x10 "CPU1TOCMIPCREPLY,CPU1TOCMIPCREPLY Register"
|
|
hexmask.long 0x10 0.--31. 1. "RDATA,CPU1 to CM IPC Reply"
|
|
line.long 0x14 "CMTOCPU1IPCBOOTSTS,CMTOCPU1IPCBOOTSTS Register"
|
|
hexmask.long 0x14 0.--31. 1. "BOOTSTS,CM to CPU1 IPC Boot Status"
|
|
line.long 0x18 "CPU1TOCMIPCBOOTMODE,CPU1TOCMIPCBOOTMODE Register"
|
|
hexmask.long 0x18 0.--31. 1. "BOOTMODE,CPU1 to CM IPC Boot Mode."
|
|
line.long 0x1C "PUMPREQUEST,PUMPREQUEST Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x1C 0.--1. "SEM,Flash Pump Request Semaphore between CPU1 CPU2 and CM" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838?D"))
|
|
tree "IpcCPU1toCPU2"
|
|
base d:0x5CE00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CPU1TOCPU2IPCACK,CPU1TOCPU2IPCACK Register"
|
|
bitfld.long 0x0 31. "IPC31,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC28 bit" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC24 bit" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC23 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC20 bit" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC16 bit" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC14 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC12 bit" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC8 bit" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC5 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC4 bit" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long 0x2++0x3
|
|
line.long 0x0 "CPU2TOCPU1IPCSTS,CPU2TOCPU1IPCSTS Register"
|
|
bitfld.long 0x0 31. "IPC31,IPC31 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,IPC30 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,IPC29 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,IPC28 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,IPC27 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,IPC26 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,IPC25 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,IPC24 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,IPC23 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,IPC22 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,IPC21 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,IPC20 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,IPC19 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,IPC18 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,IPC17 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,IPC16 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,IPC15 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,IPC14 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,IPC13 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,IPC12 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,IPC11 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,IPC10 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,IPC9 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,IPC8 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,IPC7 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,IPC6 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,IPC5 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,IPC4 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,IPC3 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,IPC2 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,IPC1 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,IPC0 Request from CPU1 to CPU2" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "CPU1TOCPU2IPCSET,CPU1TOCPU2IPCSET Register"
|
|
bitfld.long 0x0 31. "IPC31,Set CPU2TOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Set CPU2TOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Set CPU2TOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Set CPU2TOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Set CPU2TOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Set CPU2TOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Set CPU2TOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Set CPU2TOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Set CPU2TOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Set CPU2TOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Set CPU2TOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Set CPU2TOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Set CPU2TOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Set CPU2TOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Set CPU2TOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Set CPU2TOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Set CPU2TOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Set CPU2TOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Set CPU2TOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Set CPU2TOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Set CPU2TOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Set CPU2TOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Set CPU2TOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Set CPU2TOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Set CPU2TOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Set CPU2TOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Set CPU2TOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Set CPU2TOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Set CPU2TOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Set CPU2TOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Set CPU2TOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Set CPU2TOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
line.long 0x2 "CPU1TOCPU2IPCCLR,CPU1TOCPU2IPCCLR Register"
|
|
bitfld.long 0x2 31. "IPC31,Clear CPU2TOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x2 30. "IPC30,Clear CPU2TOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x2 29. "IPC29,Clear CPU2TOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x2 28. "IPC28,Clear CPU2TOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x2 27. "IPC27,Clear CPU2TOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x2 26. "IPC26,Clear CPU2TOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x2 25. "IPC25,Clear CPU2TOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x2 24. "IPC24,Clear CPU2TOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x2 23. "IPC23,Clear CPU2TOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 22. "IPC22,Clear CPU2TOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x2 21. "IPC21,Clear CPU2TOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x2 20. "IPC20,Clear CPU2TOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x2 19. "IPC19,Clear CPU2TOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x2 18. "IPC18,Clear CPU2TOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x2 17. "IPC17,Clear CPU2TOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x2 16. "IPC16,Clear CPU2TOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x2 15. "IPC15,Clear CPU2TOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x2 14. "IPC14,Clear CPU2TOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 13. "IPC13,Clear CPU2TOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x2 12. "IPC12,Clear CPU2TOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x2 11. "IPC11,Clear CPU2TOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x2 10. "IPC10,Clear CPU2TOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x2 9. "IPC9,Clear CPU2TOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x2 8. "IPC8,Clear CPU2TOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x2 7. "IPC7,Clear CPU2TOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x2 6. "IPC6,Clear CPU2TOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x2 5. "IPC5,Clear CPU2TOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 4. "IPC4,Clear CPU2TOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x2 3. "IPC3,Clear CPU2TOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x2 2. "IPC2,Clear CPU2TOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x2 1. "IPC1,Clear CPU2TOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x2 0. "IPC0,Clear CPU2TOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long 0x8++0x17
|
|
line.long 0x0 "CPU1TOCPU2IPCFLG,CPU1TOCPU2IPCFLG Register"
|
|
bitfld.long 0x0 31. "IPC31,CPU2 to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,CPU2 to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,CPU2 to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,CPU2 to CPU1 IPC28 Flag Status" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,CPU2 to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,CPU2 to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,CPU2 to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,CPU2 to CPU1 IPC24 Flag Status" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,CPU2 to CPU1 IPC23 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,CPU2 to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,CPU2 to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,CPU2 to CPU1 IPC20 Flag Status" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,CPU2 to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,CPU2 to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,CPU2 to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,CPU2 to CPU1 IPC16 Flag Status" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,CPU2 to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,CPU2 to CPU1 IPC14 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,CPU2 to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,CPU2 to CPU1 IPC12 Flag Status" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,CPU2 to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,CPU2 to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,CPU2 to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,CPU2 to CPU1 IPC8 Flag Status" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,CPU2 to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,CPU2 to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,CPU2 to CPU1 IPC5 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,CPU2 to CPU1 IPC4 Flag Status" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,CPU2 to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,CPU2 to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,CPU2 to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,CPU2 to CPU1 IPC0 Flag Status" "0,1"
|
|
line.long 0x4 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,IPC Counter's lower 32-bit"
|
|
line.long 0x6 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
hexmask.long 0x6 0.--31. 1. "COUNT,IPC Counter's upper 32-bit"
|
|
line.long 0x8 "CPU1TOCPU2IPCSENDCOM,CPU1TOCPU2IPCSENDCOM Register"
|
|
hexmask.long 0x8 0.--31. 1. "COMMAND,Refelects the state of CPU1TOCPU2IPCSENDCOM register"
|
|
line.long 0xA "CPU1TOCPU2IPCSENDADDR,CPU1TOCPU2IPCSENDADDR Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDRESS,Refelects the state of CPU1TOCPU2IPCSENDADDR register"
|
|
line.long 0xC "CPU1TOCPU2IPCSENDDATA,CPU1TOCPU2IPCSENDDATA Register"
|
|
hexmask.long 0xC 0.--31. 1. "WDATA,Refelects the state of CPU1TOCPU2IPCSENDDATA register"
|
|
group.long 0x16++0x1F
|
|
line.long 0x0 "CPU2TOCPU1IPCREPLY,CPU2TOCPU1IPCREPLY Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,CPU2 to CPU1 IPC Reply"
|
|
line.long 0x2 "CPU2TOCPU1IPCRECVCOM,CPU2TOCPU1IPCRECVCOM Register"
|
|
hexmask.long 0x2 0.--31. 1. "COMMAND,CPU2 to CPU1 IPC Command"
|
|
line.long 0x4 "CPU2TOCPU1IPCRECVADDR,CPU2TOCPU1IPCRECVADDR Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,CPU2 to CPU1 IPC Address"
|
|
line.long 0x6 "CPU2TOCPU1IPCRECVDATA,CPU2TOCPU1IPCRECVDATA Register"
|
|
hexmask.long 0x6 0.--31. 1. "WDATA,CPU2 to CPU1 IPC Data"
|
|
line.long 0x8 "CPU1TOCPU2IPCREPLY,CPU1TOCPU2IPCREPLY Register"
|
|
hexmask.long 0x8 0.--31. 1. "RDATA,CPU1 to CPU2 IPC Reply"
|
|
line.long 0xA "CPU2TOCPU1IPCBOOTSTS,CPU2TOCPU1IPCBOOTSTS Register"
|
|
hexmask.long 0xA 0.--31. 1. "BOOTSTS,CPU2 to CPU1 IPC Boot Status"
|
|
line.long 0xC "CPU1TOCPU2IPCBOOTMODE,CPU1TOCPU2IPCBOOTMODE Register"
|
|
hexmask.long 0xC 0.--31. 1. "BOOTMODE,CPU1 to CPU2 IPC Boot Mode."
|
|
line.long 0xE "PUMPREQUEST,PUMPREQUEST Register"
|
|
hexmask.long.word 0xE 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0xE 0.--1. "SEM,Flash Pump Request Semaphore between CPU1 CPU2 and CM" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838?D"))
|
|
tree "IpcCPU2toCPU1"
|
|
base d:0x5CE00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CPU2TOCPU1IPCACK,CPU2TOCPU1IPCACK Register"
|
|
bitfld.long 0x0 31. "IPC31,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC28 bit" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC24 bit" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC23 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC20 bit" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC16 bit" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC14 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC12 bit" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC8 bit" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC5 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC4 bit" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long 0x2++0x3
|
|
line.long 0x0 "CPU1TOCPU2IPCSTS,CPU1TOCPU2IPCSTS Register"
|
|
bitfld.long 0x0 31. "IPC31,IPC31 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,IPC30 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,IPC29 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,IPC28 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,IPC27 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,IPC26 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,IPC25 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,IPC24 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,IPC23 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,IPC22 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,IPC21 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,IPC20 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,IPC19 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,IPC18 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,IPC17 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,IPC16 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,IPC15 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,IPC14 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,IPC13 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,IPC12 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,IPC11 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,IPC10 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,IPC9 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,IPC8 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,IPC7 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,IPC6 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,IPC5 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,IPC4 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,IPC3 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,IPC2 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,IPC1 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,IPC0 Request from CPU1 to CPU2" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "CPU2TOCPU1IPCSET,CPU2TOCPU1IPCSET Register"
|
|
bitfld.long 0x0 31. "IPC31,Set CPU2TOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Set CPU2TOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Set CPU2TOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Set CPU2TOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Set CPU2TOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Set CPU2TOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Set CPU2TOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Set CPU2TOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Set CPU2TOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,Set CPU2TOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,Set CPU2TOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Set CPU2TOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Set CPU2TOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Set CPU2TOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Set CPU2TOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Set CPU2TOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Set CPU2TOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Set CPU2TOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,Set CPU2TOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Set CPU2TOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,Set CPU2TOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Set CPU2TOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Set CPU2TOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Set CPU2TOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Set CPU2TOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Set CPU2TOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Set CPU2TOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,Set CPU2TOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Set CPU2TOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Set CPU2TOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,Set CPU2TOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Set CPU2TOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
line.long 0x2 "CPU2TOCPU1IPCCLR,CPU2TOCPU1IPCCLR Register"
|
|
bitfld.long 0x2 31. "IPC31,Clear CPU2TOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x2 30. "IPC30,Clear CPU2TOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x2 29. "IPC29,Clear CPU2TOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x2 28. "IPC28,Clear CPU2TOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x2 27. "IPC27,Clear CPU2TOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x2 26. "IPC26,Clear CPU2TOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x2 25. "IPC25,Clear CPU2TOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x2 24. "IPC24,Clear CPU2TOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x2 23. "IPC23,Clear CPU2TOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 22. "IPC22,Clear CPU2TOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x2 21. "IPC21,Clear CPU2TOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x2 20. "IPC20,Clear CPU2TOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x2 19. "IPC19,Clear CPU2TOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x2 18. "IPC18,Clear CPU2TOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x2 17. "IPC17,Clear CPU2TOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x2 16. "IPC16,Clear CPU2TOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x2 15. "IPC15,Clear CPU2TOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x2 14. "IPC14,Clear CPU2TOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 13. "IPC13,Clear CPU2TOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x2 12. "IPC12,Clear CPU2TOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
bitfld.long 0x2 11. "IPC11,Clear CPU2TOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x2 10. "IPC10,Clear CPU2TOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x2 9. "IPC9,Clear CPU2TOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x2 8. "IPC8,Clear CPU2TOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x2 7. "IPC7,Clear CPU2TOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x2 6. "IPC6,Clear CPU2TOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x2 5. "IPC5,Clear CPU2TOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 4. "IPC4,Clear CPU2TOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x2 3. "IPC3,Clear CPU2TOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x2 2. "IPC2,Clear CPU2TOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x2 1. "IPC1,Clear CPU2TOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x2 0. "IPC0,Clear CPU2TOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long 0x8++0x17
|
|
line.long 0x0 "CPU2TOCPU1IPCFLG,CPU2TOCPU1IPCFLG Register"
|
|
bitfld.long 0x0 31. "IPC31,CPU2 to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,CPU2 to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,CPU2 to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,CPU2 to CPU1 IPC28 Flag Status" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,CPU2 to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,CPU2 to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,CPU2 to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,CPU2 to CPU1 IPC24 Flag Status" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,CPU2 to CPU1 IPC23 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "IPC22,CPU2 to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x0 21. "IPC21,CPU2 to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,CPU2 to CPU1 IPC20 Flag Status" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,CPU2 to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,CPU2 to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,CPU2 to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,CPU2 to CPU1 IPC16 Flag Status" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,CPU2 to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,CPU2 to CPU1 IPC14 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "IPC13,CPU2 to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,CPU2 to CPU1 IPC12 Flag Status" "0,1"
|
|
bitfld.long 0x0 11. "IPC11,CPU2 to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,CPU2 to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,CPU2 to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,CPU2 to CPU1 IPC8 Flag Status" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,CPU2 to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,CPU2 to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,CPU2 to CPU1 IPC5 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IPC4,CPU2 to CPU1 IPC4 Flag Status" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,CPU2 to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,CPU2 to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x0 1. "IPC1,CPU2 to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,CPU2 to CPU1 IPC0 Flag Status" "0,1"
|
|
line.long 0x4 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,IPC Counter's lower 32-bit"
|
|
line.long 0x6 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
hexmask.long 0x6 0.--31. 1. "COUNT,IPC Counter's upper 32-bit"
|
|
line.long 0x8 "CPU1TOCPU2IPCRECVCOM,CPU1TOCPU2IPCRECVCOM Register"
|
|
hexmask.long 0x8 0.--31. 1. "COMMAND,Refelects the state of CPU1TOCPU2IPCRECVCOM register"
|
|
line.long 0xA "CPU1TOCPU2IPCRECVADDR,CPU1TOCPU2IPCRECVADDR Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDRESS,Refelects the state of CPU1TOCPU2IPCRECVADDR register"
|
|
line.long 0xC "CPU1TOCPU2IPCRECVDATA,CPU1TOCPU2IPCRECVDATA Register"
|
|
hexmask.long 0xC 0.--31. 1. "WDATA,Refelects the state of CPU1TOCPU2IPCRECVDATA register"
|
|
group.long 0x16++0x1F
|
|
line.long 0x0 "CPU2TOCPU1IPCREPLY,CPU2TOCPU1IPCREPLY Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,CPU2 to CPU1 IPC Reply"
|
|
line.long 0x2 "CPU2TOCPU1IPCSENDCOM,CPU2TOCPU1IPCSENDCOM Register"
|
|
hexmask.long 0x2 0.--31. 1. "COMMAND,CPU2 to CPU1 IPC Command"
|
|
line.long 0x4 "CPU2TOCPU1IPCSENDADDR,CPU2TOCPU1IPCSENDADDR Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,CPU2 to CPU1 IPC Address"
|
|
line.long 0x6 "CPU2TOCPU1IPCSENDDATA,CPU2TOCPU1IPCSENDDATA Register"
|
|
hexmask.long 0x6 0.--31. 1. "WDATA,CPU2 to CPU1 IPC Data"
|
|
line.long 0x8 "CPU1TOCPU2IPCREPLY,CPU1TOCPU2IPCREPLY Register"
|
|
hexmask.long 0x8 0.--31. 1. "RDATA,CPU1 to CPU2 IPC Reply"
|
|
line.long 0xA "CPU2TOCPU1IPCBOOTSTS,CPU2TOCPU1IPCBOOTSTS Register"
|
|
hexmask.long 0xA 0.--31. 1. "BOOTSTS,CPU2 to CPU1 IPC Boot Status"
|
|
line.long 0xC "CPU1TOCPU2IPCBOOTMODE,CPU1TOCPU2IPCBOOTMODE Register"
|
|
hexmask.long 0xC 0.--31. 1. "BOOTMODE,CPU1 to CPU2 IPC Boot Mode."
|
|
line.long 0xE "PUMPREQUEST,PUMPREQUEST Register"
|
|
hexmask.long.word 0xE 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0xE 0.--1. "SEM,Flash Pump Request Semaphore between CPU1 CPU2 and CM" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838?D"))
|
|
tree "IpcCPU2toCM"
|
|
base d:0x5CE40
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CPU2TOCMIPCACK,CPU2TOCMIPCACK Register"
|
|
bitfld.long 0x0 31. "IPC31,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC28 bit" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC24 bit" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC23 bit" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC22 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC20 bit" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC16 bit" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC14 bit" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC12 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC8 bit" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC5 bit" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC4 bit" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC2 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long 0x2++0x3
|
|
line.long 0x0 "CMTOCPU2IPCSTS,CMTOCPU2IPCSTS Register"
|
|
bitfld.long 0x0 31. "IPC31,IPC31 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,IPC30 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,IPC29 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,IPC28 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,IPC27 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,IPC26 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,IPC25 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,IPC24 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,IPC23 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,IPC22 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,IPC21 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,IPC20 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,IPC19 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,IPC18 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,IPC17 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,IPC16 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,IPC15 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,IPC14 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,IPC13 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,IPC12 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,IPC11 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,IPC10 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,IPC9 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,IPC8 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,IPC7 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,IPC6 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,IPC5 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,IPC4 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,IPC3 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,IPC2 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,IPC1 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,IPC0 Request from CPU2 to CM" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "CPU2TOCMIPCSET,CPU2TOCMIPCSET Register"
|
|
bitfld.long 0x0 31. "IPC31,Set CMTOCPU2IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Set CMTOCPU2IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Set CMTOCPU2IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Set CMTOCPU2IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Set CMTOCPU2IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Set CMTOCPU2IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Set CMTOCPU2IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Set CMTOCPU2IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Set CMTOCPU2IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,Set CMTOCPU2IPCFLG.IPC22 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,Set CMTOCPU2IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Set CMTOCPU2IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Set CMTOCPU2IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Set CMTOCPU2IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Set CMTOCPU2IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Set CMTOCPU2IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Set CMTOCPU2IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Set CMTOCPU2IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,Set CMTOCPU2IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Set CMTOCPU2IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,Set CMTOCPU2IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Set CMTOCPU2IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Set CMTOCPU2IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Set CMTOCPU2IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Set CMTOCPU2IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Set CMTOCPU2IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Set CMTOCPU2IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,Set CMTOCPU2IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Set CMTOCPU2IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Set CMTOCPU2IPCFLG.IPC2 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,Set CMTOCPU2IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Set CMTOCPU2IPCFLG.IPC0 Flag" "0,1"
|
|
line.long 0x2 "CPU2TOCMIPCCLR,CPU2TOCMIPCCLR Register"
|
|
bitfld.long 0x2 31. "IPC31,Clear CMTOCPU2IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x2 30. "IPC30,Clear CMTOCPU2IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x2 29. "IPC29,Clear CMTOCPU2IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x2 28. "IPC28,Clear CMTOCPU2IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x2 27. "IPC27,Clear CMTOCPU2IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x2 26. "IPC26,Clear CMTOCPU2IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x2 25. "IPC25,Clear CMTOCPU2IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x2 24. "IPC24,Clear CMTOCPU2IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x2 23. "IPC23,Clear CMTOCPU2IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x2 22. "IPC22,Clear CMTOCPU2IPCFLG.IPC22 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 21. "IPC21,Clear CMTOCPU2IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x2 20. "IPC20,Clear CMTOCPU2IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x2 19. "IPC19,Clear CMTOCPU2IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x2 18. "IPC18,Clear CMTOCPU2IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x2 17. "IPC17,Clear CMTOCPU2IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x2 16. "IPC16,Clear CMTOCPU2IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x2 15. "IPC15,Clear CMTOCPU2IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x2 14. "IPC14,Clear CMTOCPU2IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x2 13. "IPC13,Clear CMTOCPU2IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x2 12. "IPC12,Clear CMTOCPU2IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "IPC11,Clear CMTOCPU2IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x2 10. "IPC10,Clear CMTOCPU2IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x2 9. "IPC9,Clear CMTOCPU2IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x2 8. "IPC8,Clear CMTOCPU2IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x2 7. "IPC7,Clear CMTOCPU2IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x2 6. "IPC6,Clear CMTOCPU2IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x2 5. "IPC5,Clear CMTOCPU2IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x2 4. "IPC4,Clear CMTOCPU2IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x2 3. "IPC3,Clear CMTOCPU2IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x2 2. "IPC2,Clear CMTOCPU2IPCFLG.IPC2 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "IPC1,Clear CMTOCPU2IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x2 0. "IPC0,Clear CMTOCPU2IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long 0x8++0x17
|
|
line.long 0x0 "CPU2TOCMIPCFLG,CPU2TOCMIPCFLG Register"
|
|
bitfld.long 0x0 31. "IPC31,CM to CPU2 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,CM to CPU2 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,CM to CPU2 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,CM to CPU2 IPC28 Flag Status" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,CM to CPU2 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,CM to CPU2 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,CM to CPU2 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,CM to CPU2 IPC24 Flag Status" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,CM to CPU2 IPC23 Flag Status" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,CM to CPU2 IPC22 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,CM to CPU2 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,CM to CPU2 IPC20 Flag Status" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,CM to CPU2 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,CM to CPU2 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,CM to CPU2 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,CM to CPU2 IPC16 Flag Status" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,CM to CPU2 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,CM to CPU2 IPC14 Flag Status" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,CM to CPU2 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,CM to CPU2 IPC12 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,CM to CPU2 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,CM to CPU2 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,CM to CPU2 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,CM to CPU2 IPC8 Flag Status" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,CM to CPU2 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,CM to CPU2 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,CM to CPU2 IPC5 Flag Status" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,CM to CPU2 IPC4 Flag Status" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,CM to CPU2 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,CM to CPU2 IPC2 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,CM to CPU2 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,CM to CPU2 IPC0 Flag Status" "0,1"
|
|
line.long 0x4 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,IPC Counter's lower 32-bit"
|
|
line.long 0x6 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
hexmask.long 0x6 0.--31. 1. "COUNT,IPC Counter's upper 32-bit"
|
|
line.long 0x8 "CPU2TOCMIPCSENDCOM,CPU2TOCMIPCSENDCOM Register"
|
|
hexmask.long 0x8 0.--31. 1. "COMMAND,Refelects the state of CPU2TOCMIPCSENDCOM register"
|
|
line.long 0xA "CPU2TOCMIPCSENDADDR,CPU2TOCMIPCSENDADDR Register"
|
|
hexmask.long 0xA 0.--31. 1. "ADDRESS,Refelects the state of CPU2TOCMIPCSENDADDR register"
|
|
line.long 0xC "CPU2TOCMIPCSENDDATA,CPU2TOCMIPCSENDDATA Register"
|
|
hexmask.long 0xC 0.--31. 1. "WDATA,Refelects the state of CPU2TOCMIPCSENDDATA register"
|
|
group.long 0x16++0x13
|
|
line.long 0x0 "CMTOCPU2IPCREPLY,CMTOCPU2IPCREPLY Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,CM to CPU2 IPC Reply"
|
|
line.long 0x2 "CMTOCPU2IPCRECVCOM,CMTOCPU2IPCRECVCOM Register"
|
|
hexmask.long 0x2 0.--31. 1. "COMMAND,CM to CPU2 IPC Command"
|
|
line.long 0x4 "CMTOCPU2IPCRECVADDR,CMTOCPU2IPCRECVADDR Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,CM to CPU2 IPC Address"
|
|
line.long 0x6 "CMTOCPU2IPCRECVDATA,CMTOCPU2IPCRECVDATA Register"
|
|
hexmask.long 0x6 0.--31. 1. "WDATA,CM to CPU2 IPC Data"
|
|
line.long 0x8 "CPU2TOCMIPCREPLY,CPU2TOCMIPCREPLY Register"
|
|
hexmask.long 0x8 0.--31. 1. "RDATA,CPU2 to CM IPC Reply"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838?D-CM"))
|
|
tree "IpcCMtoCPU2"
|
|
base d:0x400FD080
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CMTOCPU2IPCACK,CMTOCPU2IPCACK Register"
|
|
bitfld.long 0x0 31. "IPC31,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC28 bit" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC24 bit" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC23 bit" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC22 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC20 bit" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC16 bit" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC14 bit" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC12 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC8 bit" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC5 bit" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC4 bit" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC2 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CPU2TOCMIPCSTS,CPU2TOCMIPCSTS Register"
|
|
bitfld.long 0x0 31. "IPC31,IPC31 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,IPC30 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,IPC29 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,IPC28 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,IPC27 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,IPC26 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,IPC25 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,IPC24 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,IPC23 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,IPC22 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,IPC21 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,IPC20 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,IPC19 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,IPC18 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,IPC17 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,IPC16 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,IPC15 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,IPC14 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,IPC13 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,IPC12 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,IPC11 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,IPC10 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,IPC9 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,IPC8 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,IPC7 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,IPC6 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,IPC5 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,IPC4 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,IPC3 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,IPC2 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,IPC1 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,IPC0 Request from CPU2 to CM" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CMTOCPU2IPCSET,CMTOCPU2IPCSET Register"
|
|
bitfld.long 0x0 31. "IPC31,Set CMTOCPU2IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,Set CMTOCPU2IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,Set CMTOCPU2IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,Set CMTOCPU2IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,Set CMTOCPU2IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,Set CMTOCPU2IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,Set CMTOCPU2IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,Set CMTOCPU2IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,Set CMTOCPU2IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,Set CMTOCPU2IPCFLG.IPC22 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,Set CMTOCPU2IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,Set CMTOCPU2IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,Set CMTOCPU2IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,Set CMTOCPU2IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,Set CMTOCPU2IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,Set CMTOCPU2IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,Set CMTOCPU2IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,Set CMTOCPU2IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,Set CMTOCPU2IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,Set CMTOCPU2IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,Set CMTOCPU2IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,Set CMTOCPU2IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,Set CMTOCPU2IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,Set CMTOCPU2IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,Set CMTOCPU2IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,Set CMTOCPU2IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,Set CMTOCPU2IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,Set CMTOCPU2IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,Set CMTOCPU2IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,Set CMTOCPU2IPCFLG.IPC2 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,Set CMTOCPU2IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,Set CMTOCPU2IPCFLG.IPC0 Flag" "0,1"
|
|
line.long 0x4 "CMTOCPU2IPCCLR,CMTOCPU2IPCCLR Register"
|
|
bitfld.long 0x4 31. "IPC31,Clear CMTOCPU2IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x4 30. "IPC30,Clear CMTOCPU2IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x4 29. "IPC29,Clear CMTOCPU2IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x4 28. "IPC28,Clear CMTOCPU2IPCFLG.IPC28 Flag" "0,1"
|
|
bitfld.long 0x4 27. "IPC27,Clear CMTOCPU2IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x4 26. "IPC26,Clear CMTOCPU2IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x4 25. "IPC25,Clear CMTOCPU2IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x4 24. "IPC24,Clear CMTOCPU2IPCFLG.IPC24 Flag" "0,1"
|
|
bitfld.long 0x4 23. "IPC23,Clear CMTOCPU2IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x4 22. "IPC22,Clear CMTOCPU2IPCFLG.IPC22 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "IPC21,Clear CMTOCPU2IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x4 20. "IPC20,Clear CMTOCPU2IPCFLG.IPC20 Flag" "0,1"
|
|
bitfld.long 0x4 19. "IPC19,Clear CMTOCPU2IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x4 18. "IPC18,Clear CMTOCPU2IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x4 17. "IPC17,Clear CMTOCPU2IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x4 16. "IPC16,Clear CMTOCPU2IPCFLG.IPC16 Flag" "0,1"
|
|
bitfld.long 0x4 15. "IPC15,Clear CMTOCPU2IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x4 14. "IPC14,Clear CMTOCPU2IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x4 13. "IPC13,Clear CMTOCPU2IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x4 12. "IPC12,Clear CMTOCPU2IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "IPC11,Clear CMTOCPU2IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x4 10. "IPC10,Clear CMTOCPU2IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x4 9. "IPC9,Clear CMTOCPU2IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x4 8. "IPC8,Clear CMTOCPU2IPCFLG.IPC8 Flag" "0,1"
|
|
bitfld.long 0x4 7. "IPC7,Clear CMTOCPU2IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x4 6. "IPC6,Clear CMTOCPU2IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x4 5. "IPC5,Clear CMTOCPU2IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x4 4. "IPC4,Clear CMTOCPU2IPCFLG.IPC4 Flag" "0,1"
|
|
bitfld.long 0x4 3. "IPC3,Clear CMTOCPU2IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x4 2. "IPC2,Clear CMTOCPU2IPCFLG.IPC2 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "IPC1,Clear CMTOCPU2IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x4 0. "IPC0,Clear CMTOCPU2IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CMTOCPU2IPCFLG,CMTOCPU2IPCFLG Register"
|
|
bitfld.long 0x0 31. "IPC31,CM to CPU2 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x0 30. "IPC30,CM to CPU2 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x0 29. "IPC29,CM to CPU2 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x0 28. "IPC28,CM to CPU2 IPC28 Flag Status" "0,1"
|
|
bitfld.long 0x0 27. "IPC27,CM to CPU2 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x0 26. "IPC26,CM to CPU2 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x0 25. "IPC25,CM to CPU2 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x0 24. "IPC24,CM to CPU2 IPC24 Flag Status" "0,1"
|
|
bitfld.long 0x0 23. "IPC23,CM to CPU2 IPC23 Flag Status" "0,1"
|
|
bitfld.long 0x0 22. "IPC22,CM to CPU2 IPC22 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IPC21,CM to CPU2 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x0 20. "IPC20,CM to CPU2 IPC20 Flag Status" "0,1"
|
|
bitfld.long 0x0 19. "IPC19,CM to CPU2 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x0 18. "IPC18,CM to CPU2 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x0 17. "IPC17,CM to CPU2 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x0 16. "IPC16,CM to CPU2 IPC16 Flag Status" "0,1"
|
|
bitfld.long 0x0 15. "IPC15,CM to CPU2 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x0 14. "IPC14,CM to CPU2 IPC14 Flag Status" "0,1"
|
|
bitfld.long 0x0 13. "IPC13,CM to CPU2 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x0 12. "IPC12,CM to CPU2 IPC12 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IPC11,CM to CPU2 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x0 10. "IPC10,CM to CPU2 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x0 9. "IPC9,CM to CPU2 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x0 8. "IPC8,CM to CPU2 IPC8 Flag Status" "0,1"
|
|
bitfld.long 0x0 7. "IPC7,CM to CPU2 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x0 6. "IPC6,CM to CPU2 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "IPC5,CM to CPU2 IPC5 Flag Status" "0,1"
|
|
bitfld.long 0x0 4. "IPC4,CM to CPU2 IPC4 Flag Status" "0,1"
|
|
bitfld.long 0x0 3. "IPC3,CM to CPU2 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x0 2. "IPC2,CM to CPU2 IPC2 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IPC1,CM to CPU2 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x0 0. "IPC0,CM to CPU2 IPC0 Flag Status" "0,1"
|
|
rgroup.long 0x18++0x13
|
|
line.long 0x0 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,IPC Counter's lower 32-bit"
|
|
line.long 0x4 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,IPC Counter's upper 32-bit"
|
|
line.long 0x8 "CPU2TOCMIPCRECVCOM,CPU2TOCMIPCRECVCOM Register"
|
|
hexmask.long 0x8 0.--31. 1. "COMMAND,Refelects the state of CPU2TOCMIPCSENDCOM register"
|
|
line.long 0xC "CPU2TOCMIPCRECVADDR,CPU2TOCMIPCRECVADDR Register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRESS,Refelects the state of CPU2TOCMIPCSENDADDR register"
|
|
line.long 0x10 "CPU2TOCMIPCRECVDATA,CPU2TOCMIPCRECVDATA Register"
|
|
hexmask.long 0x10 0.--31. 1. "WDATA,Refelects the state of CPU2TOCMIPCSENDDATA register"
|
|
group.long 0x2C++0x13
|
|
line.long 0x0 "CMTOCPU2IPCREPLY,CMTOCPU2IPCREPLY Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDATA,CM to CPU2 IPC Reply"
|
|
line.long 0x4 "CMTOCPU2IPCSENDCOM,CMTOCPU2IPCSENDCOM Register"
|
|
hexmask.long 0x4 0.--31. 1. "COMMAND,CM to CPU2 IPC Command"
|
|
line.long 0x8 "CMTOCPU2IPCSENDADDR,CMTOCPU2IPCSENDADDR Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDRESS,CM to CPU2 IPC Address"
|
|
line.long 0xC "CMTOCPU2IPCSENDDATA,CMTOCPU2IPCSENDDATA Register"
|
|
hexmask.long 0xC 0.--31. 1. "WDATA,CM to CPU2 IPC Data"
|
|
line.long 0x10 "CPU2TOCMIPCREPLY,CPU2TOCMIPCREPLY Register"
|
|
hexmask.long 0x10 0.--31. 1. "RDATA,CPU2 to CM IPC Reply"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??")||cpuis("F2838??-CM"))
|
|
tree "MCAN (Modular Controller Area Network)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "MCAN"
|
|
base d:0x5C600
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "MCAN_CREL,MCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "MCAN_ENDN,MCAN Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianess Test Value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Resynchronization Jump Width"
|
|
line.long 0x4 "MCAN_TEST,MCAN Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1"
|
|
line.long 0x8 "MCAN_RWD,MCAN RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "MCAN_CCCR,MCAN CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non-ISO Operation" "0,1"
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1"
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering During Bus Integration" "0,1"
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1"
|
|
bitfld.long 0xC 8. "FDOE,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1"
|
|
rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0,1"
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0,1"
|
|
line.long 0x10 "MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x14 "MCAN_TSCC,MCAN Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
|
|
line.long 0x18 "MCAN_TSCV,MCAN Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
|
|
line.long 0x1C "MCAN_TOCC,MCAN Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
line.long 0x20 "MCAN_TOCV,MCAN Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "MCAN_ECR,MCAN Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "MCAN_PSR,MCAN Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message" "0,1"
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "ACT,Node Activity" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCAN_TDCR,MCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "MCAN_IR,MCAN Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message Stored to Dedicated Rx Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1"
|
|
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "MCAN_IE,MCAN Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1"
|
|
bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Enable" "0,1"
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Enable" "0,1"
|
|
bitfld.long 0x4 19. "DRXE,Message Stored to Dedicated Rx Buffer Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1"
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Enable" "0,1"
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1"
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Enable" "0,1"
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Enable" "0,1"
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Enable" "0,1"
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Enable" "0,1"
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1"
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Enable" "0,1"
|
|
line.long 0x8 "MCAN_ILS,MCAN Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Line" "0,1"
|
|
bitfld.long 0x8 23. "EPL,Error Passive Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Line" "0,1"
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Line" "0,1"
|
|
bitfld.long 0x8 19. "DRXL,Message Stored to Dedicated Rx Buffer Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Line" "0,1"
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Line" "0,1"
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Line" "0,1"
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Line" "0,1"
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Line" "0,1"
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Line" "0,1"
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Line" "0,1"
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Line" "0,1"
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Line" "0,1"
|
|
line.long 0xC "MCAN_ILE,MCAN Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "MCAN_GFC,MCAN Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "MCAN_SIDFC,MCAN Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "MCAN_XIDFC,MCAN Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "MCAN_XIDAM,MCAN Extended ID and Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "MCAN_HPMS,MCAN High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "MCAN_NDAT1,MCAN New Data 1"
|
|
bitfld.long 0x0 31. "ND31,New Data RX Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data RX Buffer 30" "0,1"
|
|
bitfld.long 0x0 29. "ND29,New Data RX Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data RX Buffer 28" "0,1"
|
|
bitfld.long 0x0 27. "ND27,New Data RX Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data RX Buffer 26" "0,1"
|
|
bitfld.long 0x0 25. "ND25,New Data RX Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data RX Buffer 24" "0,1"
|
|
bitfld.long 0x0 23. "ND23,New Data RX Buffer 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "ND22,New Data RX Buffer 22" "0,1"
|
|
bitfld.long 0x0 21. "ND21,New Data RX Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data RX Buffer 20" "0,1"
|
|
bitfld.long 0x0 19. "ND19,New Data RX Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data RX Buffer 18" "0,1"
|
|
bitfld.long 0x0 17. "ND17,New Data RX Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data RX Buffer 16" "0,1"
|
|
bitfld.long 0x0 15. "ND15,New Data RX Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data RX Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data RX Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data RX Buffer 12" "0,1"
|
|
bitfld.long 0x0 11. "ND11,New Data RX Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data RX Buffer 10" "0,1"
|
|
bitfld.long 0x0 9. "ND9,New Data RX Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data RX Buffer 8" "0,1"
|
|
bitfld.long 0x0 7. "ND7,New Data RX Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data RX Buffer 6" "0,1"
|
|
bitfld.long 0x0 5. "ND5,New Data RX Buffer 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ND4,New Data RX Buffer 4" "0,1"
|
|
bitfld.long 0x0 3. "ND3,New Data RX Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data RX Buffer 2" "0,1"
|
|
bitfld.long 0x0 1. "ND1,New Data RX Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data RX Buffer 0" "0,1"
|
|
line.long 0x4 "MCAN_NDAT2,MCAN New Data 2"
|
|
bitfld.long 0x4 31. "ND63,New Data RX Buffer 63" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data RX Buffer 62" "0,1"
|
|
bitfld.long 0x4 29. "ND61,New Data RX Buffer 61" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data RX Buffer 60" "0,1"
|
|
bitfld.long 0x4 27. "ND59,New Data RX Buffer 59" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data RX Buffer 58" "0,1"
|
|
bitfld.long 0x4 25. "ND57,New Data RX Buffer 57" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data RX Buffer 56" "0,1"
|
|
bitfld.long 0x4 23. "ND55,New Data RX Buffer 55" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "ND54,New Data RX Buffer 54" "0,1"
|
|
bitfld.long 0x4 21. "ND53,New Data RX Buffer 53" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data RX Buffer 52" "0,1"
|
|
bitfld.long 0x4 19. "ND51,New Data RX Buffer 51" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data RX Buffer 50" "0,1"
|
|
bitfld.long 0x4 17. "ND49,New Data RX Buffer 49" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data RX Buffer 48" "0,1"
|
|
bitfld.long 0x4 15. "ND47,New Data RX Buffer 47" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data RX Buffer 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data RX Buffer 45" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data RX Buffer 44" "0,1"
|
|
bitfld.long 0x4 11. "ND43,New Data RX Buffer 43" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data RX Buffer 42" "0,1"
|
|
bitfld.long 0x4 9. "ND41,New Data RX Buffer 41" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data RX Buffer 40" "0,1"
|
|
bitfld.long 0x4 7. "ND39,New Data RX Buffer 39" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data RX Buffer 38" "0,1"
|
|
bitfld.long 0x4 5. "ND37,New Data RX Buffer 37" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ND36,New Data RX Buffer 36" "0,1"
|
|
bitfld.long 0x4 3. "ND35,New Data RX Buffer 35" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data RX Buffer 34" "0,1"
|
|
bitfld.long 0x4 1. "ND33,New Data RX Buffer 33" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data RX Buffer 32" "0,1"
|
|
line.long 0x8 "MCAN_RXF0C,MCAN Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "MCAN_RXF0S,MCAN Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "MCAN_RXBC,MCAN Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "MCAN_RXF1C,MCAN Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "MCAN_RXF1S,MCAN Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MCAN_TXBC,MCAN Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "MCAN_TXFQS,MCAN Tx FIFO / Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "MCAN_TXESC,MCAN Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "MCAN_TXBRP,MCAN Tx Buffer Request Pending"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending 30" "0,1"
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending 28" "0,1"
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending 26" "0,1"
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending 24" "0,1"
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending 22" "0,1"
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending 20" "0,1"
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending 18" "0,1"
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending 16" "0,1"
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending 12" "0,1"
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending 10" "0,1"
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending 8" "0,1"
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending 6" "0,1"
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending 4" "0,1"
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending 2" "0,1"
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "MCAN_TXBAR,MCAN Tx Buffer Add Request"
|
|
bitfld.long 0x0 31. "AR31,Add Request 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request 30" "0,1"
|
|
bitfld.long 0x0 29. "AR29,Add Request 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request 28" "0,1"
|
|
bitfld.long 0x0 27. "AR27,Add Request 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request 26" "0,1"
|
|
bitfld.long 0x0 25. "AR25,Add Request 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request 24" "0,1"
|
|
bitfld.long 0x0 23. "AR23,Add Request 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AR22,Add Request 22" "0,1"
|
|
bitfld.long 0x0 21. "AR21,Add Request 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request 20" "0,1"
|
|
bitfld.long 0x0 19. "AR19,Add Request 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request 18" "0,1"
|
|
bitfld.long 0x0 17. "AR17,Add Request 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request 16" "0,1"
|
|
bitfld.long 0x0 15. "AR15,Add Request 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request 12" "0,1"
|
|
bitfld.long 0x0 11. "AR11,Add Request 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request 10" "0,1"
|
|
bitfld.long 0x0 9. "AR9,Add Request 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request 8" "0,1"
|
|
bitfld.long 0x0 7. "AR7,Add Request 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request 6" "0,1"
|
|
bitfld.long 0x0 5. "AR5,Add Request 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "AR4,Add Request 4" "0,1"
|
|
bitfld.long 0x0 3. "AR3,Add Request 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request 2" "0,1"
|
|
bitfld.long 0x0 1. "AR1,Add Request 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request 0" "0,1"
|
|
line.long 0x4 "MCAN_TXBCR,MCAN Tx Buffer Cancellation Request"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request 30" "0,1"
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request 28" "0,1"
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request 26" "0,1"
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request 24" "0,1"
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request 22" "0,1"
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request 20" "0,1"
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request 18" "0,1"
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request 16" "0,1"
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request 12" "0,1"
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request 10" "0,1"
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request 8" "0,1"
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request 6" "0,1"
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request 4" "0,1"
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request 2" "0,1"
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred 30" "0,1"
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred 28" "0,1"
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred 26" "0,1"
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred 24" "0,1"
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred 22" "0,1"
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred 20" "0,1"
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred 18" "0,1"
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred 16" "0,1"
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred 12" "0,1"
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred 10" "0,1"
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred 8" "0,1"
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred 6" "0,1"
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred 4" "0,1"
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred 2" "0,1"
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred 0" "0,1"
|
|
line.long 0x4 "MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished 30" "0,1"
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished 28" "0,1"
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished 26" "0,1"
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished 24" "0,1"
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished 22" "0,1"
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished 20" "0,1"
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished 18" "0,1"
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished 16" "0,1"
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished 12" "0,1"
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished 10" "0,1"
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished 8" "0,1"
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished 6" "0,1"
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished 4" "0,1"
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished 2" "0,1"
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 28" "0,1"
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 24" "0,1"
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 20" "0,1"
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 16" "0,1"
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 12" "0,1"
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 8" "0,1"
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 4" "0,1"
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 28" "0,1"
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 24" "0,1"
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 20" "0,1"
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 16" "0,1"
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 12" "0,1"
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 8" "0,1"
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 4" "0,1"
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "MCAN_TXEFC,MCAN Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "MCAN_TXEFS,MCAN Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "MCANERR"
|
|
base d:0x5C800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "MCANERR_REV,MCAN Error Aggregator Revision Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x0 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MCANERR_VECTOR,MCAN ECC Vector Register"
|
|
rbitfld.long 0x0 24. "RD_SVBUS_DONE,Read Completion Flag" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address Offset"
|
|
bitfld.long 0x0 15. "RD_SVBUS,Read Trigger" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "MCANERR_STAT,MCAN Error Misc Status"
|
|
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs"
|
|
line.long 0x4 "MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register"
|
|
bitfld.long 0x4 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x4 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor Revision"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "MCANERR_CTRL,MCAN ECC Control"
|
|
bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,SVBUS Timeout Enable" "0,1"
|
|
bitfld.long 0x0 6. "ERROR_ONCE,Force Error Only Once Enable" "0,1"
|
|
bitfld.long 0x0 5. "FORCE_N_ROW,Force Next Single/Double Bit Error" "0,1"
|
|
bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error Detected Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error Corrected Error" "0,1"
|
|
bitfld.long 0x0 2. "ENABLE_RMW,Enable Read-Modify-Write" "0,1"
|
|
bitfld.long 0x0 1. "ECC_CHECK,Enable ECC Check" "0,1"
|
|
bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC Generation" "0,1"
|
|
line.long 0x4 "MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ECC_ROW,Force Error Row Address"
|
|
line.long 0x8 "MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Force Error Bit2 Column Index"
|
|
hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Force Error Bit1 Column Index"
|
|
line.long 0xC "MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,ECC Error Bit Position"
|
|
bitfld.long 0xC 15. "CLR_CTRL_REG_ERROR,Clear Control Register Error" "0,1"
|
|
bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear ECC_OTHER" "0,1"
|
|
bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear ECC_DED" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear ECC_SEC" "0,1,2,3"
|
|
bitfld.long 0xC 7. "CTRL_REG_ERROR,Control Register Error" "0,1"
|
|
bitfld.long 0xC 4. "ECC_OTHER,SEC While Writeback Error Status" "0,1"
|
|
bitfld.long 0xC 2.--3. "ECC_DED,Double Bit Error Detected Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "ECC_SEC,Single Bit Error Corrected Status" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_ROW,ECC Error Row Address"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register"
|
|
bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT,Clear Serial VBUS Timeout" "0,1"
|
|
bitfld.long 0x0 1. "SVBUS_TIMEOUT,Serial VBUS Timeout Flag" "0,1"
|
|
rbitfld.long 0x0 0. "WB_PEND,Delayed Write Back Pending Status" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register"
|
|
bitfld.long 0x0 0. "EOI_WR,End of Interrupt" "0,1"
|
|
line.long 0x4 "MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register"
|
|
bitfld.long 0x4 0. "MSGMEM_PEND,Message RAM SEC Interrupt Pending" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM SEC Interrupt Pending Enable Set" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM SEC Interrupt Pending Enable Clear" "0,1"
|
|
group.long 0x13C++0x7
|
|
line.long 0x0 "MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register"
|
|
bitfld.long 0x0 0. "EOI_WR,End of Interrupt" "0,1"
|
|
line.long 0x4 "MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register"
|
|
bitfld.long 0x4 0. "MSGMEM_PEND,Message RAM DED Interrupt Pending" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM DED Interrupt Pending Enable Set" "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM DED Interrupt Pending Enable Clear" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register"
|
|
bitfld.long 0x0 1. "ENABLE_TIMEOUT_SET,Enable Timeout Errors Set" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE_PARITY_SET,Enable Parity Errors Set" "0,1"
|
|
line.long 0x4 "MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register"
|
|
bitfld.long 0x4 1. "ENABLE_TIMEOUT_CLR,Enable Timeout Errors Clear" "0,1"
|
|
bitfld.long 0x4 0. "ENABLE_PARITY_CLR,Enable Parity Errors Clear" "0,1"
|
|
line.long 0x8 "MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register"
|
|
bitfld.long 0x8 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3"
|
|
line.long 0xC "MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register"
|
|
bitfld.long 0xC 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "MCANSS"
|
|
base d:0x5C400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "MCANSS_PID,MCAN Subsystem Revision Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MCANSS_CTRL,MCAN Subsystem Control Register"
|
|
bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1"
|
|
bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
|
|
bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
|
|
bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend Free" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "MCANSS_STAT,MCAN Subsystem Status Register"
|
|
bitfld.long 0x0 2. "ENABLE_FDOE,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization Done" "0,1"
|
|
bitfld.long 0x0 0. "RESET,Soft Reset Status" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register"
|
|
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Clear" "0,1"
|
|
line.long 0x4 "MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register"
|
|
bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status" "0,1"
|
|
line.long 0x8 "MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register"
|
|
bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Clear" "0,1"
|
|
line.long 0xC "MCANSS_IE,MCAN Subsystem Interrupt Enable Register"
|
|
bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "MCANSS_IES,MCAN Subsystem Interrupt Enable Status"
|
|
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Status" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "MCANSS_EOI,MCAN Subsystem End of Interrupt"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EOI,External Timestamp Counter Overflow End of Interrupt"
|
|
line.long 0x4 "MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,External Timestamp Counter Unserviced Rollover Interrupts"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "MCANSS"
|
|
base d:0x4007C400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "MCANSS_PID,MCAN Subsystem Revision Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MCANSS_CTRL,MCAN Subsystem Control Register"
|
|
bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1"
|
|
bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
|
|
bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
|
|
bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend Free" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "MCANSS_STAT,MCAN Subsystem Status Register"
|
|
bitfld.long 0x0 2. "ENABLE_FDOE,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization Done" "0,1"
|
|
bitfld.long 0x0 0. "RESET,Soft Reset Status" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register"
|
|
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Clear" "0,1"
|
|
line.long 0x4 "MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register"
|
|
bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status" "0,1"
|
|
line.long 0x8 "MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register"
|
|
bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Clear" "0,1"
|
|
line.long 0xC "MCANSS_IE,MCAN Subsystem Interrupt Enable Register"
|
|
bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "MCANSS_IES,MCAN Subsystem Interrupt Enable Status"
|
|
bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Status" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "MCANSS_EOI,MCAN Subsystem End of Interrupt"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EOI,External Timestamp Counter Overflow End of Interrupt"
|
|
line.long 0x4 "MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,External Timestamp Counter Unserviced Rollover Interrupts"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "MCAN"
|
|
base d:0x4007C600
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "MCAN_CREL,MCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "MCAN_ENDN,MCAN Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianess Test Value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Resynchronization Jump Width"
|
|
line.long 0x4 "MCAN_TEST,MCAN Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1"
|
|
line.long 0x8 "MCAN_RWD,MCAN RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "MCAN_CCCR,MCAN CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non-ISO Operation" "0,1"
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1"
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering During Bus Integration" "0,1"
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1"
|
|
bitfld.long 0xC 8. "FDOE,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1"
|
|
rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0,1"
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0,1"
|
|
line.long 0x10 "MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x14 "MCAN_TSCC,MCAN Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
|
|
line.long 0x18 "MCAN_TSCV,MCAN Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
|
|
line.long 0x1C "MCAN_TOCC,MCAN Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
line.long 0x20 "MCAN_TOCV,MCAN Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "MCAN_ECR,MCAN Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "MCAN_PSR,MCAN Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message" "0,1"
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "ACT,Node Activity" "0,1,2,3"
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MCAN_TDCR,MCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "MCAN_IR,MCAN Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message Stored to Dedicated Rx Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1"
|
|
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "MCAN_IE,MCAN Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1"
|
|
bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Enable" "0,1"
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Enable" "0,1"
|
|
bitfld.long 0x4 19. "DRXE,Message Stored to Dedicated Rx Buffer Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1"
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Enable" "0,1"
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1"
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Enable" "0,1"
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Enable" "0,1"
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Enable" "0,1"
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Enable" "0,1"
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1"
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Enable" "0,1"
|
|
line.long 0x8 "MCAN_ILS,MCAN Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Line" "0,1"
|
|
bitfld.long 0x8 23. "EPL,Error Passive Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Line" "0,1"
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Line" "0,1"
|
|
bitfld.long 0x8 19. "DRXL,Message Stored to Dedicated Rx Buffer Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Line" "0,1"
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Line" "0,1"
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Line" "0,1"
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Line" "0,1"
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Line" "0,1"
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Line" "0,1"
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Line" "0,1"
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Line" "0,1"
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Line" "0,1"
|
|
line.long 0xC "MCAN_ILE,MCAN Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "MCAN_GFC,MCAN Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "MCAN_SIDFC,MCAN Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "MCAN_XIDFC,MCAN Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "MCAN_XIDAM,MCAN Extended ID and Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "MCAN_HPMS,MCAN High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "MCAN_NDAT1,MCAN New Data 1"
|
|
bitfld.long 0x0 31. "ND31,New Data RX Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data RX Buffer 30" "0,1"
|
|
bitfld.long 0x0 29. "ND29,New Data RX Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data RX Buffer 28" "0,1"
|
|
bitfld.long 0x0 27. "ND27,New Data RX Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data RX Buffer 26" "0,1"
|
|
bitfld.long 0x0 25. "ND25,New Data RX Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data RX Buffer 24" "0,1"
|
|
bitfld.long 0x0 23. "ND23,New Data RX Buffer 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "ND22,New Data RX Buffer 22" "0,1"
|
|
bitfld.long 0x0 21. "ND21,New Data RX Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data RX Buffer 20" "0,1"
|
|
bitfld.long 0x0 19. "ND19,New Data RX Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data RX Buffer 18" "0,1"
|
|
bitfld.long 0x0 17. "ND17,New Data RX Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data RX Buffer 16" "0,1"
|
|
bitfld.long 0x0 15. "ND15,New Data RX Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data RX Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data RX Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data RX Buffer 12" "0,1"
|
|
bitfld.long 0x0 11. "ND11,New Data RX Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data RX Buffer 10" "0,1"
|
|
bitfld.long 0x0 9. "ND9,New Data RX Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data RX Buffer 8" "0,1"
|
|
bitfld.long 0x0 7. "ND7,New Data RX Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data RX Buffer 6" "0,1"
|
|
bitfld.long 0x0 5. "ND5,New Data RX Buffer 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ND4,New Data RX Buffer 4" "0,1"
|
|
bitfld.long 0x0 3. "ND3,New Data RX Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data RX Buffer 2" "0,1"
|
|
bitfld.long 0x0 1. "ND1,New Data RX Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data RX Buffer 0" "0,1"
|
|
line.long 0x4 "MCAN_NDAT2,MCAN New Data 2"
|
|
bitfld.long 0x4 31. "ND63,New Data RX Buffer 63" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data RX Buffer 62" "0,1"
|
|
bitfld.long 0x4 29. "ND61,New Data RX Buffer 61" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data RX Buffer 60" "0,1"
|
|
bitfld.long 0x4 27. "ND59,New Data RX Buffer 59" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data RX Buffer 58" "0,1"
|
|
bitfld.long 0x4 25. "ND57,New Data RX Buffer 57" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data RX Buffer 56" "0,1"
|
|
bitfld.long 0x4 23. "ND55,New Data RX Buffer 55" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "ND54,New Data RX Buffer 54" "0,1"
|
|
bitfld.long 0x4 21. "ND53,New Data RX Buffer 53" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data RX Buffer 52" "0,1"
|
|
bitfld.long 0x4 19. "ND51,New Data RX Buffer 51" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data RX Buffer 50" "0,1"
|
|
bitfld.long 0x4 17. "ND49,New Data RX Buffer 49" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data RX Buffer 48" "0,1"
|
|
bitfld.long 0x4 15. "ND47,New Data RX Buffer 47" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data RX Buffer 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data RX Buffer 45" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data RX Buffer 44" "0,1"
|
|
bitfld.long 0x4 11. "ND43,New Data RX Buffer 43" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data RX Buffer 42" "0,1"
|
|
bitfld.long 0x4 9. "ND41,New Data RX Buffer 41" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data RX Buffer 40" "0,1"
|
|
bitfld.long 0x4 7. "ND39,New Data RX Buffer 39" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data RX Buffer 38" "0,1"
|
|
bitfld.long 0x4 5. "ND37,New Data RX Buffer 37" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ND36,New Data RX Buffer 36" "0,1"
|
|
bitfld.long 0x4 3. "ND35,New Data RX Buffer 35" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data RX Buffer 34" "0,1"
|
|
bitfld.long 0x4 1. "ND33,New Data RX Buffer 33" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data RX Buffer 32" "0,1"
|
|
line.long 0x8 "MCAN_RXF0C,MCAN Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "MCAN_RXF0S,MCAN Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "MCAN_RXBC,MCAN Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "MCAN_RXF1C,MCAN Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "MCAN_RXF1S,MCAN Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MCAN_TXBC,MCAN Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "MCAN_TXFQS,MCAN Tx FIFO / Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "MCAN_TXESC,MCAN Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "MCAN_TXBRP,MCAN Tx Buffer Request Pending"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending 30" "0,1"
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending 28" "0,1"
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending 26" "0,1"
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending 24" "0,1"
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending 22" "0,1"
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending 20" "0,1"
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending 18" "0,1"
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending 16" "0,1"
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending 12" "0,1"
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending 10" "0,1"
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending 8" "0,1"
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending 6" "0,1"
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending 4" "0,1"
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending 2" "0,1"
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "MCAN_TXBAR,MCAN Tx Buffer Add Request"
|
|
bitfld.long 0x0 31. "AR31,Add Request 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request 30" "0,1"
|
|
bitfld.long 0x0 29. "AR29,Add Request 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request 28" "0,1"
|
|
bitfld.long 0x0 27. "AR27,Add Request 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request 26" "0,1"
|
|
bitfld.long 0x0 25. "AR25,Add Request 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request 24" "0,1"
|
|
bitfld.long 0x0 23. "AR23,Add Request 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AR22,Add Request 22" "0,1"
|
|
bitfld.long 0x0 21. "AR21,Add Request 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request 20" "0,1"
|
|
bitfld.long 0x0 19. "AR19,Add Request 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request 18" "0,1"
|
|
bitfld.long 0x0 17. "AR17,Add Request 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request 16" "0,1"
|
|
bitfld.long 0x0 15. "AR15,Add Request 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request 12" "0,1"
|
|
bitfld.long 0x0 11. "AR11,Add Request 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request 10" "0,1"
|
|
bitfld.long 0x0 9. "AR9,Add Request 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request 8" "0,1"
|
|
bitfld.long 0x0 7. "AR7,Add Request 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request 6" "0,1"
|
|
bitfld.long 0x0 5. "AR5,Add Request 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "AR4,Add Request 4" "0,1"
|
|
bitfld.long 0x0 3. "AR3,Add Request 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request 2" "0,1"
|
|
bitfld.long 0x0 1. "AR1,Add Request 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request 0" "0,1"
|
|
line.long 0x4 "MCAN_TXBCR,MCAN Tx Buffer Cancellation Request"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request 30" "0,1"
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request 28" "0,1"
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request 26" "0,1"
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request 24" "0,1"
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request 22" "0,1"
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request 20" "0,1"
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request 18" "0,1"
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request 16" "0,1"
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request 12" "0,1"
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request 10" "0,1"
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request 8" "0,1"
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request 6" "0,1"
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request 4" "0,1"
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request 2" "0,1"
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred 30" "0,1"
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred 28" "0,1"
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred 26" "0,1"
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred 24" "0,1"
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred 22" "0,1"
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred 20" "0,1"
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred 18" "0,1"
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred 16" "0,1"
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred 12" "0,1"
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred 10" "0,1"
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred 8" "0,1"
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred 6" "0,1"
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred 4" "0,1"
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred 2" "0,1"
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred 0" "0,1"
|
|
line.long 0x4 "MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished 30" "0,1"
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished 28" "0,1"
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished 26" "0,1"
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished 24" "0,1"
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished 22" "0,1"
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished 20" "0,1"
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished 18" "0,1"
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished 16" "0,1"
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished 12" "0,1"
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished 10" "0,1"
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished 8" "0,1"
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished 6" "0,1"
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished 4" "0,1"
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished 2" "0,1"
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 28" "0,1"
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 24" "0,1"
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 20" "0,1"
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 16" "0,1"
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 12" "0,1"
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 8" "0,1"
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 4" "0,1"
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 28" "0,1"
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 24" "0,1"
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 23" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 20" "0,1"
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 16" "0,1"
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 12" "0,1"
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 8" "0,1"
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 4" "0,1"
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "MCAN_TXEFC,MCAN Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "MCAN_TXEFS,MCAN Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "MCANERR"
|
|
base d:0x4007C800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "MCANERR_REV,MCAN Error Aggregator Revision Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x0 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MCANERR_VECTOR,MCAN ECC Vector Register"
|
|
rbitfld.long 0x0 24. "RD_SVBUS_DONE,Read Completion Flag" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address Offset"
|
|
bitfld.long 0x0 15. "RD_SVBUS,Read Trigger" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "MCANERR_STAT,MCAN Error Misc Status"
|
|
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs"
|
|
line.long 0x4 "MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register"
|
|
bitfld.long 0x4 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x4 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor Revision"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "MCANERR_CTRL,MCAN ECC Control"
|
|
bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,SVBUS Timeout Enable" "0,1"
|
|
bitfld.long 0x0 6. "ERROR_ONCE,Force Error Only Once Enable" "0,1"
|
|
bitfld.long 0x0 5. "FORCE_N_ROW,Force Next Single/Double Bit Error" "0,1"
|
|
bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error Detected Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error Corrected Error" "0,1"
|
|
bitfld.long 0x0 2. "ENABLE_RMW,Enable Read-Modify-Write" "0,1"
|
|
bitfld.long 0x0 1. "ECC_CHECK,Enable ECC Check" "0,1"
|
|
bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC Generation" "0,1"
|
|
line.long 0x4 "MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ECC_ROW,Force Error Row Address"
|
|
line.long 0x8 "MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Force Error Bit2 Column Index"
|
|
hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Force Error Bit1 Column Index"
|
|
line.long 0xC "MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,ECC Error Bit Position"
|
|
bitfld.long 0xC 15. "CLR_CTRL_REG_ERROR,Clear Control Register Error" "0,1"
|
|
bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear ECC_OTHER" "0,1"
|
|
bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear ECC_DED" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear ECC_SEC" "0,1,2,3"
|
|
bitfld.long 0xC 7. "CTRL_REG_ERROR,Control Register Error" "0,1"
|
|
bitfld.long 0xC 4. "ECC_OTHER,SEC While Writeback Error Status" "0,1"
|
|
bitfld.long 0xC 2.--3. "ECC_DED,Double Bit Error Detected Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "ECC_SEC,Single Bit Error Corrected Status" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_ROW,ECC Error Row Address"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register"
|
|
bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT,Clear Serial VBUS Timeout" "0,1"
|
|
bitfld.long 0x0 1. "SVBUS_TIMEOUT,Serial VBUS Timeout Flag" "0,1"
|
|
rbitfld.long 0x0 0. "WB_PEND,Delayed Write Back Pending Status" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register"
|
|
bitfld.long 0x0 0. "EOI_WR,End of Interrupt" "0,1"
|
|
line.long 0x4 "MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register"
|
|
bitfld.long 0x4 0. "MSGMEM_PEND,Message RAM SEC Interrupt Pending" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM SEC Interrupt Pending Enable Set" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM SEC Interrupt Pending Enable Clear" "0,1"
|
|
group.long 0x13C++0x7
|
|
line.long 0x0 "MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register"
|
|
bitfld.long 0x0 0. "EOI_WR,End of Interrupt" "0,1"
|
|
line.long 0x4 "MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register"
|
|
bitfld.long 0x4 0. "MSGMEM_PEND,Message RAM DED Interrupt Pending" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM DED Interrupt Pending Enable Set" "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM DED Interrupt Pending Enable Clear" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register"
|
|
bitfld.long 0x0 1. "ENABLE_TIMEOUT_SET,Enable Timeout Errors Set" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE_PARITY_SET,Enable Parity Errors Set" "0,1"
|
|
line.long 0x4 "MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register"
|
|
bitfld.long 0x4 1. "ENABLE_TIMEOUT_CLR,Enable Timeout Errors Clear" "0,1"
|
|
bitfld.long 0x4 0. "ENABLE_PARITY_CLR,Enable Parity Errors Clear" "0,1"
|
|
line.long 0x8 "MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register"
|
|
bitfld.long 0x8 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3"
|
|
line.long 0xC "MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register"
|
|
bitfld.long 0xC 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "MCBSP (Multichannel Buffered Serial Port)"
|
|
base d:0x0
|
|
tree "MCBSPA"
|
|
base d:0x6000
|
|
group.word 0x0++0x3D
|
|
line.word 0x0 "DRR2,Data receive register bits 31-16"
|
|
hexmask.word.byte 0x0 8.--15. 1. "HWHB,High word high byte"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HWLB,High word low byte"
|
|
line.word 0x1 "DRR1,Data receive register bits 15-0"
|
|
hexmask.word.byte 0x1 8.--15. 1. "LWHB,Low word high byte"
|
|
hexmask.word.byte 0x1 0.--7. 1. "LWLB,Low word low byte"
|
|
line.word 0x2 "DXR2,Data transmit register bits 31-16"
|
|
hexmask.word.byte 0x2 8.--15. 1. "HWHB,High word high byte"
|
|
hexmask.word.byte 0x2 0.--7. 1. "HWLB,High word low byte"
|
|
line.word 0x3 "DXR1,Data transmit register bits 15-0"
|
|
hexmask.word.byte 0x3 8.--15. 1. "LWHB,Low word high byte"
|
|
hexmask.word.byte 0x3 0.--7. 1. "LWLB,Low word low byte"
|
|
line.word 0x4 "SPCR2,Serial port control register 2"
|
|
bitfld.word 0x4 9. "FREE,FREE bit" "0,1"
|
|
bitfld.word 0x4 8. "SOFT,SOFT bit" "0,1"
|
|
bitfld.word 0x4 7. "FRST,Frame sync logic reset" "0,1"
|
|
bitfld.word 0x4 6. "GRST,Sample rate generator reset" "0,1"
|
|
bitfld.word 0x4 4.--5. "XINTM,Transmit Interupt mode bits" "0,1,2,3"
|
|
bitfld.word 0x4 3. "XSYNCERR,Transmit sync error INT flag" "0,1"
|
|
rbitfld.word 0x4 2. "XEMPTY,Transmitter empty" "0,1"
|
|
rbitfld.word 0x4 1. "XRDY,Transmitter ready" "0,1"
|
|
bitfld.word 0x4 0. "XRST,Transmitter reset" "0,1"
|
|
line.word 0x5 "SPCR1,Serial port control register 1"
|
|
bitfld.word 0x5 15. "DLB,Digital loopback" "0,1"
|
|
bitfld.word 0x5 13.--14. "RJUST,Rx sign extension and justification mode" "0,1,2,3"
|
|
bitfld.word 0x5 11.--12. "CLKSTP,Clock stop mode" "0,1,2,3"
|
|
bitfld.word 0x5 7. "DXENA,DX delay enable" "0,1"
|
|
bitfld.word 0x5 4.--5. "RINTM,Receive Interupt mode bits" "0,1,2,3"
|
|
bitfld.word 0x5 3. "RSYNCERR,Receive sync error INT flag" "0,1"
|
|
rbitfld.word 0x5 2. "RFULL,Receiver full" "0,1"
|
|
rbitfld.word 0x5 1. "RRDY,Receiver ready" "0,1"
|
|
bitfld.word 0x5 0. "RRST,Receiver reset" "0,1"
|
|
line.word 0x6 "RCR2,Receive Control register 2"
|
|
bitfld.word 0x6 15. "RPHASE,Receive Phase" "0,1"
|
|
hexmask.word.byte 0x6 8.--14. 1. "RFRLEN2,Receive Frame length 2"
|
|
bitfld.word 0x6 5.--7. "RWDLEN2,Receive word length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--4. "RCOMPAND,Receive Companding Mode selects" "0,1,2,3"
|
|
bitfld.word 0x6 2. "RFIG,Receive frame sync ignore" "0,1"
|
|
bitfld.word 0x6 0.--1. "RDATDLY,Receive data delay" "0,1,2,3"
|
|
line.word 0x7 "RCR1,Receive Control register 1"
|
|
hexmask.word.byte 0x7 8.--14. 1. "RFRLEN1,Receive Frame length 1"
|
|
bitfld.word 0x7 5.--7. "RWDLEN1,Receive word length 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "XCR2,Transmit Control register 2"
|
|
bitfld.word 0x8 15. "XPHASE,Transmit Phase" "0,1"
|
|
hexmask.word.byte 0x8 8.--14. 1. "XFRLEN2,Transmit Frame length 2"
|
|
bitfld.word 0x8 5.--7. "XWDLEN2,Transmit word length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x8 3.--4. "XCOMPAND,Transmit Companding Mode selects" "0,1,2,3"
|
|
bitfld.word 0x8 2. "XFIG,Transmit frame sync ignore" "0,1"
|
|
bitfld.word 0x8 0.--1. "XDATDLY,Transmit data delay" "0,1,2,3"
|
|
line.word 0x9 "XCR1,Transmit Control register 1"
|
|
hexmask.word.byte 0x9 8.--14. 1. "XFRLEN1,Transmit Frame length 1"
|
|
bitfld.word 0x9 5.--7. "XWDLEN1,Transmit word length 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0xA "SRGR2,Sample rate generator register 2"
|
|
bitfld.word 0xA 15. "GSYNC,CLKG sync" "0,1"
|
|
bitfld.word 0xA 13. "CLKSM,Sample rate generator mode" "0,1"
|
|
bitfld.word 0xA 12. "FSGM,Frame sync generator mode" "0,1"
|
|
hexmask.word 0xA 0.--11. 1. "FPER,Frame-sync period"
|
|
line.word 0xB "SRGR1,Sample rate generator register 1"
|
|
hexmask.word.byte 0xB 8.--15. 1. "FWID,Frame width"
|
|
hexmask.word.byte 0xB 0.--7. 1. "CLKGDV,CLKG divider"
|
|
line.word 0xC "MCR2,Multi-channel control register 2"
|
|
bitfld.word 0xC 9. "XMCME,Transmit Frame length 2" "0,1"
|
|
bitfld.word 0xC 7.--8. "XPBBLK,Transmit word length 2" "0,1,2,3"
|
|
bitfld.word 0xC 5.--6. "XPABLK,Transmit Companding Mode selects" "0,1,2,3"
|
|
rbitfld.word 0xC 2.--4. "XCBLK,Transmit frame sync ignore" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xC 0.--1. "XMCM,Transmit data delay" "0,1,2,3"
|
|
line.word 0xD "MCR1,Multi-channel control register 1"
|
|
bitfld.word 0xD 9. "RMCME,Receive multi-channel enhance mode" "0,1"
|
|
bitfld.word 0xD 7.--8. "RPBBLK,Receive partition B Block" "0,1,2,3"
|
|
bitfld.word 0xD 5.--6. "RPABLK,Receive partition A Block" "0,1,2,3"
|
|
rbitfld.word 0xD 2.--4. "RCBLK,eceive current block" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xD 0. "RMCM,Receive multichannel mode" "0,1"
|
|
line.word 0xE "RCERA,Receive channel enable partition A"
|
|
hexmask.word 0xE 0.--15. 1. "RCEA,Receive channel enable bit."
|
|
line.word 0xF "RCERB,Receive channel enable partition B"
|
|
hexmask.word 0xF 0.--15. 1. "RCEB,Receive channel enable bit."
|
|
line.word 0x10 "XCERA,Transmit channel enable partition A"
|
|
hexmask.word 0x10 0.--15. 1. "XCERA,Transmit Channel enable bit"
|
|
line.word 0x11 "XCERB,Transmit channel enable partition B"
|
|
hexmask.word 0x11 0.--15. 1. "XCERB,Transmit Channel enable bit"
|
|
line.word 0x12 "PCR,Pin Control register"
|
|
bitfld.word 0x12 11. "FSXM,Transmit Frame Synchronization Mode" "0,1"
|
|
bitfld.word 0x12 10. "FSRM,Receive Frame Synchronization Mode" "0,1"
|
|
bitfld.word 0x12 9. "CLKXM,Transmit Clock Mode." "0,1"
|
|
bitfld.word 0x12 8. "CLKRM,Receiver Clock Mode" "0,1"
|
|
bitfld.word 0x12 7. "SCLKME,Sample clock mode selection" "0,1"
|
|
bitfld.word 0x12 3. "FSXP,Transmit Frame synchronization polarity" "0,1"
|
|
rbitfld.word 0x12 2. "FSRP,Receive Frame synchronization polarity" "0,1"
|
|
rbitfld.word 0x12 1. "CLKXP,Transmit clock polarity" "0,1"
|
|
bitfld.word 0x12 0. "CLKRP,Receive Clock polarity" "0,1"
|
|
line.word 0x13 "RCERC,Receive channel enable partition C"
|
|
hexmask.word 0x13 0.--15. 1. "RCEC,Receive channel enable bit."
|
|
line.word 0x14 "RCERD,Receive channel enable partition D"
|
|
hexmask.word 0x14 0.--15. 1. "RCED,Receive channel enable bit."
|
|
line.word 0x15 "XCERC,Transmit channel enable partition C"
|
|
hexmask.word 0x15 0.--15. 1. "XCERC,Transmit Channel enable bit"
|
|
line.word 0x16 "XCERD,Transmit channel enable partition D"
|
|
hexmask.word 0x16 0.--15. 1. "XCERD,Transmit Channel enable bit"
|
|
line.word 0x17 "RCERE,Receive channel enable partition E"
|
|
hexmask.word 0x17 0.--15. 1. "RCEE,Receive channel enable bit."
|
|
line.word 0x18 "RCERF,Receive channel enable partition F"
|
|
hexmask.word 0x18 0.--15. 1. "RCEF,Receive channel enable bit."
|
|
line.word 0x19 "XCERE,Transmit channel enable partition E"
|
|
hexmask.word 0x19 0.--15. 1. "XCERE,Transmit Channel enable bit"
|
|
line.word 0x1A "XCERF,Transmit channel enable partition F"
|
|
hexmask.word 0x1A 0.--15. 1. "XCERF,Transmit Channel enable bit"
|
|
line.word 0x1B "RCERG,Receive channel enable partition G"
|
|
hexmask.word 0x1B 0.--15. 1. "RCEG,Receive channel enable bit."
|
|
line.word 0x1C "RCERH,Receive channel enable partition H"
|
|
hexmask.word 0x1C 0.--15. 1. "RCEH,Receive channel enable bit."
|
|
line.word 0x1D "XCERG,Transmit channel enable partition G"
|
|
hexmask.word 0x1D 0.--15. 1. "XCERG,Transmit Channel enable bit"
|
|
line.word 0x1E "XCERH,Transmit channel enable partition H"
|
|
hexmask.word 0x1E 0.--15. 1. "XCERH,Transmit Channel enable bit"
|
|
group.word 0x23++0x1
|
|
line.word 0x0 "MFFINT,Interrupt enable"
|
|
bitfld.word 0x0 2. "RINT,Enable for transmit Interrupt" "0,1"
|
|
bitfld.word 0x0 0. "XINT,Enable for Receive Interrupt" "0,1"
|
|
tree.end
|
|
tree "MCBSPB"
|
|
base d:0x6040
|
|
group.word 0x0++0x3D
|
|
line.word 0x0 "DRR2,Data receive register bits 31-16"
|
|
hexmask.word.byte 0x0 8.--15. 1. "HWHB,High word high byte"
|
|
hexmask.word.byte 0x0 0.--7. 1. "HWLB,High word low byte"
|
|
line.word 0x1 "DRR1,Data receive register bits 15-0"
|
|
hexmask.word.byte 0x1 8.--15. 1. "LWHB,Low word high byte"
|
|
hexmask.word.byte 0x1 0.--7. 1. "LWLB,Low word low byte"
|
|
line.word 0x2 "DXR2,Data transmit register bits 31-16"
|
|
hexmask.word.byte 0x2 8.--15. 1. "HWHB,High word high byte"
|
|
hexmask.word.byte 0x2 0.--7. 1. "HWLB,High word low byte"
|
|
line.word 0x3 "DXR1,Data transmit register bits 15-0"
|
|
hexmask.word.byte 0x3 8.--15. 1. "LWHB,Low word high byte"
|
|
hexmask.word.byte 0x3 0.--7. 1. "LWLB,Low word low byte"
|
|
line.word 0x4 "SPCR2,Serial port control register 2"
|
|
bitfld.word 0x4 9. "FREE,FREE bit" "0,1"
|
|
bitfld.word 0x4 8. "SOFT,SOFT bit" "0,1"
|
|
bitfld.word 0x4 7. "FRST,Frame sync logic reset" "0,1"
|
|
bitfld.word 0x4 6. "GRST,Sample rate generator reset" "0,1"
|
|
bitfld.word 0x4 4.--5. "XINTM,Transmit Interupt mode bits" "0,1,2,3"
|
|
bitfld.word 0x4 3. "XSYNCERR,Transmit sync error INT flag" "0,1"
|
|
rbitfld.word 0x4 2. "XEMPTY,Transmitter empty" "0,1"
|
|
rbitfld.word 0x4 1. "XRDY,Transmitter ready" "0,1"
|
|
bitfld.word 0x4 0. "XRST,Transmitter reset" "0,1"
|
|
line.word 0x5 "SPCR1,Serial port control register 1"
|
|
bitfld.word 0x5 15. "DLB,Digital loopback" "0,1"
|
|
bitfld.word 0x5 13.--14. "RJUST,Rx sign extension and justification mode" "0,1,2,3"
|
|
bitfld.word 0x5 11.--12. "CLKSTP,Clock stop mode" "0,1,2,3"
|
|
bitfld.word 0x5 7. "DXENA,DX delay enable" "0,1"
|
|
bitfld.word 0x5 4.--5. "RINTM,Receive Interupt mode bits" "0,1,2,3"
|
|
bitfld.word 0x5 3. "RSYNCERR,Receive sync error INT flag" "0,1"
|
|
rbitfld.word 0x5 2. "RFULL,Receiver full" "0,1"
|
|
rbitfld.word 0x5 1. "RRDY,Receiver ready" "0,1"
|
|
bitfld.word 0x5 0. "RRST,Receiver reset" "0,1"
|
|
line.word 0x6 "RCR2,Receive Control register 2"
|
|
bitfld.word 0x6 15. "RPHASE,Receive Phase" "0,1"
|
|
hexmask.word.byte 0x6 8.--14. 1. "RFRLEN2,Receive Frame length 2"
|
|
bitfld.word 0x6 5.--7. "RWDLEN2,Receive word length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x6 3.--4. "RCOMPAND,Receive Companding Mode selects" "0,1,2,3"
|
|
bitfld.word 0x6 2. "RFIG,Receive frame sync ignore" "0,1"
|
|
bitfld.word 0x6 0.--1. "RDATDLY,Receive data delay" "0,1,2,3"
|
|
line.word 0x7 "RCR1,Receive Control register 1"
|
|
hexmask.word.byte 0x7 8.--14. 1. "RFRLEN1,Receive Frame length 1"
|
|
bitfld.word 0x7 5.--7. "RWDLEN1,Receive word length 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0x8 "XCR2,Transmit Control register 2"
|
|
bitfld.word 0x8 15. "XPHASE,Transmit Phase" "0,1"
|
|
hexmask.word.byte 0x8 8.--14. 1. "XFRLEN2,Transmit Frame length 2"
|
|
bitfld.word 0x8 5.--7. "XWDLEN2,Transmit word length 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x8 3.--4. "XCOMPAND,Transmit Companding Mode selects" "0,1,2,3"
|
|
bitfld.word 0x8 2. "XFIG,Transmit frame sync ignore" "0,1"
|
|
bitfld.word 0x8 0.--1. "XDATDLY,Transmit data delay" "0,1,2,3"
|
|
line.word 0x9 "XCR1,Transmit Control register 1"
|
|
hexmask.word.byte 0x9 8.--14. 1. "XFRLEN1,Transmit Frame length 1"
|
|
bitfld.word 0x9 5.--7. "XWDLEN1,Transmit word length 1" "0,1,2,3,4,5,6,7"
|
|
line.word 0xA "SRGR2,Sample rate generator register 2"
|
|
bitfld.word 0xA 15. "GSYNC,CLKG sync" "0,1"
|
|
bitfld.word 0xA 13. "CLKSM,Sample rate generator mode" "0,1"
|
|
bitfld.word 0xA 12. "FSGM,Frame sync generator mode" "0,1"
|
|
hexmask.word 0xA 0.--11. 1. "FPER,Frame-sync period"
|
|
line.word 0xB "SRGR1,Sample rate generator register 1"
|
|
hexmask.word.byte 0xB 8.--15. 1. "FWID,Frame width"
|
|
hexmask.word.byte 0xB 0.--7. 1. "CLKGDV,CLKG divider"
|
|
line.word 0xC "MCR2,Multi-channel control register 2"
|
|
bitfld.word 0xC 9. "XMCME,Transmit Frame length 2" "0,1"
|
|
bitfld.word 0xC 7.--8. "XPBBLK,Transmit word length 2" "0,1,2,3"
|
|
bitfld.word 0xC 5.--6. "XPABLK,Transmit Companding Mode selects" "0,1,2,3"
|
|
rbitfld.word 0xC 2.--4. "XCBLK,Transmit frame sync ignore" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xC 0.--1. "XMCM,Transmit data delay" "0,1,2,3"
|
|
line.word 0xD "MCR1,Multi-channel control register 1"
|
|
bitfld.word 0xD 9. "RMCME,Receive multi-channel enhance mode" "0,1"
|
|
bitfld.word 0xD 7.--8. "RPBBLK,Receive partition B Block" "0,1,2,3"
|
|
bitfld.word 0xD 5.--6. "RPABLK,Receive partition A Block" "0,1,2,3"
|
|
rbitfld.word 0xD 2.--4. "RCBLK,eceive current block" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0xD 0. "RMCM,Receive multichannel mode" "0,1"
|
|
line.word 0xE "RCERA,Receive channel enable partition A"
|
|
hexmask.word 0xE 0.--15. 1. "RCEA,Receive channel enable bit."
|
|
line.word 0xF "RCERB,Receive channel enable partition B"
|
|
hexmask.word 0xF 0.--15. 1. "RCEB,Receive channel enable bit."
|
|
line.word 0x10 "XCERA,Transmit channel enable partition A"
|
|
hexmask.word 0x10 0.--15. 1. "XCERA,Transmit Channel enable bit"
|
|
line.word 0x11 "XCERB,Transmit channel enable partition B"
|
|
hexmask.word 0x11 0.--15. 1. "XCERB,Transmit Channel enable bit"
|
|
line.word 0x12 "PCR,Pin Control register"
|
|
bitfld.word 0x12 11. "FSXM,Transmit Frame Synchronization Mode" "0,1"
|
|
bitfld.word 0x12 10. "FSRM,Receive Frame Synchronization Mode" "0,1"
|
|
bitfld.word 0x12 9. "CLKXM,Transmit Clock Mode." "0,1"
|
|
bitfld.word 0x12 8. "CLKRM,Receiver Clock Mode" "0,1"
|
|
bitfld.word 0x12 7. "SCLKME,Sample clock mode selection" "0,1"
|
|
bitfld.word 0x12 3. "FSXP,Transmit Frame synchronization polarity" "0,1"
|
|
rbitfld.word 0x12 2. "FSRP,Receive Frame synchronization polarity" "0,1"
|
|
rbitfld.word 0x12 1. "CLKXP,Transmit clock polarity" "0,1"
|
|
bitfld.word 0x12 0. "CLKRP,Receive Clock polarity" "0,1"
|
|
line.word 0x13 "RCERC,Receive channel enable partition C"
|
|
hexmask.word 0x13 0.--15. 1. "RCEC,Receive channel enable bit."
|
|
line.word 0x14 "RCERD,Receive channel enable partition D"
|
|
hexmask.word 0x14 0.--15. 1. "RCED,Receive channel enable bit."
|
|
line.word 0x15 "XCERC,Transmit channel enable partition C"
|
|
hexmask.word 0x15 0.--15. 1. "XCERC,Transmit Channel enable bit"
|
|
line.word 0x16 "XCERD,Transmit channel enable partition D"
|
|
hexmask.word 0x16 0.--15. 1. "XCERD,Transmit Channel enable bit"
|
|
line.word 0x17 "RCERE,Receive channel enable partition E"
|
|
hexmask.word 0x17 0.--15. 1. "RCEE,Receive channel enable bit."
|
|
line.word 0x18 "RCERF,Receive channel enable partition F"
|
|
hexmask.word 0x18 0.--15. 1. "RCEF,Receive channel enable bit."
|
|
line.word 0x19 "XCERE,Transmit channel enable partition E"
|
|
hexmask.word 0x19 0.--15. 1. "XCERE,Transmit Channel enable bit"
|
|
line.word 0x1A "XCERF,Transmit channel enable partition F"
|
|
hexmask.word 0x1A 0.--15. 1. "XCERF,Transmit Channel enable bit"
|
|
line.word 0x1B "RCERG,Receive channel enable partition G"
|
|
hexmask.word 0x1B 0.--15. 1. "RCEG,Receive channel enable bit."
|
|
line.word 0x1C "RCERH,Receive channel enable partition H"
|
|
hexmask.word 0x1C 0.--15. 1. "RCEH,Receive channel enable bit."
|
|
line.word 0x1D "XCERG,Transmit channel enable partition G"
|
|
hexmask.word 0x1D 0.--15. 1. "XCERG,Transmit Channel enable bit"
|
|
line.word 0x1E "XCERH,Transmit channel enable partition H"
|
|
hexmask.word 0x1E 0.--15. 1. "XCERH,Transmit Channel enable bit"
|
|
group.word 0x23++0x1
|
|
line.word 0x0 "MFFINT,Interrupt enable"
|
|
bitfld.word 0x0 2. "RINT,Enable for transmit Interrupt" "0,1"
|
|
bitfld.word 0x0 0. "XINT,Enable for Receive Interrupt" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PMBus (Power Management Bus Module)"
|
|
base d:0x6400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PMBMC,PMBUS Master Mode Control Register"
|
|
bitfld.long 0x0 20. "PRC_CALL,Master Process Call Message Enable" "0,1"
|
|
bitfld.long 0x0 19. "GRP_CMD,Master Group Command Message Enable" "0,1"
|
|
bitfld.long 0x0 18. "PEC_ENA,Master PEC Processing Enable" "0,1"
|
|
bitfld.long 0x0 17. "EXT_CMD,Master Extended Command Code Enable" "0,1"
|
|
bitfld.long 0x0 16. "CMD_ENA,Master Command Code Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BYTE_COUNT,Number of Bytes Transmitted"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SLAVE_ADDR,Slave Address"
|
|
bitfld.long 0x0 0. "RW,RnW bit of the Message" "0,1"
|
|
line.long 0x2 "PMBTXBUF,PMBUS Transmit Buffer"
|
|
hexmask.long 0x2 0.--31. 1. "TXDATA,Transmit Message Data"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PMBRXBUF,PMBUS Receive buffer"
|
|
hexmask.long 0x0 0.--31. 1. "RXDATA,PMBus Receive Data Register"
|
|
group.long 0x6++0x3
|
|
line.long 0x0 "PMBACK,PMBUS Acknowledge Register"
|
|
bitfld.long 0x0 0. "ACK,Allows firmware to ack/nack received data" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PMBSTS,PMBUS Status Register"
|
|
bitfld.long 0x0 21. "SCL_RAW,PMBus Clock Pin Real Time Status" "0,1"
|
|
bitfld.long 0x0 20. "SDA_RAW,PMBus Data Pin Real Time Status" "0,1"
|
|
bitfld.long 0x0 19. "CONTROL_RAW,Control Pin Real Time Status" "0,1"
|
|
bitfld.long 0x0 18. "ALERT_RAW,Alert Pin Real Time Status" "0,1"
|
|
bitfld.long 0x0 17. "CONTROL_EDGE,Control Edge Detection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ALERT_EDGE,Alert Edge Detection Status" "0,1"
|
|
bitfld.long 0x0 15. "MASTER,Master Indicator" "0,1"
|
|
bitfld.long 0x0 14. "LOST_ARB,Lost Arbitration Flag" "0,1"
|
|
bitfld.long 0x0 13. "BUS_FREE,PMBus Free Indicator" "0,1"
|
|
bitfld.long 0x0 12. "UNIT_BUSY,PMBus Busy Indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RPT_START,Repeated Start Flag" "0,1"
|
|
bitfld.long 0x0 10. "SLAVE_ADDR_READY,Slave Address Ready" "0,1"
|
|
bitfld.long 0x0 9. "CLK_HIGH_DETECTED,Clock High Detection Status" "0,1"
|
|
bitfld.long 0x0 8. "CLK_LOW_TIMEOUT,Clock Low Timeout Status" "0,1"
|
|
bitfld.long 0x0 7. "PEC_VALID,PEC Valid Indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "NACK,Not Acknowledge Flag Status" "0,1"
|
|
bitfld.long 0x0 5. "EOM,End of Message Indicator" "0,1"
|
|
bitfld.long 0x0 4. "DATA_REQUEST,Data Request Flag" "0,1"
|
|
bitfld.long 0x0 3. "DATA_READY,Data Ready Flag" "0,1"
|
|
bitfld.long 0x0 0.--2. "RD_BYTE_COUNT,Number of Data Bytes available in Receive Data Register" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA++0x7
|
|
line.long 0x0 "PMBINTM,PMBUS Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "CLK_HIGH_DETECT,Clock High Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "LOST_ARB,Lost Arbitration Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "CONTROL,Control Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "ALERT,Alert Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "EOM,End of Message Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SLAVE_ADDR_READY,Slave Address Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DATA_REQUEST,Data Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "DATA_READY,Data Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "BUS_LOW_TIMEOUT,Clock Low Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "BUS_FREE,Bus Free Interrupt Mask" "0,1"
|
|
line.long 0x2 "PMBSC,PMBUS Slave Mode Configuration Register"
|
|
bitfld.long 0x2 21.--22. "RX_BYTE_ACK_CNT,Number of data bytes to automatically acknowledge" "0,1,2,3"
|
|
bitfld.long 0x2 20. "MAN_CMD,Manual Command Acknowledgement Mode" "0,1"
|
|
bitfld.long 0x2 19. "TX_PEC,send a PEC byte at end of message" "0,1"
|
|
bitfld.long 0x2 16.--18. "TX_COUNT,Number of valid bytes in Transmit Data Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2 15. "PEC_ENA,PEC Processing Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x2 8.--14. 1. "SLAVE_MASK,Slave address mask"
|
|
bitfld.long 0x2 7. "MAN_SLAVE_ACK,Manual Slave Address Acknowledgement Mode" "0,1"
|
|
hexmask.long.byte 0x2 0.--6. 1. "SLAVE_ADDR,Configures the current device address of the slave."
|
|
rgroup.long 0xE++0x3
|
|
line.long 0x0 "PMBHSA,PMBUS Hold Slave Address Register"
|
|
hexmask.long.byte 0x0 1.--7. 1. "SLAVE_ADDR,Stored device address"
|
|
bitfld.long 0x0 0. "SLAVE_RW,Stored R/W bit" "0,1"
|
|
group.long 0x10++0x1B
|
|
line.long 0x0 "PMBCTRL,PMBUS Control Register"
|
|
bitfld.long 0x0 31. "I2CMODE,Bit to enable I2C mode" "0,1"
|
|
hexmask.long.byte 0x0 23.--27. 1. "CLKDIV,PMBUS Clock Divide Value"
|
|
bitfld.long 0x0 22. "MASTER_EN,PMBus Master Enable" "0,1"
|
|
bitfld.long 0x0 21. "SLAVE_EN,PMBus Slave Enable" "0,1"
|
|
bitfld.long 0x0 20. "CLK_LO_DIS,Clock Low Timeout Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "IBIAS_B_EN,PMBus Current Source B Control" "0,1"
|
|
bitfld.long 0x0 18. "IBIAS_A_EN,PMBus Current Source A Control" "0,1"
|
|
bitfld.long 0x0 17. "SCL_DIR,Configures direction of PMBus clock pin in GPIO mode" "0,1"
|
|
bitfld.long 0x0 16. "SCL_VALUE,Configures output value of PMBus clock pin in GPIO Mode" "0,1"
|
|
bitfld.long 0x0 15. "SCL_MODE,Configures mode of PMBus Clock pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SDA_DIR,Configures direction of PMBus data pin in GPIO mode" "0,1"
|
|
bitfld.long 0x0 13. "SDA_VALUE,Configures output value of PMBus data pin in GPIO Mode" "0,1"
|
|
bitfld.long 0x0 12. "SDA_MODE,Configures mode of PMBus Data pin" "0,1"
|
|
bitfld.long 0x0 11. "CNTL_DIR,Configures direction of Control pin in GPIO mode" "0,1"
|
|
bitfld.long 0x0 10. "CNTL_VALUE,Configures output value of Control pin in GPIO Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CNTL_MODE,Configures mode of Control pin" "0,1"
|
|
bitfld.long 0x0 8. "ALERT_DIR,Configures direction of Alert pin in GPIO mode" "0,1"
|
|
bitfld.long 0x0 7. "ALERT_VALUE,Configures output value of Alert pin in GPIO Mode" "0,1"
|
|
bitfld.long 0x0 6. "ALERT_MODE,Configures mode of Alert pin" "0,1"
|
|
bitfld.long 0x0 5. "CNTL_INT_EDGE,Control Interrupt Edge Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FAST_MODE,Fast Mode Enable" "0,1"
|
|
bitfld.long 0x0 2. "BUS_LO_INT_EDGE,Clock Low Timeout Interrupt Edge Select" "0,1"
|
|
bitfld.long 0x0 1. "ALERT_EN,Slave Alert Enable" "0,1"
|
|
bitfld.long 0x0 0. "RESET,PMBus Interface Synchronous Reset" "0,1"
|
|
line.long 0x2 "PMBTIMCTL,PMBUS Timing Control Register"
|
|
bitfld.long 0x2 0. "TIM_OVERRIDE,Overide the default settings of the timing parameters." "0,1"
|
|
line.long 0x4 "PMBTIMCLK,PMBUS Clock Timing Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLK_FREQ,Determines the PMBUS master clock frequency."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_LIMIT,Determines the PMBUS master clock high pulse width."
|
|
line.long 0x6 "PMBTIMSTSETUP,PMBUS Start Setup Time Register"
|
|
hexmask.long.byte 0x6 0.--7. 1. "TSU_STA,Setup time rise edge of PMBUS master clock to start edge."
|
|
line.long 0x8 "PMBTIMBIDLE,PMBUS Bus Idle Time Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "BUSIDLE,Determines the Bus Idle Limit"
|
|
line.long 0xA "PMBTIMLOWTIMOUT,PMBUS Clock Low Timeout Value Register"
|
|
hexmask.long.tbyte 0xA 0.--19. 1. "CLKLOWTIMOUT,Determines the clock low timeout value"
|
|
line.long 0xC "PMBTIMHIGHTIMOUT,PMBUS Clock High Timeout Value Register"
|
|
hexmask.long.word 0xC 0.--9. 1. "CLKHIGHTIMOUT,Determines the clock high timeout value"
|
|
tree.end
|
|
tree "SCI (Serial Communications Interface)"
|
|
base d:0x0
|
|
tree "SCIA"
|
|
base d:0x7200
|
|
group.word 0x0++0x9
|
|
line.word 0x0 "SCICCR,Communications control register"
|
|
bitfld.word 0x0 7. "STOPBITS,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x0 6. "PARITY,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x0 5. "PARITYENA,Parity enable" "0,1"
|
|
bitfld.word 0x0 4. "LOOPBKENA,Loop Back enable" "0,1"
|
|
bitfld.word 0x0 3. "ADDRIDLE_MODE,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x0 0.--2. "SCICHAR,Character length control" "0,1,2,3,4,5,6,7"
|
|
line.word 0x1 "SCICTL1,Control register 1"
|
|
bitfld.word 0x1 6. "RXERRINTENA,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x1 5. "SWRESET,Software reset" "0,1"
|
|
bitfld.word 0x1 3. "TXWAKE,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x1 2. "SLEEP,SCI sleep" "0,1"
|
|
bitfld.word 0x1 1. "TXENA,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x1 0. "RXENA,SCI receiver enable" "0,1"
|
|
line.word 0x2 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word.byte 0x2 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
line.word 0x3 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
line.word 0x4 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x4 7. "TXRDY,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x4 6. "TXEMPTY,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x4 1. "RXBKINTENA,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x4 0. "TXINTENA,Transmit __interrupt enable" "0,1"
|
|
rgroup.word 0x5++0x5
|
|
line.word 0x0 "SCIRXST,Receive status register"
|
|
bitfld.word 0x0 7. "RXERROR,Receiver error flag" "0,1"
|
|
bitfld.word 0x0 6. "RXRDY,Receiver ready flag" "0,1"
|
|
bitfld.word 0x0 5. "BRKDT,Break-detect flag" "0,1"
|
|
bitfld.word 0x0 4. "FE,Framing error flag" "0,1"
|
|
bitfld.word 0x0 3. "OE,Overrun error flag" "0,1"
|
|
bitfld.word 0x0 2. "PE,Parity error flag" "0,1"
|
|
bitfld.word 0x0 1. "RXWAKE,Receiver wakeup detect flag" "0,1"
|
|
line.word 0x1 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word.byte 0x1 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
line.word 0x2 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x2 15. "SCIFFFE,Receiver error flag" "0,1"
|
|
bitfld.word 0x2 14. "SCIFFPE,Receiver error flag" "0,1"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word 0x9++0x7
|
|
line.word 0x0 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word.byte 0x0 0.--7. 1. "TXDT,Transmit data buffer"
|
|
line.word 0x1 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x1 15. "SCIRST,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x1 14. "SCIFFENA,Enhancement enable" "0,1"
|
|
bitfld.word 0x1 13. "TXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x1 8.--12. 1. "TXFFST,FIFO status"
|
|
rbitfld.word 0x1 7. "TXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x1 6. "TXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x1 5. "TXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--4. 1. "TXFFIL,Interrupt level"
|
|
line.word 0x2 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x2 15. "RXFFOVF,FIFO overflow" "0,1"
|
|
bitfld.word 0x2 14. "RXFFOVRCLR,Clear overflow" "0,1"
|
|
bitfld.word 0x2 13. "RXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "RXFFST,FIFO status"
|
|
rbitfld.word 0x2 7. "RXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x2 6. "RXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x2 5. "RXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x2 0.--4. 1. "RXFFIL,Interrupt level"
|
|
line.word 0x3 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x3 15. "ABD,Auto baud detect" "0,1"
|
|
bitfld.word 0x3 14. "ABDCLR,Auto baud clear" "0,1"
|
|
bitfld.word 0x3 13. "CDC,Auto baud mode enable" "0,1"
|
|
hexmask.word.byte 0x3 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x0 3.--4. "FREESOFT,Emulation modes" "0,1,2,3"
|
|
tree.end
|
|
tree "SCIB"
|
|
base d:0x7210
|
|
group.word 0x0++0x9
|
|
line.word 0x0 "SCICCR,Communications control register"
|
|
bitfld.word 0x0 7. "STOPBITS,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x0 6. "PARITY,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x0 5. "PARITYENA,Parity enable" "0,1"
|
|
bitfld.word 0x0 4. "LOOPBKENA,Loop Back enable" "0,1"
|
|
bitfld.word 0x0 3. "ADDRIDLE_MODE,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x0 0.--2. "SCICHAR,Character length control" "0,1,2,3,4,5,6,7"
|
|
line.word 0x1 "SCICTL1,Control register 1"
|
|
bitfld.word 0x1 6. "RXERRINTENA,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x1 5. "SWRESET,Software reset" "0,1"
|
|
bitfld.word 0x1 3. "TXWAKE,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x1 2. "SLEEP,SCI sleep" "0,1"
|
|
bitfld.word 0x1 1. "TXENA,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x1 0. "RXENA,SCI receiver enable" "0,1"
|
|
line.word 0x2 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word.byte 0x2 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
line.word 0x3 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
line.word 0x4 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x4 7. "TXRDY,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x4 6. "TXEMPTY,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x4 1. "RXBKINTENA,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x4 0. "TXINTENA,Transmit __interrupt enable" "0,1"
|
|
rgroup.word 0x5++0x5
|
|
line.word 0x0 "SCIRXST,Receive status register"
|
|
bitfld.word 0x0 7. "RXERROR,Receiver error flag" "0,1"
|
|
bitfld.word 0x0 6. "RXRDY,Receiver ready flag" "0,1"
|
|
bitfld.word 0x0 5. "BRKDT,Break-detect flag" "0,1"
|
|
bitfld.word 0x0 4. "FE,Framing error flag" "0,1"
|
|
bitfld.word 0x0 3. "OE,Overrun error flag" "0,1"
|
|
bitfld.word 0x0 2. "PE,Parity error flag" "0,1"
|
|
bitfld.word 0x0 1. "RXWAKE,Receiver wakeup detect flag" "0,1"
|
|
line.word 0x1 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word.byte 0x1 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
line.word 0x2 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x2 15. "SCIFFFE,Receiver error flag" "0,1"
|
|
bitfld.word 0x2 14. "SCIFFPE,Receiver error flag" "0,1"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word 0x9++0x7
|
|
line.word 0x0 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word.byte 0x0 0.--7. 1. "TXDT,Transmit data buffer"
|
|
line.word 0x1 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x1 15. "SCIRST,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x1 14. "SCIFFENA,Enhancement enable" "0,1"
|
|
bitfld.word 0x1 13. "TXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x1 8.--12. 1. "TXFFST,FIFO status"
|
|
rbitfld.word 0x1 7. "TXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x1 6. "TXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x1 5. "TXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--4. 1. "TXFFIL,Interrupt level"
|
|
line.word 0x2 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x2 15. "RXFFOVF,FIFO overflow" "0,1"
|
|
bitfld.word 0x2 14. "RXFFOVRCLR,Clear overflow" "0,1"
|
|
bitfld.word 0x2 13. "RXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "RXFFST,FIFO status"
|
|
rbitfld.word 0x2 7. "RXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x2 6. "RXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x2 5. "RXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x2 0.--4. 1. "RXFFIL,Interrupt level"
|
|
line.word 0x3 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x3 15. "ABD,Auto baud detect" "0,1"
|
|
bitfld.word 0x3 14. "ABDCLR,Auto baud clear" "0,1"
|
|
bitfld.word 0x3 13. "CDC,Auto baud mode enable" "0,1"
|
|
hexmask.word.byte 0x3 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x0 3.--4. "FREESOFT,Emulation modes" "0,1,2,3"
|
|
tree.end
|
|
tree "SCIC"
|
|
base d:0x7220
|
|
group.word 0x0++0x9
|
|
line.word 0x0 "SCICCR,Communications control register"
|
|
bitfld.word 0x0 7. "STOPBITS,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x0 6. "PARITY,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x0 5. "PARITYENA,Parity enable" "0,1"
|
|
bitfld.word 0x0 4. "LOOPBKENA,Loop Back enable" "0,1"
|
|
bitfld.word 0x0 3. "ADDRIDLE_MODE,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x0 0.--2. "SCICHAR,Character length control" "0,1,2,3,4,5,6,7"
|
|
line.word 0x1 "SCICTL1,Control register 1"
|
|
bitfld.word 0x1 6. "RXERRINTENA,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x1 5. "SWRESET,Software reset" "0,1"
|
|
bitfld.word 0x1 3. "TXWAKE,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x1 2. "SLEEP,SCI sleep" "0,1"
|
|
bitfld.word 0x1 1. "TXENA,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x1 0. "RXENA,SCI receiver enable" "0,1"
|
|
line.word 0x2 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word.byte 0x2 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
line.word 0x3 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
line.word 0x4 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x4 7. "TXRDY,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x4 6. "TXEMPTY,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x4 1. "RXBKINTENA,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x4 0. "TXINTENA,Transmit __interrupt enable" "0,1"
|
|
rgroup.word 0x5++0x5
|
|
line.word 0x0 "SCIRXST,Receive status register"
|
|
bitfld.word 0x0 7. "RXERROR,Receiver error flag" "0,1"
|
|
bitfld.word 0x0 6. "RXRDY,Receiver ready flag" "0,1"
|
|
bitfld.word 0x0 5. "BRKDT,Break-detect flag" "0,1"
|
|
bitfld.word 0x0 4. "FE,Framing error flag" "0,1"
|
|
bitfld.word 0x0 3. "OE,Overrun error flag" "0,1"
|
|
bitfld.word 0x0 2. "PE,Parity error flag" "0,1"
|
|
bitfld.word 0x0 1. "RXWAKE,Receiver wakeup detect flag" "0,1"
|
|
line.word 0x1 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word.byte 0x1 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
line.word 0x2 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x2 15. "SCIFFFE,Receiver error flag" "0,1"
|
|
bitfld.word 0x2 14. "SCIFFPE,Receiver error flag" "0,1"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word 0x9++0x7
|
|
line.word 0x0 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word.byte 0x0 0.--7. 1. "TXDT,Transmit data buffer"
|
|
line.word 0x1 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x1 15. "SCIRST,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x1 14. "SCIFFENA,Enhancement enable" "0,1"
|
|
bitfld.word 0x1 13. "TXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x1 8.--12. 1. "TXFFST,FIFO status"
|
|
rbitfld.word 0x1 7. "TXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x1 6. "TXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x1 5. "TXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--4. 1. "TXFFIL,Interrupt level"
|
|
line.word 0x2 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x2 15. "RXFFOVF,FIFO overflow" "0,1"
|
|
bitfld.word 0x2 14. "RXFFOVRCLR,Clear overflow" "0,1"
|
|
bitfld.word 0x2 13. "RXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "RXFFST,FIFO status"
|
|
rbitfld.word 0x2 7. "RXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x2 6. "RXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x2 5. "RXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x2 0.--4. 1. "RXFFIL,Interrupt level"
|
|
line.word 0x3 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x3 15. "ABD,Auto baud detect" "0,1"
|
|
bitfld.word 0x3 14. "ABDCLR,Auto baud clear" "0,1"
|
|
bitfld.word 0x3 13. "CDC,Auto baud mode enable" "0,1"
|
|
hexmask.word.byte 0x3 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x0 3.--4. "FREESOFT,Emulation modes" "0,1,2,3"
|
|
tree.end
|
|
tree "SCID"
|
|
base d:0x7230
|
|
group.word 0x0++0x9
|
|
line.word 0x0 "SCICCR,Communications control register"
|
|
bitfld.word 0x0 7. "STOPBITS,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x0 6. "PARITY,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x0 5. "PARITYENA,Parity enable" "0,1"
|
|
bitfld.word 0x0 4. "LOOPBKENA,Loop Back enable" "0,1"
|
|
bitfld.word 0x0 3. "ADDRIDLE_MODE,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x0 0.--2. "SCICHAR,Character length control" "0,1,2,3,4,5,6,7"
|
|
line.word 0x1 "SCICTL1,Control register 1"
|
|
bitfld.word 0x1 6. "RXERRINTENA,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x1 5. "SWRESET,Software reset" "0,1"
|
|
bitfld.word 0x1 3. "TXWAKE,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x1 2. "SLEEP,SCI sleep" "0,1"
|
|
bitfld.word 0x1 1. "TXENA,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x1 0. "RXENA,SCI receiver enable" "0,1"
|
|
line.word 0x2 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word.byte 0x2 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
line.word 0x3 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word.byte 0x3 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
line.word 0x4 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x4 7. "TXRDY,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x4 6. "TXEMPTY,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x4 1. "RXBKINTENA,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x4 0. "TXINTENA,Transmit __interrupt enable" "0,1"
|
|
rgroup.word 0x5++0x5
|
|
line.word 0x0 "SCIRXST,Receive status register"
|
|
bitfld.word 0x0 7. "RXERROR,Receiver error flag" "0,1"
|
|
bitfld.word 0x0 6. "RXRDY,Receiver ready flag" "0,1"
|
|
bitfld.word 0x0 5. "BRKDT,Break-detect flag" "0,1"
|
|
bitfld.word 0x0 4. "FE,Framing error flag" "0,1"
|
|
bitfld.word 0x0 3. "OE,Overrun error flag" "0,1"
|
|
bitfld.word 0x0 2. "PE,Parity error flag" "0,1"
|
|
bitfld.word 0x0 1. "RXWAKE,Receiver wakeup detect flag" "0,1"
|
|
line.word 0x1 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word.byte 0x1 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
line.word 0x2 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x2 15. "SCIFFFE,Receiver error flag" "0,1"
|
|
bitfld.word 0x2 14. "SCIFFPE,Receiver error flag" "0,1"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word 0x9++0x7
|
|
line.word 0x0 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word.byte 0x0 0.--7. 1. "TXDT,Transmit data buffer"
|
|
line.word 0x1 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x1 15. "SCIRST,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x1 14. "SCIFFENA,Enhancement enable" "0,1"
|
|
bitfld.word 0x1 13. "TXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x1 8.--12. 1. "TXFFST,FIFO status"
|
|
rbitfld.word 0x1 7. "TXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x1 6. "TXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x1 5. "TXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--4. 1. "TXFFIL,Interrupt level"
|
|
line.word 0x2 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x2 15. "RXFFOVF,FIFO overflow" "0,1"
|
|
bitfld.word 0x2 14. "RXFFOVRCLR,Clear overflow" "0,1"
|
|
bitfld.word 0x2 13. "RXFIFORESET,FIFO reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "RXFFST,FIFO status"
|
|
rbitfld.word 0x2 7. "RXFFINT,INT flag" "0,1"
|
|
bitfld.word 0x2 6. "RXFFINTCLR,Clear INT flag" "0,1"
|
|
bitfld.word 0x2 5. "RXFFIENA,Interrupt enable" "0,1"
|
|
hexmask.word.byte 0x2 0.--4. 1. "RXFFIL,Interrupt level"
|
|
line.word 0x3 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x3 15. "ABD,Auto baud detect" "0,1"
|
|
bitfld.word 0x3 14. "ABDCLR,Auto baud clear" "0,1"
|
|
bitfld.word 0x3 13. "CDC,Auto baud mode enable" "0,1"
|
|
hexmask.word.byte 0x3 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x0 3.--4. "FREESOFT,Emulation modes" "0,1,2,3"
|
|
tree.end
|
|
tree.end
|
|
tree "SDFM (Sigma Delta Filter Module)"
|
|
base d:0x0
|
|
tree "SDFM1"
|
|
base d:0x5E00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SDIFLG,SD Interrupt Flag Register"
|
|
bitfld.long 0x0 31. "MIF,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 23. "SDFFINT4,SDFIFO interrupt for Ch4" "0,1"
|
|
bitfld.long 0x0 22. "SDFFINT3,SDFIFO interrupt for Ch3" "0,1"
|
|
bitfld.long 0x0 21. "SDFFINT2,SDFIFO interrupt for Ch2" "0,1"
|
|
bitfld.long 0x0 20. "SDFFINT1,SDFIFO interrupt for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SDFFOVF4,FIFO Overflow Flag for Ch4" "0,1"
|
|
bitfld.long 0x0 18. "SDFFOVF3,FIFO Overflow Flag for Ch3" "0,1"
|
|
bitfld.long 0x0 17. "SDFFOVF2,FIFO Overflow Flag for Ch2" "0,1"
|
|
bitfld.long 0x0 16. "SDFFOVF1,FIFO Overflow Flag for Ch1." "0,1"
|
|
bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2" "0,1"
|
|
bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2" "0,1"
|
|
bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 6. "FLT4_FLG_CEVT1,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FLT3_FLG_CEVT1,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 2. "FLT2_FLG_CEVT1,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Low-level Interrupt flag for Ch1" "0,1"
|
|
bitfld.long 0x0 0. "FLT1_FLG_CEVT1,High-level Interrupt flag for Ch1" "0,1"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "SDIFLGCLR,SD Interrupt Flag Clear Register"
|
|
bitfld.long 0x0 31. "MIF,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 23. "SDFFINT4,SDFIFO Interrupt flag-clear bit for Ch4" "0,1"
|
|
bitfld.long 0x0 22. "SDFFINT3,SDFIFO Interrupt flag-clear bit for Ch3" "0,1"
|
|
bitfld.long 0x0 21. "SDFFINT2,SDFIFO Interrupt flag-clear bit for Ch2" "0,1"
|
|
bitfld.long 0x0 20. "SDFFINT1,SDFIFO Interrupt flag-clear bit for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SDFFOVF4,SDFIFO overflow clear Ch4" "0,1"
|
|
bitfld.long 0x0 18. "SDFFOVF3,SDFIFO overflow clear Ch3" "0,1"
|
|
bitfld.long 0x0 17. "SDFFOVF2,SDFIFO overflow clear Ch2" "0,1"
|
|
bitfld.long 0x0 16. "SDFFOVF1,SDFIFO overflow clear Ch1" "0,1"
|
|
bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2" "0,1"
|
|
bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2" "0,1"
|
|
bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 6. "FLT4_FLG_CEVT1,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FLT3_FLG_CEVT1,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 2. "FLT2_FLG_CEVT1,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Low-level Interrupt flag for Ch1" "0,1"
|
|
bitfld.long 0x0 0. "FLT1_FLG_CEVT1,High-level Interrupt flag for Ch1" "0,1"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "SDCTL,SD Control Register"
|
|
bitfld.word 0x0 13. "MIE,Master SDy_ERR Interrupt enable" "0,1"
|
|
bitfld.word 0x0 3. "HZ4,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x0 2. "HZ3,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
bitfld.word 0x0 1. "HZ2,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
bitfld.word 0x0 0. "HZ1,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
line.word 0x2 "SDMFILEN,SD Master Filter Enable"
|
|
bitfld.word 0x2 11. "MFE,Master Filter Enable." "0,1"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "SDSTATUS,SD Status Register"
|
|
bitfld.word 0x0 15. "MAL4,Manchester locked status for filter module 4." "0,1"
|
|
bitfld.word 0x0 14. "MAL3,Manchester locked status for filter module 3." "0,1"
|
|
bitfld.word 0x0 13. "MAL2,Manchester locked status for filter module 2." "0,1"
|
|
bitfld.word 0x0 12. "MAL1,Manchester locked status for filter module 1." "0,1"
|
|
bitfld.word 0x0 11. "MS4,Manchester clock decode phase complete for filter module 4." "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "MS3,Manchester clock decode phase complete for filter module 3." "0,1"
|
|
bitfld.word 0x0 9. "MS2,Manchester clock decode phase complete for filter module 2." "0,1"
|
|
bitfld.word 0x0 8. "MS1,Manchester clock decode phase complete for filter module 1." "0,1"
|
|
bitfld.word 0x0 3. "HZ4,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x0 2. "HZ3,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "HZ2,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
bitfld.word 0x0 0. "HZ1,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
group.word 0x10++0xB
|
|
line.word 0x0 "SDCTLPARM1,Control Parameter Register for Ch1"
|
|
hexmask.word.byte 0x0 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x0 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x0 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x0 3. "SDCLKSEL,SD1 Clock source select." "0,1"
|
|
bitfld.word 0x0 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x1 "SDDFPARM1,Data Filter Parameter Register for Ch1"
|
|
bitfld.word 0x1 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x1 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x1 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x1 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x2 "SDDPARM1,Data Parameter Register for Ch1"
|
|
hexmask.word.byte 0x2 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x2 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x3 "SDFLT1CMPH1,High-level Threshold Register for Ch1"
|
|
hexmask.word 0x3 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x4 "SDFLT1CMPL1,Low-level Threshold Register for Ch1"
|
|
hexmask.word 0x4 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0x5 "SDCPARM1,Comparator Filter Parameter Register for Ch1"
|
|
bitfld.word 0x5 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x5 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0x5 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x5 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0x5 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x5 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x5 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x5 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0x5 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x16++0x7
|
|
line.long 0x0 "SDDATA1,Data Filter Data Register (16 or 32bit) for Ch1"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO1,Filter Data FIFO Output(32b) for Ch1"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x1A++0x1
|
|
line.word 0x0 "SDCDATA1,Comparator Filter Data Register (16b) for Ch1"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x1B++0x15
|
|
line.word 0x0 "SDFLT1CMPH2,Second high level threhold for CH1"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT1CMPHZ,High-level (Z) Threshold Register for Ch1"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL1,FIFO Control Register for Ch1"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC1,SD Filter Sync control for Ch1"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT1CMPL2,Second low level threhold for CH1"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
line.word 0x5 "SDCTLPARM2,Control Parameter Register for Ch2"
|
|
hexmask.word.byte 0x5 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x5 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x5 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x5 3. "SDCLKSEL,SD2 Clock source select." "0,1"
|
|
bitfld.word 0x5 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x5 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x6 "SDDFPARM2,Data Filter Parameter Register for Ch2"
|
|
bitfld.word 0x6 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x6 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x6 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x6 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x6 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x7 "SDDPARM2,Data Parameter Register for Ch2"
|
|
hexmask.word.byte 0x7 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x7 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x8 "SDFLT2CMPH1,High-level Threshold Register for Ch2"
|
|
hexmask.word 0x8 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x9 "SDFLT2CMPL1,Low-level Threshold Register for Ch2"
|
|
hexmask.word 0x9 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0xA "SDCPARM2,Comparator Filter Parameter Register for Ch2"
|
|
bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0xA 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0xA 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0xA 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x26++0x7
|
|
line.long 0x0 "SDDATA2,Data Filter Data Register (16 or 32bit) for Ch2"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO2,Filter Data FIFO Output(32b) for Ch2"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x2A++0x1
|
|
line.word 0x0 "SDCDATA2,Comparator Filter Data Register (16b) for Ch2"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x2B++0x15
|
|
line.word 0x0 "SDFLT2CMPH2,Second high level threhold for CH2"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT2CMPHZ,High-level (Z) Threshold Register for Ch2"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL2,FIFO Control Register for Ch2"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC2,SD Filter Sync control for Ch2"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT2CMPL2,Second low level threhold for CH2"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
line.word 0x5 "SDCTLPARM3,Control Parameter Register for Ch3"
|
|
hexmask.word.byte 0x5 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x5 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x5 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x5 3. "SDCLKSEL,SD3 Clock source select." "0,1"
|
|
bitfld.word 0x5 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x5 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x6 "SDDFPARM3,Data Filter Parameter Register for Ch3"
|
|
bitfld.word 0x6 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x6 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x6 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x6 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x6 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x7 "SDDPARM3,Data Parameter Register for Ch3"
|
|
hexmask.word.byte 0x7 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x7 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x8 "SDFLT3CMPH1,High-level Threshold Register for Ch3"
|
|
hexmask.word 0x8 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x9 "SDFLT3CMPL1,Low-level Threshold Register for Ch3"
|
|
hexmask.word 0x9 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0xA "SDCPARM3,Comparator Filter Parameter Register for Ch3"
|
|
bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0xA 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0xA 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0xA 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x36++0x7
|
|
line.long 0x0 "SDDATA3,Data Filter Data Register (16 or 32bit) for Ch3"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO3,Filter Data FIFO Output(32b) for Ch3"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x3A++0x1
|
|
line.word 0x0 "SDCDATA3,Comparator Filter Data Register (16b) for Ch3"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x3B++0x15
|
|
line.word 0x0 "SDFLT3CMPH2,Second high level threhold for CH3"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT3CMPHZ,High-level (Z) Threshold Register for Ch3"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL3,FIFO Control Register for Ch3"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC3,SD Filter Sync control for Ch3"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT3CMPL2,Second low level threhold for CH3"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
line.word 0x5 "SDCTLPARM4,Control Parameter Register for Ch4"
|
|
hexmask.word.byte 0x5 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x5 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x5 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x5 3. "SDCLKSEL,SD4 Clock source select." "0,1"
|
|
bitfld.word 0x5 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x5 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x6 "SDDFPARM4,Data Filter Parameter Register for Ch4"
|
|
bitfld.word 0x6 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x6 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x6 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x6 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x6 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x7 "SDDPARM4,Data Parameter Register for Ch4"
|
|
hexmask.word.byte 0x7 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x7 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x8 "SDFLT4CMPH1,High-level Threshold Register for Ch4"
|
|
hexmask.word 0x8 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x9 "SDFLT4CMPL1,Low-level Threshold Register for Ch4"
|
|
hexmask.word 0x9 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0xA "SDCPARM4,Comparator Filter Parameter Register for Ch4"
|
|
bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0xA 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0xA 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0xA 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x46++0x7
|
|
line.long 0x0 "SDDATA4,Data Filter Data Register (16 or 32bit) for Ch4"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO4,Filter Data FIFO Output(32b) for Ch4"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x4A++0x1
|
|
line.word 0x0 "SDCDATA4,Comparator Filter Data Register (16b) for Ch4"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x4B++0x9
|
|
line.word 0x0 "SDFLT4CMPH2,Second high level threhold for CH4"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT4CMPHZ,High-level (Z) Threshold Register for Ch4"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL4,FIFO Control Register for Ch4"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC4,SD Filter Sync control for Ch4"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT4CMPL2,Second low level threhold for CH4"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word 0x60++0x9
|
|
line.word 0x0 "SDCOMP1CTL,SD Comparator event filter1 Control Register"
|
|
bitfld.word 0x0 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x1 "SDCOMP1EVT2FLTCTL,COMPL/CEVT2 Digital filter1 Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "SDCOMP1EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "SDCOMP1EVT1FLTCTL,COMPH/CEVT1 Digital filter1 Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "SDCOMP1EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x67++0xB
|
|
line.word 0x0 "SDCOMP1LOCK,SD compartor event filter1 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP1CTL,COMPCTL Lock" "0,1"
|
|
line.word 0x1 "SDCOMP2CTL,SD Comparator event filter2 Control Register"
|
|
bitfld.word 0x1 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x2 "SDCOMP2EVT2FLTCTL,COMPL/CEVT2 Digital filter2 Control Register"
|
|
bitfld.word 0x2 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x2 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x3 "SDCOMP2EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x3 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x4 "SDCOMP2EVT1FLTCTL,COMPH/CEVT1 Digital filter2 Control Register"
|
|
bitfld.word 0x4 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x4 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x5 "SDCOMP2EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x5 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x6F++0xB
|
|
line.word 0x0 "SDCOMP2LOCK,SD compartor event filter2 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP2CTL,COMPCTL Lock" "0,1"
|
|
line.word 0x1 "SDCOMP3CTL,SD Comparator event filter3 Control Register"
|
|
bitfld.word 0x1 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x2 "SDCOMP3EVT2FLTCTL,COMPL/CEVT2 Digital filter3 Control Register"
|
|
bitfld.word 0x2 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x2 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x3 "SDCOMP3EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x3 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x4 "SDCOMP3EVT1FLTCTL,COMPH/CEVT1 Digital filter3 Control Register"
|
|
bitfld.word 0x4 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x4 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x5 "SDCOMP3EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x5 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x77++0xB
|
|
line.word 0x0 "SDCOMP3LOCK,SD compartor event filter3 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP3CTL,COMPCTL Lock" "0,1"
|
|
line.word 0x1 "SDCOMP4CTL,SD Comparator event filter4 Control Register"
|
|
bitfld.word 0x1 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x2 "SDCOMP4EVT2FLTCTL,COMPL/CEVT2 Digital filter4 Control Register"
|
|
bitfld.word 0x2 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x2 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x3 "SDCOMP4EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x3 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x4 "SDCOMP4EVT1FLTCTL,COMPH/CEVT1 Digital filter4 Control Register"
|
|
bitfld.word 0x4 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x4 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x5 "SDCOMP4EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x5 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x7F++0x1
|
|
line.word 0x0 "SDCOMP4LOCK,SD compartor event filter4 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP4CTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree "SDFM2"
|
|
base d:0x5E80
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SDIFLG,SD Interrupt Flag Register"
|
|
bitfld.long 0x0 31. "MIF,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 23. "SDFFINT4,SDFIFO interrupt for Ch4" "0,1"
|
|
bitfld.long 0x0 22. "SDFFINT3,SDFIFO interrupt for Ch3" "0,1"
|
|
bitfld.long 0x0 21. "SDFFINT2,SDFIFO interrupt for Ch2" "0,1"
|
|
bitfld.long 0x0 20. "SDFFINT1,SDFIFO interrupt for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SDFFOVF4,FIFO Overflow Flag for Ch4" "0,1"
|
|
bitfld.long 0x0 18. "SDFFOVF3,FIFO Overflow Flag for Ch3" "0,1"
|
|
bitfld.long 0x0 17. "SDFFOVF2,FIFO Overflow Flag for Ch2" "0,1"
|
|
bitfld.long 0x0 16. "SDFFOVF1,FIFO Overflow Flag for Ch1." "0,1"
|
|
bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2" "0,1"
|
|
bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2" "0,1"
|
|
bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 6. "FLT4_FLG_CEVT1,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FLT3_FLG_CEVT1,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 2. "FLT2_FLG_CEVT1,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Low-level Interrupt flag for Ch1" "0,1"
|
|
bitfld.long 0x0 0. "FLT1_FLG_CEVT1,High-level Interrupt flag for Ch1" "0,1"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "SDIFLGCLR,SD Interrupt Flag Clear Register"
|
|
bitfld.long 0x0 31. "MIF,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 23. "SDFFINT4,SDFIFO Interrupt flag-clear bit for Ch4" "0,1"
|
|
bitfld.long 0x0 22. "SDFFINT3,SDFIFO Interrupt flag-clear bit for Ch3" "0,1"
|
|
bitfld.long 0x0 21. "SDFFINT2,SDFIFO Interrupt flag-clear bit for Ch2" "0,1"
|
|
bitfld.long 0x0 20. "SDFFINT1,SDFIFO Interrupt flag-clear bit for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SDFFOVF4,SDFIFO overflow clear Ch4" "0,1"
|
|
bitfld.long 0x0 18. "SDFFOVF3,SDFIFO overflow clear Ch3" "0,1"
|
|
bitfld.long 0x0 17. "SDFFOVF2,SDFIFO overflow clear Ch2" "0,1"
|
|
bitfld.long 0x0 16. "SDFFOVF1,SDFIFO overflow clear Ch1" "0,1"
|
|
bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2" "0,1"
|
|
bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2" "0,1"
|
|
bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 6. "FLT4_FLG_CEVT1,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FLT3_FLG_CEVT1,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 2. "FLT2_FLG_CEVT1,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Low-level Interrupt flag for Ch1" "0,1"
|
|
bitfld.long 0x0 0. "FLT1_FLG_CEVT1,High-level Interrupt flag for Ch1" "0,1"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "SDCTL,SD Control Register"
|
|
bitfld.word 0x0 13. "MIE,Master SDy_ERR Interrupt enable" "0,1"
|
|
bitfld.word 0x0 3. "HZ4,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x0 2. "HZ3,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
bitfld.word 0x0 1. "HZ2,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
bitfld.word 0x0 0. "HZ1,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
line.word 0x2 "SDMFILEN,SD Master Filter Enable"
|
|
bitfld.word 0x2 11. "MFE,Master Filter Enable." "0,1"
|
|
rgroup.word 0x7++0x1
|
|
line.word 0x0 "SDSTATUS,SD Status Register"
|
|
bitfld.word 0x0 15. "MAL4,Manchester locked status for filter module 4." "0,1"
|
|
bitfld.word 0x0 14. "MAL3,Manchester locked status for filter module 3." "0,1"
|
|
bitfld.word 0x0 13. "MAL2,Manchester locked status for filter module 2." "0,1"
|
|
bitfld.word 0x0 12. "MAL1,Manchester locked status for filter module 1." "0,1"
|
|
bitfld.word 0x0 11. "MS4,Manchester clock decode phase complete for filter module 4." "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "MS3,Manchester clock decode phase complete for filter module 3." "0,1"
|
|
bitfld.word 0x0 9. "MS2,Manchester clock decode phase complete for filter module 2." "0,1"
|
|
bitfld.word 0x0 8. "MS1,Manchester clock decode phase complete for filter module 1." "0,1"
|
|
bitfld.word 0x0 3. "HZ4,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x0 2. "HZ3,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "HZ2,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
bitfld.word 0x0 0. "HZ1,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
group.word 0x10++0xB
|
|
line.word 0x0 "SDCTLPARM1,Control Parameter Register for Ch1"
|
|
hexmask.word.byte 0x0 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x0 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x0 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x0 3. "SDCLKSEL,SD1 Clock source select." "0,1"
|
|
bitfld.word 0x0 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x1 "SDDFPARM1,Data Filter Parameter Register for Ch1"
|
|
bitfld.word 0x1 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x1 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x1 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x1 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x1 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x2 "SDDPARM1,Data Parameter Register for Ch1"
|
|
hexmask.word.byte 0x2 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x2 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x3 "SDFLT1CMPH1,High-level Threshold Register for Ch1"
|
|
hexmask.word 0x3 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x4 "SDFLT1CMPL1,Low-level Threshold Register for Ch1"
|
|
hexmask.word 0x4 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0x5 "SDCPARM1,Comparator Filter Parameter Register for Ch1"
|
|
bitfld.word 0x5 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x5 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0x5 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x5 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0x5 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x5 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x5 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x5 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0x5 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x16++0x7
|
|
line.long 0x0 "SDDATA1,Data Filter Data Register (16 or 32bit) for Ch1"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO1,Filter Data FIFO Output(32b) for Ch1"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x1A++0x1
|
|
line.word 0x0 "SDCDATA1,Comparator Filter Data Register (16b) for Ch1"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x1B++0x15
|
|
line.word 0x0 "SDFLT1CMPH2,Second high level threhold for CH1"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT1CMPHZ,High-level (Z) Threshold Register for Ch1"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL1,FIFO Control Register for Ch1"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC1,SD Filter Sync control for Ch1"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT1CMPL2,Second low level threhold for CH1"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
line.word 0x5 "SDCTLPARM2,Control Parameter Register for Ch2"
|
|
hexmask.word.byte 0x5 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x5 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x5 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x5 3. "SDCLKSEL,SD2 Clock source select." "0,1"
|
|
bitfld.word 0x5 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x5 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x6 "SDDFPARM2,Data Filter Parameter Register for Ch2"
|
|
bitfld.word 0x6 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x6 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x6 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x6 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x6 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x7 "SDDPARM2,Data Parameter Register for Ch2"
|
|
hexmask.word.byte 0x7 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x7 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x8 "SDFLT2CMPH1,High-level Threshold Register for Ch2"
|
|
hexmask.word 0x8 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x9 "SDFLT2CMPL1,Low-level Threshold Register for Ch2"
|
|
hexmask.word 0x9 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0xA "SDCPARM2,Comparator Filter Parameter Register for Ch2"
|
|
bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0xA 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0xA 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0xA 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x26++0x7
|
|
line.long 0x0 "SDDATA2,Data Filter Data Register (16 or 32bit) for Ch2"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO2,Filter Data FIFO Output(32b) for Ch2"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x2A++0x1
|
|
line.word 0x0 "SDCDATA2,Comparator Filter Data Register (16b) for Ch2"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x2B++0x15
|
|
line.word 0x0 "SDFLT2CMPH2,Second high level threhold for CH2"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT2CMPHZ,High-level (Z) Threshold Register for Ch2"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL2,FIFO Control Register for Ch2"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC2,SD Filter Sync control for Ch2"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT2CMPL2,Second low level threhold for CH2"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
line.word 0x5 "SDCTLPARM3,Control Parameter Register for Ch3"
|
|
hexmask.word.byte 0x5 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x5 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x5 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x5 3. "SDCLKSEL,SD3 Clock source select." "0,1"
|
|
bitfld.word 0x5 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x5 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x6 "SDDFPARM3,Data Filter Parameter Register for Ch3"
|
|
bitfld.word 0x6 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x6 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x6 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x6 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x6 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x7 "SDDPARM3,Data Parameter Register for Ch3"
|
|
hexmask.word.byte 0x7 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x7 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x8 "SDFLT3CMPH1,High-level Threshold Register for Ch3"
|
|
hexmask.word 0x8 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x9 "SDFLT3CMPL1,Low-level Threshold Register for Ch3"
|
|
hexmask.word 0x9 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0xA "SDCPARM3,Comparator Filter Parameter Register for Ch3"
|
|
bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0xA 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0xA 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0xA 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x36++0x7
|
|
line.long 0x0 "SDDATA3,Data Filter Data Register (16 or 32bit) for Ch3"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO3,Filter Data FIFO Output(32b) for Ch3"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x3A++0x1
|
|
line.word 0x0 "SDCDATA3,Comparator Filter Data Register (16b) for Ch3"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x3B++0x15
|
|
line.word 0x0 "SDFLT3CMPH2,Second high level threhold for CH3"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT3CMPHZ,High-level (Z) Threshold Register for Ch3"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL3,FIFO Control Register for Ch3"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC3,SD Filter Sync control for Ch3"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT3CMPL2,Second low level threhold for CH3"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
line.word 0x5 "SDCTLPARM4,Control Parameter Register for Ch4"
|
|
hexmask.word.byte 0x5 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x5 6. "SDDATASYNC,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x5 4. "SDCLKSYNC,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x5 3. "SDCLKSEL,SD4 Clock source select." "0,1"
|
|
bitfld.word 0x5 2. "PLLCLKSEL,PLL clock select" "0,1"
|
|
newline
|
|
bitfld.word 0x5 0.--1. "MOD,Modulator clocking modes" "0,1,2,3"
|
|
line.word 0x6 "SDDFPARM4,Data Filter Parameter Register for Ch4"
|
|
bitfld.word 0x6 12. "SDSYNCEN,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x6 10.--11. "SST,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x6 9. "AE,Ack Enable" "0,1"
|
|
bitfld.word 0x6 8. "FEN,Filter Enable" "0,1"
|
|
hexmask.word.byte 0x6 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
line.word 0x7 "SDDPARM4,Data Parameter Register for Ch4"
|
|
hexmask.word.byte 0x7 11.--15. 1. "SH,Shift Control (# bits to shift in 16b mode)"
|
|
bitfld.word 0x7 10. "DR,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
line.word 0x8 "SDFLT4CMPH1,High-level Threshold Register for Ch4"
|
|
hexmask.word 0x8 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
line.word 0x9 "SDFLT4CMPL1,Low-level Threshold Register for Ch4"
|
|
hexmask.word 0x9 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
line.word 0xA "SDCPARM4,Comparator Filter Parameter Register for Ch4"
|
|
bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0xA 13. "CEN,Comparator Enable" "0,1"
|
|
bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable" "0,1"
|
|
bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7.--8. "CS1_CS0,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0xA 6. "EN_CEVT2,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0xA 5. "EN_CEVT1,CEVT1 Interrupt enable." "0,1"
|
|
hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversample Ratio. Actual rate COSR+1"
|
|
rgroup.long 0x46++0x7
|
|
line.long 0x0 "SDDATA4,Data Filter Data Register (16 or 32bit) for Ch4"
|
|
hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
line.long 0x2 "SDDATFIFO4,Filter Data FIFO Output(32b) for Ch4"
|
|
hexmask.long.word 0x2 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode"
|
|
hexmask.long.word 0x2 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word 0x4A++0x1
|
|
line.word 0x0 "SDCDATA4,Comparator Filter Data Register (16b) for Ch4"
|
|
hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only"
|
|
group.word 0x4B++0x9
|
|
line.word 0x0 "SDFLT4CMPH2,Second high level threhold for CH4"
|
|
hexmask.word 0x0 0.--14. 1. "HLT2,Second High level threshold."
|
|
line.word 0x1 "SDFLT4CMPHZ,High-level (Z) Threshold Register for Ch4"
|
|
hexmask.word 0x1 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
line.word 0x2 "SDFIFOCTL4,FIFO Control Register for Ch4"
|
|
bitfld.word 0x2 15. "OVFIEN,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x2 14. "DRINTSEL,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x2 13. "FFEN,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x2 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1"
|
|
hexmask.word.byte 0x2 6.--10. 1. "SDFFST,SDFIFO Status"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "SDFFIL,SDFIFO Interrupt Level"
|
|
line.word 0x3 "SDSYNC4,SD Filter Sync control for Ch4"
|
|
bitfld.word 0x3 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x3 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x3 8. "WTSYNCLR,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x3 7. "WTSYNFLG,Wait-for-Sync Flag" "0,1"
|
|
bitfld.word 0x3 6. "WTSYNCEN,Wait-for-Sync Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--5. 1. "SYNCSEL,SDSYNC Source Select"
|
|
line.word 0x4 "SDFLT4CMPL2,Second low level threhold for CH4"
|
|
hexmask.word 0x4 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word 0x60++0x9
|
|
line.word 0x0 "SDCOMP1CTL,SD Comparator event filter1 Control Register"
|
|
bitfld.word 0x0 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x0 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x1 "SDCOMP1EVT2FLTCTL,COMPL/CEVT2 Digital filter1 Control Register"
|
|
bitfld.word 0x1 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x1 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x1 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x2 "SDCOMP1EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x2 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x3 "SDCOMP1EVT1FLTCTL,COMPH/CEVT1 Digital filter1 Control Register"
|
|
bitfld.word 0x3 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x3 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x3 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x4 "SDCOMP1EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x67++0xB
|
|
line.word 0x0 "SDCOMP1LOCK,SD compartor event filter1 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP1CTL,COMPCTL Lock" "0,1"
|
|
line.word 0x1 "SDCOMP2CTL,SD Comparator event filter2 Control Register"
|
|
bitfld.word 0x1 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x2 "SDCOMP2EVT2FLTCTL,COMPL/CEVT2 Digital filter2 Control Register"
|
|
bitfld.word 0x2 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x2 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x3 "SDCOMP2EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x3 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x4 "SDCOMP2EVT1FLTCTL,COMPH/CEVT1 Digital filter2 Control Register"
|
|
bitfld.word 0x4 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x4 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x5 "SDCOMP2EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x5 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x6F++0xB
|
|
line.word 0x0 "SDCOMP2LOCK,SD compartor event filter2 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP2CTL,COMPCTL Lock" "0,1"
|
|
line.word 0x1 "SDCOMP3CTL,SD Comparator event filter3 Control Register"
|
|
bitfld.word 0x1 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x2 "SDCOMP3EVT2FLTCTL,COMPL/CEVT2 Digital filter3 Control Register"
|
|
bitfld.word 0x2 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x2 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x3 "SDCOMP3EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x3 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x4 "SDCOMP3EVT1FLTCTL,COMPH/CEVT1 Digital filter3 Control Register"
|
|
bitfld.word 0x4 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x4 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x5 "SDCOMP3EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x5 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x77++0xB
|
|
line.word 0x0 "SDCOMP3LOCK,SD compartor event filter3 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP3CTL,COMPCTL Lock" "0,1"
|
|
line.word 0x1 "SDCOMP4CTL,SD Comparator event filter4 Control Register"
|
|
bitfld.word 0x1 10.--11. "CEVT2DIGFILTSEL,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x1 2.--3. "CEVT1DIGFILTSEL,High Comparator Trip Select" "0,1,2,3"
|
|
line.word 0x2 "SDCOMP4EVT2FLTCTL,COMPL/CEVT2 Digital filter4 Control Register"
|
|
bitfld.word 0x2 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x2 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x3 "SDCOMP4EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x3 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
line.word 0x4 "SDCOMP4EVT1FLTCTL,COMPH/CEVT1 Digital filter4 Control Register"
|
|
bitfld.word 0x4 15. "FILINIT,Filter Initialization Bit" "0,1"
|
|
hexmask.word.byte 0x4 9.--13. 1. "THRESH,Majority Voting Threshold"
|
|
hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Sample Window"
|
|
line.word 0x5 "SDCOMP4EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x5 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word 0x7F++0x1
|
|
line.word 0x0 "SDCOMP4LOCK,SD compartor event filter4 Lock Register"
|
|
bitfld.word 0x0 3. "COMP,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x0 0. "SDCOMP4CTL,COMPCTL Lock" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base d:0x0
|
|
tree "SPIA"
|
|
base d:0x6100
|
|
group.word 0x0++0x7
|
|
line.word 0x0 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x0 7. "SPISWRESET,SPI Software Reset" "0,1"
|
|
bitfld.word 0x0 6. "CLKPOLARITY,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x0 5. "HS_MODE,High Speed mode control" "0,1"
|
|
bitfld.word 0x0 4. "SPILBK,SPI Loopback" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "SPICHAR,Character Length Control"
|
|
line.word 0x1 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x1 4. "OVERRUNINTENA,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x1 3. "CLK_PHASE,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x1 2. "MASTER_SLAVE,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x1 1. "TALK,Master/Slave Transmit Enable" "0,1"
|
|
bitfld.word 0x1 0. "SPIINTENA,SPI Interupt Enable" "0,1"
|
|
line.word 0x2 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x2 7. "OVERRUN_FLAG,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x2 6. "INT_FLAG,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x2 5. "BUFFULL_FLAG,SPI Transmit Buffer Full Flag" "0,1"
|
|
line.word 0x4 "SPIBRR,SPI Baud Rate Register"
|
|
hexmask.word.byte 0x4 0.--6. 1. "SPI_BIT_RATE,SPI Bit Rate Control"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "ERXBn,Emulation Buffer Received Data"
|
|
line.word 0x1 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
hexmask.word 0x1 0.--15. 1. "RXBn,Received Data"
|
|
group.word 0x8++0x9
|
|
line.word 0x0 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "TXBn,Transmit Data Buffer"
|
|
line.word 0x1 "SPIDAT,SPI Serial Data Register"
|
|
hexmask.word 0x1 0.--15. 1. "SDATn,Serial Data Shift Register"
|
|
line.word 0x2 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x2 15. "SPIRST,SPI Reset" "0,1"
|
|
bitfld.word 0x2 14. "SPIFFENA,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x2 13. "TXFIFO,TXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "TXFFST,Transmit FIFO Status"
|
|
rbitfld.word 0x2 7. "TXFFINT,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x2 6. "TXFFINTCLR,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x2 5. "TXFFIENA,TXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "TXFFIL,TXFIFO Interrupt Level"
|
|
line.word 0x3 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x3 15. "RXFFOVF,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x3 14. "RXFFOVFCLR,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x3 13. "RXFIFORESET,RXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x3 8.--12. 1. "RXFFST,Receive FIFO Status"
|
|
rbitfld.word 0x3 7. "RXFFINT,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x3 6. "RXFFINTCLR,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x3 5. "RXFFIENA,RXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--4. 1. "RXFFIL,RXFIFO Interrupt Level"
|
|
line.word 0x4 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word.byte 0x4 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x0 5. "SOFT,Soft emulation mode" "0,1"
|
|
bitfld.word 0x0 4. "FREE,Free emulation mode" "0,1"
|
|
bitfld.word 0x0 1. "STEINV,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x0 0. "TRIWIRE,3-wire mode select bit" "0,1"
|
|
tree.end
|
|
tree "SPIB"
|
|
base d:0x6110
|
|
group.word 0x0++0x7
|
|
line.word 0x0 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x0 7. "SPISWRESET,SPI Software Reset" "0,1"
|
|
bitfld.word 0x0 6. "CLKPOLARITY,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x0 5. "HS_MODE,High Speed mode control" "0,1"
|
|
bitfld.word 0x0 4. "SPILBK,SPI Loopback" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "SPICHAR,Character Length Control"
|
|
line.word 0x1 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x1 4. "OVERRUNINTENA,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x1 3. "CLK_PHASE,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x1 2. "MASTER_SLAVE,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x1 1. "TALK,Master/Slave Transmit Enable" "0,1"
|
|
bitfld.word 0x1 0. "SPIINTENA,SPI Interupt Enable" "0,1"
|
|
line.word 0x2 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x2 7. "OVERRUN_FLAG,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x2 6. "INT_FLAG,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x2 5. "BUFFULL_FLAG,SPI Transmit Buffer Full Flag" "0,1"
|
|
line.word 0x4 "SPIBRR,SPI Baud Rate Register"
|
|
hexmask.word.byte 0x4 0.--6. 1. "SPI_BIT_RATE,SPI Bit Rate Control"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "ERXBn,Emulation Buffer Received Data"
|
|
line.word 0x1 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
hexmask.word 0x1 0.--15. 1. "RXBn,Received Data"
|
|
group.word 0x8++0x9
|
|
line.word 0x0 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "TXBn,Transmit Data Buffer"
|
|
line.word 0x1 "SPIDAT,SPI Serial Data Register"
|
|
hexmask.word 0x1 0.--15. 1. "SDATn,Serial Data Shift Register"
|
|
line.word 0x2 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x2 15. "SPIRST,SPI Reset" "0,1"
|
|
bitfld.word 0x2 14. "SPIFFENA,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x2 13. "TXFIFO,TXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "TXFFST,Transmit FIFO Status"
|
|
rbitfld.word 0x2 7. "TXFFINT,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x2 6. "TXFFINTCLR,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x2 5. "TXFFIENA,TXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "TXFFIL,TXFIFO Interrupt Level"
|
|
line.word 0x3 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x3 15. "RXFFOVF,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x3 14. "RXFFOVFCLR,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x3 13. "RXFIFORESET,RXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x3 8.--12. 1. "RXFFST,Receive FIFO Status"
|
|
rbitfld.word 0x3 7. "RXFFINT,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x3 6. "RXFFINTCLR,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x3 5. "RXFFIENA,RXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--4. 1. "RXFFIL,RXFIFO Interrupt Level"
|
|
line.word 0x4 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word.byte 0x4 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x0 5. "SOFT,Soft emulation mode" "0,1"
|
|
bitfld.word 0x0 4. "FREE,Free emulation mode" "0,1"
|
|
bitfld.word 0x0 1. "STEINV,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x0 0. "TRIWIRE,3-wire mode select bit" "0,1"
|
|
tree.end
|
|
tree "SPIC"
|
|
base d:0x6120
|
|
group.word 0x0++0x7
|
|
line.word 0x0 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x0 7. "SPISWRESET,SPI Software Reset" "0,1"
|
|
bitfld.word 0x0 6. "CLKPOLARITY,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x0 5. "HS_MODE,High Speed mode control" "0,1"
|
|
bitfld.word 0x0 4. "SPILBK,SPI Loopback" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "SPICHAR,Character Length Control"
|
|
line.word 0x1 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x1 4. "OVERRUNINTENA,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x1 3. "CLK_PHASE,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x1 2. "MASTER_SLAVE,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x1 1. "TALK,Master/Slave Transmit Enable" "0,1"
|
|
bitfld.word 0x1 0. "SPIINTENA,SPI Interupt Enable" "0,1"
|
|
line.word 0x2 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x2 7. "OVERRUN_FLAG,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x2 6. "INT_FLAG,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x2 5. "BUFFULL_FLAG,SPI Transmit Buffer Full Flag" "0,1"
|
|
line.word 0x4 "SPIBRR,SPI Baud Rate Register"
|
|
hexmask.word.byte 0x4 0.--6. 1. "SPI_BIT_RATE,SPI Bit Rate Control"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "ERXBn,Emulation Buffer Received Data"
|
|
line.word 0x1 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
hexmask.word 0x1 0.--15. 1. "RXBn,Received Data"
|
|
group.word 0x8++0x9
|
|
line.word 0x0 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "TXBn,Transmit Data Buffer"
|
|
line.word 0x1 "SPIDAT,SPI Serial Data Register"
|
|
hexmask.word 0x1 0.--15. 1. "SDATn,Serial Data Shift Register"
|
|
line.word 0x2 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x2 15. "SPIRST,SPI Reset" "0,1"
|
|
bitfld.word 0x2 14. "SPIFFENA,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x2 13. "TXFIFO,TXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "TXFFST,Transmit FIFO Status"
|
|
rbitfld.word 0x2 7. "TXFFINT,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x2 6. "TXFFINTCLR,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x2 5. "TXFFIENA,TXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "TXFFIL,TXFIFO Interrupt Level"
|
|
line.word 0x3 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x3 15. "RXFFOVF,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x3 14. "RXFFOVFCLR,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x3 13. "RXFIFORESET,RXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x3 8.--12. 1. "RXFFST,Receive FIFO Status"
|
|
rbitfld.word 0x3 7. "RXFFINT,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x3 6. "RXFFINTCLR,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x3 5. "RXFFIENA,RXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--4. 1. "RXFFIL,RXFIFO Interrupt Level"
|
|
line.word 0x4 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word.byte 0x4 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x0 5. "SOFT,Soft emulation mode" "0,1"
|
|
bitfld.word 0x0 4. "FREE,Free emulation mode" "0,1"
|
|
bitfld.word 0x0 1. "STEINV,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x0 0. "TRIWIRE,3-wire mode select bit" "0,1"
|
|
tree.end
|
|
tree "SPID"
|
|
base d:0x6130
|
|
group.word 0x0++0x7
|
|
line.word 0x0 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x0 7. "SPISWRESET,SPI Software Reset" "0,1"
|
|
bitfld.word 0x0 6. "CLKPOLARITY,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x0 5. "HS_MODE,High Speed mode control" "0,1"
|
|
bitfld.word 0x0 4. "SPILBK,SPI Loopback" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "SPICHAR,Character Length Control"
|
|
line.word 0x1 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x1 4. "OVERRUNINTENA,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x1 3. "CLK_PHASE,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x1 2. "MASTER_SLAVE,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x1 1. "TALK,Master/Slave Transmit Enable" "0,1"
|
|
bitfld.word 0x1 0. "SPIINTENA,SPI Interupt Enable" "0,1"
|
|
line.word 0x2 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x2 7. "OVERRUN_FLAG,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x2 6. "INT_FLAG,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x2 5. "BUFFULL_FLAG,SPI Transmit Buffer Full Flag" "0,1"
|
|
line.word 0x4 "SPIBRR,SPI Baud Rate Register"
|
|
hexmask.word.byte 0x4 0.--6. 1. "SPI_BIT_RATE,SPI Bit Rate Control"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "ERXBn,Emulation Buffer Received Data"
|
|
line.word 0x1 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
hexmask.word 0x1 0.--15. 1. "RXBn,Received Data"
|
|
group.word 0x8++0x9
|
|
line.word 0x0 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
hexmask.word 0x0 0.--15. 1. "TXBn,Transmit Data Buffer"
|
|
line.word 0x1 "SPIDAT,SPI Serial Data Register"
|
|
hexmask.word 0x1 0.--15. 1. "SDATn,Serial Data Shift Register"
|
|
line.word 0x2 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x2 15. "SPIRST,SPI Reset" "0,1"
|
|
bitfld.word 0x2 14. "SPIFFENA,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x2 13. "TXFIFO,TXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x2 8.--12. 1. "TXFFST,Transmit FIFO Status"
|
|
rbitfld.word 0x2 7. "TXFFINT,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x2 6. "TXFFINTCLR,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x2 5. "TXFFIENA,TXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x2 0.--4. 1. "TXFFIL,TXFIFO Interrupt Level"
|
|
line.word 0x3 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x3 15. "RXFFOVF,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x3 14. "RXFFOVFCLR,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x3 13. "RXFIFORESET,RXFIFO Reset" "0,1"
|
|
hexmask.word.byte 0x3 8.--12. 1. "RXFFST,Receive FIFO Status"
|
|
rbitfld.word 0x3 7. "RXFFINT,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x3 6. "RXFFINTCLR,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x3 5. "RXFFIENA,RXFIFO Interrupt Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x3 0.--4. 1. "RXFFIL,RXFIFO Interrupt Level"
|
|
line.word 0x4 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word.byte 0x4 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word 0xF++0x1
|
|
line.word 0x0 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x0 5. "SOFT,Soft emulation mode" "0,1"
|
|
bitfld.word 0x0 4. "FREE,Free emulation mode" "0,1"
|
|
bitfld.word 0x0 1. "STEINV,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x0 0. "TRIWIRE,3-wire mode select bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "SSI (Synchronous Serial Interface)"
|
|
base d:0x40008000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SSICR0,SSI Control 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCR,SSI Serial Clock Rate"
|
|
bitfld.long 0x0 7. "SPH,SSI Serial clock PHase" "0,1"
|
|
bitfld.long 0x0 6. "SPO,SSI Serial clock POlarity" "0,1"
|
|
bitfld.long 0x0 4.--5. "FRF,SSI FRame Format Select" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSS,SSI Data Size Select"
|
|
line.long 0x4 "SSICR1,SSI Control 1"
|
|
bitfld.long 0x4 10. "FSSHLDFRM,FSS Hold Frame" "0,1"
|
|
bitfld.long 0x4 9. "HSCLKEN,High Speed Clock Enable" "0,1"
|
|
bitfld.long 0x4 8. "DIR,SSI Direction of Operation" "0,1"
|
|
bitfld.long 0x4 4. "EOT,End of Transmission" "0,1"
|
|
bitfld.long 0x4 2. "MS,SSI Master/Slave Select" "0,1"
|
|
bitfld.long 0x4 1. "SSE,SSI Synchronous Serial Port Enable" "0,1"
|
|
bitfld.long 0x4 0. "LBM,SSI Loopback Mode" "0,1"
|
|
line.long 0x8 "SSIDR,SSI Data"
|
|
hexmask.long.word 0x8 0.--15. 1. "DATA,SSI Receive/Transmit Data"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SSISR,SSI Status"
|
|
bitfld.long 0x0 4. "BSY,SSI Busy Bit" "0,1"
|
|
bitfld.long 0x0 3. "RFF,SSI Receive FIFO Full" "0,1"
|
|
bitfld.long 0x0 2. "RNE,SSI Receive FIFO Not Empty" "0,1"
|
|
bitfld.long 0x0 1. "TNF,SSI Transmit FIFO Not Full" "0,1"
|
|
bitfld.long 0x0 0. "TFE,SSI Transmit FIFO Empty" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SSICPSR,SSI Clock Prescale"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSDVSR,SSI Clock Prescale Divisor"
|
|
line.long 0x4 "SSIIM,SSI Interrupt Mask"
|
|
bitfld.long 0x4 6. "EOTIM,End of Transmit Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 5. "DMATXIM,SSI Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "DMARXIM,SSI Receive DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "TXIM,SSI Transmit FIFO Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 2. "RXIM,SSI Receive FIFO Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "RTIM,SSI Receive Time-Out Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 0. "RORIM,SSI Receive Overrun Interrupt Mask" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "SSIRIS,SSI Raw Interrupt Status"
|
|
bitfld.long 0x0 6. "EOTRIS,End of Transmit Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "DMATXRIS,SSI Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "DMARXRIS,SSI Receive DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "TXRIS,SSI Transmit FIFO Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "RXRIS,SSI Receive FIFO Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "RTRIS,SSI Receive Time-Out Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 0. "RORRIS,SSI Receive Overrun Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "SSIMIS,SSI Masked Interrupt Status"
|
|
bitfld.long 0x4 6. "EOTMIS,End of Transmit Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "DMATXMIS,SSI Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "DMARXMIS,SSI Receive DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "TXMIS,SSI Transmit FIFO Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "RXMIS,SSI Receive FIFO Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "RTMIS,SSI Receive Time-Out Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "RORMIS,SSI Receive Overrun Masked Interrupt Status" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SSIICR,SSI Interrupt Clear"
|
|
bitfld.long 0x0 6. "EOTIC,End of Transmit Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 5. "DMATXIC,SSI Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "DMARXIC,SSI Receive DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "RTIC,SSI Receive Time-Out Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 0. "RORIC,SSI Receive Overrun Interrupt Clear" "0,1"
|
|
line.long 0x4 "SSIDMACTL,SSI DMA Control"
|
|
bitfld.long 0x4 1. "TXDMAE,Transmit DMA Enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAE,Receive DMA Enable" "0,1"
|
|
rgroup.long 0xFB0++0x3
|
|
line.long 0x0 "SSIPV,SSI Peripheral Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MAJOR,Major Revision"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MINOR,Minor Revision"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "SSIPP,SSI Peripheral Properties"
|
|
bitfld.long 0x0 3. "FSSHLDFRM,SSInFss Hold Frame Capability" "0,1"
|
|
bitfld.long 0x0 1.--2. "MODE,Mode of Operation" "0,1,2,3"
|
|
bitfld.long 0x0 0. "HSCLK,High Speed Capability" "0,1"
|
|
group.long 0xFC4++0x3
|
|
line.long 0x0 "SSIPC,SSI Peripheral Configuration"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x0 "SSIPeriphID4,SSI Peripheral Identification 4"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID4,SSI Peripheral ID Register"
|
|
line.long 0x4 "SSIPeriphID5,SSI Peripheral Identification 5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PID5,SSI Peripheral ID Register"
|
|
line.long 0x8 "SSIPeriphID6,SSI Peripheral Identification 6"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PID6,SSI Peripheral ID Register"
|
|
line.long 0xC "SSIPeriphID7,SSI Peripheral Identification 7"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PID7,SSI Peripheral ID Register"
|
|
line.long 0x10 "SSIPeriphID0,SSI Peripheral Identification 0"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PID0,SSI Peripheral ID Register"
|
|
line.long 0x14 "SSIPeriphID1,SSI Peripheral Identification 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PID1,SSI Peripheral ID Register"
|
|
line.long 0x18 "SSIPeriphID2,SSI Peripheral Identification 2"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PID2,SSI Peripheral ID Register"
|
|
line.long 0x1C "SSIPeriphID3,SSI Peripheral Identification 3"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PID3,SSI Peripheral ID Register"
|
|
line.long 0x20 "SSIPCellID0,SSI PrimeCell Identification 0"
|
|
hexmask.long.byte 0x20 0.--7. 1. "CID0,SSI PrimeCell ID Register"
|
|
line.long 0x24 "SSIPCellID1,SSI PrimeCell Identification 1"
|
|
hexmask.long.byte 0x24 0.--7. 1. "CID1,SSI PrimeCell ID Register"
|
|
line.long 0x28 "SSIPCellID2,SSI PrimeCell Identification 2"
|
|
hexmask.long.byte 0x28 0.--7. 1. "CID2,SSI PrimeCell ID Register"
|
|
line.long 0x2C "SSIPCellID3,SSI PrimeCell Identification 3"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "CID3,SSI PrimeCell ID Register"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "SYSCTRL (System Control)"
|
|
base d:0x0
|
|
tree "ACCESSPROTECTION"
|
|
base d:0x5F500
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "NMAVFLG,Non-Master Access Violation Flag Register"
|
|
bitfld.long 0x0 10. "DMAREAD,Non Master DMA read Access Violation Flag" "0,1"
|
|
bitfld.long 0x0 6. "CLA1FETCH,Non Master CLA1 Fetch Access Violation Flag" "0,1"
|
|
bitfld.long 0x0 5. "CLA1WRITE,Non Master CLA1 Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x0 4. "CLA1READ,Non Master CLA1 Read Access Violation Flag" "0,1"
|
|
bitfld.long 0x0 3. "DMAWRITE,Non Master DMA Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x0 2. "CPUFETCH,Non Master CPU Fetch Access Violation Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CPUWRITE,Non Master CPU Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x0 0. "CPUREAD,Non Master CPU Read Access Violation Flag" "0,1"
|
|
group.long 0x2++0xB
|
|
line.long 0x0 "NMAVSET,Non-Master Access Violation Flag Set Register"
|
|
bitfld.long 0x0 10. "DMAREAD,Non Master DMA read Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 6. "CLA1FETCH,Non Master CLA1 Fetch Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 5. "CLA1WRITE,Non Master CLA1 Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 4. "CLA1READ,Non Master CLA1 Read Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 3. "DMAWRITE,Non Master DMA Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 2. "CPUFETCH,Non Master CPU Fetch Access Violation Flag Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CPUWRITE,Non Master CPU Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 0. "CPUREAD,Non Master CPU Read Access Violation Flag Set" "0,1"
|
|
line.long 0x2 "NMAVCLR,Non-Master Access Violation Flag Clear Register"
|
|
bitfld.long 0x2 10. "DMAREAD,Non Master DMA read Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 6. "CLA1FETCH,Non Master CLA1 Fetch Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 5. "CLA1WRITE,Non Master CLA1 Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 4. "CLA1READ,Non Master CLA1 Read Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 3. "DMAWRITE,Non Master DMA Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 2. "CPUFETCH,Non Master CPU Fetch Access Violation Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "CPUWRITE,Non Master CPU Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 0. "CPUREAD,Non Master CPU Read Access Violation Flag Clear" "0,1"
|
|
line.long 0x4 "NMAVINTEN,Non-Master Access Violation Interrupt Enable Register"
|
|
bitfld.long 0x4 10. "DMAREAD,Non Master DMA Read Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "CLA1FETCH,Non Master CLA1 Fetch Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 5. "CLA1WRITE,Non Master CLA1 Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "CLA1READ,Non Master CLA1 Read Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 3. "DMAWRITE,Non Master DMA Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CPUFETCH,Non Master CPU Fetch Access Violation Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CPUWRITE,Non Master CPU Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "CPUREAD,Non Master CPU Read Access Violation Interrupt Enable" "0,1"
|
|
rgroup.long 0x8++0x1B
|
|
line.long 0x0 "NMCPURDAVADDR,Non-Master CPU Read Access Violation Address"
|
|
hexmask.long 0x0 0.--31. 1. "NMCPURDAVADDR,Non Master CPU read access violation address register."
|
|
line.long 0x2 "NMCPUWRAVADDR,Non-Master CPU Write Access Violation Address"
|
|
hexmask.long 0x2 0.--31. 1. "NMCPUWRAVADDR,Non Master CPU write access violation address register."
|
|
line.long 0x4 "NMCPUFAVADDR,Non-Master CPU Fetch Access Violation Address"
|
|
hexmask.long 0x4 0.--31. 1. "NMCPUFAVADDR,Non Master CPU fetch access violation address register."
|
|
line.long 0x6 "NMDMAWRAVADDR,Non-Master DMA Write Access Violation Address"
|
|
hexmask.long 0x6 0.--31. 1. "NMDMAWRAVADDR,Non Master DMA write access violation address register."
|
|
line.long 0x8 "NMCLA1RDAVADDR,Non-Master CLA1 Read Access Violation Address"
|
|
hexmask.long 0x8 0.--31. 1. "NMCLA1RDAVADDR,Non Master CLA1 read access violation address register."
|
|
line.long 0xA "NMCLA1WRAVADDR,Non-Master CLA1 Write Access Violation Address"
|
|
hexmask.long 0xA 0.--31. 1. "NMCLA1WRAVADDR,Non Master CLA1 write access violation address register."
|
|
line.long 0xC "NMCLA1FAVADDR,Non-Master CLA1 Fetch Access Violation Address"
|
|
hexmask.long 0xC 0.--31. 1. "NMCLA1FAVADDR,Non Master CLA1 fetch access violation address register."
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "NMDMARDAVADDR,Non-Master DMA Read Access Violation Address"
|
|
hexmask.long 0x0 0.--31. 1. "NMDMARDAVADDR,Non Master DMA read access violation address register."
|
|
line.long 0x4 "MAVFLG,Master Access Violation Flag Register"
|
|
bitfld.long 0x4 2. "DMAWRITE,Master DMA Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x4 1. "CPUWRITE,Master CPU Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x4 0. "CPUFETCH,Master CPU Fetch Access Violation Flag" "0,1"
|
|
group.long 0x22++0xB
|
|
line.long 0x0 "MAVSET,Master Access Violation Flag Set Register"
|
|
bitfld.long 0x0 2. "DMAWRITE,Master DMA Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 1. "CPUWRITE,Master CPU Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x0 0. "CPUFETCH,Master CPU Fetch Access Violation Flag Set" "0,1"
|
|
line.long 0x2 "MAVCLR,Master Access Violation Flag Clear Register"
|
|
bitfld.long 0x2 2. "DMAWRITE,Master DMA Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 1. "CPUWRITE,Master CPU Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x2 0. "CPUFETCH,Master CPU Fetch Access Violation Flag Clear" "0,1"
|
|
line.long 0x4 "MAVINTEN,Master Access Violation Interrupt Enable Register"
|
|
bitfld.long 0x4 2. "DMAWRITE,Master DMA Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 1. "CPUWRITE,Master CPU Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "CPUFETCH,Master CPU Fetch Access Violation Interrupt Enable" "0,1"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "MCPUFAVADDR,Master CPU Fetch Access Violation Address"
|
|
hexmask.long 0x0 0.--31. 1. "MCPUFAVADDR,Master CPU fetch access violation address register."
|
|
line.long 0x2 "MCPUWRAVADDR,Master CPU Write Access Violation Address"
|
|
hexmask.long 0x2 0.--31. 1. "MCPUWRAVADDR,Master CPU write access violation address register."
|
|
line.long 0x4 "MDMAWRAVADDR,Master DMA Write Access Violation Address"
|
|
hexmask.long 0x4 0.--31. 1. "MDMAWRAVADDR,Master DMA write access violation address register."
|
|
tree.end
|
|
tree "CLKCFG"
|
|
base d:0x5D200
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CLKSEM,Clock Control Semaphore Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x0 0.--1. "SEM,Semaphore for CLKCFG Ownership by CPU1 or CPU2" "0,1,2,3"
|
|
line.long 0x2 "CLKCFGLOCK1,Lock bit for CLKCFG registers"
|
|
bitfld.long 0x2 18. "CMCLKCTL,Lock bit for CMCLKCTL register" "0,1"
|
|
bitfld.long 0x2 17. "ETHERCATCLKCTL,Lock bit for ETHERCATCLKCTL register" "0,1"
|
|
bitfld.long 0x2 16. "XTALCR,Lock bit for XTALCR register" "0,1"
|
|
bitfld.long 0x2 15. "LOSPCP,Lock bit for LOSPCP register" "0,1"
|
|
bitfld.long 0x2 14. "CLBCLKCTL,Lock bit for CLBCLKCTL register" "0,1"
|
|
bitfld.long 0x2 13. "PERCLKDIVSEL,Lock bit for PERCLKDIVSEL register" "0,1"
|
|
newline
|
|
bitfld.long 0x2 12. "AUXCLKDIVSEL,Lock bit for AUXCLKDIVSEL register" "0,1"
|
|
bitfld.long 0x2 11. "SYSCLKDIVSEL,Lock bit for SYSCLKDIVSEL register" "0,1"
|
|
bitfld.long 0x2 10. "AUXPLLMULT,Lock bit for AUXPLLMULT register" "0,1"
|
|
bitfld.long 0x2 7. "AUXPLLCTL1,Lock bit for AUXPLLCTL1 register" "0,1"
|
|
bitfld.long 0x2 6. "SYSPLLMULT,Lock bit for SYSPLLMULT register" "0,1"
|
|
bitfld.long 0x2 5. "SYSPLLCTL3,Lock bit for SYSPLLCTL3 register" "0,1"
|
|
newline
|
|
bitfld.long 0x2 4. "SYSPLLCTL2,Lock bit for SYSPLLCTL2 register" "0,1"
|
|
bitfld.long 0x2 3. "SYSPLLCTL1,Lock bit for SYSPLLCTL1 register" "0,1"
|
|
bitfld.long 0x2 2. "CLKSRCCTL3,Lock bit for CLKSRCCTL3 register" "0,1"
|
|
bitfld.long 0x2 1. "CLKSRCCTL2,Lock bit for CLKSRCCTL2 register" "0,1"
|
|
bitfld.long 0x2 0. "CLKSRCCTL1,Lock bit for CLKSRCCTL1 register" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CLKSRCCTL1,Clock Source Control register-1"
|
|
bitfld.long 0x0 4. "XTALOFF,Crystal (External) Oscillator Off Bit" "0,1"
|
|
bitfld.long 0x0 3. "INTOSC2OFF,Internal Oscillator 2 Off Bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "OSCCLKSRCSEL,OSCCLK Source Select Bit" "0,1,2,3"
|
|
line.long 0x2 "CLKSRCCTL2,Clock Source Control register-2"
|
|
bitfld.long 0x2 10.--11. "MCANABITCLKSEL,MCAN (global) Bit-Clock Source Select Bit" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "CANBBCLKSEL,CANB Clock Source Select Bit" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "CANABCLKSEL,CANA Clock Source Select Bit" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "AUXOSCCLKSRCSEL,AUXOSCCLK Source Select Bit" "0,1,2,3"
|
|
line.long 0x4 "CLKSRCCTL3,Clock Source Control register-3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "XCLKOUTSEL,XCLKOUT Source Select Bit"
|
|
line.long 0x6 "SYSPLLCTL1,SYSPLL Control register-1"
|
|
bitfld.long 0x6 1. "PLLCLKEN,SYSPLL bypassed or included in the PLLSYSCLK path" "0,1"
|
|
bitfld.long 0x6 0. "PLLEN,SYSPLL enable/disable bit" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SYSPLLMULT,SYSPLL Multiplier register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REFDIV,Reference Clock Divider"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ODIV,Output Clock Divider"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IMULT,SYSPLL Integer Multiplier"
|
|
rgroup.long 0x16++0x3
|
|
line.long 0x0 "SYSPLLSTS,SYSPLL Status register"
|
|
bitfld.long 0x0 1. "SLIPS,SYSPLL Slip Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "LOCKS,SYSPLL Lock Status Bit" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "AUXPLLCTL1,AUXPLL Control register-1"
|
|
bitfld.long 0x0 1. "PLLCLKEN,AUXPLL bypassed or included in the AUXPLLCLK path" "0,1"
|
|
bitfld.long 0x0 0. "PLLEN,AUXPLL enable/disable bit" "0,1"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "AUXPLLMULT,AUXPLL Multiplier register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REFDIV,Reference Clock Divider"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ODIV,Output Clock Divider"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IMULT,AUXPLL Integer Multiplier"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "AUXPLLSTS,AUXPLL Status register"
|
|
bitfld.long 0x0 1. "SLIPS,AUXPLL Slip Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "LOCKS,AUXPLL Lock Status Bit" "0,1"
|
|
group.long 0x22++0x2B
|
|
line.long 0x0 "SYSCLKDIVSEL,System Clock Divider Select register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PLLSYSCLKDIV,PLLSYSCLK Divide Select"
|
|
line.long 0x2 "AUXCLKDIVSEL,Auxillary Clock Divider Select register"
|
|
hexmask.long.byte 0x2 8.--12. 1. "MCANCLKDIV,Divider between CANFD Source Clock and CANFD Bit CLK"
|
|
bitfld.long 0x2 0.--2. "AUXPLLDIV,AUXPLLCLK Divide Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "PERCLKDIVSEL,Peripheral Clock Divider Selet register"
|
|
bitfld.long 0x4 6. "EMIF2CLKDIV,EMIF2 Clock Divide Select" "0,1"
|
|
bitfld.long 0x4 4. "EMIF1CLKDIV,EMIF1 Clock Divide Select" "0,1"
|
|
bitfld.long 0x4 0.--1. "EPWMCLKDIV,EPWM Clock Divide Select" "0,1,2,3"
|
|
line.long 0x6 "XCLKOUTDIVSEL,XCLKOUT Divider Select register"
|
|
bitfld.long 0x6 0.--1. "XCLKOUTDIV,XCLKOUT Divide Select" "0,1,2,3"
|
|
line.long 0x8 "CLBCLKCTL,CLB Clocking Control Register"
|
|
bitfld.long 0x8 23. "CLKMODECLB8,Clock mode of CLB8" "0,1"
|
|
bitfld.long 0x8 22. "CLKMODECLB7,Clock mode of CLB7" "0,1"
|
|
bitfld.long 0x8 21. "CLKMODECLB6,Clock mode of CLB6" "0,1"
|
|
bitfld.long 0x8 20. "CLKMODECLB5,Clock mode of CLB5" "0,1"
|
|
bitfld.long 0x8 19. "CLKMODECLB4,Clock mode of CLB4" "0,1"
|
|
bitfld.long 0x8 18. "CLKMODECLB3,Clock mode of CLB3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CLKMODECLB2,Clock mode of CLB2" "0,1"
|
|
bitfld.long 0x8 16. "CLKMODECLB1,Clock mode of CLB1" "0,1"
|
|
bitfld.long 0x8 4. "TILECLKDIV,CLB Tile clock divider configuration." "0,1"
|
|
bitfld.long 0x8 0.--2. "CLBCLKDIV,CLB clock divider configuration." "0,1,2,3,4,5,6,7"
|
|
line.long 0xA "LOSPCP,Low Speed Clock Source Prescalar"
|
|
bitfld.long 0xA 0.--2. "LSPCLKDIV,LSPCLK Divide Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "MCDCR,Missing Clock Detect Control Register"
|
|
bitfld.long 0xC 3. "OSCOFF,Oscillator Clock Off Bit" "0,1"
|
|
bitfld.long 0xC 2. "MCLKOFF,Missing Clock Detect Off Bit" "0,1"
|
|
bitfld.long 0xC 1. "MCLKCLR,Missing Clock Clear Bit" "0,1"
|
|
rbitfld.long 0xC 0. "MCLKSTS,Missing Clock Status Bit" "0,1"
|
|
line.long 0xE "X1CNT,10-bit Counter on X1 Clock"
|
|
bitfld.long 0xE 16. "CLR,X1 Counter Clear" "0,1"
|
|
hexmask.long.word 0xE 0.--9. 1. "X1CNT,X1 Counter"
|
|
line.long 0x10 "XTALCR,XTAL Control Register"
|
|
bitfld.long 0x10 1. "SE,XTAL Oscilator in Single-Ended mode" "0,1"
|
|
bitfld.long 0x10 0. "OSCOFF,XTAL Oscillator powered-down" "0,1"
|
|
line.long 0x14 "ETHERCATCLKCTL,ETHERCATCLKCTL"
|
|
bitfld.long 0x14 8. "PHYCLKEN,etherCAT PHY clock enable" "0,1"
|
|
bitfld.long 0x14 1.--3. "ECATDIV,etherCAT clock divider configuration." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0. "DIVSRCSEL,Clock source select for the etherCAT clock divider." "0,1"
|
|
line.long 0x16 "CMCLKCTL,CMCLKCTL"
|
|
bitfld.long 0x16 5.--7. "ETHDIV,Ethernet clock divider configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x16 4. "ETHDIVSRCSEL,Clock source select for the etherNET clock divider." "0,1"
|
|
bitfld.long 0x16 1.--3. "CMCLKDIV,CM clock divider configuration." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x16 0. "CMDIVSRCSEL,Clock source select for the CM clock divider." "0,1"
|
|
tree.end
|
|
tree "CMCONF"
|
|
base d:0x5DC00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CMRESCTL,CM Reset Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key value"
|
|
rbitfld.long 0x0 1. "RESETSTS,CM Reset status" "0,1"
|
|
bitfld.long 0x0 0. "RESET,Software reset to CM" "0,1"
|
|
line.long 0x2 "CMTOCPU1NMICTL,CM To CPU1 NMI Control register"
|
|
bitfld.long 0x2 2. "CMNMIWDRST,CMNMIWDRST NMI enable bit enables nmi generation to C28x" "0,1"
|
|
line.long 0x4 "CMTOCPU1INTCTL,CM To CPU1 interrupt Control register"
|
|
bitfld.long 0x4 2. "CMNMIWDRST,CMNMIWDRST Interrupt enable bit enables interrupt to C28x" "0,1"
|
|
bitfld.long 0x4 1. "SYSRESETREQ,SYSRESETREQ Interrupt enable bit enables interrupt to C28x" "0,1"
|
|
bitfld.long 0x4 0. "VECTRESET,VECTRESET Interrupt enable bit enables interrupt to C28x" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PALLOCATE0,CM Peripheral Allocation Register."
|
|
bitfld.long 0x0 3. "CAN_B,Allocate CANB to CM" "0,1"
|
|
bitfld.long 0x0 2. "CAN_A,Allocate CANA to CM" "0,1"
|
|
bitfld.long 0x0 1. "ETHERCAT,Allocate ETHERCAT to CM" "0,1"
|
|
bitfld.long 0x0 0. "USB_A,Allocate USB_A to CM" "0,1"
|
|
group.long 0x3FE++0x3
|
|
line.long 0x0 "CM_CONF_REGS_LOCK,CM Configuration Registers Lock"
|
|
bitfld.long 0x0 0. "LOCK,Lock one time CM configuration registers." "0,1"
|
|
tree.end
|
|
tree "CPUSYS"
|
|
base d:0x5D300
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CPUSYSLOCK1,Lock bit for CPUSYS registers"
|
|
bitfld.long 0x0 30. "PCLKCR23,Lock bit for PCLKCR23 Register" "0,1"
|
|
bitfld.long 0x0 29. "PCLKCR22,Lock bit for PCLKCR22 Register" "0,1"
|
|
bitfld.long 0x0 28. "PCLKCR21,Lock bit for PCLKCR21 Register" "0,1"
|
|
bitfld.long 0x0 27. "PCLKCR20,Lock bit for PCLKCR20 Register" "0,1"
|
|
bitfld.long 0x0 25. "PCLKCR18,Lock bit for PCLKCR18 Register" "0,1"
|
|
bitfld.long 0x0 24. "PCLKCR17,Lock bit for PCLKCR17 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPIOLPMSEL1,Lock bit for GPIOLPMSEL1 Register" "0,1"
|
|
bitfld.long 0x0 22. "GPIOLPMSEL0,Lock bit for GPIOLPMSEL0 Register" "0,1"
|
|
bitfld.long 0x0 21. "LPMCR,Lock bit for LPMCR Register" "0,1"
|
|
bitfld.long 0x0 19. "PCLKCR16,Lock bit for PCLKCR16 Register" "0,1"
|
|
bitfld.long 0x0 17. "PCLKCR14,Lock bit for PCLKCR14 Register" "0,1"
|
|
bitfld.long 0x0 16. "PCLKCR13,Lock bit for PCLKCR13 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PCLKCR11,Lock bit for PCLKCR11 Register" "0,1"
|
|
bitfld.long 0x0 13. "PCLKCR10,Lock bit for PCLKCR10 Register" "0,1"
|
|
bitfld.long 0x0 12. "PCLKCR9,Lock bit for PCLKCR9 Register" "0,1"
|
|
bitfld.long 0x0 11. "PCLKCR8,Lock bit for PCLKCR8 Register" "0,1"
|
|
bitfld.long 0x0 10. "PCLKCR7,Lock bit for PCLKCR7 Register" "0,1"
|
|
bitfld.long 0x0 9. "PCLKCR6,Lock bit for PCLKCR6 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PCLKCR4,Lock bit for PCLKCR4 Register" "0,1"
|
|
bitfld.long 0x0 6. "PCLKCR3,Lock bit for PCLKCR3 Register" "0,1"
|
|
bitfld.long 0x0 5. "PCLKCR2,Lock bit for PCLKCR2 Register" "0,1"
|
|
bitfld.long 0x0 4. "PCLKCR1,Lock bit for PCLKCR1 Register" "0,1"
|
|
bitfld.long 0x0 3. "PCLKCR0,Lock bit for PCLKCR0 Register" "0,1"
|
|
bitfld.long 0x0 2. "PIEVERRADDR,Lock bit for PIEVERRADDR Register" "0,1"
|
|
line.long 0x2 "CPUSYSLOCK2,Lock bit for CPUSYS registers"
|
|
bitfld.long 0x2 0. "ETHERCATCTL,Lock bit for ETHERCATCTL register" "0,1"
|
|
group.long 0xA++0x7
|
|
line.long 0x0 "PIEVERRADDR,PIE Vector Fetch Error Address register"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "ADDR,PIE Vector Fetch Error Handler Routine Address"
|
|
line.long 0x2 "ETHERCATCTL,ETHERCAT control register."
|
|
bitfld.long 0x2 0. "I2CLOOPBACK,Loopback I2C port of etherCAT IP to I2C_A." "0,1"
|
|
group.long 0x22++0x4F
|
|
line.long 0x0 "PCLKCR0,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x0 24. "ERAD,ERAD module clock enable" "0,1"
|
|
bitfld.long 0x0 19. "GTBCLKSYNC,EPWM Time Base Clock Global sync" "0,1"
|
|
bitfld.long 0x0 18. "TBCLKSYNC,EPWM Time Base Clock sync" "0,1"
|
|
bitfld.long 0x0 16. "HRCAL,HRCAL Clock Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "CLA1BGCRC,CLA1BGCRC Clock Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "CPUBGCRC,CPUBGCRC Clock Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CPUTIMER2,CPUTIMER2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x0 4. "CPUTIMER1,CPUTIMER1 Clock Enable bit" "0,1"
|
|
bitfld.long 0x0 3. "CPUTIMER0,CPUTIMER0 Clock Enable bit" "0,1"
|
|
bitfld.long 0x0 2. "DMA,DMA Clock Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "CLA1,CLA1 Clock Enable Bit" "0,1"
|
|
line.long 0x2 "PCLKCR1,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x2 1. "EMIF2,EMIF2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x2 0. "EMIF1,EMIF1 Clock Enable bit" "0,1"
|
|
line.long 0x4 "PCLKCR2,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x4 15. "EPWM16,EPWM16 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 14. "EPWM15,EPWM15 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 13. "EPWM14,EPWM14 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 12. "EPWM13,EPWM13 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 11. "EPWM12,EPWM12 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 10. "EPWM11,EPWM11 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "EPWM10,EPWM10 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 8. "EPWM9,EPWM9 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 7. "EPWM8,EPWM8 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 6. "EPWM7,EPWM7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 5. "EPWM6,EPWM6 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 4. "EPWM5,EPWM5 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EPWM4,EPWM4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 2. "EPWM3,EPWM3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 1. "EPWM2,EPWM2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x4 0. "EPWM1,EPWM1 Clock Enable bit" "0,1"
|
|
line.long 0x6 "PCLKCR3,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x6 6. "ECAP7,ECAP7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x6 5. "ECAP6,ECAP6 Clock Enable bit" "0,1"
|
|
bitfld.long 0x6 4. "ECAP5,ECAP5 Clock Enable bit" "0,1"
|
|
bitfld.long 0x6 3. "ECAP4,ECAP4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x6 2. "ECAP3,ECAP3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x6 1. "ECAP2,ECAP2 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x6 0. "ECAP1,ECAP1 Clock Enable bit" "0,1"
|
|
line.long 0x8 "PCLKCR4,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x8 2. "EQEP3,EQEP3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x8 1. "EQEP2,EQEP2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x8 0. "EQEP1,EQEP1 Clock Enable bit" "0,1"
|
|
line.long 0xC "PCLKCR6,Peripheral Clock Gating Registers"
|
|
bitfld.long 0xC 1. "SD2,SD2 Clock Enable bit" "0,1"
|
|
bitfld.long 0xC 0. "SD1,SD1 Clock Enable bit" "0,1"
|
|
line.long 0xE "PCLKCR7,Peripheral Clock Gating Registers"
|
|
bitfld.long 0xE 3. "SCI_D,SCI_D Clock Enable bit" "0,1"
|
|
bitfld.long 0xE 2. "SCI_C,SCI_C Clock Enable bit" "0,1"
|
|
bitfld.long 0xE 1. "SCI_B,SCI_B Clock Enable bit" "0,1"
|
|
bitfld.long 0xE 0. "SCI_A,SCI_A Clock Enable bit" "0,1"
|
|
line.long 0x10 "PCLKCR8,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x10 3. "SPI_D,SPI_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x10 2. "SPI_C,SPI_C Clock Enable bit" "0,1"
|
|
bitfld.long 0x10 1. "SPI_B,SPI_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x10 0. "SPI_A,SPI_A Clock Enable bit" "0,1"
|
|
line.long 0x12 "PCLKCR9,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x12 1. "I2C_B,I2C_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x12 0. "I2C_A,I2C_A Clock Enable bit" "0,1"
|
|
line.long 0x14 "PCLKCR10,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x14 1. "CAN_B,CAN_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x14 0. "CAN_A,CAN_A Clock Enable bit" "0,1"
|
|
line.long 0x16 "PCLKCR11,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x16 16. "USB_A,USB_A Clock Enable bit" "0,1"
|
|
bitfld.long 0x16 1. "McBSP_B,McBSP_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x16 0. "McBSP_A,McBSP_A Clock Enable bit" "0,1"
|
|
line.long 0x1A "PCLKCR13,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x1A 3. "ADC_D,ADC_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x1A 2. "ADC_C,ADC_C Clock Enable bit" "0,1"
|
|
bitfld.long 0x1A 1. "ADC_B,ADC_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x1A 0. "ADC_A,ADC_A Clock Enable bit" "0,1"
|
|
line.long 0x1C "PCLKCR14,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x1C 7. "CMPSS8,CMPSS8 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 6. "CMPSS7,CMPSS7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 5. "CMPSS6,CMPSS6 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 4. "CMPSS5,CMPSS5 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 3. "CMPSS4,CMPSS4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 2. "CMPSS3,CMPSS3 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "CMPSS2,CMPSS2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x1C 0. "CMPSS1,CMPSS1 Clock Enable bit" "0,1"
|
|
line.long 0x20 "PCLKCR16,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x20 18. "DAC_C,Buffered_DAC12_3 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x20 17. "DAC_B,Buffered_DAC12_2 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x20 16. "DAC_A,Buffered_DAC12_1 Clock Enable Bit" "0,1"
|
|
line.long 0x22 "PCLKCR17,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x22 3. "CLB4,CLB4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x22 2. "CLB3,CLB3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x22 1. "CLB2,CLB2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x22 0. "CLB1,CLB1 Clock Enable bit" "0,1"
|
|
line.long 0x24 "PCLKCR18,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x24 23. "FSIRX_H,FSIRX_H Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 22. "FSIRX_G,FSIRX_G Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 21. "FSIRX_F,FSIRX_F Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 20. "FSIRX_E,FSIRX_E Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 19. "FSIRX_D,FSIRX_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 18. "FSIRX_C,FSIRX_C Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 17. "FSIRX_B,FSIRX_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 16. "FSIRX_A,FSIRX_A Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 1. "FSITX_B,FSITX_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x24 0. "FSITX_A,FSITX_A Clock Enable bit" "0,1"
|
|
line.long 0x28 "PCLKCR20,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x28 0. "PMBUS_A,PMBUS_A Clock Enable bit" "0,1"
|
|
line.long 0x2A "PCLKCR21,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x2A 2. "DCC2,DCC2 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x2A 1. "DCC1,DCC1 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x2A 0. "DCC0,DCC0 Clock Enable Bit" "0,1"
|
|
line.long 0x2C "PCLKCR22,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x2C 0. "PBISTCLK,PBISTCLK Clock Enable Bit" "0,1"
|
|
line.long 0x2E "PCLKCR23,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x2E 0. "ETHERCAT,ETHERCAT Clock Enable Bit" "0,1"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "SIMRESET,Simulated Reset Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key value"
|
|
bitfld.long 0x0 1. "XRSn,Generates a simulated XRSn" "0,1"
|
|
bitfld.long 0x0 0. "CPU1RSn,Generates a reset to CPU" "0,1"
|
|
group.long 0x76++0x17
|
|
line.long 0x0 "LPMCR,LPM Control Register"
|
|
bitfld.long 0x0 15. "WDINTE,Enable for WDINT wakeup from STANDBY" "0,1"
|
|
hexmask.long.byte 0x0 2.--7. 1. "QUALSTDBY,STANDBY Wakeup Pin Qualification Setting"
|
|
bitfld.long 0x0 0.--1. "LPM,Low Power Mode setting" "0,1,2,3"
|
|
line.long 0x2 "GPIOLPMSEL0,GPIO LPM Wakeup select registers"
|
|
bitfld.long 0x2 31. "GPIO31,GPIO31 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 30. "GPIO30,GPIO30 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 29. "GPIO29,GPIO29 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 28. "GPIO28,GPIO28 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 27. "GPIO27,GPIO27 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 26. "GPIO26,GPIO26 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x2 25. "GPIO25,GPIO25 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 24. "GPIO24,GPIO24 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 23. "GPIO23,GPIO23 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 22. "GPIO22,GPIO22 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 21. "GPIO21,GPIO21 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 20. "GPIO20,GPIO20 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x2 19. "GPIO19,GPIO19 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 18. "GPIO18,GPIO18 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 17. "GPIO17,GPIO17 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 16. "GPIO16,GPIO16 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 15. "GPIO15,GPIO15 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 14. "GPIO14,GPIO14 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x2 13. "GPIO13,GPIO13 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 12. "GPIO12,GPIO12 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 11. "GPIO11,GPIO11 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 10. "GPIO10,GPIO10 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 9. "GPIO9,GPIO9 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 8. "GPIO8,GPIO8 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x2 7. "GPIO7,GPIO7 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 6. "GPIO6,GPIO6 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 5. "GPIO5,GPIO5 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 4. "GPIO4,GPIO4 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 3. "GPIO3,GPIO3 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 2. "GPIO2,GPIO2 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "GPIO1,GPIO1 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x2 0. "GPIO0,GPIO0 Enable for LPM Wakeup" "0,1"
|
|
line.long 0x4 "GPIOLPMSEL1,GPIO LPM Wakeup select registers"
|
|
bitfld.long 0x4 31. "GPIO63,GPIO63 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 30. "GPIO62,GPIO62 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 29. "GPIO61,GPIO61 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 28. "GPIO60,GPIO60 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 27. "GPIO59,GPIO59 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 26. "GPIO58,GPIO58 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "GPIO57,GPIO57 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 24. "GPIO56,GPIO56 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 23. "GPIO55,GPIO55 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 22. "GPIO54,GPIO54 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 21. "GPIO53,GPIO53 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 20. "GPIO52,GPIO52 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "GPIO51,GPIO51 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 18. "GPIO50,GPIO50 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 17. "GPIO49,GPIO49 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 16. "GPIO48,GPIO48 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 15. "GPIO47,GPIO47 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 14. "GPIO46,GPIO46 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "GPIO45,GPIO45 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 12. "GPIO44,GPIO44 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 11. "GPIO43,GPIO43 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 10. "GPIO42,GPIO42 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 9. "GPIO41,GPIO41 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 8. "GPIO40,GPIO40 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "GPIO39,GPIO39 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 6. "GPIO38,GPIO38 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 5. "GPIO37,GPIO37 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 4. "GPIO36,GPIO36 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 3. "GPIO35,GPIO35 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 2. "GPIO34,GPIO34 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "GPIO33,GPIO33 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x4 0. "GPIO32,GPIO32 Enable for LPM Wakeup" "0,1"
|
|
line.long 0x6 "TMR2CLKCTL,Timer2 Clock Measurement functionality control register"
|
|
bitfld.long 0x6 3.--5. "TMR2CLKPRESCALE,CPU Timer 2 Clock Pre-Scale Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x6 0.--2. "TMR2CLKSRCSEL,CPU Timer 2 Clock Source Select Bit" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "RESCCLR,Reset Cause Clear Register"
|
|
bitfld.long 0x8 11. "SIMRESET_XRSn,SIMRESET_XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 10. "SIMRESET_CPU1RSn,SIMRESET_CPU1RSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 9. "ECAT_RESET_OUT,ECAT_RESET_OUT Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 8. "SCCRESETn,SCCRESETn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 5. "HWBISTn,HWBISTn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 3. "NMIWDRSn,NMIWDRSn Reset Cause Indication Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "WDRSn,WDRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 1. "XRSn,XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x8 0. "POR,POR Reset Cause Indication Bit" "0,1"
|
|
line.long 0xA "RESC,Reset Cause register"
|
|
rbitfld.long 0xA 31. "TRSTn_pin_status,TRSTn Status" "0,1"
|
|
rbitfld.long 0xA 30. "XRSn_pin_status,XRSN Pin Status" "0,1"
|
|
bitfld.long 0xA 11. "SIMRESET_XRSn,SIMRESET_XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 10. "SIMRESET_CPU1RSn,SIMRESET_CPU1RSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 9. "ECAT_RESET_OUT,ECAT_RESET_OUT Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 8. "SCCRESETn,SCCRESETn Reset Cause Indication Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xA 5. "HWBISTn,HWBISTn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 3. "NMIWDRSn,NMIWDRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 2. "WDRSn,WDRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 1. "XRSn,XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0xA 0. "POR,POR Reset Cause Indication Bit" "0,1"
|
|
tree.end
|
|
base d:0x0
|
|
tree "CPUTIMER"
|
|
tree "CPUTIMER0"
|
|
base d:0xC00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TIM,CPU-Timer. Counter Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "MSW,CPU-Timer Counter Registers High"
|
|
hexmask.long.word 0x0 0.--15. 1. "LSW,CPU-Timer Counter Registers"
|
|
line.long 0x2 "PRD,CPU-Timer. Period Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "MSW,CPU-Timer Period Registers High"
|
|
hexmask.long.word 0x2 0.--15. 1. "LSW,CPU-Timer Period Registers"
|
|
group.word 0x4++0x5
|
|
line.word 0x0 "TCR,CPU-Timer. Control Register"
|
|
bitfld.word 0x0 15. "TIF,CPU-Timer Interrupt Flag." "0,1"
|
|
bitfld.word 0x0 14. "TIE,CPU-Timer Interrupt Enable." "0,1"
|
|
bitfld.word 0x0 11. "FREE,Emulation modes" "0,1"
|
|
bitfld.word 0x0 10. "SOFT,Emulation modes" "0,1"
|
|
bitfld.word 0x0 5. "TRB,Timer reload" "0,1"
|
|
bitfld.word 0x0 4. "TSS,CPU-Timer stop status bit." "0,1"
|
|
line.word 0x2 "TPR,CPU-Timer. Prescale Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "PSC,CPU-Timer Prescale Counter."
|
|
hexmask.word.byte 0x2 0.--7. 1. "TDDR,CPU-Timer Divide-Down."
|
|
line.word 0x3 "TPRH,CPU-Timer. Prescale Register High"
|
|
hexmask.word.byte 0x3 8.--15. 1. "PSCH,CPU-Timer Prescale Counter."
|
|
hexmask.word.byte 0x3 0.--7. 1. "TDDRH,CPU-Timer Divide-Down."
|
|
tree.end
|
|
tree "CPUTIMER1"
|
|
base d:0xC08
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TIM,CPU-Timer. Counter Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "MSW,CPU-Timer Counter Registers High"
|
|
hexmask.long.word 0x0 0.--15. 1. "LSW,CPU-Timer Counter Registers"
|
|
line.long 0x2 "PRD,CPU-Timer. Period Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "MSW,CPU-Timer Period Registers High"
|
|
hexmask.long.word 0x2 0.--15. 1. "LSW,CPU-Timer Period Registers"
|
|
group.word 0x4++0x5
|
|
line.word 0x0 "TCR,CPU-Timer. Control Register"
|
|
bitfld.word 0x0 15. "TIF,CPU-Timer Interrupt Flag." "0,1"
|
|
bitfld.word 0x0 14. "TIE,CPU-Timer Interrupt Enable." "0,1"
|
|
bitfld.word 0x0 11. "FREE,Emulation modes" "0,1"
|
|
bitfld.word 0x0 10. "SOFT,Emulation modes" "0,1"
|
|
bitfld.word 0x0 5. "TRB,Timer reload" "0,1"
|
|
bitfld.word 0x0 4. "TSS,CPU-Timer stop status bit." "0,1"
|
|
line.word 0x2 "TPR,CPU-Timer. Prescale Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "PSC,CPU-Timer Prescale Counter."
|
|
hexmask.word.byte 0x2 0.--7. 1. "TDDR,CPU-Timer Divide-Down."
|
|
line.word 0x3 "TPRH,CPU-Timer. Prescale Register High"
|
|
hexmask.word.byte 0x3 8.--15. 1. "PSCH,CPU-Timer Prescale Counter."
|
|
hexmask.word.byte 0x3 0.--7. 1. "TDDRH,CPU-Timer Divide-Down."
|
|
tree.end
|
|
tree "CPUTIMER2"
|
|
base d:0xC10
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TIM,CPU-Timer. Counter Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "MSW,CPU-Timer Counter Registers High"
|
|
hexmask.long.word 0x0 0.--15. 1. "LSW,CPU-Timer Counter Registers"
|
|
line.long 0x2 "PRD,CPU-Timer. Period Register"
|
|
hexmask.long.word 0x2 16.--31. 1. "MSW,CPU-Timer Period Registers High"
|
|
hexmask.long.word 0x2 0.--15. 1. "LSW,CPU-Timer Period Registers"
|
|
group.word 0x4++0x5
|
|
line.word 0x0 "TCR,CPU-Timer. Control Register"
|
|
bitfld.word 0x0 15. "TIF,CPU-Timer Interrupt Flag." "0,1"
|
|
bitfld.word 0x0 14. "TIE,CPU-Timer Interrupt Enable." "0,1"
|
|
bitfld.word 0x0 11. "FREE,Emulation modes" "0,1"
|
|
bitfld.word 0x0 10. "SOFT,Emulation modes" "0,1"
|
|
bitfld.word 0x0 5. "TRB,Timer reload" "0,1"
|
|
bitfld.word 0x0 4. "TSS,CPU-Timer stop status bit." "0,1"
|
|
line.word 0x2 "TPR,CPU-Timer. Prescale Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "PSC,CPU-Timer Prescale Counter."
|
|
hexmask.word.byte 0x2 0.--7. 1. "TDDR,CPU-Timer Divide-Down."
|
|
line.word 0x3 "TPRH,CPU-Timer. Prescale Register High"
|
|
hexmask.word.byte 0x3 8.--15. 1. "PSCH,CPU-Timer Prescale Counter."
|
|
hexmask.word.byte 0x3 0.--7. 1. "TDDRH,CPU-Timer Divide-Down."
|
|
tree.end
|
|
tree.end
|
|
tree "DEVCFG"
|
|
base d:0x5D000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DEVCFGLOCK1,Lock bit for DEVCFG registers"
|
|
bitfld.long 0x0 25. "CPUSEL25,Lock bit for CPUSEL25 register" "0,1"
|
|
bitfld.long 0x0 18. "CPUSEL18,Lock bit for CPUSEL18 register" "0,1"
|
|
bitfld.long 0x0 16. "CPUSEL16,Lock bit for CPUSEL16 register" "0,1"
|
|
bitfld.long 0x0 15. "CPUSEL15,Lock bit for CPUSEL15 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPUSEL14,Lock bit for CPUSEL14 register" "0,1"
|
|
bitfld.long 0x0 12. "CPUSEL12,Lock bit for CPUSEL12 register" "0,1"
|
|
bitfld.long 0x0 11. "CPUSEL11,Lock bit for CPUSEL11 register" "0,1"
|
|
bitfld.long 0x0 9. "CPUSEL9,Lock bit for CPUSEL9 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CPUSEL8,Lock bit for CPUSEL8 register" "0,1"
|
|
bitfld.long 0x0 7. "CPUSEL7,Lock bit for CPUSEL7 register" "0,1"
|
|
bitfld.long 0x0 6. "CPUSEL6,Lock bit for CPUSEL6 register" "0,1"
|
|
bitfld.long 0x0 5. "CPUSEL5,Lock bit for CPUSEL5 register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPUSEL4,Lock bit for CPUSEL4 register" "0,1"
|
|
bitfld.long 0x0 2. "CPUSEL2,Lock bit for CPUSEL2 register" "0,1"
|
|
bitfld.long 0x0 1. "CPUSEL1,Lock bit for CPUSEL1 register" "0,1"
|
|
bitfld.long 0x0 0. "CPUSEL0,Lock bit for CPUSEL0 register" "0,1"
|
|
line.long 0x2 "DEVCFGLOCK2,Lock bit for DEVCFG registers"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "PARTIDL,Lower 32-bit of Device PART Identification Number"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PARTID_FORMAT_REVISION,Revision of the PARTID format"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FLASH_SIZE,Flash size in KB"
|
|
bitfld.long 0x0 13.--14. "INSTASPIN,Motorware feature set" "0,1,2,3"
|
|
bitfld.long 0x0 8.--10. "PIN_COUNT,Device Pin Count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "QUAL,Qualification Status" "0,1,2,3"
|
|
line.long 0x2 "PARTIDH,Upper 32-bit of Device PART Identification Number"
|
|
hexmask.long.byte 0x2 24.--31. 1. "DEVICE_CLASS_ID,Device class ID"
|
|
hexmask.long.byte 0x2 16.--23. 1. "PARTNO,Device part number"
|
|
hexmask.long.byte 0x2 8.--15. 1. "FAMILY,Device family"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "REVID,Device Revision Number"
|
|
hexmask.long.word 0x0 0.--15. 1. "REVID,Device Revision ID. This is specific to the Device"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PERCNF1,Peripheral Configuration register"
|
|
bitfld.long 0x0 16. "USB_A_PHY,USB_A_PHY enable/disable bit" "0,1"
|
|
bitfld.long 0x0 3. "ADC_D_MODE,ADC Wrapper-4 mode setting bit" "0,1"
|
|
bitfld.long 0x0 2. "ADC_C_MODE,ADC Wrapper-3 mode setting bit" "0,1"
|
|
bitfld.long 0x0 1. "ADC_B_MODE,ADC Wrapper-2 mode setting bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ADC_A_MODE,ADC Wrapper-1 mode setting bit" "0,1"
|
|
rgroup.long 0x74++0x3
|
|
line.long 0x0 "FUSEERR,e-Fuse error Status register"
|
|
bitfld.long 0x0 5. "ERR,Efuse Self Test Error Status" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "ALERR,Efuse Autoload Error Status"
|
|
group.long 0x82++0x4B
|
|
line.long 0x0 "SOFTPRES0,Processing Block Software Reset register"
|
|
bitfld.long 0x0 25. "CPU2_ERAD,ERAD Module reset bit" "0,1"
|
|
bitfld.long 0x0 24. "CPU1_ERAD,ERAD Module reset bit" "0,1"
|
|
bitfld.long 0x0 17. "CPU2_CLA1BGCRC,CLA1BGCRC Module reset bit" "0,1"
|
|
bitfld.long 0x0 16. "CPU2_CPUBGCRC,CPUBGCRC Module reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPU1_CLA1BGCRC,CLA1BGCRC Module reset bit" "0,1"
|
|
bitfld.long 0x0 13. "CPU1_CPUBGCRC,CPUBGCRC Module reset bit" "0,1"
|
|
bitfld.long 0x0 2. "CPU2_CLA1,CPU2_CLA1 software reset bit" "0,1"
|
|
bitfld.long 0x0 0. "CPU1_CLA1,CPU1_CLA1 software reset bit" "0,1"
|
|
line.long 0x2 "SOFTPRES1,EMIF Software Reset register"
|
|
bitfld.long 0x2 1. "EMIF2,EMIF2 software reset bit" "0,1"
|
|
bitfld.long 0x2 0. "EMIF1,EMIF1 software reset bit" "0,1"
|
|
line.long 0x4 "SOFTPRES2,Peripheral Software Reset register"
|
|
bitfld.long 0x4 15. "EPWM16,EPWM16 software reset bit" "0,1"
|
|
bitfld.long 0x4 14. "EPWM15,EPWM15 software reset bit" "0,1"
|
|
bitfld.long 0x4 13. "EPWM14,EPWM14 software reset bit" "0,1"
|
|
bitfld.long 0x4 12. "EPWM13,EPWM13 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EPWM12,EPWM12 software reset bit" "0,1"
|
|
bitfld.long 0x4 10. "EPWM11,EPWM11 software reset bit" "0,1"
|
|
bitfld.long 0x4 9. "EPWM10,EPWM10 software reset bit" "0,1"
|
|
bitfld.long 0x4 8. "EPWM9,EPWM9 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "EPWM8,EPWM8 software reset bit" "0,1"
|
|
bitfld.long 0x4 6. "EPWM7,EPWM7 software reset bit" "0,1"
|
|
bitfld.long 0x4 5. "EPWM6,EPWM6 software reset bit" "0,1"
|
|
bitfld.long 0x4 4. "EPWM5,EPWM5 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EPWM4,EPWM4 software reset bit" "0,1"
|
|
bitfld.long 0x4 2. "EPWM3,EPWM3 software reset bit" "0,1"
|
|
bitfld.long 0x4 1. "EPWM2,EPWM2 software reset bit" "0,1"
|
|
bitfld.long 0x4 0. "EPWM1,EPWM1 software reset bit" "0,1"
|
|
line.long 0x6 "SOFTPRES3,Peripheral Software Reset register"
|
|
bitfld.long 0x6 6. "ECAP7,ECAP7 software reset bit" "0,1"
|
|
bitfld.long 0x6 5. "ECAP6,ECAP6 software reset bit" "0,1"
|
|
bitfld.long 0x6 4. "ECAP5,ECAP5 software reset bit" "0,1"
|
|
bitfld.long 0x6 3. "ECAP4,ECAP4 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x6 2. "ECAP3,ECAP3 software reset bit" "0,1"
|
|
bitfld.long 0x6 1. "ECAP2,ECAP2 software reset bit" "0,1"
|
|
bitfld.long 0x6 0. "ECAP1,ECAP1 software reset bit" "0,1"
|
|
line.long 0x8 "SOFTPRES4,Peripheral Software Reset register"
|
|
bitfld.long 0x8 2. "EQEP3,EQEP3 software reset bit" "0,1"
|
|
bitfld.long 0x8 1. "EQEP2,EQEP2 software reset bit" "0,1"
|
|
bitfld.long 0x8 0. "EQEP1,EQEP1 software reset bit" "0,1"
|
|
line.long 0xC "SOFTPRES6,Peripheral Software Reset register"
|
|
bitfld.long 0xC 1. "SD2,SD2 software reset bit" "0,1"
|
|
bitfld.long 0xC 0. "SD1,SD1 software reset bit" "0,1"
|
|
line.long 0xE "SOFTPRES7,Peripheral Software Reset register"
|
|
bitfld.long 0xE 3. "SCI_D,SCI_D software reset bit" "0,1"
|
|
bitfld.long 0xE 2. "SCI_C,SCI_C software reset bit" "0,1"
|
|
bitfld.long 0xE 1. "SCI_B,SCI_B software reset bit" "0,1"
|
|
bitfld.long 0xE 0. "SCI_A,SCI_A software reset bit" "0,1"
|
|
line.long 0x10 "SOFTPRES8,Peripheral Software Reset register"
|
|
bitfld.long 0x10 3. "SPI_D,SPI_D software reset bit" "0,1"
|
|
bitfld.long 0x10 2. "SPI_C,SPI_C software reset bit" "0,1"
|
|
bitfld.long 0x10 1. "SPI_B,SPI_B software reset bit" "0,1"
|
|
bitfld.long 0x10 0. "SPI_A,SPI_A software reset bit" "0,1"
|
|
line.long 0x12 "SOFTPRES9,Peripheral Software Reset register"
|
|
bitfld.long 0x12 1. "I2C_B,I2C_B software reset bit" "0,1"
|
|
bitfld.long 0x12 0. "I2C_A,I2C_A software reset bit" "0,1"
|
|
line.long 0x14 "SOFTPRES10,Peripheral Software Reset register"
|
|
bitfld.long 0x14 1. "CAN_B,CAN_B software reset bit" "0,1"
|
|
bitfld.long 0x14 0. "CAN_A,CAN_A software reset bit" "0,1"
|
|
line.long 0x16 "SOFTPRES11,Peripheral Software Reset register"
|
|
bitfld.long 0x16 16. "USB_A,USB_A software reset bit" "0,1"
|
|
bitfld.long 0x16 1. "McBSP_B,McBSP_B software reset bit" "0,1"
|
|
bitfld.long 0x16 0. "McBSP_A,McBSP_A software reset bit" "0,1"
|
|
line.long 0x1A "SOFTPRES13,Peripheral Software Reset register"
|
|
bitfld.long 0x1A 3. "ADC_D,ADC_D software reset bit" "0,1"
|
|
bitfld.long 0x1A 2. "ADC_C,ADC_C software reset bit" "0,1"
|
|
bitfld.long 0x1A 1. "ADC_B,ADC_B software reset bit" "0,1"
|
|
bitfld.long 0x1A 0. "ADC_A,ADC_A software reset bit" "0,1"
|
|
line.long 0x1C "SOFTPRES14,Peripheral Software Reset register"
|
|
bitfld.long 0x1C 7. "CMPSS8,CMPSS8 software reset bit" "0,1"
|
|
bitfld.long 0x1C 6. "CMPSS7,CMPSS7 software reset bit" "0,1"
|
|
bitfld.long 0x1C 5. "CMPSS6,CMPSS6 software reset bit" "0,1"
|
|
bitfld.long 0x1C 4. "CMPSS5,CMPSS5 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "CMPSS4,CMPSS4 software reset bit" "0,1"
|
|
bitfld.long 0x1C 2. "CMPSS3,CMPSS3 software reset bit" "0,1"
|
|
bitfld.long 0x1C 1. "CMPSS2,CMPSS2 software reset bit" "0,1"
|
|
bitfld.long 0x1C 0. "CMPSS1,CMPSS1 software reset bit" "0,1"
|
|
line.long 0x20 "SOFTPRES16,Peripheral Software Reset register"
|
|
bitfld.long 0x20 18. "DAC_C,Buffered_DAC12_3 software reset bit" "0,1"
|
|
bitfld.long 0x20 17. "DAC_B,Buffered_DAC12_2 software reset bit" "0,1"
|
|
bitfld.long 0x20 16. "DAC_A,Buffered_DAC12_1 software reset bit" "0,1"
|
|
line.long 0x22 "SOFTPRES17,Reserved Peripheral Software Reset register"
|
|
bitfld.long 0x22 3. "CLB4,CLB4 software reset bit" "0,1"
|
|
bitfld.long 0x22 2. "CLB3,CLB3 software reset bit" "0,1"
|
|
bitfld.long 0x22 1. "CLB2,CLB2 software reset bit" "0,1"
|
|
bitfld.long 0x22 0. "CLB1,CLB1 software reset bit" "0,1"
|
|
line.long 0x24 "SOFTPRES18,Reserved Peripheral Software Reset register"
|
|
bitfld.long 0x24 23. "FSIRX_H,FSIRX_H software reset bit" "0,1"
|
|
bitfld.long 0x24 22. "FSIRX_G,FSIRX_G software reset bit" "0,1"
|
|
bitfld.long 0x24 21. "FSIRX_F,FSIRX_F software reset bit" "0,1"
|
|
bitfld.long 0x24 20. "FSIRX_E,FSIRX_E software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 19. "FSIRX_D,FSIRX_D software reset bit" "0,1"
|
|
bitfld.long 0x24 18. "FSIRX_C,FSIRX_C software reset bit" "0,1"
|
|
bitfld.long 0x24 17. "FSIRX_B,FSIRX_B software reset bit" "0,1"
|
|
bitfld.long 0x24 16. "FSIRX_A,FSIRX_A software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "FSITX_B,FSITX_B software reset bit" "0,1"
|
|
bitfld.long 0x24 0. "FSITX_A,FSITX_A software reset bit" "0,1"
|
|
line.long 0x28 "SOFTPRES20,Peripheral Software Reset register"
|
|
bitfld.long 0x28 0. "PMBUS_A,PMBUS_A software reset bit" "0,1"
|
|
line.long 0x2A "SOFTPRES21,Peripheral Software Reset register"
|
|
bitfld.long 0x2A 2. "DCC2,DCC2 Module reset bit" "0,1"
|
|
bitfld.long 0x2A 1. "DCC1,DCC1 Module reset bit" "0,1"
|
|
bitfld.long 0x2A 0. "DCC0,DCC0 Module reset bit" "0,1"
|
|
line.long 0x2E "SOFTPRES23,Peripheral Software Reset register"
|
|
bitfld.long 0x2E 0. "ETHERCAT,ETHERCAT Module reset bit" "0,1"
|
|
group.long 0xD6++0x3B
|
|
line.long 0x0 "CPUSEL0,CPU Select register for common peripherals"
|
|
bitfld.long 0x0 15. "EPWM16,EPWM16 CPU select bit" "0,1"
|
|
bitfld.long 0x0 14. "EPWM15,EPWM15 CPU select bit" "0,1"
|
|
bitfld.long 0x0 13. "EPWM14,EPWM14 CPU select bit" "0,1"
|
|
bitfld.long 0x0 12. "EPWM13,EPWM13 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EPWM12,EPWM12 CPU select bit" "0,1"
|
|
bitfld.long 0x0 10. "EPWM11,EPWM11 CPU select bit" "0,1"
|
|
bitfld.long 0x0 9. "EPWM10,EPWM10 CPU select bit" "0,1"
|
|
bitfld.long 0x0 8. "EPWM9,EPWM9 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EPWM8,EPWM8 CPU select bit" "0,1"
|
|
bitfld.long 0x0 6. "EPWM7,EPWM7 CPU select bit" "0,1"
|
|
bitfld.long 0x0 5. "EPWM6,EPWM6 CPU select bit" "0,1"
|
|
bitfld.long 0x0 4. "EPWM5,EPWM5 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EPWM4,EPWM4 CPU select bit" "0,1"
|
|
bitfld.long 0x0 2. "EPWM3,EPWM3 CPU select bit" "0,1"
|
|
bitfld.long 0x0 1. "EPWM2,EPWM2 CPU select bit" "0,1"
|
|
bitfld.long 0x0 0. "EPWM1,EPWM1 CPU select bit" "0,1"
|
|
line.long 0x2 "CPUSEL1,CPU Select register for common peripherals"
|
|
bitfld.long 0x2 6. "ECAP7,ECAP7 CPU select bit" "0,1"
|
|
bitfld.long 0x2 5. "ECAP6,ECAP6 CPU select bit" "0,1"
|
|
bitfld.long 0x2 4. "ECAP5,ECAP5 CPU select bit" "0,1"
|
|
bitfld.long 0x2 3. "ECAP4,ECAP4 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2 2. "ECAP3,ECAP3 CPU select bit" "0,1"
|
|
bitfld.long 0x2 1. "ECAP2,ECAP2 CPU select bit" "0,1"
|
|
bitfld.long 0x2 0. "ECAP1,ECAP1 CPU select bit" "0,1"
|
|
line.long 0x4 "CPUSEL2,CPU Select register for common peripherals"
|
|
bitfld.long 0x4 2. "EQEP3,EQEP3 CPU select bit" "0,1"
|
|
bitfld.long 0x4 1. "EQEP2,EQEP2 CPU select bit" "0,1"
|
|
bitfld.long 0x4 0. "EQEP1,EQEP1 CPU select bit" "0,1"
|
|
line.long 0x8 "CPUSEL4,CPU Select register for common peripherals"
|
|
bitfld.long 0x8 1. "SD2,SD2 CPU select bit" "0,1"
|
|
bitfld.long 0x8 0. "SD1,SD1 CPU select bit" "0,1"
|
|
line.long 0xA "CPUSEL5,CPU Select register for common peripherals"
|
|
bitfld.long 0xA 3. "SCI_D,SCI_D CPU select bit" "0,1"
|
|
bitfld.long 0xA 2. "SCI_C,SCI_C CPU select bit" "0,1"
|
|
bitfld.long 0xA 1. "SCI_B,SCI_B CPU select bit" "0,1"
|
|
bitfld.long 0xA 0. "SCI_A,SCI_A CPU select bit" "0,1"
|
|
line.long 0xC "CPUSEL6,CPU Select register for common peripherals"
|
|
bitfld.long 0xC 3. "SPI_D,SPI_D CPU select bit" "0,1"
|
|
bitfld.long 0xC 2. "SPI_C,SPI_C CPU select bit" "0,1"
|
|
bitfld.long 0xC 1. "SPI_B,SPI_B CPU select bit" "0,1"
|
|
bitfld.long 0xC 0. "SPI_A,SPI_A CPU select bit" "0,1"
|
|
line.long 0xE "CPUSEL7,CPU Select register for common peripherals"
|
|
bitfld.long 0xE 1. "I2C_B,I2C_B CPU select bit" "0,1"
|
|
bitfld.long 0xE 0. "I2C_A,I2C_A CPU select bit" "0,1"
|
|
line.long 0x10 "CPUSEL8,CPU Select register for common peripherals"
|
|
bitfld.long 0x10 1. "CAN_B,CAN_B CPU select bit" "0,1"
|
|
bitfld.long 0x10 0. "CAN_A,CAN_A CPU select bit" "0,1"
|
|
line.long 0x12 "CPUSEL9,CPU Select register for common peripherals"
|
|
bitfld.long 0x12 1. "McBSP_B,McBSP_B CPU select bit" "0,1"
|
|
bitfld.long 0x12 0. "McBSP_A,McBSP_A CPU select bit" "0,1"
|
|
line.long 0x16 "CPUSEL11,CPU Select register for common peripherals"
|
|
bitfld.long 0x16 3. "ADC_D,ADC_D CPU select bit" "0,1"
|
|
bitfld.long 0x16 2. "ADC_C,ADC_C CPU select bit" "0,1"
|
|
bitfld.long 0x16 1. "ADC_B,ADC_B CPU select bit" "0,1"
|
|
bitfld.long 0x16 0. "ADC_A,ADC_A CPU select bit" "0,1"
|
|
line.long 0x18 "CPUSEL12,CPU Select register for common peripherals"
|
|
bitfld.long 0x18 7. "CMPSS8,CMPSS8 CPU select bit" "0,1"
|
|
bitfld.long 0x18 6. "CMPSS7,CMPSS7 CPU select bit" "0,1"
|
|
bitfld.long 0x18 5. "CMPSS6,CMPSS6 CPU select bit" "0,1"
|
|
bitfld.long 0x18 4. "CMPSS5,CMPSS5 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "CMPSS4,CMPSS4 CPU select bit" "0,1"
|
|
bitfld.long 0x18 2. "CMPSS3,CMPSS3 CPU select bit" "0,1"
|
|
bitfld.long 0x18 1. "CMPSS2,CMPSS2 CPU select bit" "0,1"
|
|
bitfld.long 0x18 0. "CMPSS1,CMPSS1 CPU select bit" "0,1"
|
|
line.long 0x1C "CPUSEL14,CPU Select register for common peripherals"
|
|
bitfld.long 0x1C 18. "DAC_C,Buffered_DAC12_3 CPU select bit" "0,1"
|
|
bitfld.long 0x1C 17. "DAC_B,Buffered_DAC12_2 CPU select bit" "0,1"
|
|
bitfld.long 0x1C 16. "DAC_A,Buffered_DAC12_1 CPU select bit" "0,1"
|
|
line.long 0x1E "CPUSEL15,CPU Select register for common peripherals"
|
|
bitfld.long 0x1E 3. "CLB4,CLB4 CPU select bit" "0,1"
|
|
bitfld.long 0x1E 2. "CLB3,CLB3 CPU select bit" "0,1"
|
|
bitfld.long 0x1E 1. "CLB2,CLB2 CPU select bit" "0,1"
|
|
bitfld.long 0x1E 0. "CLB1,CLB1 CPU select bit" "0,1"
|
|
line.long 0x20 "CPUSEL16,CPU Select register for common peripherals"
|
|
bitfld.long 0x20 23. "FSIRX_H,FSIRX_H CPU select bit" "0,1"
|
|
bitfld.long 0x20 22. "FSIRX_G,FSIRX_G CPU select bit" "0,1"
|
|
bitfld.long 0x20 21. "FSIRX_F,FSIRX_F CPU select bit" "0,1"
|
|
bitfld.long 0x20 20. "FSIRX_E,FSIRX_E CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 19. "FSIRX_D,FSIRX_D CPU select bit" "0,1"
|
|
bitfld.long 0x20 18. "FSIRX_C,FSIRX_C CPU select bit" "0,1"
|
|
bitfld.long 0x20 17. "FSIRX_B,FSIRX_B CPU select bit" "0,1"
|
|
bitfld.long 0x20 16. "FSIRX_A,FSIRX_A CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "FSITX_B,FSITX_B CPU select bit" "0,1"
|
|
bitfld.long 0x20 0. "FSITX_A,FSITX_A CPU select bit" "0,1"
|
|
line.long 0x24 "CPUSEL18,CPU Select register for common peripherals"
|
|
bitfld.long 0x24 0. "PMBUS_A,PMBUS_A CPU select bit" "0,1"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "CPUSEL25,CPU Select register for common peripherals"
|
|
bitfld.long 0x0 0. "HRCAL,HRCAL CPU select bit" "0,1"
|
|
group.long 0x122++0x3
|
|
line.long 0x0 "CPU2RESCTL,CPU2 Reset Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x0 0. "RESET,CPU2 Reset Control bit" "0,1"
|
|
group.word 0x124++0x1
|
|
line.word 0x0 "RSTSTAT,Reset Status register for secondary C28x CPUs"
|
|
bitfld.word 0x0 2.--3. "CPU2HWBISTRST,Tells whether a HWBIST reset was issued to CPU2 or not" "0,1,2,3"
|
|
bitfld.word 0x0 1. "CPU2NMIWDRST,Tells whether a CPU2.NMIWD reset was issued to CPU2 or not" "0,1"
|
|
rbitfld.word 0x0 0. "CPU2RES,CPU2 Reset Status bit" "0,1"
|
|
rgroup.word 0x125++0x1
|
|
line.word 0x0 "LPMSTAT,LPM Status Register for secondary C28x CPUs"
|
|
bitfld.word 0x0 0.--1. "CPU2LPMSTAT,CPU2 LPM Status" "0,1,2,3"
|
|
group.long 0x184++0x3
|
|
line.long 0x0 "BANKSEL,Configures the bank to programmed by CPU1."
|
|
bitfld.long 0x0 0.--1. "SEL,Selects the BANK to be programmed by CPU1 FMC." "0,1,2,3"
|
|
group.word 0x19A++0x7
|
|
line.word 0x0 "USBTYPE,Configures USB Type for the device"
|
|
bitfld.word 0x0 15. "LOCK,Lock bit" "0,1"
|
|
bitfld.word 0x0 0.--1. "TYPE,Configure USB type" "0,1,2,3"
|
|
line.word 0x1 "ECAPTYPE,Configures ECAP Type for the device"
|
|
bitfld.word 0x1 15. "LOCK,Lock bit" "0,1"
|
|
bitfld.word 0x1 0.--1. "TYPE,Configure ECAP type" "0,1,2,3"
|
|
line.word 0x2 "SDFMTYPE,Configures SDFM Type for the device"
|
|
bitfld.word 0x2 15. "LOCK,Lock bit" "0,1"
|
|
bitfld.word 0x2 0.--1. "TYPE,Configure SDFM type" "0,1,2,3"
|
|
line.word 0x4 "MEMMAPTYPE,Configures Memory Map Type for the device"
|
|
bitfld.word 0x4 15. "LOCK,Lock bit" "0,1"
|
|
bitfld.word 0x4 0.--1. "TYPE,Configures system specific features related to memory map." "0,1,2,3"
|
|
tree.end
|
|
tree "DMACLASRCSEL"
|
|
base d:0x7980
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CLA1TASKSRCSELLOCK,CLA1 Task Trigger Source Select Lock Register"
|
|
bitfld.long 0x0 1. "CLA1TASKSRCSEL2,CLA1TASKSRCSEL2 Register Lock bit" "0,1"
|
|
bitfld.long 0x0 0. "CLA1TASKSRCSEL1,CLA1TASKSRCSEL1 Register Lock bit" "0,1"
|
|
line.long 0x4 "DMACHSRCSELLOCK,DMA Channel Triger Source Select Lock Register"
|
|
bitfld.long 0x4 1. "DMACHSRCSEL2,DMACHSRCSEL2 Register Lock bit" "0,1"
|
|
bitfld.long 0x4 0. "DMACHSRCSEL1,DMACHSRCSEL1 Register Lock bit" "0,1"
|
|
line.long 0x6 "CLA1TASKSRCSEL1,CLA1 Task Trigger Source Select Register-1"
|
|
hexmask.long.byte 0x6 24.--31. 1. "TASK4,Selects the Trigger Source for TASK4 of CLA1"
|
|
hexmask.long.byte 0x6 16.--23. 1. "TASK3,Selects the Trigger Source for TASK3 of CLA1"
|
|
hexmask.long.byte 0x6 8.--15. 1. "TASK2,Selects the Trigger Source for TASK2 of CLA1"
|
|
hexmask.long.byte 0x6 0.--7. 1. "TASK1,Selects the Trigger Source for TASK1 of CLA1"
|
|
line.long 0x8 "CLA1TASKSRCSEL2,CLA1 Task Trigger Source Select Register-2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "TASK8,Selects the Trigger Source for TASK8 of CLA1"
|
|
hexmask.long.byte 0x8 16.--23. 1. "TASK7,Selects the Trigger Source for TASK7 of CLA1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "TASK6,Selects the Trigger Source for TASK6 of CLA1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TASK5,Selects the Trigger Source for TASK5 of CLA1"
|
|
group.long 0x16++0x7
|
|
line.long 0x0 "DMACHSRCSEL1,DMA Channel Trigger Source Select Register-1"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CH4,Selects the Trigger and Sync Source CH4 of DMA"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CH3,Selects the Trigger and Sync Source CH3 of DMA"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CH2,Selects the Trigger and Sync Source CH2 of DMA"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CH1,Selects the Trigger and Sync Source CH1 of DMA"
|
|
line.long 0x2 "DMACHSRCSEL2,DMA Channel Trigger Source Select Register-2"
|
|
hexmask.long.byte 0x2 8.--15. 1. "CH6,Selects the Trigger and Sync Source CH6 of DMA"
|
|
hexmask.long.byte 0x2 0.--7. 1. "CH5,Selects the Trigger and Sync Source CH5 of DMA"
|
|
tree.end
|
|
tree "MEMCFG"
|
|
base d:0x5F400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DxLOCK,Dedicated RAM Config Lock Register"
|
|
bitfld.long 0x0 3. "LOCK_D1,D1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_D0,D0 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_M1,M1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_M0,M0 RAM Lock bits" "0,1"
|
|
line.long 0x2 "DxCOMMIT,Dedicated RAM Config Lock Commit Register"
|
|
bitfld.long 0x2 3. "COMMIT_D1,D1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 2. "COMMIT_D0,D0 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 1. "COMMIT_M1,M1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 0. "COMMIT_M0,M0 RAM Permanent Lock bits" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DxACCPROT0,Dedicated RAM Config Register"
|
|
bitfld.long 0x0 25. "CPUWRPROT_D1,CPU WR Protection For D1 RAM" "0,1"
|
|
bitfld.long 0x0 24. "FETCHPROT_D1,Fetch Protection For D1 RAM" "0,1"
|
|
bitfld.long 0x0 17. "CPUWRPROT_D0,CPU WR Protection For D0 RAM" "0,1"
|
|
bitfld.long 0x0 16. "FETCHPROT_D0,Fetch Protection For D0 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CPUWRPROT_M1,CPU WR Protection For M1 RAM" "0,1"
|
|
bitfld.long 0x0 8. "FETCHPROT_M1,Fetch Protection For M1 RAM" "0,1"
|
|
bitfld.long 0x0 1. "CPUWRPROT_M0,CPU WR Protection For M0 RAM" "0,1"
|
|
bitfld.long 0x0 0. "FETCHPROT_M0,Fetch Protection For M0 RAM" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DxTEST,Dedicated RAM TEST Register"
|
|
bitfld.long 0x0 6.--7. "TEST_D1,Selects the different modes for D1 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "TEST_D0,Selects the different modes for D0 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "TEST_M1,Selects the different modes for M1 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TEST_M0,Selects the different modes for M0 RAM" "0,1,2,3"
|
|
line.long 0x2 "DxINIT,Dedicated RAM Init Register"
|
|
bitfld.long 0x2 3. "INIT_D1,RAM Initialization control for D1 RAM." "0,1"
|
|
bitfld.long 0x2 2. "INIT_D0,RAM Initialization control for D0 RAM." "0,1"
|
|
bitfld.long 0x2 1. "INIT_M1,RAM Initialization control for M1 RAM." "0,1"
|
|
bitfld.long 0x2 0. "INIT_M0,RAM Initialization control for M0 RAM." "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "DxINITDONE,Dedicated RAM InitDone Status Register"
|
|
bitfld.long 0x0 3. "INITDONE_D1,RAM Initialization status for D1 RAM." "0,1"
|
|
bitfld.long 0x0 2. "INITDONE_D0,RAM Initialization status for D0 RAM." "0,1"
|
|
bitfld.long 0x0 1. "INITDONE_M1,RAM Initialization status for M1 RAM." "0,1"
|
|
bitfld.long 0x0 0. "INITDONE_M0,RAM Initialization status for M0 RAM." "0,1"
|
|
group.long 0x16++0x3
|
|
line.long 0x0 "DxRAMTEST_LOCK,Lock register to Dx RAM TEST registers"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x0 3. "D1,DxTEST.TEST_D1 LOCK" "0,1"
|
|
bitfld.long 0x0 2. "D0,DxTEST.TEST_D0 LOCK" "0,1"
|
|
bitfld.long 0x0 1. "M1,DxTEST.TEST_M1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M0,DxTEST.TEST_M0 LOCK" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "LSxLOCK,Local Shared RAM Config Lock Register"
|
|
bitfld.long 0x0 7. "LOCK_LS7,LS7 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_LS6,LS6 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 5. "LOCK_LS5,LS5 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_LS4,LS4 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_LS3,LS3 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_LS2,LS2 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_LS1,LS1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_LS0,LS0 RAM Lock bits" "0,1"
|
|
line.long 0x2 "LSxCOMMIT,Local Shared RAM Config Lock Commit Register"
|
|
bitfld.long 0x2 7. "COMMIT_LS7,LS7 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 6. "COMMIT_LS6,LS6 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 5. "COMMIT_LS5,LS5 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 4. "COMMIT_LS4,LS4 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "COMMIT_LS3,LS3 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 2. "COMMIT_LS2,LS2 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 1. "COMMIT_LS1,LS1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 0. "COMMIT_LS0,LS0 RAM Permanent Lock bits" "0,1"
|
|
line.long 0x4 "LSxMSEL,Local Shared RAM Master Sel Register"
|
|
bitfld.long 0x4 14.--15. "MSEL_LS7,Master Select for LS7 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "MSEL_LS6,Master Select for LS6 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "MSEL_LS5,Master Select for LS5 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "MSEL_LS4,Master Select for LS4 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "MSEL_LS3,Master Select for LS3 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "MSEL_LS2,Master Select for LS2 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "MSEL_LS1,Master Select for LS1 RAM" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "MSEL_LS0,Master Select for LS0 RAM" "0,1,2,3"
|
|
line.long 0x6 "LSxCLAPGM,Local Shared RAM Prog/Exe control Register"
|
|
bitfld.long 0x6 7. "CLAPGM_LS7,Selects LS7 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x6 6. "CLAPGM_LS6,Selects LS6 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x6 5. "CLAPGM_LS5,Selects LS5 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x6 4. "CLAPGM_LS4,Selects LS4 RAM as program vs data memory for CLA" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "CLAPGM_LS3,Selects LS3 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x6 2. "CLAPGM_LS2,Selects LS2 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x6 1. "CLAPGM_LS1,Selects LS1 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x6 0. "CLAPGM_LS0,Selects LS0 RAM as program vs data memory for CLA" "0,1"
|
|
line.long 0x8 "LSxACCPROT0,Local Shared RAM Config Register 0"
|
|
bitfld.long 0x8 25. "CPUWRPROT_LS3,CPU WR Protection For LS3 RAM" "0,1"
|
|
bitfld.long 0x8 24. "FETCHPROT_LS3,Fetch Protection For LS3 RAM" "0,1"
|
|
bitfld.long 0x8 17. "CPUWRPROT_LS2,CPU WR Protection For LS2 RAM" "0,1"
|
|
bitfld.long 0x8 16. "FETCHPROT_LS2,Fetch Protection For LS2 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CPUWRPROT_LS1,CPU WR Protection For LS1 RAM" "0,1"
|
|
bitfld.long 0x8 8. "FETCHPROT_LS1,Fetch Protection For LS1 RAM" "0,1"
|
|
bitfld.long 0x8 1. "CPUWRPROT_LS0,CPU WR Protection For LS0 RAM" "0,1"
|
|
bitfld.long 0x8 0. "FETCHPROT_LS0,Fetch Protection For LS0 RAM" "0,1"
|
|
line.long 0xA "LSxACCPROT1,Local Shared RAM Config Register 1"
|
|
bitfld.long 0xA 25. "CPUWRPROT_LS7,CPU WR Protection For LS7 RAM" "0,1"
|
|
bitfld.long 0xA 24. "FETCHPROT_LS7,Fetch Protection For LS7 RAM" "0,1"
|
|
bitfld.long 0xA 17. "CPUWRPROT_LS6,CPU WR Protection For LS6 RAM" "0,1"
|
|
bitfld.long 0xA 16. "FETCHPROT_LS6,Fetch Protection For LS6 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xA 9. "CPUWRPROT_LS5,CPU WR Protection For LS5 RAM" "0,1"
|
|
bitfld.long 0xA 8. "FETCHPROT_LS5,Fetch Protection For LS5 RAM" "0,1"
|
|
bitfld.long 0xA 1. "CPUWRPROT_LS4,CPU WR Protection For LS4 RAM" "0,1"
|
|
bitfld.long 0xA 0. "FETCHPROT_LS4,Fetch Protection For LS4 RAM" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "LSxTEST,Local Shared RAM TEST Register"
|
|
bitfld.long 0x0 14.--15. "TEST_LS7,Selects the different modes for LS7 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "TEST_LS6,Selects the different modes for LS6 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "TEST_LS5,Selects the different modes for LS5 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "TEST_LS4,Selects the different modes for LS4 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TEST_LS3,Selects the different modes for LS3 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "TEST_LS2,Selects the different modes for LS2 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "TEST_LS1,Selects the different modes for LS1 RAM" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "TEST_LS0,Selects the different modes for LS0 RAM" "0,1,2,3"
|
|
line.long 0x2 "LSxINIT,Local Shared RAM Init Register"
|
|
bitfld.long 0x2 7. "INIT_LS7,RAM Initialization control for LS7 RAM." "0,1"
|
|
bitfld.long 0x2 6. "INIT_LS6,RAM Initialization control for LS6 RAM." "0,1"
|
|
bitfld.long 0x2 5. "INIT_LS5,RAM Initialization control for LS5 RAM." "0,1"
|
|
bitfld.long 0x2 4. "INIT_LS4,RAM Initialization control for LS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "INIT_LS3,RAM Initialization control for LS3 RAM." "0,1"
|
|
bitfld.long 0x2 2. "INIT_LS2,RAM Initialization control for LS2 RAM." "0,1"
|
|
bitfld.long 0x2 1. "INIT_LS1,RAM Initialization control for LS1 RAM." "0,1"
|
|
bitfld.long 0x2 0. "INIT_LS0,RAM Initialization control for LS0 RAM." "0,1"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "LSxINITDONE,Local Shared RAM InitDone Status Register"
|
|
bitfld.long 0x0 7. "INITDONE_LS7,RAM Initialization status for LS7 RAM." "0,1"
|
|
bitfld.long 0x0 6. "INITDONE_LS6,RAM Initialization status for LS6 RAM." "0,1"
|
|
bitfld.long 0x0 5. "INITDONE_LS5,RAM Initialization status for LS5 RAM." "0,1"
|
|
bitfld.long 0x0 4. "INITDONE_LS4,RAM Initialization status for LS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "INITDONE_LS3,RAM Initialization status for LS3 RAM." "0,1"
|
|
bitfld.long 0x0 2. "INITDONE_LS2,RAM Initialization status for LS2 RAM." "0,1"
|
|
bitfld.long 0x0 1. "INITDONE_LS1,RAM Initialization status for LS1 RAM." "0,1"
|
|
bitfld.long 0x0 0. "INITDONE_LS0,RAM Initialization status for LS0 RAM." "0,1"
|
|
group.long 0x36++0x3
|
|
line.long 0x0 "LSxRAMTEST_LOCK,Lock register to LSx RAM TEST registers"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x0 7. "LS7,LSxTEST.TEST_LS7 LOCK" "0,1"
|
|
bitfld.long 0x0 6. "LS6,LSxTEST.TEST_LS6 LOCK" "0,1"
|
|
bitfld.long 0x0 5. "LS5,LSxTEST.TEST_LS5 LOCK" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "LS4,LSxTEST.TEST_LS4 LOCK" "0,1"
|
|
bitfld.long 0x0 3. "LS3,LSxTEST.TEST_LS3 LOCK" "0,1"
|
|
bitfld.long 0x0 2. "LS2,LSxTEST.TEST_LS2 LOCK" "0,1"
|
|
bitfld.long 0x0 1. "LS1,LSxTEST.TEST_LS1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LS0,LSxTEST.TEST_LS0 LOCK" "0,1"
|
|
group.long 0x40++0x23
|
|
line.long 0x0 "GSxLOCK,Global Shared RAM Config Lock Register"
|
|
bitfld.long 0x0 15. "LOCK_GS15,GS15 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 14. "LOCK_GS14,GS14 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 13. "LOCK_GS13,GS13 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 12. "LOCK_GS12,GS12 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LOCK_GS11,GS11 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 10. "LOCK_GS10,GS10 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 9. "LOCK_GS9,GS9 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_GS8,GS8 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LOCK_GS7,GS7 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_GS6,GS6 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 5. "LOCK_GS5,GS5 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_GS4,GS4 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_GS3,GS3 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_GS2,GS2 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_GS1,GS1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_GS0,GS0 RAM Lock bits" "0,1"
|
|
line.long 0x2 "GSxCOMMIT,Global Shared RAM Config Lock Commit Register"
|
|
bitfld.long 0x2 15. "COMMIT_GS15,GS15 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 14. "COMMIT_GS14,GS14 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 13. "COMMIT_GS13,GS13 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 12. "COMMIT_GS12,GS12 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x2 11. "COMMIT_GS11,GS11 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 10. "COMMIT_GS10,GS10 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 9. "COMMIT_GS9,GS9 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 8. "COMMIT_GS8,GS8 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x2 7. "COMMIT_GS7,GS7 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 6. "COMMIT_GS6,GS6 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 5. "COMMIT_GS5,GS5 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 4. "COMMIT_GS4,GS4 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "COMMIT_GS3,GS3 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 2. "COMMIT_GS2,GS2 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 1. "COMMIT_GS1,GS1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x2 0. "COMMIT_GS0,GS0 RAM Permanent Lock bits" "0,1"
|
|
line.long 0x4 "GSxMSEL,Global Shared RAM Master Sel Register"
|
|
bitfld.long 0x4 15. "MSEL_GS15,Master Select for GS15 RAM" "0,1"
|
|
bitfld.long 0x4 14. "MSEL_GS14,Master Select for GS14 RAM" "0,1"
|
|
bitfld.long 0x4 13. "MSEL_GS13,Master Select for GS13 RAM" "0,1"
|
|
bitfld.long 0x4 12. "MSEL_GS12,Master Select for GS12 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MSEL_GS11,Master Select for GS11 RAM" "0,1"
|
|
bitfld.long 0x4 10. "MSEL_GS10,Master Select for GS10 RAM" "0,1"
|
|
bitfld.long 0x4 9. "MSEL_GS9,Master Select for GS9 RAM" "0,1"
|
|
bitfld.long 0x4 8. "MSEL_GS8,Master Select for GS8 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MSEL_GS7,Master Select for GS7 RAM" "0,1"
|
|
bitfld.long 0x4 6. "MSEL_GS6,Master Select for GS6 RAM" "0,1"
|
|
bitfld.long 0x4 5. "MSEL_GS5,Master Select for GS5 RAM" "0,1"
|
|
bitfld.long 0x4 4. "MSEL_GS4,Master Select for GS4 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MSEL_GS3,Master Select for GS3 RAM" "0,1"
|
|
bitfld.long 0x4 2. "MSEL_GS2,Master Select for GS2 RAM" "0,1"
|
|
bitfld.long 0x4 1. "MSEL_GS1,Master Select for GS1 RAM" "0,1"
|
|
bitfld.long 0x4 0. "MSEL_GS0,Master Select for GS0 RAM" "0,1"
|
|
line.long 0x8 "GSxACCPROT0,Global Shared RAM Access Protection Register 0"
|
|
bitfld.long 0x8 26. "DMAWRPROT_GS3,DMA WR Protection For GS3 RAM" "0,1"
|
|
bitfld.long 0x8 25. "CPUWRPROT_GS3,CPU WR Protection For GS3 RAM" "0,1"
|
|
bitfld.long 0x8 24. "FETCHPROT_GS3,Fetch Protection For GS3 RAM" "0,1"
|
|
bitfld.long 0x8 18. "DMAWRPROT_GS2,DMA WR Protection For GS2 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CPUWRPROT_GS2,CPU WR Protection For GS2 RAM" "0,1"
|
|
bitfld.long 0x8 16. "FETCHPROT_GS2,Fetch Protection For GS2 RAM" "0,1"
|
|
bitfld.long 0x8 10. "DMAWRPROT_GS1,DMA WR Protection For GS1 RAM" "0,1"
|
|
bitfld.long 0x8 9. "CPUWRPROT_GS1,CPU WR Protection For GS1 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FETCHPROT_GS1,Fetch Protection For GS1 RAM" "0,1"
|
|
bitfld.long 0x8 2. "DMAWRPROT_GS0,DMA WR Protection For GS0 RAM" "0,1"
|
|
bitfld.long 0x8 1. "CPUWRPROT_GS0,CPU WR Protection For GS0 RAM" "0,1"
|
|
bitfld.long 0x8 0. "FETCHPROT_GS0,Fetch Protection For GS0 RAM" "0,1"
|
|
line.long 0xA "GSxACCPROT1,Global Shared RAM Access Protection Register 1"
|
|
bitfld.long 0xA 26. "DMAWRPROT_GS7,DMA WR Protection For GS7RAM" "0,1"
|
|
bitfld.long 0xA 25. "CPUWRPROT_GS7,CPU WR Protection For GS7 RAM" "0,1"
|
|
bitfld.long 0xA 24. "FETCHPROT_GS7,Fetch Protection For GS7 RAM" "0,1"
|
|
bitfld.long 0xA 18. "DMAWRPROT_GS6,DMA WR Protection For GS6RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xA 17. "CPUWRPROT_GS6,CPU WR Protection For GS6 RAM" "0,1"
|
|
bitfld.long 0xA 16. "FETCHPROT_GS6,Fetch Protection For GS6 RAM" "0,1"
|
|
bitfld.long 0xA 10. "DMAWRPROT_GS5,DMA WR Protection For GS5RAM" "0,1"
|
|
bitfld.long 0xA 9. "CPUWRPROT_GS5,CPU WR Protection For GS5 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xA 8. "FETCHPROT_GS5,Fetch Protection For GS5 RAM" "0,1"
|
|
bitfld.long 0xA 2. "DMAWRPROT_GS4,DMA WR Protection For GS4 RAM" "0,1"
|
|
bitfld.long 0xA 1. "CPUWRPROT_GS4,CPU WR Protection For GS4 RAM" "0,1"
|
|
bitfld.long 0xA 0. "FETCHPROT_GS4,Fetch Protection For GS4 RAM" "0,1"
|
|
line.long 0xC "GSxACCPROT2,Global Shared RAM Access Protection Register 2"
|
|
bitfld.long 0xC 26. "DMAWRPROT_GS11,DMA WR Protection For GS11RAM" "0,1"
|
|
bitfld.long 0xC 25. "CPUWRPROT_GS11,CPU WR Protection For GS11 RAM" "0,1"
|
|
bitfld.long 0xC 24. "FETCHPROT_GS11,Fetch Protection For GS11 RAM" "0,1"
|
|
bitfld.long 0xC 18. "DMAWRPROT_GS10,DMA WR Protection For GS10RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "CPUWRPROT_GS10,CPU WR Protection For GS10 RAM" "0,1"
|
|
bitfld.long 0xC 16. "FETCHPROT_GS10,Fetch Protection For GS10 RAM" "0,1"
|
|
bitfld.long 0xC 10. "DMAWRPROT_GS9,DMA WR Protection For GS9RAM" "0,1"
|
|
bitfld.long 0xC 9. "CPUWRPROT_GS9,CPU WR Protection For GS9 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "FETCHPROT_GS9,Fetch Protection For GS9 RAM" "0,1"
|
|
bitfld.long 0xC 2. "DMAWRPROT_GS8,DMA WR Protection For GS8 RAM" "0,1"
|
|
bitfld.long 0xC 1. "CPUWRPROT_GS8,CPU WR Protection For GS8 RAM" "0,1"
|
|
bitfld.long 0xC 0. "FETCHPROT_GS8,Fetch Protection For GS8 RAM" "0,1"
|
|
line.long 0xE "GSxACCPROT3,Global Shared RAM Access Protection Register 3"
|
|
bitfld.long 0xE 26. "DMAWRPROT_GS15,DMA WR Protection For GS15RAM" "0,1"
|
|
bitfld.long 0xE 25. "CPUWRPROT_GS15,CPU WR Protection For GS15 RAM" "0,1"
|
|
bitfld.long 0xE 24. "FETCHPROT_GS15,Fetch Protection For GS15 RAM" "0,1"
|
|
bitfld.long 0xE 18. "DMAWRPROT_GS14,DMA WR Protection For GS14RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xE 17. "CPUWRPROT_GS14,CPU WR Protection For GS14 RAM" "0,1"
|
|
bitfld.long 0xE 16. "FETCHPROT_GS14,Fetch Protection For GS14 RAM" "0,1"
|
|
bitfld.long 0xE 10. "DMAWRPROT_GS13,DMA WR Protection For GS13RAM" "0,1"
|
|
bitfld.long 0xE 9. "CPUWRPROT_GS13,CPU WR Protection For GS13 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xE 8. "FETCHPROT_GS13,Fetch Protection For GS13 RAM" "0,1"
|
|
bitfld.long 0xE 2. "DMAWRPROT_GS12,DMA WR Protection For GS12 RAM" "0,1"
|
|
bitfld.long 0xE 1. "CPUWRPROT_GS12,CPU WR Protection For GS12 RAM" "0,1"
|
|
bitfld.long 0xE 0. "FETCHPROT_GS12,Fetch Protection For GS12 RAM" "0,1"
|
|
line.long 0x10 "GSxTEST,Global Shared RAM TEST Register"
|
|
bitfld.long 0x10 30.--31. "TEST_GS15,Selects the different modes for GS15 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "TEST_GS14,Selects the different modes for GS14 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "TEST_GS13,Selects the different modes for GS13 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "TEST_GS12,Selects the different modes for GS12 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 22.--23. "TEST_GS11,Selects the different modes for GS11 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "TEST_GS10,Selects the different modes for GS10 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "TEST_GS9,Selects the different modes for GS9 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "TEST_GS8,Selects the different modes for GS8 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "TEST_GS7,Selects the different modes for GS7 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "TEST_GS6,Selects the different modes for GS6 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "TEST_GS5,Selects the different modes for GS5 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "TEST_GS4,Selects the different modes for GS4 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "TEST_GS3,Selects the different modes for GS3 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "TEST_GS2,Selects the different modes for GS2 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "TEST_GS1,Selects the different modes for GS1 RAM" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "TEST_GS0,Selects the different modes for GS0 RAM" "0,1,2,3"
|
|
line.long 0x12 "GSxINIT,Global Shared RAM Init Register"
|
|
bitfld.long 0x12 15. "INIT_GS15,RAM Initialization control for GS15 RAM." "0,1"
|
|
bitfld.long 0x12 14. "INIT_GS14,RAM Initialization control for GS14 RAM." "0,1"
|
|
bitfld.long 0x12 13. "INIT_GS13,RAM Initialization control for GS13 RAM." "0,1"
|
|
bitfld.long 0x12 12. "INIT_GS12,RAM Initialization control for GS12 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x12 11. "INIT_GS11,RAM Initialization control for GS11 RAM." "0,1"
|
|
bitfld.long 0x12 10. "INIT_GS10,RAM Initialization control for GS10 RAM." "0,1"
|
|
bitfld.long 0x12 9. "INIT_GS9,RAM Initialization control for GS9 RAM." "0,1"
|
|
bitfld.long 0x12 8. "INIT_GS8,RAM Initialization control for GS8 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x12 7. "INIT_GS7,RAM Initialization control for GS7 RAM." "0,1"
|
|
bitfld.long 0x12 6. "INIT_GS6,RAM Initialization control for GS6 RAM." "0,1"
|
|
bitfld.long 0x12 5. "INIT_GS5,RAM Initialization control for GS5 RAM." "0,1"
|
|
bitfld.long 0x12 4. "INIT_GS4,RAM Initialization control for GS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x12 3. "INIT_GS3,RAM Initialization control for GS3 RAM." "0,1"
|
|
bitfld.long 0x12 2. "INIT_GS2,RAM Initialization control for GS2 RAM." "0,1"
|
|
bitfld.long 0x12 1. "INIT_GS1,RAM Initialization control for GS1 RAM." "0,1"
|
|
bitfld.long 0x12 0. "INIT_GS0,RAM Initialization control for GS0 RAM." "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "GSxINITDONE,Global Shared RAM InitDone Status Register"
|
|
bitfld.long 0x0 15. "INITDONE_GS15,RAM Initialization status for GS15 RAM." "0,1"
|
|
bitfld.long 0x0 14. "INITDONE_GS14,RAM Initialization status for GS14 RAM." "0,1"
|
|
bitfld.long 0x0 13. "INITDONE_GS13,RAM Initialization status for GS13 RAM." "0,1"
|
|
bitfld.long 0x0 12. "INITDONE_GS12,RAM Initialization status for GS12 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "INITDONE_GS11,RAM Initialization status for GS11 RAM." "0,1"
|
|
bitfld.long 0x0 10. "INITDONE_GS10,RAM Initialization status for GS10 RAM." "0,1"
|
|
bitfld.long 0x0 9. "INITDONE_GS9,RAM Initialization status for GS9 RAM." "0,1"
|
|
bitfld.long 0x0 8. "INITDONE_GS8,RAM Initialization status for GS8 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "INITDONE_GS7,RAM Initialization status for GS7 RAM." "0,1"
|
|
bitfld.long 0x0 6. "INITDONE_GS6,RAM Initialization status for GS6 RAM." "0,1"
|
|
bitfld.long 0x0 5. "INITDONE_GS5,RAM Initialization status for GS5 RAM." "0,1"
|
|
bitfld.long 0x0 4. "INITDONE_GS4,RAM Initialization status for GS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "INITDONE_GS3,RAM Initialization status for GS3 RAM." "0,1"
|
|
bitfld.long 0x0 2. "INITDONE_GS2,RAM Initialization status for GS2 RAM." "0,1"
|
|
bitfld.long 0x0 1. "INITDONE_GS1,RAM Initialization status for GS1 RAM." "0,1"
|
|
bitfld.long 0x0 0. "INITDONE_GS0,RAM Initialization status for GS0 RAM." "0,1"
|
|
group.long 0x56++0x3
|
|
line.long 0x0 "GSxRAMTEST_LOCK,Lock register to GSx RAM TEST registers"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x0 15. "GS15,GSxTEST.TEST_GS15 LOCK" "0,1"
|
|
bitfld.long 0x0 14. "GS14,GSxTEST.TEST_GS14 LOCK" "0,1"
|
|
bitfld.long 0x0 13. "GS13,GSxTEST.TEST_GS13 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "GS12,GSxTEST.TEST_GS12 LOCK" "0,1"
|
|
bitfld.long 0x0 11. "GS11,GSxTEST.TEST_GS11 LOCK" "0,1"
|
|
bitfld.long 0x0 10. "GS10,GSxTEST.TEST_GS10 LOCK" "0,1"
|
|
bitfld.long 0x0 9. "GS9,GSxTEST.TEST_GS9 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "GS8,GSxTEST.TEST_GS8 LOCK" "0,1"
|
|
bitfld.long 0x0 7. "GS7,GSxTEST.TEST_GS7 LOCK" "0,1"
|
|
bitfld.long 0x0 6. "GS6,GSxTEST.TEST_GS6 LOCK" "0,1"
|
|
bitfld.long 0x0 5. "GS5,GSxTEST.TEST_GS5 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "GS4,GSxTEST.TEST_GS4 LOCK" "0,1"
|
|
bitfld.long 0x0 3. "GS3,GSxTEST.TEST_GS3 LOCK" "0,1"
|
|
bitfld.long 0x0 2. "GS2,GSxTEST.TEST_GS2 LOCK" "0,1"
|
|
bitfld.long 0x0 1. "GS1,GSxTEST.TEST_GS1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "GS0,GSxTEST.TEST_GS0 LOCK" "0,1"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "MSGxLOCK,Message RAM Config Lock Register"
|
|
bitfld.long 0x0 11. "LOCK_DMATOCLA2,Lock bit of DMA to CLA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x0 10. "LOCK_CLA2TODMA,Lock bit of CLA to DMA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x0 9. "LOCK_CPUTOCM_MSGRAM1,Lock bit of CPU to CM MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_CPUTOCM_MSGRAM0,Lock bit of CPU to CM MSG RAM0 control fields" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LOCK_CPUTOCPU_MSGRAM1,Lock bit of CPU to CPU MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_DMATOCLA1,DMATOCLA1 RAM control fields lock bit" "0,1"
|
|
bitfld.long 0x0 5. "LOCK_CLA1TODMA,CLA1TODMA RAM control fields lock bit" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_CLA1TOCPU,CLA1TOCPU RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK_CPUTOCLA1,CPUTOCLA1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_CPUTOCPU_MSGRAM0,CPUTOCPU RAM Lock bits" "0,1"
|
|
line.long 0x2 "MSGxCOMMIT,Message RAM Config Lock Commit Register"
|
|
bitfld.long 0x2 11. "COMMIT_DMATOCLA_MSGRAM1,Commint bit of DMA to CLA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x2 10. "COMMIT_CLATODMA_MSGRAM0,Commint bit of CLA to DMA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x2 9. "COMMIT_CPUTOCM_MSGRAM1,Commint bit of CPU to CM MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x2 8. "COMMIT_CPUTOCM_MSGRAM0,Commint bit of CPU to CM MSG RAM0 control fields" "0,1"
|
|
newline
|
|
bitfld.long 0x2 7. "COMMIT_CPUTOCPU_MSGRAM1,Commint bit of CPU to CPU MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x2 6. "COMMIT_DMATOCLA1,DMATOCLA1 RAM control fields COMMIT bit" "0,1"
|
|
bitfld.long 0x2 5. "COMMIT_CLA1TODMA,CLA1TODMA RAM control fields COMMIT bit" "0,1"
|
|
bitfld.long 0x2 2. "COMMIT_CLA1TOCPU,CLA1TOCPU RAM control fields COMMIT bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2 1. "COMMIT_CPUTOCLA1,CPUTOCLA1 RAM control fields COMMIT bit" "0,1"
|
|
bitfld.long 0x2 0. "COMMIT_CPUTOCPU_MSGRAM0,CPUTOCPU RAM control fields COMMIT bit" "0,1"
|
|
group.long 0x68++0x13
|
|
line.long 0x0 "MSGxACCPROT0,Message RAM Access Protection Register 0"
|
|
bitfld.long 0x0 2. "DMAWRPROT_CPUTOCPU_MSGRAM0,DMA WR Protection For CPUTOCPU_MSGRAM0 RAM" "0,1"
|
|
bitfld.long 0x0 1. "CPUWRPROT_CPUTOCPU_MSGRAM0,CPU WR Protection For CPUTOCPU_MSGRAM0 RAM" "0,1"
|
|
line.long 0x2 "MSGxACCPROT1,Message RAM Access Protection Register 1"
|
|
bitfld.long 0x2 26. "DMAWRPROT_CPUTOCPU_MSGRAM1,DMA WR Protection For CPUTOCPU_MSGRAM1RAM" "0,1"
|
|
bitfld.long 0x2 25. "CPUWRPROT_CPUTOCPU_MSGRAM1,CPU WR Protection For CPUTOCPU_MSGRAM1 RAM" "0,1"
|
|
line.long 0x4 "MSGxACCPROT2,Message RAM Access Protection Register 2"
|
|
bitfld.long 0x4 10. "DMAWRPROT_CPUTOCM_MSGRAM1,DMA WR Protection For CPUTOCM_MSGRAM1RAM" "0,1"
|
|
bitfld.long 0x4 9. "CPUWRPROT_CPUTOCM_MSGRAM1,CPU WR Protection For CPUTOCM_MSGRAM1 RAM" "0,1"
|
|
bitfld.long 0x4 2. "DMAWRPROT_CPUTOCM_MSGRAM0,DMA WR Protection For CPUTOCM_MSGRAM0 RAM" "0,1"
|
|
bitfld.long 0x4 1. "CPUWRPROT_CPUTOCM_MSGRAM0,CPU WR Protection For CPUTOCM_MSGRAM0 RAM" "0,1"
|
|
line.long 0x8 "MSGxTEST,Message RAM TEST Register"
|
|
bitfld.long 0x8 18.--19. "TEST_CPUTOCM_MSGRAM1,CPU to CM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "TEST_CPUTOCM_MSGRAM0,CPU to CM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "TEST_CPUTOCPU_MSGRAM1,CPU to CPU Mode Select" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "TEST_DMATOCLA1,DMA to CLA1 MSG RAM Mode Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "TEST_CLA1TODMA,CLA1 to DMA MSG RAM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "TEST_CLA1TOCPU,CLA1 to CPU MSG RAM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "TEST_CPUTOCLA1,CPU to CLA1 MSG RAM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "TEST_CPUTOCPU_MSGRAM0,CPU to CPU Mode Select" "0,1,2,3"
|
|
line.long 0xA "MSGxINIT,Message RAM Init Register"
|
|
bitfld.long 0xA 9. "INIT_CPUTOCM_MSGRAM1,Initialization control for CPU to CM MSG RAM1" "0,1"
|
|
bitfld.long 0xA 8. "INIT_CPUTOCM_MSGRAM0,Initialization control for CPU to CM MSG RAM0" "0,1"
|
|
bitfld.long 0xA 7. "INIT_CPUTOCPU_MSGRAM1,Initialization control for CPU to CPU MSG RAM1" "0,1"
|
|
bitfld.long 0xA 6. "INIT_DMATOCLA1,Initialization control for DMA to CLA1 MSG RAM" "0,1"
|
|
newline
|
|
bitfld.long 0xA 5. "INIT_CLA1TODMA,Initialization control for CLA1 to DMA MSG RAM" "0,1"
|
|
bitfld.long 0xA 2. "INIT_CLA1TOCPU,Initialization control for CLA1TOCPU MSG RAM" "0,1"
|
|
bitfld.long 0xA 1. "INIT_CPUTOCLA1,Initialization control for CPUTOCLA1 MSG RAM" "0,1"
|
|
bitfld.long 0xA 0. "INIT_CPUTOCPU_MSGRAM0,Initialization control for CPU to CPU MSG RAM0" "0,1"
|
|
rgroup.long 0x74++0x3
|
|
line.long 0x0 "MSGxINITDONE,Message RAM InitDone Status Register"
|
|
bitfld.long 0x0 9. "INITDONE_CPUTOCM_MSGRAM1,Initialization status for CPU to CM MSG RAM1" "0,1"
|
|
bitfld.long 0x0 8. "INITDONE_CPUTOCM_MSGRAM0,Initialization status for CPU to CM MSG RAM0" "0,1"
|
|
bitfld.long 0x0 7. "INITDONE_CPUTOCPU_MSGRAM1,Initialization status for CPU to CPU MSG RAM1" "0,1"
|
|
bitfld.long 0x0 6. "INITDONE_DMATOCLA1,Initialization status for DMA to CLA1 MSG RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "INITDONE_CLA1TODMA,Initialization status for CLA1 to DMA MSG RAM" "0,1"
|
|
bitfld.long 0x0 2. "INITDONE_CLA1TOCPU,Initialization status for CLA1 to CPU MSG RAM" "0,1"
|
|
bitfld.long 0x0 1. "INITDONE_CPUTOCLA1,Initialization status for CPU to CLA1 MSG RAM" "0,1"
|
|
bitfld.long 0x0 0. "INITDONE_CPUTOCPU_MSGRAM0,Initialization status for CPU to CPU MSG RAM" "0,1"
|
|
group.long 0x76++0x3
|
|
line.long 0x0 "MSGxRAMTEST_LOCK,Lock register to MSGx RAM TEST registers"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x0 11. "DMATOCLA2,MSGxTEST.TEST_DMATOCLA2 LOCK" "0,1"
|
|
bitfld.long 0x0 10. "CLA2TODMA,MSGxTEST.TEST_CLA2TODMA LOCK" "0,1"
|
|
bitfld.long 0x0 9. "CPUTOCM_MSGRAM1,MSGxTEST.TEST_CPUTOCM_MSGRAM1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CPUTOCM_MSGRAM0,MSGxTEST.TEST_CPUTOCM_MSGRAM0 LOCK" "0,1"
|
|
bitfld.long 0x0 7. "CPUTOCPU_MSGRAM1,MSGxTEST.TEST_CPUTOCPU_MSGRAM1 LOCK" "0,1"
|
|
bitfld.long 0x0 6. "DMATOCLA1,MSGxTEST.TEST_DMATOCLA1 LOCK" "0,1"
|
|
bitfld.long 0x0 5. "CLA1TODMA,MSGxTEST.TEST_CLA1TODMA LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CLA2TOCPU,MSGxTEST.TEST_CLA2TOCPU LOCK" "0,1"
|
|
bitfld.long 0x0 3. "CPUTOCLA2,MSGxTEST.TEST_CPUTOCLA2 LOCK" "0,1"
|
|
bitfld.long 0x0 2. "CLA1TOCPU,MSGxTEST.TEST_CLA1TOCPU LOCK" "0,1"
|
|
bitfld.long 0x0 1. "CPUTOCLA1,MSGxTEST.TEST_CPUTOCLA1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPUTOCPU_MSGRAM0,MSGxTEST.TEST_CPUTOCPU_MSGRAM0 LOCK" "0,1"
|
|
group.long 0xA0++0xB
|
|
line.long 0x0 "ROM_LOCK,ROM Config Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x0 2. "LOCK_CLADATAROM,CLADATAROM Lock bits" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_SECUREROM,SECUREROM Lock bits" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_BOOTROM,BOOTROM Lock bits" "0,1"
|
|
line.long 0x2 "ROM_TEST,ROM TEST Register"
|
|
bitfld.long 0x2 4.--5. "TEST_CLADATAROM,Selects the different modes for CLADATAROM" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "TEST_SECUREROM,Selects the different modes for SECUREROM" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "TEST_BOOTROM,Selects the different modes for BOOTROM" "0,1,2,3"
|
|
line.long 0x4 "ROM_FORCE_ERROR,ROM Force Error register"
|
|
bitfld.long 0x4 2. "FORCE_CLADATAROM_ERROR,Force CLADATAROM Parity Error" "0,1"
|
|
bitfld.long 0x4 1. "FORCE_SECUREROM_ERROR,Force SECUREROM Parity Error" "0,1"
|
|
bitfld.long 0x4 0. "FORCE_BOOTROM_ERROR,Force Bootrom Parity Error" "0,1"
|
|
group.long 0xAA++0x7
|
|
line.long 0x0 "PERI_MEM_TEST_LOCK,Peripheral Memory Test Lock Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x0 0. "LOCK_PERI_MEM_TEST_CONTROL,PERI_MEM_TEST_CONTROL Lock bit" "0,1"
|
|
line.long 0x2 "PERI_MEM_TEST_CONTROL,Peripheral Memory Test control Register"
|
|
bitfld.long 0x2 5. "EtherCAT_MEM_FORCE_ERROR,Force Parity Error on EtherCAT RAM" "0,1"
|
|
bitfld.long 0x2 4. "EtherCAT_TEST_ENABLE,EtherCAT Test mode enable" "0,1"
|
|
tree.end
|
|
tree "MEMORYERROR"
|
|
base d:0x5F540
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "UCERRFLG,Uncorrectable Error Flag Register"
|
|
bitfld.long 0x0 4. "ECATRAMRDERR,ECAT RAM Read Error Flag" "0,1"
|
|
bitfld.long 0x0 2. "CLA1RDERR,CLA1 Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "DMARDERR,DMA Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "CPURDERR,CPU Uncorrectable Read Error Flag" "0,1"
|
|
group.long 0x2++0x7
|
|
line.long 0x0 "UCERRSET,Uncorrectable Error Flag Set Register"
|
|
bitfld.long 0x0 4. "ECATRAMRDERR,ECAT RAM Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 2. "CLA1RDERR,CLA1 Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 1. "DMARDERR,DMA Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 0. "CPURDERR,CPU Uncorrectable Read Error Flag Set" "0,1"
|
|
line.long 0x2 "UCERRCLR,Uncorrectable Error Flag Clear Register"
|
|
bitfld.long 0x2 4. "ECATRAMRDERR,ECAT RAM Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x2 2. "CLA1RDERR,CLA1 Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x2 1. "DMARDERR,DMA Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x2 0. "CPURDERR,CPU Uncorrectable Read Error Flag Clear" "0,1"
|
|
rgroup.long 0x6++0xF
|
|
line.long 0x0 "UCCPUREADDR,Uncorrectable CPU Read Error Address"
|
|
hexmask.long 0x0 0.--31. 1. "UCCPUREADDR,Uncorrectable CPU read/fetch access address register."
|
|
line.long 0x2 "UCDMAREADDR,Uncorrectable DMA Read Error Address"
|
|
hexmask.long 0x2 0.--31. 1. "UCDMAREADDR,Uncorrectable DMA read access address register."
|
|
line.long 0x4 "UCCLA1READDR,Uncorrectable CLA1 Read Error Address"
|
|
hexmask.long 0x4 0.--31. 1. "UCCLA1READDR,Uncorrectable CLA1 read/fetch access address register."
|
|
line.long 0x8 "UCECATRAMADDR,Uncorrectable etherCAT RAM Read Error Address"
|
|
hexmask.long 0x8 0.--31. 1. "UCECATRAMADDR,Uncorrectable ECAT RAM address register."
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "CERRFLG,Correctable Error Flag Register"
|
|
bitfld.long 0x0 2. "CLA1RDERR,CLA1 Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 1. "DMARDERR,DMA Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x0 0. "CPURDERR,CPU Correctable Read Error Flag" "0,1"
|
|
group.long 0x22++0x7
|
|
line.long 0x0 "CERRSET,Correctable Error Flag Set Register"
|
|
bitfld.long 0x0 2. "CLA1RDERR,CLA1 Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 1. "DMARDERR,DMA Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x0 0. "CPURDERR,CPU Correctable Read Error Flag Set" "0,1"
|
|
line.long 0x2 "CERRCLR,Correctable Error Flag Clear Register"
|
|
bitfld.long 0x2 2. "CLA1RDERR,CLA1 Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x2 1. "DMARDERR,DMA Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x2 0. "CPURDERR,CPU Correctable Read Error Flag Clear" "0,1"
|
|
rgroup.long 0x26++0x7
|
|
line.long 0x0 "CCPUREADDR,Correctable CPU Read Error Address"
|
|
hexmask.long 0x0 0.--31. 1. "CCPUREADDR,Correctable CPU read/fetch access address register."
|
|
line.long 0x4 "CCLA1READDR,Correctable CLA1 Read Error Address"
|
|
hexmask.long 0x4 0.--31. 1. "CCLA1READDR,Correctable CLA1 read/fetch access address register."
|
|
group.long 0x2E++0x7
|
|
line.long 0x0 "CERRCNT,Correctable Error Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CERRCNT,Correctable error count."
|
|
line.long 0x2 "CERRTHRES,Correctable Error Threshold Value Register"
|
|
hexmask.long.word 0x2 0.--15. 1. "CERRTHRES,Correctable error threshold."
|
|
rgroup.long 0x32++0x3
|
|
line.long 0x0 "CEINTFLG,Correctable Error Interrupt Flag Status Register"
|
|
bitfld.long 0x0 0. "CEINTFLAG,Total corrected error count exceeded threshold flag." "0,1"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "CEINTCLR,Correctable Error Interrupt Flag Clear Register"
|
|
bitfld.long 0x0 0. "CEINTCLR,CPU Corrected Error Threshold Exceeded Error Clear." "0,1"
|
|
line.long 0x2 "CEINTSET,Correctable Error Interrupt Flag Set Register"
|
|
bitfld.long 0x2 0. "CEINTSET,Total corrected error count exceeded flag set." "0,1"
|
|
line.long 0x4 "CEINTEN,Correctable Error Interrupt Enable Register"
|
|
bitfld.long 0x4 0. "CEINTEN,CPU/DMA/CLA Correctable Error Interrupt Enable." "0,1"
|
|
tree.end
|
|
tree "NMIINTRUPT"
|
|
base d:0x7060
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "NMICFG,NMI Configuration Register"
|
|
bitfld.word 0x0 0. "NMIE,Global NMI Enable" "0,1"
|
|
rgroup.word 0x1++0x1
|
|
line.word 0x0 "NMIFLG,NMI Flag Register (SYSRsn Clear)"
|
|
bitfld.word 0x0 14. "CRC_FAIL,CRC calculation failed." "0,1"
|
|
bitfld.word 0x0 13. "ECATNMIn,NMI from EtherCAT reset out" "0,1"
|
|
bitfld.word 0x0 12. "CMNMIWDRSn,CM NMI watch dog has timed out." "0,1"
|
|
bitfld.word 0x0 10. "CPU2NMIWDRSn,CPU2 NMIWDRSn Reset Indication Flag" "0,1"
|
|
bitfld.word 0x0 9. "CPU2WDRSn,CPU2 WDRSn Reset Indication Flag" "0,1"
|
|
bitfld.word 0x0 8. "CLBNMI,Configurable Logic Block NMI Flag" "0,1"
|
|
bitfld.word 0x0 7. "ERADNMI,ERAD Module NMI Flag" "0,1"
|
|
bitfld.word 0x0 6. "PIEVECTERR,PIE Vector Fetch Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "CPU2HWBISTERR,HW BIST Error NMI Flag" "0,1"
|
|
bitfld.word 0x0 4. "CPU1HWBISTERR,HW BIST Error NMI Flag" "0,1"
|
|
bitfld.word 0x0 3. "FLUNCERR,Flash Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.word 0x0 2. "RAMUNCERR,RAM Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.word 0x0 1. "CLOCKFAIL,Clock Fail Interrupt Flag" "0,1"
|
|
bitfld.word 0x0 0. "NMIINT,NMI Interrupt Flag" "0,1"
|
|
group.word 0x2++0x3
|
|
line.word 0x0 "NMIFLGCLR,NMI Flag Clear Register"
|
|
bitfld.word 0x0 14. "CRC_FAIL,CRC_FAIL flag clear" "0,1"
|
|
bitfld.word 0x0 13. "ECATNMIn,ECATNMIn flag clear" "0,1"
|
|
bitfld.word 0x0 12. "CMNMIWDRSn,DCDCOLF Flag Clear" "0,1"
|
|
bitfld.word 0x0 10. "CPU2NMIWDRSn,CPU2NMIWDRSn Flag Clear" "0,1"
|
|
bitfld.word 0x0 9. "CPU2WDRSn,CPU2WDRSn Flag Clear" "0,1"
|
|
bitfld.word 0x0 8. "CLBNMI,CLBNMI Flag Clear" "0,1"
|
|
bitfld.word 0x0 7. "ERADNMI,ERADNMI Flag Clear" "0,1"
|
|
bitfld.word 0x0 6. "PIEVECTERR,PIEVECTERR Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "CPU2HWBISTERR,CPU2HWBISTERR Flag Clear" "0,1"
|
|
bitfld.word 0x0 4. "CPU1HWBISTERR,CPU1HWBISTERR Flag Clear" "0,1"
|
|
bitfld.word 0x0 3. "FLUNCERR,FLUNCERR Flag Clear" "0,1"
|
|
bitfld.word 0x0 2. "RAMUNCERR,RAMUNCERR Flag Clear" "0,1"
|
|
bitfld.word 0x0 1. "CLOCKFAIL,CLOCKFAIL Flag Clear" "0,1"
|
|
bitfld.word 0x0 0. "NMIINT,NMIINT Flag Clear" "0,1"
|
|
line.word 0x1 "NMIFLGFRC,NMI Flag Force Register"
|
|
bitfld.word 0x1 14. "CRC_FAIL,CRC_FAIL flag force" "0,1"
|
|
bitfld.word 0x1 13. "ECATNMIn,ECATNMIn flag force" "0,1"
|
|
bitfld.word 0x1 12. "CMNMIWDRSn,DCDCOLF Flag Force" "0,1"
|
|
bitfld.word 0x1 10. "CPU2NMIWDRSn,CPU2NMIWDRSn Flag Force" "0,1"
|
|
bitfld.word 0x1 9. "CPU2WDRSn,CPU2WDRSn Flag Force" "0,1"
|
|
bitfld.word 0x1 8. "CLBNMI,CLBNMI Flag Force" "0,1"
|
|
bitfld.word 0x1 7. "ERADNMI,ERADNMI Flag Force" "0,1"
|
|
bitfld.word 0x1 6. "PIEVECTERR,PIEVECTERR Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x1 5. "CPU2HWBISTERR,CPU2HWBISTERR Flag Force" "0,1"
|
|
bitfld.word 0x1 4. "CPU1HWBISTERR,CPU1HWBISTERR Flag Force" "0,1"
|
|
bitfld.word 0x1 3. "FLUNCERR,FLUNCERR Flag Force" "0,1"
|
|
bitfld.word 0x1 2. "RAMUNCERR,RAMUNCERR Flag Force" "0,1"
|
|
bitfld.word 0x1 1. "CLOCKFAIL,CLOCKFAIL Flag Force" "0,1"
|
|
rgroup.word 0x4++0x1
|
|
line.word 0x0 "NMIWDCNT,NMI Watchdog Counter Register"
|
|
hexmask.word 0x0 0.--15. 1. "NMIWDCNT,NMI Watchdog Counter"
|
|
group.word 0x5++0x1
|
|
line.word 0x0 "NMIWDPRD,NMI Watchdog Period Register"
|
|
hexmask.word 0x0 0.--15. 1. "NMIWDPRD,NMI Watchdog Period"
|
|
rgroup.word 0x6++0x3
|
|
line.word 0x0 "NMISHDFLG,NMI Shadow Flag Register"
|
|
bitfld.word 0x0 14. "CRC_FAIL,CRC_FAIL flag" "0,1"
|
|
bitfld.word 0x0 13. "ECATNMIn,ECATNMIn flag" "0,1"
|
|
bitfld.word 0x0 12. "CMNMIWDRSn,Shadow DCDCOLF Flag" "0,1"
|
|
bitfld.word 0x0 10. "CPU2NMIWDRSn,Shadow CPU2NMIWDRSn Flag" "0,1"
|
|
bitfld.word 0x0 9. "CPU2WDRSn,Shadow CPU2WDRSn Flag" "0,1"
|
|
bitfld.word 0x0 8. "CLBNMI,Shadow CLBNMI Flag" "0,1"
|
|
bitfld.word 0x0 7. "ERADNMI,Shadow ERADNMI Flag" "0,1"
|
|
bitfld.word 0x0 6. "PIEVECTERR,Shadow PIEVECTERR Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "CPU2HWBISTERR,Shadow CPU2HWBISTERR Flag" "0,1"
|
|
bitfld.word 0x0 4. "CPU1HWBISTERR,Shadow CPU1HWBISTERR Flag" "0,1"
|
|
bitfld.word 0x0 3. "FLUNCERR,Shadow FLUNCERR Flag" "0,1"
|
|
bitfld.word 0x0 2. "RAMUNCERR,Shadow RAMUNCERR Flag" "0,1"
|
|
bitfld.word 0x0 1. "CLOCKFAIL,Shadow CLOCKFAIL Flag" "0,1"
|
|
line.word 0x1 "ERRORSTS,Error pin status"
|
|
bitfld.word 0x1 1. "PINSTS,Error pin status." "0,1"
|
|
bitfld.word 0x1 0. "ERROR,Error flag." "0,1"
|
|
group.word 0x8++0x7
|
|
line.word 0x0 "ERRORSTSCLR,ERRORSTS clear register"
|
|
bitfld.word 0x0 0. "ERROR,ERRORFLG.ERROR clear bit" "0,1"
|
|
line.word 0x1 "ERRORSTSFRC,ERRORSTS force register"
|
|
bitfld.word 0x1 0. "ERROR,ERRORSTS.ERROR pin force." "0,1"
|
|
line.word 0x2 "ERRORCTL,Error pin control register"
|
|
bitfld.word 0x2 0. "ERRORPOLSEL,ERROR pin polarity select" "0,1"
|
|
line.word 0x3 "ERRORLOCK,Lock register to Error pin registers."
|
|
bitfld.word 0x3 0. "ERRORCTL,ERRORCTL Lock bit" "0,1"
|
|
tree.end
|
|
tree "PIECTRL"
|
|
base d:0xCE0
|
|
group.word 0x0++0x33
|
|
line.word 0x0 "PIECTRL,ePIE Control Register"
|
|
hexmask.word 0x0 1.--15. 1. "PIEVECT,PIE Vector Address"
|
|
bitfld.word 0x0 0. "ENPIE,PIE Enable" "0,1"
|
|
line.word 0x1 "PIEACK,Interrupt Acknowledge Register"
|
|
bitfld.word 0x1 11. "ACK12,Acknowledge PIE Interrupt Group 12" "0,1"
|
|
bitfld.word 0x1 10. "ACK11,Acknowledge PIE Interrupt Group 11" "0,1"
|
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bitfld.word 0x1 9. "ACK10,Acknowledge PIE Interrupt Group 10" "0,1"
|
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bitfld.word 0x1 8. "ACK9,Acknowledge PIE Interrupt Group 9" "0,1"
|
|
bitfld.word 0x1 7. "ACK8,Acknowledge PIE Interrupt Group 8" "0,1"
|
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bitfld.word 0x1 6. "ACK7,Acknowledge PIE Interrupt Group 7" "0,1"
|
|
bitfld.word 0x1 5. "ACK6,Acknowledge PIE Interrupt Group 6" "0,1"
|
|
bitfld.word 0x1 4. "ACK5,Acknowledge PIE Interrupt Group 5" "0,1"
|
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bitfld.word 0x1 3. "ACK4,Acknowledge PIE Interrupt Group 4" "0,1"
|
|
bitfld.word 0x1 2. "ACK3,Acknowledge PIE Interrupt Group 3" "0,1"
|
|
bitfld.word 0x1 1. "ACK2,Acknowledge PIE Interrupt Group 2" "0,1"
|
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bitfld.word 0x1 0. "ACK1,Acknowledge PIE Interrupt Group 1" "0,1"
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line.word 0x2 "PIEIER1,Interrupt Group 1 Enable Register"
|
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bitfld.word 0x2 15. "INTx16,Enable for Interrupt 1.16" "0,1"
|
|
bitfld.word 0x2 14. "INTx15,Enable for Interrupt 1.15" "0,1"
|
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bitfld.word 0x2 13. "INTx14,Enable for Interrupt 1.14" "0,1"
|
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bitfld.word 0x2 12. "INTx13,Enable for Interrupt 1.13" "0,1"
|
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bitfld.word 0x2 11. "INTx12,Enable for Interrupt 1.12" "0,1"
|
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bitfld.word 0x2 10. "INTx11,Enable for Interrupt 1.11" "0,1"
|
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bitfld.word 0x2 9. "INTx10,Enable for Interrupt 1.10" "0,1"
|
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bitfld.word 0x2 8. "INTx9,Enable for Interrupt 1.9" "0,1"
|
|
bitfld.word 0x2 7. "INTx8,Enable for Interrupt 1.8" "0,1"
|
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bitfld.word 0x2 6. "INTx7,Enable for Interrupt 1.7" "0,1"
|
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bitfld.word 0x2 5. "INTx6,Enable for Interrupt 1.6" "0,1"
|
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bitfld.word 0x2 4. "INTx5,Enable for Interrupt 1.5" "0,1"
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bitfld.word 0x2 3. "INTx4,Enable for Interrupt 1.4" "0,1"
|
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bitfld.word 0x2 2. "INTx3,Enable for Interrupt 1.3" "0,1"
|
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bitfld.word 0x2 1. "INTx2,Enable for Interrupt 1.2" "0,1"
|
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bitfld.word 0x2 0. "INTx1,Enable for Interrupt 1.1" "0,1"
|
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line.word 0x3 "PIEIFR1,Interrupt Group 1 Flag Register"
|
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bitfld.word 0x3 15. "INTx16,Flag for Interrupt 1.16" "0,1"
|
|
bitfld.word 0x3 14. "INTx15,Flag for Interrupt 1.15" "0,1"
|
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bitfld.word 0x3 13. "INTx14,Flag for Interrupt 1.14" "0,1"
|
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bitfld.word 0x3 12. "INTx13,Flag for Interrupt 1.13" "0,1"
|
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bitfld.word 0x3 11. "INTx12,Flag for Interrupt 1.12" "0,1"
|
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bitfld.word 0x3 10. "INTx11,Flag for Interrupt 1.11" "0,1"
|
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bitfld.word 0x3 9. "INTx10,Flag for Interrupt 1.10" "0,1"
|
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bitfld.word 0x3 8. "INTx9,Flag for Interrupt 1.9" "0,1"
|
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bitfld.word 0x3 7. "INTx8,Flag for Interrupt 1.8" "0,1"
|
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bitfld.word 0x3 6. "INTx7,Flag for Interrupt 1.7" "0,1"
|
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bitfld.word 0x3 5. "INTx6,Flag for Interrupt 1.6" "0,1"
|
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bitfld.word 0x3 4. "INTx5,Flag for Interrupt 1.5" "0,1"
|
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newline
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bitfld.word 0x3 3. "INTx4,Flag for Interrupt 1.4" "0,1"
|
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bitfld.word 0x3 2. "INTx3,Flag for Interrupt 1.3" "0,1"
|
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bitfld.word 0x3 1. "INTx2,Flag for Interrupt 1.2" "0,1"
|
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bitfld.word 0x3 0. "INTx1,Flag for Interrupt 1.1" "0,1"
|
|
line.word 0x4 "PIEIER2,Interrupt Group 2 Enable Register"
|
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bitfld.word 0x4 15. "INTx16,Enable for Interrupt 2.16" "0,1"
|
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bitfld.word 0x4 14. "INTx15,Enable for Interrupt 2.15" "0,1"
|
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bitfld.word 0x4 13. "INTx14,Enable for Interrupt 2.14" "0,1"
|
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bitfld.word 0x4 12. "INTx13,Enable for Interrupt 2.13" "0,1"
|
|
bitfld.word 0x4 11. "INTx12,Enable for Interrupt 2.12" "0,1"
|
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bitfld.word 0x4 10. "INTx11,Enable for Interrupt 2.11" "0,1"
|
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bitfld.word 0x4 9. "INTx10,Enable for Interrupt 2.10" "0,1"
|
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bitfld.word 0x4 8. "INTx9,Enable for Interrupt 2.9" "0,1"
|
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bitfld.word 0x4 7. "INTx8,Enable for Interrupt 2.8" "0,1"
|
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bitfld.word 0x4 6. "INTx7,Enable for Interrupt 2.7" "0,1"
|
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bitfld.word 0x4 5. "INTx6,Enable for Interrupt 2.6" "0,1"
|
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bitfld.word 0x4 4. "INTx5,Enable for Interrupt 2.5" "0,1"
|
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bitfld.word 0x4 3. "INTx4,Enable for Interrupt 2.4" "0,1"
|
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bitfld.word 0x4 2. "INTx3,Enable for Interrupt 2.3" "0,1"
|
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bitfld.word 0x4 1. "INTx2,Enable for Interrupt 2.2" "0,1"
|
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bitfld.word 0x4 0. "INTx1,Enable for Interrupt 2.1" "0,1"
|
|
line.word 0x5 "PIEIFR2,Interrupt Group 2 Flag Register"
|
|
bitfld.word 0x5 15. "INTx16,Flag for Interrupt 2.16" "0,1"
|
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bitfld.word 0x5 14. "INTx15,Flag for Interrupt 2.15" "0,1"
|
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bitfld.word 0x5 13. "INTx14,Flag for Interrupt 2.14" "0,1"
|
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bitfld.word 0x5 12. "INTx13,Flag for Interrupt 2.13" "0,1"
|
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bitfld.word 0x5 11. "INTx12,Flag for Interrupt 2.12" "0,1"
|
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bitfld.word 0x5 10. "INTx11,Flag for Interrupt 2.11" "0,1"
|
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bitfld.word 0x5 9. "INTx10,Flag for Interrupt 2.10" "0,1"
|
|
bitfld.word 0x5 8. "INTx9,Flag for Interrupt 2.9" "0,1"
|
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bitfld.word 0x5 7. "INTx8,Flag for Interrupt 2.8" "0,1"
|
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bitfld.word 0x5 6. "INTx7,Flag for Interrupt 2.7" "0,1"
|
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bitfld.word 0x5 5. "INTx6,Flag for Interrupt 2.6" "0,1"
|
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bitfld.word 0x5 4. "INTx5,Flag for Interrupt 2.5" "0,1"
|
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bitfld.word 0x5 3. "INTx4,Flag for Interrupt 2.4" "0,1"
|
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bitfld.word 0x5 2. "INTx3,Flag for Interrupt 2.3" "0,1"
|
|
bitfld.word 0x5 1. "INTx2,Flag for Interrupt 2.2" "0,1"
|
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bitfld.word 0x5 0. "INTx1,Flag for Interrupt 2.1" "0,1"
|
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line.word 0x6 "PIEIER3,Interrupt Group 3 Enable Register"
|
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bitfld.word 0x6 15. "INTx16,Enable for Interrupt 3.16" "0,1"
|
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bitfld.word 0x6 14. "INTx15,Enable for Interrupt 3.15" "0,1"
|
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bitfld.word 0x6 13. "INTx14,Enable for Interrupt 3.14" "0,1"
|
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bitfld.word 0x6 12. "INTx13,Enable for Interrupt 3.13" "0,1"
|
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bitfld.word 0x6 11. "INTx12,Enable for Interrupt 3.12" "0,1"
|
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bitfld.word 0x6 10. "INTx11,Enable for Interrupt 3.11" "0,1"
|
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bitfld.word 0x6 9. "INTx10,Enable for Interrupt 3.10" "0,1"
|
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bitfld.word 0x6 8. "INTx9,Enable for Interrupt 3.9" "0,1"
|
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bitfld.word 0x6 7. "INTx8,Enable for Interrupt 3.8" "0,1"
|
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bitfld.word 0x6 6. "INTx7,Enable for Interrupt 3.7" "0,1"
|
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bitfld.word 0x6 5. "INTx6,Enable for Interrupt 3.6" "0,1"
|
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bitfld.word 0x6 4. "INTx5,Enable for Interrupt 3.5" "0,1"
|
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newline
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bitfld.word 0x6 3. "INTx4,Enable for Interrupt 3.4" "0,1"
|
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bitfld.word 0x6 2. "INTx3,Enable for Interrupt 3.3" "0,1"
|
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bitfld.word 0x6 1. "INTx2,Enable for Interrupt 3.2" "0,1"
|
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bitfld.word 0x6 0. "INTx1,Enable for Interrupt 3.1" "0,1"
|
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line.word 0x7 "PIEIFR3,Interrupt Group 3 Flag Register"
|
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bitfld.word 0x7 15. "INTx16,Flag for Interrupt 3.16" "0,1"
|
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bitfld.word 0x7 14. "INTx15,Flag for Interrupt 3.15" "0,1"
|
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bitfld.word 0x7 13. "INTx14,Flag for Interrupt 3.14" "0,1"
|
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bitfld.word 0x7 12. "INTx13,Flag for Interrupt 3.13" "0,1"
|
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bitfld.word 0x7 11. "INTx12,Flag for Interrupt 3.12" "0,1"
|
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bitfld.word 0x7 10. "INTx11,Flag for Interrupt 3.11" "0,1"
|
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bitfld.word 0x7 9. "INTx10,Flag for Interrupt 3.10" "0,1"
|
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bitfld.word 0x7 8. "INTx9,Flag for Interrupt 3.9" "0,1"
|
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bitfld.word 0x7 7. "INTx8,Flag for Interrupt 3.8" "0,1"
|
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bitfld.word 0x7 6. "INTx7,Flag for Interrupt 3.7" "0,1"
|
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bitfld.word 0x7 5. "INTx6,Flag for Interrupt 3.6" "0,1"
|
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bitfld.word 0x7 4. "INTx5,Flag for Interrupt 3.5" "0,1"
|
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newline
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bitfld.word 0x7 3. "INTx4,Flag for Interrupt 3.4" "0,1"
|
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bitfld.word 0x7 2. "INTx3,Flag for Interrupt 3.3" "0,1"
|
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bitfld.word 0x7 1. "INTx2,Flag for Interrupt 3.2" "0,1"
|
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bitfld.word 0x7 0. "INTx1,Flag for Interrupt 3.1" "0,1"
|
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line.word 0x8 "PIEIER4,Interrupt Group 4 Enable Register"
|
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bitfld.word 0x8 15. "INTx16,Enable for Interrupt 4.16" "0,1"
|
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bitfld.word 0x8 14. "INTx15,Enable for Interrupt 4.15" "0,1"
|
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bitfld.word 0x8 13. "INTx14,Enable for Interrupt 4.14" "0,1"
|
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bitfld.word 0x8 12. "INTx13,Enable for Interrupt 4.13" "0,1"
|
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bitfld.word 0x8 11. "INTx12,Enable for Interrupt 4.12" "0,1"
|
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bitfld.word 0x8 10. "INTx11,Enable for Interrupt 4.11" "0,1"
|
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bitfld.word 0x8 9. "INTx10,Enable for Interrupt 4.10" "0,1"
|
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bitfld.word 0x8 8. "INTx9,Enable for Interrupt 4.9" "0,1"
|
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bitfld.word 0x8 7. "INTx8,Enable for Interrupt 4.8" "0,1"
|
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bitfld.word 0x8 6. "INTx7,Enable for Interrupt 4.7" "0,1"
|
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bitfld.word 0x8 5. "INTx6,Enable for Interrupt 4.6" "0,1"
|
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bitfld.word 0x8 4. "INTx5,Enable for Interrupt 4.5" "0,1"
|
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newline
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bitfld.word 0x8 3. "INTx4,Enable for Interrupt 4.4" "0,1"
|
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bitfld.word 0x8 2. "INTx3,Enable for Interrupt 4.3" "0,1"
|
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bitfld.word 0x8 1. "INTx2,Enable for Interrupt 4.2" "0,1"
|
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bitfld.word 0x8 0. "INTx1,Enable for Interrupt 4.1" "0,1"
|
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line.word 0x9 "PIEIFR4,Interrupt Group 4 Flag Register"
|
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bitfld.word 0x9 15. "INTx16,Flag for Interrupt 4.16" "0,1"
|
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bitfld.word 0x9 14. "INTx15,Flag for Interrupt 4.15" "0,1"
|
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bitfld.word 0x9 13. "INTx14,Flag for Interrupt 4.14" "0,1"
|
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bitfld.word 0x9 12. "INTx13,Flag for Interrupt 4.13" "0,1"
|
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bitfld.word 0x9 11. "INTx12,Flag for Interrupt 4.12" "0,1"
|
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bitfld.word 0x9 10. "INTx11,Flag for Interrupt 4.11" "0,1"
|
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bitfld.word 0x9 9. "INTx10,Flag for Interrupt 4.10" "0,1"
|
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bitfld.word 0x9 8. "INTx9,Flag for Interrupt 4.9" "0,1"
|
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bitfld.word 0x9 7. "INTx8,Flag for Interrupt 4.8" "0,1"
|
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bitfld.word 0x9 6. "INTx7,Flag for Interrupt 4.7" "0,1"
|
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bitfld.word 0x9 5. "INTx6,Flag for Interrupt 4.6" "0,1"
|
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bitfld.word 0x9 4. "INTx5,Flag for Interrupt 4.5" "0,1"
|
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newline
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bitfld.word 0x9 3. "INTx4,Flag for Interrupt 4.4" "0,1"
|
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bitfld.word 0x9 2. "INTx3,Flag for Interrupt 4.3" "0,1"
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bitfld.word 0x9 1. "INTx2,Flag for Interrupt 4.2" "0,1"
|
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bitfld.word 0x9 0. "INTx1,Flag for Interrupt 4.1" "0,1"
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line.word 0xA "PIEIER5,Interrupt Group 5 Enable Register"
|
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bitfld.word 0xA 15. "INTx16,Enable for Interrupt 5.16" "0,1"
|
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bitfld.word 0xA 14. "INTx15,Enable for Interrupt 5.15" "0,1"
|
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bitfld.word 0xA 13. "INTx14,Enable for Interrupt 5.14" "0,1"
|
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bitfld.word 0xA 12. "INTx13,Enable for Interrupt 5.13" "0,1"
|
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bitfld.word 0xA 11. "INTx12,Enable for Interrupt 5.12" "0,1"
|
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bitfld.word 0xA 10. "INTx11,Enable for Interrupt 5.11" "0,1"
|
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bitfld.word 0xA 9. "INTx10,Enable for Interrupt 5.10" "0,1"
|
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bitfld.word 0xA 8. "INTx9,Enable for Interrupt 5.9" "0,1"
|
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bitfld.word 0xA 7. "INTx8,Enable for Interrupt 5.8" "0,1"
|
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bitfld.word 0xA 6. "INTx7,Enable for Interrupt 5.7" "0,1"
|
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bitfld.word 0xA 5. "INTx6,Enable for Interrupt 5.6" "0,1"
|
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bitfld.word 0xA 4. "INTx5,Enable for Interrupt 5.5" "0,1"
|
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newline
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bitfld.word 0xA 3. "INTx4,Enable for Interrupt 5.4" "0,1"
|
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bitfld.word 0xA 2. "INTx3,Enable for Interrupt 5.3" "0,1"
|
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bitfld.word 0xA 1. "INTx2,Enable for Interrupt 5.2" "0,1"
|
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bitfld.word 0xA 0. "INTx1,Enable for Interrupt 5.1" "0,1"
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line.word 0xB "PIEIFR5,Interrupt Group 5 Flag Register"
|
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bitfld.word 0xB 15. "INTx16,Flag for Interrupt 5.16" "0,1"
|
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bitfld.word 0xB 14. "INTx15,Flag for Interrupt 5.15" "0,1"
|
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bitfld.word 0xB 13. "INTx14,Flag for Interrupt 5.14" "0,1"
|
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bitfld.word 0xB 12. "INTx13,Flag for Interrupt 5.13" "0,1"
|
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bitfld.word 0xB 11. "INTx12,Flag for Interrupt 5.12" "0,1"
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bitfld.word 0xB 10. "INTx11,Flag for Interrupt 5.11" "0,1"
|
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bitfld.word 0xB 9. "INTx10,Flag for Interrupt 5.10" "0,1"
|
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bitfld.word 0xB 8. "INTx9,Flag for Interrupt 5.9" "0,1"
|
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bitfld.word 0xB 7. "INTx8,Flag for Interrupt 5.8" "0,1"
|
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bitfld.word 0xB 6. "INTx7,Flag for Interrupt 5.7" "0,1"
|
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bitfld.word 0xB 5. "INTx6,Flag for Interrupt 5.6" "0,1"
|
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bitfld.word 0xB 4. "INTx5,Flag for Interrupt 5.5" "0,1"
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newline
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bitfld.word 0xB 3. "INTx4,Flag for Interrupt 5.4" "0,1"
|
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bitfld.word 0xB 2. "INTx3,Flag for Interrupt 5.3" "0,1"
|
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bitfld.word 0xB 1. "INTx2,Flag for Interrupt 5.2" "0,1"
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bitfld.word 0xB 0. "INTx1,Flag for Interrupt 5.1" "0,1"
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line.word 0xC "PIEIER6,Interrupt Group 6 Enable Register"
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bitfld.word 0xC 15. "INTx16,Enable for Interrupt 6.16" "0,1"
|
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bitfld.word 0xC 14. "INTx15,Enable for Interrupt 6.15" "0,1"
|
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bitfld.word 0xC 13. "INTx14,Enable for Interrupt 6.14" "0,1"
|
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bitfld.word 0xC 12. "INTx13,Enable for Interrupt 6.13" "0,1"
|
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bitfld.word 0xC 11. "INTx12,Enable for Interrupt 6.12" "0,1"
|
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bitfld.word 0xC 10. "INTx11,Enable for Interrupt 6.11" "0,1"
|
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bitfld.word 0xC 9. "INTx10,Enable for Interrupt 6.10" "0,1"
|
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bitfld.word 0xC 8. "INTx9,Enable for Interrupt 6.9" "0,1"
|
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bitfld.word 0xC 7. "INTx8,Enable for Interrupt 6.8" "0,1"
|
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bitfld.word 0xC 6. "INTx7,Enable for Interrupt 6.7" "0,1"
|
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bitfld.word 0xC 5. "INTx6,Enable for Interrupt 6.6" "0,1"
|
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bitfld.word 0xC 4. "INTx5,Enable for Interrupt 6.5" "0,1"
|
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newline
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bitfld.word 0xC 3. "INTx4,Enable for Interrupt 6.4" "0,1"
|
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bitfld.word 0xC 2. "INTx3,Enable for Interrupt 6.3" "0,1"
|
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bitfld.word 0xC 1. "INTx2,Enable for Interrupt 6.2" "0,1"
|
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bitfld.word 0xC 0. "INTx1,Enable for Interrupt 6.1" "0,1"
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line.word 0xD "PIEIFR6,Interrupt Group 6 Flag Register"
|
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bitfld.word 0xD 15. "INTx16,Flag for Interrupt 6.16" "0,1"
|
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bitfld.word 0xD 14. "INTx15,Flag for Interrupt 6.15" "0,1"
|
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bitfld.word 0xD 13. "INTx14,Flag for Interrupt 6.14" "0,1"
|
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bitfld.word 0xD 12. "INTx13,Flag for Interrupt 6.13" "0,1"
|
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bitfld.word 0xD 11. "INTx12,Flag for Interrupt 6.12" "0,1"
|
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bitfld.word 0xD 10. "INTx11,Flag for Interrupt 6.11" "0,1"
|
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bitfld.word 0xD 9. "INTx10,Flag for Interrupt 6.10" "0,1"
|
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bitfld.word 0xD 8. "INTx9,Flag for Interrupt 6.9" "0,1"
|
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bitfld.word 0xD 7. "INTx8,Flag for Interrupt 6.8" "0,1"
|
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bitfld.word 0xD 6. "INTx7,Flag for Interrupt 6.7" "0,1"
|
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bitfld.word 0xD 5. "INTx6,Flag for Interrupt 6.6" "0,1"
|
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bitfld.word 0xD 4. "INTx5,Flag for Interrupt 6.5" "0,1"
|
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newline
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bitfld.word 0xD 3. "INTx4,Flag for Interrupt 6.4" "0,1"
|
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bitfld.word 0xD 2. "INTx3,Flag for Interrupt 6.3" "0,1"
|
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bitfld.word 0xD 1. "INTx2,Flag for Interrupt 6.2" "0,1"
|
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bitfld.word 0xD 0. "INTx1,Flag for Interrupt 6.1" "0,1"
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line.word 0xE "PIEIER7,Interrupt Group 7 Enable Register"
|
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bitfld.word 0xE 15. "INTx16,Enable for Interrupt 7.16" "0,1"
|
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bitfld.word 0xE 14. "INTx15,Enable for Interrupt 7.15" "0,1"
|
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bitfld.word 0xE 13. "INTx14,Enable for Interrupt 7.14" "0,1"
|
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bitfld.word 0xE 12. "INTx13,Enable for Interrupt 7.13" "0,1"
|
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bitfld.word 0xE 11. "INTx12,Enable for Interrupt 7.12" "0,1"
|
|
bitfld.word 0xE 10. "INTx11,Enable for Interrupt 7.11" "0,1"
|
|
bitfld.word 0xE 9. "INTx10,Enable for Interrupt 7.10" "0,1"
|
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bitfld.word 0xE 8. "INTx9,Enable for Interrupt 7.9" "0,1"
|
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bitfld.word 0xE 7. "INTx8,Enable for Interrupt 7.8" "0,1"
|
|
bitfld.word 0xE 6. "INTx7,Enable for Interrupt 7.7" "0,1"
|
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bitfld.word 0xE 5. "INTx6,Enable for Interrupt 7.6" "0,1"
|
|
bitfld.word 0xE 4. "INTx5,Enable for Interrupt 7.5" "0,1"
|
|
newline
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bitfld.word 0xE 3. "INTx4,Enable for Interrupt 7.4" "0,1"
|
|
bitfld.word 0xE 2. "INTx3,Enable for Interrupt 7.3" "0,1"
|
|
bitfld.word 0xE 1. "INTx2,Enable for Interrupt 7.2" "0,1"
|
|
bitfld.word 0xE 0. "INTx1,Enable for Interrupt 7.1" "0,1"
|
|
line.word 0xF "PIEIFR7,Interrupt Group 7 Flag Register"
|
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bitfld.word 0xF 15. "INTx16,Flag for Interrupt 7.16" "0,1"
|
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bitfld.word 0xF 14. "INTx15,Flag for Interrupt 7.15" "0,1"
|
|
bitfld.word 0xF 13. "INTx14,Flag for Interrupt 7.14" "0,1"
|
|
bitfld.word 0xF 12. "INTx13,Flag for Interrupt 7.13" "0,1"
|
|
bitfld.word 0xF 11. "INTx12,Flag for Interrupt 7.12" "0,1"
|
|
bitfld.word 0xF 10. "INTx11,Flag for Interrupt 7.11" "0,1"
|
|
bitfld.word 0xF 9. "INTx10,Flag for Interrupt 7.10" "0,1"
|
|
bitfld.word 0xF 8. "INTx9,Flag for Interrupt 7.9" "0,1"
|
|
bitfld.word 0xF 7. "INTx8,Flag for Interrupt 7.8" "0,1"
|
|
bitfld.word 0xF 6. "INTx7,Flag for Interrupt 7.7" "0,1"
|
|
bitfld.word 0xF 5. "INTx6,Flag for Interrupt 7.6" "0,1"
|
|
bitfld.word 0xF 4. "INTx5,Flag for Interrupt 7.5" "0,1"
|
|
newline
|
|
bitfld.word 0xF 3. "INTx4,Flag for Interrupt 7.4" "0,1"
|
|
bitfld.word 0xF 2. "INTx3,Flag for Interrupt 7.3" "0,1"
|
|
bitfld.word 0xF 1. "INTx2,Flag for Interrupt 7.2" "0,1"
|
|
bitfld.word 0xF 0. "INTx1,Flag for Interrupt 7.1" "0,1"
|
|
line.word 0x10 "PIEIER8,Interrupt Group 8 Enable Register"
|
|
bitfld.word 0x10 15. "INTx16,Enable for Interrupt 8.16" "0,1"
|
|
bitfld.word 0x10 14. "INTx15,Enable for Interrupt 8.15" "0,1"
|
|
bitfld.word 0x10 13. "INTx14,Enable for Interrupt 8.14" "0,1"
|
|
bitfld.word 0x10 12. "INTx13,Enable for Interrupt 8.13" "0,1"
|
|
bitfld.word 0x10 11. "INTx12,Enable for Interrupt 8.12" "0,1"
|
|
bitfld.word 0x10 10. "INTx11,Enable for Interrupt 8.11" "0,1"
|
|
bitfld.word 0x10 9. "INTx10,Enable for Interrupt 8.10" "0,1"
|
|
bitfld.word 0x10 8. "INTx9,Enable for Interrupt 8.9" "0,1"
|
|
bitfld.word 0x10 7. "INTx8,Enable for Interrupt 8.8" "0,1"
|
|
bitfld.word 0x10 6. "INTx7,Enable for Interrupt 8.7" "0,1"
|
|
bitfld.word 0x10 5. "INTx6,Enable for Interrupt 8.6" "0,1"
|
|
bitfld.word 0x10 4. "INTx5,Enable for Interrupt 8.5" "0,1"
|
|
newline
|
|
bitfld.word 0x10 3. "INTx4,Enable for Interrupt 8.4" "0,1"
|
|
bitfld.word 0x10 2. "INTx3,Enable for Interrupt 8.3" "0,1"
|
|
bitfld.word 0x10 1. "INTx2,Enable for Interrupt 8.2" "0,1"
|
|
bitfld.word 0x10 0. "INTx1,Enable for Interrupt 8.1" "0,1"
|
|
line.word 0x11 "PIEIFR8,Interrupt Group 8 Flag Register"
|
|
bitfld.word 0x11 15. "INTx16,Flag for Interrupt 8.16" "0,1"
|
|
bitfld.word 0x11 14. "INTx15,Flag for Interrupt 8.15" "0,1"
|
|
bitfld.word 0x11 13. "INTx14,Flag for Interrupt 8.14" "0,1"
|
|
bitfld.word 0x11 12. "INTx13,Flag for Interrupt 8.13" "0,1"
|
|
bitfld.word 0x11 11. "INTx12,Flag for Interrupt 8.12" "0,1"
|
|
bitfld.word 0x11 10. "INTx11,Flag for Interrupt 8.11" "0,1"
|
|
bitfld.word 0x11 9. "INTx10,Flag for Interrupt 8.10" "0,1"
|
|
bitfld.word 0x11 8. "INTx9,Flag for Interrupt 8.9" "0,1"
|
|
bitfld.word 0x11 7. "INTx8,Flag for Interrupt 8.8" "0,1"
|
|
bitfld.word 0x11 6. "INTx7,Flag for Interrupt 8.7" "0,1"
|
|
bitfld.word 0x11 5. "INTx6,Flag for Interrupt 8.6" "0,1"
|
|
bitfld.word 0x11 4. "INTx5,Flag for Interrupt 8.5" "0,1"
|
|
newline
|
|
bitfld.word 0x11 3. "INTx4,Flag for Interrupt 8.4" "0,1"
|
|
bitfld.word 0x11 2. "INTx3,Flag for Interrupt 8.3" "0,1"
|
|
bitfld.word 0x11 1. "INTx2,Flag for Interrupt 8.2" "0,1"
|
|
bitfld.word 0x11 0. "INTx1,Flag for Interrupt 8.1" "0,1"
|
|
line.word 0x12 "PIEIER9,Interrupt Group 9 Enable Register"
|
|
bitfld.word 0x12 15. "INTx16,Enable for Interrupt 9.16" "0,1"
|
|
bitfld.word 0x12 14. "INTx15,Enable for Interrupt 9.15" "0,1"
|
|
bitfld.word 0x12 13. "INTx14,Enable for Interrupt 9.14" "0,1"
|
|
bitfld.word 0x12 12. "INTx13,Enable for Interrupt 9.13" "0,1"
|
|
bitfld.word 0x12 11. "INTx12,Enable for Interrupt 9.12" "0,1"
|
|
bitfld.word 0x12 10. "INTx11,Enable for Interrupt 9.11" "0,1"
|
|
bitfld.word 0x12 9. "INTx10,Enable for Interrupt 9.10" "0,1"
|
|
bitfld.word 0x12 8. "INTx9,Enable for Interrupt 9.9" "0,1"
|
|
bitfld.word 0x12 7. "INTx8,Enable for Interrupt 9.8" "0,1"
|
|
bitfld.word 0x12 6. "INTx7,Enable for Interrupt 9.7" "0,1"
|
|
bitfld.word 0x12 5. "INTx6,Enable for Interrupt 9.6" "0,1"
|
|
bitfld.word 0x12 4. "INTx5,Enable for Interrupt 9.5" "0,1"
|
|
newline
|
|
bitfld.word 0x12 3. "INTx4,Enable for Interrupt 9.4" "0,1"
|
|
bitfld.word 0x12 2. "INTx3,Enable for Interrupt 9.3" "0,1"
|
|
bitfld.word 0x12 1. "INTx2,Enable for Interrupt 9.2" "0,1"
|
|
bitfld.word 0x12 0. "INTx1,Enable for Interrupt 9.1" "0,1"
|
|
line.word 0x13 "PIEIFR9,Interrupt Group 9 Flag Register"
|
|
bitfld.word 0x13 15. "INTx16,Flag for Interrupt 9.16" "0,1"
|
|
bitfld.word 0x13 14. "INTx15,Flag for Interrupt 9.15" "0,1"
|
|
bitfld.word 0x13 13. "INTx14,Flag for Interrupt 9.14" "0,1"
|
|
bitfld.word 0x13 12. "INTx13,Flag for Interrupt 9.13" "0,1"
|
|
bitfld.word 0x13 11. "INTx12,Flag for Interrupt 9.12" "0,1"
|
|
bitfld.word 0x13 10. "INTx11,Flag for Interrupt 9.11" "0,1"
|
|
bitfld.word 0x13 9. "INTx10,Flag for Interrupt 9.10" "0,1"
|
|
bitfld.word 0x13 8. "INTx9,Flag for Interrupt 9.9" "0,1"
|
|
bitfld.word 0x13 7. "INTx8,Flag for Interrupt 9.8" "0,1"
|
|
bitfld.word 0x13 6. "INTx7,Flag for Interrupt 9.7" "0,1"
|
|
bitfld.word 0x13 5. "INTx6,Flag for Interrupt 9.6" "0,1"
|
|
bitfld.word 0x13 4. "INTx5,Flag for Interrupt 9.5" "0,1"
|
|
newline
|
|
bitfld.word 0x13 3. "INTx4,Flag for Interrupt 9.4" "0,1"
|
|
bitfld.word 0x13 2. "INTx3,Flag for Interrupt 9.3" "0,1"
|
|
bitfld.word 0x13 1. "INTx2,Flag for Interrupt 9.2" "0,1"
|
|
bitfld.word 0x13 0. "INTx1,Flag for Interrupt 9.1" "0,1"
|
|
line.word 0x14 "PIEIER10,Interrupt Group 10 Enable Register"
|
|
bitfld.word 0x14 15. "INTx16,Enable for Interrupt 10.16" "0,1"
|
|
bitfld.word 0x14 14. "INTx15,Enable for Interrupt 10.15" "0,1"
|
|
bitfld.word 0x14 13. "INTx14,Enable for Interrupt 10.14" "0,1"
|
|
bitfld.word 0x14 12. "INTx13,Enable for Interrupt 10.13" "0,1"
|
|
bitfld.word 0x14 11. "INTx12,Enable for Interrupt 10.12" "0,1"
|
|
bitfld.word 0x14 10. "INTx11,Enable for Interrupt 10.11" "0,1"
|
|
bitfld.word 0x14 9. "INTx10,Enable for Interrupt 10.10" "0,1"
|
|
bitfld.word 0x14 8. "INTx9,Enable for Interrupt 10.9" "0,1"
|
|
bitfld.word 0x14 7. "INTx8,Enable for Interrupt 10.8" "0,1"
|
|
bitfld.word 0x14 6. "INTx7,Enable for Interrupt 10.7" "0,1"
|
|
bitfld.word 0x14 5. "INTx6,Enable for Interrupt 10.6" "0,1"
|
|
bitfld.word 0x14 4. "INTx5,Enable for Interrupt 10.5" "0,1"
|
|
newline
|
|
bitfld.word 0x14 3. "INTx4,Enable for Interrupt 10.4" "0,1"
|
|
bitfld.word 0x14 2. "INTx3,Enable for Interrupt 10.3" "0,1"
|
|
bitfld.word 0x14 1. "INTx2,Enable for Interrupt 10.2" "0,1"
|
|
bitfld.word 0x14 0. "INTx1,Enable for Interrupt 10.1" "0,1"
|
|
line.word 0x15 "PIEIFR10,Interrupt Group 10 Flag Register"
|
|
bitfld.word 0x15 15. "INTx16,Flag for Interrupt 10.16" "0,1"
|
|
bitfld.word 0x15 14. "INTx15,Flag for Interrupt 10.15" "0,1"
|
|
bitfld.word 0x15 13. "INTx14,Flag for Interrupt 10.14" "0,1"
|
|
bitfld.word 0x15 12. "INTx13,Flag for Interrupt 10.13" "0,1"
|
|
bitfld.word 0x15 11. "INTx12,Flag for Interrupt 10.12" "0,1"
|
|
bitfld.word 0x15 10. "INTx11,Flag for Interrupt 10.11" "0,1"
|
|
bitfld.word 0x15 9. "INTx10,Flag for Interrupt 10.10" "0,1"
|
|
bitfld.word 0x15 8. "INTx9,Flag for Interrupt 10.9" "0,1"
|
|
bitfld.word 0x15 7. "INTx8,Flag for Interrupt 10.8" "0,1"
|
|
bitfld.word 0x15 6. "INTx7,Flag for Interrupt 10.7" "0,1"
|
|
bitfld.word 0x15 5. "INTx6,Flag for Interrupt 10.6" "0,1"
|
|
bitfld.word 0x15 4. "INTx5,Flag for Interrupt 10.5" "0,1"
|
|
newline
|
|
bitfld.word 0x15 3. "INTx4,Flag for Interrupt 10.4" "0,1"
|
|
bitfld.word 0x15 2. "INTx3,Flag for Interrupt 10.3" "0,1"
|
|
bitfld.word 0x15 1. "INTx2,Flag for Interrupt 10.2" "0,1"
|
|
bitfld.word 0x15 0. "INTx1,Flag for Interrupt 10.1" "0,1"
|
|
line.word 0x16 "PIEIER11,Interrupt Group 11 Enable Register"
|
|
bitfld.word 0x16 15. "INTx16,Enable for Interrupt 11.16" "0,1"
|
|
bitfld.word 0x16 14. "INTx15,Enable for Interrupt 11.15" "0,1"
|
|
bitfld.word 0x16 13. "INTx14,Enable for Interrupt 11.14" "0,1"
|
|
bitfld.word 0x16 12. "INTx13,Enable for Interrupt 11.13" "0,1"
|
|
bitfld.word 0x16 11. "INTx12,Enable for Interrupt 11.12" "0,1"
|
|
bitfld.word 0x16 10. "INTx11,Enable for Interrupt 11.11" "0,1"
|
|
bitfld.word 0x16 9. "INTx10,Enable for Interrupt 11.10" "0,1"
|
|
bitfld.word 0x16 8. "INTx9,Enable for Interrupt 11.9" "0,1"
|
|
bitfld.word 0x16 7. "INTx8,Enable for Interrupt 11.8" "0,1"
|
|
bitfld.word 0x16 6. "INTx7,Enable for Interrupt 11.7" "0,1"
|
|
bitfld.word 0x16 5. "INTx6,Enable for Interrupt 11.6" "0,1"
|
|
bitfld.word 0x16 4. "INTx5,Enable for Interrupt 11.5" "0,1"
|
|
newline
|
|
bitfld.word 0x16 3. "INTx4,Enable for Interrupt 11.4" "0,1"
|
|
bitfld.word 0x16 2. "INTx3,Enable for Interrupt 11.3" "0,1"
|
|
bitfld.word 0x16 1. "INTx2,Enable for Interrupt 11.2" "0,1"
|
|
bitfld.word 0x16 0. "INTx1,Enable for Interrupt 11.1" "0,1"
|
|
line.word 0x17 "PIEIFR11,Interrupt Group 11 Flag Register"
|
|
bitfld.word 0x17 15. "INTx16,Flag for Interrupt 11.16" "0,1"
|
|
bitfld.word 0x17 14. "INTx15,Flag for Interrupt 11.15" "0,1"
|
|
bitfld.word 0x17 13. "INTx14,Flag for Interrupt 11.14" "0,1"
|
|
bitfld.word 0x17 12. "INTx13,Flag for Interrupt 11.13" "0,1"
|
|
bitfld.word 0x17 11. "INTx12,Flag for Interrupt 11.12" "0,1"
|
|
bitfld.word 0x17 10. "INTx11,Flag for Interrupt 11.11" "0,1"
|
|
bitfld.word 0x17 9. "INTx10,Flag for Interrupt 11.10" "0,1"
|
|
bitfld.word 0x17 8. "INTx9,Flag for Interrupt 11.9" "0,1"
|
|
bitfld.word 0x17 7. "INTx8,Flag for Interrupt 11.8" "0,1"
|
|
bitfld.word 0x17 6. "INTx7,Flag for Interrupt 11.7" "0,1"
|
|
bitfld.word 0x17 5. "INTx6,Flag for Interrupt 11.6" "0,1"
|
|
bitfld.word 0x17 4. "INTx5,Flag for Interrupt 11.5" "0,1"
|
|
newline
|
|
bitfld.word 0x17 3. "INTx4,Flag for Interrupt 11.4" "0,1"
|
|
bitfld.word 0x17 2. "INTx3,Flag for Interrupt 11.3" "0,1"
|
|
bitfld.word 0x17 1. "INTx2,Flag for Interrupt 11.2" "0,1"
|
|
bitfld.word 0x17 0. "INTx1,Flag for Interrupt 11.1" "0,1"
|
|
line.word 0x18 "PIEIER12,Interrupt Group 12 Enable Register"
|
|
bitfld.word 0x18 15. "INTx16,Enable for Interrupt 12.16" "0,1"
|
|
bitfld.word 0x18 14. "INTx15,Enable for Interrupt 12.15" "0,1"
|
|
bitfld.word 0x18 13. "INTx14,Enable for Interrupt 12.14" "0,1"
|
|
bitfld.word 0x18 12. "INTx13,Enable for Interrupt 12.13" "0,1"
|
|
bitfld.word 0x18 11. "INTx12,Enable for Interrupt 12.12" "0,1"
|
|
bitfld.word 0x18 10. "INTx11,Enable for Interrupt 12.11" "0,1"
|
|
bitfld.word 0x18 9. "INTx10,Enable for Interrupt 12.10" "0,1"
|
|
bitfld.word 0x18 8. "INTx9,Enable for Interrupt 12.9" "0,1"
|
|
bitfld.word 0x18 7. "INTx8,Enable for Interrupt 12.8" "0,1"
|
|
bitfld.word 0x18 6. "INTx7,Enable for Interrupt 12.7" "0,1"
|
|
bitfld.word 0x18 5. "INTx6,Enable for Interrupt 12.6" "0,1"
|
|
bitfld.word 0x18 4. "INTx5,Enable for Interrupt 12.5" "0,1"
|
|
newline
|
|
bitfld.word 0x18 3. "INTx4,Enable for Interrupt 12.4" "0,1"
|
|
bitfld.word 0x18 2. "INTx3,Enable for Interrupt 12.3" "0,1"
|
|
bitfld.word 0x18 1. "INTx2,Enable for Interrupt 12.2" "0,1"
|
|
bitfld.word 0x18 0. "INTx1,Enable for Interrupt 12.1" "0,1"
|
|
line.word 0x19 "PIEIFR12,Interrupt Group 12 Flag Register"
|
|
bitfld.word 0x19 15. "INTx16,Flag for Interrupt 12.16" "0,1"
|
|
bitfld.word 0x19 14. "INTx15,Flag for Interrupt 12.15" "0,1"
|
|
bitfld.word 0x19 13. "INTx14,Flag for Interrupt 12.14" "0,1"
|
|
bitfld.word 0x19 12. "INTx13,Flag for Interrupt 12.13" "0,1"
|
|
bitfld.word 0x19 11. "INTx12,Flag for Interrupt 12.12" "0,1"
|
|
bitfld.word 0x19 10. "INTx11,Flag for Interrupt 12.11" "0,1"
|
|
bitfld.word 0x19 9. "INTx10,Flag for Interrupt 12.10" "0,1"
|
|
bitfld.word 0x19 8. "INTx9,Flag for Interrupt 12.9" "0,1"
|
|
bitfld.word 0x19 7. "INTx8,Flag for Interrupt 12.8" "0,1"
|
|
bitfld.word 0x19 6. "INTx7,Flag for Interrupt 12.7" "0,1"
|
|
bitfld.word 0x19 5. "INTx6,Flag for Interrupt 12.6" "0,1"
|
|
bitfld.word 0x19 4. "INTx5,Flag for Interrupt 12.5" "0,1"
|
|
newline
|
|
bitfld.word 0x19 3. "INTx4,Flag for Interrupt 12.4" "0,1"
|
|
bitfld.word 0x19 2. "INTx3,Flag for Interrupt 12.3" "0,1"
|
|
bitfld.word 0x19 1. "INTx2,Flag for Interrupt 12.2" "0,1"
|
|
bitfld.word 0x19 0. "INTx1,Flag for Interrupt 12.1" "0,1"
|
|
tree.end
|
|
tree "ROMPREFETCH"
|
|
base d:0x5F588
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ROMPREFETCH,ROM Prefetch Configuration Register"
|
|
bitfld.long 0x0 0. "PFENABLE,ROM Prefetch Enable/Disable Control" "0,1"
|
|
tree.end
|
|
tree "ROMWAITSTATE"
|
|
base d:0x5F580
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ROMWAITSTATE,ROM Wait State Configuration Register"
|
|
bitfld.long 0x0 0. "WSDISABLE,ROM Wait State Enable/Disable Control" "0,1"
|
|
tree.end
|
|
tree "SYNCSOC"
|
|
base d:0x7940
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SYNCSELECT,Sync Input and Output Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNCOUT,Select Syncout Source"
|
|
line.long 0x2 "ADCSOCOUTSELECT,External ADC (Off Chip) SOC Select Register"
|
|
bitfld.long 0x2 31. "PWM16SOCBEN,PWM16SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 30. "PWM15SOCBEN,PWM15SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 29. "PWM14SOCBEN,PWM14SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 28. "PWM13SOCBEN,PWM13SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 27. "PWM12SOCBEN,PWM12SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 26. "PWM11SOCBEN,PWM11SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 25. "PWM10SOCBEN,PWM10SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
newline
|
|
bitfld.long 0x2 24. "PWM9SOCBEN,PWM9SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 23. "PWM8SOCBEN,PWM8SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 22. "PWM7SOCBEN,PWM7SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 21. "PWM6SOCBEN,PWM6SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 20. "PWM5SOCBEN,PWM5SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 19. "PWM4SOCBEN,PWM4SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 18. "PWM3SOCBEN,PWM3SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
newline
|
|
bitfld.long 0x2 17. "PWM2SOCBEN,PWM2SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 16. "PWM1SOCBEN,PWM1SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x2 15. "PWM16SOCAEN,PWM16SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 14. "PWM15SOCAEN,PWM15SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 13. "PWM14SOCAEN,PWM14SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 12. "PWM13SOCAEN,PWM13SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 11. "PWM12SOCAEN,PWM12SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
newline
|
|
bitfld.long 0x2 10. "PWM11SOCAEN,PWM11SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 9. "PWM10SOCAEN,PWM10SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 8. "PWM9SOCAEN,PWM9SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 7. "PWM8SOCAEN,PWM8SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 6. "PWM7SOCAEN,PWM7SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 5. "PWM6SOCAEN,PWM6SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 4. "PWM5SOCAEN,PWM5SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "PWM4SOCAEN,PWM4SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 2. "PWM3SOCAEN,PWM3SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 1. "PWM2SOCAEN,PWM2SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x2 0. "PWM1SOCAEN,PWM1SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
line.long 0x4 "SYNCSOCLOCK,SYNCSEL and EXTADCSOC Select Lock register"
|
|
bitfld.long 0x4 1. "ADCSOCOUTSELECT,ADCSOCOUTSELECT Register Lock bit" "0,1"
|
|
bitfld.long 0x4 0. "SYNCSELECT,SYNCSEL Register Lock bit" "0,1"
|
|
tree.end
|
|
tree "SYSSTATUS"
|
|
base d:0x5D400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CM_STATUS_INT_FLG,Status of interrupts due to multiple sources of Cortex-M4 reset."
|
|
bitfld.long 0x0 3. "CMVECTRESET,CMVECTRESET caused a reset of CM" "0,1"
|
|
bitfld.long 0x0 2. "CMSYSRESETREQ,CMSYSRESETREQ caused a reset of CM" "0,1"
|
|
bitfld.long 0x0 1. "CMNMIWDRST,CMNMIWDRST caused a reset of CM" "0,1"
|
|
bitfld.long 0x0 0. "GINT,Global Interrupt flag" "0,1"
|
|
group.long 0x2++0xB
|
|
line.long 0x0 "CM_STATUS_INT_CLR,CM_STATUS_INT_FLG clear register"
|
|
bitfld.long 0x0 3. "CMVECTRESET,CMVECTRESET interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 2. "CMSYSRESETREQ,CMSYSRESETREQ interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 1. "CMNMIWDRST,CMNMIWDRST interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 0. "GINT,Global Interrupt flag Clear bit" "0,1"
|
|
line.long 0x2 "CM_STATUS_INT_SET,CM_STATUS_INT_FLG set register"
|
|
hexmask.long.word 0x2 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x2 3. "CMVECTRESET,CMVECTRESET interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 2. "CMSYSRESETREQ,CMSYSRESETREQ interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 1. "CMNMIWDRST,CMNMIWDRST interrupt flag set bit" "0,1"
|
|
line.long 0x4 "CM_STATUS_MASK,CM_STATUS_MASK register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x4 3. "CMVECTRESET,CMVECTRESET interrupt flag set bit" "0,1"
|
|
bitfld.long 0x4 2. "CMSYSRESETREQ,CMSYSRESETREQ interrupt flag set bit" "0,1"
|
|
bitfld.long 0x4 1. "CMNMIWDRST,CMNMIWDRST flag mask bit" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SYS_ERR_INT_FLG,Status of interrupts due to multiple different errors in the system."
|
|
bitfld.long 0x0 9. "DCC2,DCC2 Interrupt flag." "0,1"
|
|
bitfld.long 0x0 8. "DCC1,DCC1 Interrupt flag." "0,1"
|
|
bitfld.long 0x0 7. "DCC0,DCC0 Interrupt flag." "0,1"
|
|
bitfld.long 0x0 6. "AUX_PLL_SLIP,Auxillary PLL Slip event flag." "0,1"
|
|
bitfld.long 0x0 5. "SYS_PLL_SLIP,System PLL Slip event flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAM_ACC_VIOL,A RAM access vioation flag." "0,1"
|
|
bitfld.long 0x0 3. "FLASH_CORRECTABLE_ERR,FLASH correctable error flag" "0,1"
|
|
bitfld.long 0x0 2. "RAM_CORRECTABLE_ERR,RAM correctable error flag" "0,1"
|
|
bitfld.long 0x0 1. "EMIF_ERR,EMIF error event flag" "0,1"
|
|
bitfld.long 0x0 0. "GINT,Global Interrupt flag" "0,1"
|
|
group.long 0x12++0xB
|
|
line.long 0x0 "SYS_ERR_INT_CLR,SYS_ERR_INT_FLG clear register"
|
|
bitfld.long 0x0 9. "DCC2,DCC2 interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 8. "DCC1,DCC1 interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 7. "DCC0,DCC0 interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 6. "AUX_PLL_SLIP,AUX_PLL_SLIP interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 5. "SYS_PLL_SLIP,SYS_PLL_SLIP interrupt flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAM_ACC_VIOL,RAM_ACC_VIOL interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 3. "FLASH_CORRECTABLE_ERR,FLASH_CORRECTABLE_ERR interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 2. "RAM_CORRECTABLE_ERR,RAM_CORRECTABLE_ERR interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 1. "EMIF_ERR,EMIF_ERR interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x0 0. "GINT,Global Interrupt flag Clear bit" "0,1"
|
|
line.long 0x2 "SYS_ERR_INT_SET,SYS_ERR_INT_FLG set register"
|
|
hexmask.long.word 0x2 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x2 9. "DCC2,DCC2 interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 8. "DCC1,DCC1 interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 7. "DCC0,DCC0 interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 6. "AUX_PLL_SLIP,AUX_PLL_SLIP interrupt flag set bit" "0,1"
|
|
newline
|
|
bitfld.long 0x2 5. "SYS_PLL_SLIP,SYS_PLL_SLIP interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 4. "RAM_ACC_VIOL,RAM_ACC_VIOL interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 3. "FLASH_CORRECTABLE_ERR,FLASH_CORRECTABLE_ERR interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 2. "RAM_CORRECTABLE_ERR,RAM_CORRECTABLE_ERR interrupt flag set bit" "0,1"
|
|
bitfld.long 0x2 1. "EMIF_ERR,Reserved" "0,1"
|
|
line.long 0x4 "SYS_ERR_MASK,SYS_ERR_MASK register"
|
|
hexmask.long.word 0x4 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x4 9. "DCC2,DCC2 flag mask bit" "0,1"
|
|
bitfld.long 0x4 8. "DCC1,DCC1 flag mask bit" "0,1"
|
|
bitfld.long 0x4 7. "DCC0,DCC0 flag mask bit" "0,1"
|
|
bitfld.long 0x4 6. "AUX_PLL_SLIP,AUX_PLL_SLIP flag mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "SYS_PLL_SLIP,SYS_PLL_SLIP flag mask bit" "0,1"
|
|
bitfld.long 0x4 4. "RAM_ACC_VIOL,RAM_ACC_VIOL flag mask bit" "0,1"
|
|
bitfld.long 0x4 3. "FLASH_CORRECTABLE_ERR,FLASH_CORRECTABLE_ERR flag mask bit" "0,1"
|
|
bitfld.long 0x4 2. "RAM_CORRECTABLE_ERR,RAM_CORRECTABLE_ERR flag mask bit" "0,1"
|
|
bitfld.long 0x4 1. "EMIF_ERR,Reserved" "0,1"
|
|
tree.end
|
|
tree "TESTERROR"
|
|
base d:0x5F590
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CPU_RAM_TEST_ERROR_STS,Ram Test: Error Status Register"
|
|
bitfld.long 0x0 1. "UNC_ERROR,UNC_ERROR flag" "0,1"
|
|
bitfld.long 0x0 0. "COR_ERROR,COR_ERROR flag" "0,1"
|
|
group.long 0x2++0x3
|
|
line.long 0x0 "CPU_RAM_TEST_ERROR_STS_CLR,Ram Test: Error Status Clear Register"
|
|
bitfld.long 0x0 1. "UNC_ERROR,UNC_ERROR flag clear bit" "0,1"
|
|
bitfld.long 0x0 0. "COR_ERROR,COR_ERROR flag clear bit" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CPU_RAM_TEST_ERROR_ADDR,Ram Test: Error address register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address which generated the error in the RAM/ROM TEST modes."
|
|
tree.end
|
|
tree "WD"
|
|
base d:0x7000
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "SCSR,System Control and Status Register"
|
|
rbitfld.word 0x0 2. "WDINTS,WD Interrupt Status" "0,1"
|
|
bitfld.word 0x0 1. "WDENINT,WD Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 0. "WDOVERRIDE,WD Override for WDDIS bit" "0,1"
|
|
rgroup.word 0x23++0x1
|
|
line.word 0x0 "WDCNTR,Watchdog Counter Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "WDCNTR,WD Counter"
|
|
group.word 0x25++0x1
|
|
line.word 0x0 "WDKEY,Watchdog Reset Key Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "WDKEY,WD KEY"
|
|
group.word 0x29++0x3
|
|
line.word 0x0 "WDCR,Watchdog Control Register"
|
|
hexmask.word.byte 0x0 8.--11. 1. "WDPRECLKDIV,WD Pre Clock Divider"
|
|
bitfld.word 0x0 7. "WDFLG,WD Reset Status Flag" "0,1"
|
|
bitfld.word 0x0 6. "WDDIS,WD Disable" "0,1"
|
|
bitfld.word 0x0 3.--5. "WDCHK,WD Check Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 0.--2. "WDPS,WD Clock Prescalar" "0,1,2,3,4,5,6,7"
|
|
line.word 0x1 "WDWCR,Watchdog Windowed Control Register"
|
|
rbitfld.word 0x1 8. "FIRSTKEY,First Key Detect Flag" "0,1"
|
|
hexmask.word.byte 0x1 0.--7. 1. "MIN,WD Min Threshold setting for Windowed Watchdog functionality"
|
|
tree.end
|
|
tree "XINT"
|
|
base d:0x7070
|
|
group.word 0x0++0x9
|
|
line.word 0x0 "XINT1CR,XINT1 configuration register"
|
|
bitfld.word 0x0 2.--3. "POLARITY,XINT1 Polarity" "0,1,2,3"
|
|
bitfld.word 0x0 0. "ENABLE,XINT1 Enable" "0,1"
|
|
line.word 0x1 "XINT2CR,XINT2 configuration register"
|
|
bitfld.word 0x1 2.--3. "POLARITY,XINT2 Polarity" "0,1,2,3"
|
|
bitfld.word 0x1 0. "ENABLE,XINT2 Enable" "0,1"
|
|
line.word 0x2 "XINT3CR,XINT3 configuration register"
|
|
bitfld.word 0x2 2.--3. "POLARITY,XINT3 Polarity" "0,1,2,3"
|
|
bitfld.word 0x2 0. "ENABLE,XINT3 Enable" "0,1"
|
|
line.word 0x3 "XINT4CR,XINT4 configuration register"
|
|
bitfld.word 0x3 2.--3. "POLARITY,XINT4 Polarity" "0,1,2,3"
|
|
bitfld.word 0x3 0. "ENABLE,XINT4 Enable" "0,1"
|
|
line.word 0x4 "XINT5CR,XINT5 configuration register"
|
|
bitfld.word 0x4 2.--3. "POLARITY,XINT5 Polarity" "0,1,2,3"
|
|
bitfld.word 0x4 0. "ENABLE,XINT5 Enable" "0,1"
|
|
rgroup.word 0x8++0x5
|
|
line.word 0x0 "XINT1CTR,XINT1 counter register"
|
|
hexmask.word 0x0 0.--15. 1. "INTCTR,XINT1 Counter"
|
|
line.word 0x1 "XINT2CTR,XINT2 counter register"
|
|
hexmask.word 0x1 0.--15. 1. "INTCTR,XINT2 Counter"
|
|
line.word 0x2 "XINT3CTR,XINT3 counter register"
|
|
hexmask.word 0x2 0.--15. 1. "INTCTR,XINT3 Counter"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??-CM"))
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base d:0x4000C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "UARTDR,UART Data"
|
|
rbitfld.long 0x0 11. "OE,UART Overrun Error" "0,1"
|
|
rbitfld.long 0x0 10. "BE,UART Break Error" "0,1"
|
|
rbitfld.long 0x0 9. "PE,UART Parity Error" "0,1"
|
|
rbitfld.long 0x0 8. "FE,UART Framing Error" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "UARTRSR,UART Receive Status/Error Clear"
|
|
bitfld.long 0x0 3. "OE,UART Overrun Error" "0,1"
|
|
bitfld.long 0x0 2. "BE,UART Break Error" "0,1"
|
|
bitfld.long 0x0 1. "PE,UART Parity Error" "0,1"
|
|
bitfld.long 0x0 0. "FE,UART Framing Error" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "UARTFR,UART Flag"
|
|
bitfld.long 0x0 7. "TXFE,UART Transmit FIFO Empty" "0,1"
|
|
bitfld.long 0x0 6. "RXFF,UART Receive FIFO Full" "0,1"
|
|
bitfld.long 0x0 5. "TXFF,UART Transmit FIFO Full" "0,1"
|
|
bitfld.long 0x0 4. "RXFE,UART Receive FIFO Empty" "0,1"
|
|
bitfld.long 0x0 3. "BUSY,UART Busy" "0,1"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "UARTILPR,UART IrDA Low-Power Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ILPDVSR,IrDA Low-Power Divisor"
|
|
line.long 0x4 "UARTIBRD,UART Integer Baud-Rate Divisor"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "UARTFBRD,UART Fractional Baud-Rate Divisor"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "UARTLCRH,UART Line Control"
|
|
bitfld.long 0xC 7. "SPS,UART Stick Parity Select" "0,1"
|
|
bitfld.long 0xC 5.--6. "WLEN,UART Word Length" "0,1,2,3"
|
|
bitfld.long 0xC 4. "FEN,UART Enable FIFOs" "0,1"
|
|
bitfld.long 0xC 3. "STP2,UART Two Stop Bits Select" "0,1"
|
|
bitfld.long 0xC 2. "EPS,UART Even Parity Select" "0,1"
|
|
bitfld.long 0xC 1. "PEN,UART Parity Enable" "0,1"
|
|
bitfld.long 0xC 0. "BRK,UART Send Break" "0,1"
|
|
line.long 0x10 "UARTCTL,UART Control"
|
|
bitfld.long 0x10 9. "RXE,UART Receive Enable" "0,1"
|
|
bitfld.long 0x10 8. "TXE,UART Transmit Enable" "0,1"
|
|
bitfld.long 0x10 7. "LBE,UART Loop Back Enable" "0,1"
|
|
bitfld.long 0x10 5. "HSE,High-Speed Enable" "0,1"
|
|
bitfld.long 0x10 4. "EOT,End of Transmission" "0,1"
|
|
bitfld.long 0x10 2. "SIRLP,UART SIR Low-Power Mode" "0,1"
|
|
bitfld.long 0x10 1. "SIREN,UART SIR Enable" "0,1"
|
|
bitfld.long 0x10 0. "UARTEN,UART Enable" "0,1"
|
|
line.long 0x14 "UARTIFLS,UART Interrupt FIFO Level Select"
|
|
bitfld.long 0x14 3.--5. "RXIFLSEL,UART Receive Interrupt FIFO Level Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "UARTIM,UART Interrupt Mask"
|
|
bitfld.long 0x18 17. "DMATXIM,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 16. "DMARXIM,Receive DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 12. "9BITIM,9-Bit Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 10. "OEIM,UART Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 9. "BEIM,UART Break Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 8. "PEIM,UART Parity Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 7. "FEIM,UART Framing Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 6. "RTIM,UART Receive Time-Out Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 5. "TXIM,UART Transmit Interrupt Mask" "0,1"
|
|
bitfld.long 0x18 4. "RXIM,UART Receive Interrupt Mask" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "UARTRIS,UART Raw Interrupt Status"
|
|
bitfld.long 0x0 17. "DMATXRIS,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 16. "DMARXRIS,Receive DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 12. "9BITRIS,9-Bit Mode Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 10. "OERIS,UART Overrun Error Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 9. "BERIS,UART Break Error Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 8. "PERIS,UART Parity Error Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 7. "FERIS,UART Framing Error Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 6. "RTRIS,UART Receive Time-Out Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "TXRIS,UART Transmit Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x0 4. "RXRIS,UART Receive Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "UARTMIS,UART Masked Interrupt Status"
|
|
bitfld.long 0x4 17. "DMATXMIS,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "DMARXMIS,Receive DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "9BITMIS,9-Bit Mode Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "OEMIS,UART Overrun Error Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "BEMIS,UART Break Error Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "PEMIS,UART Parity Error Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 7. "FEMIS,UART Framing Error Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "RTMIS,UART Receive Time-Out Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "TXMIS,UART Transmit Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "RXMIS,UART Receive Masked Interrupt Status" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "UARTICR,UART Interrupt Clear"
|
|
bitfld.long 0x0 17. "DMATXIC,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 16. "DMARXIC,Receive DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 12. "9BITIC,9-Bit Mode Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 11. "EOTIC,End of Transmission Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 10. "OEIC,Overrun Error Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 9. "BEIC,Break Error Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 8. "PEIC,Parity Error Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 7. "FEIC,Framing Error Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "RTIC,Receive Time-Out Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 5. "TXIC,Transmit Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXIC,Receive Interrupt Clear" "0,1"
|
|
line.long 0x4 "UARTDMACTL,UART DMA Control"
|
|
bitfld.long 0x4 2. "DMAERR,DMA on Error" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAE,Transmit DMA Enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAE,Receive DMA Enable" "0,1"
|
|
group.long 0xA4++0x7
|
|
line.long 0x0 "UART9BITADDR,UART 9-Bit Self Address"
|
|
bitfld.long 0x0 15. "9BITEN,Enable 9-Bit Mode" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Self Address for 9-Bit Mode"
|
|
line.long 0x4 "UART9BITAMASK,UART 9-Bit Self Address Mask"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MASK,Self Address Mask for 9-Bit Mode"
|
|
rgroup.long 0xFC0++0x3
|
|
line.long 0x0 "UARTPP,UART Peripheral Properties"
|
|
bitfld.long 0x0 3. "MSE,Modem Support Extended" "0,1"
|
|
bitfld.long 0x0 2. "MS,Modem Support" "0,1"
|
|
bitfld.long 0x0 1. "NB,9-Bit Support" "0,1"
|
|
bitfld.long 0x0 0. "SC,Smart Card Support" "0,1"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x0 "UARTPeriphID4,UART Peripheral Identification 4"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID4,UART Peripheral ID Register [7:0]"
|
|
line.long 0x4 "UARTPeriphID5,UART Peripheral Identification 5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PID5,UART Peripheral ID Register [15:8]"
|
|
line.long 0x8 "UARTPeriphID6,UART Peripheral Identification 6"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PID6,UART Peripheral ID Register [23:16]"
|
|
line.long 0xC "UARTPeriphID7,UART Peripheral Identification 7"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PID7,UART Peripheral ID Register [31:24]"
|
|
line.long 0x10 "UARTPeriphID0,UART Peripheral Identification 0"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PID0,UART Peripheral ID Register [7:0]"
|
|
line.long 0x14 "UARTPeriphID1,UART Peripheral Identification 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PID1,UART Peripheral ID Register [15:8]"
|
|
line.long 0x18 "UARTPeriphID2,UART Peripheral Identification 2"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PID2,UART Peripheral ID Register [23:16]"
|
|
line.long 0x1C "UARTPeriphID3,UART Peripheral Identification 3"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PID3,UART Peripheral ID Register [31:24]"
|
|
line.long 0x20 "UARTPCellID0,UART PrimeCell Identification 0"
|
|
hexmask.long.byte 0x20 0.--7. 1. "CID0,UART PrimeCell ID Register [7:0]"
|
|
line.long 0x24 "UARTPCellID1,UART PrimeCell Identification 1"
|
|
hexmask.long.byte 0x24 0.--7. 1. "CID1,UART PrimeCell ID Register [15:8]"
|
|
line.long 0x28 "UARTPCellID2,UART PrimeCell Identification 2"
|
|
hexmask.long.byte 0x28 0.--7. 1. "CID2,UART PrimeCell ID Register [23:16]"
|
|
line.long 0x2C "UARTPCellID3,UART PrimeCell Identification 3"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "CID3,UART PrimeCell ID Register [31:24]"
|
|
tree.end
|
|
tree "UDMA (Micro Direct Memory Access)"
|
|
base d:0x400FF000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMASTAT,DMA Status"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DMACHANS,Available DMA Channels Minus 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "STATE,Control State Machine Status"
|
|
bitfld.long 0x0 0. "MASTEN,Master Enable Status" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x0 0. "MASTEN,Controller Master Enable" "0,1"
|
|
line.long 0x4 "DMACTLBASE,DMA Channel Control Base Pointer"
|
|
hexmask.long.tbyte 0x4 10.--31. 1. "ADDR,Channel Control Base Address"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DMAALTBASE,DMA Alternate Channel Control Base Pointer"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Alternate Channel Address Pointer"
|
|
group.long 0x14++0x2B
|
|
line.long 0x0 "DMASWREQ,DMA Channel Software Request"
|
|
hexmask.long 0x0 0.--31. 1. "SWREQ,Channel [n] Software Request"
|
|
line.long 0x4 "DMAUSEBURSTSET,DMA Channel Useburst Set"
|
|
hexmask.long 0x4 0.--31. 1. "SET,Channel [n] Useburst Set"
|
|
line.long 0x8 "DMAUSEBURSTCLR,DMA Channel Useburst Clear"
|
|
hexmask.long 0x8 0.--31. 1. "CLR,Channel [n] Useburst Clear"
|
|
line.long 0xC "DMAREQMASKSET,DMA Channel Request Mask Set"
|
|
hexmask.long 0xC 0.--31. 1. "SET,Channel [n] Request Mask Set"
|
|
line.long 0x10 "DMAREQMASKCLR,DMA Channel Request Mask Clear"
|
|
hexmask.long 0x10 0.--31. 1. "CLR,Channel [n] Request Mask Clear"
|
|
line.long 0x14 "DMAENASET,DMA Channel Enable Set"
|
|
hexmask.long 0x14 0.--31. 1. "SET,Channel [n] Enable Set"
|
|
line.long 0x18 "DMAENACLR,DMA Channel Enable Clear"
|
|
hexmask.long 0x18 0.--31. 1. "CLR,Clear Channel [n] Enable Clear"
|
|
line.long 0x1C "DMAALTSET,DMA Channel Primary Alternate Set"
|
|
hexmask.long 0x1C 0.--31. 1. "SET,Channel [n] Alternate Set"
|
|
line.long 0x20 "DMAALTCLR,DMA Channel Primary Alternate Clear"
|
|
hexmask.long 0x20 0.--31. 1. "CLR,Channel [n] Alternate Clear"
|
|
line.long 0x24 "DMAPRIOSET,DMA Channel Priority Set"
|
|
hexmask.long 0x24 0.--31. 1. "SET,Channel [n] Priority Set"
|
|
line.long 0x28 "DMAPRIOCLR,DMA Channel Priority Clear"
|
|
hexmask.long 0x28 0.--31. 1. "CLR,Channel [n] Priority Clear"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DMAERRCLR,DMA Bus Error Clear"
|
|
bitfld.long 0x0 0. "ERRCLR,DMA Bus Error Status" "0,1"
|
|
group.long 0x510++0xF
|
|
line.long 0x0 "DMACHMAP0,DMA Channel Map Select 0"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CH7SEL,DMA Channel 7 Source Select"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CH6SEL,DMA Channel 6 Source Select"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CH5SEL,DMA Channel 5 Source Select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CH4SEL,DMA Channel 4 Source Select"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CH3SEL,DMA Channel 3 Source Select"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CH2SEL,DMA Channel 2 Source Select"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CH1SEL,DMA Channel 1 Source Select"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CH0SEL,DMA Channel 0 Source Select"
|
|
line.long 0x4 "DMACHMAP1,DMA Channel Map Select 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "CH15SEL,DMA Channel 15 Source Select"
|
|
hexmask.long.byte 0x4 24.--27. 1. "CH14SEL,DMA Channel 14 Source Select"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CH13SEL,DMA Channel 13 Source Select"
|
|
hexmask.long.byte 0x4 16.--19. 1. "CH12SEL,DMA Channel 12 Source Select"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CH11SEL,DMA Channel 11 Source Select"
|
|
hexmask.long.byte 0x4 8.--11. 1. "CH10SEL,DMA Channel 10 Source Select"
|
|
hexmask.long.byte 0x4 4.--7. 1. "CH9SEL,DMA Channel 9 Source Select"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CH8SEL,DMA Channel 8 Source Select"
|
|
line.long 0x8 "DMACHMAP2,DMA Channel Map Select 2"
|
|
hexmask.long.byte 0x8 28.--31. 1. "CH23SEL,DMA Channel 23 Source Select"
|
|
hexmask.long.byte 0x8 24.--27. 1. "CH22SEL,DMA Channel 22 Source Select"
|
|
hexmask.long.byte 0x8 20.--23. 1. "CH21SEL,DMA Channel 21 Source Select"
|
|
hexmask.long.byte 0x8 16.--19. 1. "CH20SEL,DMA Channel 20 Source Select"
|
|
hexmask.long.byte 0x8 12.--15. 1. "CH19SEL,DMA Channel 19 Source Select"
|
|
hexmask.long.byte 0x8 8.--11. 1. "CH18SEL,DMA Channel 18 Source Select"
|
|
hexmask.long.byte 0x8 4.--7. 1. "CH17SEL,DMA Channel 17 Source Select"
|
|
hexmask.long.byte 0x8 0.--3. 1. "CH16SEL,DMA Channel 16 Source Select"
|
|
line.long 0xC "DMACHMAP3,DMA Channel Map Select 3"
|
|
hexmask.long.byte 0xC 28.--31. 1. "CH31SEL,DMA Channel 31 Source Select"
|
|
hexmask.long.byte 0xC 24.--27. 1. "CH30SEL,DMA Channel 30 Source Select"
|
|
hexmask.long.byte 0xC 20.--23. 1. "CH29SEL,DMA Channel 29 Source Select"
|
|
hexmask.long.byte 0xC 16.--19. 1. "CH28SEL,DMA Channel 28 Source Select"
|
|
hexmask.long.byte 0xC 12.--15. 1. "CH27SEL,DMA Channel 27 Source Select"
|
|
hexmask.long.byte 0xC 8.--11. 1. "CH26SEL,DMA Channel 26 Source Select"
|
|
hexmask.long.byte 0xC 4.--7. 1. "CH25SEL,DMA Channel 25 Source Select"
|
|
hexmask.long.byte 0xC 0.--3. 1. "CH24SEL,DMA Channel 24 Source Select"
|
|
rgroup.long 0xFD0++0x3
|
|
line.long 0x0 "DMAPeriphID4,DMA Peripheral Identification 4"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID4,DMA Peripheral ID Register"
|
|
rgroup.long 0xFE0++0x1F
|
|
line.long 0x0 "DMAPeriphID0,DMA Peripheral Identification 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID0,DMA Peripheral ID Register [7:0]"
|
|
line.long 0x4 "DMAPeriphID1,DMA Peripheral Identification 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PID1,DMA Peripheral ID Register [15:8]"
|
|
line.long 0x8 "DMAPeriphID2,DMA Peripheral Identification 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PID2,DMA Peripheral ID Register [23:16]"
|
|
line.long 0xC "DMAPeriphID3,DMA Peripheral Identification 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PID3,DMA Peripheral ID Register [31:24]"
|
|
line.long 0x10 "DMAPCellID0,DMA PrimeCell Identification 0"
|
|
hexmask.long.byte 0x10 0.--7. 1. "CID0,DMA PrimeCell ID Register [7:0]"
|
|
line.long 0x14 "DMAPCellID1,DMA PrimeCell Identification 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. "CID1,DMA PrimeCell ID Register [15:8]"
|
|
line.long 0x18 "DMAPCellID2,DMA PrimeCell Identification 2"
|
|
hexmask.long.byte 0x18 0.--7. 1. "CID2,DMA PrimeCell ID Register [23:16]"
|
|
line.long 0x1C "DMAPCellID3,DMA PrimeCell Identification 3"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "CID3,DMA PrimeCell ID Register [31:24]"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "USB (Universal Serial Bus)"
|
|
base d:0x40000
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "USBFADDR,USB Device Functional Address"
|
|
hexmask.word.byte 0x0 0.--6. 1. "FUNCADDR,Functional Address"
|
|
line.word 0x1 "USBPOWER,USB Power"
|
|
bitfld.word 0x1 7. "ISOUP,Isochronous Update" "0,1"
|
|
bitfld.word 0x1 6. "SOFT_CONN,Soft Connect/Disconnect" "0,1"
|
|
bitfld.word 0x1 3. "RESET,Enable Reset Signaling" "0,1"
|
|
bitfld.word 0x1 2. "RESUME,Enable Resume Signaling" "0,1"
|
|
bitfld.word 0x1 1. "SUSPEND,Enable Suspend" "0,1"
|
|
newline
|
|
bitfld.word 0x1 0. "PWRDNPHY,Power Down PHY" "0,1"
|
|
rgroup.word 0x2++0x3
|
|
line.word 0x0 "USBTXIS,USB Transmit Interrupt Status"
|
|
bitfld.word 0x0 3. "EP3,Transmit Endpoint 3 Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "EP2,Transmit Endpoint 2 Interrupt" "0,1"
|
|
bitfld.word 0x0 1. "EP1,Transmit Endpoint 1 Interrupt" "0,1"
|
|
bitfld.word 0x0 0. "EP0,Transmit Endpoint 0 Interrupt" "0,1"
|
|
line.word 0x2 "USBRXIS,USB Receive Interrupt Status"
|
|
bitfld.word 0x2 3. "EP3,Recieve Endpoint 3 Interrupt" "0,1"
|
|
bitfld.word 0x2 2. "EP2,Recieve Endpoint 2 Interrupt" "0,1"
|
|
bitfld.word 0x2 1. "EP1,Recieve Endpoint 1 Interrupt" "0,1"
|
|
group.word 0x6++0x7
|
|
line.word 0x0 "USBTXIE,USB Transmit Interrupt Enable"
|
|
bitfld.word 0x0 3. "EP3,Transmit Endpoint 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "EP2,Transmit Endpoint 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 1. "EP1,Transmit Endpoint 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 0. "EP0,Transmit Endpoint 0 Interrupt Enable" "0,1"
|
|
line.word 0x2 "USBRXIE,USB Receive Interrupt Enable"
|
|
bitfld.word 0x2 3. "EP3,Recieve Endpoint 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "EP2,Recieve Endpoint 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 1. "EP1,Recieve Endpoint 1 Interrupt Enable" "0,1"
|
|
line.word 0x4 "USBIS,USB General Interrupt Status"
|
|
bitfld.word 0x4 5. "DISCON,Session Disconnect" "0,1"
|
|
bitfld.word 0x4 3. "SOF,Start of frame" "0,1"
|
|
bitfld.word 0x4 2. "RESET,RESET Signaling Detected" "0,1"
|
|
bitfld.word 0x4 1. "RESUME,RESUME Signaling Detected." "0,1"
|
|
rbitfld.word 0x4 0. "SUSPEND,SUSPEND Signaling Detected" "0,1"
|
|
line.word 0x5 "USBIE,USB Interrupt Enable"
|
|
bitfld.word 0x5 5. "DISCON,Session Disconnect" "0,1"
|
|
bitfld.word 0x5 3. "SOF,Start of frame" "0,1"
|
|
bitfld.word 0x5 2. "RESET,RESET Signaling Detected" "0,1"
|
|
bitfld.word 0x5 1. "RESUME,RESUME Signaling Detected." "0,1"
|
|
rbitfld.word 0x5 0. "SUSPEND,SUSPEND Signaling Detected" "0,1"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "USBFRAME,USB Frame Value"
|
|
hexmask.word 0x0 0.--10. 1. "FRAME,Frame Number"
|
|
group.word 0xE++0x3
|
|
line.word 0x0 "USBEPIDX,USB Endpoint Index"
|
|
hexmask.word.byte 0x0 0.--3. 1. "EPIDX,Endpoint Index"
|
|
line.word 0x1 "USBTEST,USB Test Mode"
|
|
bitfld.word 0x1 7. "FORCEH,Force Host Mode" "0,1"
|
|
bitfld.word 0x1 6. "FIFOACC,FIFO Access" "0,1"
|
|
bitfld.word 0x1 5. "FORCEFS,Force Full Speed Upon Reset" "0,1"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "USBFIFO0,USB FIFO Endpoint 0"
|
|
hexmask.long 0x0 0.--31. 1. "EPDATA,Endpoint Data."
|
|
line.long 0x4 "USBFIFO1,USB FIFO Endpoint 1"
|
|
hexmask.long 0x4 0.--31. 1. "EPDATA,Endpoint Data."
|
|
line.long 0x8 "USBFIFO2,USB FIFO Endpoint 2"
|
|
hexmask.long 0x8 0.--31. 1. "EPDATA,Endpoint Data."
|
|
line.long 0xC "USBFIFO3,USB FIFO Endpoint 3"
|
|
hexmask.long 0xC 0.--31. 1. "EPDATA,Endpoint Data."
|
|
group.word 0x60++0x9
|
|
line.word 0x0 "USBDEVCTL,USB Device Control"
|
|
rbitfld.word 0x0 7. "DEV,Device Mode" "0,1"
|
|
bitfld.word 0x0 6. "FSDEV,Full Speed Device Detected" "0,1"
|
|
rbitfld.word 0x0 5. "LSDEV,Low Speed Device Detected" "0,1"
|
|
bitfld.word 0x0 3.--4. "VBUS,Vbus Level" "0,1,2,3"
|
|
bitfld.word 0x0 2. "HOST,Host Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "HOSTREQ,Host Request" "0,1"
|
|
rbitfld.word 0x0 0. "SESSION,Session Start/End" "0,1"
|
|
line.word 0x2 "USBTXFIFOSZ,USB Transmit Dynamic FIFO Sizing"
|
|
bitfld.word 0x2 4. "DPB,Double Packet Buffer Support" "0,1"
|
|
hexmask.word.byte 0x2 0.--3. 1. "SIZE,Max Packet Size"
|
|
line.word 0x3 "USBRXFIFOSZ,USB Receive Dynamic FIFO Sizing"
|
|
bitfld.word 0x3 4. "DPB,Double Packet Buffer Support" "0,1"
|
|
hexmask.word.byte 0x3 0.--3. 1. "SIZE,Max Packet Size"
|
|
line.word 0x4 "USBTXFIFOADD,USB Transmit FIFO Start Address"
|
|
hexmask.word 0x4 0.--8. 1. "ADDR,Endpoint Data"
|
|
line.word 0x6 "USBRXFIFOADD,USB Receive FIFO Start Address"
|
|
hexmask.word 0x6 0.--8. 1. "ADDR,Endpoint Data"
|
|
group.word 0x7A++0x1
|
|
line.word 0x0 "USBCONTIM,USB Connect Timing"
|
|
hexmask.word.byte 0x0 4.--7. 1. "WTCON,Connect Wait"
|
|
hexmask.word.byte 0x0 0.--3. 1. "WTID,Wait ID"
|
|
group.word 0x7D++0x9
|
|
line.word 0x0 "USBFSEOF,USB Full-Speed Last Transaction to End of Frame Timing"
|
|
hexmask.word.byte 0x0 0.--7. 1. "FSEOFG,The full-speed end-of-frame gap field"
|
|
line.word 0x1 "USBLSEOF,USB Low-Speed Last Transaction to End of Frame Timing"
|
|
hexmask.word.byte 0x1 0.--7. 1. "LSEOFG,The low-speed end-of-frame gap field"
|
|
line.word 0x3 "USBTXFUNCADDR0,USB Transmit Functional Address Endpoint 0"
|
|
hexmask.word.byte 0x3 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0x5 "USBTXHUBADDR0,USB Transmit Hub Address Endpoint 0"
|
|
hexmask.word.byte 0x5 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x6 "USBTXHUBPORT0,USB Transmit Hub Port Endpoint 0"
|
|
hexmask.word.byte 0x6 0.--6. 1. "ADDR,Hub Port"
|
|
group.word 0x88++0x23
|
|
line.word 0x0 "USBTXFUNCADDR1,USB Transmit Functional Address Endpoint 1"
|
|
hexmask.word.byte 0x0 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0x2 "USBTXHUBADDR1,USB Transmit Hub Address Endpoint 1"
|
|
hexmask.word.byte 0x2 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x3 "USBTXHUBPORT1,USB Transmit Hub Port Endpoint 1"
|
|
hexmask.word.byte 0x3 0.--6. 1. "ADDR,Hub Port"
|
|
line.word 0x4 "USBRXFUNCADDR1,USB Receive Functional Address Endpoint 1"
|
|
hexmask.word.byte 0x4 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0x6 "USBRXHUBADDR1,USB Receive Hub Address Endpoint 1"
|
|
bitfld.word 0x6 7. "MULTTRAN,Hub has Multiple Translators" "0,1"
|
|
hexmask.word.byte 0x6 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x7 "USBRXHUBPORT1,USB Receive Hub Port Endpoint 1"
|
|
hexmask.word.byte 0x7 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x8 "USBTXFUNCADDR2,USB Transmit Functional Address Endpoint 2"
|
|
hexmask.word.byte 0x8 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0xA "USBTXHUBADDR2,USB Transmit Hub Address Endpoint 2"
|
|
hexmask.word.byte 0xA 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0xB "USBTXHUBPORT2,USB Transmit Hub Port Endpoint 2"
|
|
hexmask.word.byte 0xB 0.--6. 1. "ADDR,Hub Port"
|
|
line.word 0xC "USBRXFUNCADDR2,USB Receive Functional Address Endpoint 2"
|
|
hexmask.word.byte 0xC 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0xE "USBRXHUBADDR2,USB Receive Hub Address Endpoint 2"
|
|
bitfld.word 0xE 7. "MULTTRAN,Hub has Multiple Translators" "0,1"
|
|
hexmask.word.byte 0xE 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0xF "USBRXHUBPORT2,USB Receive Hub Port Endpoint 2"
|
|
hexmask.word.byte 0xF 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x10 "USBTXFUNCADDR3,USB Transmit Functional Address Endpoint 3"
|
|
hexmask.word.byte 0x10 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0x12 "USBTXHUBADDR3,USB Transmit Hub Address Endpoint 3"
|
|
hexmask.word.byte 0x12 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x13 "USBTXHUBPORT3,USB Transmit Hub Port Endpoint 3"
|
|
hexmask.word.byte 0x13 0.--6. 1. "ADDR,Hub Port"
|
|
line.word 0x14 "USBRXFUNCADDR3,USB Receive Functional Address Endpoint 3"
|
|
hexmask.word.byte 0x14 0.--6. 1. "ADDR,Device Address"
|
|
line.word 0x16 "USBRXHUBADDR3,USB Receive Hub Address Endpoint 3"
|
|
bitfld.word 0x16 7. "MULTTRAN,Hub has Multiple Translators" "0,1"
|
|
hexmask.word.byte 0x16 0.--6. 1. "ADDR,Hub Address"
|
|
line.word 0x17 "USBRXHUBPORT3,USB Receive Hub Port Endpoint 3"
|
|
hexmask.word.byte 0x17 0.--6. 1. "ADDR,Hub Address"
|
|
group.word 0x102++0x3
|
|
line.word 0x0 "USBCSRL0,USB Control and Status Endpoint 0 Low"
|
|
bitfld.word 0x0 7. "SETENDC_NAKTO,Setup End Clear/NAK Timeout" "0,1"
|
|
bitfld.word 0x0 6. "RXRDYC_STATUS,RXRDY Clear/STATUS Packet" "0,1"
|
|
bitfld.word 0x0 5. "STALL_RQPKT,Send Stall /Request Packet" "0,1"
|
|
bitfld.word 0x0 4. "SETEND_ERROR,Setup End/Error" "0,1"
|
|
bitfld.word 0x0 3. "DATAEND_SETUP,Data End/Setup Packet" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x0 1. "TXRDY,Transmit Packet Ready" "0,1"
|
|
bitfld.word 0x0 0. "RXRDY,Receive Packet Ready" "0,1"
|
|
line.word 0x1 "USBCSRH0,USB Control and Status Endpoint 0 High"
|
|
bitfld.word 0x1 2. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x1 1. "DT,Data Toggle" "0,1"
|
|
bitfld.word 0x1 0. "FLUSH,Flush FIFO" "0,1"
|
|
group.word 0x108++0x5
|
|
line.word 0x0 "USBCOUNT0,USB Receive Byte Count Endpoint 0"
|
|
hexmask.word.byte 0x0 0.--6. 1. "COUNT,FIFO Count"
|
|
line.word 0x2 "USBTYPE0,USB Type Endpoint 0"
|
|
bitfld.word 0x2 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
line.word 0x3 "USBNAKLMT,USB NAK Limit"
|
|
hexmask.word.byte 0x3 0.--4. 1. "NAKLMT,EP0 NAK Limit"
|
|
group.word 0x110++0xB
|
|
line.word 0x0 "USBTXMAXP1,USB Maximum Transmit Data Endpoint 1"
|
|
hexmask.word 0x0 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
line.word 0x2 "USBTXCSRL1,USB Transmit Control and Status Endpoint 1 Low"
|
|
bitfld.word 0x2 7. "NAKTO,NAK Timeout" "0,1"
|
|
bitfld.word 0x2 6. "CLRDT,Clear Data Toggle" "0,1"
|
|
bitfld.word 0x2 5. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x2 4. "STALL_SETUP,Send Stall/Setup Packet" "0,1"
|
|
bitfld.word 0x2 3. "FLUSH,Flush FIFO" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "UNDRN_ERROR1,Underun/Error" "0,1"
|
|
bitfld.word 0x2 1. "FIFONE,FIFO Not Empty" "0,1"
|
|
bitfld.word 0x2 0. "TXRDY,Transmit Packet Ready" "0,1"
|
|
line.word 0x3 "USBTXCSRH1,USB Transmit Control and Status Endpoint 1 High"
|
|
bitfld.word 0x3 7. "AUTOSET,Auto Set" "0,1"
|
|
bitfld.word 0x3 6. "ISO,Isochronous Transfers" "0,1"
|
|
bitfld.word 0x3 5. "MODE,Mode" "0,1"
|
|
bitfld.word 0x3 4. "DMAEN,DMA Request Enable" "0,1"
|
|
bitfld.word 0x3 3. "FDT,Force Data Toggle" "0,1"
|
|
newline
|
|
bitfld.word 0x3 2. "DMAMOD,DMA Request Mode" "0,1"
|
|
bitfld.word 0x3 1. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x3 0. "DT,Data Toggle" "0,1"
|
|
line.word 0x4 "USBRXMAXP1,USB Maximum Receive Data Endpoint 1"
|
|
hexmask.word 0x4 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
line.word 0x6 "USBRXCSRL1,USB Receive Control and Status Endpoint 1 Low"
|
|
bitfld.word 0x6 7. "CLRDT,Clear Data Toggle" "0,1"
|
|
bitfld.word 0x6 6. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x6 5. "STALLREQPKT,Send Stall/Request Packet" "0,1"
|
|
bitfld.word 0x6 4. "FLUSH,Flush FIFO" "0,1"
|
|
bitfld.word 0x6 3. "DATAERRNAKTO,Data Error/NAK Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x6 2. "OVERERROR1,Overrun/Error" "0,1"
|
|
bitfld.word 0x6 1. "FULL,FIFO Full" "0,1"
|
|
bitfld.word 0x6 0. "RXRDY,Recieve Packet Ready" "0,1"
|
|
line.word 0x7 "USBRXCSRH1,USB Receive Control and Status Endpoint 1 High"
|
|
bitfld.word 0x7 7. "AUTOCL,Auto Clear" "0,1"
|
|
bitfld.word 0x7 6. "ISOAUTORQ,Isochronous Transfers/Auto Request" "0,1"
|
|
bitfld.word 0x7 5. "DMAEN,DMA Request Enable" "0,1"
|
|
bitfld.word 0x7 4. "DISNYETPIDERR,Disable NYET / PID Error" "0,1"
|
|
bitfld.word 0x7 3. "DMAMOD,DMA Request Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x7 2. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x7 1. "DT,Data Toggle" "0,1"
|
|
rgroup.word 0x118++0x1
|
|
line.word 0x0 "USBRXCOUNT1,USB Receive Byte Count Endpoint 1"
|
|
hexmask.word 0x0 0.--12. 1. "COUNT,Receive Packet Count"
|
|
group.word 0x11A++0x7
|
|
line.word 0x0 "USBTXTYPE1,USB Host Transmit Configure Type Endpoint 1"
|
|
bitfld.word 0x0 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "PROTO,Protocol" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TEP,Target Endpoint Number"
|
|
line.word 0x1 "USBTXINTERVAL1,USB Host Transmit Interval Endpoint 1"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TXPOLLNAKLMT,TX Polling / NAK Limit"
|
|
line.word 0x2 "USBRXTYPE1,USB Host Configure Receive Type Endpoint 1"
|
|
bitfld.word 0x2 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "PROTO,Protocol" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "TEP,Target Endpoint Number"
|
|
line.word 0x3 "USBRXINTERVAL1,USB Host Receive Polling Interval Endpoint 1"
|
|
hexmask.word.byte 0x3 0.--7. 1. "RXPOLLNAKLMT,RX Polling / NAK Limit"
|
|
group.word 0x120++0xB
|
|
line.word 0x0 "USBTXMAXP2,USB Maximum Transmit Data Endpoint 2"
|
|
hexmask.word 0x0 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
line.word 0x2 "USBTXCSRL2,USB Transmit Control and Status Endpoint 2 Low"
|
|
bitfld.word 0x2 7. "NAKTO,NAK Timeout" "0,1"
|
|
bitfld.word 0x2 6. "CLRDT,Clear Data Toggle" "0,1"
|
|
bitfld.word 0x2 5. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x2 4. "STALL_SETUP,Send Stall/Setup Packet" "0,1"
|
|
bitfld.word 0x2 3. "FLUSH,Flush FIFO" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "UNDRNERROR2,Underun/Error" "0,1"
|
|
bitfld.word 0x2 1. "FIFONE,FIFO Not Empty" "0,1"
|
|
bitfld.word 0x2 0. "TXRDY,Transmit Packet Ready" "0,1"
|
|
line.word 0x3 "USBTXCSRH2,USB Transmit Control and Status Endpoint 2 High"
|
|
bitfld.word 0x3 7. "AUTOSET,Auto Set" "0,1"
|
|
bitfld.word 0x3 6. "ISO,Isochronous Transfers" "0,1"
|
|
bitfld.word 0x3 5. "MODE,Mode" "0,1"
|
|
bitfld.word 0x3 4. "DMAEN,DMA Request Enable" "0,1"
|
|
bitfld.word 0x3 3. "FDT,Force Data Toggle" "0,1"
|
|
newline
|
|
bitfld.word 0x3 2. "DMAMOD,DMA Request Mode" "0,1"
|
|
bitfld.word 0x3 1. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x3 0. "DT,Data Toggle" "0,1"
|
|
line.word 0x4 "USBRXMAXP2,USB Maximum Receive Data Endpoint 2"
|
|
hexmask.word 0x4 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
line.word 0x6 "USBRXCSRL2,USB Receive Control and Status Endpoint 2 Low"
|
|
bitfld.word 0x6 7. "CLRDT,Clear Data Toggle" "0,1"
|
|
bitfld.word 0x6 6. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x6 5. "STALLREQPKT,Send Stall/Request Packet" "0,1"
|
|
bitfld.word 0x6 4. "FLUSH,Flush FIFO" "0,1"
|
|
bitfld.word 0x6 3. "DATAERRNAKTO,Data Error/NAK Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x6 2. "OVERERROR2,Overrun/Error" "0,1"
|
|
bitfld.word 0x6 1. "FULL,FIFO Full" "0,1"
|
|
bitfld.word 0x6 0. "RXRDY,Recieve Packet Ready" "0,1"
|
|
line.word 0x7 "USBRXCSRH2,USB Receive Control and Status Endpoint 2 High"
|
|
bitfld.word 0x7 7. "AUTOCL,Auto Clear" "0,1"
|
|
bitfld.word 0x7 6. "ISOAUTORQ,Isochronous Transfers/Auto Request" "0,1"
|
|
bitfld.word 0x7 5. "DMAEN,DMA Request Enable" "0,1"
|
|
bitfld.word 0x7 4. "DISNYETPIDERR,Disable NYET / PID Error" "0,1"
|
|
bitfld.word 0x7 3. "DMAMOD,DMA Request Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x7 2. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x7 1. "DT,Data Toggle" "0,1"
|
|
rgroup.word 0x128++0x1
|
|
line.word 0x0 "USBRXCOUNT2,USB Receive Byte Count Endpoint 2"
|
|
hexmask.word 0x0 0.--12. 1. "COUNT,Receive Packet Count"
|
|
group.word 0x12A++0x7
|
|
line.word 0x0 "USBTXTYPE2,USB Host Transmit Configure Type Endpoint 2"
|
|
bitfld.word 0x0 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "PROTO,Protocol" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TEP,Target Endpoint Number"
|
|
line.word 0x1 "USBTXINTERVAL2,USB Host Transmit Interval Endpoint 2"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TXPOLLNAKLMT,TX Polling / NAK Limit"
|
|
line.word 0x2 "USBRXTYPE2,USB Host Configure Receive Type Endpoint 2"
|
|
bitfld.word 0x2 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "PROTO,Protocol" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "TEP,Target Endpoint Number"
|
|
line.word 0x3 "USBRXINTERVAL2,USB Host Receive Polling Interval Endpoint 2"
|
|
hexmask.word.byte 0x3 0.--7. 1. "RXPOLLNAKLMT,RX Polling / NAK Limit"
|
|
group.word 0x130++0xB
|
|
line.word 0x0 "USBTXMAXP3,USB Maximum Transmit Data Endpoint 3"
|
|
hexmask.word 0x0 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
line.word 0x2 "USBTXCSRL3,USB Transmit Control and Status Endpoint 3 Low"
|
|
bitfld.word 0x2 7. "NAKTO,NAK Timeout" "0,1"
|
|
bitfld.word 0x2 6. "CLRDT,Clear Data Toggle" "0,1"
|
|
bitfld.word 0x2 5. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x2 4. "STALL_SETUP,Send Stall/Setup Packet" "0,1"
|
|
bitfld.word 0x2 3. "FLUSH,Flush FIFO" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "UNDRNERROR3,Underun/Error" "0,1"
|
|
bitfld.word 0x2 1. "FIFONE,FIFO Not Empty" "0,1"
|
|
bitfld.word 0x2 0. "TXRDY,Transmit Packet Ready" "0,1"
|
|
line.word 0x3 "USBTXCSRH3,USB Transmit Control and Status Endpoint 3 High"
|
|
bitfld.word 0x3 7. "AUTOSET,Auto Set" "0,1"
|
|
bitfld.word 0x3 6. "ISO,Isochronous Transfers" "0,1"
|
|
bitfld.word 0x3 5. "MODE,Mode" "0,1"
|
|
bitfld.word 0x3 4. "DMAEN,DMA Request Enable" "0,1"
|
|
bitfld.word 0x3 3. "FDT,Force Data Toggle" "0,1"
|
|
newline
|
|
bitfld.word 0x3 2. "DMAMOD,DMA Request Mode" "0,1"
|
|
bitfld.word 0x3 1. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x3 0. "DT,Data Toggle" "0,1"
|
|
line.word 0x4 "USBRXMAXP3,USB Maximum Receive Data Endpoint 3"
|
|
hexmask.word 0x4 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
line.word 0x6 "USBRXCSRL3,USB Receive Control and Status Endpoint 3 Low"
|
|
bitfld.word 0x6 7. "CLRDT,Clear Data Toggle" "0,1"
|
|
bitfld.word 0x6 6. "STALLED,Endpoint Stalled" "0,1"
|
|
bitfld.word 0x6 5. "STALLREQPKT,Send Stall/Request Packet" "0,1"
|
|
bitfld.word 0x6 4. "FLUSH,Flush FIFO" "0,1"
|
|
bitfld.word 0x6 3. "DATAERRNAKTO,Data Error/NAK Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x6 2. "OVERERROR3,Overrun/Error" "0,1"
|
|
bitfld.word 0x6 1. "FULL,FIFO Full" "0,1"
|
|
bitfld.word 0x6 0. "RXRDY,Recieve Packet Ready" "0,1"
|
|
line.word 0x7 "USBRXCSRH3,USB Receive Control and Status Endpoint 3 High"
|
|
bitfld.word 0x7 7. "AUTOCL,Auto Clear" "0,1"
|
|
bitfld.word 0x7 6. "ISOAUTORQ,Isochronous Transfers/Auto Request" "0,1"
|
|
bitfld.word 0x7 5. "DMAEN,DMA Request Enable" "0,1"
|
|
bitfld.word 0x7 4. "DISNYETPIDERR,Disable NYET / PID Error" "0,1"
|
|
bitfld.word 0x7 3. "DMAMOD,DMA Request Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x7 2. "DTWE,Data Toggle Write Enable" "0,1"
|
|
bitfld.word 0x7 1. "DT,Data Toggle" "0,1"
|
|
rgroup.word 0x138++0x1
|
|
line.word 0x0 "USBRXCOUNT3,USB Receive Byte Count Endpoint 3"
|
|
hexmask.word 0x0 0.--12. 1. "COUNT,Receive Packet Count"
|
|
group.word 0x13A++0x7
|
|
line.word 0x0 "USBTXTYPE3,USB Host Transmit Configure Type Endpoint 3"
|
|
bitfld.word 0x0 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
bitfld.word 0x0 4.--5. "PROTO,Protocol" "0,1,2,3"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TEP,Target Endpoint Number"
|
|
line.word 0x1 "USBTXINTERVAL3,USB Host Transmit Interval Endpoint 3"
|
|
hexmask.word.byte 0x1 0.--7. 1. "TXPOLLNAKLMT,TX Polling / NAK Limit"
|
|
line.word 0x2 "USBRXTYPE3,USB Host Configure Receive Type Endpoint 3"
|
|
bitfld.word 0x2 6.--7. "SPEED,Operating Speed" "0,1,2,3"
|
|
bitfld.word 0x2 4.--5. "PROTO,Protocol" "0,1,2,3"
|
|
hexmask.word.byte 0x2 0.--3. 1. "TEP,Target Endpoint Number"
|
|
line.word 0x3 "USBRXINTERVAL3,USB Host Receive Polling Interval Endpoint 3"
|
|
hexmask.word.byte 0x3 0.--7. 1. "RXPOLLNAKLMT,RX Polling / NAK Limit"
|
|
group.word 0x304++0x1
|
|
line.word 0x0 "USBRQPKTCOUNT1,USB Request Packet Count in Block Transfer Endpoint 1"
|
|
hexmask.word 0x0 0.--12. 1. "COUNT,FIFO Count"
|
|
group.word 0x308++0x1
|
|
line.word 0x0 "USBRQPKTCOUNT2,USB Request Packet Count in Block Transfer Endpoint 2"
|
|
hexmask.word 0x0 0.--12. 1. "COUNT,FIFO Count"
|
|
group.word 0x30C++0x1
|
|
line.word 0x0 "USBRQPKTCOUNT3,USB Request Packet Count in Block Transfer Endpoint 3"
|
|
hexmask.word 0x0 0.--12. 1. "COUNT,FIFO Count"
|
|
rgroup.word 0x340++0x3
|
|
line.word 0x0 "USBRXDPKTBUFDIS,USB Receive Double Packet Buffer Disable"
|
|
bitfld.word 0x0 3. "EP3,EP3 RX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x0 2. "EP2,EP2 RX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x0 1. "EP1,EP1 RX Double Packet Buffer Disable" "0,1"
|
|
line.word 0x2 "USBTXDPKTBUFDIS,USB Transmit Double Packet Buffer Disable"
|
|
bitfld.word 0x2 3. "EP3,EP3 TX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x2 2. "EP2,EP2 TX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x2 1. "EP1,EP1 TX Double Packet Buffer Disable" "0,1"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "USBEPC,USB External Power Control"
|
|
bitfld.long 0x0 8.--9. "PFLTACT,Power Fault Action" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PFLTAEN,Power Fault Action Enable" "0,1"
|
|
bitfld.long 0x0 5. "PFLTSEN,Power Fault Sense" "0,1"
|
|
bitfld.long 0x0 4. "PFLTEN,Power Fault Input Enable" "0,1"
|
|
bitfld.long 0x0 2. "EPENDE,EPEN Drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EPEN,External Power Supply Enable Configuration" "0,1,2,3"
|
|
rgroup.long 0x404++0x13
|
|
line.long 0x0 "USBEPCRIS,USB External Power Control Raw Interrupt Status"
|
|
bitfld.long 0x0 0. "PF,Power Fault Interrupt Status" "0,1"
|
|
line.long 0x4 "USBEPCIM,USB External Power Control Interrupt Mask"
|
|
bitfld.long 0x4 0. "PF,Power Fault Interrupt Mask" "0,1"
|
|
line.long 0x8 "USBEPCISC,USB External Power Control Interrupt Status and Clear"
|
|
bitfld.long 0x8 0. "PF,Power Fault Interrupt Status and Clear" "0,1"
|
|
line.long 0xC "USBDRRIS,USB Device RESUME Raw Interrupt Status"
|
|
bitfld.long 0xC 0. "RESUME,Resume Interrupt Status" "0,1"
|
|
line.long 0x10 "USBDRIM,USB Device RESUME Interrupt Mask"
|
|
bitfld.long 0x10 0. "RESUME,Resume Interrupt Mask" "0,1"
|
|
group.long 0x418++0x7
|
|
line.long 0x0 "USBDRISC,USB Device RESUME Interrupt Status and Clear"
|
|
bitfld.long 0x0 0. "RESUME,Resume Interrupt Status and Clear" "0,1"
|
|
line.long 0x4 "USBGPCS,USB General-Purpose Control and Status"
|
|
bitfld.long 0x4 1. "DEVMODOTG,Enable Device Mode" "0,1"
|
|
bitfld.long 0x4 0. "DEVMOD,Device Mode" "0,1"
|
|
group.long 0x430++0x3
|
|
line.long 0x0 "USBVDC,USB VBUS Droop Control"
|
|
bitfld.long 0x0 0. "VBDEN,Vbus Droop Enable" "0,1"
|
|
rgroup.long 0x434++0x7
|
|
line.long 0x0 "USBVDCRIS,USB VBUS Droop Control Raw Interrupt Status"
|
|
bitfld.long 0x0 0. "VD,Vbus Droop Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "USBVDCIM,USB VBUS Droop Control Interrupt Mask"
|
|
bitfld.long 0x4 0. "VD,Vbus Droop Interrupt Mask" "0,1"
|
|
group.long 0x43C++0x3
|
|
line.long 0x0 "USBVDCISC,USB VBUS Droop Control Interrupt Status and Clear"
|
|
bitfld.long 0x0 0. "VD,Vbus Droop Interrupt Status and Clear" "0,1"
|
|
group.long 0x444++0xF
|
|
line.long 0x0 "USBIDVRIS,USB ID Valid Detect Raw Interrupt Status"
|
|
bitfld.long 0x0 0. "ID,ID Valid Detect Raw Interrupt Status" "0,1"
|
|
line.long 0x4 "USBIDVIM,USB ID Valid Detect Interrupt Mask"
|
|
bitfld.long 0x4 0. "ID,ID Valid Detect Interrupt mask" "0,1"
|
|
line.long 0x8 "USBIDVISC,USB ID Valid Detect Interrupt Status and Clear"
|
|
bitfld.long 0x8 0. "ID,ID Valid Detect Interrupt Status and Clear" "0,1"
|
|
line.long 0xC "USBDMASEL,USB DMA Select"
|
|
hexmask.long.byte 0xC 20.--23. 1. "DMACTX,DMA C TX Select"
|
|
hexmask.long.byte 0xC 16.--19. 1. "DMACRX,DMA C RX Select"
|
|
hexmask.long.byte 0xC 12.--15. 1. "DMABTX,DMA B TX Select"
|
|
hexmask.long.byte 0xC 8.--11. 1. "DMABRX,DMA B RX Select"
|
|
hexmask.long.byte 0xC 4.--7. 1. "DMAATX,DMA A TX Select"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "DMAARX,DMA A RX Select"
|
|
group.long 0x480++0xB
|
|
line.long 0x0 "USB_GLB_INT_EN,USB Global Interrupt Enable Register[[br]]Note: This Register is applicable only when USB is mapped to CPU1"
|
|
bitfld.long 0x0 0. "INTEN,Global Interrupt Enable" "0,1"
|
|
line.long 0x4 "USB_GLB_INT_FLG,USB Global Interrupt Flag Register[[br]]Note: This Register is applicable only when USB is mapped to CPU1"
|
|
bitfld.long 0x4 0. "INTFLG,Global Interrupt Flag" "0,1"
|
|
line.long 0x8 "USB_GLB_INT_FLG_CLR,USB Global Interrupt Flag Clear Register[[br]]Note: This Register is applicable only when USB is mapped to CPU1"
|
|
bitfld.long 0x8 0. "INTFLG,Global Interrupt Flag Clear" "0,1"
|
|
rgroup.long 0x500++0x3
|
|
line.long 0x0 "USBDMARIS,USB uDMA Raw Interrupt Status register.[[br]]Note: This Register is applicable only when USB is mapped to CM"
|
|
bitfld.long 0x0 5. "USB_DMAC_TX_DONE,DMA Tx done interrupt for DMAC" "0,1"
|
|
bitfld.long 0x0 4. "USB_DMAC_RX_DONE,DMA Rx done interrupt for DMAC" "0,1"
|
|
bitfld.long 0x0 3. "USB_DMAB_TX_DONE,DMA Tx done interrupt for DMAB" "0,1"
|
|
bitfld.long 0x0 2. "USB_DMAB_RX_DONE,DMA Rx done interrupt for DMAB" "0,1"
|
|
bitfld.long 0x0 1. "USB_DMAA_TX_DONE,DMA Tx done interrupt for DMAA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "USB_DMAA_Rx_DONE,DMA Rx done interrupt for DMAA" "0,1"
|
|
group.long 0x504++0x7
|
|
line.long 0x0 "USBDMAIM,USB uDMA Interrupt Mask Register[[br]]Note: This Register is applicable only when USB is mapped to CM"
|
|
bitfld.long 0x0 5. "USB_DMAC_TX_DONE,DMA Tx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x0 4. "USB_DMAC_RX_DONE,DMA Rx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x0 3. "USB_DMAB_TX_DONE,DMA Tx done interrupt mask for DMAB" "0,1"
|
|
bitfld.long 0x0 2. "USB_DMAB_RX_DONE,DMA Rx done interrupt mask for DMAB" "0,1"
|
|
bitfld.long 0x0 1. "USB_DMAA_TX_DONE,DMA Tx done interrupt mask for DMAA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "USB_DMAA_Rx_DONE,DMA Rx done interrupt mask for DMAA" "0,1"
|
|
line.long 0x4 "USBDMAISC,USB uDMA Interrupt Status and Clear Register[[br]]Note: This Register is applicable only when USB is mapped to CM"
|
|
bitfld.long 0x4 5. "USB_DMAC_TX_DONE,DMA Tx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x4 4. "USB_DMAC_RX_DONE,DMA Rx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x4 3. "USB_DMAB_TX_DONE,DMA Tx done interrupt mask for DMAB" "0,1"
|
|
bitfld.long 0x4 2. "USB_DMAB_RX_DONE,DMA Rx done interrupt mask for DMAB" "0,1"
|
|
bitfld.long 0x4 1. "USB_DMAA_TX_DONE,DMA Tx done interrupt mask for DMAA" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "USB_DMAA_Rx_DONE,DMA Rx done interrupt mask for DMAA" "0,1"
|
|
tree.end
|
|
tree "VCU (VCU Registers)"
|
|
base d:0x1200
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "VR0,General Purpose 32-bit registers"
|
|
line.long 0x2 "VR1,General Purpose 32-bit registers"
|
|
line.long 0x4 "VR2,General Purpose 32-bit registers"
|
|
line.long 0x6 "VR3,General Purpose 32-bit registers"
|
|
line.long 0x8 "VR4,General Purpose 32-bit registers"
|
|
line.long 0xA "VR5,General Purpose 32-bit registers"
|
|
line.long 0xC "VR6,General Purpose 32-bit registers"
|
|
line.long 0xE "VR7,General Purpose 32-bit registers"
|
|
line.long 0x10 "VR8,General Purpose 32-bit registers"
|
|
line.long 0x12 "VT0,Transition Bit register"
|
|
line.long 0x14 "VT1,Transition Bit register"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "VSTATUS,VCU Status Register"
|
|
bitfld.long 0x0 31. "CRCMSGFLIP,CRC message flip" "0,1"
|
|
bitfld.long 0x0 30. "DIVE,Divide by zero error" "0,1"
|
|
bitfld.long 0x0 27.--29. "K,Viterbi constraint length" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "GFORDER,Galois Field Polynomial Order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--23. 1. "GFPOLY,Galois Field Polynomial"
|
|
bitfld.long 0x0 15. "OPACK,Packing order of traceback bits" "0,1"
|
|
bitfld.long 0x0 14. "CPACK,Packing order[L:H]" "0,1"
|
|
bitfld.long 0x0 13. "OVRI,Imaginary party CMPY overflow" "0,1"
|
|
bitfld.long 0x0 12. "OVFR,General case overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RND,Rounding" "0,1"
|
|
bitfld.long 0x0 10. "SAT,Saturation" "0,1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "SHIFTL,Left shift modifier"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SHIFTR,Right shift modifier"
|
|
line.long 0x2 "VCRC,CRC Result register for un-secured memories"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "VCUREV,"
|
|
group.word 0x50++0x7F
|
|
line.word 0x0 "VSM0,Viterbi Decoding State Metric register"
|
|
line.word 0x1 "VSM1,Viterbi Decoding State Metric register"
|
|
line.word 0x2 "VSM2,Viterbi Decoding State Metric register"
|
|
line.word 0x3 "VSM3,Viterbi Decoding State Metric register"
|
|
line.word 0x4 "VSM4,Viterbi Decoding State Metric register"
|
|
line.word 0x5 "VSM5,Viterbi Decoding State Metric register"
|
|
line.word 0x6 "VSM6,Viterbi Decoding State Metric register"
|
|
line.word 0x7 "VSM7,Viterbi Decoding State Metric register"
|
|
line.word 0x8 "VSM8,Viterbi Decoding State Metric register"
|
|
line.word 0x9 "VSM9,Viterbi Decoding State Metric register"
|
|
line.word 0xA "VSM10,Viterbi Decoding State Metric register"
|
|
line.word 0xB "VSM11,Viterbi Decoding State Metric register"
|
|
line.word 0xC "VSM12,Viterbi Decoding State Metric register"
|
|
line.word 0xD "VSM13,Viterbi Decoding State Metric register"
|
|
line.word 0xE "VSM14,Viterbi Decoding State Metric register"
|
|
line.word 0xF "VSM15,Viterbi Decoding State Metric register"
|
|
line.word 0x10 "VSM16,Viterbi Decoding State Metric register"
|
|
line.word 0x11 "VSM17,Viterbi Decoding State Metric register"
|
|
line.word 0x12 "VSM18,Viterbi Decoding State Metric register"
|
|
line.word 0x13 "VSM19,Viterbi Decoding State Metric register"
|
|
line.word 0x14 "VSM20,Viterbi Decoding State Metric register"
|
|
line.word 0x15 "VSM21,Viterbi Decoding State Metric register"
|
|
line.word 0x16 "VSM22,Viterbi Decoding State Metric register"
|
|
line.word 0x17 "VSM23,Viterbi Decoding State Metric register"
|
|
line.word 0x18 "VSM24,Viterbi Decoding State Metric register"
|
|
line.word 0x19 "VSM25,Viterbi Decoding State Metric register"
|
|
line.word 0x1A "VSM26,Viterbi Decoding State Metric register"
|
|
line.word 0x1B "VSM27,Viterbi Decoding State Metric register"
|
|
line.word 0x1C "VSM28,Viterbi Decoding State Metric register"
|
|
line.word 0x1D "VSM29,Viterbi Decoding State Metric register"
|
|
line.word 0x1E "VSM30,Viterbi Decoding State Metric register"
|
|
line.word 0x1F "VSM31,Viterbi Decoding State Metric register"
|
|
line.word 0x20 "VSM32,Viterbi Decoding State Metric register"
|
|
line.word 0x21 "VSM33,Viterbi Decoding State Metric register"
|
|
line.word 0x22 "VSM34,Viterbi Decoding State Metric register"
|
|
line.word 0x23 "VSM35,Viterbi Decoding State Metric register"
|
|
line.word 0x24 "VSM36,Viterbi Decoding State Metric register"
|
|
line.word 0x25 "VSM37,Viterbi Decoding State Metric register"
|
|
line.word 0x26 "VSM38,Viterbi Decoding State Metric register"
|
|
line.word 0x27 "VSM39,Viterbi Decoding State Metric register"
|
|
line.word 0x28 "VSM40,Viterbi Decoding State Metric register"
|
|
line.word 0x29 "VSM41,Viterbi Decoding State Metric register"
|
|
line.word 0x2A "VSM42,Viterbi Decoding State Metric register"
|
|
line.word 0x2B "VSM43,Viterbi Decoding State Metric register"
|
|
line.word 0x2C "VSM44,Viterbi Decoding State Metric register"
|
|
line.word 0x2D "VSM45,Viterbi Decoding State Metric register"
|
|
line.word 0x2E "VSM46,Viterbi Decoding State Metric register"
|
|
line.word 0x2F "VSM47,Viterbi Decoding State Metric register"
|
|
line.word 0x30 "VSM48,Viterbi Decoding State Metric register"
|
|
line.word 0x31 "VSM49,Viterbi Decoding State Metric register"
|
|
line.word 0x32 "VSM50,Viterbi Decoding State Metric register"
|
|
line.word 0x33 "VSM51,Viterbi Decoding State Metric register"
|
|
line.word 0x34 "VSM52,Viterbi Decoding State Metric register"
|
|
line.word 0x35 "VSM53,Viterbi Decoding State Metric register"
|
|
line.word 0x36 "VSM54,Viterbi Decoding State Metric register"
|
|
line.word 0x37 "VSM55,Viterbi Decoding State Metric register"
|
|
line.word 0x38 "VSM56,Viterbi Decoding State Metric register"
|
|
line.word 0x39 "VSM57,Viterbi Decoding State Metric register"
|
|
line.word 0x3A "VSM58,Viterbi Decoding State Metric register"
|
|
line.word 0x3B "VSM59,Viterbi Decoding State Metric register"
|
|
line.word 0x3C "VSM60,Viterbi Decoding State Metric register"
|
|
line.word 0x3D "VSM61,Viterbi Decoding State Metric register"
|
|
line.word 0x3E "VSM62,Viterbi Decoding State Metric register"
|
|
line.word 0x3F "VSM63,Viterbi Decoding State Metric register"
|
|
group.long 0xB0++0x7F
|
|
line.long 0x0 "VR0_B0,"
|
|
line.long 0x2 "VR0_B1,"
|
|
line.long 0x4 "VR0_B2,"
|
|
line.long 0x6 "VR0_B3,"
|
|
line.long 0x8 "VR1_B0,"
|
|
line.long 0xA "VR1_B1,"
|
|
line.long 0xC "VR1_B2,"
|
|
line.long 0xE "VR1_B3,"
|
|
line.long 0x10 "VR2_B0,"
|
|
line.long 0x12 "VR2_B1,"
|
|
line.long 0x14 "VR2_B2,"
|
|
line.long 0x16 "VR2_B3,"
|
|
line.long 0x18 "VR3_B0,"
|
|
line.long 0x1A "VR3_B1,"
|
|
line.long 0x1C "VR3_B2,"
|
|
line.long 0x1E "VR3_B3,"
|
|
line.long 0x20 "VR4_B0,"
|
|
line.long 0x22 "VR4_B1,"
|
|
line.long 0x24 "VR4_B2,"
|
|
line.long 0x26 "VR4_B3,"
|
|
line.long 0x28 "VR5_B0,"
|
|
line.long 0x2A "VR5_B1,"
|
|
line.long 0x2C "VR5_B2,"
|
|
line.long 0x2E "VR5_B3,"
|
|
line.long 0x30 "VR6_B0,"
|
|
line.long 0x32 "VR6_B1,"
|
|
line.long 0x34 "VR6_B2,"
|
|
line.long 0x36 "VR6_B3,"
|
|
line.long 0x38 "VR7_B0,"
|
|
line.long 0x3A "VR7_B1,"
|
|
line.long 0x3C "VR7_B2,"
|
|
line.long 0x3E "VR7_B3,"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F28386?")||cpuis("F28388?")||cpuis("F2838??"))
|
|
tree "XBAR (Crossbar)"
|
|
base d:0x0
|
|
sif (cpuis("F2838??"))
|
|
tree "EPWMXBAR"
|
|
base d:0x7A00
|
|
group.long 0x0++0x5F
|
|
line.long 0x0 "TRIP4MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP4"
|
|
bitfld.long 0x0 30.--31. "MUX15,Mux15 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MUX14,Mux14 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MUX13,Mux13 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MUX12,Mux12 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MUX11,Mux11 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MUX10,Mux10 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MUX9,Mux9 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MUX8,Mux8 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MUX7,Mux7 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MUX6,Mux6 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MUX5,Mux5 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MUX4,Mux4 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MUX3,Mux3 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MUX2,Mux2 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MUX1,Mux1 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MUX0,Mux0 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x2 "TRIP4MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP4"
|
|
bitfld.long 0x2 30.--31. "MUX31,Mux31 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "MUX30,Mux30 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "MUX29,Mux29 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "MUX28,Mux28 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "MUX27,Mux27 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "MUX26,Mux26 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "MUX25,Mux25 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "MUX24,Mux24 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "MUX23,Mux23 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "MUX22,Mux22 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 10.--11. "MUX21,Mux21 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "MUX20,Mux20 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 6.--7. "MUX19,Mux19 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "MUX18,Mux18 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "MUX17,Mux17 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "MUX16,Mux16 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x4 "TRIP5MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP5"
|
|
bitfld.long 0x4 30.--31. "MUX15,Mux15 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "MUX14,Mux14 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "MUX13,Mux13 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "MUX12,Mux12 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "MUX11,Mux11 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "MUX10,Mux10 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "MUX9,Mux9 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "MUX8,Mux8 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "MUX7,Mux7 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "MUX6,Mux6 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "MUX5,Mux5 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "MUX4,Mux4 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "MUX3,Mux3 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "MUX2,Mux2 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "MUX1,Mux1 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "MUX0,Mux0 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x6 "TRIP5MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP5"
|
|
bitfld.long 0x6 30.--31. "MUX31,Mux31 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "MUX30,Mux30 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "MUX29,Mux29 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "MUX28,Mux28 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "MUX27,Mux27 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "MUX26,Mux26 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "MUX25,Mux25 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "MUX24,Mux24 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "MUX23,Mux23 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "MUX22,Mux22 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 10.--11. "MUX21,Mux21 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "MUX20,Mux20 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 6.--7. "MUX19,Mux19 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "MUX18,Mux18 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "MUX17,Mux17 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "MUX16,Mux16 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x8 "TRIP7MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP7"
|
|
bitfld.long 0x8 30.--31. "MUX15,Mux15 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "MUX14,Mux14 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "MUX13,Mux13 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "MUX12,Mux12 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "MUX11,Mux11 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "MUX10,Mux10 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "MUX9,Mux9 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "MUX8,Mux8 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "MUX7,Mux7 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "MUX6,Mux6 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "MUX5,Mux5 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "MUX4,Mux4 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "MUX3,Mux3 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "MUX2,Mux2 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "MUX1,Mux1 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "MUX0,Mux0 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0xA "TRIP7MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP7"
|
|
bitfld.long 0xA 30.--31. "MUX31,Mux31 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "MUX30,Mux30 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "MUX29,Mux29 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "MUX28,Mux28 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "MUX27,Mux27 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "MUX26,Mux26 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "MUX25,Mux25 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "MUX24,Mux24 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "MUX23,Mux23 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "MUX22,Mux22 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "MUX21,Mux21 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "MUX20,Mux20 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 6.--7. "MUX19,Mux19 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "MUX18,Mux18 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "MUX17,Mux17 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "MUX16,Mux16 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0xC "TRIP8MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP8"
|
|
bitfld.long 0xC 30.--31. "MUX15,Mux15 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "MUX14,Mux14 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "MUX13,Mux13 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "MUX12,Mux12 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "MUX11,Mux11 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "MUX10,Mux10 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "MUX9,Mux9 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "MUX8,Mux8 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "MUX7,Mux7 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "MUX6,Mux6 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "MUX5,Mux5 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "MUX4,Mux4 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "MUX3,Mux3 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "MUX2,Mux2 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "MUX1,Mux1 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "MUX0,Mux0 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0xE "TRIP8MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP8"
|
|
bitfld.long 0xE 30.--31. "MUX31,Mux31 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 28.--29. "MUX30,Mux30 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 26.--27. "MUX29,Mux29 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 24.--25. "MUX28,Mux28 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 22.--23. "MUX27,Mux27 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 20.--21. "MUX26,Mux26 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 18.--19. "MUX25,Mux25 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 16.--17. "MUX24,Mux24 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 14.--15. "MUX23,Mux23 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 12.--13. "MUX22,Mux22 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 10.--11. "MUX21,Mux21 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 8.--9. "MUX20,Mux20 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xE 6.--7. "MUX19,Mux19 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 4.--5. "MUX18,Mux18 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 2.--3. "MUX17,Mux17 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 0.--1. "MUX16,Mux16 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x10 "TRIP9MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP9"
|
|
bitfld.long 0x10 30.--31. "MUX15,Mux15 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "MUX14,Mux14 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "MUX13,Mux13 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "MUX12,Mux12 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "MUX11,Mux11 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "MUX10,Mux10 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "MUX9,Mux9 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "MUX8,Mux8 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "MUX7,Mux7 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "MUX6,Mux6 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "MUX5,Mux5 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "MUX4,Mux4 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "MUX3,Mux3 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "MUX2,Mux2 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "MUX1,Mux1 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "MUX0,Mux0 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x12 "TRIP9MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP9"
|
|
bitfld.long 0x12 30.--31. "MUX31,Mux31 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 28.--29. "MUX30,Mux30 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 26.--27. "MUX29,Mux29 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 24.--25. "MUX28,Mux28 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 22.--23. "MUX27,Mux27 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 20.--21. "MUX26,Mux26 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 18.--19. "MUX25,Mux25 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 16.--17. "MUX24,Mux24 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 14.--15. "MUX23,Mux23 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 12.--13. "MUX22,Mux22 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 10.--11. "MUX21,Mux21 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 8.--9. "MUX20,Mux20 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x12 6.--7. "MUX19,Mux19 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 4.--5. "MUX18,Mux18 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 2.--3. "MUX17,Mux17 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 0.--1. "MUX16,Mux16 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x14 "TRIP10MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP10"
|
|
bitfld.long 0x14 30.--31. "MUX15,Mux15 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "MUX14,Mux14 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "MUX13,Mux13 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "MUX12,Mux12 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "MUX11,Mux11 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "MUX10,Mux10 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "MUX9,Mux9 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "MUX8,Mux8 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "MUX7,Mux7 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "MUX6,Mux6 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "MUX5,Mux5 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. "MUX4,Mux4 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "MUX3,Mux3 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "MUX2,Mux2 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "MUX1,Mux1 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "MUX0,Mux0 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x16 "TRIP10MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP10"
|
|
bitfld.long 0x16 30.--31. "MUX31,Mux31 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 28.--29. "MUX30,Mux30 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 26.--27. "MUX29,Mux29 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 24.--25. "MUX28,Mux28 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 22.--23. "MUX27,Mux27 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 20.--21. "MUX26,Mux26 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 18.--19. "MUX25,Mux25 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 16.--17. "MUX24,Mux24 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 14.--15. "MUX23,Mux23 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 12.--13. "MUX22,Mux22 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 10.--11. "MUX21,Mux21 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 8.--9. "MUX20,Mux20 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x16 6.--7. "MUX19,Mux19 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 4.--5. "MUX18,Mux18 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 2.--3. "MUX17,Mux17 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 0.--1. "MUX16,Mux16 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x18 "TRIP11MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP11"
|
|
bitfld.long 0x18 30.--31. "MUX15,Mux15 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "MUX14,Mux14 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "MUX13,Mux13 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "MUX12,Mux12 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "MUX11,Mux11 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "MUX10,Mux10 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "MUX9,Mux9 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "MUX8,Mux8 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "MUX7,Mux7 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "MUX6,Mux6 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "MUX5,Mux5 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "MUX4,Mux4 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 6.--7. "MUX3,Mux3 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "MUX2,Mux2 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "MUX1,Mux1 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "MUX0,Mux0 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x1A "TRIP11MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP11"
|
|
bitfld.long 0x1A 30.--31. "MUX31,Mux31 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 28.--29. "MUX30,Mux30 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 26.--27. "MUX29,Mux29 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 24.--25. "MUX28,Mux28 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 22.--23. "MUX27,Mux27 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 20.--21. "MUX26,Mux26 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 18.--19. "MUX25,Mux25 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 16.--17. "MUX24,Mux24 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 14.--15. "MUX23,Mux23 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 12.--13. "MUX22,Mux22 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 10.--11. "MUX21,Mux21 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 8.--9. "MUX20,Mux20 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1A 6.--7. "MUX19,Mux19 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 4.--5. "MUX18,Mux18 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 2.--3. "MUX17,Mux17 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 0.--1. "MUX16,Mux16 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x1C "TRIP12MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP12"
|
|
bitfld.long 0x1C 30.--31. "MUX15,Mux15 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 28.--29. "MUX14,Mux14 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 26.--27. "MUX13,Mux13 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--25. "MUX12,Mux12 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. "MUX11,Mux11 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--21. "MUX10,Mux10 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 18.--19. "MUX9,Mux9 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 16.--17. "MUX8,Mux8 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. "MUX7,Mux7 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. "MUX6,Mux6 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 10.--11. "MUX5,Mux5 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--9. "MUX4,Mux4 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 6.--7. "MUX3,Mux3 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 4.--5. "MUX2,Mux2 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 2.--3. "MUX1,Mux1 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 0.--1. "MUX0,Mux0 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x1E "TRIP12MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP12"
|
|
bitfld.long 0x1E 30.--31. "MUX31,Mux31 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 28.--29. "MUX30,Mux30 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 26.--27. "MUX29,Mux29 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 24.--25. "MUX28,Mux28 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 22.--23. "MUX27,Mux27 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 20.--21. "MUX26,Mux26 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 18.--19. "MUX25,Mux25 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 16.--17. "MUX24,Mux24 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 14.--15. "MUX23,Mux23 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 12.--13. "MUX22,Mux22 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 10.--11. "MUX21,Mux21 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 8.--9. "MUX20,Mux20 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1E 6.--7. "MUX19,Mux19 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 4.--5. "MUX18,Mux18 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 2.--3. "MUX17,Mux17 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 0.--1. "MUX16,Mux16 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
line.long 0x20 "TRIP4MUXENABLE,ePWM XBAR Mux Enable for TRIP4"
|
|
bitfld.long 0x20 31. "MUX31,Mux31 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 30. "MUX30,Mux30 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 29. "MUX29,Mux29 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 28. "MUX28,Mux28 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 27. "MUX27,Mux27 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 26. "MUX26,Mux26 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 25. "MUX25,Mux25 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 24. "MUX24,Mux24 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 23. "MUX23,Mux23 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 22. "MUX22,Mux22 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 21. "MUX21,Mux21 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 20. "MUX20,Mux20 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x20 19. "MUX19,Mux19 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 18. "MUX18,Mux18 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 17. "MUX17,Mux17 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 16. "MUX16,Mux16 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 15. "MUX15,Mux15 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 14. "MUX14,Mux14 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 13. "MUX13,Mux13 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 12. "MUX12,Mux12 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 11. "MUX11,Mux11 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 10. "MUX10,Mux10 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 9. "MUX9,Mux9 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 8. "MUX8,Mux8 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "MUX7,Mux7 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 6. "MUX6,Mux6 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 5. "MUX5,Mux5 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 4. "MUX4,Mux4 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 3. "MUX3,Mux3 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 2. "MUX2,Mux2 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 1. "MUX1,Mux1 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x20 0. "MUX0,mux0 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
line.long 0x22 "TRIP5MUXENABLE,ePWM XBAR Mux Enable for TRIP5"
|
|
bitfld.long 0x22 31. "MUX31,Mux31 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 30. "MUX30,Mux30 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 29. "MUX29,Mux29 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 28. "MUX28,Mux28 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 27. "MUX27,Mux27 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 26. "MUX26,Mux26 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 25. "MUX25,Mux25 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 24. "MUX24,Mux24 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 23. "MUX23,Mux23 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 22. "MUX22,Mux22 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 21. "MUX21,Mux21 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 20. "MUX20,Mux20 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x22 19. "MUX19,Mux19 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 18. "MUX18,Mux18 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 17. "MUX17,Mux17 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 16. "MUX16,Mux16 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 15. "MUX15,Mux15 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 14. "MUX14,Mux14 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 13. "MUX13,Mux13 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 12. "MUX12,Mux12 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 11. "MUX11,Mux11 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 10. "MUX10,Mux10 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 9. "MUX9,Mux9 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 8. "MUX8,Mux8 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x22 7. "MUX7,Mux7 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 6. "MUX6,Mux6 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 5. "MUX5,Mux5 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 4. "MUX4,Mux4 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 3. "MUX3,Mux3 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 2. "MUX2,Mux2 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 1. "MUX1,Mux1 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x22 0. "MUX0,mux0 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
line.long 0x24 "TRIP7MUXENABLE,ePWM XBAR Mux Enable for TRIP7"
|
|
bitfld.long 0x24 31. "MUX31,Mux31 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 30. "MUX30,Mux30 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 29. "MUX29,Mux29 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 28. "MUX28,Mux28 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 27. "MUX27,Mux27 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 26. "MUX26,Mux26 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 25. "MUX25,Mux25 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 24. "MUX24,Mux24 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 23. "MUX23,Mux23 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 22. "MUX22,Mux22 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 21. "MUX21,Mux21 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 20. "MUX20,Mux20 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x24 19. "MUX19,Mux19 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 18. "MUX18,Mux18 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 17. "MUX17,Mux17 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 16. "MUX16,Mux16 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 15. "MUX15,Mux15 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 14. "MUX14,Mux14 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 13. "MUX13,Mux13 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 12. "MUX12,Mux12 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 11. "MUX11,Mux11 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 10. "MUX10,Mux10 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 9. "MUX9,Mux9 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 8. "MUX8,Mux8 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "MUX7,Mux7 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 6. "MUX6,Mux6 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 5. "MUX5,Mux5 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 4. "MUX4,Mux4 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 3. "MUX3,Mux3 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 2. "MUX2,Mux2 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 1. "MUX1,Mux1 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x24 0. "MUX0,mux0 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
line.long 0x26 "TRIP8MUXENABLE,ePWM XBAR Mux Enable for TRIP8"
|
|
bitfld.long 0x26 31. "MUX31,Mux31 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 30. "MUX30,Mux30 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 29. "MUX29,Mux29 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 28. "MUX28,Mux28 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 27. "MUX27,Mux27 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 26. "MUX26,Mux26 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 25. "MUX25,Mux25 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 24. "MUX24,Mux24 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 23. "MUX23,Mux23 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 22. "MUX22,Mux22 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 21. "MUX21,Mux21 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 20. "MUX20,Mux20 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x26 19. "MUX19,Mux19 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 18. "MUX18,Mux18 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 17. "MUX17,Mux17 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 16. "MUX16,Mux16 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 15. "MUX15,Mux15 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 14. "MUX14,Mux14 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 13. "MUX13,Mux13 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 12. "MUX12,Mux12 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 11. "MUX11,Mux11 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 10. "MUX10,Mux10 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 9. "MUX9,Mux9 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 8. "MUX8,Mux8 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x26 7. "MUX7,Mux7 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 6. "MUX6,Mux6 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 5. "MUX5,Mux5 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 4. "MUX4,Mux4 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 3. "MUX3,Mux3 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 2. "MUX2,Mux2 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 1. "MUX1,Mux1 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x26 0. "MUX0,mux0 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
line.long 0x28 "TRIP9MUXENABLE,ePWM XBAR Mux Enable for TRIP9"
|
|
bitfld.long 0x28 31. "MUX31,Mux31 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 30. "MUX30,Mux30 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 29. "MUX29,Mux29 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 28. "MUX28,Mux28 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 27. "MUX27,Mux27 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 26. "MUX26,Mux26 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 25. "MUX25,Mux25 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 24. "MUX24,Mux24 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 23. "MUX23,Mux23 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 22. "MUX22,Mux22 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 21. "MUX21,Mux21 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 20. "MUX20,Mux20 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x28 19. "MUX19,Mux19 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 18. "MUX18,Mux18 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 17. "MUX17,Mux17 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 16. "MUX16,Mux16 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 15. "MUX15,Mux15 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 14. "MUX14,Mux14 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 13. "MUX13,Mux13 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 12. "MUX12,Mux12 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 11. "MUX11,Mux11 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 10. "MUX10,Mux10 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 9. "MUX9,Mux9 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 8. "MUX8,Mux8 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x28 7. "MUX7,Mux7 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 6. "MUX6,Mux6 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 5. "MUX5,Mux5 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 4. "MUX4,Mux4 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 3. "MUX3,Mux3 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 2. "MUX2,Mux2 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 1. "MUX1,Mux1 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x28 0. "MUX0,mux0 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
line.long 0x2A "TRIP10MUXENABLE,ePWM XBAR Mux Enable for TRIP10"
|
|
bitfld.long 0x2A 31. "MUX31,Mux31 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 30. "MUX30,Mux30 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 29. "MUX29,Mux29 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 28. "MUX28,Mux28 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 27. "MUX27,Mux27 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 26. "MUX26,Mux26 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 25. "MUX25,Mux25 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 24. "MUX24,Mux24 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 23. "MUX23,Mux23 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 22. "MUX22,Mux22 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 21. "MUX21,Mux21 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 20. "MUX20,Mux20 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2A 19. "MUX19,Mux19 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 18. "MUX18,Mux18 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 17. "MUX17,Mux17 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 16. "MUX16,Mux16 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 15. "MUX15,Mux15 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 14. "MUX14,Mux14 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 13. "MUX13,Mux13 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 12. "MUX12,Mux12 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 11. "MUX11,Mux11 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 10. "MUX10,Mux10 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 9. "MUX9,Mux9 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 8. "MUX8,Mux8 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2A 7. "MUX7,Mux7 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 6. "MUX6,Mux6 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 5. "MUX5,Mux5 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 4. "MUX4,Mux4 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 3. "MUX3,Mux3 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 2. "MUX2,Mux2 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 1. "MUX1,Mux1 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2A 0. "MUX0,mux0 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
line.long 0x2C "TRIP11MUXENABLE,ePWM XBAR Mux Enable for TRIP11"
|
|
bitfld.long 0x2C 31. "MUX31,Mux31 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 30. "MUX30,Mux30 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 29. "MUX29,Mux29 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 28. "MUX28,Mux28 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 27. "MUX27,Mux27 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 26. "MUX26,Mux26 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 25. "MUX25,Mux25 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 24. "MUX24,Mux24 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 23. "MUX23,Mux23 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 22. "MUX22,Mux22 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 21. "MUX21,Mux21 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 20. "MUX20,Mux20 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 19. "MUX19,Mux19 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 18. "MUX18,Mux18 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 17. "MUX17,Mux17 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 16. "MUX16,Mux16 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 15. "MUX15,Mux15 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 14. "MUX14,Mux14 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 13. "MUX13,Mux13 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 12. "MUX12,Mux12 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 11. "MUX11,Mux11 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 10. "MUX10,Mux10 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 9. "MUX9,Mux9 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 8. "MUX8,Mux8 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 7. "MUX7,Mux7 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 6. "MUX6,Mux6 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 5. "MUX5,Mux5 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 4. "MUX4,Mux4 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 3. "MUX3,Mux3 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 2. "MUX2,Mux2 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 1. "MUX1,Mux1 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2C 0. "MUX0,mux0 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
line.long 0x2E "TRIP12MUXENABLE,ePWM XBAR Mux Enable for TRIP12"
|
|
bitfld.long 0x2E 31. "MUX31,Mux31 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 30. "MUX30,Mux30 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 29. "MUX29,Mux29 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 28. "MUX28,Mux28 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 27. "MUX27,Mux27 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 26. "MUX26,Mux26 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 25. "MUX25,Mux25 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 24. "MUX24,Mux24 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 23. "MUX23,Mux23 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 22. "MUX22,Mux22 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 21. "MUX21,Mux21 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 20. "MUX20,Mux20 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2E 19. "MUX19,Mux19 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 18. "MUX18,Mux18 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 17. "MUX17,Mux17 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 16. "MUX16,Mux16 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 15. "MUX15,Mux15 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 14. "MUX14,Mux14 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 13. "MUX13,Mux13 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 12. "MUX12,Mux12 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 11. "MUX11,Mux11 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 10. "MUX10,Mux10 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 9. "MUX9,Mux9 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 8. "MUX8,Mux8 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2E 7. "MUX7,Mux7 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 6. "MUX6,Mux6 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 5. "MUX5,Mux5 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 4. "MUX4,Mux4 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 3. "MUX3,Mux3 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 2. "MUX2,Mux2 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 1. "MUX1,Mux1 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x2E 0. "MUX0,mux0 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "TRIPOUTINV,ePWM XBAR Output Inversion Register"
|
|
bitfld.long 0x0 7. "TRIP12,Selects polarity for TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 6. "TRIP11,Selects polarity for TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 5. "TRIP10,Selects polarity for TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 4. "TRIP9,Selects polarity for TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 3. "TRIP8,Selects polarity for TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 2. "TRIP7,Selects polarity for TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 1. "TRIP5,Selects polarity for TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x0 0. "TRIP4,Selects polarity for TRIP4 of EPWM-XBAR" "0,1"
|
|
group.long 0x3E++0x3
|
|
line.long 0x0 "TRIPLOCK,ePWM XBAR Configuration Lock register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Write protection KEY"
|
|
bitfld.long 0x0 0. "LOCK,Locks the configuration for EPWM-XBAR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "INPUTXBAR1"
|
|
base d:0x7900
|
|
group.word 0x0++0x1F
|
|
line.word 0x0 "INPUT1SELECT,INPUT1 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x0 0.--15. 1. "SELECT,Select GPIO for INPUT1 signal"
|
|
line.word 0x1 "INPUT2SELECT,INPUT2 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x1 0.--15. 1. "SELECT,Select GPIO for INPUT2 signal"
|
|
line.word 0x2 "INPUT3SELECT,INPUT3 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x2 0.--15. 1. "SELECT,Select GPIO for INPUT3 signal"
|
|
line.word 0x3 "INPUT4SELECT,INPUT4 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x3 0.--15. 1. "SELECT,Select GPIO for INPUT4 signal"
|
|
line.word 0x4 "INPUT5SELECT,INPUT5 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x4 0.--15. 1. "SELECT,Select GPIO for INPUT5 signal"
|
|
line.word 0x5 "INPUT6SELECT,INPUT6 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x5 0.--15. 1. "SELECT,Select GPIO for INPUT6 signal"
|
|
line.word 0x6 "INPUT7SELECT,INPUT7 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x6 0.--15. 1. "SELECT,Select GPIO for INPUT7 signal"
|
|
line.word 0x7 "INPUT8SELECT,INPUT8 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x7 0.--15. 1. "SELECT,Select GPIO for INPUT8 signal"
|
|
line.word 0x8 "INPUT9SELECT,INPUT9 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x8 0.--15. 1. "SELECT,Select GPIO for INPUT9 signal"
|
|
line.word 0x9 "INPUT10SELECT,INPUT10 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0x9 0.--15. 1. "SELECT,Select GPIO for INPUT10 signal"
|
|
line.word 0xA "INPUT11SELECT,INPUT11 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0xA 0.--15. 1. "SELECT,Select GPIO for INPUT11 signal"
|
|
line.word 0xB "INPUT12SELECT,INPUT12 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0xB 0.--15. 1. "SELECT,Select GPIO for INPUT12 signal"
|
|
line.word 0xC "INPUT13SELECT,INPUT13 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0xC 0.--15. 1. "SELECT,Select GPIO for INPUT13 signal"
|
|
line.word 0xD "INPUT14SELECT,INPUT14 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0xD 0.--15. 1. "SELECT,Select GPIO for INPUT14 signal"
|
|
line.word 0xE "INPUT15SELECT,INPUT15 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0xE 0.--15. 1. "SELECT,Select GPIO for INPUT15 signal"
|
|
line.word 0xF "INPUT16SELECT,INPUT16 Input Select Register (GPIO0 to x)"
|
|
hexmask.word 0xF 0.--15. 1. "SELECT,Select GPIO for INPUT16 signal"
|
|
group.long 0x1E++0x3
|
|
line.long 0x0 "INPUTSELECTLOCK,Input Select Lock Register"
|
|
bitfld.long 0x0 15. "INPUT16SELECT,Lock bit for INPUT16SELECT Register" "0,1"
|
|
bitfld.long 0x0 14. "INPUT15SELECT,Lock bit for INPUT15SELECT Register" "0,1"
|
|
bitfld.long 0x0 13. "INPUT14SELECT,Lock bit for INPUT14SELECT Register" "0,1"
|
|
bitfld.long 0x0 12. "INPUT13SELECT,Lock bit for INPUT13SELECT Register" "0,1"
|
|
bitfld.long 0x0 11. "INPUT12SELECT,Lock bit for INPUT12SELECT Register" "0,1"
|
|
bitfld.long 0x0 10. "INPUT11SELECT,Lock bit for INPUT11SELECT Register" "0,1"
|
|
bitfld.long 0x0 9. "INPUT10SELECT,Lock bit for INPUT10SELECT Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "INPUT9SELECT,Lock bit for INPUT9SELECT Register" "0,1"
|
|
bitfld.long 0x0 7. "INPUT8SELECT,Lock bit for INPUT8SELECT Register" "0,1"
|
|
bitfld.long 0x0 6. "INPUT7SELECT,Lock bit for INPUT7SELECT Register" "0,1"
|
|
bitfld.long 0x0 5. "INPUT6SELECT,Lock bit for INPUT6SELECT Register" "0,1"
|
|
bitfld.long 0x0 4. "INPUT5SELECT,Lock bit for INPUT5SELECT Register" "0,1"
|
|
bitfld.long 0x0 3. "INPUT4SELECT,Lock bit for INPUT4SELECT Register" "0,1"
|
|
bitfld.long 0x0 2. "INPUT3SELECT,Lock bit for INPUT3SELECT Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INPUT2SELECT,Lock bit for INPUT2SELECT Register" "0,1"
|
|
bitfld.long 0x0 0. "INPUT1SELECT,Lock bit for INPUT1SELECT Register" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "OUTPUTXBAR1"
|
|
base d:0x7A80
|
|
group.long 0x0++0x5F
|
|
line.long 0x0 "OUTPUT1MUX0TO15CFG,Output X-BAR Mux Configuration for Output 1"
|
|
bitfld.long 0x0 30.--31. "MUX15,Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MUX14,Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MUX13,Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MUX12,Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MUX11,Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MUX10,Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MUX9,Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MUX8,Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MUX7,Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MUX6,Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MUX5,Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "MUX4,Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MUX3,Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MUX2,Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MUX1,Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MUX0,Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x2 "OUTPUT1MUX16TO31CFG,Output X-BAR Mux Configuration for Output 1"
|
|
bitfld.long 0x2 30.--31. "MUX31,Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "MUX30,Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "MUX29,Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "MUX28,Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "MUX27,Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "MUX26,Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "MUX25,Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "MUX24,Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "MUX23,Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "MUX22,Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 10.--11. "MUX21,Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 8.--9. "MUX20,Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "MUX19,Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 4.--5. "MUX18,Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "MUX17,Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "MUX16,Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x4 "OUTPUT2MUX0TO15CFG,Output X-BAR Mux Configuration for Output 2"
|
|
bitfld.long 0x4 30.--31. "MUX15,Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "MUX14,Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "MUX13,Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "MUX12,Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "MUX11,Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "MUX10,Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "MUX9,Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "MUX8,Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "MUX7,Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "MUX6,Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "MUX5,Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "MUX4,Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "MUX3,Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "MUX2,Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "MUX1,Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "MUX0,Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x6 "OUTPUT2MUX16TO31CFG,Output X-BAR Mux Configuration for Output 2"
|
|
bitfld.long 0x6 30.--31. "MUX31,Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "MUX30,Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "MUX29,Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "MUX28,Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "MUX27,Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "MUX26,Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "MUX25,Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "MUX24,Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "MUX23,Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "MUX22,Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 10.--11. "MUX21,Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 8.--9. "MUX20,Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "MUX19,Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 4.--5. "MUX18,Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "MUX17,Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "MUX16,Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x8 "OUTPUT3MUX0TO15CFG,Output X-BAR Mux Configuration for Output 3"
|
|
bitfld.long 0x8 30.--31. "MUX15,Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "MUX14,Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "MUX13,Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "MUX12,Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "MUX11,Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "MUX10,Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "MUX9,Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "MUX8,Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "MUX7,Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "MUX6,Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "MUX5,Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "MUX4,Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "MUX3,Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "MUX2,Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "MUX1,Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "MUX0,Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0xA "OUTPUT3MUX16TO31CFG,Output X-BAR Mux Configuration for Output 3"
|
|
bitfld.long 0xA 30.--31. "MUX31,Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "MUX30,Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "MUX29,Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "MUX28,Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "MUX27,Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "MUX26,Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "MUX25,Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "MUX24,Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "MUX23,Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "MUX22,Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "MUX21,Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xA 8.--9. "MUX20,Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "MUX19,Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 4.--5. "MUX18,Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "MUX17,Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "MUX16,Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0xC "OUTPUT4MUX0TO15CFG,Output X-BAR Mux Configuration for Output 4"
|
|
bitfld.long 0xC 30.--31. "MUX15,Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "MUX14,Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "MUX13,Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "MUX12,Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "MUX11,Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "MUX10,Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "MUX9,Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "MUX8,Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "MUX7,Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "MUX6,Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "MUX5,Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "MUX4,Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "MUX3,Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "MUX2,Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "MUX1,Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "MUX0,Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0xE "OUTPUT4MUX16TO31CFG,Output X-BAR Mux Configuration for Output 4"
|
|
bitfld.long 0xE 30.--31. "MUX31,Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 28.--29. "MUX30,Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 26.--27. "MUX29,Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 24.--25. "MUX28,Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 22.--23. "MUX27,Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 20.--21. "MUX26,Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 18.--19. "MUX25,Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 16.--17. "MUX24,Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 14.--15. "MUX23,Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 12.--13. "MUX22,Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 10.--11. "MUX21,Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xE 8.--9. "MUX20,Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 6.--7. "MUX19,Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 4.--5. "MUX18,Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 2.--3. "MUX17,Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 0.--1. "MUX16,Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x10 "OUTPUT5MUX0TO15CFG,Output X-BAR Mux Configuration for Output 5"
|
|
bitfld.long 0x10 30.--31. "MUX15,Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "MUX14,Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "MUX13,Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "MUX12,Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "MUX11,Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "MUX10,Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "MUX9,Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "MUX8,Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "MUX7,Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "MUX6,Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "MUX5,Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8.--9. "MUX4,Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "MUX3,Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "MUX2,Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "MUX1,Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "MUX0,Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x12 "OUTPUT5MUX16TO31CFG,Output X-BAR Mux Configuration for Output 5"
|
|
bitfld.long 0x12 30.--31. "MUX31,Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 28.--29. "MUX30,Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 26.--27. "MUX29,Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 24.--25. "MUX28,Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 22.--23. "MUX27,Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 20.--21. "MUX26,Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 18.--19. "MUX25,Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 16.--17. "MUX24,Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 14.--15. "MUX23,Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 12.--13. "MUX22,Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 10.--11. "MUX21,Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x12 8.--9. "MUX20,Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 6.--7. "MUX19,Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 4.--5. "MUX18,Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 2.--3. "MUX17,Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 0.--1. "MUX16,Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x14 "OUTPUT6MUX0TO15CFG,Output X-BAR Mux Configuration for Output 6"
|
|
bitfld.long 0x14 30.--31. "MUX15,Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "MUX14,Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "MUX13,Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "MUX12,Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "MUX11,Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "MUX10,Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "MUX9,Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "MUX8,Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "MUX7,Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "MUX6,Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "MUX5,Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "MUX4,Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "MUX3,Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "MUX2,Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "MUX1,Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "MUX0,Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x16 "OUTPUT6MUX16TO31CFG,Output X-BAR Mux Configuration for Output 6"
|
|
bitfld.long 0x16 30.--31. "MUX31,Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 28.--29. "MUX30,Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 26.--27. "MUX29,Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 24.--25. "MUX28,Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 22.--23. "MUX27,Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 20.--21. "MUX26,Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 18.--19. "MUX25,Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 16.--17. "MUX24,Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 14.--15. "MUX23,Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 12.--13. "MUX22,Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 10.--11. "MUX21,Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x16 8.--9. "MUX20,Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 6.--7. "MUX19,Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 4.--5. "MUX18,Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 2.--3. "MUX17,Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 0.--1. "MUX16,Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x18 "OUTPUT7MUX0TO15CFG,Output X-BAR Mux Configuration for Output 7"
|
|
bitfld.long 0x18 30.--31. "MUX15,Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "MUX14,Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "MUX13,Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "MUX12,Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "MUX11,Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "MUX10,Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "MUX9,Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "MUX8,Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "MUX7,Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "MUX6,Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "MUX5,Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 8.--9. "MUX4,Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "MUX3,Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 4.--5. "MUX2,Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "MUX1,Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "MUX0,Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x1A "OUTPUT7MUX16TO31CFG,Output X-BAR Mux Configuration for Output 7"
|
|
bitfld.long 0x1A 30.--31. "MUX31,Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 28.--29. "MUX30,Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 26.--27. "MUX29,Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 24.--25. "MUX28,Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 22.--23. "MUX27,Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 20.--21. "MUX26,Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 18.--19. "MUX25,Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 16.--17. "MUX24,Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 14.--15. "MUX23,Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 12.--13. "MUX22,Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 10.--11. "MUX21,Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1A 8.--9. "MUX20,Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 6.--7. "MUX19,Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 4.--5. "MUX18,Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 2.--3. "MUX17,Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 0.--1. "MUX16,Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x1C "OUTPUT8MUX0TO15CFG,Output X-BAR Mux Configuration for Output 8"
|
|
bitfld.long 0x1C 30.--31. "MUX15,Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 28.--29. "MUX14,Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 26.--27. "MUX13,Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--25. "MUX12,Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. "MUX11,Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--21. "MUX10,Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 18.--19. "MUX9,Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 16.--17. "MUX8,Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. "MUX7,Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. "MUX6,Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 10.--11. "MUX5,Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "MUX4,Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. "MUX3,Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 4.--5. "MUX2,Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 2.--3. "MUX1,Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 0.--1. "MUX0,Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x1E "OUTPUT8MUX16TO31CFG,Output X-BAR Mux Configuration for Output 8"
|
|
bitfld.long 0x1E 30.--31. "MUX31,Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 28.--29. "MUX30,Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 26.--27. "MUX29,Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 24.--25. "MUX28,Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 22.--23. "MUX27,Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 20.--21. "MUX26,Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 18.--19. "MUX25,Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 16.--17. "MUX24,Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 14.--15. "MUX23,Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 12.--13. "MUX22,Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 10.--11. "MUX21,Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1E 8.--9. "MUX20,Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 6.--7. "MUX19,Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 4.--5. "MUX18,Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 2.--3. "MUX17,Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 0.--1. "MUX16,Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
line.long 0x20 "OUTPUT1MUXENABLE,Output X-BAR Mux Enable for Output 1"
|
|
bitfld.long 0x20 31. "MUX31,Mux31 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 30. "MUX30,Mux30 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 29. "MUX29,Mux29 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 28. "MUX28,Mux28 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 27. "MUX27,Mux27 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 26. "MUX26,Mux26 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 25. "MUX25,Mux25 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 24. "MUX24,Mux24 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 23. "MUX23,Mux23 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 22. "MUX22,Mux22 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 21. "MUX21,Mux21 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x20 20. "MUX20,Mux20 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 19. "MUX19,Mux19 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 18. "MUX18,Mux18 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 17. "MUX17,Mux17 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 16. "MUX16,Mux16 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 15. "MUX15,Mux15 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 14. "MUX14,Mux14 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 13. "MUX13,Mux13 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 12. "MUX12,Mux12 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 11. "MUX11,Mux11 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 10. "MUX10,Mux10 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "MUX9,Mux9 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 8. "MUX8,Mux8 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 7. "MUX7,Mux7 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 6. "MUX6,Mux6 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 5. "MUX5,Mux5 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 4. "MUX4,Mux4 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 3. "MUX3,Mux3 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 2. "MUX2,Mux2 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 1. "MUX1,Mux1 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x20 0. "MUX0,Mux0 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x22 "OUTPUT2MUXENABLE,Output X-BAR Mux Enable for Output 2"
|
|
bitfld.long 0x22 31. "MUX31,Mux31 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 30. "MUX30,Mux30 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 29. "MUX29,Mux29 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 28. "MUX28,Mux28 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 27. "MUX27,Mux27 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 26. "MUX26,Mux26 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 25. "MUX25,Mux25 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 24. "MUX24,Mux24 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 23. "MUX23,Mux23 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 22. "MUX22,Mux22 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 21. "MUX21,Mux21 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x22 20. "MUX20,Mux20 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 19. "MUX19,Mux19 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 18. "MUX18,Mux18 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 17. "MUX17,Mux17 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 16. "MUX16,Mux16 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 15. "MUX15,Mux15 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 14. "MUX14,Mux14 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 13. "MUX13,Mux13 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 12. "MUX12,Mux12 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 11. "MUX11,Mux11 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 10. "MUX10,Mux10 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x22 9. "MUX9,Mux9 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 8. "MUX8,Mux8 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 7. "MUX7,Mux7 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 6. "MUX6,Mux6 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 5. "MUX5,Mux5 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 4. "MUX4,Mux4 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 3. "MUX3,Mux3 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 2. "MUX2,Mux2 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 1. "MUX1,Mux1 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x22 0. "MUX0,Mux0 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x24 "OUTPUT3MUXENABLE,Output X-BAR Mux Enable for Output 3"
|
|
bitfld.long 0x24 31. "MUX31,Mux31 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 30. "MUX30,Mux30 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 29. "MUX29,Mux29 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 28. "MUX28,Mux28 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 27. "MUX27,Mux27 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 26. "MUX26,Mux26 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 25. "MUX25,Mux25 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 24. "MUX24,Mux24 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 23. "MUX23,Mux23 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 22. "MUX22,Mux22 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 21. "MUX21,Mux21 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x24 20. "MUX20,Mux20 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 19. "MUX19,Mux19 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 18. "MUX18,Mux18 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 17. "MUX17,Mux17 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 16. "MUX16,Mux16 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 15. "MUX15,Mux15 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 14. "MUX14,Mux14 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 13. "MUX13,Mux13 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 12. "MUX12,Mux12 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 11. "MUX11,Mux11 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 10. "MUX10,Mux10 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x24 9. "MUX9,Mux9 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 8. "MUX8,Mux8 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 7. "MUX7,Mux7 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 6. "MUX6,Mux6 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 5. "MUX5,Mux5 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 4. "MUX4,Mux4 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 3. "MUX3,Mux3 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 2. "MUX2,Mux2 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 1. "MUX1,Mux1 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x24 0. "MUX0,Mux0 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x26 "OUTPUT4MUXENABLE,Output X-BAR Mux Enable for Output 4"
|
|
bitfld.long 0x26 31. "MUX31,Mux31 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 30. "MUX30,Mux30 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 29. "MUX29,Mux29 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 28. "MUX28,Mux28 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 27. "MUX27,Mux27 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 26. "MUX26,Mux26 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 25. "MUX25,Mux25 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 24. "MUX24,Mux24 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 23. "MUX23,Mux23 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 22. "MUX22,Mux22 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 21. "MUX21,Mux21 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x26 20. "MUX20,Mux20 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 19. "MUX19,Mux19 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 18. "MUX18,Mux18 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 17. "MUX17,Mux17 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 16. "MUX16,Mux16 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 15. "MUX15,Mux15 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 14. "MUX14,Mux14 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 13. "MUX13,Mux13 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 12. "MUX12,Mux12 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 11. "MUX11,Mux11 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 10. "MUX10,Mux10 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x26 9. "MUX9,Mux9 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 8. "MUX8,Mux8 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 7. "MUX7,Mux7 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 6. "MUX6,Mux6 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 5. "MUX5,Mux5 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 4. "MUX4,Mux4 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 3. "MUX3,Mux3 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 2. "MUX2,Mux2 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 1. "MUX1,Mux1 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x26 0. "MUX0,Mux0 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x28 "OUTPUT5MUXENABLE,Output X-BAR Mux Enable for Output 5"
|
|
bitfld.long 0x28 31. "MUX31,Mux31 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 30. "MUX30,Mux30 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 29. "MUX29,Mux29 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 28. "MUX28,Mux28 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 27. "MUX27,Mux27 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 26. "MUX26,Mux26 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 25. "MUX25,Mux25 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 24. "MUX24,Mux24 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 23. "MUX23,Mux23 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 22. "MUX22,Mux22 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 21. "MUX21,Mux21 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x28 20. "MUX20,Mux20 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 19. "MUX19,Mux19 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 18. "MUX18,Mux18 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 17. "MUX17,Mux17 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 16. "MUX16,Mux16 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 15. "MUX15,Mux15 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 14. "MUX14,Mux14 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 13. "MUX13,Mux13 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 12. "MUX12,Mux12 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 11. "MUX11,Mux11 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 10. "MUX10,Mux10 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x28 9. "MUX9,Mux9 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 8. "MUX8,Mux8 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 7. "MUX7,Mux7 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 6. "MUX6,Mux6 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 5. "MUX5,Mux5 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 4. "MUX4,Mux4 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 3. "MUX3,Mux3 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 2. "MUX2,Mux2 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 1. "MUX1,Mux1 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x28 0. "MUX0,Mux0 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x2A "OUTPUT6MUXENABLE,Output X-BAR Mux Enable for Output 6"
|
|
bitfld.long 0x2A 31. "MUX31,Mux31 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 30. "MUX30,Mux30 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 29. "MUX29,Mux29 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 28. "MUX28,Mux28 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 27. "MUX27,Mux27 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 26. "MUX26,Mux26 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 25. "MUX25,Mux25 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 24. "MUX24,Mux24 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 23. "MUX23,Mux23 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 22. "MUX22,Mux22 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 21. "MUX21,Mux21 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2A 20. "MUX20,Mux20 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 19. "MUX19,Mux19 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 18. "MUX18,Mux18 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 17. "MUX17,Mux17 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 16. "MUX16,Mux16 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 15. "MUX15,Mux15 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 14. "MUX14,Mux14 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 13. "MUX13,Mux13 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 12. "MUX12,Mux12 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 11. "MUX11,Mux11 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 10. "MUX10,Mux10 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2A 9. "MUX9,Mux9 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 8. "MUX8,Mux8 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 7. "MUX7,Mux7 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 6. "MUX6,Mux6 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 5. "MUX5,Mux5 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 4. "MUX4,Mux4 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 3. "MUX3,Mux3 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 2. "MUX2,Mux2 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 1. "MUX1,Mux1 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2A 0. "MUX0,Mux0 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x2C "OUTPUT7MUXENABLE,Output X-BAR Mux Enable for Output 7"
|
|
bitfld.long 0x2C 31. "MUX31,Mux31 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 30. "MUX30,Mux30 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 29. "MUX29,Mux29 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 28. "MUX28,Mux28 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 27. "MUX27,Mux27 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 26. "MUX26,Mux26 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 25. "MUX25,Mux25 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 24. "MUX24,Mux24 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 23. "MUX23,Mux23 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 22. "MUX22,Mux22 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 21. "MUX21,Mux21 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 20. "MUX20,Mux20 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 19. "MUX19,Mux19 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 18. "MUX18,Mux18 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 17. "MUX17,Mux17 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 16. "MUX16,Mux16 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 15. "MUX15,Mux15 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 14. "MUX14,Mux14 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 13. "MUX13,Mux13 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 12. "MUX12,Mux12 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 11. "MUX11,Mux11 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 10. "MUX10,Mux10 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 9. "MUX9,Mux9 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 8. "MUX8,Mux8 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 7. "MUX7,Mux7 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 6. "MUX6,Mux6 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 5. "MUX5,Mux5 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 4. "MUX4,Mux4 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 3. "MUX3,Mux3 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 2. "MUX2,Mux2 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 1. "MUX1,Mux1 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2C 0. "MUX0,Mux0 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x2E "OUTPUT8MUXENABLE,Output X-BAR Mux Enable for Output 8"
|
|
bitfld.long 0x2E 31. "MUX31,Mux31 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 30. "MUX30,Mux30 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 29. "MUX29,Mux29 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 28. "MUX28,Mux28 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 27. "MUX27,Mux27 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 26. "MUX26,Mux26 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 25. "MUX25,Mux25 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 24. "MUX24,Mux24 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 23. "MUX23,Mux23 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 22. "MUX22,Mux22 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 21. "MUX21,Mux21 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2E 20. "MUX20,Mux20 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 19. "MUX19,Mux19 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 18. "MUX18,Mux18 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 17. "MUX17,Mux17 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 16. "MUX16,Mux16 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 15. "MUX15,Mux15 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 14. "MUX14,Mux14 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 13. "MUX13,Mux13 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 12. "MUX12,Mux12 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 11. "MUX11,Mux11 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 10. "MUX10,Mux10 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2E 9. "MUX9,Mux9 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 8. "MUX8,Mux8 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 7. "MUX7,Mux7 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 6. "MUX6,Mux6 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 5. "MUX5,Mux5 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 4. "MUX4,Mux4 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 3. "MUX3,Mux3 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 2. "MUX2,Mux2 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 1. "MUX1,Mux1 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2E 0. "MUX0,Mux0 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "OUTPUTLATCH,Output X-BAR Output Latch"
|
|
bitfld.long 0x0 7. "OUTPUT8,Records the OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 6. "OUTPUT7,Records the OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 5. "OUTPUT6,Records the OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 4. "OUTPUT5,Records the OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 3. "OUTPUT4,Records the OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 2. "OUTPUT3,Records the OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 1. "OUTPUT2,Records the OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 0. "OUTPUT1,Records the OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long 0x32++0xF
|
|
line.long 0x0 "OUTPUTLATCHCLR,Output X-BAR Output Latch Clear"
|
|
bitfld.long 0x0 7. "OUTPUT8,Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 6. "OUTPUT7,Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 5. "OUTPUT6,Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 4. "OUTPUT5,Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 3. "OUTPUT4,Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 2. "OUTPUT3,Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 1. "OUTPUT2,Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x0 0. "OUTPUT1,Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x2 "OUTPUTLATCHFRC,Output X-BAR Output Latch Clear"
|
|
bitfld.long 0x2 7. "OUTPUT8,Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 6. "OUTPUT7,Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 5. "OUTPUT6,Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 4. "OUTPUT5,Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 3. "OUTPUT4,Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 2. "OUTPUT3,Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 1. "OUTPUT2,Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x2 0. "OUTPUT1,Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
line.long 0x4 "OUTPUTLATCHENABLE,Output X-BAR Output Latch Enable"
|
|
bitfld.long 0x4 7. "OUTPUT8,Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 6. "OUTPUT7,Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 5. "OUTPUT6,Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 4. "OUTPUT5,Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 3. "OUTPUT4,Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 2. "OUTPUT3,Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 1. "OUTPUT2,Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x4 0. "OUTPUT1,Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR" "0,1"
|
|
line.long 0x6 "OUTPUTINV,Output X-BAR Output Inversion"
|
|
bitfld.long 0x6 7. "OUTPUT8,Selects polarity for OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 6. "OUTPUT7,Selects polarity for OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 5. "OUTPUT6,Selects polarity for OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 4. "OUTPUT5,Selects polarity for OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 3. "OUTPUT4,Selects polarity for OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 2. "OUTPUT3,Selects polarity for OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 1. "OUTPUT2,Selects polarity for OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x6 0. "OUTPUT1,Selects polarity for OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long 0x3E++0x3
|
|
line.long 0x0 "OUTPUTLOCK,Output X-BAR Configuration Lock register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Write Protection KEY"
|
|
bitfld.long 0x0 0. "LOCK,Locks the configuration for OUTPUT-XBAR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F2838??"))
|
|
tree "XBAR"
|
|
base d:0x7920
|
|
rgroup.long 0x0++0xF
|
|
line.long 0x0 "XBARFLG1,X-Bar Input Flag Register 1"
|
|
bitfld.long 0x0 31. "CMPSS8_CTRIPOUTH,Input Flag for CMPSS8.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 30. "CMPSS8_CTRIPOUTL,Input Flag for CMPSS8.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 29. "CMPSS7_CTRIPOUTH,Input Flag for CMPSS7.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 28. "CMPSS7_CTRIPOUTL,Input Flag for CMPSS7.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 27. "CMPSS6_CTRIPOUTH,Input Flag for CMPSS6.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 26. "CMPSS6_CTRIPOUTL,Input Flag for CMPSS6.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 25. "CMPSS5_CTRIPOUTH,Input Flag for CMPSS5.CTRIPOUTH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CMPSS5_CTRIPOUTL,Input Flag for CMPSS5.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 23. "CMPSS4_CTRIPOUTH,Input Flag for CMPSS4.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 22. "CMPSS4_CTRIPOUTL,Input Flag for CMPSS4.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 21. "CMPSS3_CTRIPOUTH,Input Flag for CMPSS3.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 20. "CMPSS3_CTRIPOUTL,Input Flag for CMPSS3.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 19. "CMPSS2_CTRIPOUTH,Input Flag for CMPSS2.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 18. "CMPSS2_CTRIPOUTL,Input Flag for CMPSS2.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPSS1_CTRIPOUTH,Input Flag for CMPSS1.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 16. "CMPSS1_CTRIPOUTL,Input Flag for CMPSS1.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 15. "CMPSS8_CTRIPH,Input Flag for CMPSS8.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 14. "CMPSS8_CTRIPL,Input Flag for CMPSS8.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 13. "CMPSS7_CTRIPH,Input Flag for CMPSS7.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 12. "CMPSS7_CTRIPL,Input Flag for CMPSS7.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 11. "CMPSS6_CTRIPH,Input Flag for CMPSS6.CTRIPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CMPSS6_CTRIPL,Input Flag for CMPSS6.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 9. "CMPSS5_CTRIPH,Input Flag for CMPSS5.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 8. "CMPSS5_CTRIPL,Input Flag for CMPSS5.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 7. "CMPSS4_CTRIPH,Input Flag for CMPSS4.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 6. "CMPSS4_CTRIPL,Input Flag for CMPSS4.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 5. "CMPSS3_CTRIPH,Input Flag for CMPSS3.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 4. "CMPSS3_CTRIPL,Input Flag for CMPSS3.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMPSS2_CTRIPH,Input Flag for CMPSS2.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 2. "CMPSS2_CTRIPL,Input Flag for CMPSS2.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 1. "CMPSS1_CTRIPH,Input Flag for CMPSS1.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 0. "CMPSS1_CTRIPL,Input Flag for CMPSS1.CTRIPL Signal" "0,1"
|
|
line.long 0x2 "XBARFLG2,X-Bar Input Flag Register 2"
|
|
bitfld.long 0x2 31. "ADCCEVT1,Input Flag for ADCCEVT1 Signal" "0,1"
|
|
bitfld.long 0x2 30. "ADCBEVT4,Input Flag for ADCBEVT4 Signal" "0,1"
|
|
bitfld.long 0x2 29. "ADCBEVT3,Input Flag for ADCBEVT3 Signal" "0,1"
|
|
bitfld.long 0x2 28. "ADCBEVT2,Input Flag for ADCBEVT2 Signal" "0,1"
|
|
bitfld.long 0x2 27. "ADCBEVT1,Input Flag for ADCBEVT1 Signal" "0,1"
|
|
bitfld.long 0x2 26. "ADCAEVT4,Input Flag for ADCAEVT4 Signal" "0,1"
|
|
bitfld.long 0x2 25. "ADCAEVT3,Input Flag for ADCAEVT3 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 24. "ADCAEVT2,Input Flag for ADCAEVT2 Signal" "0,1"
|
|
bitfld.long 0x2 23. "ADCAEVT1,Input Flag for ADCAEVT1 Signal" "0,1"
|
|
bitfld.long 0x2 22. "EXTSYNCOUT,Input Flag for EXTSYNCOUT Signal" "0,1"
|
|
bitfld.long 0x2 21. "ECAP6_OUT,Input Flag for ECAP6.OUT Signal" "0,1"
|
|
bitfld.long 0x2 20. "ECAP5_OUT,Input Flag for ECAP5.OUT Signal" "0,1"
|
|
bitfld.long 0x2 19. "ECAP4_OUT,Input Flag for ECAP4.OUT Signal" "0,1"
|
|
bitfld.long 0x2 18. "ECAP3_OUT,Input Flag for ECAP3.OUT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 17. "ECAP2_OUT,Input Flag for ECAP2.OUT Signal" "0,1"
|
|
bitfld.long 0x2 16. "ECAP1_OUT,Input Flag for ECAP1.OUT Signal" "0,1"
|
|
bitfld.long 0x2 15. "INPUT14,Input Flag for INPUT14 Signal" "0,1"
|
|
bitfld.long 0x2 14. "INPUT13,Input Flag for INPUT13 Signal" "0,1"
|
|
bitfld.long 0x2 13. "INPUT12,Input Flag for INPUT12 Signal" "0,1"
|
|
bitfld.long 0x2 12. "INPUT11,Input Flag for INPUT11 Signal" "0,1"
|
|
bitfld.long 0x2 11. "INPUT10,Input Flag for INPUT10\ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 10. "INPUT9,Input Flag for INPUT9 Signal" "0,1"
|
|
bitfld.long 0x2 9. "INPUT8,Input Flag for INPUT8 Signal" "0,1"
|
|
bitfld.long 0x2 8. "INPUT7,Input Flag for INPUT7 Signal" "0,1"
|
|
bitfld.long 0x2 7. "ADCSOCB,Input Flag for ADCSOCB Signal" "0,1"
|
|
bitfld.long 0x2 6. "ADCSOCA,Input Flag for ADCSOCA Signal" "0,1"
|
|
bitfld.long 0x2 5. "INPUT6,Input Flag for INPUT6 Signal" "0,1"
|
|
bitfld.long 0x2 4. "INPUT5,Input Flag for INPUT5 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "INPUT4,Input Flag for INPUT4 Signal" "0,1"
|
|
bitfld.long 0x2 2. "INPUT3,Input Flag for INPUT3 Signal" "0,1"
|
|
bitfld.long 0x2 1. "INPUT2,Input Flag for INPUT2 Signal" "0,1"
|
|
bitfld.long 0x2 0. "INPUT1,Input Flag for INPUT1 Signal" "0,1"
|
|
line.long 0x4 "XBARFLG3,X-Bar Input Flag Register 3"
|
|
bitfld.long 0x4 31. "SD1FLT4_DRINT,Input Flag for SD1FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x4 30. "SD1FLT4_COMPZ,Input Flag for SD1FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 29. "SD1FLT3_DRINT,Input Flag for SD1FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x4 28. "SD1FLT3_COMPZ,Input Flag for SD1FLT3.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 27. "SD1FLT2_DRINT,Input Flag for SD1FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x4 26. "SD1FLT2_COMPZ,Input Flag for SD1FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 25. "SD1FLT1_DRINT,Input Flag for SD1FLT1.DRINT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "SD1FLT1_COMPZ,Input Flag for SD1FLT1.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 23. "ECAP7_OUT,Input Flag for ECAP7.OUT Signal" "0,1"
|
|
bitfld.long 0x4 22. "SD2FLT4_COMPH,Input Flag for SD2FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 21. "SD2FLT4_COMPL,Input Flag for SD2FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 20. "SD2FLT3_COMPH,Input Flag for SD2FLT3.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 19. "SD2FLT3_COMPL,Input Flag for SD2FLT3.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 18. "SD2FLT2_COMPH,Input Flag for SD2FLT2.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "SD2FLT2_COMPL,Input Flag for SD2FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 16. "SD2FLT1_COMPH,Input Flag for SD2FLT1.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 15. "SD2FLT1_COMPL,Input Flag for SD2FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 14. "SD1FLT4_COMPH,Input Flag for SD1FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 13. "SD1FLT4_COMPL,Input Flag for SD1FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 12. "SD1FLT3_COMPH,Input Flag for SD1FLT3.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 11. "SD1FLT3_COMPL,Input Flag for SD1FLT3.COMPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SD1FLT2_COMPH,Input Flag for SD1FLT2.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 9. "SD1FLT2_COMPL,Input Flag for SD1FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 8. "SD1FLT1_COMPH,Input Flag for SD1FLT1.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 7. "SD1FLT1_COMPL,Input Flag for SD1FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 6. "ADCDEVT4,Input Flag for ADCDEVT4 Signal" "0,1"
|
|
bitfld.long 0x4 5. "ADCDEVT3,Input Flag for ADCDEVT3 Signal" "0,1"
|
|
bitfld.long 0x4 4. "ADCDEVT2,Input Flag for ADCDEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ADCDEVT1,Input Flag for ADCDEVT1 Signal" "0,1"
|
|
bitfld.long 0x4 2. "ADCCEVT4,Input Flag for ADCCEVT4 Signal" "0,1"
|
|
bitfld.long 0x4 1. "ADCCEVT3,Input Flag for ADCCEVT3 Signal" "0,1"
|
|
bitfld.long 0x4 0. "ADCCEVT2,Input Flag for ADCCEVT2 Signal" "0,1"
|
|
line.long 0x6 "XBARFLG4,X-Bar Input Flag Register 4"
|
|
bitfld.long 0x6 31. "CLAHALT,Input Latch for CLAHALT Signal" "0,1"
|
|
bitfld.long 0x6 30. "ECATSYNC1,Input Latch for ECATSYNC1 Signal" "0,1"
|
|
bitfld.long 0x6 29. "ECATSYNC0,Input Latch for ECATSYNC0 Signal" "0,1"
|
|
bitfld.long 0x6 28. "ERRORSTS_ERROR,Input Latch for ERRORSTS_ERROR Signal" "0,1"
|
|
bitfld.long 0x6 27. "CLB6_OUT5,Input Latch for CLB6_OUT5 Signal" "0,1"
|
|
bitfld.long 0x6 26. "CLB6_OUT4,Input Latch for CLB6_OUT4 Signal" "0,1"
|
|
bitfld.long 0x6 25. "CLB5_OUT5,Input Latch for CLB5_OUT5 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 24. "CLB5_OUT4,Input Latch for CLB5_OUT4 Signal" "0,1"
|
|
bitfld.long 0x6 23. "CLB4_OUT5,Input Flag for CLB4_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 22. "CLB4_OUT4,Input Flag for CLB4_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 21. "CLB3_OUT5,Input Flag for CLB3_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 20. "CLB3_OUT4,Input Flag for CLB3_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 19. "CLB2_OUT5,Input Flag for CLB2_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 18. "CLB2_OUT4,Input Flag for CLB2_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 17. "CLB1_OUT5,Input Flag for CLB1_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 16. "CLB1_OUT4,Input Flag for CLB1_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 15. "CLB8_OUT5,Input Flag for CLB8_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 14. "CLB8_OUT4,Input Flag for CLB8_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 13. "CLB7_OUT5,Input Flag for CLB7_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 12. "CLB7_OUT4,Input Flag for CLB7_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 11. "MCANA_FEVT2,Input Flag for MCANA_FEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 10. "MCANA_FEVT1,Input Flag for MCANA_FEVT1 Signal" "0,1"
|
|
bitfld.long 0x6 9. "MCANA_FEVT0,Input Flag for MCANA_FEVT0 Signal" "0,1"
|
|
bitfld.long 0x6 8. "EMAC_PPS0,Input Flag for EMAC_PPS0 Signal" "0,1"
|
|
bitfld.long 0x6 7. "SD2FLT4_DRINT,Input Flag for SD2FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 6. "SD2FLT4_COMPZ,Input Flag for SD2FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x6 5. "SD2FLT3_DRINT,Input Flag for SD2FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 4. "SD2FLT3_COMPZ,Input Flag for SD2FLT3.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SD2FLT2_DRINT,Input Flag for SD2FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 2. "SD2FLT2_COMPZ,Input Flag for SD2FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x6 1. "SD2FLT1_DRINT,Input Flag for SD2FLT1.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 0. "SD2FLT1_COMPZ,Input Flag for SD2FLT1.COMPZ Signal" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "XBARCLR1,X-Bar Input Flag Clear Register 1"
|
|
bitfld.long 0x0 31. "CMPSS8_CTRIPOUTH,Input Flag Clear for CMPSS8.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 30. "CMPSS8_CTRIPOUTL,Input Flag Clear for CMPSS8.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 29. "CMPSS7_CTRIPOUTH,Input Flag Clear for CMPSS7.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 28. "CMPSS7_CTRIPOUTL,Input Flag Clear for CMPSS7.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 27. "CMPSS6_CTRIPOUTH,Input Flag Clear for CMPSS6.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 26. "CMPSS6_CTRIPOUTL,Input Flag Clear for CMPSS6.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 25. "CMPSS5_CTRIPOUTH,Input Flag Clear for CMPSS5.CTRIPOUTH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CMPSS5_CTRIPOUTL,Input Flag Clear for CMPSS5.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 23. "CMPSS4_CTRIPOUTH,Input Flag Clear for CMPSS4.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 22. "CMPSS4_CTRIPOUTL,Input Flag Clear for CMPSS4.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 21. "CMPSS3_CTRIPOUTH,Input Flag Clear for CMPSS3.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 20. "CMPSS3_CTRIPOUTL,Input Flag Clear for CMPSS3.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 19. "CMPSS2_CTRIPOUTH,Input Flag Clear for CMPSS2.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 18. "CMPSS2_CTRIPOUTL,Input Flag Clear for CMPSS2.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPSS1_CTRIPOUTH,Input Flag Clear for CMPSS1.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x0 16. "CMPSS1_CTRIPOUTL,Input Flag Clear for CMPSS1.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x0 15. "CMPSS8_CTRIPH,Input Flag Clear for CMPSS8.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 14. "CMPSS8_CTRIPL,Input Flag Clear for CMPSS8.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 13. "CMPSS7_CTRIPH,Input Flag Clear for CMPSS7.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 12. "CMPSS7_CTRIPL,Input Flag Clear for CMPSS7.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 11. "CMPSS6_CTRIPH,Input Flag Clear for CMPSS6.CTRIPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CMPSS6_CTRIPL,Input Flag Clear for CMPSS6.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 9. "CMPSS5_CTRIPH,Input Flag Clear for CMPSS5.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 8. "CMPSS5_CTRIPL,Input Flag Clear for CMPSS5.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 7. "CMPSS4_CTRIPH,Input Flag Clear for CMPSS4.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 6. "CMPSS4_CTRIPL,Input Flag Clear for CMPSS4.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 5. "CMPSS3_CTRIPH,Input Flag Clear for CMPSS3.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 4. "CMPSS3_CTRIPL,Input Flag Clear for CMPSS3.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMPSS2_CTRIPH,Input Flag Clear for CMPSS2.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 2. "CMPSS2_CTRIPL,Input Flag Clear for CMPSS2.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x0 1. "CMPSS1_CTRIPH,Input Flag Clear for CMPSS1.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x0 0. "CMPSS1_CTRIPL,Input Flag Clear for CMPSS1.CTRIPL Signal" "0,1"
|
|
line.long 0x2 "XBARCLR2,X-Bar Input Flag Clear Register 2"
|
|
bitfld.long 0x2 31. "ADCCEVT1,Input Flag Clear for ADCCEVT1 Signal" "0,1"
|
|
bitfld.long 0x2 30. "ADCBEVT4,Input Flag Clear for ADCBEVT4 Signal" "0,1"
|
|
bitfld.long 0x2 29. "ADCBEVT3,Input Flag Clear for ADCBEVT3 Signal" "0,1"
|
|
bitfld.long 0x2 28. "ADCBEVT2,Input Flag Clear for ADCBEVT2 Signal" "0,1"
|
|
bitfld.long 0x2 27. "ADCBEVT1,Input Flag Clear for ADCBEVT1 Signal" "0,1"
|
|
bitfld.long 0x2 26. "ADCAEVT4,Input Flag Clear for ADCAEVT4 Signal" "0,1"
|
|
bitfld.long 0x2 25. "ADCAEVT3,Input Flag Clear for ADCAEVT3 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 24. "ADCAEVT2,Input Flag Clear for ADCAEVT2 Signal" "0,1"
|
|
bitfld.long 0x2 23. "ADCAEVT1,Input Flag Clear for ADCAEVT1 Signal" "0,1"
|
|
bitfld.long 0x2 22. "EXTSYNCOUT,Input Flag Clear for EXTSYNCOUT Signal" "0,1"
|
|
bitfld.long 0x2 21. "ECAP6_OUT,Input Flag Clear for ECAP6.OUT Signal" "0,1"
|
|
bitfld.long 0x2 20. "ECAP5_OUT,Input Flag Clear for ECAP5.OUT Signal" "0,1"
|
|
bitfld.long 0x2 19. "ECAP4_OUT,Input Flag Clear for ECAP4.OUT Signal" "0,1"
|
|
bitfld.long 0x2 18. "ECAP3_OUT,Input Flag Clear for ECAP3.OUT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 17. "ECAP2_OUT,Input Flag Clear for ECAP2.OUT Signal" "0,1"
|
|
bitfld.long 0x2 16. "ECAP1_OUT,Input Flag Clear for ECAP1.OUT Signal" "0,1"
|
|
bitfld.long 0x2 15. "INPUT14,Input Flag Clear for INPUT14 Signal" "0,1"
|
|
bitfld.long 0x2 14. "INPUT13,Input Flag Clear for INPUT13 Signal" "0,1"
|
|
bitfld.long 0x2 13. "INPUT12,Input Flag Clear for INPUT12 Signal" "0,1"
|
|
bitfld.long 0x2 12. "INPUT11,Input Flag Clear for INPUT11 Signal" "0,1"
|
|
bitfld.long 0x2 11. "INPUT10,Input Flag Clear for INPUT10 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 10. "INPUT9,Input Flag Clear for INPUT9 Signal" "0,1"
|
|
bitfld.long 0x2 9. "INPUT8,Input Flag Clear for INPUT8 Signal" "0,1"
|
|
bitfld.long 0x2 8. "INPUT7,Input Flag Clear for INPUT7 Signal" "0,1"
|
|
bitfld.long 0x2 7. "ADCSOCB,Input Flag Clear for ADCSOCB Signal" "0,1"
|
|
bitfld.long 0x2 6. "ADCSOCA,Input Flag Clear for ADCSOCA Signal" "0,1"
|
|
bitfld.long 0x2 5. "INPUT6,Input Flag Clear for INPUT6 Signal" "0,1"
|
|
bitfld.long 0x2 4. "INPUT5,Input Flag Clear for INPUT5 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x2 3. "INPUT4,Input Flag Clear for INPUT4 Signal" "0,1"
|
|
bitfld.long 0x2 2. "INPUT3,Input Flag Clear for INPUT3 Signal" "0,1"
|
|
bitfld.long 0x2 1. "INPUT2,Input Flag Clear for INPUT2 Signal" "0,1"
|
|
bitfld.long 0x2 0. "INPUT1,Input Flag Clear for INPUT1 Signal" "0,1"
|
|
line.long 0x4 "XBARCLR3,X-Bar Input Flag Clear Register 3"
|
|
bitfld.long 0x4 31. "SD1FLT4_DRINT,Input Flag clear for SD1FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x4 30. "SD1FLT4_COMPZ,Input Flag clear for SD1FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 29. "SD1FLT3_DRINT,Input Flag clear for SD1FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x4 28. "SD1FLT3_COMPZ,Input Flag clear for SD1FLT3.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 27. "SD1FLT2_DRINT,Input Flag clear for SD1FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x4 26. "SD1FLT2_COMPZ,Input Flag clear for SD1FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 25. "SD1FLT1_DRINT,Input Flag clear for SD1FLT1.DRINT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "SD1FLT1_COMPZ,Input Flag clear for SD1FLT1.COMPZ Signal" "0,1"
|
|
bitfld.long 0x4 23. "ECAP7_OUT,Input Flag clear for ECAP7.OUT Signal" "0,1"
|
|
bitfld.long 0x4 22. "SD2FLT4_COMPH,Input Flag Clear for SD2FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 21. "SD2FLT4_COMPL,Input Flag Clear for SD2FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 20. "SD2FLT3_COMPH,Input Flag Clear for SD2FLT3.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 19. "SD2FLT3_COMPL,Input Flag Clear for SD2FLT3.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 18. "SD2FLT2_COMPH,Input Flag Clear for SD2FLT2.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "SD2FLT2_COMPL,Input Flag Clear for SD2FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 16. "SD2FLT1_COMPH,Input Flag Clear for SD2FLT1.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 15. "SD2FLT1_COMPL,Input Flag Clear for SD2FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 14. "SD1FLT4_COMPH,Input Flag Clear for SD1FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 13. "SD1FLT4_COMPL,Input Flag Clear for SD1FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 12. "SD1FLT3_COMPH,Input Flag Clear for SD1FLT3.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 11. "SD1FLT3_COMPL,Input Flag Clear for SD1FLT3.COMPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SD1FLT2_COMPH,Input Flag Clear for SD1FLT2.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 9. "SD1FLT2_COMPL,Input Flag Clear for SD1FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 8. "SD1FLT1_COMPH,Input Flag Clear for SD1FLT1.COMPH Signal" "0,1"
|
|
bitfld.long 0x4 7. "SD1FLT1_COMPL,Input Flag Clear for SD1FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x4 6. "ADCDEVT4,Input Flag Clear for ADCDEVT4 Signal" "0,1"
|
|
bitfld.long 0x4 5. "ADCDEVT3,Input Flag Clear for ADCDEVT3 Signal" "0,1"
|
|
bitfld.long 0x4 4. "ADCDEVT2,Input Flag Clear for ADCDEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ADCDEVT1,Input Flag Clear for ADCDEVT1 Signal" "0,1"
|
|
bitfld.long 0x4 2. "ADCCEVT4,Input Flag Clear for ADCCEVT4 Signal" "0,1"
|
|
bitfld.long 0x4 1. "ADCCEVT3,Input Flag Clear for ADCCEVT3 Signal" "0,1"
|
|
bitfld.long 0x4 0. "ADCCEVT2,Input Flag Clear for ADCCEVT2 Signal" "0,1"
|
|
line.long 0x6 "XBARCLR4,X-Bar Input Flag Clear Register 4"
|
|
rbitfld.long 0x6 31. "CLAHALT,Input Flag clear for CLAHALT Signal" "0,1"
|
|
bitfld.long 0x6 30. "ECATSYNC1,Input Latch clear for ECATSYNC1 Signal" "0,1"
|
|
bitfld.long 0x6 29. "ECATSYNC0,Input Latch clear for ECATSYNC0 Signal" "0,1"
|
|
bitfld.long 0x6 28. "ERRORSTS_ERROR,Input Latch clear for ERRORSTS_ERROR Signal" "0,1"
|
|
bitfld.long 0x6 27. "CLB6_OUT5,Input Latch clear for CLB6_OUT5 Signal" "0,1"
|
|
bitfld.long 0x6 26. "CLB6_OUT4,Input Latch clear for CLB6_OUT4 Signal" "0,1"
|
|
bitfld.long 0x6 25. "CLB5_OUT5,Input Latch clear for CLB5_OUT5 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 24. "CLB5_OUT4,Input Latch clear for CLB5_OUT4 Signal" "0,1"
|
|
bitfld.long 0x6 23. "CLB4_OUT5,Input Flag clear for CLB4_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 22. "CLB4_OUT4,Input Flag clear for CLB4_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 21. "CLB3_OUT5,Input Flag clear for CLB3_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 20. "CLB3_OUT4,Input Flag clear for CLB3_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 19. "CLB2_OUT5,Input Flag clear for CLB2_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 18. "CLB2_OUT4,Input Flag clear for CLB2_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 17. "CLB1_OUT5,Input Flag clear for CLB1_5.1 Signal" "0,1"
|
|
bitfld.long 0x6 16. "CLB1_OUT4,Input Flag clear for CLB1_4.1 Signal" "0,1"
|
|
bitfld.long 0x6 15. "CLB8_OUT5,Input Flag clear for CLB8_OUT5 Signal" "0,1"
|
|
bitfld.long 0x6 14. "CLB8_OUT4,Input Flag clear for CLB8_OUT4 Signal" "0,1"
|
|
bitfld.long 0x6 13. "CLB7_OUT5,Input Flag clear for CLB7_OUT5 Signal" "0,1"
|
|
bitfld.long 0x6 12. "CLB7_OUT4,Input Flag clear for CLB7_OUT4 Signal" "0,1"
|
|
bitfld.long 0x6 11. "MCANA_FEVT2,Input Flag clear for MCANA_FEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 10. "MCANA_FEVT1,Input Flag clear for MCANA_FEVT1 Signal" "0,1"
|
|
bitfld.long 0x6 9. "MCANA_FEVT0,Input Flag clear for MCANA_FEVT0 Signal" "0,1"
|
|
bitfld.long 0x6 8. "EMAC_PPS0,Input Flag clear for EMAC_PPS0 Signal" "0,1"
|
|
bitfld.long 0x6 7. "SD2FLT4_DRINT,Input Flag clear for SD2FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 6. "SD2FLT4_COMPZ,Input Flag clear for SD2FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x6 5. "SD2FLT3_DRINT,Input Flag clear for SD2FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 4. "SD2FLT3_COMPZ,Input Flag clear for SD2FLT3.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x6 3. "SD2FLT2_DRINT,Input Flag clear for SD2FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 2. "SD2FLT2_COMPZ,Input Flag clear for SD2FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x6 1. "SD2FLT1_DRINT,Input Flag clear for SD2FLT1.DRINT Signal" "0,1"
|
|
bitfld.long 0x6 0. "SD2FLT1_COMPZ,Input Flag clear for SD2FLT1.COMPZ Signal" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("F28386?")||cpuis("F28388?"))
|
|
tree "CLBXBAR"
|
|
base d:0x7A40
|
|
group.long 0x0++0x5F
|
|
line.long 0x0 "AUXSIG0MUX0TO15CFG,CLB XBAR Mux Configuration for Output-0"
|
|
bitfld.long 0x0 30.--31. "MUX15,MUX15 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MUX14,MUX14 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MUX13,MUX13 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MUX12,MUX12 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MUX11,MUX11 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MUX10,MUX10 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MUX9,MUX9 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MUX8,MUX8 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MUX7,MUX7 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MUX6,MUX6 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MUX5,MUX5 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MUX4,MUX4 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MUX3,MUX3 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "MUX2,MUX2 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MUX1,MUX1 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MUX0,MUX0 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x2 "AUXSIG0MUX16TO31CFG,CLB XBAR Mux Configuration for Output-0"
|
|
bitfld.long 0x2 30.--31. "MUX31,MUX31 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 28.--29. "MUX30,MUX30 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 26.--27. "MUX29,MUX29 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 24.--25. "MUX28,MUX28 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 22.--23. "MUX27,MUX27 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 20.--21. "MUX26,MUX26 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 18.--19. "MUX25,MUX25 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 16.--17. "MUX24,MUX24 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 14.--15. "MUX23,MUX23 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 12.--13. "MUX22,MUX22 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 10.--11. "MUX21,MUX21 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 8.--9. "MUX20,MUX20 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 6.--7. "MUX19,MUX19 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2 4.--5. "MUX18,MUX18 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 2.--3. "MUX17,MUX17 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x2 0.--1. "MUX16,MUX16 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x4 "AUXSIG1MUX0TO15CFG,CLB XBAR Mux Configuration for Output-1"
|
|
bitfld.long 0x4 30.--31. "MUX15,MUX15 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "MUX14,MUX14 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 26.--27. "MUX13,MUX13 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 24.--25. "MUX12,MUX12 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "MUX11,MUX11 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "MUX10,MUX10 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 18.--19. "MUX9,MUX9 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "MUX8,MUX8 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "MUX7,MUX7 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "MUX6,MUX6 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 10.--11. "MUX5,MUX5 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "MUX4,MUX4 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "MUX3,MUX3 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "MUX2,MUX2 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "MUX1,MUX1 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "MUX0,MUX0 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x6 "AUXSIG1MUX16TO31CFG,CLB XBAR Mux Configuration for Output-1"
|
|
bitfld.long 0x6 30.--31. "MUX31,MUX31 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 28.--29. "MUX30,MUX30 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 26.--27. "MUX29,MUX29 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 24.--25. "MUX28,MUX28 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 22.--23. "MUX27,MUX27 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 20.--21. "MUX26,MUX26 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 18.--19. "MUX25,MUX25 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 16.--17. "MUX24,MUX24 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 14.--15. "MUX23,MUX23 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 12.--13. "MUX22,MUX22 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 10.--11. "MUX21,MUX21 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 8.--9. "MUX20,MUX20 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 6.--7. "MUX19,MUX19 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x6 4.--5. "MUX18,MUX18 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 2.--3. "MUX17,MUX17 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x6 0.--1. "MUX16,MUX16 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x8 "AUXSIG2MUX0TO15CFG,CLB XBAR Mux Configuration for Output-2"
|
|
bitfld.long 0x8 30.--31. "MUX15,MUX15 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "MUX14,MUX14 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "MUX13,MUX13 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "MUX12,MUX12 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "MUX11,MUX11 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "MUX10,MUX10 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "MUX9,MUX9 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "MUX8,MUX8 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "MUX7,MUX7 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "MUX6,MUX6 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 10.--11. "MUX5,MUX5 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "MUX4,MUX4 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "MUX3,MUX3 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--5. "MUX2,MUX2 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "MUX1,MUX1 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "MUX0,MUX0 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0xA "AUXSIG2MUX16TO31CFG,CLB XBAR Mux Configuration for Output-2"
|
|
bitfld.long 0xA 30.--31. "MUX31,MUX31 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 28.--29. "MUX30,MUX30 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 26.--27. "MUX29,MUX29 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 24.--25. "MUX28,MUX28 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 22.--23. "MUX27,MUX27 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 20.--21. "MUX26,MUX26 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 18.--19. "MUX25,MUX25 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 16.--17. "MUX24,MUX24 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 14.--15. "MUX23,MUX23 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 12.--13. "MUX22,MUX22 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 10.--11. "MUX21,MUX21 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 8.--9. "MUX20,MUX20 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 6.--7. "MUX19,MUX19 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
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bitfld.long 0xA 4.--5. "MUX18,MUX18 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 2.--3. "MUX17,MUX17 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xA 0.--1. "MUX16,MUX16 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0xC "AUXSIG3MUX0TO15CFG,CLB XBAR Mux Configuration for Output-3"
|
|
bitfld.long 0xC 30.--31. "MUX15,MUX15 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "MUX14,MUX14 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "MUX13,MUX13 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "MUX12,MUX12 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "MUX11,MUX11 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "MUX10,MUX10 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "MUX9,MUX9 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "MUX8,MUX8 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "MUX7,MUX7 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "MUX6,MUX6 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 10.--11. "MUX5,MUX5 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "MUX4,MUX4 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "MUX3,MUX3 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
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|
bitfld.long 0xC 4.--5. "MUX2,MUX2 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "MUX1,MUX1 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "MUX0,MUX0 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0xE "AUXSIG3MUX16TO31CFG,CLB XBAR Mux Configuration for Output-3"
|
|
bitfld.long 0xE 30.--31. "MUX31,MUX31 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 28.--29. "MUX30,MUX30 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 26.--27. "MUX29,MUX29 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 24.--25. "MUX28,MUX28 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 22.--23. "MUX27,MUX27 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 20.--21. "MUX26,MUX26 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 18.--19. "MUX25,MUX25 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 16.--17. "MUX24,MUX24 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 14.--15. "MUX23,MUX23 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 12.--13. "MUX22,MUX22 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 10.--11. "MUX21,MUX21 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 8.--9. "MUX20,MUX20 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 6.--7. "MUX19,MUX19 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xE 4.--5. "MUX18,MUX18 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 2.--3. "MUX17,MUX17 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0xE 0.--1. "MUX16,MUX16 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x10 "AUXSIG4MUX0TO15CFG,CLB XBAR Mux Configuration for Output-4"
|
|
bitfld.long 0x10 30.--31. "MUX15,MUX15 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 28.--29. "MUX14,MUX14 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 26.--27. "MUX13,MUX13 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 24.--25. "MUX12,MUX12 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "MUX11,MUX11 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 20.--21. "MUX10,MUX10 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "MUX9,MUX9 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "MUX8,MUX8 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "MUX7,MUX7 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "MUX6,MUX6 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "MUX5,MUX5 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. "MUX4,MUX4 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "MUX3,MUX3 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 4.--5. "MUX2,MUX2 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "MUX1,MUX1 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "MUX0,MUX0 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x12 "AUXSIG4MUX16TO31CFG,CLB XBAR Mux Configuration for Output-4"
|
|
bitfld.long 0x12 30.--31. "MUX31,MUX31 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 28.--29. "MUX30,MUX30 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 26.--27. "MUX29,MUX29 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 24.--25. "MUX28,MUX28 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 22.--23. "MUX27,MUX27 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 20.--21. "MUX26,MUX26 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 18.--19. "MUX25,MUX25 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 16.--17. "MUX24,MUX24 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 14.--15. "MUX23,MUX23 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 12.--13. "MUX22,MUX22 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 10.--11. "MUX21,MUX21 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 8.--9. "MUX20,MUX20 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 6.--7. "MUX19,MUX19 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x12 4.--5. "MUX18,MUX18 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 2.--3. "MUX17,MUX17 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x12 0.--1. "MUX16,MUX16 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x14 "AUXSIG5MUX0TO15CFG,CLB XBAR Mux Configuration for Output-5"
|
|
bitfld.long 0x14 30.--31. "MUX15,MUX15 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "MUX14,MUX14 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 26.--27. "MUX13,MUX13 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 24.--25. "MUX12,MUX12 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "MUX11,MUX11 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 20.--21. "MUX10,MUX10 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 18.--19. "MUX9,MUX9 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "MUX8,MUX8 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "MUX7,MUX7 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "MUX6,MUX6 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "MUX5,MUX5 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. "MUX4,MUX4 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "MUX3,MUX3 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 4.--5. "MUX2,MUX2 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "MUX1,MUX1 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "MUX0,MUX0 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x16 "AUXSIG5MUX16TO31CFG,CLB XBAR Mux Configuration for Output-5"
|
|
bitfld.long 0x16 30.--31. "MUX31,MUX31 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 28.--29. "MUX30,MUX30 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 26.--27. "MUX29,MUX29 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 24.--25. "MUX28,MUX28 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 22.--23. "MUX27,MUX27 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 20.--21. "MUX26,MUX26 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 18.--19. "MUX25,MUX25 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 16.--17. "MUX24,MUX24 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 14.--15. "MUX23,MUX23 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 12.--13. "MUX22,MUX22 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 10.--11. "MUX21,MUX21 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 8.--9. "MUX20,MUX20 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 6.--7. "MUX19,MUX19 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x16 4.--5. "MUX18,MUX18 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 2.--3. "MUX17,MUX17 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x16 0.--1. "MUX16,MUX16 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x18 "AUXSIG6MUX0TO15CFG,CLB XBAR Mux Configuration for Output-6"
|
|
bitfld.long 0x18 30.--31. "MUX15,MUX15 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 28.--29. "MUX14,MUX14 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 26.--27. "MUX13,MUX13 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 24.--25. "MUX12,MUX12 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "MUX11,MUX11 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 20.--21. "MUX10,MUX10 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 18.--19. "MUX9,MUX9 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 16.--17. "MUX8,MUX8 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "MUX7,MUX7 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. "MUX6,MUX6 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 10.--11. "MUX5,MUX5 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 8.--9. "MUX4,MUX4 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "MUX3,MUX3 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 4.--5. "MUX2,MUX2 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "MUX1,MUX1 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x18 0.--1. "MUX0,MUX0 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x1A "AUXSIG6MUX16TO31CFG,CLB XBAR Mux Configuration for Output-6"
|
|
bitfld.long 0x1A 30.--31. "MUX31,MUX31 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 28.--29. "MUX30,MUX30 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 26.--27. "MUX29,MUX29 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 24.--25. "MUX28,MUX28 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 22.--23. "MUX27,MUX27 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 20.--21. "MUX26,MUX26 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 18.--19. "MUX25,MUX25 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 16.--17. "MUX24,MUX24 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 14.--15. "MUX23,MUX23 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 12.--13. "MUX22,MUX22 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 10.--11. "MUX21,MUX21 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 8.--9. "MUX20,MUX20 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 6.--7. "MUX19,MUX19 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1A 4.--5. "MUX18,MUX18 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 2.--3. "MUX17,MUX17 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1A 0.--1. "MUX16,MUX16 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x1C "AUXSIG7MUX0TO15CFG,CLB XBAR Mux Configuration for Output-7"
|
|
bitfld.long 0x1C 30.--31. "MUX15,MUX15 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 28.--29. "MUX14,MUX14 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 26.--27. "MUX13,MUX13 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--25. "MUX12,MUX12 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. "MUX11,MUX11 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--21. "MUX10,MUX10 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 18.--19. "MUX9,MUX9 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 16.--17. "MUX8,MUX8 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. "MUX7,MUX7 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. "MUX6,MUX6 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 10.--11. "MUX5,MUX5 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--9. "MUX4,MUX4 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. "MUX3,MUX3 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 4.--5. "MUX2,MUX2 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 2.--3. "MUX1,MUX1 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1C 0.--1. "MUX0,MUX0 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x1E "AUXSIG7MUX16TO31CFG,CLB XBAR Mux Configuration for Output-7"
|
|
bitfld.long 0x1E 30.--31. "MUX31,MUX31 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 28.--29. "MUX30,MUX30 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 26.--27. "MUX29,MUX29 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 24.--25. "MUX28,MUX28 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 22.--23. "MUX27,MUX27 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 20.--21. "MUX26,MUX26 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 18.--19. "MUX25,MUX25 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 16.--17. "MUX24,MUX24 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 14.--15. "MUX23,MUX23 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 12.--13. "MUX22,MUX22 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 10.--11. "MUX21,MUX21 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 8.--9. "MUX20,MUX20 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 6.--7. "MUX19,MUX19 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1E 4.--5. "MUX18,MUX18 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 2.--3. "MUX17,MUX17 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x1E 0.--1. "MUX16,MUX16 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
line.long 0x20 "AUXSIG0MUXENABLE,CLB XBAR Mux Enable Register for Output-0"
|
|
bitfld.long 0x20 31. "MUX31,MUX31 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 30. "MUX30,MUX30 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 29. "MUX29,MUX29 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 28. "MUX28,MUX28 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 27. "MUX27,MUX27 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 26. "MUX26,MUX26 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 25. "MUX25,MUX25 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 24. "MUX24,MUX24 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 23. "MUX23,MUX23 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 22. "MUX22,MUX22 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 21. "MUX21,MUX21 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 20. "MUX20,MUX20 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 19. "MUX19,MUX19 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x20 18. "MUX18,MUX18 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 17. "MUX17,MUX17 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 16. "MUX16,MUX16 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 15. "MUX15,MUX15 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 14. "MUX14,MUX14 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 13. "MUX13,MUX13 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 12. "MUX12,MUX12 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 11. "MUX11,MUX11 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 10. "MUX10,MUX10 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 9. "MUX9,MUX9 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 8. "MUX8,MUX8 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 7. "MUX7,MUX7 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 6. "MUX6,MUX6 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x20 5. "MUX5,MUX5 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 4. "MUX4,MUX4 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 3. "MUX3,MUX3 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 2. "MUX2,MUX2 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 1. "MUX1,MUX1 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x20 0. "MUX0,mux0 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
line.long 0x22 "AUXSIG1MUXENABLE,CLB XBAR Mux Enable Register for Output-1"
|
|
bitfld.long 0x22 31. "MUX31,MUX31 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 30. "MUX30,MUX30 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 29. "MUX29,MUX29 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 28. "MUX28,MUX28 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 27. "MUX27,MUX27 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 26. "MUX26,MUX26 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 25. "MUX25,MUX25 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 24. "MUX24,MUX24 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 23. "MUX23,MUX23 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 22. "MUX22,MUX22 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 21. "MUX21,MUX21 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 20. "MUX20,MUX20 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 19. "MUX19,MUX19 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x22 18. "MUX18,MUX18 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 17. "MUX17,MUX17 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 16. "MUX16,MUX16 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 15. "MUX15,MUX15 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 14. "MUX14,MUX14 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 13. "MUX13,MUX13 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 12. "MUX12,MUX12 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 11. "MUX11,MUX11 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 10. "MUX10,MUX10 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 9. "MUX9,MUX9 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 8. "MUX8,MUX8 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 7. "MUX7,MUX7 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 6. "MUX6,MUX6 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x22 5. "MUX5,MUX5 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 4. "MUX4,MUX4 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 3. "MUX3,MUX3 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 2. "MUX2,MUX2 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 1. "MUX1,MUX1 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x22 0. "MUX0,mux0 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
line.long 0x24 "AUXSIG2MUXENABLE,CLB XBAR Mux Enable Register for Output-2"
|
|
bitfld.long 0x24 31. "MUX31,MUX31 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 30. "MUX30,MUX30 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 29. "MUX29,MUX29 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 28. "MUX28,MUX28 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 27. "MUX27,MUX27 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 26. "MUX26,MUX26 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 25. "MUX25,MUX25 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 24. "MUX24,MUX24 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 23. "MUX23,MUX23 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 22. "MUX22,MUX22 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 21. "MUX21,MUX21 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 20. "MUX20,MUX20 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 19. "MUX19,MUX19 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x24 18. "MUX18,MUX18 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 17. "MUX17,MUX17 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 16. "MUX16,MUX16 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 15. "MUX15,MUX15 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 14. "MUX14,MUX14 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 13. "MUX13,MUX13 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 12. "MUX12,MUX12 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 11. "MUX11,MUX11 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 10. "MUX10,MUX10 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 9. "MUX9,MUX9 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 8. "MUX8,MUX8 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 7. "MUX7,MUX7 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 6. "MUX6,MUX6 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x24 5. "MUX5,MUX5 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 4. "MUX4,MUX4 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 3. "MUX3,MUX3 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 2. "MUX2,MUX2 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 1. "MUX1,MUX1 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x24 0. "MUX0,mux0 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
line.long 0x26 "AUXSIG3MUXENABLE,CLB XBAR Mux Enable Register for Output-3"
|
|
bitfld.long 0x26 31. "MUX31,MUX31 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 30. "MUX30,MUX30 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 29. "MUX29,MUX29 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 28. "MUX28,MUX28 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 27. "MUX27,MUX27 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 26. "MUX26,MUX26 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 25. "MUX25,MUX25 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 24. "MUX24,MUX24 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 23. "MUX23,MUX23 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 22. "MUX22,MUX22 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 21. "MUX21,MUX21 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 20. "MUX20,MUX20 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 19. "MUX19,MUX19 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x26 18. "MUX18,MUX18 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 17. "MUX17,MUX17 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 16. "MUX16,MUX16 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 15. "MUX15,MUX15 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 14. "MUX14,MUX14 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 13. "MUX13,MUX13 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 12. "MUX12,MUX12 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 11. "MUX11,MUX11 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 10. "MUX10,MUX10 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 9. "MUX9,MUX9 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 8. "MUX8,MUX8 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 7. "MUX7,MUX7 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 6. "MUX6,MUX6 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x26 5. "MUX5,MUX5 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 4. "MUX4,MUX4 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 3. "MUX3,MUX3 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 2. "MUX2,MUX2 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 1. "MUX1,MUX1 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x26 0. "MUX0,mux0 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
line.long 0x28 "AUXSIG4MUXENABLE,CLB XBAR Mux Enable Register for Output-4"
|
|
bitfld.long 0x28 31. "MUX31,MUX31 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 30. "MUX30,MUX30 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 29. "MUX29,MUX29 to drive AUXSIG4 of CLB-XBAR" "0,1"
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bitfld.long 0x28 28. "MUX28,MUX28 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 27. "MUX27,MUX27 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 26. "MUX26,MUX26 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 25. "MUX25,MUX25 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 24. "MUX24,MUX24 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 23. "MUX23,MUX23 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 22. "MUX22,MUX22 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 21. "MUX21,MUX21 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 20. "MUX20,MUX20 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 19. "MUX19,MUX19 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
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bitfld.long 0x28 18. "MUX18,MUX18 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 17. "MUX17,MUX17 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 16. "MUX16,MUX16 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 15. "MUX15,MUX15 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 14. "MUX14,MUX14 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 13. "MUX13,MUX13 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 12. "MUX12,MUX12 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 11. "MUX11,MUX11 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 10. "MUX10,MUX10 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 9. "MUX9,MUX9 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 8. "MUX8,MUX8 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 7. "MUX7,MUX7 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 6. "MUX6,MUX6 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
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bitfld.long 0x28 5. "MUX5,MUX5 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 4. "MUX4,MUX4 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 3. "MUX3,MUX3 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 2. "MUX2,MUX2 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 1. "MUX1,MUX1 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x28 0. "MUX0,mux0 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
line.long 0x2A "AUXSIG5MUXENABLE,CLB XBAR Mux Enable Register for Output-5"
|
|
bitfld.long 0x2A 31. "MUX31,MUX31 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 30. "MUX30,MUX30 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 29. "MUX29,MUX29 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 28. "MUX28,MUX28 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 27. "MUX27,MUX27 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 26. "MUX26,MUX26 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 25. "MUX25,MUX25 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 24. "MUX24,MUX24 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 23. "MUX23,MUX23 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 22. "MUX22,MUX22 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 21. "MUX21,MUX21 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 20. "MUX20,MUX20 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 19. "MUX19,MUX19 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
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bitfld.long 0x2A 18. "MUX18,MUX18 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 17. "MUX17,MUX17 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 16. "MUX16,MUX16 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 15. "MUX15,MUX15 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 14. "MUX14,MUX14 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 13. "MUX13,MUX13 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 12. "MUX12,MUX12 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 11. "MUX11,MUX11 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 10. "MUX10,MUX10 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 9. "MUX9,MUX9 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 8. "MUX8,MUX8 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 7. "MUX7,MUX7 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 6. "MUX6,MUX6 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
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bitfld.long 0x2A 5. "MUX5,MUX5 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 4. "MUX4,MUX4 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 3. "MUX3,MUX3 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 2. "MUX2,MUX2 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 1. "MUX1,MUX1 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2A 0. "MUX0,mux0 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
line.long 0x2C "AUXSIG6MUXENABLE,CLB XBAR Mux Enable Register for Output-6"
|
|
bitfld.long 0x2C 31. "MUX31,MUX31 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 30. "MUX30,MUX30 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 29. "MUX29,MUX29 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 28. "MUX28,MUX28 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 27. "MUX27,MUX27 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 26. "MUX26,MUX26 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 25. "MUX25,MUX25 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 24. "MUX24,MUX24 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 23. "MUX23,MUX23 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 22. "MUX22,MUX22 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 21. "MUX21,MUX21 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 20. "MUX20,MUX20 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 19. "MUX19,MUX19 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
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bitfld.long 0x2C 18. "MUX18,MUX18 to drive AUXSIG6 of CLB-XBAR" "0,1"
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|
bitfld.long 0x2C 17. "MUX17,MUX17 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 16. "MUX16,MUX16 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 15. "MUX15,MUX15 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 14. "MUX14,MUX14 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 13. "MUX13,MUX13 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 12. "MUX12,MUX12 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 11. "MUX11,MUX11 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 10. "MUX10,MUX10 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 9. "MUX9,MUX9 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 8. "MUX8,MUX8 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 7. "MUX7,MUX7 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 6. "MUX6,MUX6 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x2C 5. "MUX5,MUX5 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 4. "MUX4,MUX4 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 3. "MUX3,MUX3 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 2. "MUX2,MUX2 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 1. "MUX1,MUX1 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2C 0. "MUX0,mux0 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
line.long 0x2E "AUXSIG7MUXENABLE,CLB XBAR Mux Enable Register for Output-7"
|
|
bitfld.long 0x2E 31. "MUX31,MUX31 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 30. "MUX30,MUX30 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 29. "MUX29,MUX29 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 28. "MUX28,MUX28 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 27. "MUX27,MUX27 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 26. "MUX26,MUX26 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 25. "MUX25,MUX25 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 24. "MUX24,MUX24 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 23. "MUX23,MUX23 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 22. "MUX22,MUX22 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 21. "MUX21,MUX21 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 20. "MUX20,MUX20 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 19. "MUX19,MUX19 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2E 18. "MUX18,MUX18 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 17. "MUX17,MUX17 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 16. "MUX16,MUX16 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 15. "MUX15,MUX15 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 14. "MUX14,MUX14 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 13. "MUX13,MUX13 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 12. "MUX12,MUX12 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 11. "MUX11,MUX11 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 10. "MUX10,MUX10 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 9. "MUX9,MUX9 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 8. "MUX8,MUX8 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 7. "MUX7,MUX7 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 6. "MUX6,MUX6 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x2E 5. "MUX5,MUX5 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 4. "MUX4,MUX4 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 3. "MUX3,MUX3 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 2. "MUX2,MUX2 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 1. "MUX1,MUX1 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x2E 0. "MUX0,mux0 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "AUXSIGOUTINV,CLB XBAR Output Inversion Register"
|
|
bitfld.long 0x0 7. "OUT7,Selects polarity for AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,Selects polarity for AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 5. "OUT5,Selects polarity for AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,Selects polarity for AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 3. "OUT3,Selects polarity for AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,Selects polarity for AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 1. "OUT1,Selects polarity for AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,Selects polarity for AUXSIG0 of CLB-XBAR" "0,1"
|
|
group.long 0x3E++0x3
|
|
line.long 0x0 "AUXSIGLOCK,ClbXbar Configuration Lock register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Write Protection KEY"
|
|
bitfld.long 0x0 0. "LOCK,Locks the configuration for CLB-XBAR" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
newline
|
|
AUTOINDENT.OFF
|