429 lines
20 KiB
Plaintext
429 lines
20 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX93 Specific Menu
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; @Props: Released
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; @Author: NEJ, KRZ
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; @Changelog: 2023-03-14 KRZ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A55, Cortex-M33F
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; @Chip: IMX9311-CA55, IMX9311-CM33, IMX9312-CA55, IMX9312-CM33,
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; IMX9321-CA55, IMX9321-CM33, IMX9322-CA55, IMX9322-CM33,
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; IMX9331-CA55, IMX9331-CM33, IMX9332-CA55, IMX9332-CM33,
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; IMX9351-CA55, IMX9351-CM33, IMX9352-CA55, IMX9352-CM33
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menimx93.men 18835 2025-01-10 12:05:27Z kwisniewski $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)&&CPU.FEATURE(MPUTRANSLATION)
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(
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popup "[:mmu]MMU/MPU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU/MPU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU/MPU Table List" "MMU.List.PageTable"
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IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
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(
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separator
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)
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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ELSE
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(
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
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(
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separator
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)
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF CPU.FEATURE(MPUTRANSLATION)
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(
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popup "[:mmu]MPU"
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(
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menuitem "[:mmu]MPU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MPU Table List" "MMU.List.PageTable"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHEDUMP)||CPU.FEATURE(L1DCACHEDUMP)||CPU.FEATURE(L2CACHEDUMP)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA55")
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(
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popup "[:chip]Core Registers (Cortex-A55)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration"""
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menuitem "[:chip]System Instructions[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration,System Instructions"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller System Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Generic Interrupt Controller System Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Debug Registers"""
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menuitem "[:chip]Activity Monitors Unit[AArch64]" "per , ""AArch64,Activity Monitors Unit"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Watchpoint Registers"""
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separator
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menuitem "[:chip]LORegions Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,LORegions Registers"""
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separator
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menuitem "[:chip]DynamIQ Shared Unit[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,DynamIQ Shared Unit"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller System Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Generic Interrupt Controller System Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Watchpoint Registers"""
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separator
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menuitem "[:chip]DynamIQ Shared Unit[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,DynamIQ Shared Unit"""
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separator
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menuitem "[:chip]Interrupt Controller" "per , ""Core Registers (Cortex-A55),Interrupt Controller"""
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)
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)
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else if (CORENAME()=="CORTEXM33F")
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(
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popup "[:chip]Core Registers (Cortex-M33F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M33F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M33F),Memory Protection Unit (MPU)"""
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menuitem "[:chip]SAU;Security Attribution Unit" "per , ""Core Registers (Cortex-M33F),Security Attribution Unit (SAU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M33F),Nested Vectored Interrupt Controller (NVIC)"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M33F),Floating-point Unit (FPU)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M33F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M33F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M33F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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menuitem "ANA_OSC" "per , ""ANA_OSC"""
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menuitem "AXBS;Crossbar Switch" "per , ""AXBS (Crossbar Switch)"""
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menuitem "BBNSM;Battery-Backed Non-Secure Module" "per , ""BBNSM (Battery-Backed Non-Secure Module)"""
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menuitem "BLK_CTRL_MLMIX;ML Mix Domain Block Control" "per , ""BLK_CTRL_MLMIX (ML Mix Domain Block Control)"""
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menuitem "BLK_CTRL_NICMIX;NIC Mix Block Control" "per , ""BLK_CTRL_NICMIX (NIC Mix Block Control)"""
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menuitem "BLK_CTRL_NS_AONMIX;Always-on Domain/Non-secure Block Control" "per , ""BLK_CTRL_NS_AONMIX (Always-on Domain/Non-secure Block Control)"""
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menuitem "BLK_CTRL_S_AONMIX;Always-on Domain/Secure Block Control" "per , ""BLK_CTRL_S_AONMIX (Always-on Domain/Secure Block Control)"""
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menuitem "BLK_CTRL_WAKEUPMIX;Wake-up Domain Block Control" "per , ""BLK_CTRL_WAKEUPMIX (Wake-up Domain Block Control)"""
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menuitem "CACHE_ECC_MCM;ARM Cortex CM33 ECC MCM" "per , ""CACHE_ECC_MCM (ARM Cortex CM33 ECC MCM)"""
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menuitem "CAN;FlexCAN" "per , ""CAN (FlexCAN)"""
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menuitem "CCM;Clock Controller Module" "per , ""CCM (Clock Controller Module)"""
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menuitem "DDRC;DDR Memory Controller" "per , ""DDRC (DDR Memory Controller)"""
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menuitem "DDRMIX_BLK_CTRL;DDR Mix Domain Block Control" "per , ""DDRMIX_BLK_CTRL (DDR Mix Domain Block Control)"""
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menuitem "EDMA3;Enhanced Direct Memory Access (eDMA3)" "per , ""EDMA3 (Enhanced Direct Memory Access (eDMA3))"""
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menuitem "EDMA3_TCD;eDMA3 Transfer Control Descriptor" "per , ""EDMA3_TCD (eDMA3 Transfer Control Descriptor)"""
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menuitem "EDMA4;Enhanced Direct Memory Access (eDMA4)" "per , ""EDMA4 (Enhanced Direct Memory Access (eDMA4))"""
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menuitem "EDMA4_TCD;eDMA4 Transfer Control Descriptor" "per , ""EDMA4_TCD (eDMA4 Transfer Control Descriptor)"""
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menuitem "ENET;Ethernet" "per , ""ENET (Ethernet)"""
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menuitem "ENET_QOS_TSN;Ethernet Controller with TSN" "per , ""ENET_QOS_TSN (Ethernet Controller with TSN)"""
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menuitem "FLEXIO;Flexible I/O" "per , ""FLEXIO (Flexible I/O)"""
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menuitem "FLEXSPI;Flexible Serial Peripheral Interface" "per , ""FLEXSPI (Flexible Serial Peripheral Interface)"""
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menuitem "FSB" "per , ""FSB"""
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menuitem "GPC_CPU_CTRL;General Power Controller (CPU Mode)" "per , ""GPC_CPU_CTRL (General Power Controller (CPU Mode))"""
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menuitem "GPC_GLOBAL" "per , ""GPC_GLOBAL"""
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menuitem "GPIO;General-Purpose Input/Output" "per , ""GPIO (General-Purpose Input/Output)"""
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menuitem "I3C;Improved Inter-Integrated Circuit" "per , ""I3C (Improved Inter-Integrated Circuit)"""
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menuitem "IOMUXC;IOMUX Controller" "per , ""IOMUXC (IOMUX Controller)"""
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menuitem "IPC;Integrated Peripheral Control" "per , ""IPC (Integrated Peripheral Control)"""
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menuitem "ISI;Image Sensor Interface" "per , ""ISI (Image Sensor Interface)"""
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menuitem "LCDIF;LCD Interface" "per , ""LCDIF (LCD Interface)"""
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menuitem "LPI2C;Low Power Inter-Integrated Circuit" "per , ""LPI2C (Low Power Inter-Integrated Circuit)"""
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menuitem "LPIT;Low Power Periodic Interrupt Timer" "per , ""LPIT (Low Power Periodic Interrupt Timer)"""
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menuitem "LPSPI;Low Power Serial Peripheral Interface" "per , ""LPSPI (Low Power Serial Peripheral Interface)"""
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menuitem "LPTMR;Low-Power Timer" "per , ""LPTMR (Low-Power Timer)"""
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menuitem "LPTPM;Low Power Timer/PWM" "per , ""LPTPM (Low Power Timer/PWM)"""
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menuitem "LPUART;Low Power Universal Asynchronous Receiver/Transmitter" "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter)"""
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menuitem "LPWDOG;Watchdog Timers" "per , ""LPWDOG (Watchdog Timers)"""
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menuitem "MCM;Miscellaneous Control Module" "per , ""MCM (Miscellaneous Control Module)"""
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menuitem "MECC256;Memory ECC Controller" "per , ""MECC256 (Memory ECC Controller)"""
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menuitem "MEDIAMIX_BLK_CTRL;Media Mix Domain Block Control" "per , ""MEDIAMIX_BLK_CTRL (Media Mix Domain Block Control)"""
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menuitem "MIPI_CSI" "per , ""MIPI_CSI"""
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menuitem "MIPI_DSI" "per , ""MIPI_DSI"""
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menuitem "MU;Messaging Unit" "per , ""MU (Messaging Unit)"""
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menuitem "NPU;Neural Processing Unit" "per , ""NPU (Neural Processing Unit)"""
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menuitem "OTFAD;On-The-Fly AES Decryption" "per , ""OTFAD (On-The-Fly AES Decryption)"""
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menuitem "PDM;PDM Microphone Interface" "per , ""PDM (PDM Microphone Interface)"""
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menuitem "PLL" "per , ""PLL"""
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menuitem "PXP;Pixel Pipeline" "per , ""PXP (Pixel Pipeline)"""
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menuitem "S3MUA" "per , ""S3MUA"""
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menuitem "SAI;Synchronous Audio Interface" "per , ""SAI (Synchronous Audio Interface)"""
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menuitem "SAR_ADC;Analog-to-Digital Converter" "per , ""SAR_ADC (Analog-to-Digital Converter)"""
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menuitem "SEMA42;Semaphores2" "per , ""SEMA42 (Semaphores2)"""
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menuitem "SPDIF;Audio Transceiver" "per , ""SPDIF (Audio Transceiver)"""
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menuitem "SRC;System Reset Controller" "per , ""SRC (System Reset Controller)"""
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menuitem "SYS_CTR;System Counter" "per , ""SYS_CTR (System Counter)"""
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menuitem "SYSPM;Performance Monitor" "per , ""SYSPM (Performance Monitor)"""
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menuitem "TCM_ECC_MCM;Tightly Coupled Memory" "per , ""TCM_ECC_MCM (Tightly Coupled Memory)"""
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menuitem "TMU;Thermal Monitoring Unit" "per , ""TMU (Thermal Monitoring Unit)"""
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menuitem "TRDC;Trusted Resource Domain Control" "per , ""TRDC (Trusted Resource Domain Control)"""
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menuitem "TRGMUX;Trigger Mux" "per , ""TRGMUX (Trigger Mux)"""
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menuitem "TSTMR;Timer" "per , ""TSTMR (Timer)"""
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menuitem "USB;Universal Serial Bus Controller" "per , ""USB (Universal Serial Bus Controller)"""
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menuitem "USBNC;USB Non-Core Memory" "per , ""USBNC (USB Non-Core Memory)"""
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menuitem "USDHC;Ultra Secured Digital Host Controller" "per , ""USDHC (Ultra Secured Digital Host Controller)"""
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menuitem "WAKEUP_AHBRM" "per , ""WAKEUP_AHBRM"""
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menuitem "XCACHE;Cache Memory Controller" "per , ""XCACHE (Cache Memory Controller)"""
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)
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)
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