4629 lines
227 KiB
Plaintext
4629 lines
227 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: PY32F071 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-01-13 NEJ
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; @Manufacturer: PUYA - Puya Semiconductors Co., Ltd
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; @Doc: Generated (TRACE32, build: 175665.), based on:
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; PY32F071Cxx.svd (Ver. 1.0.0), PY32F071xx.svd (Ver. 1.0.0)
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; @Core: Cortex-M0+
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; @Chip: PY32F071C1BT6, PY32F071C18T6, PY32F071C1BU6,
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; PY32F071C1BT7, PY32F071K18U6, PY32F071R1BT6,
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; PY32F071R1BU6
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perpy32f071.per 18850 2025-01-14 10:18:27Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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elif (CORENAME()=="CORTEXM0+")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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else
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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endif
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40012400
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "SR,desc SR"
|
|
rbitfld.long 0x0 5. "OVER,desc OVER" "0,1"
|
|
bitfld.long 0x0 4. "STRT,desc STRT" "0,1"
|
|
bitfld.long 0x0 3. "JSTRT,desc JSTRT" "0,1"
|
|
bitfld.long 0x0 2. "JEOC,desc JEOC" "0,1"
|
|
bitfld.long 0x0 1. "EOC,desc EOC" "0,1"
|
|
bitfld.long 0x0 0. "AWD,desc AWD" "0,1"
|
|
line.long 0x4 "CR1,desc CR1"
|
|
bitfld.long 0x4 29. "OVETIE,desc OVETIE" "0,1"
|
|
bitfld.long 0x4 27. "ADSTP,desc ADSTP" "0,1"
|
|
bitfld.long 0x4 24.--25. "RESSEL,desc RESSEL" "0,1,2,3"
|
|
bitfld.long 0x4 23. "AWDEN,desc AWDEN" "0,1"
|
|
bitfld.long 0x4 22. "JAWDEN,desc JAWDEN" "0,1"
|
|
bitfld.long 0x4 13.--15. "DISCNUM,desc DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "JDISCEN,desc JDISCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DISCEN,desc DISCEN" "0,1"
|
|
bitfld.long 0x4 10. "JAUTO,desc JAUTO" "0,1"
|
|
bitfld.long 0x4 9. "AWDSGL,desc AWDSGL" "0,1"
|
|
bitfld.long 0x4 8. "SCAN,desc SCAN" "0,1"
|
|
bitfld.long 0x4 7. "JEOCIE,desc JEOCIE" "0,1"
|
|
bitfld.long 0x4 6. "AWDIE,desc AWDIE" "0,1"
|
|
bitfld.long 0x4 5. "EOCIE,desc EOCIE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "AWDCH,desc AWDCH"
|
|
line.long 0x8 "CR2,desc CR2"
|
|
bitfld.long 0x8 26.--27. "VERFBUFFERSEL,desc VERFBUFFERSEL" "0,1,2,3"
|
|
bitfld.long 0x8 25. "VERFBUFFERE,desc VERFBUFFERE" "0,1"
|
|
bitfld.long 0x8 23. "TSVREFE,desc TSVREFE" "0,1"
|
|
bitfld.long 0x8 22. "SWSTART,desc SWSTART" "0,1"
|
|
bitfld.long 0x8 21. "JSWSTART,desc JSWSTART" "0,1"
|
|
bitfld.long 0x8 20. "EXTTRIG,desc EXTTRIG" "0,1"
|
|
bitfld.long 0x8 17.--19. "EXTSEL,desc EXTSEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "JEXTTRIG,desc JEXTTRIG" "0,1"
|
|
bitfld.long 0x8 12.--14. "JEXTSEL,desc JEXTSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 11. "ALIGN,desc ALIGN" "0,1"
|
|
bitfld.long 0x8 8. "DMA,desc DMA" "0,1"
|
|
bitfld.long 0x8 3. "RSTCAL,desc RSTCAL" "0,1"
|
|
bitfld.long 0x8 2. "CAL,desc CAL" "0,1"
|
|
bitfld.long 0x8 1. "CONT,desc CONT" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ADON,desc ADON" "0,1"
|
|
line.long 0xC "SMPR1,desc SMPR1"
|
|
bitfld.long 0xC 9.--11. "SMP23,desc SMP23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 6.--8. "SMP22,desc SMP22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 3.--5. "SMP21,desc SMP21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "SMP20,desc SMP20" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SMPR2,desc SMPR2"
|
|
bitfld.long 0x10 27.--29. "SMP19,desc SMP19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 24.--26. "SMP18,desc SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 21.--23. "SMP17,desc SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 18.--20. "SMP16,desc SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 15.--17. "SMP15,desc SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 12.--14. "SMP14,desc SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 9.--11. "SMP13,desc SMP13" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 6.--8. "SMP12,desc SMP12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 3.--5. "SMP11,desc SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. "SMP10,desc SMP10" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SMPR3,desc SMPR2"
|
|
bitfld.long 0x14 27.--29. "SMP9,desc SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,desc SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,desc SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,desc SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,desc SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,desc SMP4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 9.--11. "SMP3,desc SMP3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 6.--8. "SMP2,desc SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,desc SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,desc SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "JOFR1,desc JOFR1"
|
|
hexmask.long.word 0x18 0.--11. 1. "JOFFSET1,desc JOFFSET1"
|
|
line.long 0x1C "JOFR2,desc JOFR2"
|
|
hexmask.long.word 0x1C 0.--11. 1. "JOFFSET2,desc JOFFSET2"
|
|
line.long 0x20 "JOFR3,desc JOFR3"
|
|
hexmask.long.word 0x20 0.--11. 1. "JOFFSET3,desc JOFFSET3"
|
|
line.long 0x24 "JOFR4,desc JOFR4"
|
|
hexmask.long.word 0x24 0.--11. 1. "JOFFSET4,desc JOFFSET4"
|
|
line.long 0x28 "HTR,desc HTR"
|
|
hexmask.long.word 0x28 0.--11. 1. "HT,desc HT"
|
|
line.long 0x2C "LTR,desc LTR"
|
|
hexmask.long.word 0x2C 0.--11. 1. "LT,desc LT"
|
|
line.long 0x30 "SQR1,desc SQR1"
|
|
hexmask.long.byte 0x30 20.--23. 1. "L,desc L"
|
|
hexmask.long.byte 0x30 15.--19. 1. "SQ16,desc SQ16"
|
|
hexmask.long.byte 0x30 10.--14. 1. "SQ15,desc SQ15"
|
|
hexmask.long.byte 0x30 5.--9. 1. "SQ14,desc SQ14"
|
|
hexmask.long.byte 0x30 0.--4. 1. "SQ13,desc SQ13"
|
|
line.long 0x34 "SQR2,desc SQR2"
|
|
hexmask.long.byte 0x34 25.--29. 1. "SQ12,desc SQ12"
|
|
hexmask.long.byte 0x34 20.--24. 1. "SQ11,desc SQ11"
|
|
hexmask.long.byte 0x34 15.--19. 1. "SQ10,desc SQ10"
|
|
hexmask.long.byte 0x34 10.--14. 1. "SQ9,desc SQ9"
|
|
hexmask.long.byte 0x34 5.--9. 1. "SQ8,desc SQ8"
|
|
hexmask.long.byte 0x34 0.--4. 1. "SQ7,desc SQ7"
|
|
line.long 0x38 "SQR3,desc SQR3"
|
|
hexmask.long.byte 0x38 25.--29. 1. "SQ6,desc SQ6"
|
|
hexmask.long.byte 0x38 20.--24. 1. "SQ5,desc SQ5"
|
|
hexmask.long.byte 0x38 15.--19. 1. "SQ4,desc SQ4"
|
|
hexmask.long.byte 0x38 10.--14. 1. "SQ3,desc SQ3"
|
|
hexmask.long.byte 0x38 5.--9. 1. "SQ2,desc SQ2"
|
|
hexmask.long.byte 0x38 0.--4. 1. "SQ1,desc SQ1"
|
|
line.long 0x3C "JSQR,desc JSQR"
|
|
hexmask.long.byte 0x3C 20.--23. 1. "JL,desc JL"
|
|
hexmask.long.byte 0x3C 15.--19. 1. "JSQ4,desc JSQ4"
|
|
hexmask.long.byte 0x3C 10.--14. 1. "JSQ3,desc JSQ3"
|
|
hexmask.long.byte 0x3C 5.--9. 1. "JSQ2,desc JSQ2"
|
|
hexmask.long.byte 0x3C 0.--4. 1. "JSQ1,desc JSQ1"
|
|
rgroup.long 0x40++0x13
|
|
line.long 0x0 "JDR1,desc JDR1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDR1,desc JDR1"
|
|
line.long 0x4 "JDR2,desc JDR2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDR2,desc JDR2"
|
|
line.long 0x8 "JDR3,desc JDR3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDR3,desc JDR3"
|
|
line.long 0xC "JDR4,desc JDR4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDR4,desc JDR4"
|
|
line.long 0x10 "DR,desc DR"
|
|
hexmask.long.word 0x10 0.--15. 1. "DATA,desc DATA"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CCSR,desc CCSR"
|
|
rbitfld.long 0x0 31. "CALON,desc CALON" "0,1"
|
|
bitfld.long 0x0 30. "CAPSUC,desc CAPSUC" "0,1"
|
|
bitfld.long 0x0 29. "OFFSUC,desc OFFSUC" "0,1"
|
|
bitfld.long 0x0 15. "CALSET,desc CALSET" "0,1"
|
|
bitfld.long 0x0 14. "CALBYP,desc CALBYP" "0,1"
|
|
bitfld.long 0x0 12.--13. "CALSMP,desc CALSMP" "0,1,2,3"
|
|
bitfld.long 0x0 11. "CALSEL,desc CALSEL" "0,1"
|
|
tree.end
|
|
tree "COMP (Comparator)"
|
|
base ad:0x0
|
|
tree "COMP1"
|
|
base ad:0x40010200
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,COMP control and status register"
|
|
bitfld.long 0x0 30. "COMP_OUT,Comparator output status" "0,1"
|
|
sif (cpuis("PY32F071K*")||cpuis("PY32F071R*"))
|
|
bitfld.long 0x0 27. "VCSEL,VCSEL" "0,1"
|
|
bitfld.long 0x0 26. "VCDIV_EN,VCDIV_EN" "0,1"
|
|
endif
|
|
sif (cpuis("PY32F071C*"))
|
|
bitfld.long 0x0 26.--27. "COMP_VCSEL,COMP_VCSEL" "0,1,2,3"
|
|
endif
|
|
hexmask.long.byte 0x0 20.--25. 1. "VCDIV,VCDIV"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator power mode selector" "0,1,2,3"
|
|
bitfld.long 0x0 16. "HYST,Comparator hysteresis enable selector" "0,1"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator polarity selector" "0,1"
|
|
bitfld.long 0x0 11. "WINMODE,Comparator non-inverting input selector for window mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "INPSEL,Comparator signal selector for non-inverting input"
|
|
hexmask.long.byte 0x0 2.--5. 1. "INMSEL,Comparator signal selector for inverting input INM"
|
|
bitfld.long 0x0 0. "EN,COMP enable bit" "0,1"
|
|
line.long 0x4 "FR,Comparator Filter register"
|
|
hexmask.long.word 0x4 16.--31. 1. "FLTCNT1,Comparator filter and counter"
|
|
bitfld.long 0x4 0. "FLTEN1,Filter enable bit" "0,1"
|
|
tree.end
|
|
tree "COMP2"
|
|
base ad:0x40010210
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,COMP control and status register"
|
|
bitfld.long 0x0 30. "COMP_OUT,Comparator output status" "0,1"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator power mode selector" "0,1,2,3"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator polarity selector" "0,1"
|
|
bitfld.long 0x0 11. "WINMODE,Comparator non-inverting input selector for window mode" "0,1"
|
|
hexmask.long.byte 0x0 6.--9. 1. "INPSEL,Comparator signal selector for non-inverting input"
|
|
hexmask.long.byte 0x0 2.--5. 1. "INMSEL,Comparator signal selector for inverting input INM"
|
|
bitfld.long 0x0 1. "HYST,Comparator hysteresis enable selector" "0,1"
|
|
bitfld.long 0x0 0. "EN,COMP enable bit" "0,1"
|
|
line.long 0x4 "FR,Comparator Filter register"
|
|
hexmask.long.word 0x4 16.--31. 1. "FLTCNT2,Comparator filter and counter"
|
|
bitfld.long 0x4 0. "FLTEN2,Filter enable bit" "0,1"
|
|
tree.end
|
|
tree "COMP3"
|
|
base ad:0x40010220
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,COMP control and status register"
|
|
bitfld.long 0x0 30. "COMP_OUT,Comparator output status" "0,1"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator power mode selector" "0,1,2,3"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator polarity selector" "0,1"
|
|
hexmask.long.byte 0x0 6.--9. 1. "INPSEL,Comparator signal selector for non-inverting input"
|
|
hexmask.long.byte 0x0 2.--5. 1. "INMSEL,Comparator signal selector for inverting input INM"
|
|
bitfld.long 0x0 1. "HYST,Comparator hysteresis enable selector" "0,1"
|
|
bitfld.long 0x0 0. "EN,COMP enable bit" "0,1"
|
|
line.long 0x4 "FR,Comparator Filter register"
|
|
hexmask.long.word 0x4 16.--31. 1. "FLTCNT3,Comparator filter and counter"
|
|
bitfld.long 0x4 0. "FLTEN3,Filter enable bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40023000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data Register"
|
|
line.long 0x4 "IDR,Independent Data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "IDR,Independent Data register"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 0. "RESET,Reset bit" "0,1"
|
|
tree.end
|
|
tree "CTC (Clock Calibration Controller)"
|
|
base ad:0x40006C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL0,desc CTL0"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TRIMVALUE,desc TRIMVALUE"
|
|
bitfld.long 0x0 7. "SWREFPUL,desc SWREFPUL" "0,1"
|
|
bitfld.long 0x0 6. "AUTOTRIM,desc AUTOTRIM" "0,1"
|
|
bitfld.long 0x0 5. "CNTEN,desc CNTEN" "0,1"
|
|
bitfld.long 0x0 3. "EREFIE,desc EREFIE" "0,1"
|
|
bitfld.long 0x0 2. "ERRIE,desc ERRIE" "0,1"
|
|
bitfld.long 0x0 1. "CKWARNIE,desc CKWARNIE" "0,1"
|
|
bitfld.long 0x0 0. "CKOKIE,desc CKOKIE" "0,1"
|
|
line.long 0x4 "CTL1,desc CTL1"
|
|
bitfld.long 0x4 31. "REFPOL,desc REFPOL" "0,1"
|
|
bitfld.long 0x4 28.--29. "REFSEL,desc REFSEL" "0,1,2,3"
|
|
bitfld.long 0x4 24.--26. "REFPSC,desc REFPSC" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CKLIM,desc CKLIM"
|
|
hexmask.long.word 0x4 0.--15. 1. "RLVALUE,desc RLVALUE"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,desc SR"
|
|
hexmask.long.word 0x0 16.--31. 1. "REFCAP,desc REFCAP"
|
|
bitfld.long 0x0 15. "REFDIR,desc REFDIR" "0,1"
|
|
bitfld.long 0x0 10. "TRIMERR,desc TRIMERR" "0,1"
|
|
bitfld.long 0x0 9. "REFMISS,desc REFMISS" "0,1"
|
|
bitfld.long 0x0 8. "CKERR,desc CKERR" "0,1"
|
|
bitfld.long 0x0 3. "EREFIF,desc EREFIF" "0,1"
|
|
bitfld.long 0x0 2. "ERRIF,desc ERRIF" "0,1"
|
|
bitfld.long 0x0 1. "CKWARNIF,desc CKWARNIF" "0,1"
|
|
bitfld.long 0x0 0. "CKOKIF,desc CKOKIF" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "INTC,desc INTC"
|
|
bitfld.long 0x0 3. "EREFIC,desc EREFIC" "0,1"
|
|
bitfld.long 0x0 2. "ERRIC,desc ERRIC" "0,1"
|
|
bitfld.long 0x0 1. "CKWARNIC,desc CKWARNIC" "0,1"
|
|
bitfld.long 0x0 0. "CKOKIC,desc CKOKIC" "0,1"
|
|
tree.end
|
|
tree "DAC (Digital-to-Analog Controller)"
|
|
base ad:0x40007400
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "CR,desc CR"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,desc DMAUDRIE2" "0,1"
|
|
bitfld.long 0x0 28. "DMAEN2,desc DMAEN2" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,desc MAMP2"
|
|
bitfld.long 0x0 22.--23. "WAVE2,desc WAVE2" "0,1,2,3"
|
|
bitfld.long 0x0 19.--21. "TSEL2,desc TSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18. "TEN2,desc TEN2" "0,1"
|
|
bitfld.long 0x0 17. "BOFF2,desc BOFF2" "0,1"
|
|
bitfld.long 0x0 16. "EN2,desc EN2" "0,1"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,desc DMAUDRIE1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAEN1,desc DMAEN1" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,desc MAMP1"
|
|
bitfld.long 0x0 6.--7. "WAVE1,desc WAVE1" "0,1,2,3"
|
|
bitfld.long 0x0 3.--5. "TSEL1,desc TSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "TEN1,desc TEN1" "0,1"
|
|
bitfld.long 0x0 1. "BOFF1,desc BOFF1" "0,1"
|
|
bitfld.long 0x0 0. "EN1,desc EN1" "0,1"
|
|
line.long 0x4 "SWTRIGR,desc SWTRIGR"
|
|
bitfld.long 0x4 1. "SWTRIG2,desc SWTRIG2" "0,1"
|
|
bitfld.long 0x4 0. "SWTRIG1,desc SWTRIG1" "0,1"
|
|
line.long 0x8 "DHR12R1,desc DHR12R1"
|
|
hexmask.long.word 0x8 0.--11. 1. "DACC1DHR,desc DACC1DHR"
|
|
line.long 0xC "DHR12L1,desc DHR12L1"
|
|
hexmask.long.word 0xC 4.--15. 1. "DACC1DHR,desc DACC1DHR"
|
|
line.long 0x10 "DHR8R1,desc DHR8R1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DACC1DHR,desc DACC1DHR"
|
|
line.long 0x14 "DHR12R2,desc DHR12R2"
|
|
hexmask.long.word 0x14 0.--11. 1. "DACC2DHR,desc DACC2DHR"
|
|
line.long 0x18 "DHR12L2,desc DHR12L2"
|
|
hexmask.long.word 0x18 4.--15. 1. "DACC2DHR,desc DACC2DHR"
|
|
line.long 0x1C "DHR8R2,desc DHR8R2"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "DACC2DHR,desc DACC2DHR"
|
|
line.long 0x20 "DHR12RD,desc DHR12RD"
|
|
hexmask.long.word 0x20 16.--27. 1. "DACC2DHR,desc DACC2DHR"
|
|
hexmask.long.word 0x20 0.--11. 1. "DACC1DHR,desc DACC1DHR"
|
|
line.long 0x24 "DHR12LD,desc DHR12LD"
|
|
hexmask.long.word 0x24 20.--31. 1. "DACC2DHR,desc DACC2DHR"
|
|
hexmask.long.word 0x24 4.--15. 1. "DACC1DHR,desc DACC1DHR"
|
|
line.long 0x28 "DHR8RD,desc DHR8RD"
|
|
hexmask.long.byte 0x28 8.--15. 1. "DACC2DHR,desc DACC2DHR"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DACC1DHR,desc DACC1DHR"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "DOR1,desc DOR1"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,desc DACC1DOR"
|
|
line.long 0x4 "DOR2,desc DOR2"
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,desc DACC2DOR"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "SR,desc SR"
|
|
bitfld.long 0x0 29. "DMAUDR2,desc DMAUDR2" "0,1"
|
|
bitfld.long 0x0 13. "DMAUDR1,desc DMAUDR1" "0,1"
|
|
tree.end
|
|
tree "DBGMCU (Debug Support)"
|
|
base ad:0x40015800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "IDCODE,MCU Device ID Code Register"
|
|
hexmask.long 0x0 0.--30. 1. "REV_ID,REV_ID"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "CR,Debug MCU Configuration Register"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
bitfld.long 0x0 0. "DBG_SLEEP,Debug Sleep Mode" "0,1"
|
|
line.long 0x4 "APB_FZ1,APB Freeze Register1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM_STOP,Debug LPTIM stopped when Core is halted" "0,1"
|
|
rbitfld.long 0x4 22. "DBG_I2C2_SMBUS_TIMEOUT,DBG_I2C2_SMBUS_TIMEOUT" "0,1"
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,DBG_I2C1_SMBUS_TIMEOUT" "0,1"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Debug Independent Wachdog stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Debug Window Wachdog stopped when Core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Debug RTC stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 5. "DBG_TIMER7_STOP,Debug Timer 7 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 4. "DBG_TIMER6_STOP,Debug Timer 6 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 1. "DBG_TIMER3_STOP,Debug Timer 3 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
line.long 0x8 "APB_FZ2,APB Freeze Register2"
|
|
bitfld.long 0x8 18. "DBG_TIMER17_STOP,Debug Timer 17 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIMER16_STOP,Debug Timer 16 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x8 16. "DBG_TIMER15_STOP,Debug Timer 15 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x8 15. "DBG_TIMER14_STOP,Debug Timer 14 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x8 11. "DBG_TIMER1_STOP,Debug Timer 1 stopped when Core is halted" "0,1"
|
|
tree.end
|
|
tree "DIV (Hardware Divider)"
|
|
base ad:0x40023800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DEND,Dividend"
|
|
hexmask.long 0x0 0.--31. 1. "DEND,Dividend"
|
|
line.long 0x4 "SOR,Divisor"
|
|
hexmask.long 0x4 0.--31. 1. "SOR,Divisor"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "QUOT,Quotient"
|
|
hexmask.long 0x0 0.--31. 1. "QUOT,Quotient"
|
|
line.long 0x4 "REMA,Remainder"
|
|
hexmask.long 0x4 0.--31. 1. "REMA,Remainder"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SIGN,des SIGN"
|
|
bitfld.long 0x0 0. "DIV_SIGN,des DIV_SIGN" "0,1"
|
|
line.long 0x4 "STAT,des SIGN"
|
|
bitfld.long 0x4 1. "DIV_ZERO,des DIV_ZERO" "0,1"
|
|
bitfld.long 0x4 0. "DIV_END,des DIV_END" "0,1"
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x40020000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,desc ISR"
|
|
bitfld.long 0x0 27. "TEIF7,desc TEIF7" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,desc HTIF7" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,desc TCIF7" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,desc GIF7" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,desc TEIF6" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,desc HTIF6" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,desc TCIF6" "0,1"
|
|
bitfld.long 0x0 20. "GIF6,desc GIF6" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,desc TEIF5" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,desc HTIF5" "0,1"
|
|
bitfld.long 0x0 17. "TCIF5,desc TCIF5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "GIF5,desc GIF5" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,desc TEIF4" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,desc HTIF4" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,desc TCIF4" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,desc GIF4" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,desc TEIF3" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,desc HTIF3" "0,1"
|
|
bitfld.long 0x0 9. "TCIF3,desc TCIF3" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,desc GIF3" "0,1"
|
|
bitfld.long 0x0 7. "TEIF2,desc TEIF2" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,desc HTIF2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TCIF2,desc TCIF2" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,desc GIF2" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,desc TEIF1" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,desc HTIF1" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,desc TCIF1" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,desc GIF1" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,desc IFCR"
|
|
bitfld.long 0x0 27. "CTEIF7,desc CTEIF7" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,desc CHTIF7" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,desc CTCIF7" "0,1"
|
|
bitfld.long 0x0 24. "CGIF7,desc CGIF7" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,desc CTEIF6" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,desc CHTIF6" "0,1"
|
|
bitfld.long 0x0 21. "CTCIF6,desc CTCIF6" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,desc CGIF6" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,desc CTEIF5" "0,1"
|
|
bitfld.long 0x0 18. "CHTIF5,desc CHTIF5" "0,1"
|
|
bitfld.long 0x0 17. "CTCIF5,desc CTCIF5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CGIF5,desc CGIF5" "0,1"
|
|
bitfld.long 0x0 15. "CTEIF4,desc CTEIF4" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,desc CHTIF4" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,desc CTCIF4" "0,1"
|
|
bitfld.long 0x0 12. "CGIF4,desc CGIF4" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,desc CTEIF3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,desc CHTIF3" "0,1"
|
|
bitfld.long 0x0 9. "CTCIF3,desc CTCIF3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,desc CGIF3" "0,1"
|
|
bitfld.long 0x0 7. "CTEIF2,desc CTEIF2" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,desc CHTIF2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CTCIF2,desc CTCIF2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,desc CGIF2" "0,1"
|
|
bitfld.long 0x0 3. "CTEIF1,desc CTEIF1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,desc CHTIF1" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,desc CTCIF1" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,desc CGIF1" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "CCR1,desc CCR1"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR1,desc CNDTR1"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR1,desc CPAR1"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR1,desc CMAR1"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CCR2,desc CCR2"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR2,desc CNDTR2"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR2,desc CPAR2"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR2,desc CMAR2"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "CCR3,desc CCR3"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR3,desc CNDTR3"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR3,desc CPAR3"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR3,desc CMAR3"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CCR4,desc CCR4"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR4,desc CNDTR4"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR4,desc CPAR4"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR4,desc CMAR4"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "CCR5,desc CCR5"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR5,desc CNDTR5"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR5,desc CPAR5"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR5,desc CMAR5"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "CCR6,desc CCR6"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR6,desc CNDTR6"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR6,desc CPAR6"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR6,desc CMAR6"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CCR7,desc CCR7"
|
|
bitfld.long 0x0 14. "MEM2MEM,desc MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,desc PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,desc MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,desc PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,desc MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,desc PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,desc CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,desc TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,desc HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,desc EN" "0,1"
|
|
line.long 0x4 "CNDTR7,desc CNDTR7"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,desc NDT"
|
|
line.long 0x8 "CPAR7,desc CPAR7"
|
|
hexmask.long 0x8 0.--31. 1. "PA,desc PA"
|
|
line.long 0xC "CMAR7,desc CMAR7"
|
|
hexmask.long 0xC 0.--31. 1. "MA,desc MA"
|
|
tree.end
|
|
tree "EXTI (Extended Interrupts and Events Controller)"
|
|
base ad:0x40021800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "RTSR,EXTI rising trigger selection register"
|
|
bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 16. "RT16,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0x4 "FTSR,EXTI falling trigger selection register"
|
|
bitfld.long 0x4 20. "FT20,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 16. "FT16,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0x8 "SWIER,EXTI software interrupt event register"
|
|
bitfld.long 0x8 20. "SWI20,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 18. "SWI18,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 17. "SWI17,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 16. "SWI16,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 15. "SWI15,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 14. "SWI14,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 13. "SWI13,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 11. "SWI11,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 8. "SWI8,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "SWI6,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 4. "SWI4,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Rising trigger event configuration bit of Configurable Event input" "0,1"
|
|
line.long 0xC "PR,EXTI pending register"
|
|
bitfld.long 0xC 20. "PR20,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 18. "PR18,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 17. "PR17,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 16. "PR16,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 15. "PR15,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 14. "PR14,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 13. "PR13,configurable event inputs x rising edge Pending bit" "0,1"
|
|
bitfld.long 0xC 12. "PR12,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 11. "PR11,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 10. "PR10,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 9. "PR9,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 8. "PR8,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 7. "PR7,configurable event inputs x rising edge Pending bit." "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "PR6,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 5. "PR5,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 4. "PR4,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 3. "PR3,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 2. "PR2,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 1. "PR1,configurable event inputs x rising edge Pending bit." "0,1"
|
|
bitfld.long 0xC 0. "PR0,configurable event inputs x rising edge Pending bit." "0,1"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "EXTICR1,EXTI external interrupt selection register"
|
|
bitfld.long 0x0 24.--25. "EXTI3,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "EXTI2,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EXTI1,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EXTI0,GPIO port selection" "0,1,2,3"
|
|
line.long 0x4 "EXTICR2,EXTI external interrupt selection register"
|
|
bitfld.long 0x4 24.--25. "EXTI7,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "EXTI6,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "EXTI5,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "EXTI4,GPIO port selection" "0,1,2,3"
|
|
line.long 0x8 "EXTICR3,EXTI external interrupt selection register"
|
|
bitfld.long 0x8 24.--25. "EXTI11,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "EXTI10,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "EXTI9,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "EXTI8,GPIO port selection" "0,1,2,3"
|
|
line.long 0xC "EXTICR4,EXTI external interrupt selection register"
|
|
bitfld.long 0xC 24.--25. "EXTI15,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "EXTI14,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "EXTI13,GPIO port selection" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "EXTI12,GPIO port selection" "0,1,2,3"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "IMR,EXTI CPU wakeup with interrupt mask register"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 19. "IM19,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 18. "IM18,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 17. "IM17,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 15. "IM15,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 14. "IM14,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 13. "IM13,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 12. "IM12,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 11. "IM11,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 10. "IM10,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 9. "IM9,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IM8,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on event input" "0,1"
|
|
line.long 0x4 "EMR,EXTI CPU wakeup with event mask register"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 20. "EM20,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 19. "EM19,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 18. "EM18,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 17. "EM17,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 15. "EM15,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 14. "EM14,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 13. "EM13,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 12. "EM12,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 11. "EM11,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 10. "EM10,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 9. "EM9,CPU wakeup with event mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EM8,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event mask on event input" "0,1"
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event mask on event input" "0,1"
|
|
tree.end
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ACR,desc ACR"
|
|
bitfld.long 0x0 0.--1. "LATENCY,desc LATENCY" "0,1,2,3"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "KEYR,desc KEYR"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,desc KEY"
|
|
line.long 0x4 "OPTKEYR,desc OPTKEYR"
|
|
hexmask.long 0x4 0.--31. 1. "OPTKEY,desc OPTKEY"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SR,desc SR"
|
|
rbitfld.long 0x0 16. "BSY,desc BSY" "0,1"
|
|
bitfld.long 0x0 15. "OPTVERR,desc OPTVERR" "0,1"
|
|
bitfld.long 0x0 4. "WRPERR,desc WRPERR" "0,1"
|
|
bitfld.long 0x0 0. "EOP,desc EOP" "0,1"
|
|
line.long 0x4 "CR,desc CR"
|
|
bitfld.long 0x4 31. "LOCK,desc LOCK" "0,1"
|
|
bitfld.long 0x4 30. "OPTLOCK,desc OPTLOCK" "0,1"
|
|
bitfld.long 0x4 27. "OBL_LAUNCH,desc OBL_LAUNCH" "0,1"
|
|
bitfld.long 0x4 25. "ERRIE,desc ERRIE" "0,1"
|
|
bitfld.long 0x4 24. "EOPIE,desc EOPIE" "0,1"
|
|
bitfld.long 0x4 19. "PGSTRT,desc PGSTRT" "0,1"
|
|
bitfld.long 0x4 17. "OPTSTRT,desc OPTSTRT" "0,1"
|
|
bitfld.long 0x4 11. "SER,desc SER" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MER,desc MER" "0,1"
|
|
bitfld.long 0x4 1. "PER,desc PER" "0,1"
|
|
bitfld.long 0x4 0. "PG,desc PG" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "OPTR,desc OPTR"
|
|
bitfld.long 0x0 15. "IWDG_STOP,desc IWDG_STOP" "0,1"
|
|
bitfld.long 0x0 14. "NBOOT1,desc nBOOT1" "0,1"
|
|
bitfld.long 0x0 13. "NRST_MODE,desc NRST_MODE" "0,1"
|
|
bitfld.long 0x0 12. "WWDG_SW,desc WWDG_SW" "0,1"
|
|
bitfld.long 0x0 11. "IWDG_SW,desc IWDG_SW" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDP,desc RDP"
|
|
line.long 0x4 "SDKR,desc SDKR"
|
|
bitfld.long 0x4 13.--15. "BOR_LEV,desc BOR_LEV" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 8.--12. 1. "SDK_END,desc SDK_END"
|
|
bitfld.long 0x4 5. "BOR_EN,desc BOR_EN" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SDK_STRT,desc SDK_STRT"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "WRPR,desc WRPR"
|
|
hexmask.long.word 0x0 0.--15. 1. "WRP,desc WRP"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "STCR,desc STCR"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLEEP_TIME,desc SLEEP_TIME"
|
|
bitfld.long 0x0 0. "SLEEP_EN,desc SLEEP_EN" "0,1"
|
|
group.long 0x100++0x23
|
|
line.long 0x0 "TS0,desc TS0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TS0,desc TS0"
|
|
line.long 0x4 "TS1,desc TS1"
|
|
hexmask.long.word 0x4 0.--8. 1. "TS1,desc TS1"
|
|
line.long 0x8 "TS2P,desc TS2P"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TS2P,desc TS2P"
|
|
line.long 0xC "TPS3,desc TPS3"
|
|
hexmask.long.word 0xC 0.--10. 1. "TPS3,desc TPS3"
|
|
line.long 0x10 "TS3,desc TS3"
|
|
hexmask.long.byte 0x10 0.--7. 1. "TS3,desc TS3"
|
|
line.long 0x14 "PERTPE,desc PERTPE"
|
|
hexmask.long.tbyte 0x14 0.--16. 1. "PERTPE,desc PERTPE"
|
|
line.long 0x18 "SMERTPE,desc SMERTPE"
|
|
hexmask.long.tbyte 0x18 0.--16. 1. "SMERTPE,desc SMERTPE"
|
|
line.long 0x1C "PRGTPE,desc PRGTPE"
|
|
hexmask.long.word 0x1C 0.--15. 1. "PRGTPE,desc PRGTPE"
|
|
line.long 0x20 "PRETPE,desc PRETPE"
|
|
hexmask.long.word 0x20 0.--13. 1. "PRETPE,desc PRETPE"
|
|
tree.end
|
|
tree "GPIO (General-Purpose I/Os)"
|
|
base ad:0x0
|
|
tree "GPIOA"
|
|
base ad:0x50000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y=0-15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "ID13,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "ID11,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "ID9,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "ID7,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port input data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "ID3,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y=0-15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "OD13,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "OD11,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "OD9,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "OD7,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "OD3,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y=0-15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=0-15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock (LCKK)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=0-15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y=0-7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y=8-15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x50000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y=0-15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "ID13,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "ID11,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "ID9,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "ID7,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port input data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "ID3,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y=0-15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "OD13,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "OD11,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "OD9,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "OD7,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "OD3,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y=0-15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=0-15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock (LCKK)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=0-15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y=0-7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y=8-15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x50000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y=0-15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "ID13,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "ID11,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "ID9,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "ID7,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port input data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "ID3,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y=0-15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "OD13,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "OD11,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "OD9,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "OD7,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "OD3,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y=0-15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=0-15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock (LCKK)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=0-15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y=0-7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y=8-15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOF"
|
|
base ad:0x50001400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y=0-15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y=0-15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration bits (y=0-15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "ID13,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "ID11,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "ID9,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "ID7,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port input data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "ID3,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "ID1,Port input data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port input data (y=0-15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "OD13,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "OD11,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "OD9,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "OD7,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "OD3,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "OD1,Port output data (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data (y=0-15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=0-15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock (LCKK)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=0-15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=0-15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=0-15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x bit y (y=0-7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x bit y (y=0-7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x bit y (y=8-15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x bit y (y=8-15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 15. "SWRST,desc SWRST" "0,1"
|
|
bitfld.long 0x0 13. "ALERT,desc ALERT" "0,1"
|
|
bitfld.long 0x0 12. "PEC,desc PEC" "0,1"
|
|
bitfld.long 0x0 11. "POS,desc POS" "0,1"
|
|
bitfld.long 0x0 10. "ACK,desc ACK" "0,1"
|
|
bitfld.long 0x0 9. "STOP,desc STOP" "0,1"
|
|
bitfld.long 0x0 8. "START,desc START" "0,1"
|
|
bitfld.long 0x0 7. "NOSTRETCH,desc NOSTRETCH" "0,1"
|
|
bitfld.long 0x0 6. "ENGC,desc ENGC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENPEC,desc ENPEC" "0,1"
|
|
bitfld.long 0x0 4. "ENARP,desc ENARP" "0,1"
|
|
bitfld.long 0x0 3. "SMBTYPE,desc SMBTYPE" "0,1"
|
|
bitfld.long 0x0 1. "SMBUS,desc SMBUS" "0,1"
|
|
bitfld.long 0x0 0. "PE,desc PE" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 12. "LAST,desc LAST" "0,1"
|
|
bitfld.long 0x4 11. "DMAEN,desc DMAEN" "0,1"
|
|
bitfld.long 0x4 10. "ITBUFEN,desc ITBUFEN" "0,1"
|
|
bitfld.long 0x4 9. "ITEVTEN,desc ITEVTEN" "0,1"
|
|
bitfld.long 0x4 8. "ITERREN,desc ITERREN" "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "FREQ,desc FREQ"
|
|
line.long 0x8 "OAR1,desc OAR1"
|
|
bitfld.long 0x8 15. "ADDMODE,desc ADDMODE" "0,1"
|
|
bitfld.long 0x8 8.--9. "ADD8_9,desc ADD8_9" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADD1_7,desc ADD1_7"
|
|
bitfld.long 0x8 0. "ADD0,desc ADD0" "0,1"
|
|
line.long 0xC "OAR2,desc OAR2"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADD2,desc ADD2"
|
|
bitfld.long 0xC 0. "ENDUAL,desc ENDUAL" "0,1"
|
|
line.long 0x10 "DR,desc DR"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,desc DR"
|
|
line.long 0x14 "SR1,desc SR1"
|
|
bitfld.long 0x14 15. "SMBALERT,desc SMBALERT" "0,1"
|
|
bitfld.long 0x14 14. "TIMEOUT,desc TIMEOUT" "0,1"
|
|
bitfld.long 0x14 12. "PECERR,desc PECERR" "0,1"
|
|
bitfld.long 0x14 11. "OVR,desc OVR" "0,1"
|
|
bitfld.long 0x14 10. "AF,desc AF" "0,1"
|
|
bitfld.long 0x14 9. "ARLO,desc ARLO" "0,1"
|
|
bitfld.long 0x14 8. "BERR,desc BERR" "0,1"
|
|
rbitfld.long 0x14 7. "TXE,desc TXE" "0,1"
|
|
rbitfld.long 0x14 6. "RXNE,desc RXNE" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 4. "STOPF,desc STOPF" "0,1"
|
|
rbitfld.long 0x14 3. "ADD10,desc ADD10" "0,1"
|
|
rbitfld.long 0x14 2. "BTF,desc BTF" "0,1"
|
|
rbitfld.long 0x14 1. "ADDR,desc ADDR" "0,1"
|
|
rbitfld.long 0x14 0. "SB,desc SB" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR2,desc SR2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PEC,desc PEC"
|
|
bitfld.long 0x0 7. "DUALF,desc DUALF" "0,1"
|
|
bitfld.long 0x0 6. "SMBHOST,desc SMBHOST" "0,1"
|
|
bitfld.long 0x0 5. "SMBDEFAULT,desc SMBDEFAULT" "0,1"
|
|
bitfld.long 0x0 4. "GENCALL,desc GENCALL" "0,1"
|
|
bitfld.long 0x0 2. "TRA,desc TRA" "0,1"
|
|
bitfld.long 0x0 1. "BUSY,desc BUSY" "0,1"
|
|
bitfld.long 0x0 0. "MSL,desc MSL" "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "CCR,desc CCR"
|
|
bitfld.long 0x0 15. "FS,desc FS" "0,1"
|
|
bitfld.long 0x0 14. "DUTY,desc DUTY" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "CCR,desc CCR"
|
|
line.long 0x4 "TRISE,desc TRISE"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRISE,desc TRISE"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 15. "SWRST,desc SWRST" "0,1"
|
|
bitfld.long 0x0 13. "ALERT,desc ALERT" "0,1"
|
|
bitfld.long 0x0 12. "PEC,desc PEC" "0,1"
|
|
bitfld.long 0x0 11. "POS,desc POS" "0,1"
|
|
bitfld.long 0x0 10. "ACK,desc ACK" "0,1"
|
|
bitfld.long 0x0 9. "STOP,desc STOP" "0,1"
|
|
bitfld.long 0x0 8. "START,desc START" "0,1"
|
|
bitfld.long 0x0 7. "NOSTRETCH,desc NOSTRETCH" "0,1"
|
|
bitfld.long 0x0 6. "ENGC,desc ENGC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENPEC,desc ENPEC" "0,1"
|
|
bitfld.long 0x0 4. "ENARP,desc ENARP" "0,1"
|
|
bitfld.long 0x0 3. "SMBTYPE,desc SMBTYPE" "0,1"
|
|
bitfld.long 0x0 1. "SMBUS,desc SMBUS" "0,1"
|
|
bitfld.long 0x0 0. "PE,desc PE" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 12. "LAST,desc LAST" "0,1"
|
|
bitfld.long 0x4 11. "DMAEN,desc DMAEN" "0,1"
|
|
bitfld.long 0x4 10. "ITBUFEN,desc ITBUFEN" "0,1"
|
|
bitfld.long 0x4 9. "ITEVTEN,desc ITEVTEN" "0,1"
|
|
bitfld.long 0x4 8. "ITERREN,desc ITERREN" "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "FREQ,desc FREQ"
|
|
line.long 0x8 "OAR1,desc OAR1"
|
|
bitfld.long 0x8 15. "ADDMODE,desc ADDMODE" "0,1"
|
|
bitfld.long 0x8 8.--9. "ADD8_9,desc ADD8_9" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADD1_7,desc ADD1_7"
|
|
bitfld.long 0x8 0. "ADD0,desc ADD0" "0,1"
|
|
line.long 0xC "OAR2,desc OAR2"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADD2,desc ADD2"
|
|
bitfld.long 0xC 0. "ENDUAL,desc ENDUAL" "0,1"
|
|
line.long 0x10 "DR,desc DR"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DR,desc DR"
|
|
line.long 0x14 "SR1,desc SR1"
|
|
bitfld.long 0x14 15. "SMBALERT,desc SMBALERT" "0,1"
|
|
bitfld.long 0x14 14. "TIMEOUT,desc TIMEOUT" "0,1"
|
|
bitfld.long 0x14 12. "PECERR,desc PECERR" "0,1"
|
|
bitfld.long 0x14 11. "OVR,desc OVR" "0,1"
|
|
bitfld.long 0x14 10. "AF,desc AF" "0,1"
|
|
bitfld.long 0x14 9. "ARLO,desc ARLO" "0,1"
|
|
bitfld.long 0x14 8. "BERR,desc BERR" "0,1"
|
|
rbitfld.long 0x14 7. "TXE,desc TXE" "0,1"
|
|
rbitfld.long 0x14 6. "RXNE,desc RXNE" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 4. "STOPF,desc STOPF" "0,1"
|
|
rbitfld.long 0x14 3. "ADD10,desc ADD10" "0,1"
|
|
rbitfld.long 0x14 2. "BTF,desc BTF" "0,1"
|
|
rbitfld.long 0x14 1. "ADDR,desc ADDR" "0,1"
|
|
rbitfld.long 0x14 0. "SB,desc SB" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR2,desc SR2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PEC,desc PEC"
|
|
bitfld.long 0x0 7. "DUALF,desc DUALF" "0,1"
|
|
bitfld.long 0x0 6. "SMBHOST,desc SMBHOST" "0,1"
|
|
bitfld.long 0x0 5. "SMBDEFAULT,desc SMBDEFAULT" "0,1"
|
|
bitfld.long 0x0 4. "GENCALL,desc GENCALL" "0,1"
|
|
bitfld.long 0x0 2. "TRA,desc TRA" "0,1"
|
|
bitfld.long 0x0 1. "BUSY,desc BUSY" "0,1"
|
|
bitfld.long 0x0 0. "MSL,desc MSL" "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "CCR,desc CCR"
|
|
bitfld.long 0x0 15. "FS,desc FS" "0,1"
|
|
bitfld.long 0x0 14. "DUTY,desc DUTY" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "CCR,desc CCR"
|
|
line.long 0x4 "TRISE,desc TRISE"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRISE,desc TRISE"
|
|
tree.end
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register (IWDG_KR)"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register (IWDG_PR)"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register (IWDG_RLR)"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register (IWDG_SR)"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
tree.end
|
|
tree "LCD (Liquid Crystal Controller)"
|
|
base ad:0x40002400
|
|
group.long 0x0++0x53
|
|
line.long 0x0 "CR0,Control register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CONTRAST,CONTRAST"
|
|
bitfld.long 0x0 9.--11. "BSEL,BSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "DUTY,DUTY" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5. "BIAS,BIAS" "0,1"
|
|
bitfld.long 0x0 1.--2. "LCDCLK,LCDCLK" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,EN" "0,1"
|
|
line.long 0x4 "CR1,CR1"
|
|
bitfld.long 0x4 11. "INTF,INTF" "0,1"
|
|
bitfld.long 0x4 10. "DMAEN,DMAEN" "0,1"
|
|
bitfld.long 0x4 9. "IE,IE" "0,1"
|
|
bitfld.long 0x4 8. "MODE,MODE" "0,1"
|
|
bitfld.long 0x4 6. "BLINKEN,BLINKEN" "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "BLINKCNT,BLINKCNT"
|
|
line.long 0x8 "INTCLR,INTCLR"
|
|
bitfld.long 0x8 10. "INTF_CLR,INTF_CLR" "0,1"
|
|
line.long 0xC "POEN0,POEN0"
|
|
bitfld.long 0xC 31. "S31,S31" "0,1"
|
|
bitfld.long 0xC 30. "S30,S30" "0,1"
|
|
bitfld.long 0xC 29. "S29,S29" "0,1"
|
|
bitfld.long 0xC 28. "S28,S28" "0,1"
|
|
bitfld.long 0xC 27. "S27,S27" "0,1"
|
|
bitfld.long 0xC 26. "S26,S26" "0,1"
|
|
bitfld.long 0xC 25. "S25,S25" "0,1"
|
|
bitfld.long 0xC 24. "S24,S24" "0,1"
|
|
bitfld.long 0xC 23. "S23,S23" "0,1"
|
|
bitfld.long 0xC 22. "S22,S22" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "S21,S21" "0,1"
|
|
bitfld.long 0xC 20. "S20,S20" "0,1"
|
|
bitfld.long 0xC 19. "S19,S19" "0,1"
|
|
bitfld.long 0xC 18. "S18,S18" "0,1"
|
|
bitfld.long 0xC 17. "S17,S17" "0,1"
|
|
bitfld.long 0xC 16. "S16,S16" "0,1"
|
|
bitfld.long 0xC 15. "S15,S15" "0,1"
|
|
bitfld.long 0xC 14. "S14,S14" "0,1"
|
|
bitfld.long 0xC 13. "S13,S13" "0,1"
|
|
bitfld.long 0xC 12. "S12,S12" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "S11,S11" "0,1"
|
|
bitfld.long 0xC 10. "S10,S10" "0,1"
|
|
bitfld.long 0xC 9. "S9,S9" "0,1"
|
|
bitfld.long 0xC 8. "S8,S8" "0,1"
|
|
bitfld.long 0xC 7. "S7,S7" "0,1"
|
|
bitfld.long 0xC 6. "S6,S6" "0,1"
|
|
bitfld.long 0xC 5. "S5,S5" "0,1"
|
|
bitfld.long 0xC 4. "S4,S4" "0,1"
|
|
bitfld.long 0xC 3. "S3,S3" "0,1"
|
|
bitfld.long 0xC 2. "S2,S2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "S1,S1" "0,1"
|
|
bitfld.long 0xC 0. "S0,S0" "0,1"
|
|
line.long 0x10 "POEN1,POEN1"
|
|
bitfld.long 0x10 12. "MUX,MUX" "0,1"
|
|
bitfld.long 0x10 11. "C3,C3" "0,1"
|
|
bitfld.long 0x10 10. "C2,C2" "0,1"
|
|
bitfld.long 0x10 9. "C1,C1" "0,1"
|
|
bitfld.long 0x10 8. "C0,C0" "0,1"
|
|
bitfld.long 0x10 7. "S36C7,S36" "0,1"
|
|
bitfld.long 0x10 6. "S37C6,S37" "0,1"
|
|
bitfld.long 0x10 5. "S38C5,S38" "0,1"
|
|
bitfld.long 0x10 4. "S39C4,S39" "0,1"
|
|
bitfld.long 0x10 3. "S35,S35" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "S34,S34" "0,1"
|
|
bitfld.long 0x10 1. "S33,S33" "0,1"
|
|
bitfld.long 0x10 0. "S32,S32" "0,1"
|
|
line.long 0x14 "RAM0,des RAM0"
|
|
hexmask.long 0x14 0.--31. 1. "D,des D"
|
|
line.long 0x18 "RAM1,des RAM1"
|
|
hexmask.long 0x18 0.--31. 1. "D,des D"
|
|
line.long 0x1C "RAM2,des RAM2"
|
|
hexmask.long 0x1C 0.--31. 1. "D,des D"
|
|
line.long 0x20 "RAM3,des RAM3"
|
|
hexmask.long 0x20 0.--31. 1. "D,des D"
|
|
line.long 0x24 "RAM4,des RAM4"
|
|
hexmask.long 0x24 0.--31. 1. "D,des D"
|
|
line.long 0x28 "RAM5,des RAM5"
|
|
hexmask.long 0x28 0.--31. 1. "D,des D"
|
|
line.long 0x2C "RAM6,des RAM6"
|
|
hexmask.long 0x2C 0.--31. 1. "D,des D"
|
|
line.long 0x30 "RAM7,des RAM7"
|
|
hexmask.long 0x30 0.--31. 1. "D,des D"
|
|
line.long 0x34 "RAM8,des RAM8"
|
|
hexmask.long.byte 0x34 0.--7. 1. "D,des D"
|
|
line.long 0x38 "RAM9,des RAM9"
|
|
hexmask.long.byte 0x38 0.--7. 1. "D,des D"
|
|
line.long 0x3C "RAM10,des RAM10"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "D,des D"
|
|
line.long 0x40 "RAM11,des RAM11"
|
|
hexmask.long.byte 0x40 0.--7. 1. "D,des D"
|
|
line.long 0x44 "RAM12,des RAM12"
|
|
hexmask.long.byte 0x44 0.--7. 1. "D,des D"
|
|
line.long 0x48 "RAM13,des RAM13"
|
|
hexmask.long.byte 0x48 0.--7. 1. "D,des D"
|
|
line.long 0x4C "RAM14,des RAM14"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "D,des D"
|
|
line.long 0x50 "RAM15,des RAM15"
|
|
hexmask.long.byte 0x50 0.--7. 1. "D,des D"
|
|
tree.end
|
|
tree "LPTIM (Low Power Timer)"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload match update OK" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload match update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload match update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload matchInterrupt Enable" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,LPTIM counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
tree.end
|
|
tree "OPA (Operational Amplifier)"
|
|
base ad:0x40010300
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "CR0,CR0 register"
|
|
bitfld.long 0x0 11. "OP3OEN1,OP3OEN1" "0,1"
|
|
bitfld.long 0x0 6. "OP2OEN1,OP2OEN1" "0,1"
|
|
bitfld.long 0x0 1. "OP1OEN1,OP1OEN1" "0,1"
|
|
line.long 0x4 "CR1,CR1 register"
|
|
bitfld.long 0x4 7. "EN3,EN3" "0,1"
|
|
bitfld.long 0x4 6. "EN2,EN2" "0,1"
|
|
bitfld.long 0x4 5. "EN1,EN1" "0,1"
|
|
tree.end
|
|
tree "PWR (Power Management)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,Power control register 1"
|
|
bitfld.long 0x0 19. "HSION_CTRL,HSI open time control" "0,1"
|
|
bitfld.long 0x0 14. "LPR,Low-power run" "0,1"
|
|
bitfld.long 0x0 12.--13. "FLS_SLPTIME,Flash wait time after wakeup from the stop mode" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1"
|
|
bitfld.long 0x0 4. "BIAS_CR_SEL,MR Bias current selection" "0,1"
|
|
bitfld.long 0x0 0.--2. "BIAS_CR,MR Bias current" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CR2,Power control register 2"
|
|
bitfld.long 0x4 9.--11. "FLT_TIME,Digital filter time configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8. "FLTEN,Digital filter enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDT,Power voltage detector threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2. "SRCSEL,Power voltage detector volatage selection" "0,1"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector enable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SR,Power status register"
|
|
bitfld.long 0x0 11. "PVDO,PVD output" "0,1"
|
|
tree.end
|
|
tree "RCC (Reset/Clock Controller)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR,Clock control register"
|
|
bitfld.long 0x0 25. "PLLRDY,PLL clock ready flag" "0,1"
|
|
bitfld.long 0x0 24. "PLLON,PLL enable" "0,1"
|
|
bitfld.long 0x0 21.--22. "ADC_DIV,ADC Frequency Division" "0,1,2,3"
|
|
bitfld.long 0x0 19. "CSSON,Clock security system enable" "0,1"
|
|
bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0,1"
|
|
bitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0,1"
|
|
bitfld.long 0x0 16. "HSEON,HSE clock enable" "0,1"
|
|
bitfld.long 0x0 11.--13. "HSIDIV,HSI16 clock division factor" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0,1"
|
|
bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0,1"
|
|
line.long 0x4 "ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.word 0x4 16.--24. 1. "LSI_TRIM,LSI clock trimming"
|
|
bitfld.long 0x4 13.--15. "HSI_FS,HSI frequency selection" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x4 0.--12. 1. "HSI_TRIM,HSI clock trimming"
|
|
line.long 0x8 "CFGR,Clock configuration register"
|
|
bitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 12.--14. "PPRE,APB prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 8.--11. 1. "HPRE,AHB prescaler"
|
|
rbitfld.long 0x8 3.--5. "SWS,System clock switch status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SW,System clock switch" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PLLCFGR,PLL configuration register"
|
|
bitfld.long 0xC 2.--3. "PLLMUL,PLLMUL" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PLLSRC,PLL clock source selection" "0,1,2,3"
|
|
line.long 0x10 "ECSCR,External clock source control register"
|
|
bitfld.long 0x10 20.--21. "LSE_STARTUP,LSE_STARTUP" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "LSE_DRIVER,LSE clock driver selection" "0,1,2,3"
|
|
bitfld.long 0x10 3.--4. "HSE_STARTUP,HSE_STARTUP" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "HSE_DRV,HSE_DRV" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CIER,Clock interrupt enable register"
|
|
bitfld.long 0x0 5. "PLLRDYIE,PLL ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYIE,HSI ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock secure system interrupt flag" "0,1"
|
|
bitfld.long 0x0 8. "CSSF,HSE clock secure system interrupt flag" "0,1"
|
|
bitfld.long 0x0 5. "PLLRDYF,PLL ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "CICR,Clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE clock secure system interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 8. "CSSC,clock secure system interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 5. "PLLRDYC,PLL ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0,1"
|
|
group.long 0x24++0x1F
|
|
line.long 0x0 "IOPRSTR,GPIO reset register"
|
|
bitfld.long 0x0 5. "GPIOFRST,I/O port F reset" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,I/O port F reset" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,I/O port A reset" "0,1"
|
|
line.long 0x4 "AHBRSTR,AHB peripheral reset register"
|
|
bitfld.long 0x4 24. "DIVRST,DIV reset" "0,1"
|
|
bitfld.long 0x4 12. "CRCRST,CRC reset" "0,1"
|
|
bitfld.long 0x4 0. "DMARST,DMA reset" "0,1"
|
|
line.long 0x8 "APBRSTR1,APB peripheral reset register 1"
|
|
bitfld.long 0x8 31. "LPTIMRST,Low Power Timer reset" "0,1"
|
|
bitfld.long 0x8 30. "OPARST,OPARST" "0,1"
|
|
bitfld.long 0x8 29. "DACRST,DACRST" "0,1"
|
|
bitfld.long 0x8 28. "PWRRST,Power interface reset" "0,1"
|
|
bitfld.long 0x8 27. "CTCRST,CTCRST" "0,1"
|
|
bitfld.long 0x8 23. "USBRST,USB reset" "0,1"
|
|
bitfld.long 0x8 22. "I2C2RST,I2C2 reset" "0,1"
|
|
bitfld.long 0x8 21. "I2C1RST,I2C1 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
bitfld.long 0x8 17. "USART2RST,USART2 reset" "0,1"
|
|
bitfld.long 0x8 14. "SPI2RST,SPI2 reset" "0,1"
|
|
bitfld.long 0x8 11. "WWDGRST,WWDG reset" "0,1"
|
|
bitfld.long 0x8 10. "RTCAPBRST,RTCAPB reset" "0,1"
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TIM3RST,TIM3 timer reset" "0,1"
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
line.long 0xC "APBRSTR2,APB peripheral reset register 2"
|
|
bitfld.long 0xC 23. "LCDRST,LCD reset" "0,1"
|
|
bitfld.long 0xC 22. "COMP3RST,COMP3 reset" "0,1"
|
|
bitfld.long 0xC 21. "COMP2RST,COMP2 reset" "0,1"
|
|
bitfld.long 0xC 20. "COMP1RST,COMP1 reset" "0,1"
|
|
bitfld.long 0xC 18. "TIM17RST,TIM17 reset" "0,1"
|
|
bitfld.long 0xC 17. "TIM16RST,TIM16 reset" "0,1"
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 reset" "0,1"
|
|
bitfld.long 0xC 15. "TIM14RST,TIM14 reset" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0xC 12. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0xC 11. "TIM1RST,TIM1 reset" "0,1"
|
|
bitfld.long 0xC 10. "DBGRST,DBG reset" "0,1"
|
|
bitfld.long 0xC 9. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0xC 0. "SYSCFGRST,SYSCFG reset" "0,1"
|
|
line.long 0x10 "IOPENR,GPIO clock enable register"
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable" "0,1"
|
|
line.long 0x14 "AHBENR,AHB peripheral clock enable register"
|
|
bitfld.long 0x14 24. "DIVEN,DIVEN" "0,1"
|
|
bitfld.long 0x14 12. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x14 9. "SRAMEN,SRAM memory interface clock enable" "0,1"
|
|
bitfld.long 0x14 8. "FLASHEN,Flash memory interface clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
line.long 0x18 "APBENR1,APB peripheral clock enable register 1"
|
|
bitfld.long 0x18 31. "LPTIMEN,LPTIM clock enable" "0,1"
|
|
bitfld.long 0x18 30. "OPAEN,OPA clock enable" "0,1"
|
|
bitfld.long 0x18 29. "DACEN,DAC clock enable" "0,1"
|
|
bitfld.long 0x18 28. "PWREN,Power interface clock enable" "0,1"
|
|
bitfld.long 0x18 27. "CTCEN,CTC clock enable" "0,1"
|
|
bitfld.long 0x18 23. "USBEN,USB clock enable" "0,1"
|
|
bitfld.long 0x18 22. "I2C2EN,I2C2 clock enable" "0,1"
|
|
bitfld.long 0x18 21. "I2C1EN,I2C1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
bitfld.long 0x18 17. "USART2EN,USART2 clock enable" "0,1"
|
|
bitfld.long 0x18 14. "SPI2EN,SPI2 clock enable" "0,1"
|
|
bitfld.long 0x18 11. "WWDGEN,WWDG clock enable" "0,1"
|
|
sif (cpuis("PY32F071C*"))
|
|
bitfld.long 0x18 10. "TIMDIVEN,desc TIMDIVEN" "0,1"
|
|
endif
|
|
sif (cpuis("PY32F071K*")||cpuis("PY32F071R*"))
|
|
bitfld.long 0x18 10. "RTCAPBEN,RTC APB clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
bitfld.long 0x18 1. "TIM3EN,TIM3 timer clock enable" "0,1"
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
line.long 0x1C "APBENR2,APB peripheral clock enable register 2"
|
|
bitfld.long 0x1C 23. "LCDEN,LCD clock enable" "0,1"
|
|
bitfld.long 0x1C 22. "COMP3EN,COMP3 clock enable" "0,1"
|
|
bitfld.long 0x1C 21. "COMP2EN,COMP2 clock enable" "0,1"
|
|
bitfld.long 0x1C 20. "COMP1EN,COMP1 clock enable" "0,1"
|
|
bitfld.long 0x1C 18. "TIM17EN,TIM17 clock enable" "0,1"
|
|
bitfld.long 0x1C 17. "TIM16EN,TIM16 clock enable" "0,1"
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 clock enable" "0,1"
|
|
bitfld.long 0x1C 15. "TIM14EN,TIM14 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 14. "USART1EN,USART1 clock enable" "0,1"
|
|
bitfld.long 0x1C 12. "SPI1EN,SPI1 clock enable" "0,1"
|
|
bitfld.long 0x1C 11. "TIM1EN,TIM1 clock enable" "0,1"
|
|
bitfld.long 0x1C 10. "DBGEN,DBG clock enable" "0,1"
|
|
bitfld.long 0x1C 9. "ADCEN,ADCEN clock enable" "0,1"
|
|
bitfld.long 0x1C 0. "SYSCFGEN,SYSCFG COMP and VREFBUF clock enable" "0,1"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CCIPR,Peripherals independent clock configuration register"
|
|
bitfld.long 0x0 18.--19. "LPTIM1SEL,LPTIM1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 10. "COMP3SEL,COMP3 clock source selection" "0,1"
|
|
bitfld.long 0x0 9. "COMP2SEL,COMP2 clock source selection" "0,1"
|
|
bitfld.long 0x0 8. "COMP1SEL,COMP1 clock source selection" "0,1"
|
|
bitfld.long 0x0 7. "PVDSEL,PVD detect clock source selection" "0,1"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "BDCR,RTC domain control register"
|
|
bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output selection" "0,1"
|
|
bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO) enable" "0,1"
|
|
bitfld.long 0x0 16. "BDRST,RTC domain software reset" "0,1"
|
|
bitfld.long 0x0 15. "RTCEN,RTC clock source enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LSECSSD,LSE CSS detect" "0,1"
|
|
bitfld.long 0x0 5. "LSECSSON,LSE CSS enable" "0,1"
|
|
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0,1"
|
|
line.long 0x4 "CSR,Control/status register"
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset flag" "0,1"
|
|
bitfld.long 0x4 23. "RMVF,Remove reset flags" "0,1"
|
|
bitfld.long 0x4 8. "NRST_FLTDIS,NRST_FLTDIS oscillator ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0,1"
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CRH,desc CRH"
|
|
bitfld.long 0x0 2. "OWIE,desc OWIE" "0,1"
|
|
bitfld.long 0x0 1. "ALRIE,desc ALRIE" "0,1"
|
|
bitfld.long 0x0 0. "SECIE,desc SECIE" "0,1"
|
|
line.long 0x4 "CRL,desc CRL"
|
|
rbitfld.long 0x4 5. "RTOFF,desc RTOFF" "0,1"
|
|
bitfld.long 0x4 4. "CNF,desc CNF" "0,1"
|
|
bitfld.long 0x4 3. "RSF,desc RSF" "0,1"
|
|
bitfld.long 0x4 2. "OWF,desc OWF" "0,1"
|
|
bitfld.long 0x4 1. "ALRF,desc ALRF" "0,1"
|
|
bitfld.long 0x4 0. "SECF,desc SECF" "0,1"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "PRLH,desc PRLH"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRL,desc PRL"
|
|
line.long 0x4 "PRLL,desc PRLL"
|
|
hexmask.long.word 0x4 0.--15. 1. "PRL,desc PRL"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "DIVH,desc DIVH"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DIV,desc DIV"
|
|
line.long 0x4 "DIVL,desc DIVL"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIV,desc DIV"
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "CNTH,desc CNTH"
|
|
hexmask.long.word 0x0 0.--15. 1. "RTC_CNT,desc RTC_CNT"
|
|
line.long 0x4 "CNTL,desc CNTL"
|
|
hexmask.long.word 0x4 0.--15. 1. "RTC_CNT,desc RTC_CNT"
|
|
line.long 0x8 "ALRH,desc ALRH"
|
|
hexmask.long.word 0x8 0.--15. 1. "RTC_ALR,desc RTC_ALR"
|
|
line.long 0xC "ALRL,desc ALRL"
|
|
hexmask.long.word 0xC 0.--15. 1. "RTC_ALR,desc RTC_ALR"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BKP_RTCCR,desc BKP_RTCCR"
|
|
bitfld.long 0x0 9. "ASOS,desc ASOS" "0,1"
|
|
bitfld.long 0x0 8. "ASOE,desc ASOE" "0,1"
|
|
bitfld.long 0x0 7. "CCO,desc CCO" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CAL,desc CAL"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 15. "BIDIMODE,desc BIDIMODE" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,desc BIDIOE" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,desc CRCEN" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,desc CRCNEXT" "0,1"
|
|
bitfld.long 0x0 11. "DDF,desc DDF" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,desc RXONLY" "0,1"
|
|
bitfld.long 0x0 9. "SSM,desc SSM" "0,1"
|
|
bitfld.long 0x0 8. "SSI,desc SSI" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,desc LSBFIRST" "0,1"
|
|
bitfld.long 0x0 6. "SPE,desc SPE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,desc BR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,desc MSTR" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,desc CPOL" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,desc CPHA" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 14. "LDMA_TX,desc LDMA_TX" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,desc LDMA_RX" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,desc FRXTH" "0,1"
|
|
bitfld.long 0x4 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,desc ERRIE" "0,1"
|
|
bitfld.long 0x4 4. "CLRTXFIFO,desc CLRTXFIFO" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,desc SSOE" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,desc TXDMAEN" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,desc RXDMAEN" "0,1"
|
|
line.long 0x8 "SR,desc SR"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,desc FTLVL" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,desc FRLVL" "0,1,2,3"
|
|
rbitfld.long 0x8 7. "BSY,desc BSY" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,desc OVR" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,desc MODF" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,desc CRCERR" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,desc UDR" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,desc CHSIDE" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,desc TXE" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,desc RXNE" "0,1"
|
|
line.long 0xC "DR,desc DR"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,desc DR"
|
|
line.long 0x10 "CRCPR,desc CRCPR"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,desc CRCPOLY"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,desc RXCRCR"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXCRC,desc RXCRC"
|
|
line.long 0x4 "TXCRCR,desc TXCRCR"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXCRC,desc TXCRC"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,desc I2SCFGR"
|
|
bitfld.long 0x0 11. "I2SMOD,desc I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,desc I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,desc I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,desc PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,desc I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,desc CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,desc DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,desc CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,desc I2SPR"
|
|
bitfld.long 0x4 9. "MCKOE,desc MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,desc ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,desc I2SDIV"
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 15. "BIDIMODE,desc BIDIMODE" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,desc BIDIOE" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,desc CRCEN" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,desc CRCNEXT" "0,1"
|
|
bitfld.long 0x0 11. "DDF,desc DDF" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,desc RXONLY" "0,1"
|
|
bitfld.long 0x0 9. "SSM,desc SSM" "0,1"
|
|
bitfld.long 0x0 8. "SSI,desc SSI" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,desc LSBFIRST" "0,1"
|
|
bitfld.long 0x0 6. "SPE,desc SPE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,desc BR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,desc MSTR" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,desc CPOL" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,desc CPHA" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 14. "LDMA_TX,desc LDMA_TX" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,desc LDMA_RX" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,desc FRXTH" "0,1"
|
|
bitfld.long 0x4 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,desc ERRIE" "0,1"
|
|
bitfld.long 0x4 4. "CLRTXFIFO,desc CLRTXFIFO" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,desc SSOE" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,desc TXDMAEN" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,desc RXDMAEN" "0,1"
|
|
line.long 0x8 "SR,desc SR"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,desc FTLVL" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,desc FRLVL" "0,1,2,3"
|
|
rbitfld.long 0x8 7. "BSY,desc BSY" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,desc OVR" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,desc MODF" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,desc CRCERR" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,desc UDR" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,desc CHSIDE" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,desc TXE" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,desc RXNE" "0,1"
|
|
line.long 0xC "DR,desc DR"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,desc DR"
|
|
line.long 0x10 "CRCPR,desc CRCPR"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,desc CRCPOLY"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,desc RXCRCR"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXCRC,desc RXCRC"
|
|
line.long 0x4 "TXCRCR,desc TXCRCR"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXCRC,desc TXCRC"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,desc I2SCFGR"
|
|
bitfld.long 0x0 11. "I2SMOD,desc I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,desc I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,desc I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,desc PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,desc I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,desc CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,desc DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,desc CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,desc I2SPR"
|
|
bitfld.long 0x4 9. "MCKOE,desc MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,desc ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,desc I2SDIV"
|
|
tree.end
|
|
tree.end
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CFGR1,desc CFGR1"
|
|
bitfld.long 0x0 24. "GPIO_AHB_SEL,desc GPIO_AHB_SEL" "0,1"
|
|
bitfld.long 0x0 16.--18. "ETR_SRC_TIM3,desc ETR_SRC_TIM3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "ETR_SRC_TIM2,desc ETR_SRC_TIM2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "ETR_SRC_TIM1,desc ETR_SRC_TIM1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "TIM3_IC1_SRC,desc TIM3_IC1_SRC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "TIM2_IC4_SRC,desc TIM2_IC4_SRC" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "TIM1_IC1_SRC,desc TIM1_IC1_SRC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MEM_MODE,desc MEM_MODE" "0,1,2,3"
|
|
line.long 0x4 "CFGR2,desc CFGR2"
|
|
bitfld.long 0x4 23. "COMP3_OCREF_CLR_TIM3,desc COMP3_OCREF_CLR_TIM3" "0,1"
|
|
bitfld.long 0x4 22. "COMP3_OCREF_CLR_TIM2,desc COMP3_OCREF_CLR_TIM2" "0,1"
|
|
bitfld.long 0x4 21. "COMP3_OCREF_CLR_TIM1,desc COMP3_OCREF_CLR_TIM1" "0,1"
|
|
bitfld.long 0x4 20. "COMP2_OCREF_CLR_TIM3,desc COMP2_OCREF_CLR_TIM3" "0,1"
|
|
bitfld.long 0x4 19. "COMP2_OCREF_CLR_TIM2,desc COMP2_OCREF_CLR_TIM2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "COMP2_OCREF_CLR_TIM1,desc COMP2_OCREF_CLR_TIM1" "0,1"
|
|
bitfld.long 0x4 17. "COMP1_OCREF_CLR_TIM3,desc COMP1_OCREF_CLR_TIM3" "0,1"
|
|
bitfld.long 0x4 16. "COMP1_OCREF_CLR_TIM2,desc COMP1_OCREF_CLR_TIM2" "0,1"
|
|
bitfld.long 0x4 15. "COMP1_OCREF_CLR_TIM1,desc COMP1_OCREF_CLR_TIM1" "0,1"
|
|
bitfld.long 0x4 14. "COMP3_BRK_TIM17,desc COMP3_BRK_TIM17" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "COMP2_BRK_TIM17,desc COMP2_BRK_TIM17" "0,1"
|
|
bitfld.long 0x4 12. "COMP1_BRK_TIM17,desc COMP1_BRK_TIM17" "0,1"
|
|
bitfld.long 0x4 11. "COMP3_BRK_TIM16,desc COMP3_BRK_TIM16" "0,1"
|
|
bitfld.long 0x4 10. "COMP2_BRK_TIM16,desc COMP2_BRK_TIM16" "0,1"
|
|
bitfld.long 0x4 9. "COMP1_BRK_TIM16,desc COMP1_BRK_TIM16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "COMP3_BRK_TIM15,desc COMP3_BRK_TIM15" "0,1"
|
|
bitfld.long 0x4 7. "COMP2_BRK_TIM15,desc COMP2_BRK_TIM15" "0,1"
|
|
bitfld.long 0x4 6. "COMP1_BRK_TIM15,desc COMP1_BRK_TIM15" "0,1"
|
|
bitfld.long 0x4 5. "COMP3_BRK_TIM1,desc COMP3_BRK_TIM1" "0,1"
|
|
bitfld.long 0x4 4. "COMP2_BRK_TIM1,desc COMP2_BRK_TIM1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "COMP1_BRK_TIM1,desc COMP1_BRK_TIM1" "0,1"
|
|
bitfld.long 0x4 2. "PVD_LOCK,desc PVD_LOCK" "0,1"
|
|
bitfld.long 0x4 0. "LOCKUP_LOCK,desc LOCKUP_LOCK" "0,1"
|
|
line.long 0x8 "CFGR3,desc CFGR3"
|
|
hexmask.long.byte 0x8 24.--29. 1. "DMA4_MAP,desc DMA4_MAP"
|
|
hexmask.long.byte 0x8 16.--21. 1. "DMA3_MAP,desc DMA3_MAP"
|
|
hexmask.long.byte 0x8 8.--13. 1. "DMA2_MAP,desc DMA2_MAP"
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMA1_MAP,desc DMA1_MAP"
|
|
line.long 0xC "CFGR4,desc CFGR4"
|
|
hexmask.long.byte 0xC 16.--21. 1. "DMA7_MAP,desc DMA7_MAP"
|
|
hexmask.long.byte 0xC 8.--13. 1. "DMA6_MAP,desc DMA6_MAP"
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMA5_MAP,desc DMA5_MAP"
|
|
line.long 0x10 "PAENS,desc PAENS"
|
|
hexmask.long.word 0x10 0.--15. 1. "PA_ENS,desc PA_ENS"
|
|
line.long 0x14 "PBENS,desc PBENS"
|
|
hexmask.long.word 0x14 0.--15. 1. "PB_ENS,desc PB_ENS"
|
|
line.long 0x18 "PCENS,desc PCENS"
|
|
hexmask.long.word 0x18 0.--15. 1. "PC_ENS,desc PC_ENS"
|
|
line.long 0x1C "PFENS,desc PFENS"
|
|
hexmask.long.word 0x1C 0.--15. 1. "PF_ENS,desc PF_ENS"
|
|
tree.end
|
|
tree "TIM (Timer)"
|
|
base ad:0x0
|
|
tree "TIM1 (Advanced-Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 14. "OIS4,desc OIS4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,desc OIS3N" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,desc OIS3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,desc OIS2N" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,desc OIS2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,desc OIS1N" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,desc OIS1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,desc CCUS" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,desc CCPC" "0,1"
|
|
line.long 0x8 "SMCR,desc SMCR"
|
|
bitfld.long 0x8 15. "ETP,desc ETP" "0,1"
|
|
bitfld.long 0x8 14. "ECE,desc ECE" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,desc ETPS" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,desc ETF"
|
|
bitfld.long 0x8 7. "MSM,desc MSM" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,desc TS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,desc OCCS" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,desc SMS" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,desc DIER"
|
|
bitfld.long 0xC 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0xC 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0xC 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0xC 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x10 "SR,desc SR"
|
|
bitfld.long 0x10 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x10 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x10 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x10 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x10 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x10 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_OUTPUT,desc CCMR2:OUTPUT"
|
|
bitfld.long 0x4 15. "OC4CE,desc OC4CE" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,desc OC4M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,desc OC4PE" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,desc OC4FE" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,desc OC3CE" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,desc OC3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,desc OC3PE" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,desc OC3FE" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
group.long 0x1C++0x33
|
|
line.long 0x0 "CCMR2_INPUT,desc CCMR2:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,desc IC4F"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,desc IC4PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,desc IC3F"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,desc IC3PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
line.long 0x4 "CCER,desc CCER"
|
|
bitfld.long 0x4 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x8 "CNT,desc CNT"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0xC "PSC,desc PSC"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0x10 "ARR,desc ARR"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,desc ARR"
|
|
line.long 0x14 "RCR,desc RCR"
|
|
hexmask.long.byte 0x14 0.--7. 1. "REP,desc REP"
|
|
line.long 0x18 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,desc CCR1"
|
|
line.long 0x1C "CCR2,desc CCR2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,desc CCR2"
|
|
line.long 0x20 "CCR3,desc CCR3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,desc CCR3"
|
|
line.long 0x24 "CCR4,desc CCR4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,desc CCR4"
|
|
line.long 0x28 "BDTR,desc BDTR"
|
|
bitfld.long 0x28 15. "MOE,desc MOE" "0,1"
|
|
bitfld.long 0x28 14. "AOE,desc AOE" "0,1"
|
|
bitfld.long 0x28 13. "BKP,desc BKP" "0,1"
|
|
bitfld.long 0x28 12. "BKE,desc BKE" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,desc OSSR" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,desc OSSI" "0,1"
|
|
bitfld.long 0x28 8.--9. "LOCK,desc LOCK" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,desc DTG"
|
|
line.long 0x2C "DCR,desc DCR"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,desc DBL"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,desc DBA"
|
|
line.long 0x30 "DMAR,desc DMAR"
|
|
hexmask.long.word 0x30 0.--15. 1. "DMAB,desc DMAB"
|
|
tree.end
|
|
tree "TIM2 (32-bit General Purpose Timer)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
line.long 0x8 "SMCR,desc SMCR"
|
|
bitfld.long 0x8 15. "ETP,desc ETP" "0,1"
|
|
bitfld.long 0x8 14. "ECE,desc ECE" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,desc ETPS" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,desc ETF"
|
|
bitfld.long 0x8 7. "MSM,desc MSM" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,desc TS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SMS,desc SMS" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,desc DIER"
|
|
bitfld.long 0xC 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0xC 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0xC 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0xC 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x10 "SR,desc SR"
|
|
bitfld.long 0x10 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x10 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x10 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x10 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x10 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x10 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_OUTPUT,desc CCMR2:OUTPUT"
|
|
bitfld.long 0x4 15. "OC4CE,desc OC4CE" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,desc OC4M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,desc OC4PE" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,desc OC4FE" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,desc OC3CE" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,desc OC3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,desc OC3PE" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,desc OC3FE" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_INPUT,desc CCMR2:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,desc IC4F"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,desc IC4PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,desc IC3F"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,desc IC3PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
line.long 0x4 "CCER,desc CCER"
|
|
bitfld.long 0x4 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x8 "CNT,desc CNT"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0xC "PSC,desc PSC"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0x10 "ARR,desc ARR"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,desc ARR"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,desc CCR1"
|
|
line.long 0x4 "CCR2,desc CCR2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2,desc CCR2"
|
|
line.long 0x8 "CCR3,desc CCR3"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3,desc CCR3"
|
|
line.long 0xC "CCR4,desc CCR4"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4,desc CCR4"
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "DCR,desc DCR"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,desc DBL"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,desc DBA"
|
|
line.long 0x4 "DMAR,desc DMAR"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,desc DMAB"
|
|
tree.end
|
|
tree "TIM3 (16-bit General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
line.long 0x8 "SMCR,desc SMCR"
|
|
bitfld.long 0x8 15. "ETP,desc ETP" "0,1"
|
|
bitfld.long 0x8 14. "ECE,desc ECE" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,desc ETPS" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,desc ETF"
|
|
bitfld.long 0x8 7. "MSM,desc MSM" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,desc TS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SMS,desc SMS" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,desc DIER"
|
|
bitfld.long 0xC 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0xC 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0xC 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0xC 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x10 "SR,desc SR"
|
|
bitfld.long 0x10 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x10 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x10 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x10 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x10 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x10 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_OUTPUT,desc CCMR2:OUTPUT"
|
|
bitfld.long 0x4 15. "OC4CE,desc OC4CE" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,desc OC4M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,desc OC4PE" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,desc OC4FE" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,desc OC3CE" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,desc OC3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,desc OC3PE" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,desc OC3FE" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_INPUT,desc CCMR2:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,desc IC4F"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,desc IC4PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,desc CC4S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,desc IC3F"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,desc IC3PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,desc CC3S" "0,1,2,3"
|
|
line.long 0x4 "CCER,desc CCER"
|
|
bitfld.long 0x4 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x8 "CNT,desc CNT"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0xC "PSC,desc PSC"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0x10 "ARR,desc ARR"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,desc ARR"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,desc CCR1"
|
|
line.long 0x4 "CCR2,desc CCR2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2,desc CCR2"
|
|
line.long 0x8 "CCR3,desc CCR3"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3,desc CCR3"
|
|
line.long 0xC "CCR4,desc CCR4"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4,desc CCR4"
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "DCR,desc DCR"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,desc DBL"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,desc DBA"
|
|
line.long 0x4 "DMAR,desc DMAR"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,desc DMAB"
|
|
tree.end
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,desc DIER"
|
|
bitfld.long 0x0 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0x0 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0x0 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0x0 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0x0 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0x0 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0x0 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0x0 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0x0 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0x0 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x4 "SR,desc SR"
|
|
bitfld.long 0x4 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x4 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x4 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x4 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x4 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x4 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x4 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x4 9. "CC1OF,desc CC1OF" "0,1"
|
|
bitfld.long 0x4 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x4 6. "TIF,desc TIF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x4 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x4 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x4 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x4 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,desc CNT"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0x4 "PSC,desc PSC"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0x8 "ARR,desc ARR"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,desc ARR"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,desc DIER"
|
|
bitfld.long 0x0 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0x0 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0x0 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0x0 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0x0 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0x0 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0x0 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0x0 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0x0 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0x0 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x4 "SR,desc SR"
|
|
bitfld.long 0x4 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x4 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x4 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x4 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x4 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x4 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x4 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x4 9. "CC1OF,desc CC1OF" "0,1"
|
|
bitfld.long 0x4 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x4 6. "TIF,desc TIF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x4 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x4 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x4 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x4 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,desc CNT"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0x4 "PSC,desc PSC"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0x8 "ARR,desc ARR"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,desc ARR"
|
|
tree.end
|
|
tree "TIM14 (16-bit General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,desc DIER"
|
|
bitfld.long 0x0 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0x0 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0x0 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0x0 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0x0 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0x0 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0x0 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0x0 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0x0 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,desc CC1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x4 "SR,desc SR"
|
|
bitfld.long 0x4 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x4 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x4 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x4 9. "CC1OF,desc CC1OF" "0,1"
|
|
bitfld.long 0x4 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x4 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x4 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x4 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x4 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,desc CCER"
|
|
bitfld.long 0x0 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x0 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x0 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x0 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x0 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x4 "CNT,desc CNT"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0x8 "PSC,desc PSC"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0xC "ARR,desc ARR"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,desc ARR"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,desc CCR1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "OR,desc OR"
|
|
bitfld.long 0x0 0.--1. "TI1_RMP,desc TI1_RMP" "0,1,2,3"
|
|
tree.end
|
|
tree "TIM15 (16-bit General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
line.long 0x8 "SMCR,desc SMCR"
|
|
bitfld.long 0x8 15. "ETP,desc ETP" "0,1"
|
|
bitfld.long 0x8 14. "ECE,desc ECE" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,desc ETPS" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,desc ETF"
|
|
bitfld.long 0x8 7. "MSM,desc MSM" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,desc TS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SMS,desc SMS" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,desc DIER"
|
|
bitfld.long 0xC 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0xC 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0xC 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0xC 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x10 "SR,desc SR"
|
|
bitfld.long 0x10 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x10 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x10 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x10 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x10 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x10 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x10 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x10 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,desc CCER"
|
|
bitfld.long 0x0 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x0 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x0 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x0 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x0 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x4 "CNT,desc CNT"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0x8 "PSC,desc PSC"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0xC "ARR,desc ARR"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,desc ARR"
|
|
line.long 0x10 "RCR,desc RCR"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,desc REP"
|
|
line.long 0x14 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,desc CCR1"
|
|
line.long 0x18 "CCR2,desc CCR2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,desc CCR2"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,desc BDTR"
|
|
bitfld.long 0x0 15. "MOE,desc MOE" "0,1"
|
|
bitfld.long 0x0 14. "AOE,desc AOE" "0,1"
|
|
bitfld.long 0x0 13. "BKP,desc BKP" "0,1"
|
|
bitfld.long 0x0 12. "BKE,desc BKE" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,desc OSSR" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,desc OSSI" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,desc LOCK" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,desc DTG"
|
|
line.long 0x4 "DCR,desc DCR"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,desc DBL"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,desc DBA"
|
|
line.long 0x8 "DMAR,desc DMAR"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,desc DMAB"
|
|
tree.end
|
|
tree "TIM16 (16-bit General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,desc DIER"
|
|
bitfld.long 0x0 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0x0 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0x0 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0x0 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0x0 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0x0 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0x0 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0x0 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0x0 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0x0 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x4 "SR,desc SR"
|
|
bitfld.long 0x4 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x4 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x4 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x4 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x4 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x4 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x4 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x4 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x4 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x4 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x4 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x4 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x4 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,desc CCER"
|
|
bitfld.long 0x0 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x0 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x0 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x0 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x0 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x4 "CNT,desc CNT"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0x8 "PSC,desc PSC"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0xC "ARR,desc ARR"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,desc ARR"
|
|
line.long 0x10 "RCR,desc RCR"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,desc REP"
|
|
line.long 0x14 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,desc CCR1"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,desc BDTR"
|
|
bitfld.long 0x0 15. "MOE,desc MOE" "0,1"
|
|
bitfld.long 0x0 14. "AOE,desc AOE" "0,1"
|
|
bitfld.long 0x0 13. "BKP,desc BKP" "0,1"
|
|
bitfld.long 0x0 12. "BKE,desc BKE" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,desc OSSR" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,desc OSSI" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,desc LOCK" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,desc DTG"
|
|
line.long 0x4 "DCR,desc DCR"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,desc DBL"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,desc DBA"
|
|
line.long 0x8 "DMAR,desc DMAR"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,desc DMAB"
|
|
tree.end
|
|
tree "TIM17 (16-bit General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,desc CR1"
|
|
bitfld.long 0x0 8.--9. "CKD,desc CKD" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,desc ARPE" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,desc CMS" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,desc DIR" "0,1"
|
|
bitfld.long 0x0 3. "OPM,desc OPM" "0,1"
|
|
bitfld.long 0x0 2. "URS,desc URS" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,desc UDIS" "0,1"
|
|
bitfld.long 0x0 0. "CEN,desc CEN" "0,1"
|
|
line.long 0x4 "CR2,desc CR2"
|
|
bitfld.long 0x4 7. "TI1S,desc TI1S" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,desc MMS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,desc CCDS" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,desc DIER"
|
|
bitfld.long 0x0 14. "TDE,desc TDE" "0,1"
|
|
bitfld.long 0x0 12. "CC4DE,desc CC4DE" "0,1"
|
|
bitfld.long 0x0 11. "CC3DE,desc CC3DE" "0,1"
|
|
bitfld.long 0x0 10. "CC2DE,desc CC2DE" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,desc CC1DE" "0,1"
|
|
bitfld.long 0x0 8. "UDE,desc UDE" "0,1"
|
|
bitfld.long 0x0 6. "TIE,desc TIE" "0,1"
|
|
bitfld.long 0x0 4. "CC4IE,desc CC4IE" "0,1"
|
|
bitfld.long 0x0 3. "CC3IE,desc CC3IE" "0,1"
|
|
bitfld.long 0x0 2. "CC2IE,desc CC2IE" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,desc CC1IE" "0,1"
|
|
bitfld.long 0x0 0. "UIE,desc UIE" "0,1"
|
|
line.long 0x4 "SR,desc SR"
|
|
bitfld.long 0x4 23. "IC4IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 22. "IC3IF,desc IC3IF" "0,1"
|
|
bitfld.long 0x4 21. "IC2IF,desc IC2IF" "0,1"
|
|
bitfld.long 0x4 20. "IC1IF,desc IC1IF" "0,1"
|
|
bitfld.long 0x4 19. "IC4IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 18. "IC3IR,desc IC3IR" "0,1"
|
|
bitfld.long 0x4 17. "IC2IR,desc IC2IR" "0,1"
|
|
bitfld.long 0x4 16. "IC1IR,desc IC1IR" "0,1"
|
|
bitfld.long 0x4 12. "CC4OF,desc CC4OF" "0,1"
|
|
bitfld.long 0x4 11. "CC3OF,desc CC3OF" "0,1"
|
|
bitfld.long 0x4 10. "CC2OF,desc CC2OF" "0,1"
|
|
bitfld.long 0x4 9. "CC1OF,desc CC1OF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BIF,desc BIF" "0,1"
|
|
bitfld.long 0x4 6. "TIF,desc TIF" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,desc COMIF" "0,1"
|
|
bitfld.long 0x4 4. "CC4IF,desc CC4IF" "0,1"
|
|
bitfld.long 0x4 3. "CC3IF,desc CC3IF" "0,1"
|
|
bitfld.long 0x4 2. "CC2IF,desc CC2IF" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,desc CC1IF" "0,1"
|
|
bitfld.long 0x4 0. "UIF,desc UIF" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,desc EGR"
|
|
bitfld.long 0x0 6. "TG,desc TG" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,desc CC4G" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,desc CC3G" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,desc CC2G" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 Generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,desc UG" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_OUTPUT,desc CCMR1:OUTPUT"
|
|
bitfld.long 0x0 15. "OC2CE,desc OC2CE" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,desc OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,desc OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,desc OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,desc OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,desc OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,desc OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,desc OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_INPUT,desc CCMR1:INPUT"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,desc IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,desc IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,desc CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,desc IC1F"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,desc IC1PSC" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,desc CC1S" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,desc CCER"
|
|
bitfld.long 0x0 13. "CC4P,desc CC4P" "0,1"
|
|
bitfld.long 0x0 12. "CC4E,desc CC4E" "0,1"
|
|
bitfld.long 0x0 9. "CC3P,desc CC3P" "0,1"
|
|
bitfld.long 0x0 8. "CC3E,desc CC3E" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,desc CC2P" "0,1"
|
|
bitfld.long 0x0 4. "CC2E,desc CC2E" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,desc CC1P" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,desc CC1E" "0,1"
|
|
line.long 0x4 "CNT,desc CNT"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,desc CNT"
|
|
line.long 0x8 "PSC,desc PSC"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,desc PSC"
|
|
line.long 0xC "ARR,desc ARR"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,desc ARR"
|
|
line.long 0x10 "RCR,desc RCR"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,desc REP"
|
|
line.long 0x14 "CCR1,desc CCR1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,desc CCR1"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,desc BDTR"
|
|
bitfld.long 0x0 15. "MOE,desc MOE" "0,1"
|
|
bitfld.long 0x0 14. "AOE,desc AOE" "0,1"
|
|
bitfld.long 0x0 13. "BKP,desc BKP" "0,1"
|
|
bitfld.long 0x0 12. "BKE,desc BKE" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,desc OSSR" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,desc OSSI" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,desc LOCK" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,desc DTG"
|
|
line.long 0x4 "DCR,desc DCR"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,desc DBL"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,desc DBA"
|
|
line.long 0x8 "DMAR,desc DMAR"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,desc DMAB"
|
|
tree.end
|
|
tree.end
|
|
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "SR,desc SR"
|
|
bitfld.long 0x0 12. "ABRRQ,desc ABRRQ" "0,1"
|
|
rbitfld.long 0x0 11. "ABRE,desc ABRE" "0,1"
|
|
rbitfld.long 0x0 10. "ABRF,desc ABRF" "0,1"
|
|
bitfld.long 0x0 9. "CTS,desc CTS" "0,1"
|
|
bitfld.long 0x0 8. "LBD,desc LBD" "0,1"
|
|
rbitfld.long 0x0 7. "TXE,desc TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,desc TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,desc RXNE" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "IDLE,desc IDLE" "0,1"
|
|
rbitfld.long 0x0 3. "ORE,desc ORE" "0,1"
|
|
rbitfld.long 0x0 2. "NE,desc NE" "0,1"
|
|
rbitfld.long 0x0 1. "FE,desc FE" "0,1"
|
|
rbitfld.long 0x0 0. "PE,desc PE" "0,1"
|
|
line.long 0x4 "DR,desc DR"
|
|
hexmask.long.word 0x4 0.--8. 1. "DR,desc DR"
|
|
line.long 0x8 "BRR,desc BRR"
|
|
hexmask.long.word 0x8 4.--15. 1. "DIV_MANTISSA,desc DIV_Mantissa"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DIV_FRACTION,desc DIV_Fraction"
|
|
line.long 0xC "CR1,desc CR1"
|
|
bitfld.long 0xC 13. "UE,desc UE" "0,1"
|
|
bitfld.long 0xC 12. "M,desc M" "0,1"
|
|
bitfld.long 0xC 11. "WAKE,desc WAKE" "0,1"
|
|
bitfld.long 0xC 10. "PCE,desc PCE" "0,1"
|
|
bitfld.long 0xC 9. "PS,desc PS" "0,1"
|
|
bitfld.long 0xC 8. "PEIE,desc PEIE" "0,1"
|
|
bitfld.long 0xC 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0xC 6. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0xC 4. "IDLEIE,desc IDLEIE" "0,1"
|
|
bitfld.long 0xC 3. "TE,desc TE" "0,1"
|
|
bitfld.long 0xC 2. "RE,desc RE" "0,1"
|
|
bitfld.long 0xC 1. "RWU,desc RWU" "0,1"
|
|
bitfld.long 0xC 0. "SBK,desc SBK" "0,1"
|
|
line.long 0x10 "CR2,desc CR2"
|
|
bitfld.long 0x10 14. "LINEN,desc LINEN" "0,1"
|
|
bitfld.long 0x10 12.--13. "STOP,desc STOP" "0,1,2,3"
|
|
bitfld.long 0x10 11. "CLKEN,desc CLKEN" "0,1"
|
|
bitfld.long 0x10 10. "CPOL,desc CPOL" "0,1"
|
|
bitfld.long 0x10 9. "CPHA,desc CPHA" "0,1"
|
|
bitfld.long 0x10 8. "LBCL,desc LBCL" "0,1"
|
|
bitfld.long 0x10 6. "LBDIE,desc LBDIE" "0,1"
|
|
bitfld.long 0x10 5. "LBDL,desc LBDL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "ADD,desc ADD"
|
|
line.long 0x14 "CR3,desc CR3"
|
|
bitfld.long 0x14 13.--14. "ABRMODE,desc ABRMODE" "0,1,2,3"
|
|
bitfld.long 0x14 12. "ABREN,desc ABREN" "0,1"
|
|
bitfld.long 0x14 11. "OVER8,desc OVER8" "0,1"
|
|
bitfld.long 0x14 10. "CTSIE,desc CTSIE" "0,1"
|
|
bitfld.long 0x14 9. "CTSE,desc CTSE" "0,1"
|
|
bitfld.long 0x14 8. "RTSE,desc RTSE" "0,1"
|
|
bitfld.long 0x14 7. "DMAT,desc DMAT" "0,1"
|
|
bitfld.long 0x14 6. "DMAR,desc DMAR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "SCEN,desc SCEN" "0,1"
|
|
bitfld.long 0x14 4. "NACK,desc NACK" "0,1"
|
|
bitfld.long 0x14 3. "HDSEL,desc HDSEL" "0,1"
|
|
bitfld.long 0x14 2. "IRLP,desc IRLP" "0,1"
|
|
bitfld.long 0x14 1. "IREN,desc IREN" "0,1"
|
|
bitfld.long 0x14 0. "EIE,desc EIE" "0,1"
|
|
line.long 0x18 "GTPR,desc GTPR"
|
|
hexmask.long.byte 0x18 8.--15. 1. "GT,desc GT"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PSC,desc PSC"
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "SR,desc SR"
|
|
bitfld.long 0x0 12. "ABRRQ,desc ABRRQ" "0,1"
|
|
rbitfld.long 0x0 11. "ABRE,desc ABRE" "0,1"
|
|
rbitfld.long 0x0 10. "ABRF,desc ABRF" "0,1"
|
|
bitfld.long 0x0 9. "CTS,desc CTS" "0,1"
|
|
bitfld.long 0x0 8. "LBD,desc LBD" "0,1"
|
|
rbitfld.long 0x0 7. "TXE,desc TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,desc TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,desc RXNE" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "IDLE,desc IDLE" "0,1"
|
|
rbitfld.long 0x0 3. "ORE,desc ORE" "0,1"
|
|
rbitfld.long 0x0 2. "NE,desc NE" "0,1"
|
|
rbitfld.long 0x0 1. "FE,desc FE" "0,1"
|
|
rbitfld.long 0x0 0. "PE,desc PE" "0,1"
|
|
line.long 0x4 "DR,desc DR"
|
|
hexmask.long.word 0x4 0.--8. 1. "DR,desc DR"
|
|
line.long 0x8 "BRR,desc BRR"
|
|
hexmask.long.word 0x8 4.--15. 1. "DIV_MANTISSA,desc DIV_Mantissa"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DIV_FRACTION,desc DIV_Fraction"
|
|
line.long 0xC "CR1,desc CR1"
|
|
bitfld.long 0xC 13. "UE,desc UE" "0,1"
|
|
bitfld.long 0xC 12. "M,desc M" "0,1"
|
|
bitfld.long 0xC 11. "WAKE,desc WAKE" "0,1"
|
|
bitfld.long 0xC 10. "PCE,desc PCE" "0,1"
|
|
bitfld.long 0xC 9. "PS,desc PS" "0,1"
|
|
bitfld.long 0xC 8. "PEIE,desc PEIE" "0,1"
|
|
bitfld.long 0xC 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0xC 6. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0xC 4. "IDLEIE,desc IDLEIE" "0,1"
|
|
bitfld.long 0xC 3. "TE,desc TE" "0,1"
|
|
bitfld.long 0xC 2. "RE,desc RE" "0,1"
|
|
bitfld.long 0xC 1. "RWU,desc RWU" "0,1"
|
|
bitfld.long 0xC 0. "SBK,desc SBK" "0,1"
|
|
line.long 0x10 "CR2,desc CR2"
|
|
bitfld.long 0x10 14. "LINEN,desc LINEN" "0,1"
|
|
bitfld.long 0x10 12.--13. "STOP,desc STOP" "0,1,2,3"
|
|
bitfld.long 0x10 11. "CLKEN,desc CLKEN" "0,1"
|
|
bitfld.long 0x10 10. "CPOL,desc CPOL" "0,1"
|
|
bitfld.long 0x10 9. "CPHA,desc CPHA" "0,1"
|
|
bitfld.long 0x10 8. "LBCL,desc LBCL" "0,1"
|
|
bitfld.long 0x10 6. "LBDIE,desc LBDIE" "0,1"
|
|
bitfld.long 0x10 5. "LBDL,desc LBDL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "ADD,desc ADD"
|
|
line.long 0x14 "CR3,desc CR3"
|
|
bitfld.long 0x14 13.--14. "ABRMODE,desc ABRMODE" "0,1,2,3"
|
|
bitfld.long 0x14 12. "ABREN,desc ABREN" "0,1"
|
|
bitfld.long 0x14 11. "OVER8,desc OVER8" "0,1"
|
|
bitfld.long 0x14 10. "CTSIE,desc CTSIE" "0,1"
|
|
bitfld.long 0x14 9. "CTSE,desc CTSE" "0,1"
|
|
bitfld.long 0x14 8. "RTSE,desc RTSE" "0,1"
|
|
bitfld.long 0x14 7. "DMAT,desc DMAT" "0,1"
|
|
bitfld.long 0x14 6. "DMAR,desc DMAR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "SCEN,desc SCEN" "0,1"
|
|
bitfld.long 0x14 4. "NACK,desc NACK" "0,1"
|
|
bitfld.long 0x14 3. "HDSEL,desc HDSEL" "0,1"
|
|
bitfld.long 0x14 2. "IRLP,desc IRLP" "0,1"
|
|
bitfld.long 0x14 1. "IREN,desc IREN" "0,1"
|
|
bitfld.long 0x14 0. "EIE,desc EIE" "0,1"
|
|
line.long 0x18 "GTPR,desc GTPR"
|
|
hexmask.long.byte 0x18 8.--15. 1. "GT,desc GT"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PSC,desc PSC"
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "SR,desc SR"
|
|
bitfld.long 0x0 12. "ABRRQ,desc ABRRQ" "0,1"
|
|
rbitfld.long 0x0 11. "ABRE,desc ABRE" "0,1"
|
|
rbitfld.long 0x0 10. "ABRF,desc ABRF" "0,1"
|
|
bitfld.long 0x0 9. "CTS,desc CTS" "0,1"
|
|
bitfld.long 0x0 8. "LBD,desc LBD" "0,1"
|
|
rbitfld.long 0x0 7. "TXE,desc TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,desc TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,desc RXNE" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "IDLE,desc IDLE" "0,1"
|
|
rbitfld.long 0x0 3. "ORE,desc ORE" "0,1"
|
|
rbitfld.long 0x0 2. "NE,desc NE" "0,1"
|
|
rbitfld.long 0x0 1. "FE,desc FE" "0,1"
|
|
rbitfld.long 0x0 0. "PE,desc PE" "0,1"
|
|
line.long 0x4 "DR,desc DR"
|
|
hexmask.long.word 0x4 0.--8. 1. "DR,desc DR"
|
|
line.long 0x8 "BRR,desc BRR"
|
|
hexmask.long.word 0x8 4.--15. 1. "DIV_MANTISSA,desc DIV_Mantissa"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DIV_FRACTION,desc DIV_Fraction"
|
|
line.long 0xC "CR1,desc CR1"
|
|
bitfld.long 0xC 13. "UE,desc UE" "0,1"
|
|
bitfld.long 0xC 12. "M,desc M" "0,1"
|
|
bitfld.long 0xC 11. "WAKE,desc WAKE" "0,1"
|
|
bitfld.long 0xC 10. "PCE,desc PCE" "0,1"
|
|
bitfld.long 0xC 9. "PS,desc PS" "0,1"
|
|
bitfld.long 0xC 8. "PEIE,desc PEIE" "0,1"
|
|
bitfld.long 0xC 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0xC 6. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0xC 4. "IDLEIE,desc IDLEIE" "0,1"
|
|
bitfld.long 0xC 3. "TE,desc TE" "0,1"
|
|
bitfld.long 0xC 2. "RE,desc RE" "0,1"
|
|
bitfld.long 0xC 1. "RWU,desc RWU" "0,1"
|
|
bitfld.long 0xC 0. "SBK,desc SBK" "0,1"
|
|
line.long 0x10 "CR2,desc CR2"
|
|
bitfld.long 0x10 14. "LINEN,desc LINEN" "0,1"
|
|
bitfld.long 0x10 12.--13. "STOP,desc STOP" "0,1,2,3"
|
|
bitfld.long 0x10 11. "CLKEN,desc CLKEN" "0,1"
|
|
bitfld.long 0x10 10. "CPOL,desc CPOL" "0,1"
|
|
bitfld.long 0x10 9. "CPHA,desc CPHA" "0,1"
|
|
bitfld.long 0x10 8. "LBCL,desc LBCL" "0,1"
|
|
bitfld.long 0x10 6. "LBDIE,desc LBDIE" "0,1"
|
|
bitfld.long 0x10 5. "LBDL,desc LBDL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "ADD,desc ADD"
|
|
line.long 0x14 "CR3,desc CR3"
|
|
bitfld.long 0x14 13.--14. "ABRMODE,desc ABRMODE" "0,1,2,3"
|
|
bitfld.long 0x14 12. "ABREN,desc ABREN" "0,1"
|
|
bitfld.long 0x14 11. "OVER8,desc OVER8" "0,1"
|
|
bitfld.long 0x14 10. "CTSIE,desc CTSIE" "0,1"
|
|
bitfld.long 0x14 9. "CTSE,desc CTSE" "0,1"
|
|
bitfld.long 0x14 8. "RTSE,desc RTSE" "0,1"
|
|
bitfld.long 0x14 7. "DMAT,desc DMAT" "0,1"
|
|
bitfld.long 0x14 6. "DMAR,desc DMAR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "SCEN,desc SCEN" "0,1"
|
|
bitfld.long 0x14 4. "NACK,desc NACK" "0,1"
|
|
bitfld.long 0x14 3. "HDSEL,desc HDSEL" "0,1"
|
|
bitfld.long 0x14 2. "IRLP,desc IRLP" "0,1"
|
|
bitfld.long 0x14 1. "IREN,desc IREN" "0,1"
|
|
bitfld.long 0x14 0. "EIE,desc EIE" "0,1"
|
|
line.long 0x18 "GTPR,desc GTPR"
|
|
hexmask.long.byte 0x18 8.--15. 1. "GT,desc GT"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PSC,desc PSC"
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "SR,desc SR"
|
|
bitfld.long 0x0 12. "ABRRQ,desc ABRRQ" "0,1"
|
|
rbitfld.long 0x0 11. "ABRE,desc ABRE" "0,1"
|
|
rbitfld.long 0x0 10. "ABRF,desc ABRF" "0,1"
|
|
bitfld.long 0x0 9. "CTS,desc CTS" "0,1"
|
|
bitfld.long 0x0 8. "LBD,desc LBD" "0,1"
|
|
rbitfld.long 0x0 7. "TXE,desc TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,desc TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,desc RXNE" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "IDLE,desc IDLE" "0,1"
|
|
rbitfld.long 0x0 3. "ORE,desc ORE" "0,1"
|
|
rbitfld.long 0x0 2. "NE,desc NE" "0,1"
|
|
rbitfld.long 0x0 1. "FE,desc FE" "0,1"
|
|
rbitfld.long 0x0 0. "PE,desc PE" "0,1"
|
|
line.long 0x4 "DR,desc DR"
|
|
hexmask.long.word 0x4 0.--8. 1. "DR,desc DR"
|
|
line.long 0x8 "BRR,desc BRR"
|
|
hexmask.long.word 0x8 4.--15. 1. "DIV_MANTISSA,desc DIV_Mantissa"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DIV_FRACTION,desc DIV_Fraction"
|
|
line.long 0xC "CR1,desc CR1"
|
|
bitfld.long 0xC 13. "UE,desc UE" "0,1"
|
|
bitfld.long 0xC 12. "M,desc M" "0,1"
|
|
bitfld.long 0xC 11. "WAKE,desc WAKE" "0,1"
|
|
bitfld.long 0xC 10. "PCE,desc PCE" "0,1"
|
|
bitfld.long 0xC 9. "PS,desc PS" "0,1"
|
|
bitfld.long 0xC 8. "PEIE,desc PEIE" "0,1"
|
|
bitfld.long 0xC 7. "TXEIE,desc TXEIE" "0,1"
|
|
bitfld.long 0xC 6. "TCIE,desc TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXNEIE,desc RXNEIE" "0,1"
|
|
bitfld.long 0xC 4. "IDLEIE,desc IDLEIE" "0,1"
|
|
bitfld.long 0xC 3. "TE,desc TE" "0,1"
|
|
bitfld.long 0xC 2. "RE,desc RE" "0,1"
|
|
bitfld.long 0xC 1. "RWU,desc RWU" "0,1"
|
|
bitfld.long 0xC 0. "SBK,desc SBK" "0,1"
|
|
line.long 0x10 "CR2,desc CR2"
|
|
bitfld.long 0x10 14. "LINEN,desc LINEN" "0,1"
|
|
bitfld.long 0x10 12.--13. "STOP,desc STOP" "0,1,2,3"
|
|
bitfld.long 0x10 11. "CLKEN,desc CLKEN" "0,1"
|
|
bitfld.long 0x10 10. "CPOL,desc CPOL" "0,1"
|
|
bitfld.long 0x10 9. "CPHA,desc CPHA" "0,1"
|
|
bitfld.long 0x10 8. "LBCL,desc LBCL" "0,1"
|
|
bitfld.long 0x10 6. "LBDIE,desc LBDIE" "0,1"
|
|
bitfld.long 0x10 5. "LBDL,desc LBDL" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "ADD,desc ADD"
|
|
line.long 0x14 "CR3,desc CR3"
|
|
bitfld.long 0x14 13.--14. "ABRMODE,desc ABRMODE" "0,1,2,3"
|
|
bitfld.long 0x14 12. "ABREN,desc ABREN" "0,1"
|
|
bitfld.long 0x14 11. "OVER8,desc OVER8" "0,1"
|
|
bitfld.long 0x14 10. "CTSIE,desc CTSIE" "0,1"
|
|
bitfld.long 0x14 9. "CTSE,desc CTSE" "0,1"
|
|
bitfld.long 0x14 8. "RTSE,desc RTSE" "0,1"
|
|
bitfld.long 0x14 7. "DMAT,desc DMAT" "0,1"
|
|
bitfld.long 0x14 6. "DMAR,desc DMAR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "SCEN,desc SCEN" "0,1"
|
|
bitfld.long 0x14 4. "NACK,desc NACK" "0,1"
|
|
bitfld.long 0x14 3. "HDSEL,desc HDSEL" "0,1"
|
|
bitfld.long 0x14 2. "IRLP,desc IRLP" "0,1"
|
|
bitfld.long 0x14 1. "IREN,desc IREN" "0,1"
|
|
bitfld.long 0x14 0. "EIE,desc EIE" "0,1"
|
|
line.long 0x18 "GTPR,desc GTPR"
|
|
hexmask.long.byte 0x18 8.--15. 1. "GT,desc GT"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PSC,desc PSC"
|
|
tree.end
|
|
tree.end
|
|
tree "USB (USB Full Speed Device Interface)"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,CR"
|
|
bitfld.long 0x0 15. "ISO_Update,ISO_Update" "0,1"
|
|
bitfld.long 0x0 11. "Reset,Reset" "0,1"
|
|
bitfld.long 0x0 10. "Resume,Resume" "0,1"
|
|
bitfld.long 0x0 9. "Suspend_Mode,Suspend_Mode" "0,1"
|
|
bitfld.long 0x0 8. "Enable_Suspend,Enable_Suspend" "0,1"
|
|
bitfld.long 0x0 7. "UPDATE,UPDATE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "ADD,ADD"
|
|
line.long 0x4 "INTR,INTR"
|
|
bitfld.long 0x4 21. "EP5IN,EP5IN" "0,1"
|
|
bitfld.long 0x4 20. "EP4IN,EP4IN" "0,1"
|
|
bitfld.long 0x4 19. "EP3IN,EP3IN" "0,1"
|
|
bitfld.long 0x4 18. "EP2IN,EP2IN" "0,1"
|
|
bitfld.long 0x4 17. "EP1IN,EP1IN" "0,1"
|
|
bitfld.long 0x4 16. "EP0,EP0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "EP5OUT,EP5OUT" "0,1"
|
|
bitfld.long 0x4 12. "EP4OUT,EP4OUT" "0,1"
|
|
bitfld.long 0x4 11. "EP3OUT,EP3OUT" "0,1"
|
|
bitfld.long 0x4 10. "EP2OUT,EP2OUT" "0,1"
|
|
bitfld.long 0x4 9. "EP1OUT,EP1OUT" "0,1"
|
|
bitfld.long 0x4 3. "SOF,SOF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "Reset,Reset" "0,1"
|
|
bitfld.long 0x4 1. "Resume,Resume" "0,1"
|
|
bitfld.long 0x4 0. "Suspend,Suspend" "0,1"
|
|
line.long 0x8 "INTRE,INTRE"
|
|
bitfld.long 0x8 21. "EP5INE,EP5INE" "0,1"
|
|
bitfld.long 0x8 20. "EP4INE,EP4INE" "0,1"
|
|
bitfld.long 0x8 19. "EP3INE,EP3INE" "0,1"
|
|
bitfld.long 0x8 18. "EP2INE,EP2INE" "0,1"
|
|
bitfld.long 0x8 17. "EP1INE,EP1INE" "0,1"
|
|
bitfld.long 0x8 16. "EP0,EP0" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "EP5OUTE,EP5OUTE" "0,1"
|
|
bitfld.long 0x8 12. "EP4OUTE,EP4OUTE" "0,1"
|
|
bitfld.long 0x8 11. "EP3OUTE,EP3OUTE" "0,1"
|
|
bitfld.long 0x8 10. "EP2OUTE,EP2OUTE" "0,1"
|
|
bitfld.long 0x8 9. "EP1OUTE,EP1OUTE" "0,1"
|
|
bitfld.long 0x8 3. "EN_SOF,EN_SOF" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EN_Reset,EN_Reset" "0,1"
|
|
bitfld.long 0x8 1. "EN_Resume,EN_Resume" "0,1"
|
|
bitfld.long 0x8 0. "EN_Suspend,EN_Suspend" "0,1"
|
|
wgroup.long 0xC++0x13
|
|
line.long 0x0 "FRAME,FRAME"
|
|
hexmask.long.byte 0x0 16.--19. 1. "INDEX,INDEX"
|
|
hexmask.long.word 0x0 0.--10. 1. "FramNUM,FramNUM"
|
|
line.long 0x4 "EP0CSR,EP0CSR"
|
|
bitfld.long 0x4 8. "COUNT0,COUNT0" "0,1"
|
|
bitfld.long 0x4 7. "ServicedSetupEnd,ServicedSetupEnd" "0,1"
|
|
bitfld.long 0x4 6. "ServicedOutPktRdy,ServicedOutPktRdy" "0,1"
|
|
bitfld.long 0x4 5. "SendStall,OutPktRdy" "0,1"
|
|
bitfld.long 0x4 4. "SetupEnd,SetupEnd" "0,1"
|
|
bitfld.long 0x4 3. "DataEnd,DataEnd" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SentStall,SentStall" "0,1"
|
|
bitfld.long 0x4 1. "InPktRdy,InPktRdy" "0,1"
|
|
bitfld.long 0x4 0. "OutPktRdy,OutPktRdy" "0,1"
|
|
line.long 0x8 "INEPxCSR,INEPxCSR"
|
|
bitfld.long 0x8 16. "INMAXP,INMAXP" "0,1"
|
|
bitfld.long 0x8 14. "ClrDataTog,ClrDataTog" "0,1"
|
|
bitfld.long 0x8 13. "SentStall,SentStall" "0,1"
|
|
bitfld.long 0x8 12. "SendStall,SendStall" "0,1"
|
|
bitfld.long 0x8 11. "FlushFIFO,FlushFIFO" "0,1"
|
|
bitfld.long 0x8 10. "UnderRun,UnderRun" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "FIFONotEmpty,FIFONotEmpty" "0,1"
|
|
bitfld.long 0x8 8. "InPktRdy,InPktRdy" "0,1"
|
|
bitfld.long 0x8 7. "AutoSet,AutoSet" "0,1"
|
|
bitfld.long 0x8 6. "ISO,ISO" "0,1"
|
|
bitfld.long 0x8 5. "Mode,Mode" "0,1"
|
|
bitfld.long 0x8 4. "DMAEnab,DMAEnab" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FrcDataTog,FrcDataTog" "0,1"
|
|
line.long 0xC "OUTEPxCSR,OUTEPxCSR"
|
|
bitfld.long 0xC 16. "INMAXP,INMAXP" "0,1"
|
|
bitfld.long 0xC 15. "ClrDataTog,ClrDataTog" "0,1"
|
|
bitfld.long 0xC 14. "SentStall,SentStall" "0,1"
|
|
bitfld.long 0xC 13. "SendStall,SendStall" "0,1"
|
|
bitfld.long 0xC 12. "FlushFIFO,FlushFIFO" "0,1"
|
|
bitfld.long 0xC 11. "DataError,DataError" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "OverRun,OverRun" "0,1"
|
|
bitfld.long 0xC 9. "FIFOFull,FIFOFull" "0,1"
|
|
bitfld.long 0xC 8. "OutPktRdy,OutPktRdy" "0,1"
|
|
bitfld.long 0xC 7. "AutoClear,AutoClear" "0,1"
|
|
bitfld.long 0xC 6. "ISO,ISO" "0,1"
|
|
bitfld.long 0xC 5. "DMAEnab,DMAEnab" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "DMAMode,DMAMode" "0,1"
|
|
line.long 0x10 "OUTCOUNT,OUTCOUNT"
|
|
hexmask.long.word 0x10 0.--9. 1. "OUTCOUNT,OUTCOUNT"
|
|
tree.end
|
|
tree "WWDG (System Window Watchdog)"
|
|
base ad:0x40002C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register (WWDG_CR)"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register (WWDG_CFR)"
|
|
bitfld.long 0x4 9. "EWI,Early Wakeup Interrupt" "0,1"
|
|
bitfld.long 0x4 7.--8. "WDGTB,Timer Base" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register (WWDG_SR)"
|
|
bitfld.long 0x8 0. "EWIF,Early Wakeup Interrupt flag" "0,1"
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
|