48159 lines
3.2 MiB
48159 lines
3.2 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32H7S On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2024-04-19 NEJ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: Generated (TRACE32, build: 168685.), based on: STM32H7S.svd (Ver. 1.0)
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; @Core: Cortex-M7F
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; @Chip: STM32H7S3A8, STM32H7S3I8, STM32H7S3L8, STM32H7S3R8,
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; STM32H7S3V8, STM32H7S3Z8, STM32H7S7A8, STM32H7S7I8,
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; STM32H7S7L8, STM32H7S7Z8
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32h7s.per 17801 2024-04-22 11:12:10Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC27=Cortex-M7"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
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line.long 0x08 "DCISW,Data cache invalidate by set/way"
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line.long 0x0C "DCCMVAU,Data cache by address to PoU"
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line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
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line.long 0x14 "DCCSW,Data cache clean by set/way"
|
|
line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
|
|
line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
|
|
group.long 0xF90++0x13
|
|
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digtal Converter)"
|
|
base ad:0x0
|
|
tree "ADC1"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred"
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred"
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred"
|
|
newline
|
|
bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete"
|
|
bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete"
|
|
newline
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete"
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
newline
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.."
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled"
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL launches a calibration in..,1: Writing ADCAL launches a calibration in.."
|
|
newline
|
|
bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled."
|
|
newline
|
|
bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing."
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing."
|
|
newline
|
|
bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
line.long 0xC "ADC_CFGR,ADC configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected queue disable" "0: Injected queue enabled,1: Injected queue disabled"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
newline
|
|
bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled"
|
|
bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels"
|
|
newline
|
|
bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels"
|
|
bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
newline
|
|
bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.."
|
|
bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled"
|
|
newline
|
|
bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels"
|
|
bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled"
|
|
newline
|
|
bitfld.long 0xC 15. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on"
|
|
newline
|
|
bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode"
|
|
bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
bitfld.long 0xC 9. "EXTSEL4,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
newline
|
|
bitfld.long 0xC 8. "EXTSEL3,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
bitfld.long 0xC 7. "EXTSEL2,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
newline
|
|
bitfld.long 0xC 6. "EXTSEL1,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
bitfld.long 0xC 5. "EXTSEL0,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
newline
|
|
bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit"
|
|
bitfld.long 0xC 2. "ADFCFG,ADF mode configuration" "0: ADF mode disabled,1: ADF mode enabled"
|
|
newline
|
|
bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA One Shot mode selected,1: DMA Circular mode selected"
|
|
bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
line.long 0x10 "ADC_CFGR2,ADC configuration register 2"
|
|
bitfld.long 0x10 27. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled"
|
|
bitfld.long 0x10 26. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.."
|
|
newline
|
|
bitfld.long 0x10 25. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.."
|
|
bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.."
|
|
newline
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled"
|
|
newline
|
|
bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled"
|
|
line.long 0x14 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time." "0: The sampling time remains set to 2.5 ADC clock..,1: 2.5 ADC clock cycle sampling time becomes 3.5.."
|
|
bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
line.long 0x18 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_TR1,ADC watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_TR2,ADC watchdog threshold register 2"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_TR3,ADC watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,Analog watchdog 3 lower threshold"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "ADC_SQR1,ADC regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "ADC_SQR2,ADC regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence"
|
|
line.long 0x8 "ADC_SQR3,ADC regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence"
|
|
line.long 0xC "ADC_SQR4,ADC regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC regular data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "ADC_JSQR,ADC injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence"
|
|
newline
|
|
bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS = 0 (queue enabled) hardware and..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External Trigger Selection for injected group"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "ADC_OFR1,ADC offset 1 register"
|
|
bitfld.long 0x0 31. "OFFSET_EN,Offset y enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
|
|
newline
|
|
bitfld.long 0x0 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
|
|
bitfld.long 0x0 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
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line.long 0x4 "ADC_OFR2,ADC offset 2 register"
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bitfld.long 0x4 31. "OFFSET_EN,Offset y enable" "0,1"
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|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
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newline
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bitfld.long 0x4 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
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bitfld.long 0x4 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
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newline
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hexmask.long.word 0x4 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
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line.long 0x8 "ADC_OFR3,ADC offset 3 register"
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bitfld.long 0x8 31. "OFFSET_EN,Offset y enable" "0,1"
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hexmask.long.byte 0x8 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
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newline
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bitfld.long 0x8 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
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bitfld.long 0x8 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
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newline
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hexmask.long.word 0x8 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
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line.long 0xC "ADC_OFR4,ADC offset 4 register"
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bitfld.long 0xC 31. "OFFSET_EN,Offset y enable" "0,1"
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hexmask.long.byte 0xC 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
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newline
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bitfld.long 0xC 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
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bitfld.long 0xC 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
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newline
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hexmask.long.word 0xC 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
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rgroup.long 0x80++0xF
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line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register"
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hexmask.long.word 0x0 0.--15. 1. "JDATA,Injected data"
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line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register"
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hexmask.long.word 0x4 0.--15. 1. "JDATA,Injected data"
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line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register"
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hexmask.long.word 0x8 0.--15. 1. "JDATA,Injected data"
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line.long 0xC "ADC_JDR4,ADC injected channel 4 data register"
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hexmask.long.word 0xC 0.--15. 1. "JDATA,Injected data"
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group.long 0xA0++0x7
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line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
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hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,Analog watchdog 2 channel selection"
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line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
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hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,Analog watchdog 3 channel selection"
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group.long 0xB0++0x7
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line.long 0x0 "ADC_DIFSEL,ADC Differential mode Selection Register"
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hexmask.long.tbyte 0x0 0.--18. 1. "DIFSEL,Differential mode for channels 18 to 0."
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line.long 0x4 "ADC_CALFACT,ADC Calibration Factors"
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hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,Calibration Factors in differential mode"
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hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,Calibration Factors In Single-ended mode"
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group.long 0xC8++0x3
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line.long 0x0 "ADC_OR,ADC option register"
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bitfld.long 0x0 0. "OP0,Option bit 0" "0: V<sub>DDCORE </sub>channel disabled,1: V<sub>DDCORE </sub>channel enabled"
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tree.end
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tree "ADC2"
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base ad:0x40022100
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group.long 0x0++0x1B
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line.long 0x0 "ADC_ISR,ADC interrupt and status register"
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bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred"
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bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred"
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newline
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bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred"
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bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred"
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newline
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bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete"
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bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete"
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newline
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bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
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bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete"
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newline
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bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete"
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bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached"
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newline
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bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
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line.long 0x4 "ADC_IER,ADC interrupt enable register"
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bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.."
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|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled"
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newline
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bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled"
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|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled"
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newline
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bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.."
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|
bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.."
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newline
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bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
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|
bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
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|
newline
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bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.."
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|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
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|
newline
|
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bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
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|
bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL launches a calibration in..,1: Writing ADCAL launches a calibration in.."
|
|
newline
|
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bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled."
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|
newline
|
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bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing."
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing."
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|
newline
|
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bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.."
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bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.."
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newline
|
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bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
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|
bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
line.long 0xC "ADC_CFGR,ADC configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected queue disable" "0: Injected queue enabled,1: Injected queue disabled"
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hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
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newline
|
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bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled"
|
|
bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels"
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|
newline
|
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bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels"
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bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
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newline
|
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bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.."
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|
bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled"
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|
newline
|
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bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels"
|
|
bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled"
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newline
|
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bitfld.long 0xC 15. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on"
|
|
newline
|
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bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode"
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|
bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
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|
newline
|
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bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
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bitfld.long 0xC 9. "EXTSEL4,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
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|
newline
|
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bitfld.long 0xC 8. "EXTSEL3,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
bitfld.long 0xC 7. "EXTSEL2,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
newline
|
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bitfld.long 0xC 6. "EXTSEL1,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
|
|
bitfld.long 0xC 5. "EXTSEL0,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1"
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|
newline
|
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bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit"
|
|
bitfld.long 0xC 2. "ADFCFG,ADF mode configuration" "0: ADF mode disabled,1: ADF mode enabled"
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|
newline
|
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bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA One Shot mode selected,1: DMA Circular mode selected"
|
|
bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
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line.long 0x10 "ADC_CFGR2,ADC configuration register 2"
|
|
bitfld.long 0x10 27. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled"
|
|
bitfld.long 0x10 26. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.."
|
|
newline
|
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bitfld.long 0x10 25. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.."
|
|
bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.."
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|
newline
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift"
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|
newline
|
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bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled"
|
|
newline
|
|
bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled"
|
|
line.long 0x14 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time." "0: The sampling time remains set to 2.5 ADC clock..,1: 2.5 ADC clock cycle sampling time becomes 3.5.."
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|
bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
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bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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newline
|
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bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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newline
|
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bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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newline
|
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bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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newline
|
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bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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line.long 0x18 "ADC_SMPR2,ADC sample time register 2"
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|
bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
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bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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newline
|
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bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
newline
|
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bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
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newline
|
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bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
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newline
|
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bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_TR1,ADC watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.."
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|
newline
|
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hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_TR2,ADC watchdog threshold register 2"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_TR3,ADC watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,Analog watchdog 3 lower threshold"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "ADC_SQR1,ADC regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "ADC_SQR2,ADC regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence"
|
|
line.long 0x8 "ADC_SQR3,ADC regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence"
|
|
line.long 0xC "ADC_SQR4,ADC regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC regular data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "ADC_JSQR,ADC injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence"
|
|
newline
|
|
bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS = 0 (queue enabled) hardware and..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External Trigger Selection for injected group"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "ADC_OFR1,ADC offset 1 register"
|
|
bitfld.long 0x0 31. "OFFSET_EN,Offset y enable" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
|
|
newline
|
|
bitfld.long 0x0 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
|
|
bitfld.long 0x0 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
|
|
line.long 0x4 "ADC_OFR2,ADC offset 2 register"
|
|
bitfld.long 0x4 31. "OFFSET_EN,Offset y enable" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
|
|
newline
|
|
bitfld.long 0x4 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
|
|
bitfld.long 0x4 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
|
|
line.long 0x8 "ADC_OFR3,ADC offset 3 register"
|
|
bitfld.long 0x8 31. "OFFSET_EN,Offset y enable" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
|
|
newline
|
|
bitfld.long 0x8 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
|
|
bitfld.long 0x8 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
|
|
line.long 0xC "ADC_OFR4,ADC offset 4 register"
|
|
bitfld.long 0xC 31. "OFFSET_EN,Offset y enable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y"
|
|
newline
|
|
bitfld.long 0xC 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.."
|
|
bitfld.long 0xC 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected channel 4 data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA,Injected data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,Analog watchdog 2 channel selection"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,Analog watchdog 3 channel selection"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "ADC_DIFSEL,ADC Differential mode Selection Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "DIFSEL,Differential mode for channels 18 to 0."
|
|
line.long 0x4 "ADC_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,Calibration Factors in differential mode"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,Calibration Factors In Single-ended mode"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "ADC_OR,ADC option register"
|
|
bitfld.long 0x0 0. "OP0,Option bit 0" "0: V<sub>DDCORE </sub>channel disabled,1: V<sub>DDCORE </sub>channel enabled"
|
|
tree.end
|
|
tree "ADC12_common"
|
|
base ad:0x40022300
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "ADC_CSR,ADC common status register"
|
|
bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1"
|
|
bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1"
|
|
bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of the master ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1"
|
|
bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1"
|
|
bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1"
|
|
bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1"
|
|
bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common control register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: V<sub>BAT</sub> channel disabled,1: V<sub>BAT</sub> channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,V<sub>SENSE</sub> enable" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,V<sub>REFINT</sub> enable" "0: V<sub>REFINT</sub> channel disabled,1: V<sub>REFINT</sub> channel enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0: adc_ker_ck (x = 1/2) (Asynchronous clock mode)..,1: adc_hclk/1 (Synchronous clock mode). This..,2: adc_hclk/2 (Synchronous clock mode),3: adc_hclk/4 (Synchronous clock mode)"
|
|
bitfld.long 0x0 14.--15. "MDMA,Direct memory access mode for dual ADC mode" "0: MDMA mode disabled,1: FIELD Reserved,2: MDMA mode enabled for 12 and 10-bit resolution,3: MDMA mode enabled for 8 and 6-bit resolution"
|
|
newline
|
|
bitfld.long 0x0 13. "DMACFG,DMA configuration (for dual ADC mode)" "0: DMA One Shot mode selected,1: DMA Circular mode selected"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling phases"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection"
|
|
rgroup.long 0x30C++0x3
|
|
line.long 0x0 "ADC_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC."
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "ADC_HWCFGR0,ADC hardware configuration register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IDLEVALUE,Idle value for non-selected channels"
|
|
hexmask.long.byte 0x0 8.--11. 1. "OPBITS,Number of option bits"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "MULPIPE,Number of pipeline stages"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADCNUM,Number of ADCs implemented"
|
|
line.long 0x4 "ADC_VERR,ADC version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "ADC_IPDR,ADC identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Peripheral identifier"
|
|
line.long 0xC "ADC_SIDR,ADC size identification register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
tree.end
|
|
tree "ADF (Audio Digital Filter)"
|
|
base ad:0x4002F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ADF_GCR,ADF global control register"
|
|
bitfld.long 0x0 0. "TRGO,Trigger output control" "0: Write 0 has no effect. Read 0 means that the..,1: Write 1 generates a positive pulse on the.."
|
|
line.long 0x4 "ADF_CKGCR,ADF clock generator control register"
|
|
rbitfld.long 0x4 31. "CKGACTIVE,Clock generator active flag" "0: The clock generator is not active and can be..,1: The clock generator is active and protected.."
|
|
hexmask.long.byte 0x4 24.--30. 1. "PROCDIV,Divider to control the serial interface clock"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "CCKDIV,Divider to control the ADF_CCK clock"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TRGSRC,Digital filter trigger signal selection"
|
|
newline
|
|
bitfld.long 0x4 8. "TRGSENS,CKGEN trigger sensitivity selection" "0: A rising edge event triggers the activation of..,1: A falling edge even triggers the activation of.."
|
|
bitfld.long 0x4 6. "CCK1DIR,ADF_CCK1 direction" "0: The ADF_CCK1 pin direction is in input.,1: The ADF_CCK1 pin direction is in output."
|
|
newline
|
|
bitfld.long 0x4 5. "CCK0DIR,ADF_CCK0 direction" "0: The ADF_CCK0 pin direction is in input.,1: The ADF_CCK0 pin direction is in output."
|
|
bitfld.long 0x4 4. "CKGMOD,Clock generator mode" "0: The kernel clock is provided to the dividers as..,1: The kernel clock is provided to the dividers.."
|
|
newline
|
|
bitfld.long 0x4 2. "CCK1EN,ADF_CCK1 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the ADF_CCK1 pin."
|
|
bitfld.long 0x4 1. "CCK0EN,ADF_CCK0 clock enable" "0: Bitstream clock not generated,1: Bitstream clock generated on the ADF_CCK0 pin"
|
|
newline
|
|
bitfld.long 0x4 0. "CKGDEN,CKGEN dividers enable" "0: CKGEN dividers disabled,1: CKGEN dividers enabled"
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "ADF_SITF0CR,ADF serial interface control register 0"
|
|
rbitfld.long 0x0 31. "SITFACTIVE,Serial interface active flag" "0: The serial interface is not active and can be..,1: The serial interface is active and protected.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "STH,Manchester symbol threshold/SPI threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "SITFMOD,Serial interface type" "0: LF_MASTER SPI mode,1: Normal SPI mode,2: Manchester mode: rising edge = logic 0 falling..,3: Manchester mode: rising edge = logic 1 falling.."
|
|
bitfld.long 0x0 1.--2. "SCKSRC,Serial clock source" "0: Serial clock source is ADF_CCK0.,1: Serial clock source is ADF_CCK1.,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "SITFEN,Serial interface enable" "0: Serial interface disabled,1: Serial interface enabled"
|
|
line.long 0x4 "ADF_BSMX0CR,ADF bitstream matrix control register 0"
|
|
rbitfld.long 0x4 31. "BSMXACTIVE,BSMX active flag" "0: BSMX is not active and can be configured if..,1: BSMX is active and protected fields cannot be.."
|
|
hexmask.long.byte 0x4 0.--4. 1. "BSSEL,Bitstream selection"
|
|
line.long 0x8 "ADF_DFLT0CR,ADF digital filter control register 0"
|
|
rbitfld.long 0x8 31. "DFLTACTIVE,DFLT0 active flag" "0: DFLT0 not active (can be re-enabled again via..,1: DFLT0 active"
|
|
rbitfld.long 0x8 30. "DFLTRUN,DFLT0 run status flag" "0: DFLT0 not running and ready to accept a new..,1: DFLT0running"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--27. 1. "NBDIS,Number of samples to be discarded"
|
|
hexmask.long.byte 0x8 12.--15. 1. "TRGSRC,DFLT0 trigger signal selection"
|
|
newline
|
|
bitfld.long 0x8 8. "TRGSENS,DFLT0 trigger sensitivity selection" "0: A rising edge event triggers the acquisition.,1: A falling edge even triggers the acquisition."
|
|
bitfld.long 0x8 4.--6. "ACQMOD,DFLT0 trigger mode" "0: Asynchronous continuous acquisition mode,1: Asynchronous single-shot acquisition mode,2: Synchronous continuous acquisition mode,3: Synchronous single-shot acquisition mode,4: Window continuous acquisition mode,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 2. "FTH,RXFIFO threshold selection" "0: RXFIFO threshold event generated when the RXFIFO..,1: RXFIFO threshold event generated when the RXFIFO.."
|
|
bitfld.long 0x8 1. "DMAEN,DMA requests enable" "0: DMA interface for the corresponding digital..,1: DMA interface for the corresponding digital.."
|
|
newline
|
|
bitfld.long 0x8 0. "DFLTEN,DFLT0 enable" "0: Acquisition immediately stopped,1: Acquisition immediately started if ACQMOD[2:0] =.."
|
|
line.long 0xC "ADF_DFLT0CICR,ADF digital filer configuration register 0"
|
|
hexmask.long.byte 0xC 20.--25. 1. "SCALE,Scaling factor selection"
|
|
bitfld.long 0xC 16. "MCICD8,CIC decimation ratio selection" "0: Decimation ratio is 2.,1: Decimation ratio is 2."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "MCICD,CIC decimation ratio selection"
|
|
bitfld.long 0xC 4.--6. "CICMOD,Select the CIC order" "?,?,?,?,4: MCIC configured in single Sinc<sup>4</sup> filter,5: MCIC configured in single Sinc<sup>5</sup> filter,?,?"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "DATSRC,Source data for the digital filter" "?,?,2: Stream coming from the ADCITF1 selected,3: Stream coming from the ADCITF2 selected"
|
|
line.long 0x10 "ADF_DFLT0RSFR,ADF reshape filter configuration register 0"
|
|
bitfld.long 0x10 8.--9. "HPFC,High-pass filter cut-off frequency" "0: Cut-off frequency = 0.000625 x FPCM,1: Cut-off frequency = 0.00125 x FPCM,2: Cut-off frequency = 0.00250 x FPCM,3: Cut-off frequency = 0.00950 x FPCM"
|
|
bitfld.long 0x10 7. "HPFBYP,High-pass filter bypass" "0: HPF not bypassed (default value),1: HPF bypassed"
|
|
newline
|
|
bitfld.long 0x10 4. "RSFLTD,Reshaper filter decimation ratio" "0: Decimation ratio is 4 (default value).,1: Decimation ratio is 1."
|
|
bitfld.long 0x10 0. "RSFLTBYP,Reshaper filter bypass" "0: Reshape filter not bypassed (default value),1: Reshape filter bypassed"
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "ADF_DLY0CR,ADF delay control register 0"
|
|
rbitfld.long 0x0 31. "SKPBF,Skip busy flag" "0: ADF ready to accept a new value into SKPDLY[6:0],1: Last valid SKPDLY[6:0] still under precessing"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SKPDLY,Delay to apply to a bitstream"
|
|
group.long 0xAC++0x7
|
|
line.long 0x0 "ADF_DFLT0IER,ADF DFLT0 interrupt enable register"
|
|
bitfld.long 0x0 13. "SDLVLIE,SAD sound-level value ready enable" "0: Sound-level-ready interrupt disabled,1: Sound-level-ready interrupt enabled"
|
|
bitfld.long 0x0 12. "SDDETIE,Sound activity detection interrupt enable" "0: Sound-trigger interrupt disabled,1: Sound-trigger interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "RFOVRIE,Reshape filter overrun interrupt enable" "0: Reshape filter overrun interrupt disabled,1: Reshape filter overrun interrupt enabled"
|
|
bitfld.long 0x0 10. "CKABIE,Clock absence detection interrupt enable" "0: Clock absence interrupt disabled,1: Clock absence interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "SATIE,Saturation detection interrupt enable" "0: Saturation interrupt disabled,1: Saturation interrupt enabled"
|
|
bitfld.long 0x0 1. "DOVRIE,Data overflow interrupt enable" "0: Data overflow interrupt disabled,1: Data overflow interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "FTHIE,RXFIFO threshold interrupt enable" "0: RXFIFO threshold interrupt disabled,1: RXFIFO threshold interrupt enabled"
|
|
line.long 0x4 "ADF_DFLT0ISR,ADF DFLT0 interrupt status register 0"
|
|
bitfld.long 0x4 13. "SDLVLF,Sound level value ready flag" "0: Read 0 means that new sound level value is not..,1: Read 1 means that new sound level value is.."
|
|
bitfld.long 0x4 12. "SDDETF,Sound activity detection flag" "0: Read 0 means that no sound activity is detected.,1: Read 1 means that sound activity is detected."
|
|
newline
|
|
bitfld.long 0x4 11. "RFOVRF,Reshape filter overrun detection flag" "0: Read 0 means that no reshape filter overrun is..,1: Read 1 means that reshape filter overrun is.."
|
|
bitfld.long 0x4 10. "CKABF,Clock absence detection flag" "0: Read 0 means that no clock absence is detected.,1: Read 1 means that a clock absence is detected."
|
|
newline
|
|
bitfld.long 0x4 9. "SATF,Saturation detection flag" "0: Read 0 means that no saturation is detected.,1: Read 1 means that a saturation is detected."
|
|
rbitfld.long 0x4 3. "RXNEF,RXFIFO not empty flag" "0: RXFIFO empty,1: RXFIFO not empty"
|
|
newline
|
|
bitfld.long 0x4 1. "DOVRF,Data overflow flag" "0: Read 0 means that no overflow is detected. Write..,1: Read 1 means that an overflow is detected; Write.."
|
|
rbitfld.long 0x4 0. "FTHF,RXFIFO threshold flag" "0: RXFIFO threshold not reached,1: RXFIFO threshold reached"
|
|
group.long 0xB8++0x7
|
|
line.long 0x0 "ADF_SADCR,ADF SAD control register"
|
|
rbitfld.long 0x0 31. "SADACTIVE,SAD Active flag" "0: SAD not active and can be configured if needed,1: SAD active and protected fields cannot be.."
|
|
bitfld.long 0x0 12.--13. "SADMOD,SAD working mode" "0: Threshold value computed according to the..,1: Threshold value equal to ANMIN[12:0] multiplied..,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FRSIZE,Frame size" "0: 8 PCM samples used to compute the short-term..,1: 16 PCM samples used to compute the short-term..,2: 32 PCM samples used to compute the short-term..,3: 64 PCM samples used to compute the short-term..,4: 128 PCM samples used to compute the short-term..,5: 256 PCM samples used to compute the short-term..,?,?"
|
|
bitfld.long 0x0 7. "HYSTEN,Hysteresis enable" "0: Hysteresis function disabled. THR<sub>H</sub> is..,1: Hysteresis function enabled. THR<sub>H</sub> is.."
|
|
newline
|
|
rbitfld.long 0x0 4.--5. "SADST,SAD state" "0: SAD in LEARN state,1: SAD in MONITOR state,?,3: SAD in DETECT state"
|
|
bitfld.long 0x0 3. "DETCFG,Sound trigger event configuration" "0: sddet_evt generated when SAD enters the MONITOR..,1: sddet_evt generated when SAD enters or exits the.."
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATCAP,Data capture mode" "0: Samples from DFLT0 not transfered into the memory,1: Samples from DFLT0 transfered into the memory..,?,?"
|
|
bitfld.long 0x0 0. "SADEN,Sound activity detector enable" "0: SAD disabled and SAD state reset,1: SAD enabled"
|
|
line.long 0x4 "ADF_SADCFGR,ADF SAD configuration register"
|
|
hexmask.long.word 0x4 16.--28. 1. "ANMIN,Minimum noise level"
|
|
bitfld.long 0x4 12.--14. "HGOVR,Hangover time window" "0: SAD back to MONITOR state if sound is below..,1: SAD back to MONITOR state if sound is below..,2: SAD back to MONITOR state if sound is below..,3: SAD back to MONITOR state if sound is below..,4: SAD back to MONITOR state if sound is below..,5: SAD back to MONITOR state if sound is below..,6: SAD back to MONITOR state if sound is below..,7: SAD back to MONITOR state if sound is below.."
|
|
newline
|
|
bitfld.long 0x4 8.--10. "LFRNB,Number of learning frames" "0: 2 frames used to compute the initial noise level,1: 4 frames used to compute the initial noise level,2: 8 frames used to compute the initial noise level,3: 16 frames used to compute the initial noise level,?,?,?,?"
|
|
bitfld.long 0x4 4.--6. "ANSLP,Ambient noise slope control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "SNTHR,Signal to noise threshold"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "ADF_SADSDLVR,ADF SAD sound level register"
|
|
hexmask.long.word 0x0 0.--14. 1. "SDLVL,Short term sound level"
|
|
line.long 0x4 "ADF_SADANLVR,ADF SAD ambient noise level register"
|
|
hexmask.long.word 0x4 0.--14. 1. "ANLVL,Ambient noise level estimation"
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "ADF_DFLT0DR,ADF digital filter data register 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data processed by DFT0"
|
|
tree.end
|
|
tree "CEC (HDMI-CEC Controller)"
|
|
base ad:0x40006C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CEC_CR,CEC control register"
|
|
bitfld.long 0x0 2. "TXEOM,Tx end of message" "0: TXDR data byte is transmitted with EOM = 0,1: TXDR data byte is transmitted with EOM = 1"
|
|
bitfld.long 0x0 1. "TXSOM,Tx start of message" "0: No CEC transmission is on-going,1: CEC transmission command"
|
|
newline
|
|
bitfld.long 0x0 0. "CECEN,CEC enable" "0: CEC peripheral is off.,1: CEC peripheral is on."
|
|
line.long 0x4 "CEC_CFGR,CEC configuration register"
|
|
bitfld.long 0x4 31. "LSTN,Listen mode" "0: CEC peripheral receives only message addressed..,1: CEC peripheral receives messages addressed to.."
|
|
hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration"
|
|
newline
|
|
bitfld.long 0x4 8. "SFTOP,SFT option bit" "0: SFT timer starts when TXSOM is set by software.,1: SFT timer starts automatically at the end of.."
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid error-bit generation in broadcast" "0: BRE detection with BRESTP = 1 and BREGEN = 0 on..,1: Error-bit is not generated in the same condition.."
|
|
newline
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate error-bit on long bit period error" "0: LBPE detection does not generate an error-bit on..,1: LBPE detection generates an error-bit on the CEC.."
|
|
bitfld.long 0x4 5. "BREGEN,Generate error-bit on bit rising error" "0: BRE detection does not generate an error-bit on..,1: BRE detection generates an error-bit on the CEC.."
|
|
newline
|
|
bitfld.long 0x4 4. "BRESTP,Rx-stop on bit rising error" "0: BRE detection does not stop reception of the CEC..,1: BRE detection stops message reception."
|
|
bitfld.long 0x4 3. "RXTOL,Rx-tolerance" "0: Standard tolerance margin:,1: Extended tolerance"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SFT,Signal free time" "?,1: 0.5 nominal data bit periods,2: 1.5 nominal data bit periods,3: 2.5 nominal data bit periods,4: 3.5 nominal data bit periods,5: 4.5 nominal data bit periods,6: 5.5 nominal data bit periods,7: 6.5 nominal data bit periods"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CEC_TXDR,CEC Tx data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx data"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CEC_RXDR,CEC Rx data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx data"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CEC_ISR,CEC interrupt and status register"
|
|
bitfld.long 0x0 12. "TXACKE,Tx-missing acknowledge error" "0,1"
|
|
bitfld.long 0x0 11. "TXERR,Tx-error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXUDR,Tx-buffer underrun" "0,1"
|
|
bitfld.long 0x0 9. "TXEND,End of transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXBR,Tx-byte request" "0,1"
|
|
bitfld.long 0x0 7. "ARBLST,Arbitration lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXACKE,Rx-missing acknowledge" "0,1"
|
|
bitfld.long 0x0 5. "LBPE,Rx-long bit period error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SBPE,Rx-short bit period error" "0,1"
|
|
bitfld.long 0x0 3. "BRE,Rx-bit rising error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXOVR,Rx-overrun" "0,1"
|
|
bitfld.long 0x0 1. "RXEND,End of reception" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXBR,Rx-byte received" "0,1"
|
|
line.long 0x4 "CEC_IER,CEC interrupt enable register"
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-missing acknowledge error interrupt enable" "0: TXACKE interrupt disabled,1: TXACKE interrupt enabled"
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-error interrupt enable" "0: TXERR interrupt disabled,1: TXERR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-underrun interrupt enable" "0: TXUDR interrupt disabled,1: TXUDR interrupt enabled"
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-end of message interrupt enable" "0: TXEND interrupt disabled,1: TXEND interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-byte request interrupt enable" "0: TXBR interrupt disabled,1: TXBR interrupt enabled"
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration lost interrupt enable" "0: ARBLST interrupt disabled,1: ARBLST interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-missing acknowledge error interrupt enable" "0: RXACKE interrupt disabled,1: RXACKE interrupt enabled"
|
|
bitfld.long 0x4 5. "LBPEIE,Long bit period error interrupt enable" "0: LBPE interrupt disabled,1: LBPE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "SBPEIE,Short bit period error interrupt enable" "0: SBPE interrupt disabled,1: SBPE interrupt enabled"
|
|
bitfld.long 0x4 3. "BREIE,Bit rising error interrupt enable" "0: BRE interrupt disabled,1: BRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-buffer overrun interrupt enable" "0: RXOVR interrupt disabled,1: RXOVR interrupt enabled"
|
|
bitfld.long 0x4 1. "RXENDIE,End of reception interrupt enable" "0: RXEND interrupt disabled,1: RXEND interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "RXBRIE,Rx-byte received interrupt enable" "0: RXBR interrupt disabled,1: RXBR interrupt enabled"
|
|
tree.end
|
|
tree "CORDIC (CORDIC Co-processor)"
|
|
base ad:0x48004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CORDIC_CSR,CORDIC control/status register"
|
|
rbitfld.long 0x0 31. "RRDY,Result ready flag" "0: No new data in output register,1: CORDIC_RDATA register contains new data."
|
|
bitfld.long 0x0 22. "ARGSIZE,Width of input data" "0: 32-bit,1: 16-bit"
|
|
newline
|
|
bitfld.long 0x0 21. "RESSIZE,Width of output data" "0: 32-bit,1: 16-bit"
|
|
bitfld.long 0x0 20. "NARGS,Number of arguments expected by the CORDIC_WDATA register" "0: Only one 32-bit write (or two 16-bit values if..,1: Two 32-bit values must be written to the.."
|
|
newline
|
|
bitfld.long 0x0 19. "NRES,Number of results in the CORDIC_RDATA register" "0: Only one 32-bit value (or two 16-bit values if..,1: Two 32-bit values are transferred to the.."
|
|
bitfld.long 0x0 18. "DMAWEN,Enable DMA write channel" "0: Disabled. No DMA write requests are generated.,1: Enabled. Requests are generated on the DMA write.."
|
|
newline
|
|
bitfld.long 0x0 17. "DMAREN,Enable DMA read channel" "0: Disabled. No DMA read requests are generated.,1: Enabled. Requests are generated on the DMA read.."
|
|
bitfld.long 0x0 16. "IEN,Enable interrupt." "0: Disabled. No interrupt requests are generated.,1: Enabled. An interrupt request is generated.."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "SCALE,Scaling factor" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRECISION,Precision required (number of iterations)"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FUNC,Function"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "CORDIC_WDATA,CORDIC argument register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG,Function input arguments"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CORDIC_RDATA,CORDIC result register"
|
|
hexmask.long 0x0 0.--31. 1. "RES,Function result"
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x58024C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,CRC data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,CRC independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
|
|
line.long 0x8 "CRC_CR,CRC control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,CRC initial value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
|
|
line.long 0x4 "CRC_POL,CRC polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
tree.end
|
|
tree "CRS (Clock Recovery System)"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CRS_CR,CRS control register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming"
|
|
bitfld.long 0x0 7. "SWSYNC,Generate software SYNC event" "0: No action,1: A software SYNC event is generated."
|
|
newline
|
|
bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable" "0: Automatic trimming disabled TRIM bits can be..,1: Automatic trimming enabled TRIM bits are.."
|
|
bitfld.long 0x0 5. "CEN,Frequency error counter enable" "0: Frequency error counter disabled,1: Frequency error counter enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt enable" "0: Expected SYNC (ESYNCF) interrupt disabled,1: Expected SYNC (ESYNCF) interrupt enabled"
|
|
bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error interrupt enable" "0: Synchronization or trimming error (ERRF)..,1: Synchronization or trimming error (ERRF).."
|
|
newline
|
|
bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt enable" "0: SYNC warning (SYNCWARNF) interrupt disabled,1: SYNC warning (SYNCWARNF) interrupt enabled"
|
|
bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt enable" "0: SYNC event OK (SYNCOKF) interrupt disabled,1: SYNC event OK (SYNCOKF) interrupt enabled"
|
|
line.long 0x4 "CRS_CFGR,CRS configuration register"
|
|
bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection" "0: SYNC active on rising edge (default),1: SYNC active on falling edge"
|
|
bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection" "0: CRS_SYNC pin selected as SYNC signal source,1: LSE selected as SYNC signal source,2: OTG HS SOF selected as SYNC signal source..,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider" "0: SYNC not divided (default),1: SYNC divided by 2,2: SYNC divided by 4,3: SYNC divided by 8,4: SYNC divided by 16,5: SYNC divided by 32,6: SYNC divided by 64,7: SYNC divided by 128"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CRS_ISR,CRS interrupt and status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture"
|
|
bitfld.long 0x0 15. "FEDIR,Frequency error direction" "0: Upcounting direction the actual frequency is..,1: Downcounting direction the actual frequency is.."
|
|
newline
|
|
bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow" "0: No trimming error signalized,1: Trimming error signalized"
|
|
bitfld.long 0x0 9. "SYNCMISS,SYNC missed" "0: No SYNC missed error signalized,1: SYNC missed error signalized"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNCERR,SYNC error" "0: No SYNC error signalized,1: SYNC error signalized"
|
|
bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag" "0: No expected SYNC signalized,1: Expected SYNC signalized"
|
|
newline
|
|
bitfld.long 0x0 2. "ERRF,Error flag" "0: No synchronization or trimming error signalized,1: Synchronization or trimming error signalized"
|
|
bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag" "0: No SYNC warning signalized,1: SYNC warning signalized"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag" "0: No SYNC event OK signalized,1: SYNC event OK signalized"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CRS_ICR,CRS interrupt flag clear register"
|
|
bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag" "0,1"
|
|
bitfld.long 0x0 2. "ERRC,Error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag" "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag" "0,1"
|
|
tree.end
|
|
tree "CRYP (Cryptographic Acceleration)"
|
|
base ad:0x48020800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CRYP_CR,CRYP control register"
|
|
bitfld.long 0x0 31. "IPRST,CRYP peripheral software reset" "0,1"
|
|
bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal-key mode. Key registers are freely usable.,?,2: Shared-key mode. If shared-key mode is properly..,?"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block"
|
|
bitfld.long 0x0 19. "ALGOMODE_1,ALGOMODE[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM or CCM phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase"
|
|
bitfld.long 0x0 15. "CRYPEN,CRYP enable" "0: CRYP disabled,1: CRYP enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "FFLUSH,FIFO flush" "0: No effect,1: FIFO flush enabled"
|
|
bitfld.long 0x0 8.--9. "KEYSIZE,Key size selection" "0: 128-bits,1: 192 bits,2: 256 bits,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DATATYPE,Data type" "0: No swapping (32-bit data).,1: Half-word swapping (16-bit data).,2: Byte swapping (8-bit data).,3: Bit-level swapping."
|
|
bitfld.long 0x0 3.--5. "ALGOMODE,ALGOMODE[2:0]: Algorithm mode" "?,?,?,?,4: Electronic codebook (ECB),5: Cipher Block Chaining (CBC),6: Counter mode (CTR),7: AES key preparation for ECB or CBC decryption"
|
|
newline
|
|
bitfld.long 0x0 2. "ALGODIR,Algorithm direction" "0: Encryption,1: Decryption"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CRYP_SR,CRYP status register"
|
|
bitfld.long 0x0 7. "KEYVALID,Key valid flag" "0: Key not valid,1: Key valid"
|
|
bitfld.long 0x0 6. "KERF,Key error flag" "0: No key error detected,1: Key information failed to load into key registers"
|
|
newline
|
|
bitfld.long 0x0 4. "BUSY,Busy bit" "0: Idle,1: Busy"
|
|
bitfld.long 0x0 3. "OFFU,Output FIFO full flag" "0: Output FIFO is not full,1: Output FIFO is full"
|
|
newline
|
|
bitfld.long 0x0 2. "OFNE,Output FIFO not empty flag" "0: Output FIFO is empty,1: Output FIFO is not empty"
|
|
bitfld.long 0x0 1. "IFNF,Input FIFO not full flag" "0: Input FIFO is full,1: Input FIFO is not full"
|
|
newline
|
|
bitfld.long 0x0 0. "IFEM,Input FIFO empty flag" "0: Input FIFO is not empty,1: Input FIFO is empty"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CRYP_DINR,CRYP data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DIN,Data input"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CRYP_DOUTR,CRYP data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DOUT,Data output"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRYP_DMACR,CRYP DMA control register"
|
|
bitfld.long 0x0 1. "DOEN,DMA output enable" "0: Outgoing data transfer from CRYP via DMA is..,1: Outgoing data transfer from CRYP via DMA is.."
|
|
bitfld.long 0x0 0. "DIEN,DMA input enable" "0: Incoming data transfer to CRYP via DMA is disabled,1: Incoming data transfer to CRYP via DMA is disabled"
|
|
line.long 0x4 "CRYP_IMSCR,CRYP interrupt mask set/clear register"
|
|
bitfld.long 0x4 1. "OUTIM,Output FIFO service interrupt mask" "0: Output FIFO interrupt is disabled (masked)..,1: Output FIFO interrupt is enabled (not masked)"
|
|
bitfld.long 0x4 0. "INIM,Input FIFO service interrupt mask" "0: Input FIFO interrupt is disabled (masked) masked..,1: Input FIFO interrupt is enabled (not masked)"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "CRYP_RISR,CRYP raw interrupt status register"
|
|
bitfld.long 0x0 1. "OUTRIS,Output FIFO service raw interrupt status" "0: No output FIFO event detected,1: Output FIFO full or not empty detected; an.."
|
|
bitfld.long 0x0 0. "INRIS,Input FIFO service raw interrupt status" "0: No input FIFO event detected,1: Input FIFO empty or not full detected; an.."
|
|
line.long 0x4 "CRYP_MISR,CRYP masked interrupt status register"
|
|
bitfld.long 0x4 1. "OUTMIS,Output FIFO service masked interrupt status" "0: No output FIFO event detected or OUTIM mask..,1: Output FIFO full or not empty detected with an.."
|
|
bitfld.long 0x4 0. "INMIS,Input FIFO service masked interrupt status" "0: No input FIFO event detected or INIM mask..,1: Input FIFO empty or not full detected with an.."
|
|
wgroup.long 0x20++0x1F
|
|
line.long 0x0 "CRYP_K0LR,CRYP key register 0L"
|
|
hexmask.long 0x0 0.--31. 1. "K,Key bit x"
|
|
line.long 0x4 "CRYP_K0RR,CRYP key register 0R"
|
|
hexmask.long 0x4 0.--31. 1. "K,Key bit x"
|
|
line.long 0x8 "CRYP_K1LR,CRYP key register 1L"
|
|
hexmask.long 0x8 0.--31. 1. "K,Key bit x"
|
|
line.long 0xC "CRYP_K1RR,CRYP key register 1R"
|
|
hexmask.long 0xC 0.--31. 1. "K,Key bit x"
|
|
line.long 0x10 "CRYP_K2LR,CRYP key register 2L"
|
|
hexmask.long 0x10 0.--31. 1. "K,Key bit x"
|
|
line.long 0x14 "CRYP_K2RR,CRYP key register 2R"
|
|
hexmask.long 0x14 0.--31. 1. "K,Key bit x"
|
|
line.long 0x18 "CRYP_K3LR,CRYP key register 3L"
|
|
hexmask.long 0x18 0.--31. 1. "K,Key bit x"
|
|
line.long 0x1C "CRYP_K3RR,CRYP key register 3R"
|
|
hexmask.long 0x1C 0.--31. 1. "K,Key bit x"
|
|
group.long 0x40++0x4F
|
|
line.long 0x0 "CRYP_IV0LR,CRYP initialization vector register 0L"
|
|
hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector bit x"
|
|
line.long 0x4 "CRYP_IV0RR,CRYP initialization vector register 0R"
|
|
hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector bit x"
|
|
line.long 0x8 "CRYP_IV1LR,CRYP initialization vector register 1L"
|
|
hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector bit x"
|
|
line.long 0xC "CRYP_IV1RR,CRYP initialization vector register 1R"
|
|
hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector bit x"
|
|
line.long 0x10 "CRYP_CSGCMCCM0R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x10 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x14 "CRYP_CSGCMCCM1R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x14 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x18 "CRYP_CSGCMCCM2R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x18 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x1C "CRYP_CSGCMCCM3R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x1C 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x20 "CRYP_CSGCMCCM4R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x20 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x24 "CRYP_CSGCMCCM5R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x24 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x28 "CRYP_CSGCMCCM6R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x28 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x2C "CRYP_CSGCMCCM7R,CRYP context swap GCM-CCM registers"
|
|
hexmask.long 0x2C 0.--31. 1. "CSGCMCCM,Context swap for GCM/GMAC and CCM modes"
|
|
line.long 0x30 "CRYP_CSGCM0R,CRYP context swap GCM registers"
|
|
hexmask.long 0x30 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x34 "CRYP_CSGCM1R,CRYP context swap GCM registers"
|
|
hexmask.long 0x34 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x38 "CRYP_CSGCM2R,CRYP context swap GCM registers"
|
|
hexmask.long 0x38 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x3C "CRYP_CSGCM3R,CRYP context swap GCM registers"
|
|
hexmask.long 0x3C 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x40 "CRYP_CSGCM4R,CRYP context swap GCM registers"
|
|
hexmask.long 0x40 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x44 "CRYP_CSGCM5R,CRYP context swap GCM registers"
|
|
hexmask.long 0x44 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x48 "CRYP_CSGCM6R,CRYP context swap GCM registers"
|
|
hexmask.long 0x48 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
line.long 0x4C "CRYP_CSGCM7R,CRYP context swap GCM registers"
|
|
hexmask.long 0x4C 0.--31. 1. "CSGCM,Context swap for GCM/GMAC modes"
|
|
tree.end
|
|
tree "DBGMCU (MCU Debug Component)"
|
|
base ad:0x5C001000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBGMCU_IDC,DBGMCU identity code register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device ID"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "DBGMCU_CR,DBGMCU configuration register"
|
|
bitfld.long 0x0 28. "TRGOEN,External trigger output enable" "0: Input - TRGIO is connected to TRGIN,1: Output - TRGIO is connected to TRGOUT"
|
|
newline
|
|
bitfld.long 0x0 21. "D1DBGCKEN,D1 debug clock enable" "0: Disabled - D1 domain debug components are..,1: Enabled - D1 domain debug components are clocked.."
|
|
newline
|
|
bitfld.long 0x0 20. "TRACECLKEN,Trace port clock enable." "0: Disabled - TRACECLK is disabled,1: Enabled - TRACECLK is active"
|
|
newline
|
|
bitfld.long 0x0 16. "DCRT,Debug credentials reset type" "0: System reset,1: Power reset"
|
|
newline
|
|
bitfld.long 0x0 2. "DBGSTBY,Debug in Standby mode enable" "0: Normal operation - all clocks are disabled and..,1: Automatic clock stop/power-down disabled - all.."
|
|
newline
|
|
bitfld.long 0x0 1. "DBGSTOP,Debug in Stop mode enable" "0: Normal operation - all clocks are disabled..,1: Automatic clock stop disabled - all active.."
|
|
newline
|
|
bitfld.long 0x0 0. "DBGSLEEP,Debug in Sleep mode enable" "0: Normal operation - the processor clock is..,1: Automatic clock stop disabled - processor clock.."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "DBGMCU_AHB5FZR,DBGMCU AHB5 peripheral freeze register"
|
|
bitfld.long 0x0 15. "DBG_HPDMA_15_STOP,HPDMA channel 15 stop in debug" "0: normal operation. HPDMA channel 15 continues to..,1: stop in debug. HPDMA channel 15 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 14. "DBG_HPDMA_14_STOP,HPDMA channel 14 stop in debug" "0: normal operation. HPDMA channel 14 continues to..,1: stop in debug. HPDMA channel 14 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 13. "DBG_HPDMA_13_STOP,HPDMA channel 13 stop in debug" "0: normal operation. HPDMA channel 13 continues to..,1: stop in debug. HPDMA channel 13 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 12. "DBG_HPDMA_12_STOP,HPDMA channel 12 stop in debug" "0: normal operation. HPDMA channel 12 continues to..,1: stop in debug. HPDMA channel 12 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 11. "DBG_HPDMA_11_STOP,HPDMA channel 11 stop in debug" "0: normal operation. HPDMA channel 11 continues to..,1: stop in debug. HPDMA channel 11 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 10. "DBG_HPDMA_10_STOP,HPDMA channel 10 stop in debug" "0: normal operation. HPDMA channel 10 continues to..,1: stop in debug. HPDMA channel 10 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 9. "DBG_HPDMA_9_STOP,HPDMA channel 9 stop in debug" "0: normal operation. HPDMA channel 9 continues to..,1: stop in debug. HPDMA channel 9 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 8. "DBG_HPDMA_8_STOP,HPDMA channel 8 stop in debug" "0: normal operation. HPDMA channel 8 continues to..,1: stop in debug. HPDMA channel _ is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 7. "DBG_HPDMA_7_STOP,HPDMA channel 7 stop in debug" "0: normal operation. HPDMA channel 7 continues to..,1: stop in debug. HPDMA channel 7 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 6. "DBG_HPDMA_6_STOP,HPDMA channel 6 stop in debug" "0: normal operation. HPDMA channel 6 continues to..,1: stop in debug. HPDMA channel 6 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 5. "DBG_HPDMA_5_STOP,HPDMA channel 5 stop in debug" "0: normal operation. HPDMA channel 5 continues to..,1: stop in debug. HPDMA channel 5 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 4. "DBG_HPDMA_4_STOP,HPDMA channel 4 stop in debug" "0: normal operation. HPDMA channel 4 continues to..,1: stop in debug. HPDMA channel 4 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 3. "DBG_HPDMA_3_STOP,HPDMA channel 3 stop in debug" "0: normal operation. HPDMA channel 3 continues to..,1: stop in debug. HPDMA channel 3 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 2. "DBG_HPDMA_2_STOP,HPDMA channel 2 stop in debug" "0: normal operation. HPDMA channel 2 continues to..,1: stop in debug. HPDMA channel 2 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 1. "DBG_HPDMA_1_STOP,HPDMA channel 1 stop in debug" "0: normal operation. HPDMA channel 1continues to..,1: stop in debug. HPDMA channel 1 is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 0. "DBG_HPDMA_0_STOP,HPDMA channel 0 stop in debug" "0: normal operation. HPDMA channel 0 continues to..,1: stop in debug. HPDMA channel 0 is frozen while.."
|
|
line.long 0x4 "DBGMCU_AHB1FZR,DBGMCU AHB1 peripheral freeze register"
|
|
bitfld.long 0x4 15. "DBG_GPDMA_15_STOP,GPDMA channel 15 stop in debug" "0: normal operation. GPDMA channel 15 continues to..,1: stop in debug. GPDMA channel 15 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 14. "DBG_GPDMA_14_STOP,GPDMA channel 14 stop in debug" "0: normal operation. GPDMA channel 14 continues to..,1: stop in debug. GPDMA channel 14 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 13. "DBG_GPDMA_13_STOP,GPDMA channel 13 stop in debug" "0: normal operation. GPDMA channel 13 continues to..,1: stop in debug. GPDMA channel 13 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 12. "DBG_GPDMA_12_STOP,GPDMA channel 12 stop in debug" "0: normal operation. GPDMA channel 12 continues to..,1: stop in debug. GPDMA channel 12 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_GPDMA_11_STOP,GPDMA channel 11 stop in debug" "0: normal operation. GPDMA channel 11 continues to..,1: stop in debug. GPDMA channel 11 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 10. "DBG_GPDMA_10_STOP,GPDMA channel 10 stop in debug" "0: normal operation. GPDMA channel 10 continues to..,1: stop in debug. GPDMA channel 10 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 9. "DBG_GPDMA_9_STOP,GPDMA channel 9 stop in debug" "0: normal operation. GPDMA channel 9 continues to..,1: stop in debug. GPDMA channel 9 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 8. "DBG_GPDMA_8_STOP,GPDMA channel 8 stop in debug" "0: normal operation. GPDMA channel 8 continues to..,1: stop in debug. GPDMA channel _ is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 7. "DBG_GPDMA_7_STOP,GPDMA channel 7 stop in debug" "0: normal operation. GPDMA channel 7 continues to..,1: stop in debug. GPDMA channel 7 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 6. "DBG_GPDMA_6_STOP,GPDMA channel 6 stop in debug" "0: normal operation. GPDMA channel 6 continues to..,1: stop in debug. GPDMA channel 6 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_GPDMA_5_STOP,GPDMA channel 5 stop in debug" "0: normal operation. GPDMA channel 5 continues to..,1: stop in debug. GPDMA channel 5 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 4. "DBG_GPDMA_4_STOP,GPDMA channel 4 stop in debug" "0: normal operation. GPDMA channel 4 continues to..,1: stop in debug. GPDMA channel 4 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 3. "DBG_GPDMA_3_STOP,GPDMA channel 3 stop in debug" "0: normal operation. GPDMA channel 3 continues to..,1: stop in debug. GPDMA channel 3 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 2. "DBG_GPDMA_2_STOP,GPDMA channel 2 stop in debug" "0: normal operation. GPDMA channel 2 continues to..,1: stop in debug. GPDMA channel 2 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_GPDMA_1_STOP,GPDMA channel 1 stop in debug" "0: normal operation. GPDMA channel 1continues to..,1: stop in debug. GPDMA channel 1 is frozen while.."
|
|
newline
|
|
bitfld.long 0x4 0. "DBG_GPDMA_0_STOP,GPDMA channel 0 stop in debug" "0: normal operation. GPDMA channel 0 continues to..,1: stop in debug. GPDMA channel 0 is frozen while.."
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "DBGMCU_APB1FZR,DBGMCU APB1 peripheral freeze register"
|
|
bitfld.long 0x0 23. "I2C3,I2C3 SMBUS timeout stop in debug" "0: Normal operation - I2C3 SMBUS timeout continues..,1: Stop in debug - I2C3 SMBUS timeout is frozen.."
|
|
newline
|
|
bitfld.long 0x0 22. "I2C2,I2C2 SMBUS timeout stop in debug" "0: Normal operation - I2C2 SMBUS timeout continues..,1: Stop in debug - I2C2 SMBUS timeout is frozen.."
|
|
newline
|
|
bitfld.long 0x0 21. "I2C1,I2C1 SMBUS timeout stop in debug" "0: Normal operation - I2C1 SMBUS timeout continues..,1: Stop in debug - I2C1 SMBUS timeout is frozen.."
|
|
newline
|
|
bitfld.long 0x0 11. "WWDG,WWDG stop in debug" "0: Normal operation - WWDG continues to operate..,1: Stop in debug - WWDG is frozen while the.."
|
|
newline
|
|
bitfld.long 0x0 9. "LPTIM1,LPTIM1 stop in debug" "0: Normal operation - LPTIM1 continues operating..,1: Stop in debug - LPTIM1 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 8. "TIM14,TIM14 stop in debug" "0: Normal operation - TIM14 continues operating..,1: Stop in debug - TIM14 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 7. "TIM13,TIM13 stop in debug" "0: Normal operation - TIM13 continues operating..,1: Stop in debug - TIM13 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 6. "TIM12,TIM12 stop in debug" "0: Normal operation - TIM12 continues operatinge..,1: Stop in debug - TIM12 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 5. "TIM7,TIM7 stop in debug" "0: Normal operation - TIM7 continues operatinge..,1: Stop in debug - TIM7 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 4. "TIM6,TIM6 stop in debug" "0: Normal operation - TIM6 continues operating..,1: Stop in debug - TIM6 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIM5,TIM5 stop in debug" "0: Normal operation - TIM5 continues operating..,1: Stop in debug - TIM5 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 2. "TIM4,TIM4 stop in debug" "0: Normal operation - TIM4 continues operating..,1: Stop in debug - TIM4 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 1. "TIM3,TIM3 stop in debug" "0: Normal operation - TIM3 continues operating..,1: Stop in debug - TIM3 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 0. "TIM2,TIM2 stop in debug" "0: Normal operation - TIM2 continues operating..,1: Stop in debug - TIM2 is frozen while Cortex-M7.."
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DBGMCU_APB2FZ,DBGMCU APB2 peripheral freeze register"
|
|
bitfld.long 0x0 19. "TIM9,TIM9 stop in debug" "0: Normal operation - TIM9 continues operating..,1: Stop in debug - TIM9 is frozen and TIM9 outputs.."
|
|
newline
|
|
bitfld.long 0x0 18. "TIM17,TIM17 stop in debug" "0: Normal operation - TIM17 continues operating..,1: Stop in debug - TIM17 is frozen and TIM17.."
|
|
newline
|
|
bitfld.long 0x0 17. "TIM16,TIM16 stop in debug" "0: Normal operation - TIM16 continues operating..,1: Stop in debug - TIM16 is frozen and TIM16.."
|
|
newline
|
|
bitfld.long 0x0 16. "TIM15,TIM15 stop in debug" "0: Normal operation - TIM15 continues operating..,1: Stop in debug - TIM15 is frozen and TIM15.."
|
|
newline
|
|
bitfld.long 0x0 0. "TIM1,TIM1 stop in debug" "0: Normal operation - TIM1 continues operating..,1: Stop in debug - TIM1 is frozen and TIM1 outputs.."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DBGMCU_APB4FZR,DBGMCU APB4 peripheral freeze register"
|
|
bitfld.long 0x0 18. "IWDG,Independent watchdog for stop in debug" "0: Normal operation - watchdog continues counting..,1: Stop in debug - watchdog is frozen while.."
|
|
newline
|
|
bitfld.long 0x0 16. "RTC,RTC stop in debug" "0: Normal operation - RTC continues operating while..,1: Stop in debug - RTC is frozen while Cortex-M7 is.."
|
|
newline
|
|
bitfld.long 0x0 12. "LPTIM5,LPTIM5 stop in debug" "0: Normal operation - LPTIM5 continues operating..,1: Stop in debug - LPTIM5 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 11. "LPTIM4,LPTIM4 stop in debug" "0: Normal operation - LPTIM4 continues operating..,1: Stop in debug - LPTIM4 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 10. "LPTIM3,LPTIM2 stop in debug" "0: Normal operation - LPTIM2 continues operating..,1: Stop in debug - LPTIM2 is frozen while Cortex-M7.."
|
|
newline
|
|
bitfld.long 0x0 9. "LPTIM2,LPTIM2 stop in debug" "0: Normal operation - LPTIM2 continues operating..,1: Stop in debug - LPTIM2 is frozen while Cortex-M7.."
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "DBGMCU_SR,DBGMCU status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "AP_ENABLED,Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "AP_PRESENT,Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)"
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "DBGMCU_DBG_AUTH_HOST,DBGMCU debug authentication mailbox host register"
|
|
hexmask.long 0x0 0.--31. 1. "MESSAGE,Debug host to device mailbox message."
|
|
line.long 0x4 "DBGMCU_DBG_AUTH_DEVICE,DBGMCU debug authentication mailbox device register"
|
|
hexmask.long 0x4 0.--31. 1. "MESSAGE,Device to debug host mailbox message."
|
|
line.long 0x8 "DBGMCU_DBG_AUTH_ACK,DBGMCU debug authentication mailbox acknowledge register"
|
|
bitfld.long 0x8 1. "DEV_ACK,Device to device acknowledge. The host sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_HOST register. It is reset by the device after reading the message" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "HOST_ACK,Host to device acknowledge. The device sets this bit to indicate that it has placed a message in the DBGMCU_DBG_AUTH_DEVICE register. It should be reset by the host after reading the message" "0,1"
|
|
rgroup.long 0xFD0++0x3
|
|
line.long 0x0 "DBGMCU_PIDR4,DBGMCU peripheral identity register 4"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SIZE,Register file size"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "JEP106CON,JEP106 continuation code"
|
|
rgroup.long 0xFE0++0x1F
|
|
line.long 0x0 "DBGMCU_PIDR0,DBGMCU peripheral identity register 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PARTNUM,Part number field bits [7:0]"
|
|
line.long 0x4 "DBGMCU_PIDR1,DBGMCU peripheral identity register 1"
|
|
hexmask.long.byte 0x4 4.--7. 1. "JEP106ID,JEP106 identity code field bits [3:0]"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "PARTNUM,Part number field bits [11:8]"
|
|
line.long 0x8 "DBGMCU_PIDR2,DBGMCU peripheral identity register 2"
|
|
hexmask.long.byte 0x8 4.--7. 1. "REVISION,Component revision number"
|
|
newline
|
|
bitfld.long 0x8 3. "JEDEC,JEDEC assigned value" "?,1: Designer ID specified by JEDEC"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "JEP106ID,JEP106 identity code field bits [6:4]" "?,?,2: STMicroelectronics JEDEC code,?,?,?,?,?"
|
|
line.long 0xC "DBGMCU_PIDR3,DBGMCU peripheral identity register 3"
|
|
hexmask.long.byte 0xC 4.--7. 1. "REVAND,Metal fix version"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "CMOD,Customer modified"
|
|
line.long 0x10 "DBGMCU_CIDR0,DBGMCU component identity register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PREAMBLE,Component ID field bits [7:0]"
|
|
line.long 0x14 "DBGMCU_CIDR1,DBGMCU component identity register"
|
|
hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component ID field bits [15:12] - component class"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "PREAMBLE,Component ID field bits [11:8]"
|
|
line.long 0x18 "DBGMCU_CIDR2,DBGMCU component identity register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PREAMBLE,Component ID field bits [23:16]"
|
|
line.long 0x1C "DBGMCU_CIDR3,DBGMCU component identity register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PREAMBLE,Component ID field bits [31:24]"
|
|
tree.end
|
|
tree "DCMIPP (Digital Camera Interface Pixel Pipeline)"
|
|
base ad:0x50002000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DCMIPP_IPGR1,DCMIPP IP-Plug global register 1"
|
|
bitfld.long 0x0 24. "QOS_MODE,Quality of service" "0,1"
|
|
bitfld.long 0x0 0.--2. "MEMORYPAGE,Memory page size as power of 2 of 64-byte units:" "0: 64 bytes,1: 128 bytes,?,?,?,?,?,?"
|
|
line.long 0x4 "DCMIPP_IPGR2,DCMIPP IP-Plug global register 2"
|
|
bitfld.long 0x4 0. "PSTART,Request to lock the IP-Plug to allow reconfiguration." "0: No lock requested IP-Plug runs on demand by..,1: Lock requested: IP-Plug freezes shortly (see.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DCMIPP_IPGR3,DCMIPP IP-Plug global register 3"
|
|
bitfld.long 0x0 0. "IDLE,Status of IP-Plug" "0: IP-Plug is running (on demand by background HW),1: IP-Plug is currently locked and can be.."
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "DCMIPP_IPGR8,DCMIPP IP-Plug identification register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IPPID,IP identifier (0xAA)"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ARCHIID,Architecture identifier (0x04)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REVID,Revision identifier (0x03)"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DID,Division identifier (0x14)"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "DCMIPP_IPC1R1,DCMIPP IP-Plug Clientx register 1"
|
|
bitfld.long 0x0 8.--9. "OTR,Maximum outstanding transactions" "0: Disabled. No outstanding transaction limitation..,1: Maximum two outstanding transactions ongoing.,?,?"
|
|
bitfld.long 0x0 0.--2. "TRAFFIC,Burst size as power of 2 of 8-byte units" "0: 8 bytes,1: 16 bytes,?,?,?,?,?,?"
|
|
line.long 0x4 "DCMIPP_IPC1R2,DCMIPP IP-Plug Clientx register 2"
|
|
hexmask.long.byte 0x4 16.--19. 1. "WLRU,Ratio for WLRU[3:0] arbitration"
|
|
hexmask.long.byte 0x4 8.--11. 1. "SVCMAPPING,Non-user must be kept at reset value."
|
|
line.long 0x8 "DCMIPP_IPC1R3,DCMIPP IP-Plug Clientx register 3"
|
|
hexmask.long.byte 0x8 16.--20. 1. "DPREGEND,End word (AXI width = 64 bits) of the FIFO of Clientx."
|
|
hexmask.long.byte 0x8 0.--4. 1. "DPREGSTART,Start word (AXI width = 64 bits) of the FIFO of Clientx."
|
|
group.long 0x104++0xB
|
|
line.long 0x0 "DCMIPP_PRCR,DCMIPP parallel interface control register"
|
|
bitfld.long 0x0 26. "SWAPBITS,Swap LSB vs. MSB within each received component" "0: As received,1: Swapped MSB vs. LSB"
|
|
bitfld.long 0x0 25. "SWAPCYCLES,Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles" "0: Default,1: Swap active: the data of cycle 1 is used before.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "FORMAT,Other values: data are captured and output as-is only through the data/dump pipeline (for example JPEG or byte input format)."
|
|
bitfld.long 0x0 14. "ENABLE,Parallel interface enable" "0: Parallel interface disabled to lower power..,1: Parallel interface enabled"
|
|
newline
|
|
bitfld.long 0x0 10.--12. "EDM,Extended data mode" "0: Interface captures 8-bit data on every pixel clock,1: Interface captures 10-bit data on every pixel..,2: Interface captures 12-bit data on every pixel..,3: Interface captures 14-bit data on every pixel..,4: Interface captures 16-bit data on every pixel..,?,?,?"
|
|
bitfld.long 0x0 7. "VSPOL,Vertical synchronization polarity" "0: VSYNC active low,1: VSYNC active high"
|
|
newline
|
|
bitfld.long 0x0 6. "HSPOL,Horizontal synchronization polarity" "0: HSYNC active low,1: HSYNC active high"
|
|
bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0: Falling edge active,1: Rising edge active"
|
|
newline
|
|
bitfld.long 0x0 4. "ESS,Embedded synchronization select" "0: Hardware synchronization data capture..,1: Embedded synchronization data capture is.."
|
|
line.long 0x4 "DCMIPP_PRESCR,DCMIPP parallel interface embedded synchronization code register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FEC,Frame end delimiter code"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LEC,Line end delimiter code"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "LSC,Line start delimiter code"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FSC,Frame start delimiter code"
|
|
line.long 0x8 "DCMIPP_PRESUR,DCMIPP parallel interface embedded synchronization unmask register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "FEU,Frame end delimiter unmask"
|
|
hexmask.long.byte 0x8 16.--23. 1. "LEU,Line end delimiter unmask"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "LSU,Line start delimiter unmask"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FSU,Frame start delimiter unmask"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x0 "DCMIPP_PRIER,DCMIPP parallel interface interrupt enable register"
|
|
bitfld.long 0x0 6. "ERRIE,Synchronization error interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the embedded.."
|
|
rgroup.long 0x1F8++0x3
|
|
line.long 0x0 "DCMIPP_PRSR,DCMIPP parallel interface status register"
|
|
bitfld.long 0x0 17. "VSYNC,This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit .." "0: Active frame,1: Synchronization between frames"
|
|
bitfld.long 0x0 16. "HSYNC,This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit .." "0: Active line,1: Synchronization between lines"
|
|
newline
|
|
bitfld.long 0x0 6. "ERRF,Synchronization error raw interrupt status" "0: No synchronization error detected,1: Embedded synchronization characters are not.."
|
|
wgroup.long 0x1FC++0x3
|
|
line.long 0x0 "DCMIPP_PRFCR,DCMIPP parallel interface interrupt clear register"
|
|
bitfld.long 0x0 6. "CERRF,Synchronization error interrupt status clear" "0,1"
|
|
wgroup.long 0x204++0x3
|
|
line.long 0x0 "DCMIPP_CMCR,DCMIPP common configuration register"
|
|
bitfld.long 0x0 4. "CFC,Clear frame counter" "0,1"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "DCMIPP_CMFRCR,DCMIPP common frame counter register"
|
|
hexmask.long 0x0 0.--31. 1. "FRMCNT,Frame counter read-only loops around."
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "DCMIPP_CMIER,DCMIPP common interrupt enable register"
|
|
bitfld.long 0x0 15. "P0OVRIE,Overrun interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated"
|
|
bitfld.long 0x0 14. "P0LIMITIE,Limit interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated"
|
|
newline
|
|
bitfld.long 0x0 10. "P0VSYNCIE,Vertical sync interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated"
|
|
bitfld.long 0x0 9. "P0FRAMEIE,Frame capture complete interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated"
|
|
newline
|
|
bitfld.long 0x0 8. "P0LINEIE,Multi-line capture complete interrupt enable for Pipe0" "0: No interrupt generation,1: An interrupt is generated"
|
|
bitfld.long 0x0 6. "PRERRIE,Limit interrupt enable for the parallel Interface" "0: No interrupt generation,1: An interrupt is generated"
|
|
newline
|
|
bitfld.long 0x0 5. "ATXERRIE,AXI transfer error interrupt enable for IP-Plug" "0: No interrupt generation,1: An interrupt is generated"
|
|
rgroup.long 0x3F4++0x7
|
|
line.long 0x0 "DCMIPP_CMSR1,DCMIPP common status register 1"
|
|
bitfld.long 0x0 15. "P0CPTACT,Active frame capture (active from start-of-frame to frame complete) for Pipe0" "0: No capture currently active,1: Capture currently active"
|
|
bitfld.long 0x0 1. "PRVSYNC,This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the.." "0: Active frame,1: Synchronization between frames"
|
|
newline
|
|
bitfld.long 0x0 0. "PRHSYNC,This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the.." "0: Active line,1: Synchronization between lines"
|
|
line.long 0x4 "DCMIPP_CMSR2,DCMIPP common status register 2"
|
|
bitfld.long 0x4 15. "P0OVRF,Overrun raw interrupt status for Pipe0" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.."
|
|
bitfld.long 0x4 14. "P0LIMITF,Limit raw interrupt status for Pipe0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "P0VSYNCF,VSYNC raw interrupt status for Pipe0" "0,1"
|
|
bitfld.long 0x4 9. "P0FRAMEF,Frame capture completed raw interrupt status for Pipe0" "0: No capture or ongoing capture,1: All data of a frame have been captured"
|
|
newline
|
|
bitfld.long 0x4 8. "P0LINEF,Multi-line capture completed raw interrupt status for Pipe0" "0,1"
|
|
bitfld.long 0x4 6. "PRERRF,Synchronization error raw interrupt status for the parallel interface." "0: No synchronization error detected,1: Embedded synchronization characters are not.."
|
|
newline
|
|
bitfld.long 0x4 5. "ATXERRF,AXI transfer error interrupt status flag for the IP-Plug." "0: No AXI transfer error detected,1: AXI transfer error occurred on an AXI client."
|
|
wgroup.long 0x3FC++0x3
|
|
line.long 0x0 "DCMIPP_CMFCR,DCMIPP common interrupt clear register"
|
|
bitfld.long 0x0 15. "CP0OVRF,Overrun interrupt status clear" "0,1"
|
|
bitfld.long 0x0 14. "CP0LIMITF,limit interrupt status clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CP0VSYNCF,Vertical synchronization interrupt status clear" "0,1"
|
|
bitfld.long 0x0 9. "CP0FRAMEF,Frame capture complete interrupt status clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CP0LINEF,Multi-line capture complete interrupt status clear" "0,1"
|
|
bitfld.long 0x0 6. "CPRERRF,Synchronization error interrupt status clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CATXERRF,AXI transfer error interrupt status clear" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "DCMIPP_P0FSCR,DCMIPP Pipe0 flow selection configuration register"
|
|
bitfld.long 0x0 31. "PIPEN,Activation of PipeN" "0: Pipe disabled,1: Pipe enabled can start capturing with CPTMODE.."
|
|
group.long 0x500++0xB
|
|
line.long 0x0 "DCMIPP_P0FCTCR,DCMIPP Pipe0 flow control configuration register"
|
|
bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame,1: Capture requested for next frame"
|
|
bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.."
|
|
line.long 0x4 "DCMIPP_P0SCSTR,DCMIPP Pipe0 stat/crop start register"
|
|
hexmask.long.word 0x4 16.--27. 1. "VSTART,Vertical start from 0 to 4094 pixels high"
|
|
hexmask.long.word 0x4 0.--11. 1. "HSTART,Horizontal start from 0 to 4094 words wide"
|
|
line.long 0x8 "DCMIPP_P0SCSZR,DCMIPP Pipe0 stat/crop size register"
|
|
bitfld.long 0x8 31. "ENABLE,This bit is set and cleared by software." "0: Bypass. All the data are computed if the..,1: Enable. Depending on bit POSNEG value the.."
|
|
bitfld.long 0x8 30. "POSNEG,This bit is set and cleared by software. It has a meaning only if ENABLE bit is set." "0: Positive area the rectangle defined by VSIZE..,1: Negative area the area excluding the rectangle.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--27. 1. "VSIZE,Vertical size from 0 to 4094 pixels high"
|
|
hexmask.long.word 0x8 0.--11. 1. "HSIZE,Horizontal size from 0 to 4094 word wide (data 32-bit)"
|
|
rgroup.long 0x5B0++0x3
|
|
line.long 0x0 "DCMIPP_P0DCCNTR,DCMIPP Pipe0 dump counter register"
|
|
hexmask.long 0x0 0.--25. 1. "CNT,Number of data dumped during the frame."
|
|
group.long 0x5B4++0x3
|
|
line.long 0x0 "DCMIPP_P0DCLMTR,DCMIPP Pipe0 dump limit register"
|
|
bitfld.long 0x0 31. "ENABLE," "0: Disabled no check on the amount of 32-bit words..,1: Enabled check done versus limit"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "LIMIT,Maximum number of 32-bit data that can be dumped during a frame after the crop 2D operation."
|
|
group.long 0x5C0++0xB
|
|
line.long 0x0 "DCMIPP_P0PPCR,DCMIPP Pipe0 pixel packer configuration register"
|
|
bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe0 always..,1: Double buffer mode activated. Dump address.."
|
|
bitfld.long 0x0 13.--15. "LINEMULT,Amount of capture completed lines for LINE event and interrupt" "0: Event after one line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines"
|
|
newline
|
|
bitfld.long 0x0 11. "OELS,Odd/even line select (line select start)" "0: Interface captures first line after the frame..,1: Interface captures second line from the frame.."
|
|
bitfld.long 0x0 10. "LSM,Line select mode" "0: Interface captures all received lines,1: Interface captures one line out of two"
|
|
newline
|
|
bitfld.long 0x0 9. "OEBS,Odd/even byte select (byte select start)" "0: Interface captures the first data (byte or..,1: Interface captures the second data (byte or.."
|
|
bitfld.long 0x0 7.--8. "BSM,Byte select mode" "0: Interface captures all received data,1: Interface captures 1 data out of 2,2: Interface captures one byte out of four,3: Interface captures two bytes out of four"
|
|
newline
|
|
bitfld.long 0x0 5. "PAD,Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment." "0: Aligns on LSB (and pads null bits on MSB) for..,1: Aligns on MSB (and pads null bits on LSB) for.."
|
|
line.long 0x4 "DCMIPP_P0PPM0AR1,DCMIPP Pipe0 pixel packer Memory0 address register 1"
|
|
hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address"
|
|
line.long 0x8 "DCMIPP_P0PPM0AR2,DCMIPP Pipe0 pixel packer Memory0 address register 2"
|
|
hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address"
|
|
group.long 0x5F4++0x3
|
|
line.long 0x0 "DCMIPP_P0IER,DCMIPP Pipe0 interrupt enable register"
|
|
bitfld.long 0x0 7. "OVRIE,Overrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if the AXI master is.."
|
|
bitfld.long 0x0 6. "LIMITIE,Limit interrupt enable" "0: No interrupt generation when the limit is reached,1: An interrupt is generated when the limit is.."
|
|
newline
|
|
bitfld.long 0x0 2. "VSYNCIE,VSYNC interrupt enable" "0: No interrupt generation,1: An interrupt is generated on each VSYNC.."
|
|
bitfld.long 0x0 1. "FRAMEIE,Frame capture completed interrupt enable" "0: No interrupt generation,1: An interrupt is generated after the full capture.."
|
|
newline
|
|
bitfld.long 0x0 0. "LINEIE,Multi-line capture completed interrupt enable" "0: No interrupt generation when the line is received,1: An interrupt is generated after the full capture.."
|
|
rgroup.long 0x5F8++0x3
|
|
line.long 0x0 "DCMIPP_P0SR,DCMIPP Pipe0 status register"
|
|
bitfld.long 0x0 23. "CPTACT,Capture immediate status" "0: Capture currently inactive,1: Capture currently active"
|
|
bitfld.long 0x0 7. "OVRF,Overrun raw interrupt status" "0: No data buffer overrun occurred,1: A data buffer overrun occurred and this frame.."
|
|
newline
|
|
bitfld.long 0x0 6. "LIMITF,Limit raw interrupt status" "0,1"
|
|
bitfld.long 0x0 2. "VSYNCF,VSYNC raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FRAMEF,Frame capture completed raw interrupt status" "0: No capture or ongoing capture,1: All data of a frame have been captured"
|
|
bitfld.long 0x0 0. "LINEF,Multi-line capture completed raw interrupt status" "0,1"
|
|
wgroup.long 0x5FC++0x3
|
|
line.long 0x0 "DCMIPP_P0FCR,DCMIPP Pipe0 interrupt clear register"
|
|
bitfld.long 0x0 7. "COVRF,Overrun interrupt status clear" "0,1"
|
|
bitfld.long 0x0 6. "CLIMITF,limit interrupt status clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CVSYNCF,Vertical synchronization interrupt status clear" "0,1"
|
|
bitfld.long 0x0 1. "CFRAMEF,Frame capture complete interrupt status clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLINEF,Multi-line capture complete interrupt status clear" "0,1"
|
|
rgroup.long 0x700++0xB
|
|
line.long 0x0 "DCMIPP_P0CFCTCR,DCMIPP Pipe0 current flow control configuration register"
|
|
bitfld.long 0x0 3. "CPTREQ,Capture requested" "0: Capture not requested for next frame.,1: Capture requested for next frame."
|
|
bitfld.long 0x0 2. "CPTMODE,Capture mode" "0: Continuous grab mode - The received data are..,1: Snapshot mode (single frame) - Once activated.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FRATE,Frame capture rate control" "0: All frames are captured,1: One out of two frames captured (50% bandwidth..,2: One out of four frames captured (75% bandwidth..,3: One out of eight frames captured (87% bandwidth.."
|
|
line.long 0x4 "DCMIPP_P0CSCSTR,DCMIPP Pipe0 current stat/crop start register"
|
|
hexmask.long.word 0x4 16.--27. 1. "VSTART,Current vertical start from 0 to 4094 pixels high"
|
|
hexmask.long.word 0x4 0.--11. 1. "HSTART,Current horizontal start from 0 to 4094 words wide"
|
|
line.long 0x8 "DCMIPP_P0CSCSZR,DCMIPP Pipe0 current stat/crop size register"
|
|
bitfld.long 0x8 31. "ENABLE,Current value of the ENABLE bit" "0: Bypass. All data are computed if the statistics..,1: Enable: Depending on bit POSNEG value the.."
|
|
bitfld.long 0x8 30. "POSNEG,Current value of the POSNEG bit" "0: Positive area. The rectangle defined by VSIZE..,1: Negative area. The active area is the area.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--27. 1. "VSIZE,Current vertical size from 0 to 4094 pixels high."
|
|
hexmask.long.word 0x8 0.--11. 1. "HSIZE,Current horizontal size from 0 to 4094 word wide (data 32-bit)."
|
|
rgroup.long 0x7C0++0xB
|
|
line.long 0x0 "DCMIPP_P0CPPCR,DCMIPP Pipe0 current pixel packer configuration register"
|
|
bitfld.long 0x0 16. "DBM,Double buffer mode" "0: No double buffer mode activated. Pipe0 is always..,1: Double buffer mode activated. Dump address.."
|
|
bitfld.long 0x0 13.--15. "LINEMULT,Current amount of capture completed lines for LINE event and interrupt" "0: Event after every line,1: Event after two lines,2: Event after four lines,3: Event after eight lines,4: Event after sixteen lines,5: Event after 32 lines,6: Event after 64 lines,7: Event after 128 lines"
|
|
newline
|
|
bitfld.long 0x0 11. "OELS,Current odd/even line select (ine select start)" "0: Interface captures the first line after the..,1: Interface captures the second line from the.."
|
|
bitfld.long 0x0 10. "LSM,Current Line select mode" "0: Interface captures all received lines,1: Interface captures one line out of two"
|
|
newline
|
|
bitfld.long 0x0 9. "OEBS,Current odd/even byte select (byte select start)" "0: Interface captures the first data (byte or..,1: Interface captures the second data (byte or.."
|
|
bitfld.long 0x0 7.--8. "BSM,Current Byte select mode" "0: Interface captures all received data,1: Interface captures one data out of two,2: Interface captures one byte out of four,3: Interface captures two bytes out of four"
|
|
newline
|
|
bitfld.long 0x0 5. "PAD,Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment" "0: Aligns on LSB (and pads null bits on MSB) for..,1: Aligns on MSB (and pads null bits on LSB) for.."
|
|
line.long 0x4 "DCMIPP_P0CPPM0AR1,DCMIPP Pipe0 current pixel packer Memory0 address register 1"
|
|
hexmask.long 0x4 0.--31. 1. "M0A,Memory0 address"
|
|
line.long 0x8 "DCMIPP_P0CPPM0AR2,DCMIPP Pipe0 current pixel packer Memory0 address register 2"
|
|
hexmask.long 0x8 0.--31. 1. "M0A,Memory0 address"
|
|
tree.end
|
|
tree "DLYB (Delay Block)"
|
|
base ad:0x0
|
|
tree "DLYB1"
|
|
base ad:0x52008000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DLYB_CR,DLYB control register"
|
|
bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0: Sampler length and register access to UNIT[6:0]..,1: Sampler length and register access to UNIT[6:0].."
|
|
bitfld.long 0x0 0. "DEN,Delay block enable bit" "0: DLYB disabled.,1: DLYB enabled."
|
|
line.long 0x4 "DLYB_CFGR,DLYB configuration register"
|
|
rbitfld.long 0x4 31. "LNGF,Length valid flag" "0: Length value in LNG is not valid.,1: Length value in LNG is valid."
|
|
hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value"
|
|
hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay of a unit delay cell."
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL,Phase for the output clock."
|
|
tree.end
|
|
tree "DLYB2"
|
|
base ad:0x48002800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DLYB_CR,DLYB control register"
|
|
bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0: Sampler length and register access to UNIT[6:0]..,1: Sampler length and register access to UNIT[6:0].."
|
|
bitfld.long 0x0 0. "DEN,Delay block enable bit" "0: DLYB disabled.,1: DLYB enabled."
|
|
line.long 0x4 "DLYB_CFGR,DLYB configuration register"
|
|
rbitfld.long 0x4 31. "LNGF,Length valid flag" "0: Length value in LNG is not valid.,1: Length value in LNG is valid."
|
|
hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value"
|
|
hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay of a unit delay cell."
|
|
hexmask.long.byte 0x4 0.--3. 1. "SEL,Phase for the output clock."
|
|
tree.end
|
|
tree.end
|
|
tree "DMA2D (Chrom-ART Accelerator Controller)"
|
|
base ad:0x52001000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DMA2D_CR,DMA2D control register"
|
|
bitfld.long 0x0 16.--18. "MODE,DMA2D mode" "0: Memory-to-memory (FG fetch only),1: Memory-to-memory with PFC (FG fetch only with FG..,2: Memory-to-memory with blending (FG and BG fetch..,3: Register-to-memory (no FG nor BG only output..,4: Memory-to-memory with blending and fixed color..,5: Memory-to-memory with blending and fixed color..,?,?"
|
|
bitfld.long 0x0 13. "CEIE,Configuration error (CE) interrupt enable" "0: CE interrupt disabled,1: CE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "CTCIE,CLUT transfer complete (CTC) interrupt enable" "0: CTC interrupt disabled,1: CTC interrupt enabled"
|
|
bitfld.long 0x0 11. "CAEIE,CLUT access error (CAE) interrupt enable" "0: CAE interrupt disabled,1: CAE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 10. "TWIE,Transfer watermark (TW) interrupt enable" "0: TW interrupt disabled,1: TW interrupt enabled"
|
|
bitfld.long 0x0 9. "TCIE,Transfer complete (TC) interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "TEIE,Transfer error (TE) interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
|
|
bitfld.long 0x0 6. "LOM,Line offset mode" "0: Line offsets expressed in pixels,1: Line offsets expressed in bytes"
|
|
newline
|
|
bitfld.long 0x0 2. "ABORT,Abort" "0: No transfer abort requested,1: Transfer abort requested"
|
|
bitfld.long 0x0 1. "SUSP,Suspend" "0: Transfer not suspended,1: Transfer suspended"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA2D_ISR,DMA2D interrupt status register"
|
|
bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag" "0,1"
|
|
group.long 0x8++0x33
|
|
line.long 0x0 "DMA2D_IFCR,DMA2D interrupt flag clear register"
|
|
bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1"
|
|
bitfld.long 0x0 0. "CTEIF,Clear transfer error interrupt flag" "0,1"
|
|
line.long 0x4 "DMA2D_FGMAR,DMA2D foreground memory address register"
|
|
hexmask.long 0x4 0.--31. 1. "MA,Memory address address of the data used for the foreground image"
|
|
line.long 0x8 "DMA2D_FGOR,DMA2D foreground offset register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LO,Line offset"
|
|
line.long 0xC "DMA2D_BGMAR,DMA2D background memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Memory address address of the data used for the background image"
|
|
line.long 0x10 "DMA2D_BGOR,DMA2D background offset register"
|
|
hexmask.long.word 0x10 0.--15. 1. "LO,Line offset"
|
|
line.long 0x14 "DMA2D_FGPFCCR,DMA2D foreground PFC control register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value"
|
|
bitfld.long 0x14 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)"
|
|
newline
|
|
bitfld.long 0x14 20. "AI,Alpha inverted" "0: Regular alpha,1: Inverted alpha"
|
|
bitfld.long 0x14 18.--19. "CSS,Chroma subsampling" "0: 4:4:4 (no chroma subsampling),1: 4:2:2,2: 4:2:0,?"
|
|
newline
|
|
bitfld.long 0x14 16.--17. "AM,Alpha mode" "0: No modification of the foreground image alpha..,1: Replace original foreground image alpha channel..,2: Replace original foreground image alpha channel..,?"
|
|
hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size"
|
|
newline
|
|
bitfld.long 0x14 5. "START,Start" "0,1"
|
|
bitfld.long 0x14 4. "CCM,CLUT color mode" "0: ARGB8888,1: RGB888"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode"
|
|
line.long 0x18 "DMA2D_FGCOLR,DMA2D foreground color register"
|
|
hexmask.long.byte 0x18 16.--23. 1. "RED,Red value for the A4 or A8 mode of the foreground image"
|
|
hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green value for the A4 or A8 mode of the foreground image"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue value for the A4 or A8 mode of the foreground image"
|
|
line.long 0x1C "DMA2D_BGPFCCR,DMA2D background PFC control register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value"
|
|
bitfld.long 0x1C 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)"
|
|
newline
|
|
bitfld.long 0x1C 20. "AI,Alpha Inverted" "0: Regular alpha,1: Inverted alpha"
|
|
bitfld.long 0x1C 16.--17. "AM,Alpha mode" "0: No modification of the foreground image alpha..,1: Replace original background image alpha channel..,2: Replace original background image alpha channel..,?"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size"
|
|
bitfld.long 0x1C 5. "START,Start" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "CCM,CLUT color mode" "0: ARGB8888,1: RGB888"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode"
|
|
line.long 0x20 "DMA2D_BGCOLR,DMA2D background color register"
|
|
hexmask.long.byte 0x20 16.--23. 1. "RED,Red value for the A4 or A8 mode of the background"
|
|
hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green value for the A4 or A8 mode of the background"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue value for the A4 or A8 mode of the background"
|
|
line.long 0x24 "DMA2D_FGCMAR,DMA2D foreground CLUT memory address register"
|
|
hexmask.long 0x24 0.--31. 1. "MA,Memory address"
|
|
line.long 0x28 "DMA2D_BGCMAR,DMA2D background CLUT memory address register"
|
|
hexmask.long 0x28 0.--31. 1. "MA,Memory address"
|
|
line.long 0x2C "DMA2D_OPFCCR,DMA2D output PFC control register"
|
|
bitfld.long 0x2C 21. "RBS,Red/Blue swap" "0: Regular mode (RGB or ARGB),1: Swap mode (BGR or ABGR)"
|
|
bitfld.long 0x2C 20. "AI,Alpha Inverted" "0: Regular alpha,1: Inverted alpha"
|
|
newline
|
|
bitfld.long 0x2C 8. "SB,Swap bytes" "0: Bytes in regular order in the output FIFO,1: Bytes swapped two by two in the output FIFO"
|
|
bitfld.long 0x2C 0.--2. "CM,Color mode" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,?,?,?"
|
|
line.long 0x30 "DMA2D_OCOLR_ARGB8888,DMA2D output color register"
|
|
hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha channel value of the output color in ARGB8888 mode (otherwise reserved)"
|
|
hexmask.long.byte 0x30 16.--23. 1. "RED,Red value of the output image in ARGB8888 or RGB888 mode"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green value of the output image in ARGB8888 or RGB888"
|
|
hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue value of the output image in ARGB8888 or RGB888"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DMA2D_OCOLR_RGB565,DMA2D output color register"
|
|
hexmask.long.byte 0x0 11.--15. 1. "RED,Red value of the output image in RGB565 mode"
|
|
hexmask.long.byte 0x0 5.--10. 1. "GREEN,Green value of the output image in RGB565 mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value of the output image in RGB565 mode"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DMA2D_OCOLR_ARGB1555,DMA2D output color register"
|
|
bitfld.long 0x0 15. "A,Alpha channel value of the output color in ARGB1555 mode" "0,1"
|
|
hexmask.long.byte 0x0 10.--14. 1. "RED,Red value of the output image in ARGB1555 mode"
|
|
newline
|
|
hexmask.long.byte 0x0 5.--9. 1. "GREEN,Green value of the output image in ARGB1555 mode"
|
|
hexmask.long.byte 0x0 0.--4. 1. "BLUE,Blue value of the output image in ARGB1555 mode"
|
|
group.long 0x38++0x17
|
|
line.long 0x0 "DMA2D_OCOLR_ARGB4444,DMA2D output color register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "ALPHA,Alpha channel of the output color value in ARGB4444"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RED,Red value of the output image in ARGB4444 mode"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "GREEN,Green value of the output image in ARGB4444 mode"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLUE,Blue value of the output image in ARGB4444 mode"
|
|
line.long 0x4 "DMA2D_OMAR,DMA2D output memory address register"
|
|
hexmask.long 0x4 0.--31. 1. "MA,Memory address"
|
|
line.long 0x8 "DMA2D_OOR,DMA2D output offset register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LO,Line offset"
|
|
line.long 0xC "DMA2D_NLR,DMA2D number of line register"
|
|
hexmask.long.word 0xC 16.--29. 1. "PL,Pixel per lines per lines of the area to be transferred"
|
|
hexmask.long.word 0xC 0.--15. 1. "NL,Number of lines of the area to be transferred."
|
|
line.long 0x10 "DMA2D_LWR,DMA2D line watermark register"
|
|
hexmask.long.word 0x10 0.--15. 1. "LW,Line watermark for interrupt generation"
|
|
line.long 0x14 "DMA2D_AMTCR,DMA2D AXI master timer configuration register"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DT,Dead time"
|
|
bitfld.long 0x14 0. "EN,Dead-time functionality enable" "0,1"
|
|
group.long 0x400++0x7FF
|
|
line.long 0x0 "DMA2D_FGCLUT0,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4 "DMA2D_FGCLUT1,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x8 "DMA2D_FGCLUT2,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xC "DMA2D_FGCLUT3,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x10 "DMA2D_FGCLUT4,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x10 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x10 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x10 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x14 "DMA2D_FGCLUT5,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x14 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x14 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x18 "DMA2D_FGCLUT6,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x18 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x18 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1C "DMA2D_FGCLUT7,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x20 "DMA2D_FGCLUT8,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x20 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x20 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x24 "DMA2D_FGCLUT9,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x24 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x24 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x24 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x28 "DMA2D_FGCLUT10,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x28 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x28 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2C "DMA2D_FGCLUT11,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x30 "DMA2D_FGCLUT12,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x30 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x34 "DMA2D_FGCLUT13,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x34 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x34 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x34 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x38 "DMA2D_FGCLUT14,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x38 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x38 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x38 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3C "DMA2D_FGCLUT15,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x40 "DMA2D_FGCLUT16,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x40 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x40 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x40 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x40 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x44 "DMA2D_FGCLUT17,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x44 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x44 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x44 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x48 "DMA2D_FGCLUT18,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x48 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x48 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x48 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x48 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4C "DMA2D_FGCLUT19,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x4C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x50 "DMA2D_FGCLUT20,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x50 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x50 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x50 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x50 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x54 "DMA2D_FGCLUT21,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x54 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x54 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x54 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x54 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x58 "DMA2D_FGCLUT22,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x58 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x58 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x58 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x58 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5C "DMA2D_FGCLUT23,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x5C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x60 "DMA2D_FGCLUT24,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x60 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x60 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x60 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x60 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x64 "DMA2D_FGCLUT25,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x64 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x64 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x64 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x64 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x68 "DMA2D_FGCLUT26,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x68 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x68 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x68 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x68 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6C "DMA2D_FGCLUT27,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x6C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x70 "DMA2D_FGCLUT28,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x70 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x70 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x70 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x70 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x74 "DMA2D_FGCLUT29,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x74 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x74 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x74 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x78 "DMA2D_FGCLUT30,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x78 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x78 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x78 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x78 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7C "DMA2D_FGCLUT31,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x7C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x80 "DMA2D_FGCLUT32,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x80 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x80 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x80 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x80 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x84 "DMA2D_FGCLUT33,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x84 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x84 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x84 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x88 "DMA2D_FGCLUT34,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x88 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x88 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x88 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x88 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x8C "DMA2D_FGCLUT35,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x8C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x90 "DMA2D_FGCLUT36,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x90 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x90 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x90 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x90 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x94 "DMA2D_FGCLUT37,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x94 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x94 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x94 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x98 "DMA2D_FGCLUT38,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x98 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x98 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x98 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x98 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x9C "DMA2D_FGCLUT39,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x9C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xA0 "DMA2D_FGCLUT40,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xA0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xA0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xA4 "DMA2D_FGCLUT41,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xA4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xA8 "DMA2D_FGCLUT42,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xA8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xA8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xAC "DMA2D_FGCLUT43,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xAC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xB0 "DMA2D_FGCLUT44,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xB0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xB0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xB4 "DMA2D_FGCLUT45,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xB4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xB4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xB8 "DMA2D_FGCLUT46,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xB8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xB8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xB8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xBC "DMA2D_FGCLUT47,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xBC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xBC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xC0 "DMA2D_FGCLUT48,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xC0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xC0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xC0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xC4 "DMA2D_FGCLUT49,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xC4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xC4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xC8 "DMA2D_FGCLUT50,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xC8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xC8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xC8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xCC "DMA2D_FGCLUT51,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xCC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xCC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xD0 "DMA2D_FGCLUT52,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xD0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xD0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xD0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xD4 "DMA2D_FGCLUT53,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xD4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xD4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xD4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xD8 "DMA2D_FGCLUT54,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xD8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xD8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xD8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xDC "DMA2D_FGCLUT55,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xDC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xDC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xDC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xE0 "DMA2D_FGCLUT56,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xE0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xE0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xE0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xE0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xE4 "DMA2D_FGCLUT57,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xE4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xE4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xE4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xE4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xE8 "DMA2D_FGCLUT58,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xE8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xE8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xE8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xE8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xEC "DMA2D_FGCLUT59,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xEC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xEC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xEC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xEC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xF0 "DMA2D_FGCLUT60,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xF0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xF0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xF0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xF0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xF4 "DMA2D_FGCLUT61,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xF4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xF4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xF4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xF4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xF8 "DMA2D_FGCLUT62,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xF8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xF8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xF8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xF8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0xFC "DMA2D_FGCLUT63,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0xFC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0xFC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0xFC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0xFC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x100 "DMA2D_FGCLUT64,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x100 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x100 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x100 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x100 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x104 "DMA2D_FGCLUT65,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x104 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x104 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x104 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x104 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x108 "DMA2D_FGCLUT66,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x108 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x108 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x108 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x108 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x10C "DMA2D_FGCLUT67,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x10C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x10C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x10C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x10C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x110 "DMA2D_FGCLUT68,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x110 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x110 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x110 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x110 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x114 "DMA2D_FGCLUT69,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x114 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x114 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x114 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x114 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x118 "DMA2D_FGCLUT70,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x118 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x118 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x118 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x118 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x11C "DMA2D_FGCLUT71,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x11C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x11C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x11C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x11C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x120 "DMA2D_FGCLUT72,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x120 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x120 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x120 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x120 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x124 "DMA2D_FGCLUT73,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x124 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x124 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x124 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x124 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x128 "DMA2D_FGCLUT74,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x128 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x128 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x128 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x128 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x12C "DMA2D_FGCLUT75,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x12C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x12C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x12C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x12C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x130 "DMA2D_FGCLUT76,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x130 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x130 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x130 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x130 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x134 "DMA2D_FGCLUT77,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x134 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x134 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x134 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x134 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x138 "DMA2D_FGCLUT78,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x138 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x138 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x138 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x138 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x13C "DMA2D_FGCLUT79,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x13C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x13C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x13C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x13C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x140 "DMA2D_FGCLUT80,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x140 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x140 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x140 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x140 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x144 "DMA2D_FGCLUT81,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x144 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x144 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x144 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x144 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x148 "DMA2D_FGCLUT82,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x148 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x148 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x148 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x148 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x14C "DMA2D_FGCLUT83,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x14C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x14C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x14C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x14C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x150 "DMA2D_FGCLUT84,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x150 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x150 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x150 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x150 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x154 "DMA2D_FGCLUT85,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x154 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x154 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x154 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x154 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x158 "DMA2D_FGCLUT86,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x158 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x158 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x158 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x158 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x15C "DMA2D_FGCLUT87,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x15C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x15C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x15C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x15C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x160 "DMA2D_FGCLUT88,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x160 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x160 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x160 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x160 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x164 "DMA2D_FGCLUT89,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x164 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x164 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x164 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x164 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x168 "DMA2D_FGCLUT90,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x168 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x168 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x168 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x168 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x16C "DMA2D_FGCLUT91,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x16C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x16C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x16C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x16C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x170 "DMA2D_FGCLUT92,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x170 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x170 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x170 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x170 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x174 "DMA2D_FGCLUT93,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x174 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x174 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x174 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x174 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x178 "DMA2D_FGCLUT94,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x178 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x178 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x178 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x178 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x17C "DMA2D_FGCLUT95,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x17C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x17C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x17C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x17C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x180 "DMA2D_FGCLUT96,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x180 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x180 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x180 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x180 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x184 "DMA2D_FGCLUT97,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x184 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x184 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x184 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x184 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x188 "DMA2D_FGCLUT98,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x188 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x188 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x188 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x188 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x18C "DMA2D_FGCLUT99,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x18C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x18C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x18C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x18C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x190 "DMA2D_FGCLUT100,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x190 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x190 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x190 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x190 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x194 "DMA2D_FGCLUT101,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x194 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x194 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x194 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x194 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x198 "DMA2D_FGCLUT102,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x198 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x198 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x198 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x198 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x19C "DMA2D_FGCLUT103,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x19C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x19C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x19C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x19C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1A0 "DMA2D_FGCLUT104,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1A4 "DMA2D_FGCLUT105,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1A8 "DMA2D_FGCLUT106,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1AC "DMA2D_FGCLUT107,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1B0 "DMA2D_FGCLUT108,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1B4 "DMA2D_FGCLUT109,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1B8 "DMA2D_FGCLUT110,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1BC "DMA2D_FGCLUT111,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1C0 "DMA2D_FGCLUT112,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1C4 "DMA2D_FGCLUT113,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1C8 "DMA2D_FGCLUT114,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1CC "DMA2D_FGCLUT115,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1D0 "DMA2D_FGCLUT116,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1D4 "DMA2D_FGCLUT117,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1D8 "DMA2D_FGCLUT118,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1DC "DMA2D_FGCLUT119,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1E0 "DMA2D_FGCLUT120,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1E4 "DMA2D_FGCLUT121,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1E8 "DMA2D_FGCLUT122,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1EC "DMA2D_FGCLUT123,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1F0 "DMA2D_FGCLUT124,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1F4 "DMA2D_FGCLUT125,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1F8 "DMA2D_FGCLUT126,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x1FC "DMA2D_FGCLUT127,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x1FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x1FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x200 "DMA2D_FGCLUT128,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x200 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x200 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x200 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x200 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x204 "DMA2D_FGCLUT129,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x204 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x204 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x204 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x204 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x208 "DMA2D_FGCLUT130,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x208 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x208 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x208 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x208 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x20C "DMA2D_FGCLUT131,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x20C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x20C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x20C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x20C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x210 "DMA2D_FGCLUT132,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x210 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x210 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x210 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x210 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x214 "DMA2D_FGCLUT133,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x214 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x214 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x214 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x214 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x218 "DMA2D_FGCLUT134,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x218 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x218 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x218 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x218 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x21C "DMA2D_FGCLUT135,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x21C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x21C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x21C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x21C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x220 "DMA2D_FGCLUT136,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x220 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x220 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x220 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x220 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x224 "DMA2D_FGCLUT137,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x224 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x224 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x224 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x224 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x228 "DMA2D_FGCLUT138,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x228 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x228 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x228 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x228 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x22C "DMA2D_FGCLUT139,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x22C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x22C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x22C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x22C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x230 "DMA2D_FGCLUT140,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x230 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x230 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x230 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x230 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x234 "DMA2D_FGCLUT141,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x234 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x234 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x234 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x234 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x238 "DMA2D_FGCLUT142,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x238 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x238 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x238 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x238 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x23C "DMA2D_FGCLUT143,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x23C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x23C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x23C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x23C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x240 "DMA2D_FGCLUT144,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x240 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x240 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x240 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x240 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x244 "DMA2D_FGCLUT145,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x244 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x244 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x244 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x244 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x248 "DMA2D_FGCLUT146,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x248 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x248 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x248 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x248 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x24C "DMA2D_FGCLUT147,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x24C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x24C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x24C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x24C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x250 "DMA2D_FGCLUT148,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x250 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x250 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x250 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x250 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x254 "DMA2D_FGCLUT149,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x254 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x254 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x254 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x254 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x258 "DMA2D_FGCLUT150,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x258 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x258 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x258 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x258 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x25C "DMA2D_FGCLUT151,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x25C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x25C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x25C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x25C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x260 "DMA2D_FGCLUT152,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x260 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x260 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x260 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x260 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x264 "DMA2D_FGCLUT153,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x264 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x264 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x264 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x264 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x268 "DMA2D_FGCLUT154,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x268 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x268 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x268 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x268 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x26C "DMA2D_FGCLUT155,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x26C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x26C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x26C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x26C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x270 "DMA2D_FGCLUT156,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x270 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x270 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x270 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x270 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x274 "DMA2D_FGCLUT157,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x274 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x274 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x274 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x274 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x278 "DMA2D_FGCLUT158,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x278 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x278 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x278 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x278 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x27C "DMA2D_FGCLUT159,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x27C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x27C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x27C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x27C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x280 "DMA2D_FGCLUT160,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x280 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x280 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x280 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x280 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x284 "DMA2D_FGCLUT161,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x284 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x284 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x284 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x284 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x288 "DMA2D_FGCLUT162,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x288 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x288 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x288 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x288 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x28C "DMA2D_FGCLUT163,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x28C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x28C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x28C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x28C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x290 "DMA2D_FGCLUT164,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x290 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x290 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x290 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x290 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x294 "DMA2D_FGCLUT165,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x294 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x294 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x294 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x294 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x298 "DMA2D_FGCLUT166,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x298 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x298 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x298 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x298 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x29C "DMA2D_FGCLUT167,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x29C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x29C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x29C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x29C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2A0 "DMA2D_FGCLUT168,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2A4 "DMA2D_FGCLUT169,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2A8 "DMA2D_FGCLUT170,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2AC "DMA2D_FGCLUT171,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2B0 "DMA2D_FGCLUT172,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2B4 "DMA2D_FGCLUT173,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2B8 "DMA2D_FGCLUT174,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2BC "DMA2D_FGCLUT175,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2C0 "DMA2D_FGCLUT176,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2C4 "DMA2D_FGCLUT177,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2C8 "DMA2D_FGCLUT178,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2CC "DMA2D_FGCLUT179,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2D0 "DMA2D_FGCLUT180,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2D4 "DMA2D_FGCLUT181,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2D8 "DMA2D_FGCLUT182,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2DC "DMA2D_FGCLUT183,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2E0 "DMA2D_FGCLUT184,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2E4 "DMA2D_FGCLUT185,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2E8 "DMA2D_FGCLUT186,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2EC "DMA2D_FGCLUT187,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2F0 "DMA2D_FGCLUT188,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2F4 "DMA2D_FGCLUT189,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2F8 "DMA2D_FGCLUT190,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x2FC "DMA2D_FGCLUT191,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x2FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x2FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x300 "DMA2D_FGCLUT192,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x300 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x300 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x300 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x300 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x304 "DMA2D_FGCLUT193,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x304 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x304 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x304 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x304 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x308 "DMA2D_FGCLUT194,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x308 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x308 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x308 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x308 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x30C "DMA2D_FGCLUT195,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x30C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x30C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x30C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x30C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x310 "DMA2D_FGCLUT196,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x310 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x310 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x310 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x310 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x314 "DMA2D_FGCLUT197,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x314 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x314 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x314 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x314 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x318 "DMA2D_FGCLUT198,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x318 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x318 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x318 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x318 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x31C "DMA2D_FGCLUT199,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x31C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x31C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x31C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x31C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x320 "DMA2D_FGCLUT200,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x320 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x320 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x320 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x320 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x324 "DMA2D_FGCLUT201,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x324 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x324 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x324 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x324 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x328 "DMA2D_FGCLUT202,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x328 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x328 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x328 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x328 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x32C "DMA2D_FGCLUT203,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x32C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x32C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x32C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x32C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x330 "DMA2D_FGCLUT204,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x330 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x330 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x330 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x330 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x334 "DMA2D_FGCLUT205,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x334 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x334 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x334 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x334 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x338 "DMA2D_FGCLUT206,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x338 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x338 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x338 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x338 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x33C "DMA2D_FGCLUT207,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x33C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x33C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x33C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x33C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x340 "DMA2D_FGCLUT208,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x340 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x340 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x340 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x340 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x344 "DMA2D_FGCLUT209,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x344 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x344 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x344 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x344 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x348 "DMA2D_FGCLUT210,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x348 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x348 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x348 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x348 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x34C "DMA2D_FGCLUT211,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x34C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x34C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x34C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x34C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x350 "DMA2D_FGCLUT212,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x350 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x350 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x350 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x350 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x354 "DMA2D_FGCLUT213,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x354 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x354 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x354 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x354 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x358 "DMA2D_FGCLUT214,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x358 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x358 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x358 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x358 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x35C "DMA2D_FGCLUT215,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x35C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x35C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x35C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x35C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x360 "DMA2D_FGCLUT216,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x360 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x360 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x360 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x360 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x364 "DMA2D_FGCLUT217,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x364 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x364 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x364 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x364 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x368 "DMA2D_FGCLUT218,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x368 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x368 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x368 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x368 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x36C "DMA2D_FGCLUT219,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x36C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x36C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x36C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x36C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x370 "DMA2D_FGCLUT220,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x370 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x370 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x370 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x370 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x374 "DMA2D_FGCLUT221,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x374 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x374 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x374 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x374 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x378 "DMA2D_FGCLUT222,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x378 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x378 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x378 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x378 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x37C "DMA2D_FGCLUT223,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x37C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x37C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x37C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x37C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x380 "DMA2D_FGCLUT224,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x380 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x380 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x380 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x380 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x384 "DMA2D_FGCLUT225,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x384 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x384 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x384 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x384 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x388 "DMA2D_FGCLUT226,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x388 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x388 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x388 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x388 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x38C "DMA2D_FGCLUT227,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x38C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x38C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x38C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x38C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x390 "DMA2D_FGCLUT228,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x390 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x390 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x390 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x390 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x394 "DMA2D_FGCLUT229,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x394 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x394 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x394 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x394 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x398 "DMA2D_FGCLUT230,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x398 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x398 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x398 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x398 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x39C "DMA2D_FGCLUT231,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x39C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x39C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x39C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x39C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3A0 "DMA2D_FGCLUT232,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3A4 "DMA2D_FGCLUT233,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3A8 "DMA2D_FGCLUT234,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3AC "DMA2D_FGCLUT235,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3B0 "DMA2D_FGCLUT236,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3B4 "DMA2D_FGCLUT237,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3B8 "DMA2D_FGCLUT238,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3BC "DMA2D_FGCLUT239,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3C0 "DMA2D_FGCLUT240,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3C4 "DMA2D_FGCLUT241,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3C8 "DMA2D_FGCLUT242,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3CC "DMA2D_FGCLUT243,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3D0 "DMA2D_FGCLUT244,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3D4 "DMA2D_FGCLUT245,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3D8 "DMA2D_FGCLUT246,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3DC "DMA2D_FGCLUT247,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3E0 "DMA2D_FGCLUT248,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3E4 "DMA2D_FGCLUT249,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3E8 "DMA2D_FGCLUT250,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3EC "DMA2D_FGCLUT251,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3F0 "DMA2D_FGCLUT252,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3F4 "DMA2D_FGCLUT253,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3F8 "DMA2D_FGCLUT254,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x3FC "DMA2D_FGCLUT255,DMA2D foreground CLUT"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x3FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x3FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x400 "DMA2D_BGCLUT0,DMA2D background CLUT"
|
|
hexmask.long.byte 0x400 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x400 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x400 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x400 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x404 "DMA2D_BGCLUT1,DMA2D background CLUT"
|
|
hexmask.long.byte 0x404 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x404 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x404 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x404 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x408 "DMA2D_BGCLUT2,DMA2D background CLUT"
|
|
hexmask.long.byte 0x408 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x408 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x408 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x408 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x40C "DMA2D_BGCLUT3,DMA2D background CLUT"
|
|
hexmask.long.byte 0x40C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x40C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x40C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x40C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x410 "DMA2D_BGCLUT4,DMA2D background CLUT"
|
|
hexmask.long.byte 0x410 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x410 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x410 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x410 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x414 "DMA2D_BGCLUT5,DMA2D background CLUT"
|
|
hexmask.long.byte 0x414 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x414 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x414 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x414 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x418 "DMA2D_BGCLUT6,DMA2D background CLUT"
|
|
hexmask.long.byte 0x418 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x418 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x418 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x418 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x41C "DMA2D_BGCLUT7,DMA2D background CLUT"
|
|
hexmask.long.byte 0x41C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x41C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x41C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x41C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x420 "DMA2D_BGCLUT8,DMA2D background CLUT"
|
|
hexmask.long.byte 0x420 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x420 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x420 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x420 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x424 "DMA2D_BGCLUT9,DMA2D background CLUT"
|
|
hexmask.long.byte 0x424 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x424 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x424 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x424 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x428 "DMA2D_BGCLUT10,DMA2D background CLUT"
|
|
hexmask.long.byte 0x428 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x428 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x428 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x428 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x42C "DMA2D_BGCLUT11,DMA2D background CLUT"
|
|
hexmask.long.byte 0x42C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x42C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x42C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x42C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x430 "DMA2D_BGCLUT12,DMA2D background CLUT"
|
|
hexmask.long.byte 0x430 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x430 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x430 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x430 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x434 "DMA2D_BGCLUT13,DMA2D background CLUT"
|
|
hexmask.long.byte 0x434 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x434 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x434 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x434 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x438 "DMA2D_BGCLUT14,DMA2D background CLUT"
|
|
hexmask.long.byte 0x438 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x438 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x438 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x438 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x43C "DMA2D_BGCLUT15,DMA2D background CLUT"
|
|
hexmask.long.byte 0x43C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x43C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x43C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x43C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x440 "DMA2D_BGCLUT16,DMA2D background CLUT"
|
|
hexmask.long.byte 0x440 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x440 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x440 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x440 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x444 "DMA2D_BGCLUT17,DMA2D background CLUT"
|
|
hexmask.long.byte 0x444 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x444 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x444 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x444 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x448 "DMA2D_BGCLUT18,DMA2D background CLUT"
|
|
hexmask.long.byte 0x448 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x448 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x448 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x448 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x44C "DMA2D_BGCLUT19,DMA2D background CLUT"
|
|
hexmask.long.byte 0x44C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x44C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x44C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x44C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x450 "DMA2D_BGCLUT20,DMA2D background CLUT"
|
|
hexmask.long.byte 0x450 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x450 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x450 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x450 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x454 "DMA2D_BGCLUT21,DMA2D background CLUT"
|
|
hexmask.long.byte 0x454 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x454 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x454 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x454 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x458 "DMA2D_BGCLUT22,DMA2D background CLUT"
|
|
hexmask.long.byte 0x458 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x458 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x458 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x458 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x45C "DMA2D_BGCLUT23,DMA2D background CLUT"
|
|
hexmask.long.byte 0x45C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x45C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x45C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x45C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x460 "DMA2D_BGCLUT24,DMA2D background CLUT"
|
|
hexmask.long.byte 0x460 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x460 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x460 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x460 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x464 "DMA2D_BGCLUT25,DMA2D background CLUT"
|
|
hexmask.long.byte 0x464 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x464 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x464 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x464 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x468 "DMA2D_BGCLUT26,DMA2D background CLUT"
|
|
hexmask.long.byte 0x468 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x468 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x468 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x468 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x46C "DMA2D_BGCLUT27,DMA2D background CLUT"
|
|
hexmask.long.byte 0x46C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x46C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x46C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x46C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x470 "DMA2D_BGCLUT28,DMA2D background CLUT"
|
|
hexmask.long.byte 0x470 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x470 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x470 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x470 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x474 "DMA2D_BGCLUT29,DMA2D background CLUT"
|
|
hexmask.long.byte 0x474 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x474 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x474 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x474 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x478 "DMA2D_BGCLUT30,DMA2D background CLUT"
|
|
hexmask.long.byte 0x478 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x478 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x478 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x478 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x47C "DMA2D_BGCLUT31,DMA2D background CLUT"
|
|
hexmask.long.byte 0x47C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x47C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x47C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x47C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x480 "DMA2D_BGCLUT32,DMA2D background CLUT"
|
|
hexmask.long.byte 0x480 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x480 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x480 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x480 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x484 "DMA2D_BGCLUT33,DMA2D background CLUT"
|
|
hexmask.long.byte 0x484 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x484 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x484 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x484 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x488 "DMA2D_BGCLUT34,DMA2D background CLUT"
|
|
hexmask.long.byte 0x488 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x488 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x488 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x488 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x48C "DMA2D_BGCLUT35,DMA2D background CLUT"
|
|
hexmask.long.byte 0x48C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x48C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x48C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x48C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x490 "DMA2D_BGCLUT36,DMA2D background CLUT"
|
|
hexmask.long.byte 0x490 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x490 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x490 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x490 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x494 "DMA2D_BGCLUT37,DMA2D background CLUT"
|
|
hexmask.long.byte 0x494 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x494 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x494 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x494 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x498 "DMA2D_BGCLUT38,DMA2D background CLUT"
|
|
hexmask.long.byte 0x498 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x498 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x498 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x498 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x49C "DMA2D_BGCLUT39,DMA2D background CLUT"
|
|
hexmask.long.byte 0x49C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x49C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x49C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x49C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4A0 "DMA2D_BGCLUT40,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4A4 "DMA2D_BGCLUT41,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4A8 "DMA2D_BGCLUT42,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4AC "DMA2D_BGCLUT43,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4B0 "DMA2D_BGCLUT44,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4B4 "DMA2D_BGCLUT45,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4B8 "DMA2D_BGCLUT46,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4BC "DMA2D_BGCLUT47,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4C0 "DMA2D_BGCLUT48,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4C4 "DMA2D_BGCLUT49,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4C8 "DMA2D_BGCLUT50,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4CC "DMA2D_BGCLUT51,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4D0 "DMA2D_BGCLUT52,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4D4 "DMA2D_BGCLUT53,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4D8 "DMA2D_BGCLUT54,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4DC "DMA2D_BGCLUT55,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4E0 "DMA2D_BGCLUT56,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4E4 "DMA2D_BGCLUT57,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4E8 "DMA2D_BGCLUT58,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4EC "DMA2D_BGCLUT59,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4F0 "DMA2D_BGCLUT60,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4F4 "DMA2D_BGCLUT61,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4F8 "DMA2D_BGCLUT62,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x4FC "DMA2D_BGCLUT63,DMA2D background CLUT"
|
|
hexmask.long.byte 0x4FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x4FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x4FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x4FC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x500 "DMA2D_BGCLUT64,DMA2D background CLUT"
|
|
hexmask.long.byte 0x500 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x500 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x500 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x500 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x504 "DMA2D_BGCLUT65,DMA2D background CLUT"
|
|
hexmask.long.byte 0x504 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x504 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x504 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x504 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x508 "DMA2D_BGCLUT66,DMA2D background CLUT"
|
|
hexmask.long.byte 0x508 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x508 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x508 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x508 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x50C "DMA2D_BGCLUT67,DMA2D background CLUT"
|
|
hexmask.long.byte 0x50C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x50C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x50C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x50C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x510 "DMA2D_BGCLUT68,DMA2D background CLUT"
|
|
hexmask.long.byte 0x510 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x510 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x510 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x510 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x514 "DMA2D_BGCLUT69,DMA2D background CLUT"
|
|
hexmask.long.byte 0x514 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x514 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x514 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x514 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x518 "DMA2D_BGCLUT70,DMA2D background CLUT"
|
|
hexmask.long.byte 0x518 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x518 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x518 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x518 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x51C "DMA2D_BGCLUT71,DMA2D background CLUT"
|
|
hexmask.long.byte 0x51C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x51C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x51C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x51C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x520 "DMA2D_BGCLUT72,DMA2D background CLUT"
|
|
hexmask.long.byte 0x520 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x520 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x520 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x520 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x524 "DMA2D_BGCLUT73,DMA2D background CLUT"
|
|
hexmask.long.byte 0x524 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x524 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x524 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x524 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x528 "DMA2D_BGCLUT74,DMA2D background CLUT"
|
|
hexmask.long.byte 0x528 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x528 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x528 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x528 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x52C "DMA2D_BGCLUT75,DMA2D background CLUT"
|
|
hexmask.long.byte 0x52C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x52C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x52C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x52C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x530 "DMA2D_BGCLUT76,DMA2D background CLUT"
|
|
hexmask.long.byte 0x530 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x530 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x530 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x530 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x534 "DMA2D_BGCLUT77,DMA2D background CLUT"
|
|
hexmask.long.byte 0x534 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x534 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x534 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x534 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x538 "DMA2D_BGCLUT78,DMA2D background CLUT"
|
|
hexmask.long.byte 0x538 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x538 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x538 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x538 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x53C "DMA2D_BGCLUT79,DMA2D background CLUT"
|
|
hexmask.long.byte 0x53C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x53C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x53C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x53C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x540 "DMA2D_BGCLUT80,DMA2D background CLUT"
|
|
hexmask.long.byte 0x540 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x540 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x540 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x540 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x544 "DMA2D_BGCLUT81,DMA2D background CLUT"
|
|
hexmask.long.byte 0x544 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x544 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x544 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x544 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x548 "DMA2D_BGCLUT82,DMA2D background CLUT"
|
|
hexmask.long.byte 0x548 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x548 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x548 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x548 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x54C "DMA2D_BGCLUT83,DMA2D background CLUT"
|
|
hexmask.long.byte 0x54C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x54C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x54C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x54C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x550 "DMA2D_BGCLUT84,DMA2D background CLUT"
|
|
hexmask.long.byte 0x550 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x550 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x550 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x550 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x554 "DMA2D_BGCLUT85,DMA2D background CLUT"
|
|
hexmask.long.byte 0x554 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x554 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x554 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x554 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x558 "DMA2D_BGCLUT86,DMA2D background CLUT"
|
|
hexmask.long.byte 0x558 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x558 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x558 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x558 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x55C "DMA2D_BGCLUT87,DMA2D background CLUT"
|
|
hexmask.long.byte 0x55C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x55C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x55C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x55C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x560 "DMA2D_BGCLUT88,DMA2D background CLUT"
|
|
hexmask.long.byte 0x560 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x560 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x560 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x560 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x564 "DMA2D_BGCLUT89,DMA2D background CLUT"
|
|
hexmask.long.byte 0x564 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x564 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x564 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x564 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x568 "DMA2D_BGCLUT90,DMA2D background CLUT"
|
|
hexmask.long.byte 0x568 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x568 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x568 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x568 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x56C "DMA2D_BGCLUT91,DMA2D background CLUT"
|
|
hexmask.long.byte 0x56C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x56C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x56C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x56C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x570 "DMA2D_BGCLUT92,DMA2D background CLUT"
|
|
hexmask.long.byte 0x570 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x570 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x570 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x570 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x574 "DMA2D_BGCLUT93,DMA2D background CLUT"
|
|
hexmask.long.byte 0x574 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x574 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x574 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x574 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x578 "DMA2D_BGCLUT94,DMA2D background CLUT"
|
|
hexmask.long.byte 0x578 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x578 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x578 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x578 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x57C "DMA2D_BGCLUT95,DMA2D background CLUT"
|
|
hexmask.long.byte 0x57C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x57C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x57C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x57C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x580 "DMA2D_BGCLUT96,DMA2D background CLUT"
|
|
hexmask.long.byte 0x580 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x580 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x580 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x580 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x584 "DMA2D_BGCLUT97,DMA2D background CLUT"
|
|
hexmask.long.byte 0x584 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x584 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x584 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x584 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x588 "DMA2D_BGCLUT98,DMA2D background CLUT"
|
|
hexmask.long.byte 0x588 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x588 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x588 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x588 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x58C "DMA2D_BGCLUT99,DMA2D background CLUT"
|
|
hexmask.long.byte 0x58C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x58C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x58C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x58C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x590 "DMA2D_BGCLUT100,DMA2D background CLUT"
|
|
hexmask.long.byte 0x590 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x590 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x590 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x590 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x594 "DMA2D_BGCLUT101,DMA2D background CLUT"
|
|
hexmask.long.byte 0x594 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x594 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x594 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x594 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x598 "DMA2D_BGCLUT102,DMA2D background CLUT"
|
|
hexmask.long.byte 0x598 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x598 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x598 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x598 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x59C "DMA2D_BGCLUT103,DMA2D background CLUT"
|
|
hexmask.long.byte 0x59C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x59C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x59C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x59C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5A0 "DMA2D_BGCLUT104,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5A4 "DMA2D_BGCLUT105,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5A8 "DMA2D_BGCLUT106,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5AC "DMA2D_BGCLUT107,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5B0 "DMA2D_BGCLUT108,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5B4 "DMA2D_BGCLUT109,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5B8 "DMA2D_BGCLUT110,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5BC "DMA2D_BGCLUT111,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5C0 "DMA2D_BGCLUT112,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5C4 "DMA2D_BGCLUT113,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5C8 "DMA2D_BGCLUT114,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5CC "DMA2D_BGCLUT115,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5D0 "DMA2D_BGCLUT116,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5D4 "DMA2D_BGCLUT117,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5D8 "DMA2D_BGCLUT118,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5DC "DMA2D_BGCLUT119,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5E0 "DMA2D_BGCLUT120,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5E4 "DMA2D_BGCLUT121,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5E8 "DMA2D_BGCLUT122,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5EC "DMA2D_BGCLUT123,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5F0 "DMA2D_BGCLUT124,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5F4 "DMA2D_BGCLUT125,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5F8 "DMA2D_BGCLUT126,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x5FC "DMA2D_BGCLUT127,DMA2D background CLUT"
|
|
hexmask.long.byte 0x5FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x5FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x5FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x5FC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x600 "DMA2D_BGCLUT128,DMA2D background CLUT"
|
|
hexmask.long.byte 0x600 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x600 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x600 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x600 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x604 "DMA2D_BGCLUT129,DMA2D background CLUT"
|
|
hexmask.long.byte 0x604 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x604 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x604 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x604 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x608 "DMA2D_BGCLUT130,DMA2D background CLUT"
|
|
hexmask.long.byte 0x608 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x608 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x608 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x608 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x60C "DMA2D_BGCLUT131,DMA2D background CLUT"
|
|
hexmask.long.byte 0x60C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x60C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x60C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x60C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x610 "DMA2D_BGCLUT132,DMA2D background CLUT"
|
|
hexmask.long.byte 0x610 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x610 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x610 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x610 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x614 "DMA2D_BGCLUT133,DMA2D background CLUT"
|
|
hexmask.long.byte 0x614 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x614 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x614 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x614 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x618 "DMA2D_BGCLUT134,DMA2D background CLUT"
|
|
hexmask.long.byte 0x618 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x618 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x618 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x618 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x61C "DMA2D_BGCLUT135,DMA2D background CLUT"
|
|
hexmask.long.byte 0x61C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x61C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x61C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x61C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x620 "DMA2D_BGCLUT136,DMA2D background CLUT"
|
|
hexmask.long.byte 0x620 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x620 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x620 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x620 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x624 "DMA2D_BGCLUT137,DMA2D background CLUT"
|
|
hexmask.long.byte 0x624 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x624 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x624 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x624 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x628 "DMA2D_BGCLUT138,DMA2D background CLUT"
|
|
hexmask.long.byte 0x628 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x628 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x628 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x628 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x62C "DMA2D_BGCLUT139,DMA2D background CLUT"
|
|
hexmask.long.byte 0x62C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x62C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x62C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x62C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x630 "DMA2D_BGCLUT140,DMA2D background CLUT"
|
|
hexmask.long.byte 0x630 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x630 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x630 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x630 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x634 "DMA2D_BGCLUT141,DMA2D background CLUT"
|
|
hexmask.long.byte 0x634 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x634 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x634 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x634 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x638 "DMA2D_BGCLUT142,DMA2D background CLUT"
|
|
hexmask.long.byte 0x638 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x638 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x638 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x638 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x63C "DMA2D_BGCLUT143,DMA2D background CLUT"
|
|
hexmask.long.byte 0x63C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x63C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x63C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x63C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x640 "DMA2D_BGCLUT144,DMA2D background CLUT"
|
|
hexmask.long.byte 0x640 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x640 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x640 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x640 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x644 "DMA2D_BGCLUT145,DMA2D background CLUT"
|
|
hexmask.long.byte 0x644 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x644 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x644 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x644 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x648 "DMA2D_BGCLUT146,DMA2D background CLUT"
|
|
hexmask.long.byte 0x648 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x648 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x648 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x648 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x64C "DMA2D_BGCLUT147,DMA2D background CLUT"
|
|
hexmask.long.byte 0x64C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x64C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x64C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x64C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x650 "DMA2D_BGCLUT148,DMA2D background CLUT"
|
|
hexmask.long.byte 0x650 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x650 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x650 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x650 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x654 "DMA2D_BGCLUT149,DMA2D background CLUT"
|
|
hexmask.long.byte 0x654 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x654 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x654 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x654 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x658 "DMA2D_BGCLUT150,DMA2D background CLUT"
|
|
hexmask.long.byte 0x658 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x658 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x658 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x658 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x65C "DMA2D_BGCLUT151,DMA2D background CLUT"
|
|
hexmask.long.byte 0x65C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x65C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x65C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x65C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x660 "DMA2D_BGCLUT152,DMA2D background CLUT"
|
|
hexmask.long.byte 0x660 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x660 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x660 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x660 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x664 "DMA2D_BGCLUT153,DMA2D background CLUT"
|
|
hexmask.long.byte 0x664 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x664 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x664 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x664 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x668 "DMA2D_BGCLUT154,DMA2D background CLUT"
|
|
hexmask.long.byte 0x668 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x668 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x668 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x668 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x66C "DMA2D_BGCLUT155,DMA2D background CLUT"
|
|
hexmask.long.byte 0x66C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x66C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x66C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x66C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x670 "DMA2D_BGCLUT156,DMA2D background CLUT"
|
|
hexmask.long.byte 0x670 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x670 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x670 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x670 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x674 "DMA2D_BGCLUT157,DMA2D background CLUT"
|
|
hexmask.long.byte 0x674 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x674 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x674 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x674 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x678 "DMA2D_BGCLUT158,DMA2D background CLUT"
|
|
hexmask.long.byte 0x678 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x678 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x678 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x678 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x67C "DMA2D_BGCLUT159,DMA2D background CLUT"
|
|
hexmask.long.byte 0x67C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x67C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x67C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x67C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x680 "DMA2D_BGCLUT160,DMA2D background CLUT"
|
|
hexmask.long.byte 0x680 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x680 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x680 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x680 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x684 "DMA2D_BGCLUT161,DMA2D background CLUT"
|
|
hexmask.long.byte 0x684 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x684 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x684 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x684 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x688 "DMA2D_BGCLUT162,DMA2D background CLUT"
|
|
hexmask.long.byte 0x688 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x688 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x688 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x688 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x68C "DMA2D_BGCLUT163,DMA2D background CLUT"
|
|
hexmask.long.byte 0x68C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x68C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x68C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x68C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x690 "DMA2D_BGCLUT164,DMA2D background CLUT"
|
|
hexmask.long.byte 0x690 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x690 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x690 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x690 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x694 "DMA2D_BGCLUT165,DMA2D background CLUT"
|
|
hexmask.long.byte 0x694 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x694 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x694 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x694 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x698 "DMA2D_BGCLUT166,DMA2D background CLUT"
|
|
hexmask.long.byte 0x698 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x698 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x698 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x698 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x69C "DMA2D_BGCLUT167,DMA2D background CLUT"
|
|
hexmask.long.byte 0x69C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x69C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x69C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x69C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6A0 "DMA2D_BGCLUT168,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6A4 "DMA2D_BGCLUT169,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6A8 "DMA2D_BGCLUT170,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6AC "DMA2D_BGCLUT171,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6B0 "DMA2D_BGCLUT172,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6B4 "DMA2D_BGCLUT173,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6B8 "DMA2D_BGCLUT174,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6BC "DMA2D_BGCLUT175,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6C0 "DMA2D_BGCLUT176,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6C4 "DMA2D_BGCLUT177,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6C8 "DMA2D_BGCLUT178,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6CC "DMA2D_BGCLUT179,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6D0 "DMA2D_BGCLUT180,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6D4 "DMA2D_BGCLUT181,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6D8 "DMA2D_BGCLUT182,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6DC "DMA2D_BGCLUT183,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6E0 "DMA2D_BGCLUT184,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6E4 "DMA2D_BGCLUT185,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6E8 "DMA2D_BGCLUT186,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6EC "DMA2D_BGCLUT187,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6F0 "DMA2D_BGCLUT188,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6F4 "DMA2D_BGCLUT189,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6F8 "DMA2D_BGCLUT190,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x6FC "DMA2D_BGCLUT191,DMA2D background CLUT"
|
|
hexmask.long.byte 0x6FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x6FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x6FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x6FC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x700 "DMA2D_BGCLUT192,DMA2D background CLUT"
|
|
hexmask.long.byte 0x700 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x700 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x700 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x700 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x704 "DMA2D_BGCLUT193,DMA2D background CLUT"
|
|
hexmask.long.byte 0x704 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x704 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x704 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x704 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x708 "DMA2D_BGCLUT194,DMA2D background CLUT"
|
|
hexmask.long.byte 0x708 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x708 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x708 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x708 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x70C "DMA2D_BGCLUT195,DMA2D background CLUT"
|
|
hexmask.long.byte 0x70C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x70C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x70C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x70C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x710 "DMA2D_BGCLUT196,DMA2D background CLUT"
|
|
hexmask.long.byte 0x710 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x710 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x710 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x710 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x714 "DMA2D_BGCLUT197,DMA2D background CLUT"
|
|
hexmask.long.byte 0x714 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x714 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x714 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x714 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x718 "DMA2D_BGCLUT198,DMA2D background CLUT"
|
|
hexmask.long.byte 0x718 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x718 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x718 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x718 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x71C "DMA2D_BGCLUT199,DMA2D background CLUT"
|
|
hexmask.long.byte 0x71C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x71C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x71C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x71C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x720 "DMA2D_BGCLUT200,DMA2D background CLUT"
|
|
hexmask.long.byte 0x720 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x720 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x720 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x720 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x724 "DMA2D_BGCLUT201,DMA2D background CLUT"
|
|
hexmask.long.byte 0x724 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x724 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x724 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x724 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x728 "DMA2D_BGCLUT202,DMA2D background CLUT"
|
|
hexmask.long.byte 0x728 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x728 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x728 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x728 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x72C "DMA2D_BGCLUT203,DMA2D background CLUT"
|
|
hexmask.long.byte 0x72C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x72C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x72C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x72C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x730 "DMA2D_BGCLUT204,DMA2D background CLUT"
|
|
hexmask.long.byte 0x730 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x730 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x730 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x730 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x734 "DMA2D_BGCLUT205,DMA2D background CLUT"
|
|
hexmask.long.byte 0x734 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x734 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x734 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x734 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x738 "DMA2D_BGCLUT206,DMA2D background CLUT"
|
|
hexmask.long.byte 0x738 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x738 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x738 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x738 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x73C "DMA2D_BGCLUT207,DMA2D background CLUT"
|
|
hexmask.long.byte 0x73C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x73C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x73C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x73C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x740 "DMA2D_BGCLUT208,DMA2D background CLUT"
|
|
hexmask.long.byte 0x740 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x740 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x740 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x740 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x744 "DMA2D_BGCLUT209,DMA2D background CLUT"
|
|
hexmask.long.byte 0x744 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x744 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x744 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x744 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x748 "DMA2D_BGCLUT210,DMA2D background CLUT"
|
|
hexmask.long.byte 0x748 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x748 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x748 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x748 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x74C "DMA2D_BGCLUT211,DMA2D background CLUT"
|
|
hexmask.long.byte 0x74C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x74C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x74C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x74C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x750 "DMA2D_BGCLUT212,DMA2D background CLUT"
|
|
hexmask.long.byte 0x750 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x750 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x750 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x750 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x754 "DMA2D_BGCLUT213,DMA2D background CLUT"
|
|
hexmask.long.byte 0x754 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x754 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x754 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x754 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x758 "DMA2D_BGCLUT214,DMA2D background CLUT"
|
|
hexmask.long.byte 0x758 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x758 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x758 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x758 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x75C "DMA2D_BGCLUT215,DMA2D background CLUT"
|
|
hexmask.long.byte 0x75C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x75C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x75C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x75C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x760 "DMA2D_BGCLUT216,DMA2D background CLUT"
|
|
hexmask.long.byte 0x760 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x760 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x760 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x760 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x764 "DMA2D_BGCLUT217,DMA2D background CLUT"
|
|
hexmask.long.byte 0x764 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x764 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x764 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x764 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x768 "DMA2D_BGCLUT218,DMA2D background CLUT"
|
|
hexmask.long.byte 0x768 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x768 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x768 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x768 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x76C "DMA2D_BGCLUT219,DMA2D background CLUT"
|
|
hexmask.long.byte 0x76C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x76C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x76C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x76C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x770 "DMA2D_BGCLUT220,DMA2D background CLUT"
|
|
hexmask.long.byte 0x770 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x770 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x770 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x770 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x774 "DMA2D_BGCLUT221,DMA2D background CLUT"
|
|
hexmask.long.byte 0x774 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x774 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x774 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x774 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x778 "DMA2D_BGCLUT222,DMA2D background CLUT"
|
|
hexmask.long.byte 0x778 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x778 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x778 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x778 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x77C "DMA2D_BGCLUT223,DMA2D background CLUT"
|
|
hexmask.long.byte 0x77C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x77C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x77C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x77C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x780 "DMA2D_BGCLUT224,DMA2D background CLUT"
|
|
hexmask.long.byte 0x780 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x780 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x780 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x780 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x784 "DMA2D_BGCLUT225,DMA2D background CLUT"
|
|
hexmask.long.byte 0x784 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x784 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x784 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x784 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x788 "DMA2D_BGCLUT226,DMA2D background CLUT"
|
|
hexmask.long.byte 0x788 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x788 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x788 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x788 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x78C "DMA2D_BGCLUT227,DMA2D background CLUT"
|
|
hexmask.long.byte 0x78C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x78C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x78C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x78C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x790 "DMA2D_BGCLUT228,DMA2D background CLUT"
|
|
hexmask.long.byte 0x790 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x790 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x790 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x790 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x794 "DMA2D_BGCLUT229,DMA2D background CLUT"
|
|
hexmask.long.byte 0x794 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x794 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x794 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x794 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x798 "DMA2D_BGCLUT230,DMA2D background CLUT"
|
|
hexmask.long.byte 0x798 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x798 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x798 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x798 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x79C "DMA2D_BGCLUT231,DMA2D background CLUT"
|
|
hexmask.long.byte 0x79C 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x79C 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x79C 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x79C 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7A0 "DMA2D_BGCLUT232,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7A0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7A0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7A0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7A0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7A4 "DMA2D_BGCLUT233,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7A4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7A4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7A4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7A4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7A8 "DMA2D_BGCLUT234,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7A8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7A8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7A8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7A8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7AC "DMA2D_BGCLUT235,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7AC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7AC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7AC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7AC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7B0 "DMA2D_BGCLUT236,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7B0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7B0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7B0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7B0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7B4 "DMA2D_BGCLUT237,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7B4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7B4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7B4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7B4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7B8 "DMA2D_BGCLUT238,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7B8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7B8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7B8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7B8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7BC "DMA2D_BGCLUT239,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7BC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7BC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7BC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7BC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7C0 "DMA2D_BGCLUT240,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7C0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7C0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7C0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7C0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7C4 "DMA2D_BGCLUT241,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7C4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7C4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7C4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7C4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7C8 "DMA2D_BGCLUT242,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7C8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7C8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7C8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7C8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7CC "DMA2D_BGCLUT243,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7CC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7CC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7CC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7CC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7D0 "DMA2D_BGCLUT244,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7D0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7D0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7D0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7D0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7D4 "DMA2D_BGCLUT245,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7D4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7D4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7D4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7D4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7D8 "DMA2D_BGCLUT246,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7D8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7D8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7D8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7D8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7DC "DMA2D_BGCLUT247,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7DC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7DC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7DC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7DC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7E0 "DMA2D_BGCLUT248,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7E0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7E0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7E0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7E0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7E4 "DMA2D_BGCLUT249,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7E4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7E4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7E4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7E4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7E8 "DMA2D_BGCLUT250,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7E8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7E8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7E8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7E8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7EC "DMA2D_BGCLUT251,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7EC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7EC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7EC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7EC 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7F0 "DMA2D_BGCLUT252,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7F0 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7F0 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7F0 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7F0 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7F4 "DMA2D_BGCLUT253,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7F4 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7F4 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7F4 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7F4 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7F8 "DMA2D_BGCLUT254,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7F8 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7F8 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7F8 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7F8 0.--7. 1. "BLUE,Blue"
|
|
line.long 0x7FC "DMA2D_BGCLUT255,DMA2D background CLUT"
|
|
hexmask.long.byte 0x7FC 24.--31. 1. "ALPHA,Alpha"
|
|
hexmask.long.byte 0x7FC 16.--23. 1. "RED,Red"
|
|
newline
|
|
hexmask.long.byte 0x7FC 8.--15. 1. "GREEN,Green"
|
|
hexmask.long.byte 0x7FC 0.--7. 1. "BLUE,Blue"
|
|
tree.end
|
|
tree "DTS (Digital Temperature Sensor)"
|
|
base ad:0x58006800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DTS_CFGR1,Temperature sensor configuration register 1"
|
|
hexmask.long.byte 0x0 24.--30. 1. "HSREF_CLK_DIV,High speed clock division ratio"
|
|
bitfld.long 0x0 21. "Q_MEAS_OPT,Quick measurement option bit" "0: Measurement with calibration,1: Measurement without calibration"
|
|
newline
|
|
bitfld.long 0x0 20. "REFCLK_SEL,Reference clock selection bit" "0: High speed reference clock (PCLK),1: Low speed reference clock (LSE)"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TS1_SMP_TIME,Sampling time for temperature sensor 1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TS1_INTRIG_SEL,Input trigger selection bit for temperature sensor 1"
|
|
bitfld.long 0x0 4. "TS1_START,Start frequency measurement on temperature sensor 1" "0: No software trigger.,1: Software trigger for a frequency measurement."
|
|
newline
|
|
bitfld.long 0x0 0. "TS1_EN,Temperature sensor 1 enable bit" "0: Temperature sensor 1 disabled,1: Temperature sensor 1 enabled"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DTS_T0VALR1,Temperature sensor T0 value register 1"
|
|
bitfld.long 0x0 16.--17. "TS1_T0,Engineering value of the T0 temperature for temperature sensor 1." "0: 30 C,1: 130 C,?,?"
|
|
hexmask.long.word 0x0 0.--15. 1. "TS1_FMT0,Engineering value of the frequency measured at T0 for"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "DTS_RAMPVALR,Temperature sensor ramp value register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TS1_RAMP_COEFF,Engineering value of the ramp coefficient for the temperature sensor 1."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DTS_ITR1,Temperature sensor interrupt threshold register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "TS1_HITTHD,High interrupt threshold for temperature sensor 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "TS1_LITTHD,Low interrupt threshold for temperature sensor 1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "DTS_DR,Temperature sensor data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TS1_MFREQ,Value of the counter output value for temperature sensor 1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "DTS_SR,Temperature sensor status register"
|
|
bitfld.long 0x0 15. "TS1_RDY,Temperature sensor 1 ready flag" "0: Temperature sensor 1 busy,1: Temperature sensor 1 ready"
|
|
bitfld.long 0x0 6. "TS1_AITHF,Asynchronous interrupt flag for high threshold on temperature sensor 1" "0: High threshold not reached on temperature sensor 1,1: High threshold reached on temperature sensor 1"
|
|
newline
|
|
bitfld.long 0x0 5. "TS1_AITLF,Asynchronous interrupt flag for low threshold on temperature sensor 1" "0: Low threshold not reached on temperature sensor 1,1: Low threshold reached on temperature sensor 1"
|
|
bitfld.long 0x0 4. "TS1_AITEF,Asynchronous interrupt flag for end of measure on temperature sensor 1" "0: End of measure not detected on temperature..,1: End of measure detected on temperature sensor 1"
|
|
newline
|
|
bitfld.long 0x0 2. "TS1_ITHF,Interrupt flag for high threshold on temperature sensor 1 synchronized on PCLK" "0: High threshold not reached on temperature sensor 1,1: High threshold reached on temperature sensor 1"
|
|
bitfld.long 0x0 1. "TS1_ITLF,Interrupt flag for low threshold on temperature sensor 1 synchronized on PCLK." "0: Low threshold not reached on temperature sensor 1,1: Low threshold reached on temperature sensor 1"
|
|
newline
|
|
bitfld.long 0x0 0. "TS1_ITEF,Interrupt flag for end of measurement on temperature sensor 1 synchronized on PCLK." "0: No end of measurement detected on temperature..,1: End of measure detected on temperature sensor 1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "DTS_ITENR,Temperature sensor interrupt enable register"
|
|
bitfld.long 0x0 6. "TS1_AITHEN,Asynchronous interrupt enable flag on high threshold for temperature sensor 1." "0: Asynchronous interrupt on high threshold..,1: Asynchronous interrupt on high threshold enabled.."
|
|
bitfld.long 0x0 5. "TS1_AITLEN,Asynchronous interrupt enable flag for low threshold on temperature sensor 1." "0: Asynchronous interrupt on low threshold disabled..,1: Asynchronous interrupt on low threshold enabled.."
|
|
newline
|
|
bitfld.long 0x0 4. "TS1_AITEEN,Asynchronous interrupt enable flag for end of measurement on temperature sensor 1" "0: Asynchronous interrupt for end of measurement..,1: Asynchronous interrupt for end of measurement.."
|
|
bitfld.long 0x0 2. "TS1_ITHEN,Interrupt enable flag for high threshold on temperature sensor 1 synchronized on PCLK." "0: Synchronous interrupt for high threshold..,1: Synchronous interrupt for high threshold enabled.."
|
|
newline
|
|
bitfld.long 0x0 1. "TS1_ITLEN,Interrupt enable flag for low threshold on temperature sensor 1 synchronized on PCLK." "0: Synchronous interrupt for low threshold disabled..,1: Synchronous interrupt for low threshold enabled.."
|
|
bitfld.long 0x0 0. "TS1_ITEEN,Interrupt enable flag for end of measurement on temperature sensor 1 synchronized on PCLK." "0: Synchronous interrupt for end of measurement..,1: Synchronous interrupt for end of measurement.."
|
|
line.long 0x4 "DTS_ICIFR,Temperature sensor clear interrupt flag register"
|
|
bitfld.long 0x4 6. "TS1_CAITHF,Asynchronous interrupt clear flag for high threshold on temperature sensor 1" "0,1"
|
|
bitfld.long 0x4 5. "TS1_CAITLF,Asynchronous interrupt clear flag for low threshold on temperature sensor 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TS1_CAITEF,Write once bit. Clear the asynchronous IT flag for End Of Measure for thermal sensor 1." "0,1"
|
|
bitfld.long 0x4 2. "TS1_CITHF,Interrupt clear flag for high threshold on temperature sensor 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TS1_CITLF,Interrupt clear flag for low threshold on temperature sensor 1" "0,1"
|
|
bitfld.long 0x4 0. "TS1_CITEF,Interrupt clear flag for end of measurement on temperature sensor 1" "0,1"
|
|
line.long 0x8 "DTS_OR,Temperature sensor option register"
|
|
bitfld.long 0x8 31. "TS_OP31,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 30. "TS_OP30,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TS_OP29,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 28. "TS_OP28,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "TS_OP27,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 26. "TS_OP26,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "TS_OP25,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 24. "TS_OP24,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "TS_OP23,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 22. "TS_OP22,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "TS_OP21,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 20. "TS_OP20,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "TS_OP19,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 18. "TS_OP18,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "TS_OP17,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 16. "TS_OP16,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TS_OP15,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 14. "TS_OP14,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TS_OP13,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 12. "TS_OP12,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TS_OP11,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 10. "TS_OP10,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TS_OP9,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 8. "TS_OP8,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "TS_OP7,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 6. "TS_OP6,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TS_OP5,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 4. "TS_OP4,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TS_OP3,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 2. "TS_OP2,general purpose option bits" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TS_OP1,general purpose option bits" "0,1"
|
|
bitfld.long 0x8 0. "TS_OP0,general purpose option bits" "0,1"
|
|
tree.end
|
|
tree "ETH (Ethernet)"
|
|
base ad:0x40028000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "ETH_MACCR,Operating mode configuration register"
|
|
bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "?,?,2: the MAC inserts the content of the MAC Address 0..,3: the MAC replaces the content of the MAC Address..,?,?,6: the MAC inserts the content of the MAC Address 1..,7: the MAC replaces the content of the MAC Address.."
|
|
newline
|
|
bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times"
|
|
newline
|
|
bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "JD,Jabber Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "FES,MAC Speed" "0: 10 Mbps,1: 100 Mbps"
|
|
newline
|
|
bitfld.long 0x0 13. "DM,Duplex Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "LM,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-duplex mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DO,Disable Receive Own" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DR,Disable Retry" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "BL,Back-Off Limit" "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1)"
|
|
newline
|
|
bitfld.long 0x0 4. "DC,Deferral Check" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,3: Reserved must not be used"
|
|
newline
|
|
bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RE,Receiver Enable" "0,1"
|
|
line.long 0x4 "ETH_MACECR,Extended operating mode configuration register"
|
|
hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap"
|
|
newline
|
|
bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit"
|
|
line.long 0x8 "ETH_MACPFR,Packet filtering control register"
|
|
bitfld.long 0x8 31. "RA,Receive All" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.."
|
|
newline
|
|
bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1"
|
|
line.long 0xC "ETH_MACWTR,Watchdog timeout register"
|
|
bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout"
|
|
line.long 0x10 "ETH_MACHT0R,Hash Table 0 register"
|
|
hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits"
|
|
line.long 0x14 "ETH_MACHT1R,Hash Table 1 register"
|
|
hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "ETH_MACVTR,VLAN tag register"
|
|
bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
|
|
newline
|
|
bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
|
|
newline
|
|
bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VL,VLAN Tag Identifier for Receive Packets"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ETH_MACVHTR,VLAN Hash table register"
|
|
hexmask.long.word 0x0 0.--15. 1. "VLHT,VLAN Hash Table"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "ETH_MACVIR,VLAN inclusion register"
|
|
bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN"
|
|
newline
|
|
bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets"
|
|
line.long 0x4 "ETH_MACIVIR,Inner VLAN inclusion register"
|
|
bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN"
|
|
newline
|
|
bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "ETH_MACQTXFCR,Tx Queue flow control register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time"
|
|
newline
|
|
bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "ETH_MACRXFCR,Rx flow control register"
|
|
bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1"
|
|
group.long 0xB0++0xB
|
|
line.long 0x0 "ETH_MACISR,Interrupt status register"
|
|
bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1"
|
|
line.long 0x4 "ETH_MACIER,Interrupt enable register"
|
|
bitfld.long 0x4 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TSIE,Timestamp Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LPIIE,LPI Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PMTIE,PMT Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PHYIE,PHY Interrupt Enable" "0,1"
|
|
line.long 0x8 "ETH_MACRXTXSR,Rx Tx status register"
|
|
bitfld.long 0x8 8. "RWT,Receive Watchdog Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EXCOL,Excessive Collisions" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "LCOL,Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EXDEF,Excessive Deferral" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "LCARR,Loss of Carrier" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NCARR,No Carrier" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TJT,Transmit Jabber Timeout" "0,1"
|
|
group.long 0xC0++0x7
|
|
line.long 0x0 "ETH_MACPCSR,PMT control status register"
|
|
bitfld.long 0x0 31. "RWKFILTRST,Remote wakeup Packet Filter Register Pointer Reset" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote wakeup FIFO Pointer"
|
|
newline
|
|
bitfld.long 0x0 10. "RWKPFE,Remote wakeup Packet Forwarding Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "RWKPRCVD,Remote wakeup Packet Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RWKPKTEN,Remote wakeup Packet Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1"
|
|
line.long 0x4 "ETH_MACRWKPFR,Remote wakeup packet filter register"
|
|
hexmask.long 0x4 0.--31. 1. "MACRWKPFR,Remote wakeup packet filter"
|
|
group.long 0xD0++0xF
|
|
line.long 0x0 "ETH_MACLCSR,LPI control and status register"
|
|
bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LPITE,LPI Timer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PLS,PHY Link Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LPIEN,LPI Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 9. "RLPIST,Receive LPI State" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0,1"
|
|
line.long 0x4 "ETH_MACLTCR,LPI timers control register"
|
|
hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer"
|
|
line.long 0x8 "ETH_MACLETR,LPI entry timer register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "LPIET,LPI Entry Timer"
|
|
line.long 0xC "ETH_MAC1USTCR,One-microsecond-tick counter register"
|
|
hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1 s tick Counter"
|
|
rgroup.long 0x110++0x7
|
|
line.long 0x0 "ETH_MACVR,Version register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "USERVER,ST-defined version"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,IP version"
|
|
line.long 0x4 "ETH_MACDR,Debug register"
|
|
bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission"
|
|
newline
|
|
bitfld.long 0x4 16. "TPESTS,MAC MII Transmit Protocol Engine Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0. "RPESTS,MAC MII Receive Protocol Engine Status" "0,1"
|
|
rgroup.long 0x11C++0xF
|
|
line.long 0x0 "ETH_MACHWF0R,HW feature 0 register"
|
|
bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,?"
|
|
newline
|
|
bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "0: Reserved must not be used,1: Internal,2: External,3: Both"
|
|
newline
|
|
bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wakeup Packet Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HDSEL,Half-duplex Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support" "0,1"
|
|
line.long 0x4 "ETH_MACHWF1R,HW feature 1 register"
|
|
hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "0: No Hash table,1: 64,2: 128,3: 256"
|
|
newline
|
|
bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "AVSEL,AV Feature Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "DCBEN,DCB Feature Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "ADDR64,Address width" "0: 32 bits,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PTOEN,PTP Offload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size"
|
|
line.long 0x8 "ETH_MACHWF2R,HW feature 2 register"
|
|
bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors"
|
|
newline
|
|
hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels"
|
|
newline
|
|
hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues"
|
|
line.long 0xC "ETH_MACHWF3R,HW feature 3 register"
|
|
bitfld.long 0xC 5. "DVLAN,Double VLAN processing enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?,?"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "ETH_MACMDIOAR,MDIO address register"
|
|
bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range"
|
|
newline
|
|
bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "GOC,MII Operation Command" "0: Reserved must not be used,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read"
|
|
newline
|
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bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "MB,MII Busy" "0,1"
|
|
line.long 0x4 "ETH_MACMDIODR,MDIO data register"
|
|
hexmask.long.word 0x4 16.--31. 1. "RA,Register Address"
|
|
newline
|
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hexmask.long.word 0x4 0.--15. 1. "MD,MII Data"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "ETH_MACARPAR,ARP address register"
|
|
hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "ETH_MACCSRSWCR,CSR software control register"
|
|
bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1"
|
|
group.long 0x300++0x1F
|
|
line.long 0x0 "ETH_MACA0HR,MAC Address 0 high register"
|
|
rbitfld.long 0x0 31. "AE,Address Enable" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]"
|
|
line.long 0x4 "ETH_MACA0LR,MAC Address 0 low register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address x [31:0]"
|
|
line.long 0x8 "ETH_MACA1HR,MAC Address 1 high register"
|
|
bitfld.long 0x8 31. "AE,Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "SA,Source Address" "0: DA,1: SA"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]"
|
|
line.long 0xC "ETH_MACA1LR,MAC Address 1 low register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address x [31:0]"
|
|
line.long 0x10 "ETH_MACA2HR,MAC Address 2 high register"
|
|
bitfld.long 0x10 31. "AE,Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "SA,Source Address" "0: DA,1: SA"
|
|
newline
|
|
hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32]"
|
|
line.long 0x14 "ETH_MACA2LR,MAC Address 2 low register"
|
|
hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address x [31:0]"
|
|
line.long 0x18 "ETH_MACA3HR,MAC Address 3 high register"
|
|
bitfld.long 0x18 31. "AE,Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 30. "SA,Source Address" "0: DA,1: SA"
|
|
newline
|
|
hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32]"
|
|
line.long 0x1C "ETH_MACA3LR,MAC Address 3 low register"
|
|
hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address x [31:0]"
|
|
group.long 0x700++0x13
|
|
line.long 0x0 "ETH_MMC_CONTROL,MMC control register"
|
|
bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1"
|
|
line.long 0x4 "ETH_MMC_RX_INTERRUPT,MMC Rx interrupt register"
|
|
bitfld.long 0x4 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1"
|
|
line.long 0x8 "ETH_MMC_TX_INTERRUPT,MMC Tx interrupt register"
|
|
bitfld.long 0x8 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1"
|
|
line.long 0xC "ETH_MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register"
|
|
bitfld.long 0xC 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1"
|
|
line.long 0x10 "ETH_MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register"
|
|
bitfld.long 0x10 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x10 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask" "0,1"
|
|
rgroup.long 0x74C++0x7
|
|
line.long 0x0 "ETH_TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets register"
|
|
hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets"
|
|
line.long 0x4 "ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets register"
|
|
hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets"
|
|
rgroup.long 0x768++0x3
|
|
line.long 0x0 "ETH_TX_PACKET_COUNT_GOOD,Tx packet count good register"
|
|
hexmask.long 0x0 0.--31. 1. "TXPKTG,Tx Packet Count Good"
|
|
rgroup.long 0x794++0x7
|
|
line.long 0x0 "ETH_RX_CRC_ERROR_PACKETS,Rx CRC error packets register"
|
|
hexmask.long 0x0 0.--31. 1. "RXCRCERR,Rx CRC Error Packets"
|
|
line.long 0x4 "ETH_RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets register"
|
|
hexmask.long 0x4 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets"
|
|
rgroup.long 0x7C4++0x3
|
|
line.long 0x0 "ETH_RX_UNICAST_PACKETS_GOOD,Rx unicast packets good register"
|
|
hexmask.long 0x0 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good"
|
|
rgroup.long 0x7EC++0xF
|
|
line.long 0x0 "ETH_TX_LPI_USEC_CNTR,Tx LPI microsecond timer register"
|
|
hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter"
|
|
line.long 0x4 "ETH_TX_LPI_TRAN_CNTR,Tx LPI transition counter register"
|
|
hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter"
|
|
line.long 0x8 "ETH_RX_LPI_USEC_CNTR,Rx LPI microsecond counter register"
|
|
hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter"
|
|
line.long 0xC "ETH_RX_LPI_TRAN_CNTR,Rx LPI transition counter register"
|
|
hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter"
|
|
group.long 0x900++0x7
|
|
line.long 0x0 "ETH_MACL3L4C0R,L3 and L4 control 0 register"
|
|
bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA higher bits match"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA higher bits match"
|
|
newline
|
|
bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1"
|
|
line.long 0x4 "ETH_MACL4A0R,Layer4 Address filter 0 register"
|
|
hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field"
|
|
group.long 0x910++0xF
|
|
line.long 0x0 "ETH_MACL3A00R,Layer3 Address 0 filter 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field"
|
|
line.long 0x4 "ETH_MACL3A10R,Layer3 Address 1 filter 0 register"
|
|
hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field"
|
|
line.long 0x8 "ETH_MACL3A20R,Layer3 Address 2 filter 0 register"
|
|
hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field"
|
|
line.long 0xC "ETH_MACL3A30R,Layer3 Address 3 filter 0 register"
|
|
hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field"
|
|
group.long 0x930++0x7
|
|
line.long 0x0 "ETH_MACL3L4C1R,L3 and L4 control 1 register"
|
|
bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA higher bits match"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match"
|
|
newline
|
|
bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable" "0,1"
|
|
line.long 0x4 "ETH_MACL4A1R,Layer 4 address filter 1 register"
|
|
hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field"
|
|
group.long 0x940++0xF
|
|
line.long 0x0 "ETH_MACL3A01R,Layer3 address 0 filter 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field"
|
|
line.long 0x4 "ETH_MACL3A11R,Layer3 address 1 filter 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field"
|
|
line.long 0x8 "ETH_MACL3A21R,Layer3 address 2 filter 1 Register"
|
|
hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field"
|
|
line.long 0xC "ETH_MACL3A31R,Layer3 address 3 filter 1 register"
|
|
hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field"
|
|
group.long 0xB00++0x7
|
|
line.long 0x0 "ETH_MACTSCR,Timestamp control Register"
|
|
bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1"
|
|
line.long 0x4 "ETH_MACSSIR,Subsecond increment register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "SSINC,Subsecond Increment Value"
|
|
rgroup.long 0xB08++0x7
|
|
line.long 0x0 "ETH_MACSTSR,System time seconds register"
|
|
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second"
|
|
line.long 0x4 "ETH_MACSTNR,System time nanoseconds register"
|
|
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp subseconds"
|
|
group.long 0xB10++0xB
|
|
line.long 0x0 "ETH_MACSTSUR,System time seconds update register"
|
|
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds"
|
|
line.long 0x4 "ETH_MACSTNUR,System time nanoseconds update register"
|
|
bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp subseconds"
|
|
line.long 0x8 "ETH_MACTSAR,Timestamp addend register"
|
|
hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register"
|
|
group.long 0xB20++0x3
|
|
line.long 0x0 "ETH_MACTSSR,Timestamp status register"
|
|
hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots"
|
|
newline
|
|
bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier"
|
|
newline
|
|
bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1"
|
|
group.long 0xB30++0x3
|
|
line.long 0x0 "ETH_MACTXTSSNR,Tx timestamp status nanoseconds register"
|
|
rbitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1"
|
|
newline
|
|
hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low"
|
|
rgroup.long 0xB34++0x3
|
|
line.long 0x0 "ETH_MACTXTSSSR,Tx timestamp status seconds register"
|
|
hexmask.long 0x0 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High"
|
|
group.long 0xB40++0x3
|
|
line.long 0x0 "ETH_MACACR,Auxiliary control register"
|
|
bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1"
|
|
rgroup.long 0xB48++0x7
|
|
line.long 0x0 "ETH_MACATSNR,Auxiliary timestamp nanoseconds register"
|
|
hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp"
|
|
line.long 0x4 "ETH_MACATSSR,Auxiliary timestamp seconds register"
|
|
hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp"
|
|
group.long 0xB50++0xF
|
|
line.long 0x0 "ETH_MACTSIACR,Timestamp Ingress asymmetric correction register"
|
|
hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction"
|
|
line.long 0x4 "ETH_MACTSEACR,Timestamp Egress asymmetric correction register"
|
|
hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction"
|
|
line.long 0x8 "ETH_MACTSICNR,Timestamp Ingress correction nanosecond register"
|
|
hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction"
|
|
line.long 0xC "ETH_MACTSECNR,Timestamp Egress correction nanosecond register"
|
|
hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction"
|
|
group.long 0xB70++0x3
|
|
line.long 0x0 "ETH_MACPPSCR,PPS control register"
|
|
bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
|
|
newline
|
|
bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPS Output Frequency Control"
|
|
group.long 0xB70++0x3
|
|
line.long 0x0 "ETH_MACPPSCR_alternate,PPS control register"
|
|
bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
|
|
newline
|
|
bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PPSCMD,Flexible PPS Output (eth_ptp_pps_out) Control"
|
|
group.long 0xB80++0xF
|
|
line.long 0x0 "ETH_MACPPSTTSR,PPS target time seconds register"
|
|
hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register"
|
|
line.long 0x4 "ETH_MACPPSTTNR,PPS target time nanoseconds register"
|
|
bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register"
|
|
line.long 0x8 "ETH_MACPPSIR,PPS interval register"
|
|
hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval"
|
|
line.long 0xC "ETH_MACPPSWR,PPS width register"
|
|
hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width"
|
|
group.long 0xBC0++0x13
|
|
line.long 0x0 "ETH_MACPOCR,PTP Offload control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number"
|
|
newline
|
|
bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PTOEN,PTP Offload Enable" "0,1"
|
|
line.long 0x4 "ETH_MACSPI0R,PTP Source Port Identity 0 Register"
|
|
hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0"
|
|
line.long 0x8 "ETH_MACSPI1R,PTP Source port identity 1 register"
|
|
hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1"
|
|
line.long 0xC "ETH_MACSPI2R,PTP Source port identity 2 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2"
|
|
line.long 0x10 "ETH_MACLMIR,Log message interval register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval"
|
|
newline
|
|
bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,?,?,?,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval"
|
|
group.long 0xC00++0x3
|
|
line.long 0x0 "ETH_MTLOMR,Operating mode Register"
|
|
bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0,1"
|
|
rgroup.long 0xC20++0x3
|
|
line.long 0x0 "ETH_MTLISR,Interrupt status Register"
|
|
bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1"
|
|
group.long 0xD00++0x7
|
|
line.long 0x0 "ETH_MTLTXQOMR,Tx queue operating mode Register"
|
|
bitfld.long 0x0 16.--18. "TQS,Transmit queue size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
|
|
newline
|
|
rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?"
|
|
newline
|
|
bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1"
|
|
line.long 0x4 "ETH_MTLTXQUR,Tx queue underflow register"
|
|
bitfld.long 0x4 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--10. 1. "UFFRMCNT,Underflow Packet Counter"
|
|
rgroup.long 0xD08++0x3
|
|
line.long 0x0 "ETH_MTLTXQDR,Tx queue debug Register"
|
|
bitfld.long 0x0 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
|
|
newline
|
|
bitfld.long 0x0 0. "TXQPAUSED,Transmit Queue in Pause" "0,1"
|
|
group.long 0xD2C++0xB
|
|
line.long 0x0 "ETH_MTLQICSR,Queue interrupt control status Register"
|
|
bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1"
|
|
line.long 0x4 "ETH_MTLRXQOMR,Rx queue operating mode register"
|
|
rbitfld.long 0x4 20.--22. "RQS,Receive Queue Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128"
|
|
line.long 0x8 "ETH_MTLRXQMPOCR,Rx queue missed packet and overflow counter register"
|
|
bitfld.long 0x8 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 16.--26. 1. "MISPKTCNT,Missed Packet Counter"
|
|
newline
|
|
bitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter"
|
|
rgroup.long 0xD38++0x3
|
|
line.long 0x0 "ETH_MTLRXQDR,Rx queue debug register"
|
|
hexmask.long.word 0x0 16.--29. 1. "PRXQ,Number of Packets in Receive Queue"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
|
|
newline
|
|
bitfld.long 0x0 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "ETH_DMAMR,DMA mode register"
|
|
bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "PR,Priority ratio" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme" "0: Weighted Round-Robin with Rx:Tx or Tx:Rx,1: Fixed priority"
|
|
newline
|
|
bitfld.long 0x0 0. "SWR,Software Reset" "0,1"
|
|
line.long 0x4 "ETH_DMASBMR,System bus mode register"
|
|
rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1"
|
|
rgroup.long 0x1008++0x7
|
|
line.long 0x0 "ETH_DMAISR,Interrupt status register"
|
|
bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt Status" "0,1"
|
|
line.long 0x4 "ETH_DMADSR,Debug status register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process State"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process State"
|
|
newline
|
|
bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "ETH_DMACCR,Channel control register"
|
|
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size"
|
|
line.long 0x4 "ETH_DMACTXCR,Channel transmit control register"
|
|
hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1"
|
|
line.long 0x8 "ETH_DMACRXCR,Channel receive control register"
|
|
bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet Flush" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length"
|
|
newline
|
|
hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size"
|
|
newline
|
|
bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "ETH_DMACTXDLAR,Channel Tx descriptor list address register"
|
|
hexmask.long 0x0 0.--31. 1. "TDESLA,Start of Transmit List"
|
|
group.long 0x111C++0x7
|
|
line.long 0x0 "ETH_DMACRXDLAR,Channel Rx descriptor list address register"
|
|
hexmask.long 0x0 0.--31. 1. "RDESLA,Start of Receive List"
|
|
line.long 0x4 "ETH_DMACTXDTPR,Channel Tx descriptor tail pointer register"
|
|
hexmask.long 0x4 0.--31. 1. "TDT,Transmit Descriptor Tail Pointer"
|
|
group.long 0x1128++0x13
|
|
line.long 0x0 "ETH_DMACRXDTPR,Channel Rx descriptor tail pointer register"
|
|
hexmask.long 0x0 0.--31. 1. "RDT,Receive Descriptor Tail Pointer"
|
|
line.long 0x4 "ETH_DMACTXRLR,Channel Tx descriptor ring length register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length"
|
|
line.long 0x8 "ETH_DMACRXRLR,Channel Rx descriptor ring length register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "ARBS,Alternate Receive Buffer Size"
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length"
|
|
line.long 0xC "ETH_DMACIER,Channel interrupt enable register"
|
|
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: Transmit Interrupt,?"
|
|
newline
|
|
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: Transmit Process Stopped"
|
|
newline
|
|
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1"
|
|
line.long 0x10 "ETH_DMACRXIWTR,Channel Rx interrupt watchdog timer register"
|
|
bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count"
|
|
rgroup.long 0x1144++0x3
|
|
line.long 0x0 "ETH_DMACCATXDR,Channel current application transmit descriptor register"
|
|
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer"
|
|
rgroup.long 0x114C++0x3
|
|
line.long 0x0 "ETH_DMACCARXDR,Channel current application receive descriptor register"
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|
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer"
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rgroup.long 0x1154++0x3
|
|
line.long 0x0 "ETH_DMACCATXBR,Channel current application transmit buffer register"
|
|
hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer"
|
|
rgroup.long 0x115C++0x3
|
|
line.long 0x0 "ETH_DMACCARXBR,Channel current application receive buffer register"
|
|
hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer"
|
|
group.long 0x1160++0x3
|
|
line.long 0x0 "ETH_DMACSR,Channel status register"
|
|
rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7"
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|
newline
|
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rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: Transmit Interrupt,?"
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|
newline
|
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bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: Transmit Process Stopped"
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newline
|
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bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1"
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|
newline
|
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bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1"
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|
newline
|
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bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1"
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|
newline
|
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bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1"
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|
newline
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bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1"
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newline
|
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bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1"
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|
group.long 0x116C++0x3
|
|
line.long 0x0 "ETH_DMACMFCR,Channel missed frame count register"
|
|
bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters"
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|
tree.end
|
|
tree "EXTI (External Interrupt/Event Controller)"
|
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base ad:0x58000000
|
|
group.long 0x0++0x37
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line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register"
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bitfld.long 0x0 21. "TR21,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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bitfld.long 0x0 20. "TR20,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
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bitfld.long 0x0 19. "TR19,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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bitfld.long 0x0 18. "TR18,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
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bitfld.long 0x0 17. "TR17,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
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bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
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bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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newline
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bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
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bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
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bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
newline
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
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|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
newline
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
newline
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit of configurable event input x." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register"
|
|
bitfld.long 0x4 21. "TR21,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 20. "TR20,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 19. "TR19,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 18. "TR18,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 17. "TR17,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 16. "TR16,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 15. "TR15,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 14. "TR14,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 13. "TR13,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 12. "TR12,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 11. "TR11,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 10. "TR10,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 9. "TR9,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 8. "TR8,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 7. "TR7,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 6. "TR6,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 5. "TR5,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 4. "TR4,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 3. "TR3,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 2. "TR2,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x4 1. "TR1,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x4 0. "TR0,Falling trigger event configuration bit of configurable event input x." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register"
|
|
bitfld.long 0x8 21. "SWIER21,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 20. "SWIER20,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 19. "SWIER19,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 18. "SWIER18,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 17. "SWIER17,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 16. "SWIER16,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 15. "SWIER15,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 14. "SWIER14,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 13. "SWIER13,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 12. "SWIER12,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 11. "SWIER11,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 10. "SWIER10,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 9. "SWIER9,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 8. "SWIER8,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 7. "SWIER7,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 6. "SWIER6,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 5. "SWIER5,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 4. "SWIER4,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 3. "SWIER3,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 2. "SWIER2,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x8 1. "SWIER1,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x8 0. "SWIER0,Software interrupt on line x" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
line.long 0xC "EXTI_RTSR2,EXTI rising trigger selection register"
|
|
bitfld.long 0xC 22. "TR54,Rising trigger event configuration bit of configurable event input x+32." "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
bitfld.long 0xC 19. "TR51,Rising trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
newline
|
|
bitfld.long 0xC 17. "TR49,Rising trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
bitfld.long 0xC 14. "TR46,Rising trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
newline
|
|
bitfld.long 0xC 2. "TR34,Rising trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Rising trigger disabled (for event and..,1: Rising trigger enabled (for event and interrupt).."
|
|
line.long 0x10 "EXTI_FTSR2,EXTI falling trigger selection register"
|
|
bitfld.long 0x10 22. "TR54,Falling trigger event configuration bit of configurable event input x+32." "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x10 19. "TR51,Falling trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x10 17. "TR49,Falling trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
bitfld.long 0x10 14. "TR46,Falling trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
newline
|
|
bitfld.long 0x10 2. "TR34,Falling trigger event configuration bit of configurable event input x+32.<sup>(1)</sup>" "0: Falling trigger disabled (for event and..,1: Falling trigger enabled (for event and.."
|
|
line.long 0x14 "EXTI_SWIER2,EXTI software interrupt event register"
|
|
bitfld.long 0x14 22. "SWIER54,Software interrupt on line x+32" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x14 19. "SWIER51,Software interrupt on line x+32" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x14 17. "SWIER49,Software interrupt on line x+32" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
bitfld.long 0x14 14. "SWIER46,Software interrupt on line x+32" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
newline
|
|
bitfld.long 0x14 2. "SWIER34,Software interrupt on line x+32" "0: Writing 0 has no effect.,1: Writing a 1 to this bit triggers an event on.."
|
|
line.long 0x18 "EXTI_IMR1,EXTI interrupt mask register"
|
|
bitfld.long 0x18 31. "MR31,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 30. "MR30,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 29. "MR29,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 28. "MR28,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 27. "MR27,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 26. "MR26,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 25. "MR25,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 24. "MR24,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 23. "MR23,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 22. "MR22,CPU interrupt mask on direct event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 21. "MR21,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 20. "MR20,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 19. "MR19,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 18. "MR18,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 17. "MR17,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 16. "MR16,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 15. "MR15,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 14. "MR14,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 13. "MR13,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 12. "MR12,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 11. "MR11,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 10. "MR10,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 9. "MR9,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 8. "MR8,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 7. "MR7,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 6. "MR6,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 5. "MR5,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 4. "MR4,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x18 3. "MR3,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 2. "MR2,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
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bitfld.long 0x18 1. "MR1,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x18 0. "MR0,CPU interrupt mask on configurable event input x" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
line.long 0x1C "EXTI_EMR1,EXTI event mask register"
|
|
bitfld.long 0x1C 31. "MR31,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 30. "MR30,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 29. "MR29,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 28. "MR28,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 27. "MR27,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 26. "MR26,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 25. "MR25,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 24. "MR24,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 23. "MR23,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 22. "MR22,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 21. "MR21,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 20. "MR20,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 19. "MR19,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 18. "MR18,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 17. "MR17,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 16. "MR16,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 15. "MR15,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 14. "MR14,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 13. "MR13,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 12. "MR12,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 11. "MR11,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 10. "MR10,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 9. "MR9,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 8. "MR8,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 7. "MR7,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 6. "MR6,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 5. "MR5,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 4. "MR4,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 3. "MR3,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 2. "MR2,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x1C 1. "MR1,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
bitfld.long 0x1C 0. "MR0,CPU event mask on event input x" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
line.long 0x20 "EXTI_PR1,EXTI pending register"
|
|
bitfld.long 0x20 21. "PR21,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 20. "PR20,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 19. "PR19,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 18. "PR18,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 17. "PR17,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 16. "PR16,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 15. "PR15,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 14. "PR14,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 13. "PR13,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 12. "PR12,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 11. "PR11,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 10. "PR10,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 9. "PR9,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 8. "PR8,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 7. "PR7,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 6. "PR6,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 5. "PR5,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 4. "PR4,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 3. "PR3,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 2. "PR2,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x20 1. "PR1,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x20 0. "PR0,Configurable event inputs x Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
line.long 0x24 "EXTI_IMR2,EXTI interrupt mask register"
|
|
bitfld.long 0x24 27. "MR59,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 26. "MR58,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 25. "MR57,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 24. "MR56,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 23. "MR55,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 22. "MR54,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 21. "MR53,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 20. "MR52,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 19. "MR51,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 18. "MR50,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 17. "MR49,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 16. "MR48,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 15. "MR47,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 14. "MR46,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 13. "MR45,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 12. "MR44,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 11. "MR43,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 10. "MR42,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 9. "MR41,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 8. "MR40,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 7. "MR39,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 6. "MR38,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 5. "MR37,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 4. "MR36,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 3. "MR35,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 2. "MR34,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
newline
|
|
bitfld.long 0x24 1. "MR33,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
bitfld.long 0x24 0. "MR32,CPU interrupt mask on direct event input i" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
line.long 0x28 "EXTI_EMR2,EXTI event mask register"
|
|
bitfld.long 0x28 27. "MR59,CPU event mask on event input i" "0: Event request from line 59 is masked,1: Event request from line 59 is unmasked"
|
|
bitfld.long 0x28 26. "MR58,CPU event mask on event input i" "0: Event request from line 58 is masked,1: Event request from line 58 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 25. "MR57,CPU event mask on event input i" "0: Event request from line 57 is masked,1: Event request from line 57 is unmasked"
|
|
bitfld.long 0x28 24. "MR56,CPU event mask on event input i" "0: Event request from line 56 is masked,1: Event request from line 56 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 23. "MR55,CPU event mask on event input i" "0: Event request from line 55 is masked,1: Event request from line 55 is unmasked"
|
|
bitfld.long 0x28 22. "MR54,CPU event mask on event input i" "0: Event request from line 54 is masked,1: Event request from line 54 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 21. "MR53,CPU event mask on event input i" "0: Event request from line 53 is masked,1: Event request from line 53 is unmasked"
|
|
bitfld.long 0x28 20. "MR52,CPU event mask on event input i" "0: Event request from line 52 is masked,1: Event request from line 52 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 19. "MR51,CPU event mask on event input i" "0: Event request from line 51 is masked,1: Event request from line 51 is unmasked"
|
|
bitfld.long 0x28 18. "MR50,CPU event mask on event input i" "0: Event request from line 50 is masked,1: Event request from line 50 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 17. "MR49,CPU event mask on event input i" "0: Event request from line 49 is masked,1: Event request from line 49 is unmasked"
|
|
bitfld.long 0x28 16. "MR48,CPU event mask on event input i" "0: Event request from line 48 is masked,1: Event request from line 48 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 15. "MR47,CPU event mask on event input i" "0: Event request from line 47 is masked,1: Event request from line 47 is unmasked"
|
|
bitfld.long 0x28 14. "MR46,CPU event mask on event input i" "0: Event request from line 46 is masked,1: Event request from line 46 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 13. "MR45,CPU event mask on event input i" "0: Event request from line 45 is masked,1: Event request from line 45 is unmasked"
|
|
bitfld.long 0x28 12. "MR44,CPU event mask on event input i" "0: Event request from line 44 is masked,1: Event request from line 44 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 11. "MR43,CPU event mask on event input i" "0: Event request from line 43 is masked,1: Event request from line 43 is unmasked"
|
|
bitfld.long 0x28 10. "MR42,CPU event mask on event input i" "0: Event request from line 42 is masked,1: Event request from line 42 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 9. "MR41,CPU event mask on event input i" "0: Event request from line 41 is masked,1: Event request from line 41 is unmasked"
|
|
bitfld.long 0x28 8. "MR40,CPU event mask on event input i" "0: Event request from line 40 is masked,1: Event request from line 40 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 7. "MR39,CPU event mask on event input i" "0: Event request from line 39 is masked,1: Event request from line 39 is unmasked"
|
|
bitfld.long 0x28 6. "MR38,CPU event mask on event input i" "0: Event request from line 38 is masked,1: Event request from line 38 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 5. "MR37,CPU event mask on event input i" "0: Event request from line 37 is masked,1: Event request from line 37 is unmasked"
|
|
bitfld.long 0x28 4. "MR36,CPU event mask on event input i" "0: Event request from line 36 is masked,1: Event request from line 36 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 3. "MR35,CPU event mask on event input i" "0: Event request from line 35 is masked,1: Event request from line 35 is unmasked"
|
|
bitfld.long 0x28 2. "MR34,CPU event mask on event input i" "0: Event request from line 34 is masked,1: Event request from line 34 is unmasked"
|
|
newline
|
|
bitfld.long 0x28 1. "MR33,CPU event mask on event input i" "0: Event request from line 33 is masked,1: Event request from line 33 is unmasked"
|
|
bitfld.long 0x28 0. "MR32,CPU event mask on event input i" "0: Event request from line 32 is masked,1: Event request from line 32 is unmasked"
|
|
line.long 0x2C "EXTI_PR2,EXTI pending register"
|
|
bitfld.long 0x2C 22. "PR54,Configurable event inputs x+32 Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x2C 19. "PR51,Configurable event inputs x+32 Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x2C 17. "PR49,Configurable event inputs x+32 Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
bitfld.long 0x2C 14. "PR46,Configurable event inputs x+32 Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
newline
|
|
bitfld.long 0x2C 2. "PR34,Configurable event inputs x+32 Pending bit" "0: No trigger request occurred,1: selected trigger request occurred"
|
|
line.long 0x30 "EXTI_IMR3,EXTI interrupt mask register"
|
|
bitfld.long 0x30 13. "MR77,CPU interrupt mask on direct event input x+64" "0: Interrupt request from line x is masked,1: Interrupt request from line x is unmasked"
|
|
line.long 0x34 "EXTI_EMR3,EXTI event mask register"
|
|
bitfld.long 0x34 13. "MR77,CPU event mask on event input x+64" "0: Event request from line x is masked,1: Event request from line x is unmasked"
|
|
tree.end
|
|
tree "FDCAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "FDCAN1"
|
|
base ad:0x4000A000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
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bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
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rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
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|
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bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN Timestamp Counter Value Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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|
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN Timeout Counter Value Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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|
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
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|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
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rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
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line.long 0x8 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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|
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
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|
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
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|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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|
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bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
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|
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|
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
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|
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|
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
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|
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
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|
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bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
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bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
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|
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
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|
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
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bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
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line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN Extended ID and Mask Register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
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bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status Register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
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bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx Buffer Configuration Register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
tree "FDCAN2"
|
|
base ad:0x4000A400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register"
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hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
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group.long 0xC++0x23
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line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
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|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
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|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
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|
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
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line.long 0x4 "FDCAN_TEST,FDCAN test register"
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rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
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bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
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line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
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line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
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bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
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bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
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bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
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bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
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bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
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bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
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newline
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rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
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bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
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bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
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line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
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hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
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hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
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hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
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line.long 0x14 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration Register"
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hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
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bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
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line.long 0x18 "FDCAN_TSCV,FDCAN Timestamp Counter Value Register"
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hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
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line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
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hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
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bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
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line.long 0x20 "FDCAN_TOCV,FDCAN Timeout Counter Value Register"
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hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
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group.long 0x40++0xB
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line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register"
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
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rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
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hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
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line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register"
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
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bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
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bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
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rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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newline
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
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line.long 0x8 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation Register"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
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|
group.long 0x50++0xF
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line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
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bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
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newline
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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newline
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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newline
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
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bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
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newline
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
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bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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newline
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bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
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bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
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newline
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
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bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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newline
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bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
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newline
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
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bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
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bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
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newline
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
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bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
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bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
|
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bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
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newline
|
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bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
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bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
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bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
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bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
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bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
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newline
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
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bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
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newline
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
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bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
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newline
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
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line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
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bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
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bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
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group.long 0x80++0x7
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line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
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hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
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hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
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newline
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
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bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
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newline
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
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bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
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newline
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
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|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
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line.long 0x4 "FDCAN_XIDAM,FDCAN Extended ID and Mask Register"
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hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
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rgroup.long 0x88++0x3
|
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line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
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bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
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hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
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newline
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bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
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bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x90++0x3
|
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line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status Register"
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|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
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|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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newline
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
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bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x98++0x3
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line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status Register"
|
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bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
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newline
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bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
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newline
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hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx Buffer Configuration Register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
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|
newline
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bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
tree.end
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x52002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLASH_ACR,Access control register"
|
|
bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "FLASH_KEYR,FLASH control key register"
|
|
hexmask.long 0x0 0.--31. 1. "CUKEY,Control unlock key"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FLASH_CR,FLASH control register"
|
|
bitfld.long 0x0 24. "ALL_BANKS,All banks select bit" "0,1"
|
|
bitfld.long 0x0 17. "CRC_EN,CRC enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PG_OTP,Program Enable for OTP Area" "0,1"
|
|
bitfld.long 0x0 6.--7. "SSN,Sector erase selection number" "0: Sector 0,1: Sector 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 5. "START,Erase start control bit" "0,1"
|
|
bitfld.long 0x0 4. "FW,Force write" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BER,Bank erase request" "0: Bank erase is not requested,1: Bank erase is requested. Actual erase is started.."
|
|
bitfld.long 0x0 2. "SER,Sector erase request" "0: Sector erase not requested,1: Sector erase requested"
|
|
newline
|
|
bitfld.long 0x0 1. "PG,Internal buffer control bit" "0: Internal buffer disabled for write operations,1: Internal buffer enabled for write operations"
|
|
bitfld.long 0x0 0. "LOCK,Configuration lock bit" "0: FLASH_CR and FLASH_IER registers are unlocked,1: Writes to FLASH_IER and to other bits than LOCK.."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "FLASH_SR,FLASH status register"
|
|
bitfld.long 0x0 25. "RCHECKF,Root code check flag" "0: Root code check is fail. Reads to Flash returns..,1: Root code check is pass."
|
|
bitfld.long 0x0 6. "IS_OPTCHANGE,Is an option change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IS_ERASE,Is an erase" "0,1"
|
|
bitfld.long 0x0 4. "IS_PROGRAM,Is a program" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRC_BUSY,CRC busy flag" "0: No CRC calculation ongoing,1: CRC calculation ongoing"
|
|
bitfld.long 0x0 2. "QW,Wait queue flag" "0: No write erase or option byte change operations..,1: At least one write erase or option byte change.."
|
|
newline
|
|
bitfld.long 0x0 1. "WBNE,Write buffer not empty flag" "0: Write buffer empty or full,1: Write buffer waiting data to complete"
|
|
bitfld.long 0x0 0. "BUSY,Busy flag" "0: No programming erase or option byte change..,1: Programming erase or option byte change.."
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "FLASH_FCR,FLASH status register"
|
|
bitfld.long 0x0 25. "RCHECKF,Root code check flag clear" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLASH_IER,FLASH interrupt enable register"
|
|
bitfld.long 0x0 28. "CRCRDERRIE,CRC read error interrupt enable bit" "0: No interrupt is generated when CRCRDERRF bit is..,1: An interrupt is generated when CRCRDERRF bit is.."
|
|
bitfld.long 0x0 27. "CRCENDIE,CRC end of calculation interrupt enable bit" "0: No interrupt is generated when CRCEN bit is set..,1: An interrupt is generated when CRCEN bit is set.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBECCERRIE,ECC double detection error interrupt enable bit" "0: No interrupt is generated when DBECCERRF bit is..,1: An interrupt is generated when DBECCERRF bit is.."
|
|
bitfld.long 0x0 25. "SNECCERRIE,ECC single correction error interrupt enable bit" "0: No interrupt is generated when SNECCERRF bit is..,1: An interrupt is generated when SNECCERRF bit is.."
|
|
newline
|
|
bitfld.long 0x0 24. "RDSERRIE,Read security error interrupt enable bit" "0: No interrupt is generated when RDSERRF bit is..,1: An interrupt is generated when RDSERRF bit is.."
|
|
bitfld.long 0x0 21. "INCERRIE,Inconsistency error interrupt enable bit" "0: No interrupt is generated when INCERRF bit is..,1: An interrupt is generated when INCERRF bit is.."
|
|
newline
|
|
bitfld.long 0x0 20. "OBLERRIE,Option byte loading error interrupt enable bit" "0: No interrupt is generated when OBLERRF bit is..,1: An interrupt is generated when OBLERRF bit is.."
|
|
bitfld.long 0x0 19. "STRBERRIE,Strobe error interrupt enable bit" "0: No interrupt is generated when STRBERRF bit is..,1: An interrupt is generated when STRBERRF bit is.."
|
|
newline
|
|
bitfld.long 0x0 18. "PGSERRIE,Programming sequence error interrupt enable bit" "0: No interrupt is generated when PGSERRF bit is..,1: An interrupt is generated when PGSERRF bit is.."
|
|
bitfld.long 0x0 17. "WRPERRIE,Write protection error interrupt enable bit" "0: No interrupt is generated when WRPERRF bit is..,1: An interrupt is generated when WRPERRF bit is.."
|
|
newline
|
|
bitfld.long 0x0 16. "EOPIE,End-of-program interrupt control bit" "0: No interrupt is generated when OEPF bit is set..,1: An interrupt is generated when OEPF bit is set.."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "FLASH_ISR,FLASH interrupt status register"
|
|
bitfld.long 0x0 28. "CRCRDERRF,CRC read error flag" "0: No protected area detected inside addresses read..,1: At least one protected area has been detected.."
|
|
bitfld.long 0x0 27. "CRCENDF,CRC end flag" "0: CRC computation not complete,1: CRC computation complete"
|
|
newline
|
|
bitfld.long 0x0 26. "DBECCERRF,ECC double error flag" "0: No ECC double detection error occurred,1: ECC double detection error occurred"
|
|
bitfld.long 0x0 25. "SNECCERRF,ECC single error flag" "0: No ECC single correction error occurred,1: ECC single correction error occurred"
|
|
newline
|
|
bitfld.long 0x0 24. "RDSERRF,Read security error flag" "0: No security error occurred,1: A security error occurred"
|
|
bitfld.long 0x0 21. "INCERRF,Inconsistency error flag" "0: No inconsistency error occurred,1: A inconsistency error occurred"
|
|
newline
|
|
bitfld.long 0x0 20. "OBLERRF,Option byte loading error flag" "0: No error found during option byte loading sequence,1: Some errors found during option byte loading.."
|
|
bitfld.long 0x0 19. "STRBERRF,Strobe error flag" "0: No strobe error occurred,1: Astrobe error occurred"
|
|
newline
|
|
bitfld.long 0x0 18. "PGSERRF,Programming sequence error flag" "0: No sequence error occurred,1: Asequence error occurred"
|
|
bitfld.long 0x0 17. "WRPERRF,Write protection error flag" "0: No write protection error occurred,1: A write protection error occurred"
|
|
newline
|
|
bitfld.long 0x0 16. "EOPF,End-of-program flag" "0: No programming operation completed,1: A programming operation completed"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "FLASH_ICR,FLASH interrupt clear register"
|
|
bitfld.long 0x0 28. "CRCRDERRF,CRC error flag clear" "0,1"
|
|
bitfld.long 0x0 27. "CRCENDF,CRC end flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DBECCERRF,ECC double error flag clear" "0,1"
|
|
bitfld.long 0x0 25. "SNECCERRF,ECC single error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RDSERRF,Read security error flag clear" "0,1"
|
|
bitfld.long 0x0 21. "INCERRF,Inconsistency error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "OBLERRF,Option byte loading error flag clear" "0,1"
|
|
bitfld.long 0x0 19. "STRBERRF,Strobe error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PGSERRF,Programming sequence error flag clear" "0,1"
|
|
bitfld.long 0x0 17. "WRPERRF,Write protection error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EOPF,End-of-program flag clear" "0,1"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "FLASH_CRCCR,FLASH CRC control register"
|
|
bitfld.long 0x0 24. "ALL_SECT,All sectors selection" "0,1"
|
|
bitfld.long 0x0 20.--21. "CRC_BURST,CRC burst size" "0: every burst has a size of 4 Flash words (64 Bytes),1: every burst has a size of 16 Flash words (256..,2: every burst has a size of 64 Flash words (1..,3: every burst has a size of 256 Flash words (4.."
|
|
newline
|
|
bitfld.long 0x0 17. "CLEAN_CRC,CRC clear bit" "0,1"
|
|
bitfld.long 0x0 16. "START_CRC,CRC start bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CLEAN_SECT,CRC sector list clear bit" "0,1"
|
|
bitfld.long 0x0 10. "ADD_SECT,CRC sector select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CRC_BY_SECT,CRC sector mode select bit" "0,1"
|
|
bitfld.long 0x0 0.--1. "CRC_SECT,CRC sector number" "0: sector 0 for CRC,1: sector 1 for CRC,?,?"
|
|
line.long 0x4 "FLASH_CRCSADDR,FLASH CRC start address register"
|
|
hexmask.long.word 0x4 6.--16. 1. "CRC_START_ADDR,CRC start address"
|
|
line.long 0x8 "FLASH_CRCEADDR,FLASH CRC end address register"
|
|
hexmask.long.word 0x8 6.--16. 1. "CRC_END_ADDR,CRC end address"
|
|
rgroup.long 0x3C++0xB
|
|
line.long 0x0 "FLASH_CRCDATAR,FLASH CRC data register"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_DATA,CRC result"
|
|
line.long 0x4 "FLASH_ECCSFADDR,FLASH ECC single error fail address"
|
|
hexmask.long 0x4 0.--31. 1. "SEC_FADD,ECC single error correction fail address"
|
|
line.long 0x8 "FLASH_ECCDFADDR,FLASH ECC double error fail address"
|
|
hexmask.long 0x8 0.--31. 1. "DED_FADD,ECC double error detection fail address"
|
|
wgroup.long 0x100++0x3
|
|
line.long 0x0 "FLASH_OPTKEYR,FLASH options key register"
|
|
hexmask.long 0x0 0.--31. 1. "OCUKEY,Options configuration unlock key"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "FLASH_OPTCR,FLASH options control register"
|
|
bitfld.long 0x0 30. "OPTERRIE,Option byte change error interrupt enable bit" "0: no interrupt is generated when an error occurs..,1: an interrupt is generated when and error occurs.."
|
|
bitfld.long 0x0 28. "KTEIE,Key transfer error interrupt enable bit" "0: no interrupt is generated when a key transfer..,1: an interrupt is generated when a key transfer.."
|
|
newline
|
|
bitfld.long 0x0 27. "KVEIE,Key valid error interrupt enable bit" "0: no interrupt is generated when a key valid error..,1: an interrupt is generated when a key valid error.."
|
|
bitfld.long 0x0 1. "PG_OPT,Program options" "0: Update operations to user option bytes and..,1: Write operation to user option bytes and option.."
|
|
newline
|
|
bitfld.long 0x0 0. "OPTLOCK,Options lock" "0: OTP words FLASH_OPTCR FLASH_OBKCR and..,1: Writes to OTP words FLASH_OBKCR FLASH_xxSRP and.."
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x0 "FLASH_OPTISR,FLASH options interrupt status register"
|
|
bitfld.long 0x0 30. "OPTERRF,Option byte change error flag" "0: No option byte change errors occurred,1: One or more errors occurred during an option.."
|
|
bitfld.long 0x0 28. "KTEF,Key transfer error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "KVEF,Key valid error flag" "0,1"
|
|
wgroup.long 0x10C++0x3
|
|
line.long 0x0 "FLASH_OPTICR,FLASH options interrupt clear register"
|
|
bitfld.long 0x0 30. "OPTERRF,Option byte change error flag" "0,1"
|
|
bitfld.long 0x0 28. "KTEF,key transfer error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "KVEF,key valid error flag" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "FLASH_OBKCR,FLASH option byte key control register"
|
|
bitfld.long 0x0 15. "KEYSTART,Key option start" "0,1"
|
|
bitfld.long 0x0 14. "KEYPROG,Key program" "0: Read key. Result of the operation is stored in..,1: Program key if PG_OPT is set in FLASH_OPTCR.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "OBKSIZE,Option byte key size" "0: Key size is 32 bits,1: Key size is 64 bits,2: Key size is 128 bits,3: Key size is 256 bits"
|
|
bitfld.long 0x0 8.--9. "NEXTKL,Next key level" "0: OBKINDEX represents the index of the option byte..,1: OBKINDEX represents the index of the option byte..,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "OBKINDEX,Option byte key index"
|
|
group.long 0x118++0x1F
|
|
line.long 0x0 "FLASH_OBKDR0,FLASH option bytes key data register 0"
|
|
hexmask.long 0x0 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0x4 "FLASH_OBKDR1,FLASH option bytes key data register 1"
|
|
hexmask.long 0x4 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0x8 "FLASH_OBKDR2,FLASH option bytes key data register 2"
|
|
hexmask.long 0x8 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0xC "FLASH_OBKDR3,FLASH option bytes key data register 3"
|
|
hexmask.long 0xC 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0x10 "FLASH_OBKDR4,FLASH option bytes key data register 4"
|
|
hexmask.long 0x10 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0x14 "FLASH_OBKDR5,FLASH option bytes key data register 5"
|
|
hexmask.long 0x14 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0x18 "FLASH_OBKDR6,FLASH option bytes key data register 6"
|
|
hexmask.long 0x18 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
line.long 0x1C "FLASH_OBKDR7,FLASH option bytes key data register 7"
|
|
hexmask.long 0x1C 0.--31. 1. "OBKDATA,option byte key data bits [31+x:0+x]"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "FLASH_NVSR,FLASH non-volatile status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NVSTATE,Non-volatile state"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLASH_NVSRP,FLASH security status register programming"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NVSTATE,Non-volatile state programming"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "FLASH_ROTSR,FLASH RoT status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IROT_SELECT,iRoT selection"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DBG_AUTH,Debug authentication method"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "OEM_PROVD,OEM provisioned device"
|
|
group.long 0x20C++0x3
|
|
line.long 0x0 "FLASH_ROTSRP,FLASH RoT status register programming"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IROT_SELECT,iRoT selection"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DBG_AUTH,Debug authentication method programming"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "OEM_PROVD,OEM provisioned device"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLASH_OTPLSR,FLASH OTP lock status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "OTPL,OTP lock n"
|
|
group.long 0x214++0xB
|
|
line.long 0x0 "FLASH_OTPLSRP,FLASH OTP lock status register programming"
|
|
hexmask.long.word 0x0 0.--15. 1. "OTPL,OTP lock n programming"
|
|
line.long 0x4 "FLASH_WRPSR,FLASH write protection status register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "WRPS,Write protection for sector n"
|
|
line.long 0x8 "FLASH_WRPSRP,FLASH write protection status register programming"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WRPS,Write protection for sector n programming"
|
|
rgroup.long 0x230++0x3
|
|
line.long 0x0 "FLASH_HDPSR,FLASH hide protection status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "HDP_AREA_END,Hide protection user Flash area end"
|
|
hexmask.long.word 0x0 0.--8. 1. "HDP_AREA_START,Hide protection user Flash area start"
|
|
group.long 0x234++0x3
|
|
line.long 0x0 "FLASH_HDPSRP,FLASH hide protection status register programming"
|
|
hexmask.long.word 0x0 16.--24. 1. "HDP_AREA_END,Hide protection user Flash area end programming"
|
|
hexmask.long.word 0x0 0.--8. 1. "HDP_AREA_START,Hide protection user Flash area start programming"
|
|
rgroup.long 0x250++0x3
|
|
line.long 0x0 "FLASH_EPOCHSR,FLASH epoch status register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "EPOCH,Epoch"
|
|
group.long 0x254++0x3
|
|
line.long 0x0 "FLASH_EPOCHSRP,FLASH RoT status register programming"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "EPOCH,Epoch programming"
|
|
rgroup.long 0x260++0x3
|
|
line.long 0x0 "FLASH_OBW1SR,FLASH option byte word 1 status register"
|
|
bitfld.long 0x0 29. "VDDIO_HSLV,I/O High-Speed at Low-Voltage" "0: Product working in the full voltage range I/O..,1: Product operating below 2.5 V I/O speed.."
|
|
bitfld.long 0x0 28. "PERSO_OK,Personalization OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "IWDG_FZ_SDBY,IWDG standby mode freeze" "0: Independent watchdog frozen in Standby mode,1: Independent watchdog keep running in Standby mode"
|
|
bitfld.long 0x0 17. "IWDG_FZ_STOP,IWDG stop mode freeze" "0: Independent watchdog frozen in Stop mode,1: Independent watchdog keep running in Stop mode"
|
|
newline
|
|
bitfld.long 0x0 9. "OCTO2_HSLV,XSPIM_P2 High-Speed at Low-Voltage" "0: I/O XSPIM_P2 High-Speed option disabled,1: I/O XSPIM_P2 High-Speed option enabled"
|
|
bitfld.long 0x0 8. "OCTO1_HSLV,XSPIM_P1 High-Speed at Low-Voltage" "0: I/O XSPIM_P1 High-Speed option disabled,1: I/O XSPIM_P1 High-Speed option enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "NRST_STBY,Reset on standby mode" "0: Independent WDG generates a reset if STANDBY..,1: Independent WDG does not generate a reset if.."
|
|
bitfld.long 0x0 6. "NRST_STOP,Reset on stop mode" "0: Independent WDG generates a reset if STOP mode..,1: Independent WDG does not generate a reset if.."
|
|
newline
|
|
bitfld.long 0x0 4. "IWDG_HW,Independent watchdog HW Control" "0: IWDG watchdog is controller by hardware,1: IWDG watchdog is controlled by software"
|
|
bitfld.long 0x0 2.--3. "BOR_LEV,Brownout level" "0: BOR OFF POR/PDR reset threshold level is applied,1: BOR Level 1 the threshold level is low (around..,2: BOR Level 2 the threshold level is medium..,3: BOR Level 3 the threshold level is high (around.."
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "FLASH_OBW1SRP,FLASH option byte word 1 status register programming"
|
|
bitfld.long 0x0 29. "VDDIO_HSLV,I/O High-Speed at Low-Voltage programming" "0,1"
|
|
bitfld.long 0x0 18. "IWDG_FZ_SDBY,IWDG standby mode freeze programming" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "IWDG_FZ_STOP,IWDG stop mode freeze" "0,1"
|
|
bitfld.long 0x0 9. "OCTO2_HSLV,XSPIM_P2 High-Speed at Low-Voltage programming" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OCTO1_HSLV,XSPIM_P1 High-Speed at Low-Voltage" "0,1"
|
|
bitfld.long 0x0 7. "NRST_STBY,Reset on standby mode programming" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "NRST_STOP,Reset on stop mode programming" "0,1"
|
|
bitfld.long 0x0 4. "IWDG_HW,Independent watchdog HW Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "BOR_LEV,Brownout level" "0,1,2,3"
|
|
rgroup.long 0x268++0x3
|
|
line.long 0x0 "FLASH_OBW2SR,FLASH option byte word 2 status register"
|
|
bitfld.long 0x0 9. "I2C_NI3C,I2C Not I3C" "0: I3C is selected,1: I2C is selected"
|
|
bitfld.long 0x0 8. "ECC_ON_SRAM,ECC on SRAM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DTCM_AXI_SHARE,DTCM SRAM configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "ITCM_AXI_SHARE,ITCM SRAM configuration" "0,1,2,3,4,5,6,7"
|
|
group.long 0x26C++0x3
|
|
line.long 0x0 "FLASH_OBW2SRP,FLASH option byte word 2 status register programming"
|
|
bitfld.long 0x0 9. "I2C_NI3C,I2C Not I3C" "0,1"
|
|
bitfld.long 0x0 8. "ECC_ON_SRAM,ECC on SRAM programming" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DTCM_AXI_SHARE,DTCM AXI share programming" "0: DTCM_AXI_SHARE = 000 or,1: DTCM 128 Kbytes,?,?,?,?,?,?"
|
|
bitfld.long 0x0 0.--2. "ITCM_AXI_SHARE,ITCM AXI share programming" "0: ITCM_AXI_SHARE: = 000 or,1: ITCM 128 Kbytes,?,?,?,?,?,?"
|
|
tree.end
|
|
tree "FMC (Flexible Memory Controller)"
|
|
base ad:0x52004000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "FMC_BCR1,SRAM/NOR-flash chip-select control registers for bank 1"
|
|
bitfld.long 0x0 31. "FMCEN,FMC Enable" "0: Disable the FMC,1: Enable the FMC"
|
|
bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping" "0: Default mapping (refer to Figure 108 and Table..,1: NOR/PSRAM bank and SDRAM bank 1 are swapped.,2: FIELD Reserved,3: Reserved."
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|
newline
|
|
bitfld.long 0x0 21. "WFDIS,Write FIFO Disable" "0: Write FIFO enabled (Default after reset),1: Write FIFO disabled"
|
|
bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.."
|
|
newline
|
|
bitfld.long 0x0 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in Synchronous.."
|
|
bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size" "0: No burst split when crossing page boundary..,1: 128 bytes,2: 256 bytes,?,4: 1024 bytes,?,?,?"
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|
newline
|
|
bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal is not taken in to account when..,1: NWAIT signal is taken in to account when running.."
|
|
bitfld.long 0x0 14. "EXTMOD,Extended mode enable." "0: values inside FMC_BWTR register are not taken..,1: values inside FMC_BWTR register are taken into.."
|
|
newline
|
|
bitfld.long 0x0 13. "WAITEN,Wait enable bit" "0: NWAIT signal is disabled (its level not taken..,1: NWAIT signal is enabled (its level is taken into.."
|
|
bitfld.long 0x0 12. "WREN,Write enable bit" "0: Write operations are disabled in the bank by the..,1: Write operations are enabled for the bank by the.."
|
|
newline
|
|
bitfld.long 0x0 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal is active one data cycle before..,1: NWAIT signal is active during wait state (not.."
|
|
bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high."
|
|
newline
|
|
bitfld.long 0x0 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.."
|
|
bitfld.long 0x0 6. "FACCEN,Flash access enable" "0: Corresponding NOR flash memory access is disabled,1: Corresponding NOR flash memory access is enabled.."
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|
newline
|
|
bitfld.long 0x0 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,3: FIELD Reserved"
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|
bitfld.long 0x0 2.--3. "MTYP,Memory type" "0: SRAM (default after reset for Bank 2...4),1: PSRAM (CRAM),2: NOR flash/OneNAND flash (default after reset for..,3: FIELD Reserved"
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|
newline
|
|
bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.."
|
|
bitfld.long 0x0 0. "MBKEN,Memory bank enable bit" "0: Corresponding memory bank is disabled,1: Corresponding memory bank is enabled"
|
|
line.long 0x4 "FMC_BTR1,SRAM/NOR-flash chip-select timing registers for bank 1"
|
|
bitfld.long 0x4 28.--29. "ACCMOD,Access mode" "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x4 24.--27. 1. "DATLAT,(see note below bit descriptions): Data latency for synchronous memory"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration"
|
|
hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration"
|
|
line.long 0x8 "FMC_BCR2,SRAM/NOR-flash chip-select control registers for bank 2"
|
|
bitfld.long 0x8 31. "FMCEN,FMC Enable" "0: Disable the FMC,1: Enable the FMC"
|
|
bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping" "0: Default mapping (refer to Figure 108 and Table..,1: NOR/PSRAM bank and SDRAM bank 1 are swapped.,2: FIELD Reserved,3: Reserved."
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|
newline
|
|
bitfld.long 0x8 21. "WFDIS,Write FIFO Disable" "0: Write FIFO enabled (Default after reset),1: Write FIFO disabled"
|
|
bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.."
|
|
newline
|
|
bitfld.long 0x8 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in Synchronous.."
|
|
bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size" "0: No burst split when crossing page boundary..,1: 128 bytes,2: 256 bytes,?,4: 1024 bytes,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal is not taken in to account when..,1: NWAIT signal is taken in to account when running.."
|
|
bitfld.long 0x8 14. "EXTMOD,Extended mode enable." "0: values inside FMC_BWTR register are not taken..,1: values inside FMC_BWTR register are taken into.."
|
|
newline
|
|
bitfld.long 0x8 13. "WAITEN,Wait enable bit" "0: NWAIT signal is disabled (its level not taken..,1: NWAIT signal is enabled (its level is taken into.."
|
|
bitfld.long 0x8 12. "WREN,Write enable bit" "0: Write operations are disabled in the bank by the..,1: Write operations are enabled for the bank by the.."
|
|
newline
|
|
bitfld.long 0x8 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal is active one data cycle before..,1: NWAIT signal is active during wait state (not.."
|
|
bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high."
|
|
newline
|
|
bitfld.long 0x8 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.."
|
|
bitfld.long 0x8 6. "FACCEN,Flash access enable" "0: Corresponding NOR flash memory access is disabled,1: Corresponding NOR flash memory access is enabled.."
|
|
newline
|
|
bitfld.long 0x8 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,3: FIELD Reserved"
|
|
bitfld.long 0x8 2.--3. "MTYP,Memory type" "0: SRAM (default after reset for Bank 2...4),1: PSRAM (CRAM),2: NOR flash/OneNAND flash (default after reset for..,3: FIELD Reserved"
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|
newline
|
|
bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.."
|
|
bitfld.long 0x8 0. "MBKEN,Memory bank enable bit" "0: Corresponding memory bank is disabled,1: Corresponding memory bank is enabled"
|
|
line.long 0xC "FMC_BTR2,SRAM/NOR-flash chip-select timing registers for bank 2"
|
|
bitfld.long 0xC 28.--29. "ACCMOD,Access mode" "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0xC 24.--27. 1. "DATLAT,(see note below bit descriptions): Data latency for synchronous memory"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)"
|
|
hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration"
|
|
hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration"
|
|
line.long 0x10 "FMC_BCR3,SRAM/NOR-flash chip-select control registers for bank 3"
|
|
bitfld.long 0x10 31. "FMCEN,FMC Enable" "0: Disable the FMC,1: Enable the FMC"
|
|
bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping" "0: Default mapping (refer to Figure 108 and Table..,1: NOR/PSRAM bank and SDRAM bank 1 are swapped.,2: FIELD Reserved,3: Reserved."
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|
newline
|
|
bitfld.long 0x10 21. "WFDIS,Write FIFO Disable" "0: Write FIFO enabled (Default after reset),1: Write FIFO disabled"
|
|
bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.."
|
|
newline
|
|
bitfld.long 0x10 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in Synchronous.."
|
|
bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size" "0: No burst split when crossing page boundary..,1: 128 bytes,2: 256 bytes,?,4: 1024 bytes,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal is not taken in to account when..,1: NWAIT signal is taken in to account when running.."
|
|
bitfld.long 0x10 14. "EXTMOD,Extended mode enable." "0: values inside FMC_BWTR register are not taken..,1: values inside FMC_BWTR register are taken into.."
|
|
newline
|
|
bitfld.long 0x10 13. "WAITEN,Wait enable bit" "0: NWAIT signal is disabled (its level not taken..,1: NWAIT signal is enabled (its level is taken into.."
|
|
bitfld.long 0x10 12. "WREN,Write enable bit" "0: Write operations are disabled in the bank by the..,1: Write operations are enabled for the bank by the.."
|
|
newline
|
|
bitfld.long 0x10 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal is active one data cycle before..,1: NWAIT signal is active during wait state (not.."
|
|
bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high."
|
|
newline
|
|
bitfld.long 0x10 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.."
|
|
bitfld.long 0x10 6. "FACCEN,Flash access enable" "0: Corresponding NOR flash memory access is disabled,1: Corresponding NOR flash memory access is enabled.."
|
|
newline
|
|
bitfld.long 0x10 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,3: FIELD Reserved"
|
|
bitfld.long 0x10 2.--3. "MTYP,Memory type" "0: SRAM (default after reset for Bank 2...4),1: PSRAM (CRAM),2: NOR flash/OneNAND flash (default after reset for..,3: FIELD Reserved"
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|
newline
|
|
bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.."
|
|
bitfld.long 0x10 0. "MBKEN,Memory bank enable bit" "0: Corresponding memory bank is disabled,1: Corresponding memory bank is enabled"
|
|
line.long 0x14 "FMC_BTR3,SRAM/NOR-flash chip-select timing registers for bank 3"
|
|
bitfld.long 0x14 28.--29. "ACCMOD,Access mode" "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x14 24.--27. 1. "DATLAT,(see note below bit descriptions): Data latency for synchronous memory"
|
|
newline
|
|
hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)"
|
|
hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration"
|
|
hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration"
|
|
line.long 0x18 "FMC_BCR4,SRAM/NOR-flash chip-select control registers for bank 4"
|
|
bitfld.long 0x18 31. "FMCEN,FMC Enable" "0: Disable the FMC,1: Enable the FMC"
|
|
bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping" "0: Default mapping (refer to Figure 108 and Table..,1: NOR/PSRAM bank and SDRAM bank 1 are swapped.,2: FIELD Reserved,3: Reserved."
|
|
newline
|
|
bitfld.long 0x18 21. "WFDIS,Write FIFO Disable" "0: Write FIFO enabled (Default after reset),1: Write FIFO disabled"
|
|
bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable" "0: The FMC_CLK is only generated during the..,1: The FMC_CLK is generated continuously during.."
|
|
newline
|
|
bitfld.long 0x18 19. "CBURSTRW,Write burst enable" "0: Write operations are always performed in..,1: Write operations are performed in Synchronous.."
|
|
bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size" "0: No burst split when crossing page boundary..,1: 128 bytes,2: 256 bytes,?,4: 1024 bytes,?,?,?"
|
|
newline
|
|
bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous transfers" "0: NWAIT signal is not taken in to account when..,1: NWAIT signal is taken in to account when running.."
|
|
bitfld.long 0x18 14. "EXTMOD,Extended mode enable." "0: values inside FMC_BWTR register are not taken..,1: values inside FMC_BWTR register are taken into.."
|
|
newline
|
|
bitfld.long 0x18 13. "WAITEN,Wait enable bit" "0: NWAIT signal is disabled (its level not taken..,1: NWAIT signal is enabled (its level is taken into.."
|
|
bitfld.long 0x18 12. "WREN,Write enable bit" "0: Write operations are disabled in the bank by the..,1: Write operations are enabled for the bank by the.."
|
|
newline
|
|
bitfld.long 0x18 11. "WAITCFG,Wait timing configuration" "0: NWAIT signal is active one data cycle before..,1: NWAIT signal is active during wait state (not.."
|
|
bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit" "0: NWAIT active low (default after reset),1: NWAIT active high."
|
|
newline
|
|
bitfld.long 0x18 8. "BURSTEN,Burst enable bit" "0: Burst mode disabled (default after reset). Read..,1: Burst mode enable. Read accesses are performed.."
|
|
bitfld.long 0x18 6. "FACCEN,Flash access enable" "0: Corresponding NOR flash memory access is disabled,1: Corresponding NOR flash memory access is enabled.."
|
|
newline
|
|
bitfld.long 0x18 4.--5. "MWID,Memory data bus width" "0: 8 bits,1: 16 bits (default after reset),2: 32 bits,3: FIELD Reserved"
|
|
bitfld.long 0x18 2.--3. "MTYP,Memory type" "0: SRAM (default after reset for Bank 2...4),1: PSRAM (CRAM),2: NOR flash/OneNAND flash (default after reset for..,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0: Address/Data non-multiplexed,1: Address/Data multiplexed on databus (default.."
|
|
bitfld.long 0x18 0. "MBKEN,Memory bank enable bit" "0: Corresponding memory bank is disabled,1: Corresponding memory bank is enabled"
|
|
line.long 0x1C "FMC_BTR4,SRAM/NOR-flash chip-select timing registers for bank 4"
|
|
bitfld.long 0x1C 28.--29. "ACCMOD,Access mode" "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,(see note below bit descriptions): Data latency for synchronous memory"
|
|
newline
|
|
hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)"
|
|
hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "FMC_PCR,NAND flash control registers"
|
|
bitfld.long 0x0 17.--19. "ECCPS,ECC page size." "0: 256 bytes,1: 512 bytes,2: 1024 bytes,3: 2048 bytes,4: 4096 bytes,5: 8192 bytes,?,?"
|
|
bitfld.long 0x0 16. "TAR3,ALE to RE delay." "0: 1 x fmc_ker_ck cycle (default),?"
|
|
newline
|
|
bitfld.long 0x0 15. "TAR2,ALE to RE delay." "0: 1 x fmc_ker_ck cycle (default),?"
|
|
bitfld.long 0x0 14. "TAR1,ALE to RE delay." "0: 1 x fmc_ker_ck cycle (default),?"
|
|
newline
|
|
bitfld.long 0x0 13. "TAR0,ALE to RE delay." "0: 1 x fmc_ker_ck cycle (default),?"
|
|
hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay."
|
|
newline
|
|
bitfld.long 0x0 6. "ECCEN,ECC computation logic enable bit" "0: ECC logic is disabled and reset (default after..,1: ECC logic is enabled."
|
|
bitfld.long 0x0 4.--5. "PWID,Data bus width." "0: 8 bits,1: 16 bits (default after reset).,2: reserved.,3: reserved."
|
|
newline
|
|
bitfld.long 0x0 2. "PBKEN,NAND flash memory bank enable bit." "0: Corresponding memory bank is disabled (default..,1: Corresponding memory bank is enabled"
|
|
bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit." "0: disabled,1: enabled"
|
|
line.long 0x4 "FMC_SR,FIFO status and interrupt register"
|
|
rbitfld.long 0x4 6. "FEMPT,FIFO empty." "0: FIFO not empty,1: FIFO empty"
|
|
bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable bit" "0: Interrupt falling edge detection request disabled,1: Interrupt falling edge detection request enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable bit" "0: Interrupt high-level detection request disabled,1: Interrupt high-level detection request enabled"
|
|
bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable bit" "0: Interrupt rising edge detection request disabled,1: Interrupt rising edge detection request enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "IFS,Interrupt falling edge status" "0: No interrupt falling edge occurred,1: Interrupt falling edge occurred"
|
|
bitfld.long 0x4 1. "ILS,Interrupt high-level status" "0: No Interrupt high-level occurred,1: Interrupt high-level occurred"
|
|
newline
|
|
bitfld.long 0x4 0. "IRS,Interrupt rising edge status" "0: No interrupt rising edge occurred,1: Interrupt rising edge occurred"
|
|
line.long 0x8 "FMC_PMEM,Common memory space timing register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time"
|
|
line.long 0xC "FMC_PATT,Attribute memory space timing registers"
|
|
hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time"
|
|
hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time"
|
|
hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "FMC_ECCR,ECC result registers"
|
|
hexmask.long 0x0 0.--31. 1. "ECC,ECC result"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "FMC_BWTR1,SRAM/NOR-flash write timing registers for bank 1"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration."
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration."
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "FMC_BWTR2,SRAM/NOR-flash write timing registers for bank 2"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration."
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration."
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "FMC_BWTR3,SRAM/NOR-flash write timing registers for bank 3"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration."
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration."
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "FMC_BWTR4,SRAM/NOR-flash write timing registers for bank 4"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,Access mode." "0: access mode A,1: access mode B,2: access mode C,3: access mode D"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration."
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration."
|
|
group.long 0x140++0x17
|
|
line.long 0x0 "FMC_SDCR1,SDRAM Control registers for SDRAM memory bank 1"
|
|
bitfld.long 0x0 13.--14. "RPIPE,Read pipe" "0: No fmc_ker_ck clock cycle delay,1: One fmc_ker_ck clock cycle delay,2: Two fmc_ker_ck clock cycle delay,3: reserved."
|
|
bitfld.long 0x0 12. "RBURST,Burst read" "0: single read requests are not managed as bursts,1: single read requests are always managed as bursts"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration" "0: SDCLK clock disabled,1: FIELD Reserved,2: SDCLK period = 2 x fmc_ker_ck periods,3: SDCLK period = 3 x fmc_ker_ck periods"
|
|
bitfld.long 0x0 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored"
|
|
newline
|
|
bitfld.long 0x0 7.--8. "CAS,CAS Latency" "0: reserved.,1: 1 cycle,2: 2 cycles,3: 3 cycles"
|
|
bitfld.long 0x0 6. "NB,Number of internal banks" "0: Two internal Banks,1: Four internal Banks"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,3: reserved."
|
|
bitfld.long 0x0 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,3: reserved."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits."
|
|
line.long 0x4 "FMC_SDCR2,SDRAM Control registers for SDRAM memory bank 2"
|
|
bitfld.long 0x4 13.--14. "RPIPE,Read pipe" "0: No fmc_ker_ck clock cycle delay,1: One fmc_ker_ck clock cycle delay,2: Two fmc_ker_ck clock cycle delay,3: reserved."
|
|
bitfld.long 0x4 12. "RBURST,Burst read" "0: single read requests are not managed as bursts,1: single read requests are always managed as bursts"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration" "0: SDCLK clock disabled,1: FIELD Reserved,2: SDCLK period = 2 x fmc_ker_ck periods,3: SDCLK period = 3 x fmc_ker_ck periods"
|
|
bitfld.long 0x4 9. "WP,Write protection" "0: Write accesses allowed,1: Write accesses ignored"
|
|
newline
|
|
bitfld.long 0x4 7.--8. "CAS,CAS Latency" "0: reserved.,1: 1 cycle,2: 2 cycles,3: 3 cycles"
|
|
bitfld.long 0x4 6. "NB,Number of internal banks" "0: Two internal Banks,1: Four internal Banks"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "MWID,Memory data bus width." "0: 8 bits,1: 16 bits,2: 32 bits,3: reserved."
|
|
bitfld.long 0x4 2.--3. "NR,Number of row address bits" "0: 11 bit,1: 12 bits,2: 13 bits,3: reserved."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "NC,Number of column address bits" "0: 8 bits,1: 9 bits,2: 10 bits,3: 11 bits."
|
|
line.long 0x8 "FMC_SDTR1,SDRAM Timing registers for SDRAM memory bank 1"
|
|
hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay"
|
|
hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay"
|
|
hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time"
|
|
hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active"
|
|
line.long 0xC "FMC_SDTR2,SDRAM Timing registers for SDRAM memory bank 2"
|
|
hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay"
|
|
hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay"
|
|
hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time"
|
|
hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active"
|
|
line.long 0x10 "FMC_SDCMR,SDRAM Command mode register"
|
|
hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition"
|
|
hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh"
|
|
newline
|
|
bitfld.long 0x10 4. "CTB1,Command Target Bank 1" "0: Command not issued to SDRAM Bank 1,1: Command issued to SDRAM Bank 1"
|
|
bitfld.long 0x10 3. "CTB2,Command Target Bank 2" "0: Command not issued to SDRAM Bank 2,1: Command issued to SDRAM Bank 2"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "MODE,Command mode" "0: Normal Mode,1: Clock Configuration Enable,2: PALL (All Bank Precharge) command,3: Auto-refresh command,4: Load Mode Register,5: Self-refresh command,6: Power-down command,7: FIELD Reserved"
|
|
line.long 0x14 "FMC_SDRTR,SDRAM refresh timer register"
|
|
bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0: Interrupt is disabled,1: An Interrupt is generated if RE = 1"
|
|
hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count"
|
|
newline
|
|
bitfld.long 0x14 0. "CRE,Clear Refresh error flag" "0: no effect,1: Refresh Error flag is cleared"
|
|
rgroup.long 0x158++0x3
|
|
line.long 0x0 "FMC_SDSR,SDRAM Status register"
|
|
bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2" "0: Normal Mode,1: Self-refresh mode,2: Power-down mode,?"
|
|
bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1" "0: Normal Mode,1: Self-refresh mode,2: Power-down mode,?"
|
|
newline
|
|
bitfld.long 0x0 0. "RE,Refresh error flag" "0: No refresh error has been detected,1: A refresh error has been detected"
|
|
tree.end
|
|
tree "GFXMMU (Chrom-GRC)"
|
|
base ad:0x52010000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "GFXMMU_CR,GFXMMU configuration register"
|
|
bitfld.long 0x0 31. "B3PM,Buffer 3 packing mode" "0: MSB is removed,1: LSB is removed"
|
|
bitfld.long 0x0 30. "B3PE,Buffer 3 packing enable" "0: Packing is disabled,1: Packing is enable"
|
|
bitfld.long 0x0 29. "B2PM,Buffer 2 packing mode" "0: MSB is removed,1: LSB is removed"
|
|
newline
|
|
bitfld.long 0x0 28. "B2PE,Buffer 2 packing enable" "0: Packing is disabled,1: Packing is enable"
|
|
bitfld.long 0x0 27. "B1PM,Buffer 1 packing mode" "0: MSB is removed,1: LSB is removed"
|
|
bitfld.long 0x0 26. "B1PE,Buffer 1 packing enable" "0: Packing is disabled,1: Packing is enable"
|
|
newline
|
|
bitfld.long 0x0 25. "B0PM,Buffer 0 packing mode" "0: MSB is removed,1: LSB is removed"
|
|
bitfld.long 0x0 24. "B0PE,Buffer 0 packing enable" "0: Packing is disabled,1: Packing is enable"
|
|
bitfld.long 0x0 15. "ATE,Address translation enable" "0: Address translation is disable,1: Address translation is enable"
|
|
newline
|
|
bitfld.long 0x0 6. "BS,Block size" "0: 16-byte blocks,1: 12-byte blocks"
|
|
bitfld.long 0x0 4. "AMEIE,AXI master error interrupt enable" "0: Interrupt disable,1: Interrupt enabled"
|
|
bitfld.long 0x0 3. "B3OIE,Buffer 3 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "B2OIE,Buffer 2 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled"
|
|
bitfld.long 0x0 1. "B1OIE,Buffer 1 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled"
|
|
bitfld.long 0x0 0. "B0OIE,Buffer 0 overflow interrupt enable" "0: Interrupt disable,1: Interrupt enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "GFXMMU_SR,GFXMMU status register"
|
|
bitfld.long 0x0 4. "AMEF,AXI master error flag" "0,1"
|
|
bitfld.long 0x0 3. "B3OF,Buffer 3 overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "B2OF,Buffer 2 overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "B1OF,Buffer 1 overflow flag" "0,1"
|
|
bitfld.long 0x0 0. "B0OF,Buffer 0 overflow flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "GFXMMU_FCR,GFXMMU flag clear register"
|
|
bitfld.long 0x0 4. "CAMEF,Clear AXI master error flag" "0,1"
|
|
bitfld.long 0x0 3. "CB3OF,Clear buffer 3 overflow flag" "0,1"
|
|
bitfld.long 0x0 2. "CB2OF,Clear buffer 2 overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CB1OF,Clear buffer 1 overflow flag" "0,1"
|
|
bitfld.long 0x0 0. "CB0OF,Clear buffer 0 overflow flag" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "GFXMMU_DVR,GFXMMU default value register"
|
|
hexmask.long 0x0 0.--31. 1. "DV,Default value"
|
|
line.long 0x4 "GFXMMU_DAR,GFXMMU default alpha register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DA,Default alpha"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "GFXMMU_B0CR,GFXMMU buffer 0 configuration register"
|
|
hexmask.long.word 0x0 23.--31. 1. "PBBA,Physical buffer base address"
|
|
hexmask.long.tbyte 0x0 4.--22. 1. "PBO,Physical buffer offset"
|
|
line.long 0x4 "GFXMMU_B1CR,GFXMMU buffer 1 configuration register"
|
|
hexmask.long.word 0x4 23.--31. 1. "PBBA,Physical buffer base address"
|
|
hexmask.long.tbyte 0x4 4.--22. 1. "PBO,Physical buffer offset"
|
|
line.long 0x8 "GFXMMU_B2CR,GFXMMU buffer 2 configuration register"
|
|
hexmask.long.word 0x8 23.--31. 1. "PBBA,Physical buffer base address"
|
|
hexmask.long.tbyte 0x8 4.--22. 1. "PBO,Physical buffer offset"
|
|
line.long 0xC "GFXMMU_B3CR,GFXMMU buffer 3 configuration register"
|
|
hexmask.long.word 0xC 23.--31. 1. "PBBA,Physical buffer base address"
|
|
hexmask.long.tbyte 0xC 4.--22. 1. "PBO,Physical buffer offset"
|
|
group.long 0x1000++0xFFF
|
|
line.long 0x0 "GFXMMU_LUT0L,GFXMMU LUT entry 0 low"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4 "GFXMMU_LUT0H,GFXMMU LUT entry 0 high"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8 "GFXMMU_LUT1L,GFXMMU LUT entry 1 low"
|
|
hexmask.long.byte 0x8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC "GFXMMU_LUT1H,GFXMMU LUT entry 1 high"
|
|
hexmask.long.tbyte 0xC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x10 "GFXMMU_LUT2L,GFXMMU LUT entry 2 low"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x14 "GFXMMU_LUT2H,GFXMMU LUT entry 2 high"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. "LO,Line offset"
|
|
line.long 0x18 "GFXMMU_LUT3L,GFXMMU LUT entry 3 low"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1C "GFXMMU_LUT3H,GFXMMU LUT entry 3 high"
|
|
hexmask.long.tbyte 0x1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x20 "GFXMMU_LUT4L,GFXMMU LUT entry 4 low"
|
|
hexmask.long.byte 0x20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x24 "GFXMMU_LUT4H,GFXMMU LUT entry 4 high"
|
|
hexmask.long.tbyte 0x24 0.--17. 1. "LO,Line offset"
|
|
line.long 0x28 "GFXMMU_LUT5L,GFXMMU LUT entry 5 low"
|
|
hexmask.long.byte 0x28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2C "GFXMMU_LUT5H,GFXMMU LUT entry 5 high"
|
|
hexmask.long.tbyte 0x2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x30 "GFXMMU_LUT6L,GFXMMU LUT entry 6 low"
|
|
hexmask.long.byte 0x30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x34 "GFXMMU_LUT6H,GFXMMU LUT entry 6 high"
|
|
hexmask.long.tbyte 0x34 0.--17. 1. "LO,Line offset"
|
|
line.long 0x38 "GFXMMU_LUT7L,GFXMMU LUT entry 7 low"
|
|
hexmask.long.byte 0x38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3C "GFXMMU_LUT7H,GFXMMU LUT entry 7 high"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x40 "GFXMMU_LUT8L,GFXMMU LUT entry 8 low"
|
|
hexmask.long.byte 0x40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x44 "GFXMMU_LUT8H,GFXMMU LUT entry 8 high"
|
|
hexmask.long.tbyte 0x44 0.--17. 1. "LO,Line offset"
|
|
line.long 0x48 "GFXMMU_LUT9L,GFXMMU LUT entry 9 low"
|
|
hexmask.long.byte 0x48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4C "GFXMMU_LUT9H,GFXMMU LUT entry 9 high"
|
|
hexmask.long.tbyte 0x4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x50 "GFXMMU_LUT10L,GFXMMU LUT entry 10 low"
|
|
hexmask.long.byte 0x50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x54 "GFXMMU_LUT10H,GFXMMU LUT entry 10 high"
|
|
hexmask.long.tbyte 0x54 0.--17. 1. "LO,Line offset"
|
|
line.long 0x58 "GFXMMU_LUT11L,GFXMMU LUT entry 11 low"
|
|
hexmask.long.byte 0x58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5C "GFXMMU_LUT11H,GFXMMU LUT entry 11 high"
|
|
hexmask.long.tbyte 0x5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x60 "GFXMMU_LUT12L,GFXMMU LUT entry 12 low"
|
|
hexmask.long.byte 0x60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x64 "GFXMMU_LUT12H,GFXMMU LUT entry 12 high"
|
|
hexmask.long.tbyte 0x64 0.--17. 1. "LO,Line offset"
|
|
line.long 0x68 "GFXMMU_LUT13L,GFXMMU LUT entry 13 low"
|
|
hexmask.long.byte 0x68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6C "GFXMMU_LUT13H,GFXMMU LUT entry 13 high"
|
|
hexmask.long.tbyte 0x6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x70 "GFXMMU_LUT14L,GFXMMU LUT entry 14 low"
|
|
hexmask.long.byte 0x70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x74 "GFXMMU_LUT14H,GFXMMU LUT entry 14 high"
|
|
hexmask.long.tbyte 0x74 0.--17. 1. "LO,Line offset"
|
|
line.long 0x78 "GFXMMU_LUT15L,GFXMMU LUT entry 15 low"
|
|
hexmask.long.byte 0x78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7C "GFXMMU_LUT15H,GFXMMU LUT entry 15 high"
|
|
hexmask.long.tbyte 0x7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x80 "GFXMMU_LUT16L,GFXMMU LUT entry 16 low"
|
|
hexmask.long.byte 0x80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x84 "GFXMMU_LUT16H,GFXMMU LUT entry 16 high"
|
|
hexmask.long.tbyte 0x84 0.--17. 1. "LO,Line offset"
|
|
line.long 0x88 "GFXMMU_LUT17L,GFXMMU LUT entry 17 low"
|
|
hexmask.long.byte 0x88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8C "GFXMMU_LUT17H,GFXMMU LUT entry 17 high"
|
|
hexmask.long.tbyte 0x8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x90 "GFXMMU_LUT18L,GFXMMU LUT entry 18 low"
|
|
hexmask.long.byte 0x90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x94 "GFXMMU_LUT18H,GFXMMU LUT entry 18 high"
|
|
hexmask.long.tbyte 0x94 0.--17. 1. "LO,Line offset"
|
|
line.long 0x98 "GFXMMU_LUT19L,GFXMMU LUT entry 19 low"
|
|
hexmask.long.byte 0x98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9C "GFXMMU_LUT19H,GFXMMU LUT entry 19 high"
|
|
hexmask.long.tbyte 0x9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA0 "GFXMMU_LUT20L,GFXMMU LUT entry 20 low"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA4 "GFXMMU_LUT20H,GFXMMU LUT entry 20 high"
|
|
hexmask.long.tbyte 0xA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA8 "GFXMMU_LUT21L,GFXMMU LUT entry 21 low"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAC "GFXMMU_LUT21H,GFXMMU LUT entry 21 high"
|
|
hexmask.long.tbyte 0xAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB0 "GFXMMU_LUT22L,GFXMMU LUT entry 22 low"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB4 "GFXMMU_LUT22H,GFXMMU LUT entry 22 high"
|
|
hexmask.long.tbyte 0xB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB8 "GFXMMU_LUT23L,GFXMMU LUT entry 23 low"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBC "GFXMMU_LUT23H,GFXMMU LUT entry 23 high"
|
|
hexmask.long.tbyte 0xBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC0 "GFXMMU_LUT24L,GFXMMU LUT entry 24 low"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC4 "GFXMMU_LUT24H,GFXMMU LUT entry 24 high"
|
|
hexmask.long.tbyte 0xC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC8 "GFXMMU_LUT25L,GFXMMU LUT entry 25 low"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCC "GFXMMU_LUT25H,GFXMMU LUT entry 25 high"
|
|
hexmask.long.tbyte 0xCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD0 "GFXMMU_LUT26L,GFXMMU LUT entry 26 low"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD4 "GFXMMU_LUT26H,GFXMMU LUT entry 26 high"
|
|
hexmask.long.tbyte 0xD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD8 "GFXMMU_LUT27L,GFXMMU LUT entry 27 low"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDC "GFXMMU_LUT27H,GFXMMU LUT entry 27 high"
|
|
hexmask.long.tbyte 0xDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE0 "GFXMMU_LUT28L,GFXMMU LUT entry 28 low"
|
|
hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE4 "GFXMMU_LUT28H,GFXMMU LUT entry 28 high"
|
|
hexmask.long.tbyte 0xE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE8 "GFXMMU_LUT29L,GFXMMU LUT entry 29 low"
|
|
hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEC "GFXMMU_LUT29H,GFXMMU LUT entry 29 high"
|
|
hexmask.long.tbyte 0xEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF0 "GFXMMU_LUT30L,GFXMMU LUT entry 30 low"
|
|
hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF4 "GFXMMU_LUT30H,GFXMMU LUT entry 30 high"
|
|
hexmask.long.tbyte 0xF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF8 "GFXMMU_LUT31L,GFXMMU LUT entry 31 low"
|
|
hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFC "GFXMMU_LUT31H,GFXMMU LUT entry 31 high"
|
|
hexmask.long.tbyte 0xFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x100 "GFXMMU_LUT32L,GFXMMU LUT entry 32 low"
|
|
hexmask.long.byte 0x100 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x100 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x104 "GFXMMU_LUT32H,GFXMMU LUT entry 32 high"
|
|
hexmask.long.tbyte 0x104 0.--17. 1. "LO,Line offset"
|
|
line.long 0x108 "GFXMMU_LUT33L,GFXMMU LUT entry 33 low"
|
|
hexmask.long.byte 0x108 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x108 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x10C "GFXMMU_LUT33H,GFXMMU LUT entry 33 high"
|
|
hexmask.long.tbyte 0x10C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x110 "GFXMMU_LUT34L,GFXMMU LUT entry 34 low"
|
|
hexmask.long.byte 0x110 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x110 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x114 "GFXMMU_LUT34H,GFXMMU LUT entry 34 high"
|
|
hexmask.long.tbyte 0x114 0.--17. 1. "LO,Line offset"
|
|
line.long 0x118 "GFXMMU_LUT35L,GFXMMU LUT entry 35 low"
|
|
hexmask.long.byte 0x118 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x118 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x11C "GFXMMU_LUT35H,GFXMMU LUT entry 35 high"
|
|
hexmask.long.tbyte 0x11C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x120 "GFXMMU_LUT36L,GFXMMU LUT entry 36 low"
|
|
hexmask.long.byte 0x120 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x120 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x124 "GFXMMU_LUT36H,GFXMMU LUT entry 36 high"
|
|
hexmask.long.tbyte 0x124 0.--17. 1. "LO,Line offset"
|
|
line.long 0x128 "GFXMMU_LUT37L,GFXMMU LUT entry 37 low"
|
|
hexmask.long.byte 0x128 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x128 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x12C "GFXMMU_LUT37H,GFXMMU LUT entry 37 high"
|
|
hexmask.long.tbyte 0x12C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x130 "GFXMMU_LUT38L,GFXMMU LUT entry 38 low"
|
|
hexmask.long.byte 0x130 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x130 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x134 "GFXMMU_LUT38H,GFXMMU LUT entry 38 high"
|
|
hexmask.long.tbyte 0x134 0.--17. 1. "LO,Line offset"
|
|
line.long 0x138 "GFXMMU_LUT39L,GFXMMU LUT entry 39 low"
|
|
hexmask.long.byte 0x138 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x138 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x13C "GFXMMU_LUT39H,GFXMMU LUT entry 39 high"
|
|
hexmask.long.tbyte 0x13C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x140 "GFXMMU_LUT40L,GFXMMU LUT entry 40 low"
|
|
hexmask.long.byte 0x140 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x140 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x144 "GFXMMU_LUT40H,GFXMMU LUT entry 40 high"
|
|
hexmask.long.tbyte 0x144 0.--17. 1. "LO,Line offset"
|
|
line.long 0x148 "GFXMMU_LUT41L,GFXMMU LUT entry 41 low"
|
|
hexmask.long.byte 0x148 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x148 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x14C "GFXMMU_LUT41H,GFXMMU LUT entry 41 high"
|
|
hexmask.long.tbyte 0x14C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x150 "GFXMMU_LUT42L,GFXMMU LUT entry 42 low"
|
|
hexmask.long.byte 0x150 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x150 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x154 "GFXMMU_LUT42H,GFXMMU LUT entry 42 high"
|
|
hexmask.long.tbyte 0x154 0.--17. 1. "LO,Line offset"
|
|
line.long 0x158 "GFXMMU_LUT43L,GFXMMU LUT entry 43 low"
|
|
hexmask.long.byte 0x158 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x158 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x15C "GFXMMU_LUT43H,GFXMMU LUT entry 43 high"
|
|
hexmask.long.tbyte 0x15C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x160 "GFXMMU_LUT44L,GFXMMU LUT entry 44 low"
|
|
hexmask.long.byte 0x160 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x160 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x164 "GFXMMU_LUT44H,GFXMMU LUT entry 44 high"
|
|
hexmask.long.tbyte 0x164 0.--17. 1. "LO,Line offset"
|
|
line.long 0x168 "GFXMMU_LUT45L,GFXMMU LUT entry 45 low"
|
|
hexmask.long.byte 0x168 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x168 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x16C "GFXMMU_LUT45H,GFXMMU LUT entry 45 high"
|
|
hexmask.long.tbyte 0x16C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x170 "GFXMMU_LUT46L,GFXMMU LUT entry 46 low"
|
|
hexmask.long.byte 0x170 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x170 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x174 "GFXMMU_LUT46H,GFXMMU LUT entry 46 high"
|
|
hexmask.long.tbyte 0x174 0.--17. 1. "LO,Line offset"
|
|
line.long 0x178 "GFXMMU_LUT47L,GFXMMU LUT entry 47 low"
|
|
hexmask.long.byte 0x178 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x178 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x17C "GFXMMU_LUT47H,GFXMMU LUT entry 47 high"
|
|
hexmask.long.tbyte 0x17C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x180 "GFXMMU_LUT48L,GFXMMU LUT entry 48 low"
|
|
hexmask.long.byte 0x180 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x180 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x184 "GFXMMU_LUT48H,GFXMMU LUT entry 48 high"
|
|
hexmask.long.tbyte 0x184 0.--17. 1. "LO,Line offset"
|
|
line.long 0x188 "GFXMMU_LUT49L,GFXMMU LUT entry 49 low"
|
|
hexmask.long.byte 0x188 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x188 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x18C "GFXMMU_LUT49H,GFXMMU LUT entry 49 high"
|
|
hexmask.long.tbyte 0x18C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x190 "GFXMMU_LUT50L,GFXMMU LUT entry 50 low"
|
|
hexmask.long.byte 0x190 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x190 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x194 "GFXMMU_LUT50H,GFXMMU LUT entry 50 high"
|
|
hexmask.long.tbyte 0x194 0.--17. 1. "LO,Line offset"
|
|
line.long 0x198 "GFXMMU_LUT51L,GFXMMU LUT entry 51 low"
|
|
hexmask.long.byte 0x198 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x198 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x19C "GFXMMU_LUT51H,GFXMMU LUT entry 51 high"
|
|
hexmask.long.tbyte 0x19C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1A0 "GFXMMU_LUT52L,GFXMMU LUT entry 52 low"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1A4 "GFXMMU_LUT52H,GFXMMU LUT entry 52 high"
|
|
hexmask.long.tbyte 0x1A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1A8 "GFXMMU_LUT53L,GFXMMU LUT entry 53 low"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1AC "GFXMMU_LUT53H,GFXMMU LUT entry 53 high"
|
|
hexmask.long.tbyte 0x1AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1B0 "GFXMMU_LUT54L,GFXMMU LUT entry 54 low"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1B4 "GFXMMU_LUT54H,GFXMMU LUT entry 54 high"
|
|
hexmask.long.tbyte 0x1B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1B8 "GFXMMU_LUT55L,GFXMMU LUT entry 55 low"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1BC "GFXMMU_LUT55H,GFXMMU LUT entry 55 high"
|
|
hexmask.long.tbyte 0x1BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1C0 "GFXMMU_LUT56L,GFXMMU LUT entry 56 low"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1C4 "GFXMMU_LUT56H,GFXMMU LUT entry 56 high"
|
|
hexmask.long.tbyte 0x1C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1C8 "GFXMMU_LUT57L,GFXMMU LUT entry 57 low"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1CC "GFXMMU_LUT57H,GFXMMU LUT entry 57 high"
|
|
hexmask.long.tbyte 0x1CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1D0 "GFXMMU_LUT58L,GFXMMU LUT entry 58 low"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1D4 "GFXMMU_LUT58H,GFXMMU LUT entry 58 high"
|
|
hexmask.long.tbyte 0x1D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1D8 "GFXMMU_LUT59L,GFXMMU LUT entry 59 low"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1DC "GFXMMU_LUT59H,GFXMMU LUT entry 59 high"
|
|
hexmask.long.tbyte 0x1DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1E0 "GFXMMU_LUT60L,GFXMMU LUT entry 60 low"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1E4 "GFXMMU_LUT60H,GFXMMU LUT entry 60 high"
|
|
hexmask.long.tbyte 0x1E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1E8 "GFXMMU_LUT61L,GFXMMU LUT entry 61 low"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1EC "GFXMMU_LUT61H,GFXMMU LUT entry 61 high"
|
|
hexmask.long.tbyte 0x1EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1F0 "GFXMMU_LUT62L,GFXMMU LUT entry 62 low"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1F4 "GFXMMU_LUT62H,GFXMMU LUT entry 62 high"
|
|
hexmask.long.tbyte 0x1F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1F8 "GFXMMU_LUT63L,GFXMMU LUT entry 63 low"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1FC "GFXMMU_LUT63H,GFXMMU LUT entry 63 high"
|
|
hexmask.long.tbyte 0x1FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x200 "GFXMMU_LUT64L,GFXMMU LUT entry 64 low"
|
|
hexmask.long.byte 0x200 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x200 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x204 "GFXMMU_LUT64H,GFXMMU LUT entry 64 high"
|
|
hexmask.long.tbyte 0x204 0.--17. 1. "LO,Line offset"
|
|
line.long 0x208 "GFXMMU_LUT65L,GFXMMU LUT entry 65 low"
|
|
hexmask.long.byte 0x208 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x208 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x20C "GFXMMU_LUT65H,GFXMMU LUT entry 65 high"
|
|
hexmask.long.tbyte 0x20C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x210 "GFXMMU_LUT66L,GFXMMU LUT entry 66 low"
|
|
hexmask.long.byte 0x210 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x210 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x214 "GFXMMU_LUT66H,GFXMMU LUT entry 66 high"
|
|
hexmask.long.tbyte 0x214 0.--17. 1. "LO,Line offset"
|
|
line.long 0x218 "GFXMMU_LUT67L,GFXMMU LUT entry 67 low"
|
|
hexmask.long.byte 0x218 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x218 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x21C "GFXMMU_LUT67H,GFXMMU LUT entry 67 high"
|
|
hexmask.long.tbyte 0x21C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x220 "GFXMMU_LUT68L,GFXMMU LUT entry 68 low"
|
|
hexmask.long.byte 0x220 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x220 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x224 "GFXMMU_LUT68H,GFXMMU LUT entry 68 high"
|
|
hexmask.long.tbyte 0x224 0.--17. 1. "LO,Line offset"
|
|
line.long 0x228 "GFXMMU_LUT69L,GFXMMU LUT entry 69 low"
|
|
hexmask.long.byte 0x228 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x228 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x22C "GFXMMU_LUT69H,GFXMMU LUT entry 69 high"
|
|
hexmask.long.tbyte 0x22C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x230 "GFXMMU_LUT70L,GFXMMU LUT entry 70 low"
|
|
hexmask.long.byte 0x230 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x230 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x234 "GFXMMU_LUT70H,GFXMMU LUT entry 70 high"
|
|
hexmask.long.tbyte 0x234 0.--17. 1. "LO,Line offset"
|
|
line.long 0x238 "GFXMMU_LUT71L,GFXMMU LUT entry 71 low"
|
|
hexmask.long.byte 0x238 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x238 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x23C "GFXMMU_LUT71H,GFXMMU LUT entry 71 high"
|
|
hexmask.long.tbyte 0x23C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x240 "GFXMMU_LUT72L,GFXMMU LUT entry 72 low"
|
|
hexmask.long.byte 0x240 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x240 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x244 "GFXMMU_LUT72H,GFXMMU LUT entry 72 high"
|
|
hexmask.long.tbyte 0x244 0.--17. 1. "LO,Line offset"
|
|
line.long 0x248 "GFXMMU_LUT73L,GFXMMU LUT entry 73 low"
|
|
hexmask.long.byte 0x248 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x248 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x24C "GFXMMU_LUT73H,GFXMMU LUT entry 73 high"
|
|
hexmask.long.tbyte 0x24C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x250 "GFXMMU_LUT74L,GFXMMU LUT entry 74 low"
|
|
hexmask.long.byte 0x250 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x250 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x254 "GFXMMU_LUT74H,GFXMMU LUT entry 74 high"
|
|
hexmask.long.tbyte 0x254 0.--17. 1. "LO,Line offset Line offset of line number x expressed in number of blocks"
|
|
line.long 0x258 "GFXMMU_LUT75L,GFXMMU LUT entry 75 low"
|
|
hexmask.long.byte 0x258 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x258 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x25C "GFXMMU_LUT75H,GFXMMU LUT entry 75 high"
|
|
hexmask.long.tbyte 0x25C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x260 "GFXMMU_LUT76L,GFXMMU LUT entry 76 low"
|
|
hexmask.long.byte 0x260 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x260 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x264 "GFXMMU_LUT76H,GFXMMU LUT entry 76 high"
|
|
hexmask.long.tbyte 0x264 0.--17. 1. "LO,Line offset"
|
|
line.long 0x268 "GFXMMU_LUT77L,GFXMMU LUT entry 77 low"
|
|
hexmask.long.byte 0x268 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x268 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x26C "GFXMMU_LUT77H,GFXMMU LUT entry 77 high"
|
|
hexmask.long.tbyte 0x26C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x270 "GFXMMU_LUT78L,GFXMMU LUT entry 78 low"
|
|
hexmask.long.byte 0x270 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x270 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x274 "GFXMMU_LUT78H,GFXMMU LUT entry 78 high"
|
|
hexmask.long.tbyte 0x274 0.--17. 1. "LO,Line offset"
|
|
line.long 0x278 "GFXMMU_LUT79L,GFXMMU LUT entry 79 low"
|
|
hexmask.long.byte 0x278 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x278 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x27C "GFXMMU_LUT79H,GFXMMU LUT entry 79 high"
|
|
hexmask.long.tbyte 0x27C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x280 "GFXMMU_LUT80L,GFXMMU LUT entry 80 low"
|
|
hexmask.long.byte 0x280 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x280 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x284 "GFXMMU_LUT80H,GFXMMU LUT entry 80 high"
|
|
hexmask.long.tbyte 0x284 0.--17. 1. "LO,Line offset"
|
|
line.long 0x288 "GFXMMU_LUT81L,GFXMMU LUT entry 81 low"
|
|
hexmask.long.byte 0x288 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x288 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x28C "GFXMMU_LUT81H,GFXMMU LUT entry 81 high"
|
|
hexmask.long.tbyte 0x28C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x290 "GFXMMU_LUT82L,GFXMMU LUT entry 82 low"
|
|
hexmask.long.byte 0x290 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x290 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x294 "GFXMMU_LUT82H,GFXMMU LUT entry 82 high"
|
|
hexmask.long.tbyte 0x294 0.--17. 1. "LO,Line offset"
|
|
line.long 0x298 "GFXMMU_LUT83L,GFXMMU LUT entry 83 low"
|
|
hexmask.long.byte 0x298 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x298 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x29C "GFXMMU_LUT83H,GFXMMU LUT entry 83 high"
|
|
hexmask.long.tbyte 0x29C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2A0 "GFXMMU_LUT84L,GFXMMU LUT entry 84 low"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2A4 "GFXMMU_LUT84H,GFXMMU LUT entry 84 high"
|
|
hexmask.long.tbyte 0x2A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2A8 "GFXMMU_LUT85L,GFXMMU LUT entry 85 low"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2AC "GFXMMU_LUT85H,GFXMMU LUT entry 85 high"
|
|
hexmask.long.tbyte 0x2AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2B0 "GFXMMU_LUT86L,GFXMMU LUT entry 86 low"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2B4 "GFXMMU_LUT86H,GFXMMU LUT entry 86 high"
|
|
hexmask.long.tbyte 0x2B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2B8 "GFXMMU_LUT87L,GFXMMU LUT entry 87 low"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2BC "GFXMMU_LUT87H,GFXMMU LUT entry 87 high"
|
|
hexmask.long.tbyte 0x2BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2C0 "GFXMMU_LUT88L,GFXMMU LUT entry 88 low"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2C4 "GFXMMU_LUT88H,GFXMMU LUT entry 88 high"
|
|
hexmask.long.tbyte 0x2C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2C8 "GFXMMU_LUT89L,GFXMMU LUT entry 89 low"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2CC "GFXMMU_LUT89H,GFXMMU LUT entry 89 high"
|
|
hexmask.long.tbyte 0x2CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2D0 "GFXMMU_LUT90L,GFXMMU LUT entry 90 low"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2D4 "GFXMMU_LUT90H,GFXMMU LUT entry 90 high"
|
|
hexmask.long.tbyte 0x2D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2D8 "GFXMMU_LUT91L,GFXMMU LUT entry 91 low"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2DC "GFXMMU_LUT91H,GFXMMU LUT entry 91 high"
|
|
hexmask.long.tbyte 0x2DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2E0 "GFXMMU_LUT92L,GFXMMU LUT entry 92 low"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2E4 "GFXMMU_LUT92H,GFXMMU LUT entry 92 high"
|
|
hexmask.long.tbyte 0x2E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2E8 "GFXMMU_LUT93L,GFXMMU LUT entry 93 low"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2EC "GFXMMU_LUT93H,GFXMMU LUT entry 93 high"
|
|
hexmask.long.tbyte 0x2EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2F0 "GFXMMU_LUT94L,GFXMMU LUT entry 94 low"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2F4 "GFXMMU_LUT94H,GFXMMU LUT entry 94 high"
|
|
hexmask.long.tbyte 0x2F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2F8 "GFXMMU_LUT95L,GFXMMU LUT entry 95 low"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2FC "GFXMMU_LUT95H,GFXMMU LUT entry 95 high"
|
|
hexmask.long.tbyte 0x2FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x300 "GFXMMU_LUT96L,GFXMMU LUT entry 96 low"
|
|
hexmask.long.byte 0x300 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x300 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x304 "GFXMMU_LUT96H,GFXMMU LUT entry 96 high"
|
|
hexmask.long.tbyte 0x304 0.--17. 1. "LO,Line offset"
|
|
line.long 0x308 "GFXMMU_LUT97L,GFXMMU LUT entry 97 low"
|
|
hexmask.long.byte 0x308 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x308 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x30C "GFXMMU_LUT97H,GFXMMU LUT entry 97 high"
|
|
hexmask.long.tbyte 0x30C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x310 "GFXMMU_LUT98L,GFXMMU LUT entry 98 low"
|
|
hexmask.long.byte 0x310 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x310 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x314 "GFXMMU_LUT98H,GFXMMU LUT entry 98 high"
|
|
hexmask.long.tbyte 0x314 0.--17. 1. "LO,Line offset"
|
|
line.long 0x318 "GFXMMU_LUT99L,GFXMMU LUT entry 99 low"
|
|
hexmask.long.byte 0x318 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x318 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x31C "GFXMMU_LUT99H,GFXMMU LUT entry 99 high"
|
|
hexmask.long.tbyte 0x31C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x320 "GFXMMU_LUT100L,GFXMMU LUT entry 100 low"
|
|
hexmask.long.byte 0x320 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x320 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x324 "GFXMMU_LUT100H,GFXMMU LUT entry 100 high"
|
|
hexmask.long.tbyte 0x324 0.--17. 1. "LO,Line offset"
|
|
line.long 0x328 "GFXMMU_LUT101L,GFXMMU LUT entry 101 low"
|
|
hexmask.long.byte 0x328 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x328 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x32C "GFXMMU_LUT101H,GFXMMU LUT entry 101 high"
|
|
hexmask.long.tbyte 0x32C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x330 "GFXMMU_LUT102L,GFXMMU LUT entry 102 low"
|
|
hexmask.long.byte 0x330 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x330 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x334 "GFXMMU_LUT102H,GFXMMU LUT entry 102 high"
|
|
hexmask.long.tbyte 0x334 0.--17. 1. "LO,Line offset"
|
|
line.long 0x338 "GFXMMU_LUT103L,GFXMMU LUT entry 103 low"
|
|
hexmask.long.byte 0x338 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x338 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x33C "GFXMMU_LUT103H,GFXMMU LUT entry 103 high"
|
|
hexmask.long.tbyte 0x33C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x340 "GFXMMU_LUT104L,GFXMMU LUT entry 104 low"
|
|
hexmask.long.byte 0x340 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x340 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x344 "GFXMMU_LUT104H,GFXMMU LUT entry 104 high"
|
|
hexmask.long.tbyte 0x344 0.--17. 1. "LO,Line offset"
|
|
line.long 0x348 "GFXMMU_LUT105L,GFXMMU LUT entry 105 low"
|
|
hexmask.long.byte 0x348 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x348 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x34C "GFXMMU_LUT105H,GFXMMU LUT entry 105 high"
|
|
hexmask.long.tbyte 0x34C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x350 "GFXMMU_LUT106L,GFXMMU LUT entry 106 low"
|
|
hexmask.long.byte 0x350 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x350 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x354 "GFXMMU_LUT106H,GFXMMU LUT entry 106 high"
|
|
hexmask.long.tbyte 0x354 0.--17. 1. "LO,Line offset"
|
|
line.long 0x358 "GFXMMU_LUT107L,GFXMMU LUT entry 107 low"
|
|
hexmask.long.byte 0x358 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x358 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x35C "GFXMMU_LUT107H,GFXMMU LUT entry 107 high"
|
|
hexmask.long.tbyte 0x35C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x360 "GFXMMU_LUT108L,GFXMMU LUT entry 108 low"
|
|
hexmask.long.byte 0x360 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x360 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x364 "GFXMMU_LUT108H,GFXMMU LUT entry 108 high"
|
|
hexmask.long.tbyte 0x364 0.--17. 1. "LO,Line offset"
|
|
line.long 0x368 "GFXMMU_LUT109L,GFXMMU LUT entry 109 low"
|
|
hexmask.long.byte 0x368 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x368 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x36C "GFXMMU_LUT109H,GFXMMU LUT entry 109 high"
|
|
hexmask.long.tbyte 0x36C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x370 "GFXMMU_LUT110L,GFXMMU LUT entry 110 low"
|
|
hexmask.long.byte 0x370 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x370 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x374 "GFXMMU_LUT110H,GFXMMU LUT entry 110 high"
|
|
hexmask.long.tbyte 0x374 0.--17. 1. "LO,Line offset"
|
|
line.long 0x378 "GFXMMU_LUT111L,GFXMMU LUT entry 111 low"
|
|
hexmask.long.byte 0x378 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x378 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x37C "GFXMMU_LUT111H,GFXMMU LUT entry 111 high"
|
|
hexmask.long.tbyte 0x37C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x380 "GFXMMU_LUT112L,GFXMMU LUT entry 112 low"
|
|
hexmask.long.byte 0x380 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x380 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x384 "GFXMMU_LUT112H,GFXMMU LUT entry 112 high"
|
|
hexmask.long.tbyte 0x384 0.--17. 1. "LO,Line offset"
|
|
line.long 0x388 "GFXMMU_LUT113L,GFXMMU LUT entry 113 low"
|
|
hexmask.long.byte 0x388 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x388 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x38C "GFXMMU_LUT113H,GFXMMU LUT entry 113 high"
|
|
hexmask.long.tbyte 0x38C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x390 "GFXMMU_LUT114L,GFXMMU LUT entry 114 low"
|
|
hexmask.long.byte 0x390 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x390 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x394 "GFXMMU_LUT114H,GFXMMU LUT entry 114 high"
|
|
hexmask.long.tbyte 0x394 0.--17. 1. "LO,Line offset"
|
|
line.long 0x398 "GFXMMU_LUT115L,GFXMMU LUT entry 115 low"
|
|
hexmask.long.byte 0x398 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x398 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x39C "GFXMMU_LUT115H,GFXMMU LUT entry 115 high"
|
|
hexmask.long.tbyte 0x39C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3A0 "GFXMMU_LUT116L,GFXMMU LUT entry 116 low"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3A4 "GFXMMU_LUT116H,GFXMMU LUT entry 116 high"
|
|
hexmask.long.tbyte 0x3A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3A8 "GFXMMU_LUT117L,GFXMMU LUT entry 117 low"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3AC "GFXMMU_LUT117H,GFXMMU LUT entry 117 high"
|
|
hexmask.long.tbyte 0x3AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3B0 "GFXMMU_LUT118L,GFXMMU LUT entry 118 low"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3B4 "GFXMMU_LUT118H,GFXMMU LUT entry 118 high"
|
|
hexmask.long.tbyte 0x3B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3B8 "GFXMMU_LUT119L,GFXMMU LUT entry 119 low"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3BC "GFXMMU_LUT119H,GFXMMU LUT entry 119 high"
|
|
hexmask.long.tbyte 0x3BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3C0 "GFXMMU_LUT120L,GFXMMU LUT entry 120 low"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3C4 "GFXMMU_LUT120H,GFXMMU LUT entry 120 high"
|
|
hexmask.long.tbyte 0x3C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3C8 "GFXMMU_LUT121L,GFXMMU LUT entry 121 low"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3CC "GFXMMU_LUT121H,GFXMMU LUT entry 121 high"
|
|
hexmask.long.tbyte 0x3CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3D0 "GFXMMU_LUT122L,GFXMMU LUT entry 122 low"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3D4 "GFXMMU_LUT122H,GFXMMU LUT entry 122 high"
|
|
hexmask.long.tbyte 0x3D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3D8 "GFXMMU_LUT123L,GFXMMU LUT entry 123 low"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3DC "GFXMMU_LUT123H,GFXMMU LUT entry 123 high"
|
|
hexmask.long.tbyte 0x3DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3E0 "GFXMMU_LUT124L,GFXMMU LUT entry 124 low"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3E4 "GFXMMU_LUT124H,GFXMMU LUT entry 124 high"
|
|
hexmask.long.tbyte 0x3E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3E8 "GFXMMU_LUT125L,GFXMMU LUT entry 125 low"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3EC "GFXMMU_LUT125H,GFXMMU LUT entry 125 high"
|
|
hexmask.long.tbyte 0x3EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3F0 "GFXMMU_LUT126L,GFXMMU LUT entry 126 low"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3F4 "GFXMMU_LUT126H,GFXMMU LUT entry 126 high"
|
|
hexmask.long.tbyte 0x3F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3F8 "GFXMMU_LUT127L,GFXMMU LUT entry 127 low"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3FC "GFXMMU_LUT127H,GFXMMU LUT entry 127 high"
|
|
hexmask.long.tbyte 0x3FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x400 "GFXMMU_LUT128L,GFXMMU LUT entry 128 low"
|
|
hexmask.long.byte 0x400 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x400 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x404 "GFXMMU_LUT128H,GFXMMU LUT entry 128 high"
|
|
hexmask.long.tbyte 0x404 0.--17. 1. "LO,Line offset"
|
|
line.long 0x408 "GFXMMU_LUT129L,GFXMMU LUT entry 129 low"
|
|
hexmask.long.byte 0x408 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x408 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x40C "GFXMMU_LUT129H,GFXMMU LUT entry 129 high"
|
|
hexmask.long.tbyte 0x40C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x410 "GFXMMU_LUT130L,GFXMMU LUT entry 130 low"
|
|
hexmask.long.byte 0x410 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x410 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x414 "GFXMMU_LUT130H,GFXMMU LUT entry 130 high"
|
|
hexmask.long.tbyte 0x414 0.--17. 1. "LO,Line offset"
|
|
line.long 0x418 "GFXMMU_LUT131L,GFXMMU LUT entry 131 low"
|
|
hexmask.long.byte 0x418 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x418 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x41C "GFXMMU_LUT131H,GFXMMU LUT entry 131 high"
|
|
hexmask.long.tbyte 0x41C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x420 "GFXMMU_LUT132L,GFXMMU LUT entry 132 low"
|
|
hexmask.long.byte 0x420 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x420 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x424 "GFXMMU_LUT132H,GFXMMU LUT entry 132 high"
|
|
hexmask.long.tbyte 0x424 0.--17. 1. "LO,Line offset"
|
|
line.long 0x428 "GFXMMU_LUT133L,GFXMMU LUT entry 133 low"
|
|
hexmask.long.byte 0x428 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x428 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x42C "GFXMMU_LUT133H,GFXMMU LUT entry 133 high"
|
|
hexmask.long.tbyte 0x42C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x430 "GFXMMU_LUT134L,GFXMMU LUT entry 134 low"
|
|
hexmask.long.byte 0x430 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x430 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x434 "GFXMMU_LUT134H,GFXMMU LUT entry 134 high"
|
|
hexmask.long.tbyte 0x434 0.--17. 1. "LO,Line offset"
|
|
line.long 0x438 "GFXMMU_LUT135L,GFXMMU LUT entry 135 low"
|
|
hexmask.long.byte 0x438 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x438 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x43C "GFXMMU_LUT135H,GFXMMU LUT entry 135 high"
|
|
hexmask.long.tbyte 0x43C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x440 "GFXMMU_LUT136L,GFXMMU LUT entry 136 low"
|
|
hexmask.long.byte 0x440 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x440 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x444 "GFXMMU_LUT136H,GFXMMU LUT entry 136 high"
|
|
hexmask.long.tbyte 0x444 0.--17. 1. "LO,Line offset"
|
|
line.long 0x448 "GFXMMU_LUT137L,GFXMMU LUT entry 137 low"
|
|
hexmask.long.byte 0x448 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x448 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x44C "GFXMMU_LUT137H,GFXMMU LUT entry 137 high"
|
|
hexmask.long.tbyte 0x44C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x450 "GFXMMU_LUT138L,GFXMMU LUT entry 138 low"
|
|
hexmask.long.byte 0x450 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x450 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x454 "GFXMMU_LUT138H,GFXMMU LUT entry 138 high"
|
|
hexmask.long.tbyte 0x454 0.--17. 1. "LO,Line offset"
|
|
line.long 0x458 "GFXMMU_LUT139L,GFXMMU LUT entry 139 low"
|
|
hexmask.long.byte 0x458 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x458 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x45C "GFXMMU_LUT139H,GFXMMU LUT entry 139 high"
|
|
hexmask.long.tbyte 0x45C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x460 "GFXMMU_LUT140L,GFXMMU LUT entry 140 low"
|
|
hexmask.long.byte 0x460 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x460 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x464 "GFXMMU_LUT140H,GFXMMU LUT entry 140 high"
|
|
hexmask.long.tbyte 0x464 0.--17. 1. "LO,Line offset"
|
|
line.long 0x468 "GFXMMU_LUT141L,GFXMMU LUT entry 141 low"
|
|
hexmask.long.byte 0x468 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x468 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x46C "GFXMMU_LUT141H,GFXMMU LUT entry 141 high"
|
|
hexmask.long.tbyte 0x46C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x470 "GFXMMU_LUT142L,GFXMMU LUT entry 142 low"
|
|
hexmask.long.byte 0x470 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x470 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x474 "GFXMMU_LUT142H,GFXMMU LUT entry 142 high"
|
|
hexmask.long.tbyte 0x474 0.--17. 1. "LO,Line offset"
|
|
line.long 0x478 "GFXMMU_LUT143L,GFXMMU LUT entry 143 low"
|
|
hexmask.long.byte 0x478 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x478 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x47C "GFXMMU_LUT143H,GFXMMU LUT entry 143 high"
|
|
hexmask.long.tbyte 0x47C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x480 "GFXMMU_LUT144L,GFXMMU LUT entry 144 low"
|
|
hexmask.long.byte 0x480 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x480 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x484 "GFXMMU_LUT144H,GFXMMU LUT entry 144 high"
|
|
hexmask.long.tbyte 0x484 0.--17. 1. "LO,Line offset"
|
|
line.long 0x488 "GFXMMU_LUT145L,GFXMMU LUT entry 145 low"
|
|
hexmask.long.byte 0x488 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x488 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x48C "GFXMMU_LUT145H,GFXMMU LUT entry 145 high"
|
|
hexmask.long.tbyte 0x48C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x490 "GFXMMU_LUT146L,GFXMMU LUT entry 146 low"
|
|
hexmask.long.byte 0x490 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x490 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x494 "GFXMMU_LUT146H,GFXMMU LUT entry 146 high"
|
|
hexmask.long.tbyte 0x494 0.--17. 1. "LO,Line offset"
|
|
line.long 0x498 "GFXMMU_LUT147L,GFXMMU LUT entry 147 low"
|
|
hexmask.long.byte 0x498 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x498 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x49C "GFXMMU_LUT147H,GFXMMU LUT entry 147 high"
|
|
hexmask.long.tbyte 0x49C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4A0 "GFXMMU_LUT148L,GFXMMU LUT entry 148 low"
|
|
hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4A4 "GFXMMU_LUT148H,GFXMMU LUT entry 148 high"
|
|
hexmask.long.tbyte 0x4A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4A8 "GFXMMU_LUT149L,GFXMMU LUT entry 149 low"
|
|
hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4AC "GFXMMU_LUT149H,GFXMMU LUT entry 149 high"
|
|
hexmask.long.tbyte 0x4AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4B0 "GFXMMU_LUT150L,GFXMMU LUT entry 150 low"
|
|
hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4B4 "GFXMMU_LUT150H,GFXMMU LUT entry 150 high"
|
|
hexmask.long.tbyte 0x4B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4B8 "GFXMMU_LUT151L,GFXMMU LUT entry 151 low"
|
|
hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4BC "GFXMMU_LUT151H,GFXMMU LUT entry 151 high"
|
|
hexmask.long.tbyte 0x4BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4C0 "GFXMMU_LUT152L,GFXMMU LUT entry 152 low"
|
|
hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4C4 "GFXMMU_LUT152H,GFXMMU LUT entry 152 high"
|
|
hexmask.long.tbyte 0x4C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4C8 "GFXMMU_LUT153L,GFXMMU LUT entry 153 low"
|
|
hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4CC "GFXMMU_LUT153H,GFXMMU LUT entry 153 high"
|
|
hexmask.long.tbyte 0x4CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4D0 "GFXMMU_LUT154L,GFXMMU LUT entry 154 low"
|
|
hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4D4 "GFXMMU_LUT154H,GFXMMU LUT entry 154 high"
|
|
hexmask.long.tbyte 0x4D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4D8 "GFXMMU_LUT155L,GFXMMU LUT entry 155 low"
|
|
hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4DC "GFXMMU_LUT155H,GFXMMU LUT entry 155 high"
|
|
hexmask.long.tbyte 0x4DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4E0 "GFXMMU_LUT156L,GFXMMU LUT entry 156 low"
|
|
hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4E4 "GFXMMU_LUT156H,GFXMMU LUT entry 156 high"
|
|
hexmask.long.tbyte 0x4E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4E8 "GFXMMU_LUT157L,GFXMMU LUT entry 157 low"
|
|
hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4EC "GFXMMU_LUT157H,GFXMMU LUT entry 157 high"
|
|
hexmask.long.tbyte 0x4EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4F0 "GFXMMU_LUT158L,GFXMMU LUT entry 158 low"
|
|
hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4F4 "GFXMMU_LUT158H,GFXMMU LUT entry 158 high"
|
|
hexmask.long.tbyte 0x4F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4F8 "GFXMMU_LUT159L,GFXMMU LUT entry 159 low"
|
|
hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4FC "GFXMMU_LUT159H,GFXMMU LUT entry 159 high"
|
|
hexmask.long.tbyte 0x4FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x500 "GFXMMU_LUT160L,GFXMMU LUT entry 160 low"
|
|
hexmask.long.byte 0x500 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x500 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x504 "GFXMMU_LUT160H,GFXMMU LUT entry 160 high"
|
|
hexmask.long.tbyte 0x504 0.--17. 1. "LO,Line offset"
|
|
line.long 0x508 "GFXMMU_LUT161L,GFXMMU LUT entry 161 low"
|
|
hexmask.long.byte 0x508 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x508 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x50C "GFXMMU_LUT161H,GFXMMU LUT entry 161 high"
|
|
hexmask.long.tbyte 0x50C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x510 "GFXMMU_LUT162L,GFXMMU LUT entry 162 low"
|
|
hexmask.long.byte 0x510 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x510 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x514 "GFXMMU_LUT162H,GFXMMU LUT entry 162 high"
|
|
hexmask.long.tbyte 0x514 0.--17. 1. "LO,Line offset"
|
|
line.long 0x518 "GFXMMU_LUT163L,GFXMMU LUT entry 163 low"
|
|
hexmask.long.byte 0x518 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x518 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x51C "GFXMMU_LUT163H,GFXMMU LUT entry 163 high"
|
|
hexmask.long.tbyte 0x51C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x520 "GFXMMU_LUT164L,GFXMMU LUT entry 164 low"
|
|
hexmask.long.byte 0x520 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x520 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x524 "GFXMMU_LUT164H,GFXMMU LUT entry 164 high"
|
|
hexmask.long.tbyte 0x524 0.--17. 1. "LO,Line offset"
|
|
line.long 0x528 "GFXMMU_LUT165L,GFXMMU LUT entry 165 low"
|
|
hexmask.long.byte 0x528 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x528 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x52C "GFXMMU_LUT165H,GFXMMU LUT entry 165 high"
|
|
hexmask.long.tbyte 0x52C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x530 "GFXMMU_LUT166L,GFXMMU LUT entry 166 low"
|
|
hexmask.long.byte 0x530 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x530 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x534 "GFXMMU_LUT166H,GFXMMU LUT entry 166 high"
|
|
hexmask.long.tbyte 0x534 0.--17. 1. "LO,Line offset"
|
|
line.long 0x538 "GFXMMU_LUT167L,GFXMMU LUT entry 167 low"
|
|
hexmask.long.byte 0x538 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x538 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x53C "GFXMMU_LUT167H,GFXMMU LUT entry 167 high"
|
|
hexmask.long.tbyte 0x53C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x540 "GFXMMU_LUT168L,GFXMMU LUT entry 168 low"
|
|
hexmask.long.byte 0x540 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x540 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x544 "GFXMMU_LUT168H,GFXMMU LUT entry 168 high"
|
|
hexmask.long.tbyte 0x544 0.--17. 1. "LO,Line offset"
|
|
line.long 0x548 "GFXMMU_LUT169L,GFXMMU LUT entry 169 low"
|
|
hexmask.long.byte 0x548 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x548 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x54C "GFXMMU_LUT169H,GFXMMU LUT entry 169 high"
|
|
hexmask.long.tbyte 0x54C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x550 "GFXMMU_LUT170L,GFXMMU LUT entry 170 low"
|
|
hexmask.long.byte 0x550 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x550 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x554 "GFXMMU_LUT170H,GFXMMU LUT entry 170 high"
|
|
hexmask.long.tbyte 0x554 0.--17. 1. "LO,Line offset"
|
|
line.long 0x558 "GFXMMU_LUT171L,GFXMMU LUT entry 171 low"
|
|
hexmask.long.byte 0x558 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x558 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x55C "GFXMMU_LUT171H,GFXMMU LUT entry 171 high"
|
|
hexmask.long.tbyte 0x55C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x560 "GFXMMU_LUT172L,GFXMMU LUT entry 172 low"
|
|
hexmask.long.byte 0x560 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x560 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x564 "GFXMMU_LUT172H,GFXMMU LUT entry 172 high"
|
|
hexmask.long.tbyte 0x564 0.--17. 1. "LO,Line offset"
|
|
line.long 0x568 "GFXMMU_LUT173L,GFXMMU LUT entry 173 low"
|
|
hexmask.long.byte 0x568 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x568 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x56C "GFXMMU_LUT173H,GFXMMU LUT entry 173 high"
|
|
hexmask.long.tbyte 0x56C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x570 "GFXMMU_LUT174L,GFXMMU LUT entry 174 low"
|
|
hexmask.long.byte 0x570 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x570 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x574 "GFXMMU_LUT174H,GFXMMU LUT entry 174 high"
|
|
hexmask.long.tbyte 0x574 0.--17. 1. "LO,Line offset"
|
|
line.long 0x578 "GFXMMU_LUT175L,GFXMMU LUT entry 175 low"
|
|
hexmask.long.byte 0x578 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x578 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x57C "GFXMMU_LUT175H,GFXMMU LUT entry 175 high"
|
|
hexmask.long.tbyte 0x57C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x580 "GFXMMU_LUT176L,GFXMMU LUT entry 176 low"
|
|
hexmask.long.byte 0x580 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x580 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x584 "GFXMMU_LUT176H,GFXMMU LUT entry 176 high"
|
|
hexmask.long.tbyte 0x584 0.--17. 1. "LO,Line offset"
|
|
line.long 0x588 "GFXMMU_LUT177L,GFXMMU LUT entry 177 low"
|
|
hexmask.long.byte 0x588 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x588 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x58C "GFXMMU_LUT177H,GFXMMU LUT entry 177 high"
|
|
hexmask.long.tbyte 0x58C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x590 "GFXMMU_LUT178L,GFXMMU LUT entry 178 low"
|
|
hexmask.long.byte 0x590 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x590 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x594 "GFXMMU_LUT178H,GFXMMU LUT entry 178 high"
|
|
hexmask.long.tbyte 0x594 0.--17. 1. "LO,Line offset"
|
|
line.long 0x598 "GFXMMU_LUT179L,GFXMMU LUT entry 179 low"
|
|
hexmask.long.byte 0x598 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x598 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x59C "GFXMMU_LUT179H,GFXMMU LUT entry 179 high"
|
|
hexmask.long.tbyte 0x59C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5A0 "GFXMMU_LUT180L,GFXMMU LUT entry 180 low"
|
|
hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5A4 "GFXMMU_LUT180H,GFXMMU LUT entry 180 high"
|
|
hexmask.long.tbyte 0x5A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5A8 "GFXMMU_LUT181L,GFXMMU LUT entry 181 low"
|
|
hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5AC "GFXMMU_LUT181H,GFXMMU LUT entry 181 high"
|
|
hexmask.long.tbyte 0x5AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5B0 "GFXMMU_LUT182L,GFXMMU LUT entry 182 low"
|
|
hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5B4 "GFXMMU_LUT182H,GFXMMU LUT entry 182 high"
|
|
hexmask.long.tbyte 0x5B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5B8 "GFXMMU_LUT183L,GFXMMU LUT entry 183 low"
|
|
hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5BC "GFXMMU_LUT183H,GFXMMU LUT entry 183 high"
|
|
hexmask.long.tbyte 0x5BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5C0 "GFXMMU_LUT184L,GFXMMU LUT entry 184 low"
|
|
hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5C4 "GFXMMU_LUT184H,GFXMMU LUT entry 184 high"
|
|
hexmask.long.tbyte 0x5C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5C8 "GFXMMU_LUT185L,GFXMMU LUT entry 185 low"
|
|
hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5CC "GFXMMU_LUT185H,GFXMMU LUT entry 185 high"
|
|
hexmask.long.tbyte 0x5CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5D0 "GFXMMU_LUT186L,GFXMMU LUT entry 186 low"
|
|
hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5D4 "GFXMMU_LUT186H,GFXMMU LUT entry 186 high"
|
|
hexmask.long.tbyte 0x5D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5D8 "GFXMMU_LUT187L,GFXMMU LUT entry 187 low"
|
|
hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5DC "GFXMMU_LUT187H,GFXMMU LUT entry 187 high"
|
|
hexmask.long.tbyte 0x5DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5E0 "GFXMMU_LUT188L,GFXMMU LUT entry 188 low"
|
|
hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5E4 "GFXMMU_LUT188H,GFXMMU LUT entry 188 high"
|
|
hexmask.long.tbyte 0x5E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5E8 "GFXMMU_LUT189L,GFXMMU LUT entry 189 low"
|
|
hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5EC "GFXMMU_LUT189H,GFXMMU LUT entry 189 high"
|
|
hexmask.long.tbyte 0x5EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5F0 "GFXMMU_LUT190L,GFXMMU LUT entry 190 low"
|
|
hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5F4 "GFXMMU_LUT190H,GFXMMU LUT entry 190 high"
|
|
hexmask.long.tbyte 0x5F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5F8 "GFXMMU_LUT191L,GFXMMU LUT entry 191 low"
|
|
hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5FC "GFXMMU_LUT191H,GFXMMU LUT entry 191 high"
|
|
hexmask.long.tbyte 0x5FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x600 "GFXMMU_LUT192L,GFXMMU LUT entry 192 low"
|
|
hexmask.long.byte 0x600 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x600 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x604 "GFXMMU_LUT192H,GFXMMU LUT entry 192 high"
|
|
hexmask.long.tbyte 0x604 0.--17. 1. "LO,Line offset"
|
|
line.long 0x608 "GFXMMU_LUT193L,GFXMMU LUT entry 193 low"
|
|
hexmask.long.byte 0x608 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x608 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x60C "GFXMMU_LUT193H,GFXMMU LUT entry 193 high"
|
|
hexmask.long.tbyte 0x60C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x610 "GFXMMU_LUT194L,GFXMMU LUT entry 194 low"
|
|
hexmask.long.byte 0x610 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x610 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x614 "GFXMMU_LUT194H,GFXMMU LUT entry 194 high"
|
|
hexmask.long.tbyte 0x614 0.--17. 1. "LO,Line offset"
|
|
line.long 0x618 "GFXMMU_LUT195L,GFXMMU LUT entry 195 low"
|
|
hexmask.long.byte 0x618 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x618 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x61C "GFXMMU_LUT195H,GFXMMU LUT entry 195 high"
|
|
hexmask.long.tbyte 0x61C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x620 "GFXMMU_LUT196L,GFXMMU LUT entry 196 low"
|
|
hexmask.long.byte 0x620 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x620 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x624 "GFXMMU_LUT196H,GFXMMU LUT entry 196 high"
|
|
hexmask.long.tbyte 0x624 0.--17. 1. "LO,Line offset"
|
|
line.long 0x628 "GFXMMU_LUT197L,GFXMMU LUT entry 197 low"
|
|
hexmask.long.byte 0x628 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x628 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x62C "GFXMMU_LUT197H,GFXMMU LUT entry 197 high"
|
|
hexmask.long.tbyte 0x62C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x630 "GFXMMU_LUT198L,GFXMMU LUT entry 198 low"
|
|
hexmask.long.byte 0x630 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x630 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x634 "GFXMMU_LUT198H,GFXMMU LUT entry 198 high"
|
|
hexmask.long.tbyte 0x634 0.--17. 1. "LO,Line offset"
|
|
line.long 0x638 "GFXMMU_LUT199L,GFXMMU LUT entry 199 low"
|
|
hexmask.long.byte 0x638 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x638 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x63C "GFXMMU_LUT199H,GFXMMU LUT entry 199 high"
|
|
hexmask.long.tbyte 0x63C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x640 "GFXMMU_LUT200L,GFXMMU LUT entry 200 low"
|
|
hexmask.long.byte 0x640 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x640 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x644 "GFXMMU_LUT200H,GFXMMU LUT entry 200 high"
|
|
hexmask.long.tbyte 0x644 0.--17. 1. "LO,Line offset"
|
|
line.long 0x648 "GFXMMU_LUT201L,GFXMMU LUT entry 201 low"
|
|
hexmask.long.byte 0x648 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x648 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x64C "GFXMMU_LUT201H,GFXMMU LUT entry 201 high"
|
|
hexmask.long.tbyte 0x64C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x650 "GFXMMU_LUT202L,GFXMMU LUT entry 202 low"
|
|
hexmask.long.byte 0x650 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x650 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x654 "GFXMMU_LUT202H,GFXMMU LUT entry 202 high"
|
|
hexmask.long.tbyte 0x654 0.--17. 1. "LO,Line offset"
|
|
line.long 0x658 "GFXMMU_LUT203L,GFXMMU LUT entry 203 low"
|
|
hexmask.long.byte 0x658 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x658 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x65C "GFXMMU_LUT203H,GFXMMU LUT entry 203 high"
|
|
hexmask.long.tbyte 0x65C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x660 "GFXMMU_LUT204L,GFXMMU LUT entry 204 low"
|
|
hexmask.long.byte 0x660 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x660 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x664 "GFXMMU_LUT204H,GFXMMU LUT entry 204 high"
|
|
hexmask.long.tbyte 0x664 0.--17. 1. "LO,Line offset"
|
|
line.long 0x668 "GFXMMU_LUT205L,GFXMMU LUT entry 205 low"
|
|
hexmask.long.byte 0x668 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x668 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x66C "GFXMMU_LUT205H,GFXMMU LUT entry 205 high"
|
|
hexmask.long.tbyte 0x66C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x670 "GFXMMU_LUT206L,GFXMMU LUT entry 206 low"
|
|
hexmask.long.byte 0x670 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x670 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x674 "GFXMMU_LUT206H,GFXMMU LUT entry 206 high"
|
|
hexmask.long.tbyte 0x674 0.--17. 1. "LO,Line offset"
|
|
line.long 0x678 "GFXMMU_LUT207L,GFXMMU LUT entry 207 low"
|
|
hexmask.long.byte 0x678 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x678 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x67C "GFXMMU_LUT207H,GFXMMU LUT entry 207 high"
|
|
hexmask.long.tbyte 0x67C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x680 "GFXMMU_LUT208L,GFXMMU LUT entry 208 low"
|
|
hexmask.long.byte 0x680 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x680 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x684 "GFXMMU_LUT208H,GFXMMU LUT entry 208 high"
|
|
hexmask.long.tbyte 0x684 0.--17. 1. "LO,Line offset"
|
|
line.long 0x688 "GFXMMU_LUT209L,GFXMMU LUT entry 209 low"
|
|
hexmask.long.byte 0x688 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x688 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x68C "GFXMMU_LUT209H,GFXMMU LUT entry 209 high"
|
|
hexmask.long.tbyte 0x68C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x690 "GFXMMU_LUT210L,GFXMMU LUT entry 210 low"
|
|
hexmask.long.byte 0x690 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x690 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x694 "GFXMMU_LUT210H,GFXMMU LUT entry 210 high"
|
|
hexmask.long.tbyte 0x694 0.--17. 1. "LO,Line offset"
|
|
line.long 0x698 "GFXMMU_LUT211L,GFXMMU LUT entry 211 low"
|
|
hexmask.long.byte 0x698 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x698 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x69C "GFXMMU_LUT211H,GFXMMU LUT entry 211 high"
|
|
hexmask.long.tbyte 0x69C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6A0 "GFXMMU_LUT212L,GFXMMU LUT entry 212 low"
|
|
hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6A4 "GFXMMU_LUT212H,GFXMMU LUT entry 212 high"
|
|
hexmask.long.tbyte 0x6A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6A8 "GFXMMU_LUT213L,GFXMMU LUT entry 213 low"
|
|
hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6AC "GFXMMU_LUT213H,GFXMMU LUT entry 213 high"
|
|
hexmask.long.tbyte 0x6AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6B0 "GFXMMU_LUT214L,GFXMMU LUT entry 214 low"
|
|
hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6B4 "GFXMMU_LUT214H,GFXMMU LUT entry 214 high"
|
|
hexmask.long.tbyte 0x6B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6B8 "GFXMMU_LUT215L,GFXMMU LUT entry 215 low"
|
|
hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6BC "GFXMMU_LUT215H,GFXMMU LUT entry 215 high"
|
|
hexmask.long.tbyte 0x6BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6C0 "GFXMMU_LUT216L,GFXMMU LUT entry 216 low"
|
|
hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6C4 "GFXMMU_LUT216H,GFXMMU LUT entry 216 high"
|
|
hexmask.long.tbyte 0x6C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6C8 "GFXMMU_LUT217L,GFXMMU LUT entry 217 low"
|
|
hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6CC "GFXMMU_LUT217H,GFXMMU LUT entry 217 high"
|
|
hexmask.long.tbyte 0x6CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6D0 "GFXMMU_LUT218L,GFXMMU LUT entry 218 low"
|
|
hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6D4 "GFXMMU_LUT218H,GFXMMU LUT entry 218 high"
|
|
hexmask.long.tbyte 0x6D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6D8 "GFXMMU_LUT219L,GFXMMU LUT entry 219 low"
|
|
hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6DC "GFXMMU_LUT219H,GFXMMU LUT entry 219 high"
|
|
hexmask.long.tbyte 0x6DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6E0 "GFXMMU_LUT220L,GFXMMU LUT entry 220 low"
|
|
hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6E4 "GFXMMU_LUT220H,GFXMMU LUT entry 220 high"
|
|
hexmask.long.tbyte 0x6E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6E8 "GFXMMU_LUT221L,GFXMMU LUT entry 221 low"
|
|
hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6EC "GFXMMU_LUT221H,GFXMMU LUT entry 221 high"
|
|
hexmask.long.tbyte 0x6EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6F0 "GFXMMU_LUT222L,GFXMMU LUT entry 222 low"
|
|
hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6F4 "GFXMMU_LUT222H,GFXMMU LUT entry 222 high"
|
|
hexmask.long.tbyte 0x6F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6F8 "GFXMMU_LUT223L,GFXMMU LUT entry 223 low"
|
|
hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6FC "GFXMMU_LUT223H,GFXMMU LUT entry 223 high"
|
|
hexmask.long.tbyte 0x6FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x700 "GFXMMU_LUT224L,GFXMMU LUT entry 224 low"
|
|
hexmask.long.byte 0x700 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x700 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x704 "GFXMMU_LUT224H,GFXMMU LUT entry 224 high"
|
|
hexmask.long.tbyte 0x704 0.--17. 1. "LO,Line offset"
|
|
line.long 0x708 "GFXMMU_LUT225L,GFXMMU LUT entry 225 low"
|
|
hexmask.long.byte 0x708 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x708 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x70C "GFXMMU_LUT225H,GFXMMU LUT entry 225 high"
|
|
hexmask.long.tbyte 0x70C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x710 "GFXMMU_LUT226L,GFXMMU LUT entry 226 low"
|
|
hexmask.long.byte 0x710 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x710 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x714 "GFXMMU_LUT226H,GFXMMU LUT entry 226 high"
|
|
hexmask.long.tbyte 0x714 0.--17. 1. "LO,Line offset"
|
|
line.long 0x718 "GFXMMU_LUT227L,GFXMMU LUT entry 227 low"
|
|
hexmask.long.byte 0x718 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x718 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x71C "GFXMMU_LUT227H,GFXMMU LUT entry 227 high"
|
|
hexmask.long.tbyte 0x71C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x720 "GFXMMU_LUT228L,GFXMMU LUT entry 228 low"
|
|
hexmask.long.byte 0x720 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x720 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x724 "GFXMMU_LUT228H,GFXMMU LUT entry 228 high"
|
|
hexmask.long.tbyte 0x724 0.--17. 1. "LO,Line offset"
|
|
line.long 0x728 "GFXMMU_LUT229L,GFXMMU LUT entry 229 low"
|
|
hexmask.long.byte 0x728 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x728 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x72C "GFXMMU_LUT229H,GFXMMU LUT entry 229 high"
|
|
hexmask.long.tbyte 0x72C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x730 "GFXMMU_LUT230L,GFXMMU LUT entry 230 low"
|
|
hexmask.long.byte 0x730 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x730 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x734 "GFXMMU_LUT230H,GFXMMU LUT entry 230 high"
|
|
hexmask.long.tbyte 0x734 0.--17. 1. "LO,Line offset"
|
|
line.long 0x738 "GFXMMU_LUT231L,GFXMMU LUT entry 231 low"
|
|
hexmask.long.byte 0x738 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x738 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x73C "GFXMMU_LUT231H,GFXMMU LUT entry 231 high"
|
|
hexmask.long.tbyte 0x73C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x740 "GFXMMU_LUT232L,GFXMMU LUT entry 232 low"
|
|
hexmask.long.byte 0x740 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x740 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x744 "GFXMMU_LUT232H,GFXMMU LUT entry 232 high"
|
|
hexmask.long.tbyte 0x744 0.--17. 1. "LO,Line offset"
|
|
line.long 0x748 "GFXMMU_LUT233L,GFXMMU LUT entry 233 low"
|
|
hexmask.long.byte 0x748 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x748 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x74C "GFXMMU_LUT233H,GFXMMU LUT entry 233 high"
|
|
hexmask.long.tbyte 0x74C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x750 "GFXMMU_LUT234L,GFXMMU LUT entry 234 low"
|
|
hexmask.long.byte 0x750 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x750 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x754 "GFXMMU_LUT234H,GFXMMU LUT entry 234 high"
|
|
hexmask.long.tbyte 0x754 0.--17. 1. "LO,Line offset"
|
|
line.long 0x758 "GFXMMU_LUT235L,GFXMMU LUT entry 235 low"
|
|
hexmask.long.byte 0x758 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x758 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x75C "GFXMMU_LUT235H,GFXMMU LUT entry 235 high"
|
|
hexmask.long.tbyte 0x75C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x760 "GFXMMU_LUT236L,GFXMMU LUT entry 236 low"
|
|
hexmask.long.byte 0x760 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x760 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x764 "GFXMMU_LUT236H,GFXMMU LUT entry 236 high"
|
|
hexmask.long.tbyte 0x764 0.--17. 1. "LO,Line offset"
|
|
line.long 0x768 "GFXMMU_LUT237L,GFXMMU LUT entry 237 low"
|
|
hexmask.long.byte 0x768 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x768 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x76C "GFXMMU_LUT237H,GFXMMU LUT entry 237 high"
|
|
hexmask.long.tbyte 0x76C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x770 "GFXMMU_LUT238L,GFXMMU LUT entry 238 low"
|
|
hexmask.long.byte 0x770 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x770 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x774 "GFXMMU_LUT238H,GFXMMU LUT entry 238 high"
|
|
hexmask.long.tbyte 0x774 0.--17. 1. "LO,Line offset"
|
|
line.long 0x778 "GFXMMU_LUT239L,GFXMMU LUT entry 239 low"
|
|
hexmask.long.byte 0x778 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x778 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x77C "GFXMMU_LUT239H,GFXMMU LUT entry 239 high"
|
|
hexmask.long.tbyte 0x77C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x780 "GFXMMU_LUT240L,GFXMMU LUT entry 240 low"
|
|
hexmask.long.byte 0x780 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x780 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x784 "GFXMMU_LUT240H,GFXMMU LUT entry 240 high"
|
|
hexmask.long.tbyte 0x784 0.--17. 1. "LO,Line offset"
|
|
line.long 0x788 "GFXMMU_LUT241L,GFXMMU LUT entry 241 low"
|
|
hexmask.long.byte 0x788 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x788 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x78C "GFXMMU_LUT241H,GFXMMU LUT entry 241 high"
|
|
hexmask.long.tbyte 0x78C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x790 "GFXMMU_LUT242L,GFXMMU LUT entry 242 low"
|
|
hexmask.long.byte 0x790 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x790 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x794 "GFXMMU_LUT242H,GFXMMU LUT entry 242 high"
|
|
hexmask.long.tbyte 0x794 0.--17. 1. "LO,Line offset"
|
|
line.long 0x798 "GFXMMU_LUT243L,GFXMMU LUT entry 243 low"
|
|
hexmask.long.byte 0x798 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x798 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x79C "GFXMMU_LUT243H,GFXMMU LUT entry 243 high"
|
|
hexmask.long.tbyte 0x79C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7A0 "GFXMMU_LUT244L,GFXMMU LUT entry 244 low"
|
|
hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7A4 "GFXMMU_LUT244H,GFXMMU LUT entry 244 high"
|
|
hexmask.long.tbyte 0x7A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7A8 "GFXMMU_LUT245L,GFXMMU LUT entry 245 low"
|
|
hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7AC "GFXMMU_LUT245H,GFXMMU LUT entry 245 high"
|
|
hexmask.long.tbyte 0x7AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7B0 "GFXMMU_LUT246L,GFXMMU LUT entry 246 low"
|
|
hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7B4 "GFXMMU_LUT246H,GFXMMU LUT entry 246 high"
|
|
hexmask.long.tbyte 0x7B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7B8 "GFXMMU_LUT247L,GFXMMU LUT entry 247 low"
|
|
hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7BC "GFXMMU_LUT247H,GFXMMU LUT entry 247 high"
|
|
hexmask.long.tbyte 0x7BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7C0 "GFXMMU_LUT248L,GFXMMU LUT entry 248 low"
|
|
hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7C4 "GFXMMU_LUT248H,GFXMMU LUT entry 248 high"
|
|
hexmask.long.tbyte 0x7C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7C8 "GFXMMU_LUT249L,GFXMMU LUT entry 249 low"
|
|
hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7CC "GFXMMU_LUT249H,GFXMMU LUT entry 249 high"
|
|
hexmask.long.tbyte 0x7CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7D0 "GFXMMU_LUT250L,GFXMMU LUT entry 250 low"
|
|
hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7D4 "GFXMMU_LUT250H,GFXMMU LUT entry 250 high"
|
|
hexmask.long.tbyte 0x7D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7D8 "GFXMMU_LUT251L,GFXMMU LUT entry 251 low"
|
|
hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7DC "GFXMMU_LUT251H,GFXMMU LUT entry 251 high"
|
|
hexmask.long.tbyte 0x7DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7E0 "GFXMMU_LUT252L,GFXMMU LUT entry 252 low"
|
|
hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7E4 "GFXMMU_LUT252H,GFXMMU LUT entry 252 high"
|
|
hexmask.long.tbyte 0x7E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7E8 "GFXMMU_LUT253L,GFXMMU LUT entry 253 low"
|
|
hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7EC "GFXMMU_LUT253H,GFXMMU LUT entry 253 high"
|
|
hexmask.long.tbyte 0x7EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7F0 "GFXMMU_LUT254L,GFXMMU LUT entry 254 low"
|
|
hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7F4 "GFXMMU_LUT254H,GFXMMU LUT entry 254 high"
|
|
hexmask.long.tbyte 0x7F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7F8 "GFXMMU_LUT255L,GFXMMU LUT entry 255 low"
|
|
hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7FC "GFXMMU_LUT255H,GFXMMU LUT entry 255 high"
|
|
hexmask.long.tbyte 0x7FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x800 "GFXMMU_LUT256L,GFXMMU LUT entry 256 low"
|
|
hexmask.long.byte 0x800 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x800 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x804 "GFXMMU_LUT256H,GFXMMU LUT entry 256 high"
|
|
hexmask.long.tbyte 0x804 0.--17. 1. "LO,Line offset"
|
|
line.long 0x808 "GFXMMU_LUT257L,GFXMMU LUT entry 257 low"
|
|
hexmask.long.byte 0x808 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x808 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x80C "GFXMMU_LUT257H,GFXMMU LUT entry 257 high"
|
|
hexmask.long.tbyte 0x80C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x810 "GFXMMU_LUT258L,GFXMMU LUT entry 258 low"
|
|
hexmask.long.byte 0x810 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x810 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x814 "GFXMMU_LUT258H,GFXMMU LUT entry 258 high"
|
|
hexmask.long.tbyte 0x814 0.--17. 1. "LO,Line offset"
|
|
line.long 0x818 "GFXMMU_LUT259L,GFXMMU LUT entry 259 low"
|
|
hexmask.long.byte 0x818 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x818 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x81C "GFXMMU_LUT259H,GFXMMU LUT entry 259 high"
|
|
hexmask.long.tbyte 0x81C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x820 "GFXMMU_LUT260L,GFXMMU LUT entry 260 low"
|
|
hexmask.long.byte 0x820 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x820 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x824 "GFXMMU_LUT260H,GFXMMU LUT entry 260 high"
|
|
hexmask.long.tbyte 0x824 0.--17. 1. "LO,Line offset"
|
|
line.long 0x828 "GFXMMU_LUT261L,GFXMMU LUT entry 261 low"
|
|
hexmask.long.byte 0x828 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x828 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x82C "GFXMMU_LUT261H,GFXMMU LUT entry 261 high"
|
|
hexmask.long.tbyte 0x82C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x830 "GFXMMU_LUT262L,GFXMMU LUT entry 262 low"
|
|
hexmask.long.byte 0x830 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x830 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x834 "GFXMMU_LUT262H,GFXMMU LUT entry 262 high"
|
|
hexmask.long.tbyte 0x834 0.--17. 1. "LO,Line offset"
|
|
line.long 0x838 "GFXMMU_LUT263L,GFXMMU LUT entry 263 low"
|
|
hexmask.long.byte 0x838 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x838 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x83C "GFXMMU_LUT263H,GFXMMU LUT entry 263 high"
|
|
hexmask.long.tbyte 0x83C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x840 "GFXMMU_LUT264L,GFXMMU LUT entry 264 low"
|
|
hexmask.long.byte 0x840 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x840 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x844 "GFXMMU_LUT264H,GFXMMU LUT entry 264 high"
|
|
hexmask.long.tbyte 0x844 0.--17. 1. "LO,Line offset"
|
|
line.long 0x848 "GFXMMU_LUT265L,GFXMMU LUT entry 265 low"
|
|
hexmask.long.byte 0x848 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x848 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x84C "GFXMMU_LUT265H,GFXMMU LUT entry 265 high"
|
|
hexmask.long.tbyte 0x84C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x850 "GFXMMU_LUT266L,GFXMMU LUT entry 266 low"
|
|
hexmask.long.byte 0x850 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x850 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x854 "GFXMMU_LUT266H,GFXMMU LUT entry 266 high"
|
|
hexmask.long.tbyte 0x854 0.--17. 1. "LO,Line offset"
|
|
line.long 0x858 "GFXMMU_LUT267L,GFXMMU LUT entry 267 low"
|
|
hexmask.long.byte 0x858 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x858 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x85C "GFXMMU_LUT267H,GFXMMU LUT entry 267 high"
|
|
hexmask.long.tbyte 0x85C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x860 "GFXMMU_LUT268L,GFXMMU LUT entry 268 low"
|
|
hexmask.long.byte 0x860 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x860 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x864 "GFXMMU_LUT268H,GFXMMU LUT entry 268 high"
|
|
hexmask.long.tbyte 0x864 0.--17. 1. "LO,Line offset"
|
|
line.long 0x868 "GFXMMU_LUT269L,GFXMMU LUT entry 269 low"
|
|
hexmask.long.byte 0x868 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x868 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x86C "GFXMMU_LUT269H,GFXMMU LUT entry 269 high"
|
|
hexmask.long.tbyte 0x86C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x870 "GFXMMU_LUT270L,GFXMMU LUT entry 270 low"
|
|
hexmask.long.byte 0x870 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x870 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x874 "GFXMMU_LUT270H,GFXMMU LUT entry 270 high"
|
|
hexmask.long.tbyte 0x874 0.--17. 1. "LO,Line offset"
|
|
line.long 0x878 "GFXMMU_LUT271L,GFXMMU LUT entry 271 low"
|
|
hexmask.long.byte 0x878 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x878 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x87C "GFXMMU_LUT271H,GFXMMU LUT entry 271 high"
|
|
hexmask.long.tbyte 0x87C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x880 "GFXMMU_LUT272L,GFXMMU LUT entry 272 low"
|
|
hexmask.long.byte 0x880 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x880 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x884 "GFXMMU_LUT272H,GFXMMU LUT entry 272 high"
|
|
hexmask.long.tbyte 0x884 0.--17. 1. "LO,Line offset"
|
|
line.long 0x888 "GFXMMU_LUT273L,GFXMMU LUT entry 273 low"
|
|
hexmask.long.byte 0x888 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x888 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x88C "GFXMMU_LUT273H,GFXMMU LUT entry 273 high"
|
|
hexmask.long.tbyte 0x88C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x890 "GFXMMU_LUT274L,GFXMMU LUT entry 274 low"
|
|
hexmask.long.byte 0x890 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x890 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x894 "GFXMMU_LUT274H,GFXMMU LUT entry 274 high"
|
|
hexmask.long.tbyte 0x894 0.--17. 1. "LO,Line offset"
|
|
line.long 0x898 "GFXMMU_LUT275L,GFXMMU LUT entry 275 low"
|
|
hexmask.long.byte 0x898 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x898 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x89C "GFXMMU_LUT275H,GFXMMU LUT entry 275 high"
|
|
hexmask.long.tbyte 0x89C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8A0 "GFXMMU_LUT276L,GFXMMU LUT entry 276 low"
|
|
hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8A4 "GFXMMU_LUT276H,GFXMMU LUT entry 276 high"
|
|
hexmask.long.tbyte 0x8A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8A8 "GFXMMU_LUT277L,GFXMMU LUT entry 277 low"
|
|
hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8AC "GFXMMU_LUT277H,GFXMMU LUT entry 277 high"
|
|
hexmask.long.tbyte 0x8AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8B0 "GFXMMU_LUT278L,GFXMMU LUT entry 278 low"
|
|
hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8B4 "GFXMMU_LUT278H,GFXMMU LUT entry 278 high"
|
|
hexmask.long.tbyte 0x8B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8B8 "GFXMMU_LUT279L,GFXMMU LUT entry 279 low"
|
|
hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8BC "GFXMMU_LUT279H,GFXMMU LUT entry 279 high"
|
|
hexmask.long.tbyte 0x8BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8C0 "GFXMMU_LUT280L,GFXMMU LUT entry 280 low"
|
|
hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8C4 "GFXMMU_LUT280H,GFXMMU LUT entry 280 high"
|
|
hexmask.long.tbyte 0x8C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8C8 "GFXMMU_LUT281L,GFXMMU LUT entry 281 low"
|
|
hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8CC "GFXMMU_LUT281H,GFXMMU LUT entry 281 high"
|
|
hexmask.long.tbyte 0x8CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8D0 "GFXMMU_LUT282L,GFXMMU LUT entry 282 low"
|
|
hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8D4 "GFXMMU_LUT282H,GFXMMU LUT entry 282 high"
|
|
hexmask.long.tbyte 0x8D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8D8 "GFXMMU_LUT283L,GFXMMU LUT entry 283 low"
|
|
hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8DC "GFXMMU_LUT283H,GFXMMU LUT entry 283 high"
|
|
hexmask.long.tbyte 0x8DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8E0 "GFXMMU_LUT284L,GFXMMU LUT entry 284 low"
|
|
hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8E4 "GFXMMU_LUT284H,GFXMMU LUT entry 284 high"
|
|
hexmask.long.tbyte 0x8E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8E8 "GFXMMU_LUT285L,GFXMMU LUT entry 285 low"
|
|
hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8EC "GFXMMU_LUT285H,GFXMMU LUT entry 285 high"
|
|
hexmask.long.tbyte 0x8EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8F0 "GFXMMU_LUT286L,GFXMMU LUT entry 286 low"
|
|
hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8F4 "GFXMMU_LUT286H,GFXMMU LUT entry 286 high"
|
|
hexmask.long.tbyte 0x8F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8F8 "GFXMMU_LUT287L,GFXMMU LUT entry 287 low"
|
|
hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8FC "GFXMMU_LUT287H,GFXMMU LUT entry 287 high"
|
|
hexmask.long.tbyte 0x8FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x900 "GFXMMU_LUT288L,GFXMMU LUT entry 288 low"
|
|
hexmask.long.byte 0x900 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x900 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x904 "GFXMMU_LUT288H,GFXMMU LUT entry 288 high"
|
|
hexmask.long.tbyte 0x904 0.--17. 1. "LO,Line offset"
|
|
line.long 0x908 "GFXMMU_LUT289L,GFXMMU LUT entry 289 low"
|
|
hexmask.long.byte 0x908 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x908 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x90C "GFXMMU_LUT289H,GFXMMU LUT entry 289 high"
|
|
hexmask.long.tbyte 0x90C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x910 "GFXMMU_LUT290L,GFXMMU LUT entry 290 low"
|
|
hexmask.long.byte 0x910 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x910 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x914 "GFXMMU_LUT290H,GFXMMU LUT entry 290 high"
|
|
hexmask.long.tbyte 0x914 0.--17. 1. "LO,Line offset"
|
|
line.long 0x918 "GFXMMU_LUT291L,GFXMMU LUT entry 291 low"
|
|
hexmask.long.byte 0x918 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x918 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x91C "GFXMMU_LUT291H,GFXMMU LUT entry 291 high"
|
|
hexmask.long.tbyte 0x91C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x920 "GFXMMU_LUT292L,GFXMMU LUT entry 292 low"
|
|
hexmask.long.byte 0x920 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x920 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x924 "GFXMMU_LUT292H,GFXMMU LUT entry 292 high"
|
|
hexmask.long.tbyte 0x924 0.--17. 1. "LO,Line offset"
|
|
line.long 0x928 "GFXMMU_LUT293L,GFXMMU LUT entry 293 low"
|
|
hexmask.long.byte 0x928 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x928 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x92C "GFXMMU_LUT293H,GFXMMU LUT entry 293 high"
|
|
hexmask.long.tbyte 0x92C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x930 "GFXMMU_LUT294L,GFXMMU LUT entry 294 low"
|
|
hexmask.long.byte 0x930 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x930 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x934 "GFXMMU_LUT294H,GFXMMU LUT entry 294 high"
|
|
hexmask.long.tbyte 0x934 0.--17. 1. "LO,Line offset"
|
|
line.long 0x938 "GFXMMU_LUT295L,GFXMMU LUT entry 295 low"
|
|
hexmask.long.byte 0x938 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x938 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x93C "GFXMMU_LUT295H,GFXMMU LUT entry 295 high"
|
|
hexmask.long.tbyte 0x93C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x940 "GFXMMU_LUT296L,GFXMMU LUT entry 296 low"
|
|
hexmask.long.byte 0x940 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x940 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x944 "GFXMMU_LUT296H,GFXMMU LUT entry 296 high"
|
|
hexmask.long.tbyte 0x944 0.--17. 1. "LO,Line offset"
|
|
line.long 0x948 "GFXMMU_LUT297L,GFXMMU LUT entry 297 low"
|
|
hexmask.long.byte 0x948 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x948 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x94C "GFXMMU_LUT297H,GFXMMU LUT entry 297 high"
|
|
hexmask.long.tbyte 0x94C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x950 "GFXMMU_LUT298L,GFXMMU LUT entry 298 low"
|
|
hexmask.long.byte 0x950 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x950 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x954 "GFXMMU_LUT298H,GFXMMU LUT entry 298 high"
|
|
hexmask.long.tbyte 0x954 0.--17. 1. "LO,Line offset"
|
|
line.long 0x958 "GFXMMU_LUT299L,GFXMMU LUT entry 299 low"
|
|
hexmask.long.byte 0x958 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x958 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x95C "GFXMMU_LUT299H,GFXMMU LUT entry 299 high"
|
|
hexmask.long.tbyte 0x95C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x960 "GFXMMU_LUT300L,GFXMMU LUT entry 300 low"
|
|
hexmask.long.byte 0x960 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x960 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x964 "GFXMMU_LUT300H,GFXMMU LUT entry 300 high"
|
|
hexmask.long.tbyte 0x964 0.--17. 1. "LO,Line offset"
|
|
line.long 0x968 "GFXMMU_LUT301L,GFXMMU LUT entry 301 low"
|
|
hexmask.long.byte 0x968 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x968 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x96C "GFXMMU_LUT301H,GFXMMU LUT entry 301 high"
|
|
hexmask.long.tbyte 0x96C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x970 "GFXMMU_LUT302L,GFXMMU LUT entry 302 low"
|
|
hexmask.long.byte 0x970 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x970 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x974 "GFXMMU_LUT302H,GFXMMU LUT entry 302 high"
|
|
hexmask.long.tbyte 0x974 0.--17. 1. "LO,Line offset"
|
|
line.long 0x978 "GFXMMU_LUT303L,GFXMMU LUT entry 303 low"
|
|
hexmask.long.byte 0x978 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x978 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x97C "GFXMMU_LUT303H,GFXMMU LUT entry 303 high"
|
|
hexmask.long.tbyte 0x97C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x980 "GFXMMU_LUT304L,GFXMMU LUT entry 304 low"
|
|
hexmask.long.byte 0x980 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x980 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x984 "GFXMMU_LUT304H,GFXMMU LUT entry 304 high"
|
|
hexmask.long.tbyte 0x984 0.--17. 1. "LO,Line offset"
|
|
line.long 0x988 "GFXMMU_LUT305L,GFXMMU LUT entry 305 low"
|
|
hexmask.long.byte 0x988 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x988 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x98C "GFXMMU_LUT305H,GFXMMU LUT entry 305 high"
|
|
hexmask.long.tbyte 0x98C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x990 "GFXMMU_LUT306L,GFXMMU LUT entry 306 low"
|
|
hexmask.long.byte 0x990 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x990 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x994 "GFXMMU_LUT306H,GFXMMU LUT entry 306 high"
|
|
hexmask.long.tbyte 0x994 0.--17. 1. "LO,Line offset"
|
|
line.long 0x998 "GFXMMU_LUT307L,GFXMMU LUT entry 307 low"
|
|
hexmask.long.byte 0x998 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x998 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x99C "GFXMMU_LUT307H,GFXMMU LUT entry 307 high"
|
|
hexmask.long.tbyte 0x99C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9A0 "GFXMMU_LUT308L,GFXMMU LUT entry 308 low"
|
|
hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9A4 "GFXMMU_LUT308H,GFXMMU LUT entry 308 high"
|
|
hexmask.long.tbyte 0x9A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9A8 "GFXMMU_LUT309L,GFXMMU LUT entry 309 low"
|
|
hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9AC "GFXMMU_LUT309H,GFXMMU LUT entry 309 high"
|
|
hexmask.long.tbyte 0x9AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9B0 "GFXMMU_LUT310L,GFXMMU LUT entry 310 low"
|
|
hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9B4 "GFXMMU_LUT310H,GFXMMU LUT entry 310 high"
|
|
hexmask.long.tbyte 0x9B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9B8 "GFXMMU_LUT311L,GFXMMU LUT entry 311 low"
|
|
hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9BC "GFXMMU_LUT311H,GFXMMU LUT entry 311 high"
|
|
hexmask.long.tbyte 0x9BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9C0 "GFXMMU_LUT312L,GFXMMU LUT entry 312 low"
|
|
hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9C4 "GFXMMU_LUT312H,GFXMMU LUT entry 312 high"
|
|
hexmask.long.tbyte 0x9C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9C8 "GFXMMU_LUT313L,GFXMMU LUT entry 313 low"
|
|
hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9CC "GFXMMU_LUT313H,GFXMMU LUT entry 313 high"
|
|
hexmask.long.tbyte 0x9CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9D0 "GFXMMU_LUT314L,GFXMMU LUT entry 314 low"
|
|
hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9D4 "GFXMMU_LUT314H,GFXMMU LUT entry 314 high"
|
|
hexmask.long.tbyte 0x9D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9D8 "GFXMMU_LUT315L,GFXMMU LUT entry 315 low"
|
|
hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9DC "GFXMMU_LUT315H,GFXMMU LUT entry 315 high"
|
|
hexmask.long.tbyte 0x9DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9E0 "GFXMMU_LUT316L,GFXMMU LUT entry 316 low"
|
|
hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9E4 "GFXMMU_LUT316H,GFXMMU LUT entry 316 high"
|
|
hexmask.long.tbyte 0x9E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9E8 "GFXMMU_LUT317L,GFXMMU LUT entry 317 low"
|
|
hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9EC "GFXMMU_LUT317H,GFXMMU LUT entry 317 high"
|
|
hexmask.long.tbyte 0x9EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9F0 "GFXMMU_LUT318L,GFXMMU LUT entry 318 low"
|
|
hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9F4 "GFXMMU_LUT318H,GFXMMU LUT entry 318 high"
|
|
hexmask.long.tbyte 0x9F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9F8 "GFXMMU_LUT319L,GFXMMU LUT entry 319 low"
|
|
hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9FC "GFXMMU_LUT319H,GFXMMU LUT entry 319 high"
|
|
hexmask.long.tbyte 0x9FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA00 "GFXMMU_LUT320L,GFXMMU LUT entry 320 low"
|
|
hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA04 "GFXMMU_LUT320H,GFXMMU LUT entry 320 high"
|
|
hexmask.long.tbyte 0xA04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA08 "GFXMMU_LUT321L,GFXMMU LUT entry 321 low"
|
|
hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA0C "GFXMMU_LUT321H,GFXMMU LUT entry 321 high"
|
|
hexmask.long.tbyte 0xA0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA10 "GFXMMU_LUT322L,GFXMMU LUT entry 322 low"
|
|
hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA14 "GFXMMU_LUT322H,GFXMMU LUT entry 322 high"
|
|
hexmask.long.tbyte 0xA14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA18 "GFXMMU_LUT323L,GFXMMU LUT entry 323 low"
|
|
hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA1C "GFXMMU_LUT323H,GFXMMU LUT entry 323 high"
|
|
hexmask.long.tbyte 0xA1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA20 "GFXMMU_LUT324L,GFXMMU LUT entry 324 low"
|
|
hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA24 "GFXMMU_LUT324H,GFXMMU LUT entry 324 high"
|
|
hexmask.long.tbyte 0xA24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA28 "GFXMMU_LUT325L,GFXMMU LUT entry 325 low"
|
|
hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA2C "GFXMMU_LUT325H,GFXMMU LUT entry 325 high"
|
|
hexmask.long.tbyte 0xA2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA30 "GFXMMU_LUT326L,GFXMMU LUT entry 326 low"
|
|
hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA34 "GFXMMU_LUT326H,GFXMMU LUT entry 326 high"
|
|
hexmask.long.tbyte 0xA34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA38 "GFXMMU_LUT327L,GFXMMU LUT entry 327 low"
|
|
hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA3C "GFXMMU_LUT327H,GFXMMU LUT entry 327 high"
|
|
hexmask.long.tbyte 0xA3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA40 "GFXMMU_LUT328L,GFXMMU LUT entry 328 low"
|
|
hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA44 "GFXMMU_LUT328H,GFXMMU LUT entry 328 high"
|
|
hexmask.long.tbyte 0xA44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA48 "GFXMMU_LUT329L,GFXMMU LUT entry 329 low"
|
|
hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA4C "GFXMMU_LUT329H,GFXMMU LUT entry 329 high"
|
|
hexmask.long.tbyte 0xA4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA50 "GFXMMU_LUT330L,GFXMMU LUT entry 330 low"
|
|
hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA54 "GFXMMU_LUT330H,GFXMMU LUT entry 330 high"
|
|
hexmask.long.tbyte 0xA54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA58 "GFXMMU_LUT331L,GFXMMU LUT entry 331 low"
|
|
hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA5C "GFXMMU_LUT331H,GFXMMU LUT entry 331 high"
|
|
hexmask.long.tbyte 0xA5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA60 "GFXMMU_LUT332L,GFXMMU LUT entry 332 low"
|
|
hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA64 "GFXMMU_LUT332H,GFXMMU LUT entry 332 high"
|
|
hexmask.long.tbyte 0xA64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA68 "GFXMMU_LUT333L,GFXMMU LUT entry 333 low"
|
|
hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA6C "GFXMMU_LUT333H,GFXMMU LUT entry 333 high"
|
|
hexmask.long.tbyte 0xA6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA70 "GFXMMU_LUT334L,GFXMMU LUT entry 334 low"
|
|
hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA74 "GFXMMU_LUT334H,GFXMMU LUT entry 334 high"
|
|
hexmask.long.tbyte 0xA74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA78 "GFXMMU_LUT335L,GFXMMU LUT entry 335 low"
|
|
hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA7C "GFXMMU_LUT335H,GFXMMU LUT entry 335 high"
|
|
hexmask.long.tbyte 0xA7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA80 "GFXMMU_LUT336L,GFXMMU LUT entry 336 low"
|
|
hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA84 "GFXMMU_LUT336H,GFXMMU LUT entry 336 high"
|
|
hexmask.long.tbyte 0xA84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA88 "GFXMMU_LUT337L,GFXMMU LUT entry 337 low"
|
|
hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA8C "GFXMMU_LUT337H,GFXMMU LUT entry 337 high"
|
|
hexmask.long.tbyte 0xA8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA90 "GFXMMU_LUT338L,GFXMMU LUT entry 338 low"
|
|
hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA94 "GFXMMU_LUT338H,GFXMMU LUT entry 338 high"
|
|
hexmask.long.tbyte 0xA94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA98 "GFXMMU_LUT339L,GFXMMU LUT entry 339 low"
|
|
hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA9C "GFXMMU_LUT339H,GFXMMU LUT entry 339 high"
|
|
hexmask.long.tbyte 0xA9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAA0 "GFXMMU_LUT340L,GFXMMU LUT entry 340 low"
|
|
hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAA4 "GFXMMU_LUT340H,GFXMMU LUT entry 340 high"
|
|
hexmask.long.tbyte 0xAA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAA8 "GFXMMU_LUT341L,GFXMMU LUT entry 341 low"
|
|
hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAAC "GFXMMU_LUT341H,GFXMMU LUT entry 341 high"
|
|
hexmask.long.tbyte 0xAAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAB0 "GFXMMU_LUT342L,GFXMMU LUT entry 342 low"
|
|
hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAB4 "GFXMMU_LUT342H,GFXMMU LUT entry 342 high"
|
|
hexmask.long.tbyte 0xAB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAB8 "GFXMMU_LUT343L,GFXMMU LUT entry 343 low"
|
|
hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xABC "GFXMMU_LUT343H,GFXMMU LUT entry 343 high"
|
|
hexmask.long.tbyte 0xABC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAC0 "GFXMMU_LUT344L,GFXMMU LUT entry 344 low"
|
|
hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAC4 "GFXMMU_LUT344H,GFXMMU LUT entry 344 high"
|
|
hexmask.long.tbyte 0xAC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAC8 "GFXMMU_LUT345L,GFXMMU LUT entry 345 low"
|
|
hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xACC "GFXMMU_LUT345H,GFXMMU LUT entry 345 high"
|
|
hexmask.long.tbyte 0xACC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAD0 "GFXMMU_LUT346L,GFXMMU LUT entry 346 low"
|
|
hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAD4 "GFXMMU_LUT346H,GFXMMU LUT entry 346 high"
|
|
hexmask.long.tbyte 0xAD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAD8 "GFXMMU_LUT347L,GFXMMU LUT entry 347 low"
|
|
hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xADC "GFXMMU_LUT347H,GFXMMU LUT entry 347 high"
|
|
hexmask.long.tbyte 0xADC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAE0 "GFXMMU_LUT348L,GFXMMU LUT entry 348 low"
|
|
hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAE4 "GFXMMU_LUT348H,GFXMMU LUT entry 348 high"
|
|
hexmask.long.tbyte 0xAE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAE8 "GFXMMU_LUT349L,GFXMMU LUT entry 349 low"
|
|
hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAEC "GFXMMU_LUT349H,GFXMMU LUT entry 349 high"
|
|
hexmask.long.tbyte 0xAEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAF0 "GFXMMU_LUT350L,GFXMMU LUT entry 350 low"
|
|
hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAF4 "GFXMMU_LUT350H,GFXMMU LUT entry 350 high"
|
|
hexmask.long.tbyte 0xAF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAF8 "GFXMMU_LUT351L,GFXMMU LUT entry 351 low"
|
|
hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAFC "GFXMMU_LUT351H,GFXMMU LUT entry 351 high"
|
|
hexmask.long.tbyte 0xAFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB00 "GFXMMU_LUT352L,GFXMMU LUT entry 352 low"
|
|
hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB04 "GFXMMU_LUT352H,GFXMMU LUT entry 352 high"
|
|
hexmask.long.tbyte 0xB04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB08 "GFXMMU_LUT353L,GFXMMU LUT entry 353 low"
|
|
hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB0C "GFXMMU_LUT353H,GFXMMU LUT entry 353 high"
|
|
hexmask.long.tbyte 0xB0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB10 "GFXMMU_LUT354L,GFXMMU LUT entry 354 low"
|
|
hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB14 "GFXMMU_LUT354H,GFXMMU LUT entry 354 high"
|
|
hexmask.long.tbyte 0xB14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB18 "GFXMMU_LUT355L,GFXMMU LUT entry 355 low"
|
|
hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB1C "GFXMMU_LUT355H,GFXMMU LUT entry 355 high"
|
|
hexmask.long.tbyte 0xB1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB20 "GFXMMU_LUT356L,GFXMMU LUT entry 356 low"
|
|
hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB24 "GFXMMU_LUT356H,GFXMMU LUT entry 356 high"
|
|
hexmask.long.tbyte 0xB24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB28 "GFXMMU_LUT357L,GFXMMU LUT entry 357 low"
|
|
hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB2C "GFXMMU_LUT357H,GFXMMU LUT entry 357 high"
|
|
hexmask.long.tbyte 0xB2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB30 "GFXMMU_LUT358L,GFXMMU LUT entry 358 low"
|
|
hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB34 "GFXMMU_LUT358H,GFXMMU LUT entry 358 high"
|
|
hexmask.long.tbyte 0xB34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB38 "GFXMMU_LUT359L,GFXMMU LUT entry 359 low"
|
|
hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB3C "GFXMMU_LUT359H,GFXMMU LUT entry 359 high"
|
|
hexmask.long.tbyte 0xB3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB40 "GFXMMU_LUT360L,GFXMMU LUT entry 360 low"
|
|
hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB44 "GFXMMU_LUT360H,GFXMMU LUT entry 360 high"
|
|
hexmask.long.tbyte 0xB44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB48 "GFXMMU_LUT361L,GFXMMU LUT entry 361 low"
|
|
hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB4C "GFXMMU_LUT361H,GFXMMU LUT entry 361 high"
|
|
hexmask.long.tbyte 0xB4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB50 "GFXMMU_LUT362L,GFXMMU LUT entry 362 low"
|
|
hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB54 "GFXMMU_LUT362H,GFXMMU LUT entry 362 high"
|
|
hexmask.long.tbyte 0xB54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB58 "GFXMMU_LUT363L,GFXMMU LUT entry 363 low"
|
|
hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB5C "GFXMMU_LUT363H,GFXMMU LUT entry 363 high"
|
|
hexmask.long.tbyte 0xB5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB60 "GFXMMU_LUT364L,GFXMMU LUT entry 364 low"
|
|
hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB64 "GFXMMU_LUT364H,GFXMMU LUT entry 364 high"
|
|
hexmask.long.tbyte 0xB64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB68 "GFXMMU_LUT365L,GFXMMU LUT entry 365 low"
|
|
hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB6C "GFXMMU_LUT365H,GFXMMU LUT entry 365 high"
|
|
hexmask.long.tbyte 0xB6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB70 "GFXMMU_LUT366L,GFXMMU LUT entry 366 low"
|
|
hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB74 "GFXMMU_LUT366H,GFXMMU LUT entry 366 high"
|
|
hexmask.long.tbyte 0xB74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB78 "GFXMMU_LUT367L,GFXMMU LUT entry 367 low"
|
|
hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB7C "GFXMMU_LUT367H,GFXMMU LUT entry 367 high"
|
|
hexmask.long.tbyte 0xB7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB80 "GFXMMU_LUT368L,GFXMMU LUT entry 368 low"
|
|
hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB84 "GFXMMU_LUT368H,GFXMMU LUT entry 368 high"
|
|
hexmask.long.tbyte 0xB84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB88 "GFXMMU_LUT369L,GFXMMU LUT entry 369 low"
|
|
hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB8C "GFXMMU_LUT369H,GFXMMU LUT entry 369 high"
|
|
hexmask.long.tbyte 0xB8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB90 "GFXMMU_LUT370L,GFXMMU LUT entry 370 low"
|
|
hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB94 "GFXMMU_LUT370H,GFXMMU LUT entry 370 high"
|
|
hexmask.long.tbyte 0xB94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB98 "GFXMMU_LUT371L,GFXMMU LUT entry 371 low"
|
|
hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB9C "GFXMMU_LUT371H,GFXMMU LUT entry 371 high"
|
|
hexmask.long.tbyte 0xB9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBA0 "GFXMMU_LUT372L,GFXMMU LUT entry 372 low"
|
|
hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBA4 "GFXMMU_LUT372H,GFXMMU LUT entry 372 high"
|
|
hexmask.long.tbyte 0xBA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBA8 "GFXMMU_LUT373L,GFXMMU LUT entry 373 low"
|
|
hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBAC "GFXMMU_LUT373H,GFXMMU LUT entry 373 high"
|
|
hexmask.long.tbyte 0xBAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBB0 "GFXMMU_LUT374L,GFXMMU LUT entry 374 low"
|
|
hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBB4 "GFXMMU_LUT374H,GFXMMU LUT entry 374 high"
|
|
hexmask.long.tbyte 0xBB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBB8 "GFXMMU_LUT375L,GFXMMU LUT entry 375 low"
|
|
hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBBC "GFXMMU_LUT375H,GFXMMU LUT entry 375 high"
|
|
hexmask.long.tbyte 0xBBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBC0 "GFXMMU_LUT376L,GFXMMU LUT entry 376 low"
|
|
hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBC4 "GFXMMU_LUT376H,GFXMMU LUT entry 376 high"
|
|
hexmask.long.tbyte 0xBC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBC8 "GFXMMU_LUT377L,GFXMMU LUT entry 377 low"
|
|
hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBCC "GFXMMU_LUT377H,GFXMMU LUT entry 377 high"
|
|
hexmask.long.tbyte 0xBCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBD0 "GFXMMU_LUT378L,GFXMMU LUT entry 378 low"
|
|
hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBD4 "GFXMMU_LUT378H,GFXMMU LUT entry 378 high"
|
|
hexmask.long.tbyte 0xBD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBD8 "GFXMMU_LUT379L,GFXMMU LUT entry 379 low"
|
|
hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBDC "GFXMMU_LUT379H,GFXMMU LUT entry 379 high"
|
|
hexmask.long.tbyte 0xBDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBE0 "GFXMMU_LUT380L,GFXMMU LUT entry 380 low"
|
|
hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBE4 "GFXMMU_LUT380H,GFXMMU LUT entry 380 high"
|
|
hexmask.long.tbyte 0xBE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBE8 "GFXMMU_LUT381L,GFXMMU LUT entry 381 low"
|
|
hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBEC "GFXMMU_LUT381H,GFXMMU LUT entry 381 high"
|
|
hexmask.long.tbyte 0xBEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBF0 "GFXMMU_LUT382L,GFXMMU LUT entry 382 low"
|
|
hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBF4 "GFXMMU_LUT382H,GFXMMU LUT entry 382 high"
|
|
hexmask.long.tbyte 0xBF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBF8 "GFXMMU_LUT383L,GFXMMU LUT entry 383 low"
|
|
hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBFC "GFXMMU_LUT383H,GFXMMU LUT entry 383 high"
|
|
hexmask.long.tbyte 0xBFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC00 "GFXMMU_LUT384L,GFXMMU LUT entry 384 low"
|
|
hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC04 "GFXMMU_LUT384H,GFXMMU LUT entry 384 high"
|
|
hexmask.long.tbyte 0xC04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC08 "GFXMMU_LUT385L,GFXMMU LUT entry 385 low"
|
|
hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC0C "GFXMMU_LUT385H,GFXMMU LUT entry 385 high"
|
|
hexmask.long.tbyte 0xC0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC10 "GFXMMU_LUT386L,GFXMMU LUT entry 386 low"
|
|
hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC14 "GFXMMU_LUT386H,GFXMMU LUT entry 386 high"
|
|
hexmask.long.tbyte 0xC14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC18 "GFXMMU_LUT387L,GFXMMU LUT entry 387 low"
|
|
hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC1C "GFXMMU_LUT387H,GFXMMU LUT entry 387 high"
|
|
hexmask.long.tbyte 0xC1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC20 "GFXMMU_LUT388L,GFXMMU LUT entry 388 low"
|
|
hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC24 "GFXMMU_LUT388H,GFXMMU LUT entry 388 high"
|
|
hexmask.long.tbyte 0xC24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC28 "GFXMMU_LUT389L,GFXMMU LUT entry 389 low"
|
|
hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC2C "GFXMMU_LUT389H,GFXMMU LUT entry 389 high"
|
|
hexmask.long.tbyte 0xC2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC30 "GFXMMU_LUT390L,GFXMMU LUT entry 390 low"
|
|
hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC34 "GFXMMU_LUT390H,GFXMMU LUT entry 390 high"
|
|
hexmask.long.tbyte 0xC34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC38 "GFXMMU_LUT391L,GFXMMU LUT entry 391 low"
|
|
hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC3C "GFXMMU_LUT391H,GFXMMU LUT entry 391 high"
|
|
hexmask.long.tbyte 0xC3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC40 "GFXMMU_LUT392L,GFXMMU LUT entry 392 low"
|
|
hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC44 "GFXMMU_LUT392H,GFXMMU LUT entry 392 high"
|
|
hexmask.long.tbyte 0xC44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC48 "GFXMMU_LUT393L,GFXMMU LUT entry 393 low"
|
|
hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC4C "GFXMMU_LUT393H,GFXMMU LUT entry 393 high"
|
|
hexmask.long.tbyte 0xC4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC50 "GFXMMU_LUT394L,GFXMMU LUT entry 394 low"
|
|
hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC54 "GFXMMU_LUT394H,GFXMMU LUT entry 394 high"
|
|
hexmask.long.tbyte 0xC54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC58 "GFXMMU_LUT395L,GFXMMU LUT entry 395 low"
|
|
hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC5C "GFXMMU_LUT395H,GFXMMU LUT entry 395 high"
|
|
hexmask.long.tbyte 0xC5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC60 "GFXMMU_LUT396L,GFXMMU LUT entry 396 low"
|
|
hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC64 "GFXMMU_LUT396H,GFXMMU LUT entry 396 high"
|
|
hexmask.long.tbyte 0xC64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC68 "GFXMMU_LUT397L,GFXMMU LUT entry 397 low"
|
|
hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC6C "GFXMMU_LUT397H,GFXMMU LUT entry 397 high"
|
|
hexmask.long.tbyte 0xC6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC70 "GFXMMU_LUT398L,GFXMMU LUT entry 398 low"
|
|
hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC74 "GFXMMU_LUT398H,GFXMMU LUT entry 398 high"
|
|
hexmask.long.tbyte 0xC74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC78 "GFXMMU_LUT399L,GFXMMU LUT entry 399 low"
|
|
hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC7C "GFXMMU_LUT399H,GFXMMU LUT entry 399 high"
|
|
hexmask.long.tbyte 0xC7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC80 "GFXMMU_LUT400L,GFXMMU LUT entry 400 low"
|
|
hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC84 "GFXMMU_LUT400H,GFXMMU LUT entry 400 high"
|
|
hexmask.long.tbyte 0xC84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC88 "GFXMMU_LUT401L,GFXMMU LUT entry 401 low"
|
|
hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC8C "GFXMMU_LUT401H,GFXMMU LUT entry 401 high"
|
|
hexmask.long.tbyte 0xC8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC90 "GFXMMU_LUT402L,GFXMMU LUT entry 402 low"
|
|
hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC94 "GFXMMU_LUT402H,GFXMMU LUT entry 402 high"
|
|
hexmask.long.tbyte 0xC94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC98 "GFXMMU_LUT403L,GFXMMU LUT entry 403 low"
|
|
hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC9C "GFXMMU_LUT403H,GFXMMU LUT entry 403 high"
|
|
hexmask.long.tbyte 0xC9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCA0 "GFXMMU_LUT404L,GFXMMU LUT entry 404 low"
|
|
hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCA4 "GFXMMU_LUT404H,GFXMMU LUT entry 404 high"
|
|
hexmask.long.tbyte 0xCA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCA8 "GFXMMU_LUT405L,GFXMMU LUT entry 405 low"
|
|
hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCAC "GFXMMU_LUT405H,GFXMMU LUT entry 405 high"
|
|
hexmask.long.tbyte 0xCAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCB0 "GFXMMU_LUT406L,GFXMMU LUT entry 406 low"
|
|
hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCB4 "GFXMMU_LUT406H,GFXMMU LUT entry 406 high"
|
|
hexmask.long.tbyte 0xCB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCB8 "GFXMMU_LUT407L,GFXMMU LUT entry 407 low"
|
|
hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCBC "GFXMMU_LUT407H,GFXMMU LUT entry 407 high"
|
|
hexmask.long.tbyte 0xCBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCC0 "GFXMMU_LUT408L,GFXMMU LUT entry 408 low"
|
|
hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCC4 "GFXMMU_LUT408H,GFXMMU LUT entry 408 high"
|
|
hexmask.long.tbyte 0xCC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCC8 "GFXMMU_LUT409L,GFXMMU LUT entry 409 low"
|
|
hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCCC "GFXMMU_LUT409H,GFXMMU LUT entry 409 high"
|
|
hexmask.long.tbyte 0xCCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCD0 "GFXMMU_LUT410L,GFXMMU LUT entry 410 low"
|
|
hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCD4 "GFXMMU_LUT410H,GFXMMU LUT entry 410 high"
|
|
hexmask.long.tbyte 0xCD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCD8 "GFXMMU_LUT411L,GFXMMU LUT entry 411 low"
|
|
hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCDC "GFXMMU_LUT411H,GFXMMU LUT entry 411 high"
|
|
hexmask.long.tbyte 0xCDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCE0 "GFXMMU_LUT412L,GFXMMU LUT entry 412 low"
|
|
hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCE4 "GFXMMU_LUT412H,GFXMMU LUT entry 412 high"
|
|
hexmask.long.tbyte 0xCE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCE8 "GFXMMU_LUT413L,GFXMMU LUT entry 413 low"
|
|
hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCEC "GFXMMU_LUT413H,GFXMMU LUT entry 413 high"
|
|
hexmask.long.tbyte 0xCEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCF0 "GFXMMU_LUT414L,GFXMMU LUT entry 414 low"
|
|
hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCF4 "GFXMMU_LUT414H,GFXMMU LUT entry 414 high"
|
|
hexmask.long.tbyte 0xCF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCF8 "GFXMMU_LUT415L,GFXMMU LUT entry 415 low"
|
|
hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCFC "GFXMMU_LUT415H,GFXMMU LUT entry 415 high"
|
|
hexmask.long.tbyte 0xCFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD00 "GFXMMU_LUT416L,GFXMMU LUT entry 416 low"
|
|
hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD04 "GFXMMU_LUT416H,GFXMMU LUT entry 416 high"
|
|
hexmask.long.tbyte 0xD04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD08 "GFXMMU_LUT417L,GFXMMU LUT entry 417 low"
|
|
hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD0C "GFXMMU_LUT417H,GFXMMU LUT entry 417 high"
|
|
hexmask.long.tbyte 0xD0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD10 "GFXMMU_LUT418L,GFXMMU LUT entry 418 low"
|
|
hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD14 "GFXMMU_LUT418H,GFXMMU LUT entry 418 high"
|
|
hexmask.long.tbyte 0xD14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD18 "GFXMMU_LUT419L,GFXMMU LUT entry 419 low"
|
|
hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD1C "GFXMMU_LUT419H,GFXMMU LUT entry 419 high"
|
|
hexmask.long.tbyte 0xD1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD20 "GFXMMU_LUT420L,GFXMMU LUT entry 420 low"
|
|
hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD24 "GFXMMU_LUT420H,GFXMMU LUT entry 420 high"
|
|
hexmask.long.tbyte 0xD24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD28 "GFXMMU_LUT421L,GFXMMU LUT entry 421 low"
|
|
hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD2C "GFXMMU_LUT421H,GFXMMU LUT entry 421 high"
|
|
hexmask.long.tbyte 0xD2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD30 "GFXMMU_LUT422L,GFXMMU LUT entry 422 low"
|
|
hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD34 "GFXMMU_LUT422H,GFXMMU LUT entry 422 high"
|
|
hexmask.long.tbyte 0xD34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD38 "GFXMMU_LUT423L,GFXMMU LUT entry 423 low"
|
|
hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD3C "GFXMMU_LUT423H,GFXMMU LUT entry 423 high"
|
|
hexmask.long.tbyte 0xD3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD40 "GFXMMU_LUT424L,GFXMMU LUT entry 424 low"
|
|
hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD44 "GFXMMU_LUT424H,GFXMMU LUT entry 424 high"
|
|
hexmask.long.tbyte 0xD44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD48 "GFXMMU_LUT425L,GFXMMU LUT entry 425 low"
|
|
hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD4C "GFXMMU_LUT425H,GFXMMU LUT entry 425 high"
|
|
hexmask.long.tbyte 0xD4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD50 "GFXMMU_LUT426L,GFXMMU LUT entry 426 low"
|
|
hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD54 "GFXMMU_LUT426H,GFXMMU LUT entry 426 high"
|
|
hexmask.long.tbyte 0xD54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD58 "GFXMMU_LUT427L,GFXMMU LUT entry 427 low"
|
|
hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD5C "GFXMMU_LUT427H,GFXMMU LUT entry 427 high"
|
|
hexmask.long.tbyte 0xD5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD60 "GFXMMU_LUT428L,GFXMMU LUT entry 428 low"
|
|
hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD64 "GFXMMU_LUT428H,GFXMMU LUT entry 428 high"
|
|
hexmask.long.tbyte 0xD64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD68 "GFXMMU_LUT429L,GFXMMU LUT entry 429 low"
|
|
hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD6C "GFXMMU_LUT429H,GFXMMU LUT entry 429 high"
|
|
hexmask.long.tbyte 0xD6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD70 "GFXMMU_LUT430L,GFXMMU LUT entry 430 low"
|
|
hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD74 "GFXMMU_LUT430H,GFXMMU LUT entry 430 high"
|
|
hexmask.long.tbyte 0xD74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD78 "GFXMMU_LUT431L,GFXMMU LUT entry 431 low"
|
|
hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD7C "GFXMMU_LUT431H,GFXMMU LUT entry 431 high"
|
|
hexmask.long.tbyte 0xD7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD80 "GFXMMU_LUT432L,GFXMMU LUT entry 432 low"
|
|
hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD84 "GFXMMU_LUT432H,GFXMMU LUT entry 432 high"
|
|
hexmask.long.tbyte 0xD84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD88 "GFXMMU_LUT433L,GFXMMU LUT entry 433 low"
|
|
hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD8C "GFXMMU_LUT433H,GFXMMU LUT entry 433 high"
|
|
hexmask.long.tbyte 0xD8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD90 "GFXMMU_LUT434L,GFXMMU LUT entry 434 low"
|
|
hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD94 "GFXMMU_LUT434H,GFXMMU LUT entry 434 high"
|
|
hexmask.long.tbyte 0xD94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD98 "GFXMMU_LUT435L,GFXMMU LUT entry 435 low"
|
|
hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD9C "GFXMMU_LUT435H,GFXMMU LUT entry 435 high"
|
|
hexmask.long.tbyte 0xD9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDA0 "GFXMMU_LUT436L,GFXMMU LUT entry 436 low"
|
|
hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDA4 "GFXMMU_LUT436H,GFXMMU LUT entry 436 high"
|
|
hexmask.long.tbyte 0xDA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDA8 "GFXMMU_LUT437L,GFXMMU LUT entry 437 low"
|
|
hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDAC "GFXMMU_LUT437H,GFXMMU LUT entry 437 high"
|
|
hexmask.long.tbyte 0xDAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDB0 "GFXMMU_LUT438L,GFXMMU LUT entry 438 low"
|
|
hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDB4 "GFXMMU_LUT438H,GFXMMU LUT entry 438 high"
|
|
hexmask.long.tbyte 0xDB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDB8 "GFXMMU_LUT439L,GFXMMU LUT entry 439 low"
|
|
hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDBC "GFXMMU_LUT439H,GFXMMU LUT entry 439 high"
|
|
hexmask.long.tbyte 0xDBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDC0 "GFXMMU_LUT440L,GFXMMU LUT entry 440 low"
|
|
hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDC4 "GFXMMU_LUT440H,GFXMMU LUT entry 440 high"
|
|
hexmask.long.tbyte 0xDC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDC8 "GFXMMU_LUT441L,GFXMMU LUT entry 441 low"
|
|
hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDCC "GFXMMU_LUT441H,GFXMMU LUT entry 441 high"
|
|
hexmask.long.tbyte 0xDCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDD0 "GFXMMU_LUT442L,GFXMMU LUT entry 442 low"
|
|
hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDD4 "GFXMMU_LUT442H,GFXMMU LUT entry 442 high"
|
|
hexmask.long.tbyte 0xDD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDD8 "GFXMMU_LUT443L,GFXMMU LUT entry 443 low"
|
|
hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDDC "GFXMMU_LUT443H,GFXMMU LUT entry 443 high"
|
|
hexmask.long.tbyte 0xDDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDE0 "GFXMMU_LUT444L,GFXMMU LUT entry 444 low"
|
|
hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDE4 "GFXMMU_LUT444H,GFXMMU LUT entry 444 high"
|
|
hexmask.long.tbyte 0xDE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDE8 "GFXMMU_LUT445L,GFXMMU LUT entry 445 low"
|
|
hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDEC "GFXMMU_LUT445H,GFXMMU LUT entry 445 high"
|
|
hexmask.long.tbyte 0xDEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDF0 "GFXMMU_LUT446L,GFXMMU LUT entry 446 low"
|
|
hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDF4 "GFXMMU_LUT446H,GFXMMU LUT entry 446 high"
|
|
hexmask.long.tbyte 0xDF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDF8 "GFXMMU_LUT447L,GFXMMU LUT entry 447 low"
|
|
hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDFC "GFXMMU_LUT447H,GFXMMU LUT entry 447 high"
|
|
hexmask.long.tbyte 0xDFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE00 "GFXMMU_LUT448L,GFXMMU LUT entry 448 low"
|
|
hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE04 "GFXMMU_LUT448H,GFXMMU LUT entry 448 high"
|
|
hexmask.long.tbyte 0xE04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE08 "GFXMMU_LUT449L,GFXMMU LUT entry 449 low"
|
|
hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE0C "GFXMMU_LUT449H,GFXMMU LUT entry 449 high"
|
|
hexmask.long.tbyte 0xE0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE10 "GFXMMU_LUT450L,GFXMMU LUT entry 450 low"
|
|
hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE14 "GFXMMU_LUT450H,GFXMMU LUT entry 450 high"
|
|
hexmask.long.tbyte 0xE14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE18 "GFXMMU_LUT451L,GFXMMU LUT entry 451 low"
|
|
hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE1C "GFXMMU_LUT451H,GFXMMU LUT entry 451 high"
|
|
hexmask.long.tbyte 0xE1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE20 "GFXMMU_LUT452L,GFXMMU LUT entry 452 low"
|
|
hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE24 "GFXMMU_LUT452H,GFXMMU LUT entry 452 high"
|
|
hexmask.long.tbyte 0xE24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE28 "GFXMMU_LUT453L,GFXMMU LUT entry 453 low"
|
|
hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE2C "GFXMMU_LUT453H,GFXMMU LUT entry 453 high"
|
|
hexmask.long.tbyte 0xE2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE30 "GFXMMU_LUT454L,GFXMMU LUT entry 454 low"
|
|
hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE34 "GFXMMU_LUT454H,GFXMMU LUT entry 454 high"
|
|
hexmask.long.tbyte 0xE34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE38 "GFXMMU_LUT455L,GFXMMU LUT entry 455 low"
|
|
hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE3C "GFXMMU_LUT455H,GFXMMU LUT entry 455 high"
|
|
hexmask.long.tbyte 0xE3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE40 "GFXMMU_LUT456L,GFXMMU LUT entry 456 low"
|
|
hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE44 "GFXMMU_LUT456H,GFXMMU LUT entry 456 high"
|
|
hexmask.long.tbyte 0xE44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE48 "GFXMMU_LUT457L,GFXMMU LUT entry 457 low"
|
|
hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE4C "GFXMMU_LUT457H,GFXMMU LUT entry 457 high"
|
|
hexmask.long.tbyte 0xE4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE50 "GFXMMU_LUT458L,GFXMMU LUT entry 458 low"
|
|
hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE54 "GFXMMU_LUT458H,GFXMMU LUT entry 458 high"
|
|
hexmask.long.tbyte 0xE54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE58 "GFXMMU_LUT459L,GFXMMU LUT entry 459 low"
|
|
hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE5C "GFXMMU_LUT459H,GFXMMU LUT entry 459 high"
|
|
hexmask.long.tbyte 0xE5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE60 "GFXMMU_LUT460L,GFXMMU LUT entry 460 low"
|
|
hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE64 "GFXMMU_LUT460H,GFXMMU LUT entry 460 high"
|
|
hexmask.long.tbyte 0xE64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE68 "GFXMMU_LUT461L,GFXMMU LUT entry 461 low"
|
|
hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE6C "GFXMMU_LUT461H,GFXMMU LUT entry 461 high"
|
|
hexmask.long.tbyte 0xE6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE70 "GFXMMU_LUT462L,GFXMMU LUT entry 462 low"
|
|
hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE74 "GFXMMU_LUT462H,GFXMMU LUT entry 462 high"
|
|
hexmask.long.tbyte 0xE74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE78 "GFXMMU_LUT463L,GFXMMU LUT entry 463 low"
|
|
hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE7C "GFXMMU_LUT463H,GFXMMU LUT entry 463 high"
|
|
hexmask.long.tbyte 0xE7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE80 "GFXMMU_LUT464L,GFXMMU LUT entry 464 low"
|
|
hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE84 "GFXMMU_LUT464H,GFXMMU LUT entry 464 high"
|
|
hexmask.long.tbyte 0xE84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE88 "GFXMMU_LUT465L,GFXMMU LUT entry 465 low"
|
|
hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE8C "GFXMMU_LUT465H,GFXMMU LUT entry 465 high"
|
|
hexmask.long.tbyte 0xE8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE90 "GFXMMU_LUT466L,GFXMMU LUT entry 466 low"
|
|
hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE94 "GFXMMU_LUT466H,GFXMMU LUT entry 466 high"
|
|
hexmask.long.tbyte 0xE94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE98 "GFXMMU_LUT467L,GFXMMU LUT entry 467 low"
|
|
hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE9C "GFXMMU_LUT467H,GFXMMU LUT entry 467 high"
|
|
hexmask.long.tbyte 0xE9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEA0 "GFXMMU_LUT468L,GFXMMU LUT entry 468 low"
|
|
hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEA4 "GFXMMU_LUT468H,GFXMMU LUT entry 468 high"
|
|
hexmask.long.tbyte 0xEA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEA8 "GFXMMU_LUT469L,GFXMMU LUT entry 469 low"
|
|
hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEAC "GFXMMU_LUT469H,GFXMMU LUT entry 469 high"
|
|
hexmask.long.tbyte 0xEAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEB0 "GFXMMU_LUT470L,GFXMMU LUT entry 470 low"
|
|
hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEB4 "GFXMMU_LUT470H,GFXMMU LUT entry 470 high"
|
|
hexmask.long.tbyte 0xEB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEB8 "GFXMMU_LUT471L,GFXMMU LUT entry 471 low"
|
|
hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEBC "GFXMMU_LUT471H,GFXMMU LUT entry 471 high"
|
|
hexmask.long.tbyte 0xEBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEC0 "GFXMMU_LUT472L,GFXMMU LUT entry 472 low"
|
|
hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEC4 "GFXMMU_LUT472H,GFXMMU LUT entry 472 high"
|
|
hexmask.long.tbyte 0xEC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEC8 "GFXMMU_LUT473L,GFXMMU LUT entry 473 low"
|
|
hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xECC "GFXMMU_LUT473H,GFXMMU LUT entry 473 high"
|
|
hexmask.long.tbyte 0xECC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xED0 "GFXMMU_LUT474L,GFXMMU LUT entry 474 low"
|
|
hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xED0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xED4 "GFXMMU_LUT474H,GFXMMU LUT entry 474 high"
|
|
hexmask.long.tbyte 0xED4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xED8 "GFXMMU_LUT475L,GFXMMU LUT entry 475 low"
|
|
hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xED8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEDC "GFXMMU_LUT475H,GFXMMU LUT entry 475 high"
|
|
hexmask.long.tbyte 0xEDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEE0 "GFXMMU_LUT476L,GFXMMU LUT entry 476 low"
|
|
hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEE4 "GFXMMU_LUT476H,GFXMMU LUT entry 476 high"
|
|
hexmask.long.tbyte 0xEE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEE8 "GFXMMU_LUT477L,GFXMMU LUT entry 477 low"
|
|
hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEEC "GFXMMU_LUT477H,GFXMMU LUT entry 477 high"
|
|
hexmask.long.tbyte 0xEEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEF0 "GFXMMU_LUT478L,GFXMMU LUT entry 478 low"
|
|
hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEF4 "GFXMMU_LUT478H,GFXMMU LUT entry 478 high"
|
|
hexmask.long.tbyte 0xEF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEF8 "GFXMMU_LUT479L,GFXMMU LUT entry 479 low"
|
|
hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEFC "GFXMMU_LUT479H,GFXMMU LUT entry 479 high"
|
|
hexmask.long.tbyte 0xEFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF00 "GFXMMU_LUT480L,GFXMMU LUT entry 480 low"
|
|
hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF04 "GFXMMU_LUT480H,GFXMMU LUT entry 480 high"
|
|
hexmask.long.tbyte 0xF04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF08 "GFXMMU_LUT481L,GFXMMU LUT entry 481 low"
|
|
hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF0C "GFXMMU_LUT481H,GFXMMU LUT entry 481 high"
|
|
hexmask.long.tbyte 0xF0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF10 "GFXMMU_LUT482L,GFXMMU LUT entry 482 low"
|
|
hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF14 "GFXMMU_LUT482H,GFXMMU LUT entry 482 high"
|
|
hexmask.long.tbyte 0xF14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF18 "GFXMMU_LUT483L,GFXMMU LUT entry 483 low"
|
|
hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF1C "GFXMMU_LUT483H,GFXMMU LUT entry 483 high"
|
|
hexmask.long.tbyte 0xF1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF20 "GFXMMU_LUT484L,GFXMMU LUT entry 484 low"
|
|
hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF24 "GFXMMU_LUT484H,GFXMMU LUT entry 484 high"
|
|
hexmask.long.tbyte 0xF24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF28 "GFXMMU_LUT485L,GFXMMU LUT entry 485 low"
|
|
hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF2C "GFXMMU_LUT485H,GFXMMU LUT entry 485 high"
|
|
hexmask.long.tbyte 0xF2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF30 "GFXMMU_LUT486L,GFXMMU LUT entry 486 low"
|
|
hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF34 "GFXMMU_LUT486H,GFXMMU LUT entry 486 high"
|
|
hexmask.long.tbyte 0xF34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF38 "GFXMMU_LUT487L,GFXMMU LUT entry 487 low"
|
|
hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF3C "GFXMMU_LUT487H,GFXMMU LUT entry 487 high"
|
|
hexmask.long.tbyte 0xF3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF40 "GFXMMU_LUT488L,GFXMMU LUT entry 488 low"
|
|
hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF44 "GFXMMU_LUT488H,GFXMMU LUT entry 488 high"
|
|
hexmask.long.tbyte 0xF44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF48 "GFXMMU_LUT489L,GFXMMU LUT entry 489 low"
|
|
hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF4C "GFXMMU_LUT489H,GFXMMU LUT entry 489 high"
|
|
hexmask.long.tbyte 0xF4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF50 "GFXMMU_LUT490L,GFXMMU LUT entry 490 low"
|
|
hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF54 "GFXMMU_LUT490H,GFXMMU LUT entry 490 high"
|
|
hexmask.long.tbyte 0xF54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF58 "GFXMMU_LUT491L,GFXMMU LUT entry 491 low"
|
|
hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF5C "GFXMMU_LUT491H,GFXMMU LUT entry 491 high"
|
|
hexmask.long.tbyte 0xF5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF60 "GFXMMU_LUT492L,GFXMMU LUT entry 492 low"
|
|
hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF64 "GFXMMU_LUT492H,GFXMMU LUT entry 492 high"
|
|
hexmask.long.tbyte 0xF64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF68 "GFXMMU_LUT493L,GFXMMU LUT entry 493 low"
|
|
hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF6C "GFXMMU_LUT493H,GFXMMU LUT entry 493 high"
|
|
hexmask.long.tbyte 0xF6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF70 "GFXMMU_LUT494L,GFXMMU LUT entry 494 low"
|
|
hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF74 "GFXMMU_LUT494H,GFXMMU LUT entry 494 high"
|
|
hexmask.long.tbyte 0xF74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF78 "GFXMMU_LUT495L,GFXMMU LUT entry 495 low"
|
|
hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF7C "GFXMMU_LUT495H,GFXMMU LUT entry 495 high"
|
|
hexmask.long.tbyte 0xF7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF80 "GFXMMU_LUT496L,GFXMMU LUT entry 496 low"
|
|
hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF84 "GFXMMU_LUT496H,GFXMMU LUT entry 496 high"
|
|
hexmask.long.tbyte 0xF84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF88 "GFXMMU_LUT497L,GFXMMU LUT entry 497 low"
|
|
hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF8C "GFXMMU_LUT497H,GFXMMU LUT entry 497 high"
|
|
hexmask.long.tbyte 0xF8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF90 "GFXMMU_LUT498L,GFXMMU LUT entry 498 low"
|
|
hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF94 "GFXMMU_LUT498H,GFXMMU LUT entry 498 high"
|
|
hexmask.long.tbyte 0xF94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF98 "GFXMMU_LUT499L,GFXMMU LUT entry 499 low"
|
|
hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF9C "GFXMMU_LUT499H,GFXMMU LUT entry 499 high"
|
|
hexmask.long.tbyte 0xF9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFA0 "GFXMMU_LUT500L,GFXMMU LUT entry 500 low"
|
|
hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFA4 "GFXMMU_LUT500H,GFXMMU LUT entry 500 high"
|
|
hexmask.long.tbyte 0xFA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFA8 "GFXMMU_LUT501L,GFXMMU LUT entry 501 low"
|
|
hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFAC "GFXMMU_LUT501H,GFXMMU LUT entry 501 high"
|
|
hexmask.long.tbyte 0xFAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFB0 "GFXMMU_LUT502L,GFXMMU LUT entry 502 low"
|
|
hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFB4 "GFXMMU_LUT502H,GFXMMU LUT entry 502 high"
|
|
hexmask.long.tbyte 0xFB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFB8 "GFXMMU_LUT503L,GFXMMU LUT entry 503 low"
|
|
hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFBC "GFXMMU_LUT503H,GFXMMU LUT entry 503 high"
|
|
hexmask.long.tbyte 0xFBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFC0 "GFXMMU_LUT504L,GFXMMU LUT entry 504 low"
|
|
hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFC4 "GFXMMU_LUT504H,GFXMMU LUT entry 504 high"
|
|
hexmask.long.tbyte 0xFC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFC8 "GFXMMU_LUT505L,GFXMMU LUT entry 505 low"
|
|
hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFCC "GFXMMU_LUT505H,GFXMMU LUT entry 505 high"
|
|
hexmask.long.tbyte 0xFCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFD0 "GFXMMU_LUT506L,GFXMMU LUT entry 506 low"
|
|
hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFD4 "GFXMMU_LUT506H,GFXMMU LUT entry 506 high"
|
|
hexmask.long.tbyte 0xFD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFD8 "GFXMMU_LUT507L,GFXMMU LUT entry 507 low"
|
|
hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFDC "GFXMMU_LUT507H,GFXMMU LUT entry 507 high"
|
|
hexmask.long.tbyte 0xFDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFE0 "GFXMMU_LUT508L,GFXMMU LUT entry 508 low"
|
|
hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFE4 "GFXMMU_LUT508H,GFXMMU LUT entry 508 high"
|
|
hexmask.long.tbyte 0xFE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFE8 "GFXMMU_LUT509L,GFXMMU LUT entry 509 low"
|
|
hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFEC "GFXMMU_LUT509H,GFXMMU LUT entry 509 high"
|
|
hexmask.long.tbyte 0xFEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFF0 "GFXMMU_LUT510L,GFXMMU LUT entry 510 low"
|
|
hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFF4 "GFXMMU_LUT510H,GFXMMU LUT entry 510 high"
|
|
hexmask.long.tbyte 0xFF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFF8 "GFXMMU_LUT511L,GFXMMU LUT entry 511 low"
|
|
hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFFC "GFXMMU_LUT511H,GFXMMU LUT entry 511 high"
|
|
hexmask.long.tbyte 0xFFC 0.--17. 1. "LO,Line offset"
|
|
group.long 0x2000++0xFFF
|
|
line.long 0x0 "GFXMMU_LUT512L,GFXMMU LUT entry 512 low"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4 "GFXMMU_LUT512H,GFXMMU LUT entry 512 high"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8 "GFXMMU_LUT513L,GFXMMU LUT entry 513 low"
|
|
hexmask.long.byte 0x8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC "GFXMMU_LUT513H,GFXMMU LUT entry 513 high"
|
|
hexmask.long.tbyte 0xC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x10 "GFXMMU_LUT514L,GFXMMU LUT entry 514 low"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x14 "GFXMMU_LUT514H,GFXMMU LUT entry 514 high"
|
|
hexmask.long.tbyte 0x14 0.--17. 1. "LO,Line offset"
|
|
line.long 0x18 "GFXMMU_LUT515L,GFXMMU LUT entry 515 low"
|
|
hexmask.long.byte 0x18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1C "GFXMMU_LUT515H,GFXMMU LUT entry 515 high"
|
|
hexmask.long.tbyte 0x1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x20 "GFXMMU_LUT516L,GFXMMU LUT entry 516 low"
|
|
hexmask.long.byte 0x20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x24 "GFXMMU_LUT516H,GFXMMU LUT entry 516 high"
|
|
hexmask.long.tbyte 0x24 0.--17. 1. "LO,Line offset"
|
|
line.long 0x28 "GFXMMU_LUT517L,GFXMMU LUT entry 517 low"
|
|
hexmask.long.byte 0x28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2C "GFXMMU_LUT517H,GFXMMU LUT entry 517 high"
|
|
hexmask.long.tbyte 0x2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x30 "GFXMMU_LUT518L,GFXMMU LUT entry 518 low"
|
|
hexmask.long.byte 0x30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x34 "GFXMMU_LUT518H,GFXMMU LUT entry 518 high"
|
|
hexmask.long.tbyte 0x34 0.--17. 1. "LO,Line offset"
|
|
line.long 0x38 "GFXMMU_LUT519L,GFXMMU LUT entry 519 low"
|
|
hexmask.long.byte 0x38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3C "GFXMMU_LUT519H,GFXMMU LUT entry 519 high"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x40 "GFXMMU_LUT520L,GFXMMU LUT entry 520 low"
|
|
hexmask.long.byte 0x40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x44 "GFXMMU_LUT520H,GFXMMU LUT entry 520 high"
|
|
hexmask.long.tbyte 0x44 0.--17. 1. "LO,Line offset"
|
|
line.long 0x48 "GFXMMU_LUT521L,GFXMMU LUT entry 521 low"
|
|
hexmask.long.byte 0x48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4C "GFXMMU_LUT521H,GFXMMU LUT entry 521 high"
|
|
hexmask.long.tbyte 0x4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x50 "GFXMMU_LUT522L,GFXMMU LUT entry 522 low"
|
|
hexmask.long.byte 0x50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x54 "GFXMMU_LUT522H,GFXMMU LUT entry 522 high"
|
|
hexmask.long.tbyte 0x54 0.--17. 1. "LO,Line offset"
|
|
line.long 0x58 "GFXMMU_LUT523L,GFXMMU LUT entry 523 low"
|
|
hexmask.long.byte 0x58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5C "GFXMMU_LUT523H,GFXMMU LUT entry 523 high"
|
|
hexmask.long.tbyte 0x5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x60 "GFXMMU_LUT524L,GFXMMU LUT entry 524 low"
|
|
hexmask.long.byte 0x60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x64 "GFXMMU_LUT524H,GFXMMU LUT entry 524 high"
|
|
hexmask.long.tbyte 0x64 0.--17. 1. "LO,Line offset"
|
|
line.long 0x68 "GFXMMU_LUT525L,GFXMMU LUT entry 525 low"
|
|
hexmask.long.byte 0x68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6C "GFXMMU_LUT525H,GFXMMU LUT entry 525 high"
|
|
hexmask.long.tbyte 0x6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x70 "GFXMMU_LUT526L,GFXMMU LUT entry 526 low"
|
|
hexmask.long.byte 0x70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x74 "GFXMMU_LUT526H,GFXMMU LUT entry 526 high"
|
|
hexmask.long.tbyte 0x74 0.--17. 1. "LO,Line offset"
|
|
line.long 0x78 "GFXMMU_LUT527L,GFXMMU LUT entry 527 low"
|
|
hexmask.long.byte 0x78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7C "GFXMMU_LUT527H,GFXMMU LUT entry 527 high"
|
|
hexmask.long.tbyte 0x7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x80 "GFXMMU_LUT528L,GFXMMU LUT entry 528 low"
|
|
hexmask.long.byte 0x80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x84 "GFXMMU_LUT528H,GFXMMU LUT entry 528 high"
|
|
hexmask.long.tbyte 0x84 0.--17. 1. "LO,Line offset"
|
|
line.long 0x88 "GFXMMU_LUT529L,GFXMMU LUT entry 529 low"
|
|
hexmask.long.byte 0x88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8C "GFXMMU_LUT529H,GFXMMU LUT entry 529 high"
|
|
hexmask.long.tbyte 0x8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x90 "GFXMMU_LUT530L,GFXMMU LUT entry 530 low"
|
|
hexmask.long.byte 0x90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x94 "GFXMMU_LUT530H,GFXMMU LUT entry 530 high"
|
|
hexmask.long.tbyte 0x94 0.--17. 1. "LO,Line offset"
|
|
line.long 0x98 "GFXMMU_LUT531L,GFXMMU LUT entry 531 low"
|
|
hexmask.long.byte 0x98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9C "GFXMMU_LUT531H,GFXMMU LUT entry 531 high"
|
|
hexmask.long.tbyte 0x9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA0 "GFXMMU_LUT532L,GFXMMU LUT entry 532 low"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA4 "GFXMMU_LUT532H,GFXMMU LUT entry 532 high"
|
|
hexmask.long.tbyte 0xA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA8 "GFXMMU_LUT533L,GFXMMU LUT entry 533 low"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAC "GFXMMU_LUT533H,GFXMMU LUT entry 533 high"
|
|
hexmask.long.tbyte 0xAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB0 "GFXMMU_LUT534L,GFXMMU LUT entry 534 low"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB4 "GFXMMU_LUT534H,GFXMMU LUT entry 534 high"
|
|
hexmask.long.tbyte 0xB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB8 "GFXMMU_LUT535L,GFXMMU LUT entry 535 low"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBC "GFXMMU_LUT535H,GFXMMU LUT entry 535 high"
|
|
hexmask.long.tbyte 0xBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC0 "GFXMMU_LUT536L,GFXMMU LUT entry 536 low"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC4 "GFXMMU_LUT536H,GFXMMU LUT entry 536 high"
|
|
hexmask.long.tbyte 0xC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC8 "GFXMMU_LUT537L,GFXMMU LUT entry 537 low"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCC "GFXMMU_LUT537H,GFXMMU LUT entry 537 high"
|
|
hexmask.long.tbyte 0xCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD0 "GFXMMU_LUT538L,GFXMMU LUT entry 538 low"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD4 "GFXMMU_LUT538H,GFXMMU LUT entry 538 high"
|
|
hexmask.long.tbyte 0xD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD8 "GFXMMU_LUT539L,GFXMMU LUT entry 539 low"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDC "GFXMMU_LUT539H,GFXMMU LUT entry 539 high"
|
|
hexmask.long.tbyte 0xDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE0 "GFXMMU_LUT540L,GFXMMU LUT entry 540 low"
|
|
hexmask.long.byte 0xE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE4 "GFXMMU_LUT540H,GFXMMU LUT entry 540 high"
|
|
hexmask.long.tbyte 0xE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE8 "GFXMMU_LUT541L,GFXMMU LUT entry 541 low"
|
|
hexmask.long.byte 0xE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEC "GFXMMU_LUT541H,GFXMMU LUT entry 541 high"
|
|
hexmask.long.tbyte 0xEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF0 "GFXMMU_LUT542L,GFXMMU LUT entry 542 low"
|
|
hexmask.long.byte 0xF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF4 "GFXMMU_LUT542H,GFXMMU LUT entry 542 high"
|
|
hexmask.long.tbyte 0xF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF8 "GFXMMU_LUT543L,GFXMMU LUT entry 543 low"
|
|
hexmask.long.byte 0xF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFC "GFXMMU_LUT543H,GFXMMU LUT entry 543 high"
|
|
hexmask.long.tbyte 0xFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x100 "GFXMMU_LUT544L,GFXMMU LUT entry 544 low"
|
|
hexmask.long.byte 0x100 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x100 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x100 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x104 "GFXMMU_LUT544H,GFXMMU LUT entry 544 high"
|
|
hexmask.long.tbyte 0x104 0.--17. 1. "LO,Line offset"
|
|
line.long 0x108 "GFXMMU_LUT545L,GFXMMU LUT entry 545 low"
|
|
hexmask.long.byte 0x108 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x108 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x108 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x10C "GFXMMU_LUT545H,GFXMMU LUT entry 545 high"
|
|
hexmask.long.tbyte 0x10C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x110 "GFXMMU_LUT546L,GFXMMU LUT entry 546 low"
|
|
hexmask.long.byte 0x110 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x110 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x110 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x114 "GFXMMU_LUT546H,GFXMMU LUT entry 546 high"
|
|
hexmask.long.tbyte 0x114 0.--17. 1. "LO,Line offset"
|
|
line.long 0x118 "GFXMMU_LUT547L,GFXMMU LUT entry 547 low"
|
|
hexmask.long.byte 0x118 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x118 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x118 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x11C "GFXMMU_LUT547H,GFXMMU LUT entry 547 high"
|
|
hexmask.long.tbyte 0x11C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x120 "GFXMMU_LUT548L,GFXMMU LUT entry 548 low"
|
|
hexmask.long.byte 0x120 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x120 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x120 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x124 "GFXMMU_LUT548H,GFXMMU LUT entry 548 high"
|
|
hexmask.long.tbyte 0x124 0.--17. 1. "LO,Line offset"
|
|
line.long 0x128 "GFXMMU_LUT549L,GFXMMU LUT entry 549 low"
|
|
hexmask.long.byte 0x128 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x128 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x128 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x12C "GFXMMU_LUT549H,GFXMMU LUT entry 549 high"
|
|
hexmask.long.tbyte 0x12C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x130 "GFXMMU_LUT550L,GFXMMU LUT entry 550 low"
|
|
hexmask.long.byte 0x130 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x130 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x130 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x134 "GFXMMU_LUT550H,GFXMMU LUT entry 550 high"
|
|
hexmask.long.tbyte 0x134 0.--17. 1. "LO,Line offset"
|
|
line.long 0x138 "GFXMMU_LUT551L,GFXMMU LUT entry 551 low"
|
|
hexmask.long.byte 0x138 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x138 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x138 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x13C "GFXMMU_LUT551H,GFXMMU LUT entry 551 high"
|
|
hexmask.long.tbyte 0x13C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x140 "GFXMMU_LUT552L,GFXMMU LUT entry 552 low"
|
|
hexmask.long.byte 0x140 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x140 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x140 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x144 "GFXMMU_LUT552H,GFXMMU LUT entry 552 high"
|
|
hexmask.long.tbyte 0x144 0.--17. 1. "LO,Line offset"
|
|
line.long 0x148 "GFXMMU_LUT553L,GFXMMU LUT entry 553 low"
|
|
hexmask.long.byte 0x148 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x148 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x148 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x14C "GFXMMU_LUT553H,GFXMMU LUT entry 553 high"
|
|
hexmask.long.tbyte 0x14C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x150 "GFXMMU_LUT554L,GFXMMU LUT entry 554 low"
|
|
hexmask.long.byte 0x150 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x150 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x150 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x154 "GFXMMU_LUT554H,GFXMMU LUT entry 554 high"
|
|
hexmask.long.tbyte 0x154 0.--17. 1. "LO,Line offset"
|
|
line.long 0x158 "GFXMMU_LUT555L,GFXMMU LUT entry 555 low"
|
|
hexmask.long.byte 0x158 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x158 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x158 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x15C "GFXMMU_LUT555H,GFXMMU LUT entry 555 high"
|
|
hexmask.long.tbyte 0x15C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x160 "GFXMMU_LUT556L,GFXMMU LUT entry 556 low"
|
|
hexmask.long.byte 0x160 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x160 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x160 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x164 "GFXMMU_LUT556H,GFXMMU LUT entry 556 high"
|
|
hexmask.long.tbyte 0x164 0.--17. 1. "LO,Line offset"
|
|
line.long 0x168 "GFXMMU_LUT557L,GFXMMU LUT entry 557 low"
|
|
hexmask.long.byte 0x168 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x168 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x168 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x16C "GFXMMU_LUT557H,GFXMMU LUT entry 557 high"
|
|
hexmask.long.tbyte 0x16C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x170 "GFXMMU_LUT558L,GFXMMU LUT entry 558 low"
|
|
hexmask.long.byte 0x170 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x170 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x170 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x174 "GFXMMU_LUT558H,GFXMMU LUT entry 558 high"
|
|
hexmask.long.tbyte 0x174 0.--17. 1. "LO,Line offset"
|
|
line.long 0x178 "GFXMMU_LUT559L,GFXMMU LUT entry 559 low"
|
|
hexmask.long.byte 0x178 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x178 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x178 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x17C "GFXMMU_LUT559H,GFXMMU LUT entry 559 high"
|
|
hexmask.long.tbyte 0x17C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x180 "GFXMMU_LUT560L,GFXMMU LUT entry 560 low"
|
|
hexmask.long.byte 0x180 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x180 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x180 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x184 "GFXMMU_LUT560H,GFXMMU LUT entry 560 high"
|
|
hexmask.long.tbyte 0x184 0.--17. 1. "LO,Line offset"
|
|
line.long 0x188 "GFXMMU_LUT561L,GFXMMU LUT entry 561 low"
|
|
hexmask.long.byte 0x188 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x188 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x188 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x18C "GFXMMU_LUT561H,GFXMMU LUT entry 561 high"
|
|
hexmask.long.tbyte 0x18C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x190 "GFXMMU_LUT562L,GFXMMU LUT entry 562 low"
|
|
hexmask.long.byte 0x190 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x190 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x190 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x194 "GFXMMU_LUT562H,GFXMMU LUT entry 562 high"
|
|
hexmask.long.tbyte 0x194 0.--17. 1. "LO,Line offset"
|
|
line.long 0x198 "GFXMMU_LUT563L,GFXMMU LUT entry 563 low"
|
|
hexmask.long.byte 0x198 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x198 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x198 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x19C "GFXMMU_LUT563H,GFXMMU LUT entry 563 high"
|
|
hexmask.long.tbyte 0x19C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1A0 "GFXMMU_LUT564L,GFXMMU LUT entry 564 low"
|
|
hexmask.long.byte 0x1A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1A4 "GFXMMU_LUT564H,GFXMMU LUT entry 564 high"
|
|
hexmask.long.tbyte 0x1A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1A8 "GFXMMU_LUT565L,GFXMMU LUT entry 565 low"
|
|
hexmask.long.byte 0x1A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1AC "GFXMMU_LUT565H,GFXMMU LUT entry 565 high"
|
|
hexmask.long.tbyte 0x1AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1B0 "GFXMMU_LUT566L,GFXMMU LUT entry 566 low"
|
|
hexmask.long.byte 0x1B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1B4 "GFXMMU_LUT566H,GFXMMU LUT entry 566 high"
|
|
hexmask.long.tbyte 0x1B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1B8 "GFXMMU_LUT567L,GFXMMU LUT entry 567 low"
|
|
hexmask.long.byte 0x1B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1BC "GFXMMU_LUT567H,GFXMMU LUT entry 567 high"
|
|
hexmask.long.tbyte 0x1BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1C0 "GFXMMU_LUT568L,GFXMMU LUT entry 568 low"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1C4 "GFXMMU_LUT568H,GFXMMU LUT entry 568 high"
|
|
hexmask.long.tbyte 0x1C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1C8 "GFXMMU_LUT569L,GFXMMU LUT entry 569 low"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1CC "GFXMMU_LUT569H,GFXMMU LUT entry 569 high"
|
|
hexmask.long.tbyte 0x1CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1D0 "GFXMMU_LUT570L,GFXMMU LUT entry 570 low"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1D4 "GFXMMU_LUT570H,GFXMMU LUT entry 570 high"
|
|
hexmask.long.tbyte 0x1D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1D8 "GFXMMU_LUT571L,GFXMMU LUT entry 571 low"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1DC "GFXMMU_LUT571H,GFXMMU LUT entry 571 high"
|
|
hexmask.long.tbyte 0x1DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1E0 "GFXMMU_LUT572L,GFXMMU LUT entry 572 low"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1E4 "GFXMMU_LUT572H,GFXMMU LUT entry 572 high"
|
|
hexmask.long.tbyte 0x1E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1E8 "GFXMMU_LUT573L,GFXMMU LUT entry 573 low"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1EC "GFXMMU_LUT573H,GFXMMU LUT entry 573 high"
|
|
hexmask.long.tbyte 0x1EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1F0 "GFXMMU_LUT574L,GFXMMU LUT entry 574 low"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1F4 "GFXMMU_LUT574H,GFXMMU LUT entry 574 high"
|
|
hexmask.long.tbyte 0x1F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x1F8 "GFXMMU_LUT575L,GFXMMU LUT entry 575 low"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x1F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x1F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x1FC "GFXMMU_LUT575H,GFXMMU LUT entry 575 high"
|
|
hexmask.long.tbyte 0x1FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x200 "GFXMMU_LUT576L,GFXMMU LUT entry 576 low"
|
|
hexmask.long.byte 0x200 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x200 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x200 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x204 "GFXMMU_LUT576H,GFXMMU LUT entry 576 high"
|
|
hexmask.long.tbyte 0x204 0.--17. 1. "LO,Line offset"
|
|
line.long 0x208 "GFXMMU_LUT577L,GFXMMU LUT entry 577 low"
|
|
hexmask.long.byte 0x208 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x208 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x208 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x20C "GFXMMU_LUT577H,GFXMMU LUT entry 577 high"
|
|
hexmask.long.tbyte 0x20C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x210 "GFXMMU_LUT578L,GFXMMU LUT entry 578 low"
|
|
hexmask.long.byte 0x210 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x210 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x210 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x214 "GFXMMU_LUT578H,GFXMMU LUT entry 578 high"
|
|
hexmask.long.tbyte 0x214 0.--17. 1. "LO,Line offset"
|
|
line.long 0x218 "GFXMMU_LUT579L,GFXMMU LUT entry 579 low"
|
|
hexmask.long.byte 0x218 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x218 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x218 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x21C "GFXMMU_LUT579H,GFXMMU LUT entry 579 high"
|
|
hexmask.long.tbyte 0x21C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x220 "GFXMMU_LUT580L,GFXMMU LUT entry 580 low"
|
|
hexmask.long.byte 0x220 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x220 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x220 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x224 "GFXMMU_LUT580H,GFXMMU LUT entry 580 high"
|
|
hexmask.long.tbyte 0x224 0.--17. 1. "LO,Line offset"
|
|
line.long 0x228 "GFXMMU_LUT581L,GFXMMU LUT entry 581 low"
|
|
hexmask.long.byte 0x228 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x228 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x228 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x22C "GFXMMU_LUT581H,GFXMMU LUT entry 581 high"
|
|
hexmask.long.tbyte 0x22C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x230 "GFXMMU_LUT582L,GFXMMU LUT entry 582 low"
|
|
hexmask.long.byte 0x230 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x230 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x230 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x234 "GFXMMU_LUT582H,GFXMMU LUT entry 582 high"
|
|
hexmask.long.tbyte 0x234 0.--17. 1. "LO,Line offset"
|
|
line.long 0x238 "GFXMMU_LUT583L,GFXMMU LUT entry 583 low"
|
|
hexmask.long.byte 0x238 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x238 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x238 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x23C "GFXMMU_LUT583H,GFXMMU LUT entry 583 high"
|
|
hexmask.long.tbyte 0x23C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x240 "GFXMMU_LUT584L,GFXMMU LUT entry 584 low"
|
|
hexmask.long.byte 0x240 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x240 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x240 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x244 "GFXMMU_LUT584H,GFXMMU LUT entry 584 high"
|
|
hexmask.long.tbyte 0x244 0.--17. 1. "LO,Line offset"
|
|
line.long 0x248 "GFXMMU_LUT585L,GFXMMU LUT entry 585 low"
|
|
hexmask.long.byte 0x248 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x248 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x248 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x24C "GFXMMU_LUT585H,GFXMMU LUT entry 585 high"
|
|
hexmask.long.tbyte 0x24C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x250 "GFXMMU_LUT586L,GFXMMU LUT entry 586 low"
|
|
hexmask.long.byte 0x250 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x250 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x250 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x254 "GFXMMU_LUT586H,GFXMMU LUT entry 586 high"
|
|
hexmask.long.tbyte 0x254 0.--17. 1. "LO,Line offset"
|
|
line.long 0x258 "GFXMMU_LUT587L,GFXMMU LUT entry 587 low"
|
|
hexmask.long.byte 0x258 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x258 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x258 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x25C "GFXMMU_LUT587H,GFXMMU LUT entry 587 high"
|
|
hexmask.long.tbyte 0x25C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x260 "GFXMMU_LUT588L,GFXMMU LUT entry 588 low"
|
|
hexmask.long.byte 0x260 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x260 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x260 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x264 "GFXMMU_LUT588H,GFXMMU LUT entry 588 high"
|
|
hexmask.long.tbyte 0x264 0.--17. 1. "LO,Line offset"
|
|
line.long 0x268 "GFXMMU_LUT589L,GFXMMU LUT entry 589 low"
|
|
hexmask.long.byte 0x268 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x268 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x268 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x26C "GFXMMU_LUT589H,GFXMMU LUT entry 589 high"
|
|
hexmask.long.tbyte 0x26C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x270 "GFXMMU_LUT590L,GFXMMU LUT entry 590 low"
|
|
hexmask.long.byte 0x270 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x270 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x270 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x274 "GFXMMU_LUT590H,GFXMMU LUT entry 590 high"
|
|
hexmask.long.tbyte 0x274 0.--17. 1. "LO,Line offset"
|
|
line.long 0x278 "GFXMMU_LUT591L,GFXMMU LUT entry 591 low"
|
|
hexmask.long.byte 0x278 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x278 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x278 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x27C "GFXMMU_LUT591H,GFXMMU LUT entry 591 high"
|
|
hexmask.long.tbyte 0x27C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x280 "GFXMMU_LUT592L,GFXMMU LUT entry 592 low"
|
|
hexmask.long.byte 0x280 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x280 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x280 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x284 "GFXMMU_LUT592H,GFXMMU LUT entry 592 high"
|
|
hexmask.long.tbyte 0x284 0.--17. 1. "LO,Line offset"
|
|
line.long 0x288 "GFXMMU_LUT593L,GFXMMU LUT entry 593 low"
|
|
hexmask.long.byte 0x288 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x288 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x288 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x28C "GFXMMU_LUT593H,GFXMMU LUT entry 593 high"
|
|
hexmask.long.tbyte 0x28C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x290 "GFXMMU_LUT594L,GFXMMU LUT entry 594 low"
|
|
hexmask.long.byte 0x290 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x290 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x290 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x294 "GFXMMU_LUT594H,GFXMMU LUT entry 594 high"
|
|
hexmask.long.tbyte 0x294 0.--17. 1. "LO,Line offset"
|
|
line.long 0x298 "GFXMMU_LUT595L,GFXMMU LUT entry 595 low"
|
|
hexmask.long.byte 0x298 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x298 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x298 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x29C "GFXMMU_LUT595H,GFXMMU LUT entry 595 high"
|
|
hexmask.long.tbyte 0x29C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2A0 "GFXMMU_LUT596L,GFXMMU LUT entry 596 low"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2A4 "GFXMMU_LUT596H,GFXMMU LUT entry 596 high"
|
|
hexmask.long.tbyte 0x2A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2A8 "GFXMMU_LUT597L,GFXMMU LUT entry 597 low"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2AC "GFXMMU_LUT597H,GFXMMU LUT entry 597 high"
|
|
hexmask.long.tbyte 0x2AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2B0 "GFXMMU_LUT598L,GFXMMU LUT entry 598 low"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2B4 "GFXMMU_LUT598H,GFXMMU LUT entry 598 high"
|
|
hexmask.long.tbyte 0x2B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2B8 "GFXMMU_LUT599L,GFXMMU LUT entry 599 low"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2BC "GFXMMU_LUT599H,GFXMMU LUT entry 599 high"
|
|
hexmask.long.tbyte 0x2BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2C0 "GFXMMU_LUT600L,GFXMMU LUT entry 600 low"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2C4 "GFXMMU_LUT600H,GFXMMU LUT entry 600 high"
|
|
hexmask.long.tbyte 0x2C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2C8 "GFXMMU_LUT601L,GFXMMU LUT entry 601 low"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2CC "GFXMMU_LUT601H,GFXMMU LUT entry 601 high"
|
|
hexmask.long.tbyte 0x2CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2D0 "GFXMMU_LUT602L,GFXMMU LUT entry 602 low"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2D4 "GFXMMU_LUT602H,GFXMMU LUT entry 602 high"
|
|
hexmask.long.tbyte 0x2D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2D8 "GFXMMU_LUT603L,GFXMMU LUT entry 603 low"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2DC "GFXMMU_LUT603H,GFXMMU LUT entry 603 high"
|
|
hexmask.long.tbyte 0x2DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2E0 "GFXMMU_LUT604L,GFXMMU LUT entry 604 low"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2E4 "GFXMMU_LUT604H,GFXMMU LUT entry 604 high"
|
|
hexmask.long.tbyte 0x2E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2E8 "GFXMMU_LUT605L,GFXMMU LUT entry 605 low"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2EC "GFXMMU_LUT605H,GFXMMU LUT entry 605 high"
|
|
hexmask.long.tbyte 0x2EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2F0 "GFXMMU_LUT606L,GFXMMU LUT entry 606 low"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2F4 "GFXMMU_LUT606H,GFXMMU LUT entry 606 high"
|
|
hexmask.long.tbyte 0x2F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x2F8 "GFXMMU_LUT607L,GFXMMU LUT entry 607 low"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x2F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x2F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x2FC "GFXMMU_LUT607H,GFXMMU LUT entry 607 high"
|
|
hexmask.long.tbyte 0x2FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x300 "GFXMMU_LUT608L,GFXMMU LUT entry 608 low"
|
|
hexmask.long.byte 0x300 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x300 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x300 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x304 "GFXMMU_LUT608H,GFXMMU LUT entry 608 high"
|
|
hexmask.long.tbyte 0x304 0.--17. 1. "LO,Line offset"
|
|
line.long 0x308 "GFXMMU_LUT609L,GFXMMU LUT entry 609 low"
|
|
hexmask.long.byte 0x308 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x308 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x308 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x30C "GFXMMU_LUT609H,GFXMMU LUT entry 609 high"
|
|
hexmask.long.tbyte 0x30C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x310 "GFXMMU_LUT610L,GFXMMU LUT entry 610 low"
|
|
hexmask.long.byte 0x310 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x310 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x310 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x314 "GFXMMU_LUT610H,GFXMMU LUT entry 610 high"
|
|
hexmask.long.tbyte 0x314 0.--17. 1. "LO,Line offset"
|
|
line.long 0x318 "GFXMMU_LUT611L,GFXMMU LUT entry 611 low"
|
|
hexmask.long.byte 0x318 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x318 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x318 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x31C "GFXMMU_LUT611H,GFXMMU LUT entry 611 high"
|
|
hexmask.long.tbyte 0x31C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x320 "GFXMMU_LUT612L,GFXMMU LUT entry 612 low"
|
|
hexmask.long.byte 0x320 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x320 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x320 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x324 "GFXMMU_LUT612H,GFXMMU LUT entry 612 high"
|
|
hexmask.long.tbyte 0x324 0.--17. 1. "LO,Line offset"
|
|
line.long 0x328 "GFXMMU_LUT613L,GFXMMU LUT entry 613 low"
|
|
hexmask.long.byte 0x328 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x328 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x328 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x32C "GFXMMU_LUT613H,GFXMMU LUT entry 613 high"
|
|
hexmask.long.tbyte 0x32C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x330 "GFXMMU_LUT614L,GFXMMU LUT entry 614 low"
|
|
hexmask.long.byte 0x330 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x330 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x330 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x334 "GFXMMU_LUT614H,GFXMMU LUT entry 614 high"
|
|
hexmask.long.tbyte 0x334 0.--17. 1. "LO,Line offset"
|
|
line.long 0x338 "GFXMMU_LUT615L,GFXMMU LUT entry 615 low"
|
|
hexmask.long.byte 0x338 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x338 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x338 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x33C "GFXMMU_LUT615H,GFXMMU LUT entry 615 high"
|
|
hexmask.long.tbyte 0x33C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x340 "GFXMMU_LUT616L,GFXMMU LUT entry 616 low"
|
|
hexmask.long.byte 0x340 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x340 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x340 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x344 "GFXMMU_LUT616H,GFXMMU LUT entry 616 high"
|
|
hexmask.long.tbyte 0x344 0.--17. 1. "LO,Line offset"
|
|
line.long 0x348 "GFXMMU_LUT617L,GFXMMU LUT entry 617 low"
|
|
hexmask.long.byte 0x348 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x348 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x348 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x34C "GFXMMU_LUT617H,GFXMMU LUT entry 617 high"
|
|
hexmask.long.tbyte 0x34C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x350 "GFXMMU_LUT618L,GFXMMU LUT entry 618 low"
|
|
hexmask.long.byte 0x350 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x350 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x350 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x354 "GFXMMU_LUT618H,GFXMMU LUT entry 618 high"
|
|
hexmask.long.tbyte 0x354 0.--17. 1. "LO,Line offset"
|
|
line.long 0x358 "GFXMMU_LUT619L,GFXMMU LUT entry 619 low"
|
|
hexmask.long.byte 0x358 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x358 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x358 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x35C "GFXMMU_LUT619H,GFXMMU LUT entry 619 high"
|
|
hexmask.long.tbyte 0x35C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x360 "GFXMMU_LUT620L,GFXMMU LUT entry 620 low"
|
|
hexmask.long.byte 0x360 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x360 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x360 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x364 "GFXMMU_LUT620H,GFXMMU LUT entry 620 high"
|
|
hexmask.long.tbyte 0x364 0.--17. 1. "LO,Line offset"
|
|
line.long 0x368 "GFXMMU_LUT621L,GFXMMU LUT entry 621 low"
|
|
hexmask.long.byte 0x368 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x368 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x368 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x36C "GFXMMU_LUT621H,GFXMMU LUT entry 621 high"
|
|
hexmask.long.tbyte 0x36C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x370 "GFXMMU_LUT622L,GFXMMU LUT entry 622 low"
|
|
hexmask.long.byte 0x370 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x370 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x370 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x374 "GFXMMU_LUT622H,GFXMMU LUT entry 622 high"
|
|
hexmask.long.tbyte 0x374 0.--17. 1. "LO,Line offset"
|
|
line.long 0x378 "GFXMMU_LUT623L,GFXMMU LUT entry 623 low"
|
|
hexmask.long.byte 0x378 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x378 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x378 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x37C "GFXMMU_LUT623H,GFXMMU LUT entry 623 high"
|
|
hexmask.long.tbyte 0x37C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x380 "GFXMMU_LUT624L,GFXMMU LUT entry 624 low"
|
|
hexmask.long.byte 0x380 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x380 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x380 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x384 "GFXMMU_LUT624H,GFXMMU LUT entry 624 high"
|
|
hexmask.long.tbyte 0x384 0.--17. 1. "LO,Line offset"
|
|
line.long 0x388 "GFXMMU_LUT625L,GFXMMU LUT entry 625 low"
|
|
hexmask.long.byte 0x388 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x388 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x388 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x38C "GFXMMU_LUT625H,GFXMMU LUT entry 625 high"
|
|
hexmask.long.tbyte 0x38C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x390 "GFXMMU_LUT626L,GFXMMU LUT entry 626 low"
|
|
hexmask.long.byte 0x390 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x390 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x390 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x394 "GFXMMU_LUT626H,GFXMMU LUT entry 626 high"
|
|
hexmask.long.tbyte 0x394 0.--17. 1. "LO,Line offset"
|
|
line.long 0x398 "GFXMMU_LUT627L,GFXMMU LUT entry 627 low"
|
|
hexmask.long.byte 0x398 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x398 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x398 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x39C "GFXMMU_LUT627H,GFXMMU LUT entry 627 high"
|
|
hexmask.long.tbyte 0x39C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3A0 "GFXMMU_LUT628L,GFXMMU LUT entry 628 low"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3A4 "GFXMMU_LUT628H,GFXMMU LUT entry 628 high"
|
|
hexmask.long.tbyte 0x3A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3A8 "GFXMMU_LUT629L,GFXMMU LUT entry 629 low"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3AC "GFXMMU_LUT629H,GFXMMU LUT entry 629 high"
|
|
hexmask.long.tbyte 0x3AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3B0 "GFXMMU_LUT630L,GFXMMU LUT entry 630 low"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3B4 "GFXMMU_LUT630H,GFXMMU LUT entry 630 high"
|
|
hexmask.long.tbyte 0x3B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3B8 "GFXMMU_LUT631L,GFXMMU LUT entry 631 low"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3BC "GFXMMU_LUT631H,GFXMMU LUT entry 631 high"
|
|
hexmask.long.tbyte 0x3BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3C0 "GFXMMU_LUT632L,GFXMMU LUT entry 632 low"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3C4 "GFXMMU_LUT632H,GFXMMU LUT entry 632 high"
|
|
hexmask.long.tbyte 0x3C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3C8 "GFXMMU_LUT633L,GFXMMU LUT entry 633 low"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3CC "GFXMMU_LUT633H,GFXMMU LUT entry 633 high"
|
|
hexmask.long.tbyte 0x3CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3D0 "GFXMMU_LUT634L,GFXMMU LUT entry 634 low"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3D4 "GFXMMU_LUT634H,GFXMMU LUT entry 634 high"
|
|
hexmask.long.tbyte 0x3D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3D8 "GFXMMU_LUT635L,GFXMMU LUT entry 635 low"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3DC "GFXMMU_LUT635H,GFXMMU LUT entry 635 high"
|
|
hexmask.long.tbyte 0x3DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3E0 "GFXMMU_LUT636L,GFXMMU LUT entry 636 low"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3E4 "GFXMMU_LUT636H,GFXMMU LUT entry 636 high"
|
|
hexmask.long.tbyte 0x3E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3E8 "GFXMMU_LUT637L,GFXMMU LUT entry 637 low"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3EC "GFXMMU_LUT637H,GFXMMU LUT entry 637 high"
|
|
hexmask.long.tbyte 0x3EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3F0 "GFXMMU_LUT638L,GFXMMU LUT entry 638 low"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3F4 "GFXMMU_LUT638H,GFXMMU LUT entry 638 high"
|
|
hexmask.long.tbyte 0x3F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x3F8 "GFXMMU_LUT639L,GFXMMU LUT entry 639 low"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x3F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x3F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x3FC "GFXMMU_LUT639H,GFXMMU LUT entry 639 high"
|
|
hexmask.long.tbyte 0x3FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x400 "GFXMMU_LUT640L,GFXMMU LUT entry 640 low"
|
|
hexmask.long.byte 0x400 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x400 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x400 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x404 "GFXMMU_LUT640H,GFXMMU LUT entry 640 high"
|
|
hexmask.long.tbyte 0x404 0.--17. 1. "LO,Line offset"
|
|
line.long 0x408 "GFXMMU_LUT641L,GFXMMU LUT entry 641 low"
|
|
hexmask.long.byte 0x408 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x408 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x408 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x40C "GFXMMU_LUT641H,GFXMMU LUT entry 641 high"
|
|
hexmask.long.tbyte 0x40C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x410 "GFXMMU_LUT642L,GFXMMU LUT entry 642 low"
|
|
hexmask.long.byte 0x410 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x410 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x410 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x414 "GFXMMU_LUT642H,GFXMMU LUT entry 642 high"
|
|
hexmask.long.tbyte 0x414 0.--17. 1. "LO,Line offset"
|
|
line.long 0x418 "GFXMMU_LUT643L,GFXMMU LUT entry 643 low"
|
|
hexmask.long.byte 0x418 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x418 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x418 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x41C "GFXMMU_LUT643H,GFXMMU LUT entry 643 high"
|
|
hexmask.long.tbyte 0x41C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x420 "GFXMMU_LUT644L,GFXMMU LUT entry 644 low"
|
|
hexmask.long.byte 0x420 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x420 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x420 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x424 "GFXMMU_LUT644H,GFXMMU LUT entry 644 high"
|
|
hexmask.long.tbyte 0x424 0.--17. 1. "LO,Line offset"
|
|
line.long 0x428 "GFXMMU_LUT645L,GFXMMU LUT entry 645 low"
|
|
hexmask.long.byte 0x428 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x428 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x428 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x42C "GFXMMU_LUT645H,GFXMMU LUT entry 645 high"
|
|
hexmask.long.tbyte 0x42C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x430 "GFXMMU_LUT646L,GFXMMU LUT entry 646 low"
|
|
hexmask.long.byte 0x430 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x430 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x430 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x434 "GFXMMU_LUT646H,GFXMMU LUT entry 646 high"
|
|
hexmask.long.tbyte 0x434 0.--17. 1. "LO,Line offset"
|
|
line.long 0x438 "GFXMMU_LUT647L,GFXMMU LUT entry 647 low"
|
|
hexmask.long.byte 0x438 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x438 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x438 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x43C "GFXMMU_LUT647H,GFXMMU LUT entry 647 high"
|
|
hexmask.long.tbyte 0x43C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x440 "GFXMMU_LUT648L,GFXMMU LUT entry 648 low"
|
|
hexmask.long.byte 0x440 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x440 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x440 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x444 "GFXMMU_LUT648H,GFXMMU LUT entry 648 high"
|
|
hexmask.long.tbyte 0x444 0.--17. 1. "LO,Line offset"
|
|
line.long 0x448 "GFXMMU_LUT649L,GFXMMU LUT entry 649 low"
|
|
hexmask.long.byte 0x448 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x448 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x448 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x44C "GFXMMU_LUT649H,GFXMMU LUT entry 649 high"
|
|
hexmask.long.tbyte 0x44C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x450 "GFXMMU_LUT650L,GFXMMU LUT entry 650 low"
|
|
hexmask.long.byte 0x450 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x450 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x450 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x454 "GFXMMU_LUT650H,GFXMMU LUT entry 650 high"
|
|
hexmask.long.tbyte 0x454 0.--17. 1. "LO,Line offset"
|
|
line.long 0x458 "GFXMMU_LUT651L,GFXMMU LUT entry 651 low"
|
|
hexmask.long.byte 0x458 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x458 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x458 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x45C "GFXMMU_LUT651H,GFXMMU LUT entry 651 high"
|
|
hexmask.long.tbyte 0x45C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x460 "GFXMMU_LUT652L,GFXMMU LUT entry 652 low"
|
|
hexmask.long.byte 0x460 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x460 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x460 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x464 "GFXMMU_LUT652H,GFXMMU LUT entry 652 high"
|
|
hexmask.long.tbyte 0x464 0.--17. 1. "LO,Line offset"
|
|
line.long 0x468 "GFXMMU_LUT653L,GFXMMU LUT entry 653 low"
|
|
hexmask.long.byte 0x468 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x468 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x468 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x46C "GFXMMU_LUT653H,GFXMMU LUT entry 653 high"
|
|
hexmask.long.tbyte 0x46C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x470 "GFXMMU_LUT654L,GFXMMU LUT entry 654 low"
|
|
hexmask.long.byte 0x470 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x470 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x470 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x474 "GFXMMU_LUT654H,GFXMMU LUT entry 654 high"
|
|
hexmask.long.tbyte 0x474 0.--17. 1. "LO,Line offset"
|
|
line.long 0x478 "GFXMMU_LUT655L,GFXMMU LUT entry 655 low"
|
|
hexmask.long.byte 0x478 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x478 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x478 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x47C "GFXMMU_LUT655H,GFXMMU LUT entry 655 high"
|
|
hexmask.long.tbyte 0x47C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x480 "GFXMMU_LUT656L,GFXMMU LUT entry 656 low"
|
|
hexmask.long.byte 0x480 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x480 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x480 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x484 "GFXMMU_LUT656H,GFXMMU LUT entry 656 high"
|
|
hexmask.long.tbyte 0x484 0.--17. 1. "LO,Line offset"
|
|
line.long 0x488 "GFXMMU_LUT657L,GFXMMU LUT entry 657 low"
|
|
hexmask.long.byte 0x488 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x488 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x488 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x48C "GFXMMU_LUT657H,GFXMMU LUT entry 657 high"
|
|
hexmask.long.tbyte 0x48C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x490 "GFXMMU_LUT658L,GFXMMU LUT entry 658 low"
|
|
hexmask.long.byte 0x490 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x490 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x490 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x494 "GFXMMU_LUT658H,GFXMMU LUT entry 658 high"
|
|
hexmask.long.tbyte 0x494 0.--17. 1. "LO,Line offset"
|
|
line.long 0x498 "GFXMMU_LUT659L,GFXMMU LUT entry 659 low"
|
|
hexmask.long.byte 0x498 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x498 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x498 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x49C "GFXMMU_LUT659H,GFXMMU LUT entry 659 high"
|
|
hexmask.long.tbyte 0x49C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4A0 "GFXMMU_LUT660L,GFXMMU LUT entry 660 low"
|
|
hexmask.long.byte 0x4A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4A4 "GFXMMU_LUT660H,GFXMMU LUT entry 660 high"
|
|
hexmask.long.tbyte 0x4A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4A8 "GFXMMU_LUT661L,GFXMMU LUT entry 661 low"
|
|
hexmask.long.byte 0x4A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4AC "GFXMMU_LUT661H,GFXMMU LUT entry 661 high"
|
|
hexmask.long.tbyte 0x4AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4B0 "GFXMMU_LUT662L,GFXMMU LUT entry 662 low"
|
|
hexmask.long.byte 0x4B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4B4 "GFXMMU_LUT662H,GFXMMU LUT entry 662 high"
|
|
hexmask.long.tbyte 0x4B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4B8 "GFXMMU_LUT663L,GFXMMU LUT entry 663 low"
|
|
hexmask.long.byte 0x4B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4BC "GFXMMU_LUT663H,GFXMMU LUT entry 663 high"
|
|
hexmask.long.tbyte 0x4BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4C0 "GFXMMU_LUT664L,GFXMMU LUT entry 664 low"
|
|
hexmask.long.byte 0x4C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4C4 "GFXMMU_LUT664H,GFXMMU LUT entry 664 high"
|
|
hexmask.long.tbyte 0x4C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4C8 "GFXMMU_LUT665L,GFXMMU LUT entry 665 low"
|
|
hexmask.long.byte 0x4C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4CC "GFXMMU_LUT665H,GFXMMU LUT entry 665 high"
|
|
hexmask.long.tbyte 0x4CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4D0 "GFXMMU_LUT666L,GFXMMU LUT entry 666 low"
|
|
hexmask.long.byte 0x4D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4D4 "GFXMMU_LUT666H,GFXMMU LUT entry 666 high"
|
|
hexmask.long.tbyte 0x4D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4D8 "GFXMMU_LUT667L,GFXMMU LUT entry 667 low"
|
|
hexmask.long.byte 0x4D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4DC "GFXMMU_LUT667H,GFXMMU LUT entry 667 high"
|
|
hexmask.long.tbyte 0x4DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4E0 "GFXMMU_LUT668L,GFXMMU LUT entry 668 low"
|
|
hexmask.long.byte 0x4E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4E4 "GFXMMU_LUT668H,GFXMMU LUT entry 668 high"
|
|
hexmask.long.tbyte 0x4E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4E8 "GFXMMU_LUT669L,GFXMMU LUT entry 669 low"
|
|
hexmask.long.byte 0x4E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4EC "GFXMMU_LUT669H,GFXMMU LUT entry 669 high"
|
|
hexmask.long.tbyte 0x4EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4F0 "GFXMMU_LUT670L,GFXMMU LUT entry 670 low"
|
|
hexmask.long.byte 0x4F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4F4 "GFXMMU_LUT670H,GFXMMU LUT entry 670 high"
|
|
hexmask.long.tbyte 0x4F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x4F8 "GFXMMU_LUT671L,GFXMMU LUT entry 671 low"
|
|
hexmask.long.byte 0x4F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x4F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x4F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x4FC "GFXMMU_LUT671H,GFXMMU LUT entry 671 high"
|
|
hexmask.long.tbyte 0x4FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x500 "GFXMMU_LUT672L,GFXMMU LUT entry 672 low"
|
|
hexmask.long.byte 0x500 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x500 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x500 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x504 "GFXMMU_LUT672H,GFXMMU LUT entry 672 high"
|
|
hexmask.long.tbyte 0x504 0.--17. 1. "LO,Line offset"
|
|
line.long 0x508 "GFXMMU_LUT673L,GFXMMU LUT entry 673 low"
|
|
hexmask.long.byte 0x508 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x508 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x508 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x50C "GFXMMU_LUT673H,GFXMMU LUT entry 673 high"
|
|
hexmask.long.tbyte 0x50C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x510 "GFXMMU_LUT674L,GFXMMU LUT entry 674 low"
|
|
hexmask.long.byte 0x510 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x510 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x510 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x514 "GFXMMU_LUT674H,GFXMMU LUT entry 674 high"
|
|
hexmask.long.tbyte 0x514 0.--17. 1. "LO,Line offset"
|
|
line.long 0x518 "GFXMMU_LUT675L,GFXMMU LUT entry 675 low"
|
|
hexmask.long.byte 0x518 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x518 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x518 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x51C "GFXMMU_LUT675H,GFXMMU LUT entry 675 high"
|
|
hexmask.long.tbyte 0x51C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x520 "GFXMMU_LUT676L,GFXMMU LUT entry 676 low"
|
|
hexmask.long.byte 0x520 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x520 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x520 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x524 "GFXMMU_LUT676H,GFXMMU LUT entry 676 high"
|
|
hexmask.long.tbyte 0x524 0.--17. 1. "LO,Line offset"
|
|
line.long 0x528 "GFXMMU_LUT677L,GFXMMU LUT entry 677 low"
|
|
hexmask.long.byte 0x528 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x528 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x528 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x52C "GFXMMU_LUT677H,GFXMMU LUT entry 677 high"
|
|
hexmask.long.tbyte 0x52C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x530 "GFXMMU_LUT678L,GFXMMU LUT entry 678 low"
|
|
hexmask.long.byte 0x530 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x530 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x530 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x534 "GFXMMU_LUT678H,GFXMMU LUT entry 678 high"
|
|
hexmask.long.tbyte 0x534 0.--17. 1. "LO,Line offset"
|
|
line.long 0x538 "GFXMMU_LUT679L,GFXMMU LUT entry 679 low"
|
|
hexmask.long.byte 0x538 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x538 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x538 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x53C "GFXMMU_LUT679H,GFXMMU LUT entry 679 high"
|
|
hexmask.long.tbyte 0x53C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x540 "GFXMMU_LUT680L,GFXMMU LUT entry 680 low"
|
|
hexmask.long.byte 0x540 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x540 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x540 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x544 "GFXMMU_LUT680H,GFXMMU LUT entry 680 high"
|
|
hexmask.long.tbyte 0x544 0.--17. 1. "LO,Line offset"
|
|
line.long 0x548 "GFXMMU_LUT681L,GFXMMU LUT entry 681 low"
|
|
hexmask.long.byte 0x548 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x548 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x548 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x54C "GFXMMU_LUT681H,GFXMMU LUT entry 681 high"
|
|
hexmask.long.tbyte 0x54C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x550 "GFXMMU_LUT682L,GFXMMU LUT entry 682 low"
|
|
hexmask.long.byte 0x550 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x550 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x550 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x554 "GFXMMU_LUT682H,GFXMMU LUT entry 682 high"
|
|
hexmask.long.tbyte 0x554 0.--17. 1. "LO,Line offset"
|
|
line.long 0x558 "GFXMMU_LUT683L,GFXMMU LUT entry 683 low"
|
|
hexmask.long.byte 0x558 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x558 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x558 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x55C "GFXMMU_LUT683H,GFXMMU LUT entry 683 high"
|
|
hexmask.long.tbyte 0x55C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x560 "GFXMMU_LUT684L,GFXMMU LUT entry 684 low"
|
|
hexmask.long.byte 0x560 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x560 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x560 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x564 "GFXMMU_LUT684H,GFXMMU LUT entry 684 high"
|
|
hexmask.long.tbyte 0x564 0.--17. 1. "LO,Line offset"
|
|
line.long 0x568 "GFXMMU_LUT685L,GFXMMU LUT entry 685 low"
|
|
hexmask.long.byte 0x568 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x568 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x568 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x56C "GFXMMU_LUT685H,GFXMMU LUT entry 685 high"
|
|
hexmask.long.tbyte 0x56C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x570 "GFXMMU_LUT686L,GFXMMU LUT entry 686 low"
|
|
hexmask.long.byte 0x570 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x570 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x570 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x574 "GFXMMU_LUT686H,GFXMMU LUT entry 686 high"
|
|
hexmask.long.tbyte 0x574 0.--17. 1. "LO,Line offset"
|
|
line.long 0x578 "GFXMMU_LUT687L,GFXMMU LUT entry 687 low"
|
|
hexmask.long.byte 0x578 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x578 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x578 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x57C "GFXMMU_LUT687H,GFXMMU LUT entry 687 high"
|
|
hexmask.long.tbyte 0x57C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x580 "GFXMMU_LUT688L,GFXMMU LUT entry 688 low"
|
|
hexmask.long.byte 0x580 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x580 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x580 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x584 "GFXMMU_LUT688H,GFXMMU LUT entry 688 high"
|
|
hexmask.long.tbyte 0x584 0.--17. 1. "LO,Line offset"
|
|
line.long 0x588 "GFXMMU_LUT689L,GFXMMU LUT entry 689 low"
|
|
hexmask.long.byte 0x588 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x588 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x588 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x58C "GFXMMU_LUT689H,GFXMMU LUT entry 689 high"
|
|
hexmask.long.tbyte 0x58C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x590 "GFXMMU_LUT690L,GFXMMU LUT entry 690 low"
|
|
hexmask.long.byte 0x590 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x590 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x590 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x594 "GFXMMU_LUT690H,GFXMMU LUT entry 690 high"
|
|
hexmask.long.tbyte 0x594 0.--17. 1. "LO,Line offset"
|
|
line.long 0x598 "GFXMMU_LUT691L,GFXMMU LUT entry 691 low"
|
|
hexmask.long.byte 0x598 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x598 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x598 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x59C "GFXMMU_LUT691H,GFXMMU LUT entry 691 high"
|
|
hexmask.long.tbyte 0x59C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5A0 "GFXMMU_LUT692L,GFXMMU LUT entry 692 low"
|
|
hexmask.long.byte 0x5A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5A4 "GFXMMU_LUT692H,GFXMMU LUT entry 692 high"
|
|
hexmask.long.tbyte 0x5A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5A8 "GFXMMU_LUT693L,GFXMMU LUT entry 693 low"
|
|
hexmask.long.byte 0x5A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5AC "GFXMMU_LUT693H,GFXMMU LUT entry 693 high"
|
|
hexmask.long.tbyte 0x5AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5B0 "GFXMMU_LUT694L,GFXMMU LUT entry 694 low"
|
|
hexmask.long.byte 0x5B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5B4 "GFXMMU_LUT694H,GFXMMU LUT entry 694 high"
|
|
hexmask.long.tbyte 0x5B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5B8 "GFXMMU_LUT695L,GFXMMU LUT entry 695 low"
|
|
hexmask.long.byte 0x5B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5BC "GFXMMU_LUT695H,GFXMMU LUT entry 695 high"
|
|
hexmask.long.tbyte 0x5BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5C0 "GFXMMU_LUT696L,GFXMMU LUT entry 696 low"
|
|
hexmask.long.byte 0x5C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5C4 "GFXMMU_LUT696H,GFXMMU LUT entry 696 high"
|
|
hexmask.long.tbyte 0x5C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5C8 "GFXMMU_LUT697L,GFXMMU LUT entry 697 low"
|
|
hexmask.long.byte 0x5C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5CC "GFXMMU_LUT697H,GFXMMU LUT entry 697 high"
|
|
hexmask.long.tbyte 0x5CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5D0 "GFXMMU_LUT698L,GFXMMU LUT entry 698 low"
|
|
hexmask.long.byte 0x5D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5D4 "GFXMMU_LUT698H,GFXMMU LUT entry 698 high"
|
|
hexmask.long.tbyte 0x5D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5D8 "GFXMMU_LUT699L,GFXMMU LUT entry 699 low"
|
|
hexmask.long.byte 0x5D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5DC "GFXMMU_LUT699H,GFXMMU LUT entry 699 high"
|
|
hexmask.long.tbyte 0x5DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5E0 "GFXMMU_LUT700L,GFXMMU LUT entry 700 low"
|
|
hexmask.long.byte 0x5E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5E4 "GFXMMU_LUT700H,GFXMMU LUT entry 700 high"
|
|
hexmask.long.tbyte 0x5E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5E8 "GFXMMU_LUT701L,GFXMMU LUT entry 701 low"
|
|
hexmask.long.byte 0x5E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5EC "GFXMMU_LUT701H,GFXMMU LUT entry 701 high"
|
|
hexmask.long.tbyte 0x5EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5F0 "GFXMMU_LUT702L,GFXMMU LUT entry 702 low"
|
|
hexmask.long.byte 0x5F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5F4 "GFXMMU_LUT702H,GFXMMU LUT entry 702 high"
|
|
hexmask.long.tbyte 0x5F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x5F8 "GFXMMU_LUT703L,GFXMMU LUT entry 703 low"
|
|
hexmask.long.byte 0x5F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x5F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x5F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x5FC "GFXMMU_LUT703H,GFXMMU LUT entry 703 high"
|
|
hexmask.long.tbyte 0x5FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x600 "GFXMMU_LUT704L,GFXMMU LUT entry 704 low"
|
|
hexmask.long.byte 0x600 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x600 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x600 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x604 "GFXMMU_LUT704H,GFXMMU LUT entry 704 high"
|
|
hexmask.long.tbyte 0x604 0.--17. 1. "LO,Line offset"
|
|
line.long 0x608 "GFXMMU_LUT705L,GFXMMU LUT entry 705 low"
|
|
hexmask.long.byte 0x608 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x608 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x608 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x60C "GFXMMU_LUT705H,GFXMMU LUT entry 705 high"
|
|
hexmask.long.tbyte 0x60C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x610 "GFXMMU_LUT706L,GFXMMU LUT entry 706 low"
|
|
hexmask.long.byte 0x610 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x610 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x610 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x614 "GFXMMU_LUT706H,GFXMMU LUT entry 706 high"
|
|
hexmask.long.tbyte 0x614 0.--17. 1. "LO,Line offset"
|
|
line.long 0x618 "GFXMMU_LUT707L,GFXMMU LUT entry 707 low"
|
|
hexmask.long.byte 0x618 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x618 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x618 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x61C "GFXMMU_LUT707H,GFXMMU LUT entry 707 high"
|
|
hexmask.long.tbyte 0x61C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x620 "GFXMMU_LUT708L,GFXMMU LUT entry 708 low"
|
|
hexmask.long.byte 0x620 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x620 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x620 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x624 "GFXMMU_LUT708H,GFXMMU LUT entry 708 high"
|
|
hexmask.long.tbyte 0x624 0.--17. 1. "LO,Line offset"
|
|
line.long 0x628 "GFXMMU_LUT709L,GFXMMU LUT entry 709 low"
|
|
hexmask.long.byte 0x628 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x628 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x628 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x62C "GFXMMU_LUT709H,GFXMMU LUT entry 709 high"
|
|
hexmask.long.tbyte 0x62C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x630 "GFXMMU_LUT710L,GFXMMU LUT entry 710 low"
|
|
hexmask.long.byte 0x630 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x630 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x630 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x634 "GFXMMU_LUT710H,GFXMMU LUT entry 710 high"
|
|
hexmask.long.tbyte 0x634 0.--17. 1. "LO,Line offset"
|
|
line.long 0x638 "GFXMMU_LUT711L,GFXMMU LUT entry 711 low"
|
|
hexmask.long.byte 0x638 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x638 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x638 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x63C "GFXMMU_LUT711H,GFXMMU LUT entry 711 high"
|
|
hexmask.long.tbyte 0x63C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x640 "GFXMMU_LUT712L,GFXMMU LUT entry 712 low"
|
|
hexmask.long.byte 0x640 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x640 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x640 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x644 "GFXMMU_LUT712H,GFXMMU LUT entry 712 high"
|
|
hexmask.long.tbyte 0x644 0.--17. 1. "LO,Line offset"
|
|
line.long 0x648 "GFXMMU_LUT713L,GFXMMU LUT entry 713 low"
|
|
hexmask.long.byte 0x648 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x648 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x648 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x64C "GFXMMU_LUT713H,GFXMMU LUT entry 713 high"
|
|
hexmask.long.tbyte 0x64C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x650 "GFXMMU_LUT714L,GFXMMU LUT entry 714 low"
|
|
hexmask.long.byte 0x650 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x650 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x650 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x654 "GFXMMU_LUT714H,GFXMMU LUT entry 714 high"
|
|
hexmask.long.tbyte 0x654 0.--17. 1. "LO,Line offset"
|
|
line.long 0x658 "GFXMMU_LUT715L,GFXMMU LUT entry 715 low"
|
|
hexmask.long.byte 0x658 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x658 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x658 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x65C "GFXMMU_LUT715H,GFXMMU LUT entry 715 high"
|
|
hexmask.long.tbyte 0x65C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x660 "GFXMMU_LUT716L,GFXMMU LUT entry 716 low"
|
|
hexmask.long.byte 0x660 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x660 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x660 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x664 "GFXMMU_LUT716H,GFXMMU LUT entry 716 high"
|
|
hexmask.long.tbyte 0x664 0.--17. 1. "LO,Line offset"
|
|
line.long 0x668 "GFXMMU_LUT717L,GFXMMU LUT entry 717 low"
|
|
hexmask.long.byte 0x668 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x668 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x668 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x66C "GFXMMU_LUT717H,GFXMMU LUT entry 717 high"
|
|
hexmask.long.tbyte 0x66C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x670 "GFXMMU_LUT718L,GFXMMU LUT entry 718 low"
|
|
hexmask.long.byte 0x670 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x670 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x670 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x674 "GFXMMU_LUT718H,GFXMMU LUT entry 718 high"
|
|
hexmask.long.tbyte 0x674 0.--17. 1. "LO,Line offset"
|
|
line.long 0x678 "GFXMMU_LUT719L,GFXMMU LUT entry 719 low"
|
|
hexmask.long.byte 0x678 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x678 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x678 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x67C "GFXMMU_LUT719H,GFXMMU LUT entry 719 high"
|
|
hexmask.long.tbyte 0x67C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x680 "GFXMMU_LUT720L,GFXMMU LUT entry 720 low"
|
|
hexmask.long.byte 0x680 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x680 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x680 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x684 "GFXMMU_LUT720H,GFXMMU LUT entry 720 high"
|
|
hexmask.long.tbyte 0x684 0.--17. 1. "LO,Line offset"
|
|
line.long 0x688 "GFXMMU_LUT721L,GFXMMU LUT entry 721 low"
|
|
hexmask.long.byte 0x688 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x688 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x688 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x68C "GFXMMU_LUT721H,GFXMMU LUT entry 721 high"
|
|
hexmask.long.tbyte 0x68C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x690 "GFXMMU_LUT722L,GFXMMU LUT entry 722 low"
|
|
hexmask.long.byte 0x690 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x690 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x690 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x694 "GFXMMU_LUT722H,GFXMMU LUT entry 722 high"
|
|
hexmask.long.tbyte 0x694 0.--17. 1. "LO,Line offset"
|
|
line.long 0x698 "GFXMMU_LUT723L,GFXMMU LUT entry 723 low"
|
|
hexmask.long.byte 0x698 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x698 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x698 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x69C "GFXMMU_LUT723H,GFXMMU LUT entry 723 high"
|
|
hexmask.long.tbyte 0x69C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6A0 "GFXMMU_LUT724L,GFXMMU LUT entry 724 low"
|
|
hexmask.long.byte 0x6A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6A4 "GFXMMU_LUT724H,GFXMMU LUT entry 724 high"
|
|
hexmask.long.tbyte 0x6A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6A8 "GFXMMU_LUT725L,GFXMMU LUT entry 725 low"
|
|
hexmask.long.byte 0x6A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6AC "GFXMMU_LUT725H,GFXMMU LUT entry 725 high"
|
|
hexmask.long.tbyte 0x6AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6B0 "GFXMMU_LUT726L,GFXMMU LUT entry 726 low"
|
|
hexmask.long.byte 0x6B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6B4 "GFXMMU_LUT726H,GFXMMU LUT entry 726 high"
|
|
hexmask.long.tbyte 0x6B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6B8 "GFXMMU_LUT727L,GFXMMU LUT entry 727 low"
|
|
hexmask.long.byte 0x6B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6BC "GFXMMU_LUT727H,GFXMMU LUT entry 727 high"
|
|
hexmask.long.tbyte 0x6BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6C0 "GFXMMU_LUT728L,GFXMMU LUT entry 728 low"
|
|
hexmask.long.byte 0x6C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6C4 "GFXMMU_LUT728H,GFXMMU LUT entry 728 high"
|
|
hexmask.long.tbyte 0x6C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6C8 "GFXMMU_LUT729L,GFXMMU LUT entry 729 low"
|
|
hexmask.long.byte 0x6C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6CC "GFXMMU_LUT729H,GFXMMU LUT entry 729 high"
|
|
hexmask.long.tbyte 0x6CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6D0 "GFXMMU_LUT730L,GFXMMU LUT entry 730 low"
|
|
hexmask.long.byte 0x6D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6D4 "GFXMMU_LUT730H,GFXMMU LUT entry 730 high"
|
|
hexmask.long.tbyte 0x6D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6D8 "GFXMMU_LUT731L,GFXMMU LUT entry 731 low"
|
|
hexmask.long.byte 0x6D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6DC "GFXMMU_LUT731H,GFXMMU LUT entry 731 high"
|
|
hexmask.long.tbyte 0x6DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6E0 "GFXMMU_LUT732L,GFXMMU LUT entry 732 low"
|
|
hexmask.long.byte 0x6E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6E4 "GFXMMU_LUT732H,GFXMMU LUT entry 732 high"
|
|
hexmask.long.tbyte 0x6E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6E8 "GFXMMU_LUT733L,GFXMMU LUT entry 733 low"
|
|
hexmask.long.byte 0x6E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6EC "GFXMMU_LUT733H,GFXMMU LUT entry 733 high"
|
|
hexmask.long.tbyte 0x6EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6F0 "GFXMMU_LUT734L,GFXMMU LUT entry 734 low"
|
|
hexmask.long.byte 0x6F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6F4 "GFXMMU_LUT734H,GFXMMU LUT entry 734 high"
|
|
hexmask.long.tbyte 0x6F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x6F8 "GFXMMU_LUT735L,GFXMMU LUT entry 735 low"
|
|
hexmask.long.byte 0x6F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x6F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x6F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x6FC "GFXMMU_LUT735H,GFXMMU LUT entry 735 high"
|
|
hexmask.long.tbyte 0x6FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x700 "GFXMMU_LUT736L,GFXMMU LUT entry 736 low"
|
|
hexmask.long.byte 0x700 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x700 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x700 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x704 "GFXMMU_LUT736H,GFXMMU LUT entry 736 high"
|
|
hexmask.long.tbyte 0x704 0.--17. 1. "LO,Line offset"
|
|
line.long 0x708 "GFXMMU_LUT737L,GFXMMU LUT entry 737 low"
|
|
hexmask.long.byte 0x708 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x708 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x708 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x70C "GFXMMU_LUT737H,GFXMMU LUT entry 737 high"
|
|
hexmask.long.tbyte 0x70C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x710 "GFXMMU_LUT738L,GFXMMU LUT entry 738 low"
|
|
hexmask.long.byte 0x710 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x710 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x710 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x714 "GFXMMU_LUT738H,GFXMMU LUT entry 738 high"
|
|
hexmask.long.tbyte 0x714 0.--17. 1. "LO,Line offset"
|
|
line.long 0x718 "GFXMMU_LUT739L,GFXMMU LUT entry 739 low"
|
|
hexmask.long.byte 0x718 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x718 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x718 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x71C "GFXMMU_LUT739H,GFXMMU LUT entry 739 high"
|
|
hexmask.long.tbyte 0x71C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x720 "GFXMMU_LUT740L,GFXMMU LUT entry 740 low"
|
|
hexmask.long.byte 0x720 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x720 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x720 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x724 "GFXMMU_LUT740H,GFXMMU LUT entry 740 high"
|
|
hexmask.long.tbyte 0x724 0.--17. 1. "LO,Line offset"
|
|
line.long 0x728 "GFXMMU_LUT741L,GFXMMU LUT entry 741 low"
|
|
hexmask.long.byte 0x728 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x728 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x728 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x72C "GFXMMU_LUT741H,GFXMMU LUT entry 741 high"
|
|
hexmask.long.tbyte 0x72C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x730 "GFXMMU_LUT742L,GFXMMU LUT entry 742 low"
|
|
hexmask.long.byte 0x730 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x730 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x730 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x734 "GFXMMU_LUT742H,GFXMMU LUT entry 742 high"
|
|
hexmask.long.tbyte 0x734 0.--17. 1. "LO,Line offset"
|
|
line.long 0x738 "GFXMMU_LUT743L,GFXMMU LUT entry 743 low"
|
|
hexmask.long.byte 0x738 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x738 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x738 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x73C "GFXMMU_LUT743H,GFXMMU LUT entry 743 high"
|
|
hexmask.long.tbyte 0x73C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x740 "GFXMMU_LUT744L,GFXMMU LUT entry 744 low"
|
|
hexmask.long.byte 0x740 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x740 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x740 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x744 "GFXMMU_LUT744H,GFXMMU LUT entry 744 high"
|
|
hexmask.long.tbyte 0x744 0.--17. 1. "LO,Line offset"
|
|
line.long 0x748 "GFXMMU_LUT745L,GFXMMU LUT entry 745 low"
|
|
hexmask.long.byte 0x748 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x748 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x748 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x74C "GFXMMU_LUT745H,GFXMMU LUT entry 745 high"
|
|
hexmask.long.tbyte 0x74C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x750 "GFXMMU_LUT746L,GFXMMU LUT entry 746 low"
|
|
hexmask.long.byte 0x750 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x750 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x750 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x754 "GFXMMU_LUT746H,GFXMMU LUT entry 746 high"
|
|
hexmask.long.tbyte 0x754 0.--17. 1. "LO,Line offset"
|
|
line.long 0x758 "GFXMMU_LUT747L,GFXMMU LUT entry 747 low"
|
|
hexmask.long.byte 0x758 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x758 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x758 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x75C "GFXMMU_LUT747H,GFXMMU LUT entry 747 high"
|
|
hexmask.long.tbyte 0x75C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x760 "GFXMMU_LUT748L,GFXMMU LUT entry 748 low"
|
|
hexmask.long.byte 0x760 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x760 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x760 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x764 "GFXMMU_LUT748H,GFXMMU LUT entry 748 high"
|
|
hexmask.long.tbyte 0x764 0.--17. 1. "LO,Line offset"
|
|
line.long 0x768 "GFXMMU_LUT749L,GFXMMU LUT entry 749 low"
|
|
hexmask.long.byte 0x768 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x768 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x768 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x76C "GFXMMU_LUT749H,GFXMMU LUT entry 749 high"
|
|
hexmask.long.tbyte 0x76C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x770 "GFXMMU_LUT750L,GFXMMU LUT entry 750 low"
|
|
hexmask.long.byte 0x770 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x770 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x770 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x774 "GFXMMU_LUT750H,GFXMMU LUT entry 750 high"
|
|
hexmask.long.tbyte 0x774 0.--17. 1. "LO,Line offset"
|
|
line.long 0x778 "GFXMMU_LUT751L,GFXMMU LUT entry 751 low"
|
|
hexmask.long.byte 0x778 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x778 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x778 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x77C "GFXMMU_LUT751H,GFXMMU LUT entry 751 high"
|
|
hexmask.long.tbyte 0x77C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x780 "GFXMMU_LUT752L,GFXMMU LUT entry 752 low"
|
|
hexmask.long.byte 0x780 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x780 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x780 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x784 "GFXMMU_LUT752H,GFXMMU LUT entry 752 high"
|
|
hexmask.long.tbyte 0x784 0.--17. 1. "LO,Line offset"
|
|
line.long 0x788 "GFXMMU_LUT753L,GFXMMU LUT entry 753 low"
|
|
hexmask.long.byte 0x788 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x788 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x788 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x78C "GFXMMU_LUT753H,GFXMMU LUT entry 753 high"
|
|
hexmask.long.tbyte 0x78C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x790 "GFXMMU_LUT754L,GFXMMU LUT entry 754 low"
|
|
hexmask.long.byte 0x790 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x790 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x790 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x794 "GFXMMU_LUT754H,GFXMMU LUT entry 754 high"
|
|
hexmask.long.tbyte 0x794 0.--17. 1. "LO,Line offset"
|
|
line.long 0x798 "GFXMMU_LUT755L,GFXMMU LUT entry 755 low"
|
|
hexmask.long.byte 0x798 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x798 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x798 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x79C "GFXMMU_LUT755H,GFXMMU LUT entry 755 high"
|
|
hexmask.long.tbyte 0x79C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7A0 "GFXMMU_LUT756L,GFXMMU LUT entry 756 low"
|
|
hexmask.long.byte 0x7A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7A4 "GFXMMU_LUT756H,GFXMMU LUT entry 756 high"
|
|
hexmask.long.tbyte 0x7A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7A8 "GFXMMU_LUT757L,GFXMMU LUT entry 757 low"
|
|
hexmask.long.byte 0x7A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7AC "GFXMMU_LUT757H,GFXMMU LUT entry 757 high"
|
|
hexmask.long.tbyte 0x7AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7B0 "GFXMMU_LUT758L,GFXMMU LUT entry 758 low"
|
|
hexmask.long.byte 0x7B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7B4 "GFXMMU_LUT758H,GFXMMU LUT entry 758 high"
|
|
hexmask.long.tbyte 0x7B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7B8 "GFXMMU_LUT759L,GFXMMU LUT entry 759 low"
|
|
hexmask.long.byte 0x7B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7BC "GFXMMU_LUT759H,GFXMMU LUT entry 759 high"
|
|
hexmask.long.tbyte 0x7BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7C0 "GFXMMU_LUT760L,GFXMMU LUT entry 760 low"
|
|
hexmask.long.byte 0x7C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7C4 "GFXMMU_LUT760H,GFXMMU LUT entry 760 high"
|
|
hexmask.long.tbyte 0x7C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7C8 "GFXMMU_LUT761L,GFXMMU LUT entry 761 low"
|
|
hexmask.long.byte 0x7C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7CC "GFXMMU_LUT761H,GFXMMU LUT entry 761 high"
|
|
hexmask.long.tbyte 0x7CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7D0 "GFXMMU_LUT762L,GFXMMU LUT entry 762 low"
|
|
hexmask.long.byte 0x7D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7D4 "GFXMMU_LUT762H,GFXMMU LUT entry 762 high"
|
|
hexmask.long.tbyte 0x7D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7D8 "GFXMMU_LUT763L,GFXMMU LUT entry 763 low"
|
|
hexmask.long.byte 0x7D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7DC "GFXMMU_LUT763H,GFXMMU LUT entry 763 high"
|
|
hexmask.long.tbyte 0x7DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7E0 "GFXMMU_LUT764L,GFXMMU LUT entry 764 low"
|
|
hexmask.long.byte 0x7E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7E4 "GFXMMU_LUT764H,GFXMMU LUT entry 764 high"
|
|
hexmask.long.tbyte 0x7E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7E8 "GFXMMU_LUT765L,GFXMMU LUT entry 765 low"
|
|
hexmask.long.byte 0x7E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7EC "GFXMMU_LUT765H,GFXMMU LUT entry 765 high"
|
|
hexmask.long.tbyte 0x7EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7F0 "GFXMMU_LUT766L,GFXMMU LUT entry 766 low"
|
|
hexmask.long.byte 0x7F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7F4 "GFXMMU_LUT766H,GFXMMU LUT entry 766 high"
|
|
hexmask.long.tbyte 0x7F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x7F8 "GFXMMU_LUT767L,GFXMMU LUT entry 767 low"
|
|
hexmask.long.byte 0x7F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x7F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x7F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x7FC "GFXMMU_LUT767H,GFXMMU LUT entry 767 high"
|
|
hexmask.long.tbyte 0x7FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x800 "GFXMMU_LUT768L,GFXMMU LUT entry 768 low"
|
|
hexmask.long.byte 0x800 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x800 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x800 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x804 "GFXMMU_LUT768H,GFXMMU LUT entry 768 high"
|
|
hexmask.long.tbyte 0x804 0.--17. 1. "LO,Line offset"
|
|
line.long 0x808 "GFXMMU_LUT769L,GFXMMU LUT entry 769 low"
|
|
hexmask.long.byte 0x808 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x808 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x808 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x80C "GFXMMU_LUT769H,GFXMMU LUT entry 769 high"
|
|
hexmask.long.tbyte 0x80C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x810 "GFXMMU_LUT770L,GFXMMU LUT entry 770 low"
|
|
hexmask.long.byte 0x810 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x810 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x810 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x814 "GFXMMU_LUT770H,GFXMMU LUT entry 770 high"
|
|
hexmask.long.tbyte 0x814 0.--17. 1. "LO,Line offset"
|
|
line.long 0x818 "GFXMMU_LUT771L,GFXMMU LUT entry 771 low"
|
|
hexmask.long.byte 0x818 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x818 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x818 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x81C "GFXMMU_LUT771H,GFXMMU LUT entry 771 high"
|
|
hexmask.long.tbyte 0x81C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x820 "GFXMMU_LUT772L,GFXMMU LUT entry 772 low"
|
|
hexmask.long.byte 0x820 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x820 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x820 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x824 "GFXMMU_LUT772H,GFXMMU LUT entry 772 high"
|
|
hexmask.long.tbyte 0x824 0.--17. 1. "LO,Line offset"
|
|
line.long 0x828 "GFXMMU_LUT773L,GFXMMU LUT entry 773 low"
|
|
hexmask.long.byte 0x828 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x828 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x828 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x82C "GFXMMU_LUT773H,GFXMMU LUT entry 773 high"
|
|
hexmask.long.tbyte 0x82C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x830 "GFXMMU_LUT774L,GFXMMU LUT entry 774 low"
|
|
hexmask.long.byte 0x830 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x830 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x830 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x834 "GFXMMU_LUT774H,GFXMMU LUT entry 774 high"
|
|
hexmask.long.tbyte 0x834 0.--17. 1. "LO,Line offset"
|
|
line.long 0x838 "GFXMMU_LUT775L,GFXMMU LUT entry 775 low"
|
|
hexmask.long.byte 0x838 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x838 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x838 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x83C "GFXMMU_LUT775H,GFXMMU LUT entry 775 high"
|
|
hexmask.long.tbyte 0x83C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x840 "GFXMMU_LUT776L,GFXMMU LUT entry 776 low"
|
|
hexmask.long.byte 0x840 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x840 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x840 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x844 "GFXMMU_LUT776H,GFXMMU LUT entry 776 high"
|
|
hexmask.long.tbyte 0x844 0.--17. 1. "LO,Line offset"
|
|
line.long 0x848 "GFXMMU_LUT777L,GFXMMU LUT entry 777 low"
|
|
hexmask.long.byte 0x848 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x848 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x848 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x84C "GFXMMU_LUT777H,GFXMMU LUT entry 777 high"
|
|
hexmask.long.tbyte 0x84C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x850 "GFXMMU_LUT778L,GFXMMU LUT entry 778 low"
|
|
hexmask.long.byte 0x850 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x850 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x850 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x854 "GFXMMU_LUT778H,GFXMMU LUT entry 778 high"
|
|
hexmask.long.tbyte 0x854 0.--17. 1. "LO,Line offset"
|
|
line.long 0x858 "GFXMMU_LUT779L,GFXMMU LUT entry 779 low"
|
|
hexmask.long.byte 0x858 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x858 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x858 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x85C "GFXMMU_LUT779H,GFXMMU LUT entry 779 high"
|
|
hexmask.long.tbyte 0x85C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x860 "GFXMMU_LUT780L,GFXMMU LUT entry 780 low"
|
|
hexmask.long.byte 0x860 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x860 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x860 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x864 "GFXMMU_LUT780H,GFXMMU LUT entry 780 high"
|
|
hexmask.long.tbyte 0x864 0.--17. 1. "LO,Line offset"
|
|
line.long 0x868 "GFXMMU_LUT781L,GFXMMU LUT entry 781 low"
|
|
hexmask.long.byte 0x868 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x868 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x868 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x86C "GFXMMU_LUT781H,GFXMMU LUT entry 781 high"
|
|
hexmask.long.tbyte 0x86C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x870 "GFXMMU_LUT782L,GFXMMU LUT entry 782 low"
|
|
hexmask.long.byte 0x870 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x870 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x870 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x874 "GFXMMU_LUT782H,GFXMMU LUT entry 782 high"
|
|
hexmask.long.tbyte 0x874 0.--17. 1. "LO,Line offset"
|
|
line.long 0x878 "GFXMMU_LUT783L,GFXMMU LUT entry 783 low"
|
|
hexmask.long.byte 0x878 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x878 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x878 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x87C "GFXMMU_LUT783H,GFXMMU LUT entry 783 high"
|
|
hexmask.long.tbyte 0x87C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x880 "GFXMMU_LUT784L,GFXMMU LUT entry 784 low"
|
|
hexmask.long.byte 0x880 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x880 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x880 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x884 "GFXMMU_LUT784H,GFXMMU LUT entry 784 high"
|
|
hexmask.long.tbyte 0x884 0.--17. 1. "LO,Line offset"
|
|
line.long 0x888 "GFXMMU_LUT785L,GFXMMU LUT entry 785 low"
|
|
hexmask.long.byte 0x888 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x888 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x888 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x88C "GFXMMU_LUT785H,GFXMMU LUT entry 785 high"
|
|
hexmask.long.tbyte 0x88C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x890 "GFXMMU_LUT786L,GFXMMU LUT entry 786 low"
|
|
hexmask.long.byte 0x890 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x890 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x890 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x894 "GFXMMU_LUT786H,GFXMMU LUT entry 786 high"
|
|
hexmask.long.tbyte 0x894 0.--17. 1. "LO,Line offset"
|
|
line.long 0x898 "GFXMMU_LUT787L,GFXMMU LUT entry 787 low"
|
|
hexmask.long.byte 0x898 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x898 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x898 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x89C "GFXMMU_LUT787H,GFXMMU LUT entry 787 high"
|
|
hexmask.long.tbyte 0x89C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8A0 "GFXMMU_LUT788L,GFXMMU LUT entry 788 low"
|
|
hexmask.long.byte 0x8A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8A4 "GFXMMU_LUT788H,GFXMMU LUT entry 788 high"
|
|
hexmask.long.tbyte 0x8A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8A8 "GFXMMU_LUT789L,GFXMMU LUT entry 789 low"
|
|
hexmask.long.byte 0x8A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8AC "GFXMMU_LUT789H,GFXMMU LUT entry 789 high"
|
|
hexmask.long.tbyte 0x8AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8B0 "GFXMMU_LUT790L,GFXMMU LUT entry 790 low"
|
|
hexmask.long.byte 0x8B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8B4 "GFXMMU_LUT790H,GFXMMU LUT entry 790 high"
|
|
hexmask.long.tbyte 0x8B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8B8 "GFXMMU_LUT791L,GFXMMU LUT entry 791 low"
|
|
hexmask.long.byte 0x8B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8BC "GFXMMU_LUT791H,GFXMMU LUT entry 791 high"
|
|
hexmask.long.tbyte 0x8BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8C0 "GFXMMU_LUT792L,GFXMMU LUT entry 792 low"
|
|
hexmask.long.byte 0x8C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8C4 "GFXMMU_LUT792H,GFXMMU LUT entry 792 high"
|
|
hexmask.long.tbyte 0x8C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8C8 "GFXMMU_LUT793L,GFXMMU LUT entry 793 low"
|
|
hexmask.long.byte 0x8C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8CC "GFXMMU_LUT793H,GFXMMU LUT entry 793 high"
|
|
hexmask.long.tbyte 0x8CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8D0 "GFXMMU_LUT794L,GFXMMU LUT entry 794 low"
|
|
hexmask.long.byte 0x8D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8D4 "GFXMMU_LUT794H,GFXMMU LUT entry 794 high"
|
|
hexmask.long.tbyte 0x8D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8D8 "GFXMMU_LUT795L,GFXMMU LUT entry 795 low"
|
|
hexmask.long.byte 0x8D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8DC "GFXMMU_LUT795H,GFXMMU LUT entry 795 high"
|
|
hexmask.long.tbyte 0x8DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8E0 "GFXMMU_LUT796L,GFXMMU LUT entry 796 low"
|
|
hexmask.long.byte 0x8E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8E4 "GFXMMU_LUT796H,GFXMMU LUT entry 796 high"
|
|
hexmask.long.tbyte 0x8E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8E8 "GFXMMU_LUT797L,GFXMMU LUT entry 797 low"
|
|
hexmask.long.byte 0x8E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8EC "GFXMMU_LUT797H,GFXMMU LUT entry 797 high"
|
|
hexmask.long.tbyte 0x8EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8F0 "GFXMMU_LUT798L,GFXMMU LUT entry 798 low"
|
|
hexmask.long.byte 0x8F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8F4 "GFXMMU_LUT798H,GFXMMU LUT entry 798 high"
|
|
hexmask.long.tbyte 0x8F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x8F8 "GFXMMU_LUT799L,GFXMMU LUT entry 799 low"
|
|
hexmask.long.byte 0x8F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x8F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x8F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x8FC "GFXMMU_LUT799H,GFXMMU LUT entry 799 high"
|
|
hexmask.long.tbyte 0x8FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x900 "GFXMMU_LUT800L,GFXMMU LUT entry 800 low"
|
|
hexmask.long.byte 0x900 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x900 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x900 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x904 "GFXMMU_LUT800H,GFXMMU LUT entry 800 high"
|
|
hexmask.long.tbyte 0x904 0.--17. 1. "LO,Line offset"
|
|
line.long 0x908 "GFXMMU_LUT801L,GFXMMU LUT entry 801 low"
|
|
hexmask.long.byte 0x908 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x908 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x908 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x90C "GFXMMU_LUT801H,GFXMMU LUT entry 801 high"
|
|
hexmask.long.tbyte 0x90C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x910 "GFXMMU_LUT802L,GFXMMU LUT entry 802 low"
|
|
hexmask.long.byte 0x910 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x910 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x910 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x914 "GFXMMU_LUT802H,GFXMMU LUT entry 802 high"
|
|
hexmask.long.tbyte 0x914 0.--17. 1. "LO,Line offset"
|
|
line.long 0x918 "GFXMMU_LUT803L,GFXMMU LUT entry 803 low"
|
|
hexmask.long.byte 0x918 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x918 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x918 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x91C "GFXMMU_LUT803H,GFXMMU LUT entry 803 high"
|
|
hexmask.long.tbyte 0x91C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x920 "GFXMMU_LUT804L,GFXMMU LUT entry 804 low"
|
|
hexmask.long.byte 0x920 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x920 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x920 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x924 "GFXMMU_LUT804H,GFXMMU LUT entry 804 high"
|
|
hexmask.long.tbyte 0x924 0.--17. 1. "LO,Line offset"
|
|
line.long 0x928 "GFXMMU_LUT805L,GFXMMU LUT entry 805 low"
|
|
hexmask.long.byte 0x928 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x928 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x928 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x92C "GFXMMU_LUT805H,GFXMMU LUT entry 805 high"
|
|
hexmask.long.tbyte 0x92C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x930 "GFXMMU_LUT806L,GFXMMU LUT entry 806 low"
|
|
hexmask.long.byte 0x930 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x930 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x930 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x934 "GFXMMU_LUT806H,GFXMMU LUT entry 806 high"
|
|
hexmask.long.tbyte 0x934 0.--17. 1. "LO,Line offset"
|
|
line.long 0x938 "GFXMMU_LUT807L,GFXMMU LUT entry 807 low"
|
|
hexmask.long.byte 0x938 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x938 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x938 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x93C "GFXMMU_LUT807H,GFXMMU LUT entry 807 high"
|
|
hexmask.long.tbyte 0x93C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x940 "GFXMMU_LUT808L,GFXMMU LUT entry 808 low"
|
|
hexmask.long.byte 0x940 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x940 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x940 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x944 "GFXMMU_LUT808H,GFXMMU LUT entry 808 high"
|
|
hexmask.long.tbyte 0x944 0.--17. 1. "LO,Line offset"
|
|
line.long 0x948 "GFXMMU_LUT809L,GFXMMU LUT entry 809 low"
|
|
hexmask.long.byte 0x948 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x948 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x948 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x94C "GFXMMU_LUT809H,GFXMMU LUT entry 809 high"
|
|
hexmask.long.tbyte 0x94C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x950 "GFXMMU_LUT810L,GFXMMU LUT entry 810 low"
|
|
hexmask.long.byte 0x950 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x950 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x950 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x954 "GFXMMU_LUT810H,GFXMMU LUT entry 810 high"
|
|
hexmask.long.tbyte 0x954 0.--17. 1. "LO,Line offset"
|
|
line.long 0x958 "GFXMMU_LUT811L,GFXMMU LUT entry 811 low"
|
|
hexmask.long.byte 0x958 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x958 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x958 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x95C "GFXMMU_LUT811H,GFXMMU LUT entry 811 high"
|
|
hexmask.long.tbyte 0x95C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x960 "GFXMMU_LUT812L,GFXMMU LUT entry 812 low"
|
|
hexmask.long.byte 0x960 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x960 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x960 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x964 "GFXMMU_LUT812H,GFXMMU LUT entry 812 high"
|
|
hexmask.long.tbyte 0x964 0.--17. 1. "LO,Line offset"
|
|
line.long 0x968 "GFXMMU_LUT813L,GFXMMU LUT entry 813 low"
|
|
hexmask.long.byte 0x968 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x968 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x968 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x96C "GFXMMU_LUT813H,GFXMMU LUT entry 813 high"
|
|
hexmask.long.tbyte 0x96C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x970 "GFXMMU_LUT814L,GFXMMU LUT entry 814 low"
|
|
hexmask.long.byte 0x970 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x970 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x970 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x974 "GFXMMU_LUT814H,GFXMMU LUT entry 814 high"
|
|
hexmask.long.tbyte 0x974 0.--17. 1. "LO,Line offset"
|
|
line.long 0x978 "GFXMMU_LUT815L,GFXMMU LUT entry 815 low"
|
|
hexmask.long.byte 0x978 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x978 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x978 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x97C "GFXMMU_LUT815H,GFXMMU LUT entry 815 high"
|
|
hexmask.long.tbyte 0x97C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x980 "GFXMMU_LUT816L,GFXMMU LUT entry 816 low"
|
|
hexmask.long.byte 0x980 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x980 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x980 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x984 "GFXMMU_LUT816H,GFXMMU LUT entry 816 high"
|
|
hexmask.long.tbyte 0x984 0.--17. 1. "LO,Line offset"
|
|
line.long 0x988 "GFXMMU_LUT817L,GFXMMU LUT entry 817 low"
|
|
hexmask.long.byte 0x988 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x988 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x988 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x98C "GFXMMU_LUT817H,GFXMMU LUT entry 817 high"
|
|
hexmask.long.tbyte 0x98C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x990 "GFXMMU_LUT818L,GFXMMU LUT entry 818 low"
|
|
hexmask.long.byte 0x990 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x990 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x990 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x994 "GFXMMU_LUT818H,GFXMMU LUT entry 818 high"
|
|
hexmask.long.tbyte 0x994 0.--17. 1. "LO,Line offset"
|
|
line.long 0x998 "GFXMMU_LUT819L,GFXMMU LUT entry 819 low"
|
|
hexmask.long.byte 0x998 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x998 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x998 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x99C "GFXMMU_LUT819H,GFXMMU LUT entry 819 high"
|
|
hexmask.long.tbyte 0x99C 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9A0 "GFXMMU_LUT820L,GFXMMU LUT entry 820 low"
|
|
hexmask.long.byte 0x9A0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9A0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9A0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9A4 "GFXMMU_LUT820H,GFXMMU LUT entry 820 high"
|
|
hexmask.long.tbyte 0x9A4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9A8 "GFXMMU_LUT821L,GFXMMU LUT entry 821 low"
|
|
hexmask.long.byte 0x9A8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9A8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9A8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9AC "GFXMMU_LUT821H,GFXMMU LUT entry 821 high"
|
|
hexmask.long.tbyte 0x9AC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9B0 "GFXMMU_LUT822L,GFXMMU LUT entry 822 low"
|
|
hexmask.long.byte 0x9B0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9B0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9B0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9B4 "GFXMMU_LUT822H,GFXMMU LUT entry 822 high"
|
|
hexmask.long.tbyte 0x9B4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9B8 "GFXMMU_LUT823L,GFXMMU LUT entry 823 low"
|
|
hexmask.long.byte 0x9B8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9B8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9B8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9BC "GFXMMU_LUT823H,GFXMMU LUT entry 823 high"
|
|
hexmask.long.tbyte 0x9BC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9C0 "GFXMMU_LUT824L,GFXMMU LUT entry 824 low"
|
|
hexmask.long.byte 0x9C0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9C0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9C0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9C4 "GFXMMU_LUT824H,GFXMMU LUT entry 824 high"
|
|
hexmask.long.tbyte 0x9C4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9C8 "GFXMMU_LUT825L,GFXMMU LUT entry 825 low"
|
|
hexmask.long.byte 0x9C8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9C8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9C8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9CC "GFXMMU_LUT825H,GFXMMU LUT entry 825 high"
|
|
hexmask.long.tbyte 0x9CC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9D0 "GFXMMU_LUT826L,GFXMMU LUT entry 826 low"
|
|
hexmask.long.byte 0x9D0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9D0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9D0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9D4 "GFXMMU_LUT826H,GFXMMU LUT entry 826 high"
|
|
hexmask.long.tbyte 0x9D4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9D8 "GFXMMU_LUT827L,GFXMMU LUT entry 827 low"
|
|
hexmask.long.byte 0x9D8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9D8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9D8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9DC "GFXMMU_LUT827H,GFXMMU LUT entry 827 high"
|
|
hexmask.long.tbyte 0x9DC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9E0 "GFXMMU_LUT828L,GFXMMU LUT entry 828 low"
|
|
hexmask.long.byte 0x9E0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9E0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9E0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9E4 "GFXMMU_LUT828H,GFXMMU LUT entry 828 high"
|
|
hexmask.long.tbyte 0x9E4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9E8 "GFXMMU_LUT829L,GFXMMU LUT entry 829 low"
|
|
hexmask.long.byte 0x9E8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9E8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9E8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9EC "GFXMMU_LUT829H,GFXMMU LUT entry 829 high"
|
|
hexmask.long.tbyte 0x9EC 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9F0 "GFXMMU_LUT830L,GFXMMU LUT entry 830 low"
|
|
hexmask.long.byte 0x9F0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9F0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9F0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9F4 "GFXMMU_LUT830H,GFXMMU LUT entry 830 high"
|
|
hexmask.long.tbyte 0x9F4 0.--17. 1. "LO,Line offset"
|
|
line.long 0x9F8 "GFXMMU_LUT831L,GFXMMU LUT entry 831 low"
|
|
hexmask.long.byte 0x9F8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0x9F8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0x9F8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0x9FC "GFXMMU_LUT831H,GFXMMU LUT entry 831 high"
|
|
hexmask.long.tbyte 0x9FC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA00 "GFXMMU_LUT832L,GFXMMU LUT entry 832 low"
|
|
hexmask.long.byte 0xA00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA04 "GFXMMU_LUT832H,GFXMMU LUT entry 832 high"
|
|
hexmask.long.tbyte 0xA04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA08 "GFXMMU_LUT833L,GFXMMU LUT entry 833 low"
|
|
hexmask.long.byte 0xA08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA0C "GFXMMU_LUT833H,GFXMMU LUT entry 833 high"
|
|
hexmask.long.tbyte 0xA0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA10 "GFXMMU_LUT834L,GFXMMU LUT entry 834 low"
|
|
hexmask.long.byte 0xA10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA14 "GFXMMU_LUT834H,GFXMMU LUT entry 834 high"
|
|
hexmask.long.tbyte 0xA14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA18 "GFXMMU_LUT835L,GFXMMU LUT entry 835 low"
|
|
hexmask.long.byte 0xA18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA1C "GFXMMU_LUT835H,GFXMMU LUT entry 835 high"
|
|
hexmask.long.tbyte 0xA1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA20 "GFXMMU_LUT836L,GFXMMU LUT entry 836 low"
|
|
hexmask.long.byte 0xA20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA24 "GFXMMU_LUT836H,GFXMMU LUT entry 836 high"
|
|
hexmask.long.tbyte 0xA24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA28 "GFXMMU_LUT837L,GFXMMU LUT entry 837 low"
|
|
hexmask.long.byte 0xA28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA2C "GFXMMU_LUT837H,GFXMMU LUT entry 837 high"
|
|
hexmask.long.tbyte 0xA2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA30 "GFXMMU_LUT838L,GFXMMU LUT entry 838 low"
|
|
hexmask.long.byte 0xA30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA34 "GFXMMU_LUT838H,GFXMMU LUT entry 838 high"
|
|
hexmask.long.tbyte 0xA34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA38 "GFXMMU_LUT839L,GFXMMU LUT entry 839 low"
|
|
hexmask.long.byte 0xA38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA3C "GFXMMU_LUT839H,GFXMMU LUT entry 839 high"
|
|
hexmask.long.tbyte 0xA3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA40 "GFXMMU_LUT840L,GFXMMU LUT entry 840 low"
|
|
hexmask.long.byte 0xA40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA44 "GFXMMU_LUT840H,GFXMMU LUT entry 840 high"
|
|
hexmask.long.tbyte 0xA44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA48 "GFXMMU_LUT841L,GFXMMU LUT entry 841 low"
|
|
hexmask.long.byte 0xA48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA4C "GFXMMU_LUT841H,GFXMMU LUT entry 841 high"
|
|
hexmask.long.tbyte 0xA4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA50 "GFXMMU_LUT842L,GFXMMU LUT entry 842 low"
|
|
hexmask.long.byte 0xA50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA54 "GFXMMU_LUT842H,GFXMMU LUT entry 842 high"
|
|
hexmask.long.tbyte 0xA54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA58 "GFXMMU_LUT843L,GFXMMU LUT entry 843 low"
|
|
hexmask.long.byte 0xA58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA5C "GFXMMU_LUT843H,GFXMMU LUT entry 843 high"
|
|
hexmask.long.tbyte 0xA5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA60 "GFXMMU_LUT844L,GFXMMU LUT entry 844 low"
|
|
hexmask.long.byte 0xA60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA64 "GFXMMU_LUT844H,GFXMMU LUT entry 844 high"
|
|
hexmask.long.tbyte 0xA64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA68 "GFXMMU_LUT845L,GFXMMU LUT entry 845 low"
|
|
hexmask.long.byte 0xA68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA6C "GFXMMU_LUT845H,GFXMMU LUT entry 845 high"
|
|
hexmask.long.tbyte 0xA6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA70 "GFXMMU_LUT846L,GFXMMU LUT entry 846 low"
|
|
hexmask.long.byte 0xA70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA74 "GFXMMU_LUT846H,GFXMMU LUT entry 846 high"
|
|
hexmask.long.tbyte 0xA74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA78 "GFXMMU_LUT847L,GFXMMU LUT entry 847 low"
|
|
hexmask.long.byte 0xA78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA7C "GFXMMU_LUT847H,GFXMMU LUT entry 847 high"
|
|
hexmask.long.tbyte 0xA7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA80 "GFXMMU_LUT848L,GFXMMU LUT entry 848 low"
|
|
hexmask.long.byte 0xA80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA84 "GFXMMU_LUT848H,GFXMMU LUT entry 848 high"
|
|
hexmask.long.tbyte 0xA84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA88 "GFXMMU_LUT849L,GFXMMU LUT entry 849 low"
|
|
hexmask.long.byte 0xA88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA8C "GFXMMU_LUT849H,GFXMMU LUT entry 849 high"
|
|
hexmask.long.tbyte 0xA8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA90 "GFXMMU_LUT850L,GFXMMU LUT entry 850 low"
|
|
hexmask.long.byte 0xA90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA94 "GFXMMU_LUT850H,GFXMMU LUT entry 850 high"
|
|
hexmask.long.tbyte 0xA94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xA98 "GFXMMU_LUT851L,GFXMMU LUT entry 851 low"
|
|
hexmask.long.byte 0xA98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xA98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xA98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xA9C "GFXMMU_LUT851H,GFXMMU LUT entry 851 high"
|
|
hexmask.long.tbyte 0xA9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAA0 "GFXMMU_LUT852L,GFXMMU LUT entry 852 low"
|
|
hexmask.long.byte 0xAA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAA4 "GFXMMU_LUT852H,GFXMMU LUT entry 852 high"
|
|
hexmask.long.tbyte 0xAA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAA8 "GFXMMU_LUT853L,GFXMMU LUT entry 853 low"
|
|
hexmask.long.byte 0xAA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAAC "GFXMMU_LUT853H,GFXMMU LUT entry 853 high"
|
|
hexmask.long.tbyte 0xAAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAB0 "GFXMMU_LUT854L,GFXMMU LUT entry 854 low"
|
|
hexmask.long.byte 0xAB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAB4 "GFXMMU_LUT854H,GFXMMU LUT entry 854 high"
|
|
hexmask.long.tbyte 0xAB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAB8 "GFXMMU_LUT855L,GFXMMU LUT entry 855 low"
|
|
hexmask.long.byte 0xAB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xABC "GFXMMU_LUT855H,GFXMMU LUT entry 855 high"
|
|
hexmask.long.tbyte 0xABC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAC0 "GFXMMU_LUT856L,GFXMMU LUT entry 856 low"
|
|
hexmask.long.byte 0xAC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAC4 "GFXMMU_LUT856H,GFXMMU LUT entry 856 high"
|
|
hexmask.long.tbyte 0xAC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAC8 "GFXMMU_LUT857L,GFXMMU LUT entry 857 low"
|
|
hexmask.long.byte 0xAC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xACC "GFXMMU_LUT857H,GFXMMU LUT entry 857 high"
|
|
hexmask.long.tbyte 0xACC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAD0 "GFXMMU_LUT858L,GFXMMU LUT entry 858 low"
|
|
hexmask.long.byte 0xAD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAD4 "GFXMMU_LUT858H,GFXMMU LUT entry 858 high"
|
|
hexmask.long.tbyte 0xAD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAD8 "GFXMMU_LUT859L,GFXMMU LUT entry 859 low"
|
|
hexmask.long.byte 0xAD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xADC "GFXMMU_LUT859H,GFXMMU LUT entry 859 high"
|
|
hexmask.long.tbyte 0xADC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAE0 "GFXMMU_LUT860L,GFXMMU LUT entry 860 low"
|
|
hexmask.long.byte 0xAE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAE4 "GFXMMU_LUT860H,GFXMMU LUT entry 860 high"
|
|
hexmask.long.tbyte 0xAE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAE8 "GFXMMU_LUT861L,GFXMMU LUT entry 861 low"
|
|
hexmask.long.byte 0xAE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAEC "GFXMMU_LUT861H,GFXMMU LUT entry 861 high"
|
|
hexmask.long.tbyte 0xAEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAF0 "GFXMMU_LUT862L,GFXMMU LUT entry 862 low"
|
|
hexmask.long.byte 0xAF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAF4 "GFXMMU_LUT862H,GFXMMU LUT entry 862 high"
|
|
hexmask.long.tbyte 0xAF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xAF8 "GFXMMU_LUT863L,GFXMMU LUT entry 863 low"
|
|
hexmask.long.byte 0xAF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xAF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xAF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xAFC "GFXMMU_LUT863H,GFXMMU LUT entry 863 high"
|
|
hexmask.long.tbyte 0xAFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB00 "GFXMMU_LUT864L,GFXMMU LUT entry 864 low"
|
|
hexmask.long.byte 0xB00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB04 "GFXMMU_LUT864H,GFXMMU LUT entry 864 high"
|
|
hexmask.long.tbyte 0xB04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB08 "GFXMMU_LUT865L,GFXMMU LUT entry 865 low"
|
|
hexmask.long.byte 0xB08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB0C "GFXMMU_LUT865H,GFXMMU LUT entry 865 high"
|
|
hexmask.long.tbyte 0xB0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB10 "GFXMMU_LUT866L,GFXMMU LUT entry 866 low"
|
|
hexmask.long.byte 0xB10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB14 "GFXMMU_LUT866H,GFXMMU LUT entry 866 high"
|
|
hexmask.long.tbyte 0xB14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB18 "GFXMMU_LUT867L,GFXMMU LUT entry 867 low"
|
|
hexmask.long.byte 0xB18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB1C "GFXMMU_LUT867H,GFXMMU LUT entry 867 high"
|
|
hexmask.long.tbyte 0xB1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB20 "GFXMMU_LUT868L,GFXMMU LUT entry 868 low"
|
|
hexmask.long.byte 0xB20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB24 "GFXMMU_LUT868H,GFXMMU LUT entry 868 high"
|
|
hexmask.long.tbyte 0xB24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB28 "GFXMMU_LUT869L,GFXMMU LUT entry 869 low"
|
|
hexmask.long.byte 0xB28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB2C "GFXMMU_LUT869H,GFXMMU LUT entry 869 high"
|
|
hexmask.long.tbyte 0xB2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB30 "GFXMMU_LUT870L,GFXMMU LUT entry 870 low"
|
|
hexmask.long.byte 0xB30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB34 "GFXMMU_LUT870H,GFXMMU LUT entry 870 high"
|
|
hexmask.long.tbyte 0xB34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB38 "GFXMMU_LUT871L,GFXMMU LUT entry 871 low"
|
|
hexmask.long.byte 0xB38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB3C "GFXMMU_LUT871H,GFXMMU LUT entry 871 high"
|
|
hexmask.long.tbyte 0xB3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB40 "GFXMMU_LUT872L,GFXMMU LUT entry 872 low"
|
|
hexmask.long.byte 0xB40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB44 "GFXMMU_LUT872H,GFXMMU LUT entry 872 high"
|
|
hexmask.long.tbyte 0xB44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB48 "GFXMMU_LUT873L,GFXMMU LUT entry 873 low"
|
|
hexmask.long.byte 0xB48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB4C "GFXMMU_LUT873H,GFXMMU LUT entry 873 high"
|
|
hexmask.long.tbyte 0xB4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB50 "GFXMMU_LUT874L,GFXMMU LUT entry 874 low"
|
|
hexmask.long.byte 0xB50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB54 "GFXMMU_LUT874H,GFXMMU LUT entry 874 high"
|
|
hexmask.long.tbyte 0xB54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB58 "GFXMMU_LUT875L,GFXMMU LUT entry 875 low"
|
|
hexmask.long.byte 0xB58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB5C "GFXMMU_LUT875H,GFXMMU LUT entry 875 high"
|
|
hexmask.long.tbyte 0xB5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB60 "GFXMMU_LUT876L,GFXMMU LUT entry 876 low"
|
|
hexmask.long.byte 0xB60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB64 "GFXMMU_LUT876H,GFXMMU LUT entry 876 high"
|
|
hexmask.long.tbyte 0xB64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB68 "GFXMMU_LUT877L,GFXMMU LUT entry 877 low"
|
|
hexmask.long.byte 0xB68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB6C "GFXMMU_LUT877H,GFXMMU LUT entry 877 high"
|
|
hexmask.long.tbyte 0xB6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB70 "GFXMMU_LUT878L,GFXMMU LUT entry 878 low"
|
|
hexmask.long.byte 0xB70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB74 "GFXMMU_LUT878H,GFXMMU LUT entry 878 high"
|
|
hexmask.long.tbyte 0xB74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB78 "GFXMMU_LUT879L,GFXMMU LUT entry 879 low"
|
|
hexmask.long.byte 0xB78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB7C "GFXMMU_LUT879H,GFXMMU LUT entry 879 high"
|
|
hexmask.long.tbyte 0xB7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB80 "GFXMMU_LUT880L,GFXMMU LUT entry 880 low"
|
|
hexmask.long.byte 0xB80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB84 "GFXMMU_LUT880H,GFXMMU LUT entry 880 high"
|
|
hexmask.long.tbyte 0xB84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB88 "GFXMMU_LUT881L,GFXMMU LUT entry 881 low"
|
|
hexmask.long.byte 0xB88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB8C "GFXMMU_LUT881H,GFXMMU LUT entry 881 high"
|
|
hexmask.long.tbyte 0xB8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB90 "GFXMMU_LUT882L,GFXMMU LUT entry 882 low"
|
|
hexmask.long.byte 0xB90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB94 "GFXMMU_LUT882H,GFXMMU LUT entry 882 high"
|
|
hexmask.long.tbyte 0xB94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xB98 "GFXMMU_LUT883L,GFXMMU LUT entry 883 low"
|
|
hexmask.long.byte 0xB98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xB98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xB98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xB9C "GFXMMU_LUT883H,GFXMMU LUT entry 883 high"
|
|
hexmask.long.tbyte 0xB9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBA0 "GFXMMU_LUT884L,GFXMMU LUT entry 884 low"
|
|
hexmask.long.byte 0xBA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBA4 "GFXMMU_LUT884H,GFXMMU LUT entry 884 high"
|
|
hexmask.long.tbyte 0xBA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBA8 "GFXMMU_LUT885L,GFXMMU LUT entry 885 low"
|
|
hexmask.long.byte 0xBA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBAC "GFXMMU_LUT885H,GFXMMU LUT entry 885 high"
|
|
hexmask.long.tbyte 0xBAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBB0 "GFXMMU_LUT886L,GFXMMU LUT entry 886 low"
|
|
hexmask.long.byte 0xBB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBB4 "GFXMMU_LUT886H,GFXMMU LUT entry 886 high"
|
|
hexmask.long.tbyte 0xBB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBB8 "GFXMMU_LUT887L,GFXMMU LUT entry 887 low"
|
|
hexmask.long.byte 0xBB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBBC "GFXMMU_LUT887H,GFXMMU LUT entry 887 high"
|
|
hexmask.long.tbyte 0xBBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBC0 "GFXMMU_LUT888L,GFXMMU LUT entry 888 low"
|
|
hexmask.long.byte 0xBC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBC4 "GFXMMU_LUT888H,GFXMMU LUT entry 888 high"
|
|
hexmask.long.tbyte 0xBC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBC8 "GFXMMU_LUT889L,GFXMMU LUT entry 889 low"
|
|
hexmask.long.byte 0xBC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBCC "GFXMMU_LUT889H,GFXMMU LUT entry 889 high"
|
|
hexmask.long.tbyte 0xBCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBD0 "GFXMMU_LUT890L,GFXMMU LUT entry 890 low"
|
|
hexmask.long.byte 0xBD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBD4 "GFXMMU_LUT890H,GFXMMU LUT entry 890 high"
|
|
hexmask.long.tbyte 0xBD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBD8 "GFXMMU_LUT891L,GFXMMU LUT entry 891 low"
|
|
hexmask.long.byte 0xBD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBDC "GFXMMU_LUT891H,GFXMMU LUT entry 891 high"
|
|
hexmask.long.tbyte 0xBDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBE0 "GFXMMU_LUT892L,GFXMMU LUT entry 892 low"
|
|
hexmask.long.byte 0xBE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBE4 "GFXMMU_LUT892H,GFXMMU LUT entry 892 high"
|
|
hexmask.long.tbyte 0xBE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBE8 "GFXMMU_LUT893L,GFXMMU LUT entry 893 low"
|
|
hexmask.long.byte 0xBE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBEC "GFXMMU_LUT893H,GFXMMU LUT entry 893 high"
|
|
hexmask.long.tbyte 0xBEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBF0 "GFXMMU_LUT894L,GFXMMU LUT entry 894 low"
|
|
hexmask.long.byte 0xBF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBF4 "GFXMMU_LUT894H,GFXMMU LUT entry 894 high"
|
|
hexmask.long.tbyte 0xBF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xBF8 "GFXMMU_LUT895L,GFXMMU LUT entry 895 low"
|
|
hexmask.long.byte 0xBF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xBF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xBF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xBFC "GFXMMU_LUT895H,GFXMMU LUT entry 895 high"
|
|
hexmask.long.tbyte 0xBFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC00 "GFXMMU_LUT896L,GFXMMU LUT entry 896 low"
|
|
hexmask.long.byte 0xC00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC04 "GFXMMU_LUT896H,GFXMMU LUT entry 896 high"
|
|
hexmask.long.tbyte 0xC04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC08 "GFXMMU_LUT897L,GFXMMU LUT entry 897 low"
|
|
hexmask.long.byte 0xC08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC0C "GFXMMU_LUT897H,GFXMMU LUT entry 897 high"
|
|
hexmask.long.tbyte 0xC0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC10 "GFXMMU_LUT898L,GFXMMU LUT entry 898 low"
|
|
hexmask.long.byte 0xC10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC14 "GFXMMU_LUT898H,GFXMMU LUT entry 898 high"
|
|
hexmask.long.tbyte 0xC14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC18 "GFXMMU_LUT899L,GFXMMU LUT entry 899 low"
|
|
hexmask.long.byte 0xC18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC1C "GFXMMU_LUT899H,GFXMMU LUT entry 899 high"
|
|
hexmask.long.tbyte 0xC1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC20 "GFXMMU_LUT900L,GFXMMU LUT entry 900 low"
|
|
hexmask.long.byte 0xC20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC24 "GFXMMU_LUT900H,GFXMMU LUT entry 900 high"
|
|
hexmask.long.tbyte 0xC24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC28 "GFXMMU_LUT901L,GFXMMU LUT entry 901 low"
|
|
hexmask.long.byte 0xC28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC2C "GFXMMU_LUT901H,GFXMMU LUT entry 901 high"
|
|
hexmask.long.tbyte 0xC2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC30 "GFXMMU_LUT902L,GFXMMU LUT entry 902 low"
|
|
hexmask.long.byte 0xC30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC34 "GFXMMU_LUT902H,GFXMMU LUT entry 902 high"
|
|
hexmask.long.tbyte 0xC34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC38 "GFXMMU_LUT903L,GFXMMU LUT entry 903 low"
|
|
hexmask.long.byte 0xC38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC3C "GFXMMU_LUT903H,GFXMMU LUT entry 903 high"
|
|
hexmask.long.tbyte 0xC3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC40 "GFXMMU_LUT904L,GFXMMU LUT entry 904 low"
|
|
hexmask.long.byte 0xC40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC44 "GFXMMU_LUT904H,GFXMMU LUT entry 904 high"
|
|
hexmask.long.tbyte 0xC44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC48 "GFXMMU_LUT905L,GFXMMU LUT entry 905 low"
|
|
hexmask.long.byte 0xC48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC4C "GFXMMU_LUT905H,GFXMMU LUT entry 905 high"
|
|
hexmask.long.tbyte 0xC4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC50 "GFXMMU_LUT906L,GFXMMU LUT entry 906 low"
|
|
hexmask.long.byte 0xC50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC54 "GFXMMU_LUT906H,GFXMMU LUT entry 906 high"
|
|
hexmask.long.tbyte 0xC54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC58 "GFXMMU_LUT907L,GFXMMU LUT entry 907 low"
|
|
hexmask.long.byte 0xC58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC5C "GFXMMU_LUT907H,GFXMMU LUT entry 907 high"
|
|
hexmask.long.tbyte 0xC5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC60 "GFXMMU_LUT908L,GFXMMU LUT entry 908 low"
|
|
hexmask.long.byte 0xC60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC64 "GFXMMU_LUT908H,GFXMMU LUT entry 908 high"
|
|
hexmask.long.tbyte 0xC64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC68 "GFXMMU_LUT909L,GFXMMU LUT entry 909 low"
|
|
hexmask.long.byte 0xC68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC6C "GFXMMU_LUT909H,GFXMMU LUT entry 909 high"
|
|
hexmask.long.tbyte 0xC6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC70 "GFXMMU_LUT910L,GFXMMU LUT entry 910 low"
|
|
hexmask.long.byte 0xC70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC74 "GFXMMU_LUT910H,GFXMMU LUT entry 910 high"
|
|
hexmask.long.tbyte 0xC74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC78 "GFXMMU_LUT911L,GFXMMU LUT entry 911 low"
|
|
hexmask.long.byte 0xC78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC7C "GFXMMU_LUT911H,GFXMMU LUT entry 911 high"
|
|
hexmask.long.tbyte 0xC7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC80 "GFXMMU_LUT912L,GFXMMU LUT entry 912 low"
|
|
hexmask.long.byte 0xC80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC84 "GFXMMU_LUT912H,GFXMMU LUT entry 912 high"
|
|
hexmask.long.tbyte 0xC84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC88 "GFXMMU_LUT913L,GFXMMU LUT entry 913 low"
|
|
hexmask.long.byte 0xC88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC8C "GFXMMU_LUT913H,GFXMMU LUT entry 913 high"
|
|
hexmask.long.tbyte 0xC8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC90 "GFXMMU_LUT914L,GFXMMU LUT entry 914 low"
|
|
hexmask.long.byte 0xC90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC94 "GFXMMU_LUT914H,GFXMMU LUT entry 914 high"
|
|
hexmask.long.tbyte 0xC94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xC98 "GFXMMU_LUT915L,GFXMMU LUT entry 915 low"
|
|
hexmask.long.byte 0xC98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xC98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xC98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xC9C "GFXMMU_LUT915H,GFXMMU LUT entry 915 high"
|
|
hexmask.long.tbyte 0xC9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCA0 "GFXMMU_LUT916L,GFXMMU LUT entry 916 low"
|
|
hexmask.long.byte 0xCA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCA4 "GFXMMU_LUT916H,GFXMMU LUT entry 916 high"
|
|
hexmask.long.tbyte 0xCA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCA8 "GFXMMU_LUT917L,GFXMMU LUT entry 917 low"
|
|
hexmask.long.byte 0xCA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCAC "GFXMMU_LUT917H,GFXMMU LUT entry 917 high"
|
|
hexmask.long.tbyte 0xCAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCB0 "GFXMMU_LUT918L,GFXMMU LUT entry 918 low"
|
|
hexmask.long.byte 0xCB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCB4 "GFXMMU_LUT918H,GFXMMU LUT entry 918 high"
|
|
hexmask.long.tbyte 0xCB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCB8 "GFXMMU_LUT919L,GFXMMU LUT entry 919 low"
|
|
hexmask.long.byte 0xCB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCBC "GFXMMU_LUT919H,GFXMMU LUT entry 919 high"
|
|
hexmask.long.tbyte 0xCBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCC0 "GFXMMU_LUT920L,GFXMMU LUT entry 920 low"
|
|
hexmask.long.byte 0xCC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCC4 "GFXMMU_LUT920H,GFXMMU LUT entry 920 high"
|
|
hexmask.long.tbyte 0xCC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCC8 "GFXMMU_LUT921L,GFXMMU LUT entry 921 low"
|
|
hexmask.long.byte 0xCC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCCC "GFXMMU_LUT921H,GFXMMU LUT entry 921 high"
|
|
hexmask.long.tbyte 0xCCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCD0 "GFXMMU_LUT922L,GFXMMU LUT entry 922 low"
|
|
hexmask.long.byte 0xCD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCD4 "GFXMMU_LUT922H,GFXMMU LUT entry 922 high"
|
|
hexmask.long.tbyte 0xCD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCD8 "GFXMMU_LUT923L,GFXMMU LUT entry 923 low"
|
|
hexmask.long.byte 0xCD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCDC "GFXMMU_LUT923H,GFXMMU LUT entry 923 high"
|
|
hexmask.long.tbyte 0xCDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCE0 "GFXMMU_LUT924L,GFXMMU LUT entry 924 low"
|
|
hexmask.long.byte 0xCE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCE4 "GFXMMU_LUT924H,GFXMMU LUT entry 924 high"
|
|
hexmask.long.tbyte 0xCE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCE8 "GFXMMU_LUT925L,GFXMMU LUT entry 925 low"
|
|
hexmask.long.byte 0xCE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCEC "GFXMMU_LUT925H,GFXMMU LUT entry 925 high"
|
|
hexmask.long.tbyte 0xCEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCF0 "GFXMMU_LUT926L,GFXMMU LUT entry 926 low"
|
|
hexmask.long.byte 0xCF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCF4 "GFXMMU_LUT926H,GFXMMU LUT entry 926 high"
|
|
hexmask.long.tbyte 0xCF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xCF8 "GFXMMU_LUT927L,GFXMMU LUT entry 927 low"
|
|
hexmask.long.byte 0xCF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xCF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xCF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xCFC "GFXMMU_LUT927H,GFXMMU LUT entry 927 high"
|
|
hexmask.long.tbyte 0xCFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD00 "GFXMMU_LUT928L,GFXMMU LUT entry 928 low"
|
|
hexmask.long.byte 0xD00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD04 "GFXMMU_LUT928H,GFXMMU LUT entry 928 high"
|
|
hexmask.long.tbyte 0xD04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD08 "GFXMMU_LUT929L,GFXMMU LUT entry 929 low"
|
|
hexmask.long.byte 0xD08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD0C "GFXMMU_LUT929H,GFXMMU LUT entry 929 high"
|
|
hexmask.long.tbyte 0xD0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD10 "GFXMMU_LUT930L,GFXMMU LUT entry 930 low"
|
|
hexmask.long.byte 0xD10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD14 "GFXMMU_LUT930H,GFXMMU LUT entry 930 high"
|
|
hexmask.long.tbyte 0xD14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD18 "GFXMMU_LUT931L,GFXMMU LUT entry 931 low"
|
|
hexmask.long.byte 0xD18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD1C "GFXMMU_LUT931H,GFXMMU LUT entry 931 high"
|
|
hexmask.long.tbyte 0xD1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD20 "GFXMMU_LUT932L,GFXMMU LUT entry 932 low"
|
|
hexmask.long.byte 0xD20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD24 "GFXMMU_LUT932H,GFXMMU LUT entry 932 high"
|
|
hexmask.long.tbyte 0xD24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD28 "GFXMMU_LUT933L,GFXMMU LUT entry 933 low"
|
|
hexmask.long.byte 0xD28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD2C "GFXMMU_LUT933H,GFXMMU LUT entry 933 high"
|
|
hexmask.long.tbyte 0xD2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD30 "GFXMMU_LUT934L,GFXMMU LUT entry 934 low"
|
|
hexmask.long.byte 0xD30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD34 "GFXMMU_LUT934H,GFXMMU LUT entry 934 high"
|
|
hexmask.long.tbyte 0xD34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD38 "GFXMMU_LUT935L,GFXMMU LUT entry 935 low"
|
|
hexmask.long.byte 0xD38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD3C "GFXMMU_LUT935H,GFXMMU LUT entry 935 high"
|
|
hexmask.long.tbyte 0xD3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD40 "GFXMMU_LUT936L,GFXMMU LUT entry 936 low"
|
|
hexmask.long.byte 0xD40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD44 "GFXMMU_LUT936H,GFXMMU LUT entry 936 high"
|
|
hexmask.long.tbyte 0xD44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD48 "GFXMMU_LUT937L,GFXMMU LUT entry 937 low"
|
|
hexmask.long.byte 0xD48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD4C "GFXMMU_LUT937H,GFXMMU LUT entry 937 high"
|
|
hexmask.long.tbyte 0xD4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD50 "GFXMMU_LUT938L,GFXMMU LUT entry 938 low"
|
|
hexmask.long.byte 0xD50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD54 "GFXMMU_LUT938H,GFXMMU LUT entry 938 high"
|
|
hexmask.long.tbyte 0xD54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD58 "GFXMMU_LUT939L,GFXMMU LUT entry 939 low"
|
|
hexmask.long.byte 0xD58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD5C "GFXMMU_LUT939H,GFXMMU LUT entry 939 high"
|
|
hexmask.long.tbyte 0xD5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD60 "GFXMMU_LUT940L,GFXMMU LUT entry 940 low"
|
|
hexmask.long.byte 0xD60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD64 "GFXMMU_LUT940H,GFXMMU LUT entry 940 high"
|
|
hexmask.long.tbyte 0xD64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD68 "GFXMMU_LUT941L,GFXMMU LUT entry 941 low"
|
|
hexmask.long.byte 0xD68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD6C "GFXMMU_LUT941H,GFXMMU LUT entry 941 high"
|
|
hexmask.long.tbyte 0xD6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD70 "GFXMMU_LUT942L,GFXMMU LUT entry 942 low"
|
|
hexmask.long.byte 0xD70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD74 "GFXMMU_LUT942H,GFXMMU LUT entry 942 high"
|
|
hexmask.long.tbyte 0xD74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD78 "GFXMMU_LUT943L,GFXMMU LUT entry 943 low"
|
|
hexmask.long.byte 0xD78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD7C "GFXMMU_LUT943H,GFXMMU LUT entry 943 high"
|
|
hexmask.long.tbyte 0xD7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD80 "GFXMMU_LUT944L,GFXMMU LUT entry 944 low"
|
|
hexmask.long.byte 0xD80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD84 "GFXMMU_LUT944H,GFXMMU LUT entry 944 high"
|
|
hexmask.long.tbyte 0xD84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD88 "GFXMMU_LUT945L,GFXMMU LUT entry 945 low"
|
|
hexmask.long.byte 0xD88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD8C "GFXMMU_LUT945H,GFXMMU LUT entry 945 high"
|
|
hexmask.long.tbyte 0xD8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD90 "GFXMMU_LUT946L,GFXMMU LUT entry 946 low"
|
|
hexmask.long.byte 0xD90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD94 "GFXMMU_LUT946H,GFXMMU LUT entry 946 high"
|
|
hexmask.long.tbyte 0xD94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xD98 "GFXMMU_LUT947L,GFXMMU LUT entry 947 low"
|
|
hexmask.long.byte 0xD98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xD98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xD98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xD9C "GFXMMU_LUT947H,GFXMMU LUT entry 947 high"
|
|
hexmask.long.tbyte 0xD9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDA0 "GFXMMU_LUT948L,GFXMMU LUT entry 948 low"
|
|
hexmask.long.byte 0xDA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDA4 "GFXMMU_LUT948H,GFXMMU LUT entry 948 high"
|
|
hexmask.long.tbyte 0xDA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDA8 "GFXMMU_LUT949L,GFXMMU LUT entry 949 low"
|
|
hexmask.long.byte 0xDA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDAC "GFXMMU_LUT949H,GFXMMU LUT entry 949 high"
|
|
hexmask.long.tbyte 0xDAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDB0 "GFXMMU_LUT950L,GFXMMU LUT entry 950 low"
|
|
hexmask.long.byte 0xDB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDB4 "GFXMMU_LUT950H,GFXMMU LUT entry 950 high"
|
|
hexmask.long.tbyte 0xDB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDB8 "GFXMMU_LUT951L,GFXMMU LUT entry 951 low"
|
|
hexmask.long.byte 0xDB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDBC "GFXMMU_LUT951H,GFXMMU LUT entry 951 high"
|
|
hexmask.long.tbyte 0xDBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDC0 "GFXMMU_LUT952L,GFXMMU LUT entry 952 low"
|
|
hexmask.long.byte 0xDC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDC4 "GFXMMU_LUT952H,GFXMMU LUT entry 952 high"
|
|
hexmask.long.tbyte 0xDC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDC8 "GFXMMU_LUT953L,GFXMMU LUT entry 953 low"
|
|
hexmask.long.byte 0xDC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDCC "GFXMMU_LUT953H,GFXMMU LUT entry 953 high"
|
|
hexmask.long.tbyte 0xDCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDD0 "GFXMMU_LUT954L,GFXMMU LUT entry 954 low"
|
|
hexmask.long.byte 0xDD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDD4 "GFXMMU_LUT954H,GFXMMU LUT entry 954 high"
|
|
hexmask.long.tbyte 0xDD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDD8 "GFXMMU_LUT955L,GFXMMU LUT entry 955 low"
|
|
hexmask.long.byte 0xDD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDDC "GFXMMU_LUT955H,GFXMMU LUT entry 955 high"
|
|
hexmask.long.tbyte 0xDDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDE0 "GFXMMU_LUT956L,GFXMMU LUT entry 956 low"
|
|
hexmask.long.byte 0xDE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDE4 "GFXMMU_LUT956H,GFXMMU LUT entry 956 high"
|
|
hexmask.long.tbyte 0xDE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDE8 "GFXMMU_LUT957L,GFXMMU LUT entry 957 low"
|
|
hexmask.long.byte 0xDE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDEC "GFXMMU_LUT957H,GFXMMU LUT entry 957 high"
|
|
hexmask.long.tbyte 0xDEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDF0 "GFXMMU_LUT958L,GFXMMU LUT entry 958 low"
|
|
hexmask.long.byte 0xDF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDF4 "GFXMMU_LUT958H,GFXMMU LUT entry 958 high"
|
|
hexmask.long.tbyte 0xDF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xDF8 "GFXMMU_LUT959L,GFXMMU LUT entry 959 low"
|
|
hexmask.long.byte 0xDF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xDF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xDF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xDFC "GFXMMU_LUT959H,GFXMMU LUT entry 959 high"
|
|
hexmask.long.tbyte 0xDFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE00 "GFXMMU_LUT960L,GFXMMU LUT entry 960 low"
|
|
hexmask.long.byte 0xE00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE04 "GFXMMU_LUT960H,GFXMMU LUT entry 960 high"
|
|
hexmask.long.tbyte 0xE04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE08 "GFXMMU_LUT961L,GFXMMU LUT entry 961 low"
|
|
hexmask.long.byte 0xE08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE0C "GFXMMU_LUT961H,GFXMMU LUT entry 961 high"
|
|
hexmask.long.tbyte 0xE0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE10 "GFXMMU_LUT962L,GFXMMU LUT entry 962 low"
|
|
hexmask.long.byte 0xE10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE14 "GFXMMU_LUT962H,GFXMMU LUT entry 962 high"
|
|
hexmask.long.tbyte 0xE14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE18 "GFXMMU_LUT963L,GFXMMU LUT entry 963 low"
|
|
hexmask.long.byte 0xE18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE1C "GFXMMU_LUT963H,GFXMMU LUT entry 963 high"
|
|
hexmask.long.tbyte 0xE1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE20 "GFXMMU_LUT964L,GFXMMU LUT entry 964 low"
|
|
hexmask.long.byte 0xE20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE24 "GFXMMU_LUT964H,GFXMMU LUT entry 964 high"
|
|
hexmask.long.tbyte 0xE24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE28 "GFXMMU_LUT965L,GFXMMU LUT entry 965 low"
|
|
hexmask.long.byte 0xE28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE2C "GFXMMU_LUT965H,GFXMMU LUT entry 965 high"
|
|
hexmask.long.tbyte 0xE2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE30 "GFXMMU_LUT966L,GFXMMU LUT entry 966 low"
|
|
hexmask.long.byte 0xE30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE34 "GFXMMU_LUT966H,GFXMMU LUT entry 966 high"
|
|
hexmask.long.tbyte 0xE34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE38 "GFXMMU_LUT967L,GFXMMU LUT entry 967 low"
|
|
hexmask.long.byte 0xE38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE3C "GFXMMU_LUT967H,GFXMMU LUT entry 967 high"
|
|
hexmask.long.tbyte 0xE3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE40 "GFXMMU_LUT968L,GFXMMU LUT entry 968 low"
|
|
hexmask.long.byte 0xE40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE44 "GFXMMU_LUT968H,GFXMMU LUT entry 968 high"
|
|
hexmask.long.tbyte 0xE44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE48 "GFXMMU_LUT969L,GFXMMU LUT entry 969 low"
|
|
hexmask.long.byte 0xE48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE4C "GFXMMU_LUT969H,GFXMMU LUT entry 969 high"
|
|
hexmask.long.tbyte 0xE4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE50 "GFXMMU_LUT970L,GFXMMU LUT entry 970 low"
|
|
hexmask.long.byte 0xE50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE54 "GFXMMU_LUT970H,GFXMMU LUT entry 970 high"
|
|
hexmask.long.tbyte 0xE54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE58 "GFXMMU_LUT971L,GFXMMU LUT entry 971 low"
|
|
hexmask.long.byte 0xE58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE5C "GFXMMU_LUT971H,GFXMMU LUT entry 971 high"
|
|
hexmask.long.tbyte 0xE5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE60 "GFXMMU_LUT972L,GFXMMU LUT entry 972 low"
|
|
hexmask.long.byte 0xE60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE64 "GFXMMU_LUT972H,GFXMMU LUT entry 972 high"
|
|
hexmask.long.tbyte 0xE64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE68 "GFXMMU_LUT973L,GFXMMU LUT entry 973 low"
|
|
hexmask.long.byte 0xE68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE6C "GFXMMU_LUT973H,GFXMMU LUT entry 973 high"
|
|
hexmask.long.tbyte 0xE6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE70 "GFXMMU_LUT974L,GFXMMU LUT entry 974 low"
|
|
hexmask.long.byte 0xE70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE74 "GFXMMU_LUT974H,GFXMMU LUT entry 974 high"
|
|
hexmask.long.tbyte 0xE74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE78 "GFXMMU_LUT975L,GFXMMU LUT entry 975 low"
|
|
hexmask.long.byte 0xE78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE7C "GFXMMU_LUT975H,GFXMMU LUT entry 975 high"
|
|
hexmask.long.tbyte 0xE7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE80 "GFXMMU_LUT976L,GFXMMU LUT entry 976 low"
|
|
hexmask.long.byte 0xE80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE84 "GFXMMU_LUT976H,GFXMMU LUT entry 976 high"
|
|
hexmask.long.tbyte 0xE84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE88 "GFXMMU_LUT977L,GFXMMU LUT entry 977 low"
|
|
hexmask.long.byte 0xE88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE8C "GFXMMU_LUT977H,GFXMMU LUT entry 977 high"
|
|
hexmask.long.tbyte 0xE8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE90 "GFXMMU_LUT978L,GFXMMU LUT entry 978 low"
|
|
hexmask.long.byte 0xE90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE94 "GFXMMU_LUT978H,GFXMMU LUT entry 978 high"
|
|
hexmask.long.tbyte 0xE94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xE98 "GFXMMU_LUT979L,GFXMMU LUT entry 979 low"
|
|
hexmask.long.byte 0xE98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xE98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xE98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xE9C "GFXMMU_LUT979H,GFXMMU LUT entry 979 high"
|
|
hexmask.long.tbyte 0xE9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEA0 "GFXMMU_LUT980L,GFXMMU LUT entry 980 low"
|
|
hexmask.long.byte 0xEA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEA4 "GFXMMU_LUT980H,GFXMMU LUT entry 980 high"
|
|
hexmask.long.tbyte 0xEA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEA8 "GFXMMU_LUT981L,GFXMMU LUT entry 981 low"
|
|
hexmask.long.byte 0xEA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEAC "GFXMMU_LUT981H,GFXMMU LUT entry 981 high"
|
|
hexmask.long.tbyte 0xEAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEB0 "GFXMMU_LUT982L,GFXMMU LUT entry 982 low"
|
|
hexmask.long.byte 0xEB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEB4 "GFXMMU_LUT982H,GFXMMU LUT entry 982 high"
|
|
hexmask.long.tbyte 0xEB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEB8 "GFXMMU_LUT983L,GFXMMU LUT entry 983 low"
|
|
hexmask.long.byte 0xEB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEBC "GFXMMU_LUT983H,GFXMMU LUT entry 983 high"
|
|
hexmask.long.tbyte 0xEBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEC0 "GFXMMU_LUT984L,GFXMMU LUT entry 984 low"
|
|
hexmask.long.byte 0xEC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEC4 "GFXMMU_LUT984H,GFXMMU LUT entry 984 high"
|
|
hexmask.long.tbyte 0xEC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEC8 "GFXMMU_LUT985L,GFXMMU LUT entry 985 low"
|
|
hexmask.long.byte 0xEC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xECC "GFXMMU_LUT985H,GFXMMU LUT entry 985 high"
|
|
hexmask.long.tbyte 0xECC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xED0 "GFXMMU_LUT986L,GFXMMU LUT entry 986 low"
|
|
hexmask.long.byte 0xED0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xED0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xED0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xED4 "GFXMMU_LUT986H,GFXMMU LUT entry 986 high"
|
|
hexmask.long.tbyte 0xED4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xED8 "GFXMMU_LUT987L,GFXMMU LUT entry 987 low"
|
|
hexmask.long.byte 0xED8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xED8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xED8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEDC "GFXMMU_LUT987H,GFXMMU LUT entry 987 high"
|
|
hexmask.long.tbyte 0xEDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEE0 "GFXMMU_LUT988L,GFXMMU LUT entry 988 low"
|
|
hexmask.long.byte 0xEE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEE4 "GFXMMU_LUT988H,GFXMMU LUT entry 988 high"
|
|
hexmask.long.tbyte 0xEE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEE8 "GFXMMU_LUT989L,GFXMMU LUT entry 989 low"
|
|
hexmask.long.byte 0xEE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEEC "GFXMMU_LUT989H,GFXMMU LUT entry 989 high"
|
|
hexmask.long.tbyte 0xEEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEF0 "GFXMMU_LUT990L,GFXMMU LUT entry 990 low"
|
|
hexmask.long.byte 0xEF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEF4 "GFXMMU_LUT990H,GFXMMU LUT entry 990 high"
|
|
hexmask.long.tbyte 0xEF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xEF8 "GFXMMU_LUT991L,GFXMMU LUT entry 991 low"
|
|
hexmask.long.byte 0xEF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xEF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xEF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xEFC "GFXMMU_LUT991H,GFXMMU LUT entry 991 high"
|
|
hexmask.long.tbyte 0xEFC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF00 "GFXMMU_LUT992L,GFXMMU LUT entry 992 low"
|
|
hexmask.long.byte 0xF00 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF00 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF00 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF04 "GFXMMU_LUT992H,GFXMMU LUT entry 992 high"
|
|
hexmask.long.tbyte 0xF04 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF08 "GFXMMU_LUT993L,GFXMMU LUT entry 993 low"
|
|
hexmask.long.byte 0xF08 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF08 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF08 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF0C "GFXMMU_LUT993H,GFXMMU LUT entry 993 high"
|
|
hexmask.long.tbyte 0xF0C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF10 "GFXMMU_LUT994L,GFXMMU LUT entry 994 low"
|
|
hexmask.long.byte 0xF10 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF10 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF10 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF14 "GFXMMU_LUT994H,GFXMMU LUT entry 994 high"
|
|
hexmask.long.tbyte 0xF14 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF18 "GFXMMU_LUT995L,GFXMMU LUT entry 995 low"
|
|
hexmask.long.byte 0xF18 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF18 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF18 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF1C "GFXMMU_LUT995H,GFXMMU LUT entry 995 high"
|
|
hexmask.long.tbyte 0xF1C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF20 "GFXMMU_LUT996L,GFXMMU LUT entry 996 low"
|
|
hexmask.long.byte 0xF20 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF20 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF20 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF24 "GFXMMU_LUT996H,GFXMMU LUT entry 996 high"
|
|
hexmask.long.tbyte 0xF24 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF28 "GFXMMU_LUT997L,GFXMMU LUT entry 997 low"
|
|
hexmask.long.byte 0xF28 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF28 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF28 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF2C "GFXMMU_LUT997H,GFXMMU LUT entry 997 high"
|
|
hexmask.long.tbyte 0xF2C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF30 "GFXMMU_LUT998L,GFXMMU LUT entry 998 low"
|
|
hexmask.long.byte 0xF30 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF30 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF30 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF34 "GFXMMU_LUT998H,GFXMMU LUT entry 998 high"
|
|
hexmask.long.tbyte 0xF34 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF38 "GFXMMU_LUT999L,GFXMMU LUT entry 999 low"
|
|
hexmask.long.byte 0xF38 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF38 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF38 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF3C "GFXMMU_LUT999H,GFXMMU LUT entry 999 high"
|
|
hexmask.long.tbyte 0xF3C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF40 "GFXMMU_LUT1000L,GFXMMU LUT entry 1000 low"
|
|
hexmask.long.byte 0xF40 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF40 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF40 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF44 "GFXMMU_LUT1000H,GFXMMU LUT entry 1000 high"
|
|
hexmask.long.tbyte 0xF44 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF48 "GFXMMU_LUT1001L,GFXMMU LUT entry 1001 low"
|
|
hexmask.long.byte 0xF48 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF48 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF48 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF4C "GFXMMU_LUT1001H,GFXMMU LUT entry 1001 high"
|
|
hexmask.long.tbyte 0xF4C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF50 "GFXMMU_LUT1002L,GFXMMU LUT entry 1002 low"
|
|
hexmask.long.byte 0xF50 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF50 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF50 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF54 "GFXMMU_LUT1002H,GFXMMU LUT entry 1002 high"
|
|
hexmask.long.tbyte 0xF54 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF58 "GFXMMU_LUT1003L,GFXMMU LUT entry 1003 low"
|
|
hexmask.long.byte 0xF58 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF58 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF58 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF5C "GFXMMU_LUT1003H,GFXMMU LUT entry 1003 high"
|
|
hexmask.long.tbyte 0xF5C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF60 "GFXMMU_LUT1004L,GFXMMU LUT entry 1004 low"
|
|
hexmask.long.byte 0xF60 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF60 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF60 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF64 "GFXMMU_LUT1004H,GFXMMU LUT entry 1004 high"
|
|
hexmask.long.tbyte 0xF64 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF68 "GFXMMU_LUT1005L,GFXMMU LUT entry 1005 low"
|
|
hexmask.long.byte 0xF68 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF68 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF68 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF6C "GFXMMU_LUT1005H,GFXMMU LUT entry 1005 high"
|
|
hexmask.long.tbyte 0xF6C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF70 "GFXMMU_LUT1006L,GFXMMU LUT entry 1006 low"
|
|
hexmask.long.byte 0xF70 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF70 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF70 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF74 "GFXMMU_LUT1006H,GFXMMU LUT entry 1006 high"
|
|
hexmask.long.tbyte 0xF74 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF78 "GFXMMU_LUT1007L,GFXMMU LUT entry 1007 low"
|
|
hexmask.long.byte 0xF78 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF78 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF78 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF7C "GFXMMU_LUT1007H,GFXMMU LUT entry 1007 high"
|
|
hexmask.long.tbyte 0xF7C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF80 "GFXMMU_LUT1008L,GFXMMU LUT entry 1008 low"
|
|
hexmask.long.byte 0xF80 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF80 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF80 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF84 "GFXMMU_LUT1008H,GFXMMU LUT entry 1008 high"
|
|
hexmask.long.tbyte 0xF84 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF88 "GFXMMU_LUT1009L,GFXMMU LUT entry 1009 low"
|
|
hexmask.long.byte 0xF88 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF88 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF88 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF8C "GFXMMU_LUT1009H,GFXMMU LUT entry 1009 high"
|
|
hexmask.long.tbyte 0xF8C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF90 "GFXMMU_LUT1010L,GFXMMU LUT entry 1010 low"
|
|
hexmask.long.byte 0xF90 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF90 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF90 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF94 "GFXMMU_LUT1010H,GFXMMU LUT entry 1010 high"
|
|
hexmask.long.tbyte 0xF94 0.--17. 1. "LO,Line offset"
|
|
line.long 0xF98 "GFXMMU_LUT1011L,GFXMMU LUT entry 1011 low"
|
|
hexmask.long.byte 0xF98 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xF98 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xF98 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xF9C "GFXMMU_LUT1011H,GFXMMU LUT entry 1011 high"
|
|
hexmask.long.tbyte 0xF9C 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFA0 "GFXMMU_LUT1012L,GFXMMU LUT entry 1012 low"
|
|
hexmask.long.byte 0xFA0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFA0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFA0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFA4 "GFXMMU_LUT1012H,GFXMMU LUT entry 1012 high"
|
|
hexmask.long.tbyte 0xFA4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFA8 "GFXMMU_LUT1013L,GFXMMU LUT entry 1013 low"
|
|
hexmask.long.byte 0xFA8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFA8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFA8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFAC "GFXMMU_LUT1013H,GFXMMU LUT entry 1013 high"
|
|
hexmask.long.tbyte 0xFAC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFB0 "GFXMMU_LUT1014L,GFXMMU LUT entry 1014 low"
|
|
hexmask.long.byte 0xFB0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFB0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFB0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFB4 "GFXMMU_LUT1014H,GFXMMU LUT entry 1014 high"
|
|
hexmask.long.tbyte 0xFB4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFB8 "GFXMMU_LUT1015L,GFXMMU LUT entry 1015 low"
|
|
hexmask.long.byte 0xFB8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFB8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFB8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFBC "GFXMMU_LUT1015H,GFXMMU LUT entry 1015 high"
|
|
hexmask.long.tbyte 0xFBC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFC0 "GFXMMU_LUT1016L,GFXMMU LUT entry 1016 low"
|
|
hexmask.long.byte 0xFC0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFC0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFC0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFC4 "GFXMMU_LUT1016H,GFXMMU LUT entry 1016 high"
|
|
hexmask.long.tbyte 0xFC4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFC8 "GFXMMU_LUT1017L,GFXMMU LUT entry 1017 low"
|
|
hexmask.long.byte 0xFC8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFC8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFC8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFCC "GFXMMU_LUT1017H,GFXMMU LUT entry 1017 high"
|
|
hexmask.long.tbyte 0xFCC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFD0 "GFXMMU_LUT1018L,GFXMMU LUT entry 1018 low"
|
|
hexmask.long.byte 0xFD0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFD0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFD0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFD4 "GFXMMU_LUT1018H,GFXMMU LUT entry 1018 high"
|
|
hexmask.long.tbyte 0xFD4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFD8 "GFXMMU_LUT1019L,GFXMMU LUT entry 1019 low"
|
|
hexmask.long.byte 0xFD8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFD8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFD8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFDC "GFXMMU_LUT1019H,GFXMMU LUT entry 1019 high"
|
|
hexmask.long.tbyte 0xFDC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFE0 "GFXMMU_LUT1020L,GFXMMU LUT entry 1020 low"
|
|
hexmask.long.byte 0xFE0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFE0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFE0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFE4 "GFXMMU_LUT1020H,GFXMMU LUT entry 1020 high"
|
|
hexmask.long.tbyte 0xFE4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFE8 "GFXMMU_LUT1021L,GFXMMU LUT entry 1021 low"
|
|
hexmask.long.byte 0xFE8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFE8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFE8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFEC "GFXMMU_LUT1021H,GFXMMU LUT entry 1021 high"
|
|
hexmask.long.tbyte 0xFEC 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFF0 "GFXMMU_LUT1022L,GFXMMU LUT entry 1022 low"
|
|
hexmask.long.byte 0xFF0 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFF0 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFF0 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFF4 "GFXMMU_LUT1022H,GFXMMU LUT entry 1022 high"
|
|
hexmask.long.tbyte 0xFF4 0.--17. 1. "LO,Line offset"
|
|
line.long 0xFF8 "GFXMMU_LUT1023L,GFXMMU LUT entry 1023 low"
|
|
hexmask.long.byte 0xFF8 16.--23. 1. "LVB,Last valid block"
|
|
hexmask.long.byte 0xFF8 8.--15. 1. "FVB,First valid block"
|
|
bitfld.long 0xFF8 0. "EN,Enable" "0: Line is disabled (no MMU evaluation is performed),1: Line is enabled (MMU evaluation is performed)"
|
|
line.long 0xFFC "GFXMMU_LUT1023H,GFXMMU LUT entry 1023 high"
|
|
hexmask.long.tbyte 0xFFC 0.--17. 1. "LO,Line offset"
|
|
tree.end
|
|
tree "GFXTIM (Graphic Timer)"
|
|
base ad:0x50004000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "GFXTIM_CR,GFXTIM configuration register"
|
|
bitfld.long 0x0 17. "LCCOE,line-clock calibration output enable" "0: line-clock output disabled,1: line-clock output enabled"
|
|
bitfld.long 0x0 16. "FCCOE,frame-clock calibration output enable" "0: frame-clock output disabled,1: frame-clock output enabled"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SYNCS,synchronization source" "0: gfxtim_hsync[0] and gfxtim_vsync[0] selected,1: gfxtim_hsync[1] and gfxtim_vsync[1] selected,2: gfxtim_hsync[2] and gfxtim_vsync[2] selected,3: gfxtim_hsync[3] and gfxtim_vsync[3] selected"
|
|
bitfld.long 0x0 4. "TEPOL,tearing--effect polarity" "0: tearing effect active on rising edge,1: tearing effect active on falling edge"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TES,tearing source" "0: TE input pad selected,1: gfxtim_ite selected,2: HSYNC input selected by SYNCS[1:0],3: VSYNC input selected by SYNCS[1:0]"
|
|
line.long 0x4 "GFXTIM_CGCR,GFXTIM clock generator configuration register"
|
|
bitfld.long 0x4 28.--30. "FCCHRS,frame- -clock counter hardware reload source" "0: no hardware reload,1: line- -clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge"
|
|
bitfld.long 0x4 24. "FCCFR,frame clock counter force reload" "0: No effect,1: frame clock counter reload forced"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FCCCS,frame clock counter clock source" "0: frame clock counter disabled,1: line clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge"
|
|
bitfld.long 0x4 16.--18. "FCS,frame clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "LCCHRS,line clock counter hardware reload source" "0: no hardware reload,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge"
|
|
bitfld.long 0x4 8. "LCCFR,line clock counter force reload" "0: no effect,1: line clock counter reload forced"
|
|
newline
|
|
bitfld.long 0x4 4. "LCCCS,line clock counter clock source" "0: line clock counter disabled,1: system clock selected"
|
|
bitfld.long 0x4 0.--2. "LCS,line clock source" "0: line clock counter underflow,1: frame clock counter underflow,2: HSYNC rising edge,3: HSYNC falling edge,4: VSYNC rising edge,5: VSYNC falling edge,6: TE rising edge,7: TE falling edge"
|
|
line.long 0x8 "GFXTIM_TCR,GFXTIM timers configuration register"
|
|
bitfld.long 0x8 22. "FRFC2R,force relative frame counter 2 reload" "0: no effect,1: relative frame counter 2 reload forced"
|
|
bitfld.long 0x8 21. "RFC2CM,relative frame counter 2 continuous mode" "0: relative frame counter 2 is one shot.,1: relative frame counter 2 is in continuous mode."
|
|
newline
|
|
bitfld.long 0x8 20. "RFC2EN,relative frame counter 2 enable" "0: no effect,1: relative frame counter 2 enabled"
|
|
bitfld.long 0x8 18. "FRFC1R,force relative frame counter 1 reload" "0: no effect,1: relative frame counter 1 reload forced"
|
|
newline
|
|
bitfld.long 0x8 17. "RFC1CM,relative frame counter 1 continuous mode" "0: relative frame counter 1 is one shot.,1: relative frame counter 1 is in continuous mode."
|
|
bitfld.long 0x8 16. "RFC1EN,relative frame counter 1 enable" "0: no effect,1: relative frame counter enabled"
|
|
newline
|
|
bitfld.long 0x8 5. "FALCR,force absolute line counter reset" "0: no effect,1: absolute line counter reset forced"
|
|
bitfld.long 0x8 4. "ALCEN,absolute line counter enable" "0: no effect,1: absolute line counter enabled"
|
|
newline
|
|
bitfld.long 0x8 1. "FAFCR,force absolute frame counter reset" "0: no effect,1: absolute frame counter reset forced"
|
|
bitfld.long 0x8 0. "AFCEN,absolute frame counter enable" "0: no effect,1: absolute frame counter enabled"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "GFXTIM_TDR,GFXTIM timers disable register"
|
|
bitfld.long 0x0 20. "RFC2DIS,relative frame counter 2 disable" "0: no effect,1: relative frame counter 2 disabled"
|
|
bitfld.long 0x0 16. "RFC1DIS,relative frame counter 1 disable" "0: no effect,1: relative frame counter 1 disabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ALCDIS,absolute line counter disable" "0: no effect,1: absolute line counter disabled"
|
|
bitfld.long 0x0 0. "AFCDIS,absolute frame counter disable" "0: no effect,1: absolute frame counter disabled"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "GFXTIM_EVCR,GFXTIM events control register"
|
|
bitfld.long 0x0 3. "EV4EN,event 4 enable" "0: event 4 generation disabled,1: event 4 generation enabled"
|
|
bitfld.long 0x0 2. "EV3EN,event 3 enable" "0: event 3 generation disabled,1: event 3 generation enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "EV2EN,event 2 enable" "0: event 2 generation disabled,1: event 2 generation enabled"
|
|
bitfld.long 0x0 0. "EV1EN,event 1 enable" "0: event 1 generation disabled,1: event 1 generation enabled"
|
|
line.long 0x4 "GFXTIM_EVSR,GFXTIM events selection register"
|
|
bitfld.long 0x4 28.--30. "FES4,frame-event selection 4" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?"
|
|
bitfld.long 0x4 24.--26. "LES4,line-event selection 4" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FES3,frame-event selection 3" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?"
|
|
bitfld.long 0x4 16.--18. "LES3,line-event selection 3" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "FES2,frame-event selection 2" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?"
|
|
bitfld.long 0x4 8.--10. "LES2,line-event selection 2" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "FES1,frame-event selection 1" "0: no frame event,1: absolute frame counter overflow,2: absolute frame counter compare,?,4: relative frame counter 1 reload,5: relative frame counter 2 reload,?,?"
|
|
bitfld.long 0x4 0.--2. "LES1,line-event selection 1" "0: no line event,1: absolute line counter overflow,2: tearing effect,?,4: absolute line counter 1 compare,5: absolute line counter 2 compare,?,?"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "GFXTIM_WDGTCR,GFXTIM watchdog timer configuration register"
|
|
bitfld.long 0x0 16. "FWDGR,force watchdog reload" "0: no effect,1: graphic watchdog reload forced"
|
|
hexmask.long.byte 0x0 8.--11. 1. "WDGCS,watchdog clock source"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "WDGHRC,watchdog hardware reload configuration" "0: watchdog hardware reload disabled,1: watchdog reloaded a rising edge of gfxtim_wrld,2: watchdog reloaded a falling edge of gfxtim_wrld,3: FIELD Reserved"
|
|
rbitfld.long 0x0 2. "WDGS,watchdog status" "0: graphic watchdog disabled,1: graphic watchdog enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "WDGDIS,watchdog disable" "0: no effect,1: graphic watchdog disabled"
|
|
bitfld.long 0x0 0. "WDGEN,watchdog enable" "0: no effect,1: graphic watchdog enabled"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "GFXTIM_ISR,GFXTIM interrupt status register"
|
|
bitfld.long 0x0 25. "WDGPF,watchdog pre-alarm flag" "0: no graphic watchdog pre-alarm occurred.,1: a graphic watchdog pre-alarm occurred."
|
|
bitfld.long 0x0 24. "WDGAF,watchdog alarm flag" "0: no graphic watchdog alarm occurred.,1: a graphic watchdog alarm occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "EV4F,event 4 flag" "0: no complex event 4 occurred.,1: a complex event 4 occurred."
|
|
bitfld.long 0x0 18. "EV3F,event 3 flag" "0: no complex event 3 occurred.,1: a complex event 3 occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "EV2F,event 2 flag" "0: no complex event 2 occurred.,1: a complex event 2 occurred."
|
|
bitfld.long 0x0 16. "EV1F,event 1 flag" "0: No complex event 1 occurred.,1: Complex event 1 occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "RFC2RF,relative frame counter 2 reload flag" "0: no reload occurred on relative frame counter 2.,1: a reload on relative frame counter 2 occurred."
|
|
bitfld.long 0x0 12. "RFC1RF,relative frame counter 1 reload flag" "0: no reload occurred on relative frame counter 1.,1: a reload on relative frame counter 1 occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "ALCC2F,absolute line counter compare 2 flag" "0: no match occurred on compare 2 of the absolute..,1: a match on compare 2 of the absolute line.."
|
|
bitfld.long 0x0 8. "ALCC1F,absolute line counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute line.."
|
|
newline
|
|
bitfld.long 0x0 4. "AFCC1F,absolute frame counter compare 1 flag" "0: no match occurred on compare 1 of the absolute..,1: a match on compare 1 of the absolute frame.."
|
|
bitfld.long 0x0 2. "TEF,tearing-effect flag" "0: no tearing effect occurred.,1: a tearing effect occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "ALCOF,absolute line counter overflow flag" "0: no overflow occurred on the absolute line counter.,1: a overflow on the absolute line counter occurred."
|
|
bitfld.long 0x0 0. "AFCOF,absolute frame counter overflow flag" "0: no overflow occurred on the absolute frame..,1: a overflow on the absolute frame counter occurred."
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "GFXTIM_ICR,GFXTIM interrupt clear register"
|
|
bitfld.long 0x0 25. "CWDGPF,clear watchdog pre-alarm flag" "0: no effect,1: WDGPF cleared"
|
|
bitfld.long 0x0 24. "CWDGAF,clear watchdog alarm flag" "0: no effect,1: WDGAF cleared"
|
|
newline
|
|
bitfld.long 0x0 19. "CEV4F,clear event 4 flag" "0: no effect,1: EV4F cleared"
|
|
bitfld.long 0x0 18. "CEV3F,clear event 3 flag" "0: no effect,1: EV3F cleared"
|
|
newline
|
|
bitfld.long 0x0 17. "CEV2F,clear event 2 flag" "0: no effect,1: EV2F cleared"
|
|
bitfld.long 0x0 16. "CEV1F,clear event 1 flag" "0: no effect,1: EV1F cleared"
|
|
newline
|
|
bitfld.long 0x0 13. "CRFC2RF,clear relative frame counter 2 reload flag" "0: no effect,1: RFC2RF cleared"
|
|
bitfld.long 0x0 12. "CRFC1RF,clear relative frame counter 1 reload flag" "0: no effect,1: RFC1RF cleared"
|
|
newline
|
|
bitfld.long 0x0 9. "CALCC2F,clear absolute line counter compare 2 flag" "0: no effect,1: ALCC2F cleared"
|
|
bitfld.long 0x0 8. "CALCC1F,clear absolute line counter compare 1 flag" "0: no effect,1: ALCC1F cleared"
|
|
newline
|
|
bitfld.long 0x0 4. "CAFCC1F,clear absolute frame counter compare 1 flag" "0: no effect,1: AFCC1F cleared"
|
|
bitfld.long 0x0 2. "CTEF,clear tearing-effect flag" "0: no effect,1: TEF cleared"
|
|
newline
|
|
bitfld.long 0x0 1. "CALCOF,clear absolute line counter overflow flag" "0: no effect,1: ALCOF cleared"
|
|
bitfld.long 0x0 0. "CAFCOF,clear absolute frame counter overflow flag" "0: no effect,1: AFCOF cleared"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "GFXTIM_IER,GFXTIM interrupt enable register"
|
|
bitfld.long 0x0 25. "WDGPIE,watchdog pre-alarm interrupt enable" "0: watchdog pre-alarm interrupt disabled,1: watchdog pre-alarm interrupt enabled"
|
|
bitfld.long 0x0 24. "WDGAIE,watchdog alarm interrupt enable" "0: watchdog alarm interrupt disabled,1: watchdog alarm interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "EV4IE,event 4 interrupt enable" "0: event 4 interrupt disabled,1: event 4 interrupt enabled"
|
|
bitfld.long 0x0 18. "EV3IE,event 3 interrupt enable" "0: event 3 interrupt disabled,1: event 3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "EV2IE,event 2 interrupt enable" "0: event 2 interrupt disabled,1: event 2 interrupt enabled"
|
|
bitfld.long 0x0 16. "EV1IE,event 1 interrupt enable" "0: event 1 interrupt disabled,1: event 1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "RFC2RIE,relative frame counter 2 reload interrupt enable" "0: relative frame counter 2 reload interrupt disabled,1: relative frame counter 2 reload interrupt enabled"
|
|
bitfld.long 0x0 12. "RFC1RIE,relative frame counter 1 reload interrupt enable" "0: relative frame counter 1 reload interrupt disabled,1: relative frame counter 1 reload interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "ALCC2IE,absolute line counter compare 2 interrupt enable" "0: absolute line counter compare 2 interrupt disabled,1: absolute line counter compare 2 interrupt enabled"
|
|
bitfld.long 0x0 8. "ALCC1IE,absolute line counter compare 1 interrupt enable" "0: absolute line counter compare 1 interrupt disabled,1: absolute line counter compare 1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "AFCC1IE,absolute frame counter compare 1 interrupt enable" "0: absolute frame counter compare 1 interrupt..,1: absolute frame counter compare 1 interrupt enabled"
|
|
bitfld.long 0x0 2. "TEIE,tearing-effect interrupt enable" "0: tearing-effect interrupt disabled,1: tearing-effect interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ALCOIE,absolute line counter overflow interrupt enable" "0: absolute line counter overflow interrupt disabled,1: absolute line counter overflow interrupt enabled"
|
|
bitfld.long 0x0 0. "AFCOIE,absolute frame counter overflow interrupt enable" "0: absolute frame counter overflow interrupt disabled,1: absolute frame counter overflow interrupt enabled"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "GFXTIM_TSR,GFXTIM timers status register"
|
|
bitfld.long 0x0 20. "RFC2S,relative frame counter 2 status" "0: relative frame counter 2 disabled,1: relative frame counter 2 enabled"
|
|
bitfld.long 0x0 16. "RFC1S,relative frame counter 1 status" "0: relative frame counter 1 disabled,1: relative frame counter 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ALCS,absolute line counter status" "0: absolute line counter disabled,1: absolute line counter enabled"
|
|
bitfld.long 0x0 0. "AFCS,absolute frame counter status" "0: absolute frame counter disabled,1: absolute frame counter enabled"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "GFXTIM_LCCRR,GFXTIM line clock counter reload register"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "RELOAD,reload value"
|
|
line.long 0x4 "GFXTIM_FCCRR,GFXTIM frame clock counter reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RELOAD,reload value"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "GFXTIM_ATR,GFXTIM absolute time register"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "FRAME,fame number"
|
|
hexmask.long.word 0x0 0.--11. 1. "LINE,line number"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "GFXTIM_AFCR,GFXTIM absolute frame counter register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number"
|
|
line.long 0x4 "GFXTIM_ALCR,GFXTIM absolute line counter register"
|
|
hexmask.long.word 0x4 0.--11. 1. "LINE,line number"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "GFXTIM_AFCC1R,GFXTIM absolute frame counter compare 1 register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "FRAME,frame number"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "GFXTIM_ALCC1R,GFXTIM absolute line counter compare 1 register"
|
|
hexmask.long.word 0x0 0.--11. 1. "LINE,line number"
|
|
line.long 0x4 "GFXTIM_ALCC2R,GFXTIM absolute line counter compare 2 register"
|
|
hexmask.long.word 0x4 0.--11. 1. "LINE,line number"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "GFXTIM_RFC1R,GFXTIM relative frame counter 1 register"
|
|
hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "GFXTIM_RFC1RR,GFXTIM relative frame counter 1 reload register"
|
|
hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "GFXTIM_RFC2R,GFXTIM relative frame counter 2 register"
|
|
hexmask.long.word 0x0 0.--11. 1. "FRAME,frame number"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "GFXTIM_RFC2RR,GFXTIM relative frame counter 2 reload register"
|
|
hexmask.long.word 0x0 0.--11. 1. "FRAME,frame reload value"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x0 "GFXTIM_WDGCR,GFXTIM watchdog counter register"
|
|
hexmask.long.word 0x0 0.--15. 1. "VALUE,value"
|
|
group.long 0xA4++0x7
|
|
line.long 0x0 "GFXTIM_WDGRR,GFXTIM watchdog reload register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RELOAD,reload value"
|
|
line.long 0x4 "GFXTIM_WDGPAR,GFXTIM watchdog pre-alarm register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PREALARM,pre-alarm value"
|
|
tree.end
|
|
tree "GPDMA (General Purpose Direct Memory Access Controller)"
|
|
base ad:0x40021000
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "GPDMA_PRIVCFGR,GPDMA privileged configuration register"
|
|
bitfld.long 0x0 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
line.long 0x4 "GPDMA_RCFGLOCKR,GPDMA configuration lock register"
|
|
bitfld.long 0x4 15. "LOCK15,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 14. "LOCK14,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 13. "LOCK13,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 12. "LOCK12,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 11. "LOCK11,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 10. "LOCK10,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 9. "LOCK9,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 8. "LOCK8,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 7. "LOCK7,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 6. "LOCK6,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK5,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 4. "LOCK4,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK3,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 2. "LOCK2,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK1,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 0. "LOCK0,lock the configuration of GPDMA_PRIVCFGR.PRIVx until a global GPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "GPDMA_MISR,GPDMA masked interrupt status register"
|
|
bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "GPDMA_C0LBAR,GPDMA channel 0 linked-list base address register"
|
|
hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "GPDMA_C0FCR,GPDMA channel 0 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "GPDMA_C0SR,GPDMA channel 0 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "GPDMA_C0CR,GPDMA channel 0 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
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|
group.long 0x90++0x13
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line.long 0x0 "GPDMA_C0TR1,GPDMA channel 0 transfer register 1"
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|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
newline
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|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
line.long 0x4 "GPDMA_C0TR2,GPDMA channel 0 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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|
newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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|
newline
|
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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line.long 0x8 "GPDMA_C0BR1,GPDMA channel 0 block register 1"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C0SAR,GPDMA channel 0 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C0DAR,GPDMA channel 0 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "GPDMA_C0LLR,GPDMA channel 0 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
|
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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|
newline
|
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
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|
line.long 0x4 "GPDMA_C1LBAR,GPDMA channel 1 linked-list base address register"
|
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
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wgroup.long 0xDC++0x3
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|
line.long 0x0 "GPDMA_C1FCR,GPDMA channel 1 flag clear register"
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bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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|
newline
|
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0xE0++0x3
|
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line.long 0x0 "GPDMA_C1SR,GPDMA channel 1 status register"
|
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hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
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bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
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|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "GPDMA_C1CR,GPDMA channel 1 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x110++0x13
|
|
line.long 0x0 "GPDMA_C1TR1,GPDMA channel 1 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C1TR2,GPDMA channel 1 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C1BR1,GPDMA channel 1 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C1SAR,GPDMA channel 1 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C1DAR,GPDMA channel 1 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x14C++0x7
|
|
line.long 0x0 "GPDMA_C1LLR,GPDMA channel 1 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C2LBAR,GPDMA channel 2 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x15C++0x3
|
|
line.long 0x0 "GPDMA_C2FCR,GPDMA channel 2 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x160++0x3
|
|
line.long 0x0 "GPDMA_C2SR,GPDMA channel 2 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "GPDMA_C2CR,GPDMA channel 2 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x190++0x13
|
|
line.long 0x0 "GPDMA_C2TR1,GPDMA channel 2 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
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|
newline
|
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
line.long 0x4 "GPDMA_C2TR2,GPDMA channel 2 transfer register 2"
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|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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|
newline
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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|
newline
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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|
line.long 0x8 "GPDMA_C2BR1,GPDMA channel 2 block register 1"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C2SAR,GPDMA channel 2 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C2DAR,GPDMA channel 2 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
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group.long 0x1CC++0x7
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line.long 0x0 "GPDMA_C2LLR,GPDMA channel 2 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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newline
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bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
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bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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|
newline
|
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C3LBAR,GPDMA channel 3 linked-list base address register"
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
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wgroup.long 0x1DC++0x3
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line.long 0x0 "GPDMA_C3FCR,GPDMA channel 3 flag clear register"
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bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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newline
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
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|
newline
|
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bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
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|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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newline
|
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
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|
rgroup.long 0x1E0++0x3
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line.long 0x0 "GPDMA_C3SR,GPDMA channel 3 status register"
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hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
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bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
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newline
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bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
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|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
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newline
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bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
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|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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|
newline
|
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bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
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|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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newline
|
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bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
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|
group.long 0x1E4++0x3
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line.long 0x0 "GPDMA_C3CR,GPDMA channel 3 control register"
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bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
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bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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|
newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
|
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x210++0x13
|
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line.long 0x0 "GPDMA_C3TR1,GPDMA channel 3 transfer register 1"
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|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
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bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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newline
|
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bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C3TR2,GPDMA channel 3 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C3BR1,GPDMA channel 3 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C3SAR,GPDMA channel 3 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C3DAR,GPDMA channel 3 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x24C++0x7
|
|
line.long 0x0 "GPDMA_C3LLR,GPDMA channel 3 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C4LBAR,GPDMA channel 4 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x25C++0x3
|
|
line.long 0x0 "GPDMA_C4FCR,GPDMA channel 4 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x260++0x3
|
|
line.long 0x0 "GPDMA_C4SR,GPDMA channel 4 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "GPDMA_C4CR,GPDMA channel 4 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x290++0x13
|
|
line.long 0x0 "GPDMA_C4TR1,GPDMA channel 4 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C4TR2,GPDMA channel 4 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C4BR1,GPDMA channel 4 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C4SAR,GPDMA channel 4 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C4DAR,GPDMA channel 4 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x2CC++0x7
|
|
line.long 0x0 "GPDMA_C4LLR,GPDMA channel 4 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C5LBAR,GPDMA channel 5 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x2DC++0x3
|
|
line.long 0x0 "GPDMA_C5FCR,GPDMA channel 5 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x2E0++0x3
|
|
line.long 0x0 "GPDMA_C5SR,GPDMA channel 5 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "GPDMA_C5CR,GPDMA channel 5 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x310++0x13
|
|
line.long 0x0 "GPDMA_C5TR1,GPDMA channel 5 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C5TR2,GPDMA channel 5 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C5BR1,GPDMA channel 5 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C5SAR,GPDMA channel 5 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C5DAR,GPDMA channel 5 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x34C++0x7
|
|
line.long 0x0 "GPDMA_C5LLR,GPDMA channel 5 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C6LBAR,GPDMA channel 6 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x35C++0x3
|
|
line.long 0x0 "GPDMA_C6FCR,GPDMA channel 6 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x360++0x3
|
|
line.long 0x0 "GPDMA_C6SR,GPDMA channel 6 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x364++0x3
|
|
line.long 0x0 "GPDMA_C6CR,GPDMA channel 6 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x390++0x13
|
|
line.long 0x0 "GPDMA_C6TR1,GPDMA channel 6 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C6TR2,GPDMA channel 6 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C6BR1,GPDMA channel 6 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C6SAR,GPDMA channel 6 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C6DAR,GPDMA channel 6 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x3CC++0x7
|
|
line.long 0x0 "GPDMA_C6LLR,GPDMA channel 6 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C7LBAR,GPDMA channel 7 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x3DC++0x3
|
|
line.long 0x0 "GPDMA_C7FCR,GPDMA channel 7 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x3E0++0x3
|
|
line.long 0x0 "GPDMA_C7SR,GPDMA channel 7 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x3E4++0x3
|
|
line.long 0x0 "GPDMA_C7CR,GPDMA channel 7 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x410++0x13
|
|
line.long 0x0 "GPDMA_C7TR1,GPDMA channel 7 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C7TR2,GPDMA channel 7 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C7BR1,GPDMA channel 7 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C7SAR,GPDMA channel 7 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C7DAR,GPDMA channel 7 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "GPDMA_C7LLR,GPDMA channel 7 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C8LBAR,GPDMA channel 8 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x45C++0x3
|
|
line.long 0x0 "GPDMA_C8FCR,GPDMA channel 8 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x460++0x3
|
|
line.long 0x0 "GPDMA_C8SR,GPDMA channel 8 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x464++0x3
|
|
line.long 0x0 "GPDMA_C8CR,GPDMA channel 8 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x490++0x13
|
|
line.long 0x0 "GPDMA_C8TR1,GPDMA channel 8 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C8TR2,GPDMA channel 8 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C8BR1,GPDMA channel 8 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C8SAR,GPDMA channel 8 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C8DAR,GPDMA channel 8 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x4CC++0x7
|
|
line.long 0x0 "GPDMA_C8LLR,GPDMA channel 8 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C9LBAR,GPDMA channel 9 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x4DC++0x3
|
|
line.long 0x0 "GPDMA_C9FCR,GPDMA channel 9 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x4E0++0x3
|
|
line.long 0x0 "GPDMA_C9SR,GPDMA channel 9 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "GPDMA_C9CR,GPDMA channel 9 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x510++0x13
|
|
line.long 0x0 "GPDMA_C9TR1,GPDMA channel 9 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
line.long 0x4 "GPDMA_C9TR2,GPDMA channel 9 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C9BR1,GPDMA channel 9 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C9SAR,GPDMA channel 9 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C9DAR,GPDMA channel 9 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x54C++0x7
|
|
line.long 0x0 "GPDMA_C9LLR,GPDMA channel 9 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C10LBAR,GPDMA channel 10 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x55C++0x3
|
|
line.long 0x0 "GPDMA_C10FCR,GPDMA channel 10 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x560++0x3
|
|
line.long 0x0 "GPDMA_C10SR,GPDMA channel 10 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x564++0x3
|
|
line.long 0x0 "GPDMA_C10CR,GPDMA channel 10 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x590++0x13
|
|
line.long 0x0 "GPDMA_C10TR1,GPDMA channel 10 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
newline
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
|
|
line.long 0x4 "GPDMA_C10TR2,GPDMA channel 10 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
|
|
line.long 0x8 "GPDMA_C10BR1,GPDMA channel 10 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "GPDMA_C10SAR,GPDMA channel 10 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "GPDMA_C10DAR,GPDMA channel 10 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x5CC++0x7
|
|
line.long 0x0 "GPDMA_C10LLR,GPDMA channel 10 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C11LBAR,GPDMA channel 11 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
|
wgroup.long 0x5DC++0x3
|
|
line.long 0x0 "GPDMA_C11FCR,GPDMA channel 11 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x5E0++0x3
|
|
line.long 0x0 "GPDMA_C11SR,GPDMA channel 11 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x5E4++0x3
|
|
line.long 0x0 "GPDMA_C11CR,GPDMA channel 11 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x610++0x13
|
|
line.long 0x0 "GPDMA_C11TR1,GPDMA channel 11 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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newline
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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newline
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bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
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newline
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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line.long 0x4 "GPDMA_C11TR2,GPDMA channel 11 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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newline
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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newline
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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newline
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hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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line.long 0x8 "GPDMA_C11BR1,GPDMA channel 11 block register 1"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C11SAR,GPDMA channel 11 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C11DAR,GPDMA channel 11 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
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group.long 0x64C++0x7
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line.long 0x0 "GPDMA_C11LLR,GPDMA channel 11 linked-list address register"
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bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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newline
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bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
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bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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newline
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
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line.long 0x4 "GPDMA_C12LBAR,GPDMA channel 12 linked-list base address register"
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
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wgroup.long 0x65C++0x3
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line.long 0x0 "GPDMA_C12FCR,GPDMA channel 12 flag clear register"
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bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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newline
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
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newline
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bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
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bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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newline
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
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rgroup.long 0x660++0x3
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line.long 0x0 "GPDMA_C12SR,GPDMA channel 12 status register"
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hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
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bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
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newline
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bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
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bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
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newline
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bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
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bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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newline
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bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
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bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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newline
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bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
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group.long 0x664++0x3
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line.long 0x0 "GPDMA_C12CR,GPDMA channel 12 control register"
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bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
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bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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newline
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
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bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
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group.long 0x690++0x1B
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line.long 0x0 "GPDMA_C12TR1,GPDMA channel 12 transfer register 1"
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bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
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newline
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bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
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hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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newline
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bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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newline
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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newline
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bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
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newline
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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line.long 0x4 "GPDMA_C12TR2,GPDMA channel 12 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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newline
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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newline
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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newline
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hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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line.long 0x8 "GPDMA_C12BR1,GPDMA channel 12 alternate block register 1"
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bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.."
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bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.."
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newline
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bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
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bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
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newline
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hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C12SAR,GPDMA channel 12 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C12DAR,GPDMA channel 12 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
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line.long 0x14 "GPDMA_C12TR3,GPDMA channel 12 transfer register 3"
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hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
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hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
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line.long 0x18 "GPDMA_C12BR2,GPDMA channel 12 block register 2"
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hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
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hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
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group.long 0x6CC++0x7
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line.long 0x0 "GPDMA_C12LLR,GPDMA channel 12 alternate linked-list address register"
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bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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newline
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bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
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bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update"
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newline
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bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update"
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bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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newline
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
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line.long 0x4 "GPDMA_C13LBAR,GPDMA channel 13 linked-list base address register"
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
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wgroup.long 0x6DC++0x3
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line.long 0x0 "GPDMA_C13FCR,GPDMA channel 13 flag clear register"
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bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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newline
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
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newline
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bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
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bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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newline
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
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rgroup.long 0x6E0++0x3
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line.long 0x0 "GPDMA_C13SR,GPDMA channel 13 status register"
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hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
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bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
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newline
|
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bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
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bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
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newline
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bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
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bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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newline
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bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
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bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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newline
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bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
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group.long 0x6E4++0x3
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line.long 0x0 "GPDMA_C13CR,GPDMA channel 13 control register"
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bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
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bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
|
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x710++0x1B
|
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line.long 0x0 "GPDMA_C13TR1,GPDMA channel 13 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
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bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
newline
|
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
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newline
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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|
line.long 0x4 "GPDMA_C13TR2,GPDMA channel 13 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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newline
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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newline
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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newline
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hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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line.long 0x8 "GPDMA_C13BR1,GPDMA channel 13 alternate block register 1"
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bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.."
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bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.."
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newline
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bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
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bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
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newline
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hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C13SAR,GPDMA channel 13 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C13DAR,GPDMA channel 13 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
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line.long 0x14 "GPDMA_C13TR3,GPDMA channel 13 transfer register 3"
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hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
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hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
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line.long 0x18 "GPDMA_C13BR2,GPDMA channel 13 block register 2"
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hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
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hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
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group.long 0x74C++0x7
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line.long 0x0 "GPDMA_C13LLR,GPDMA channel 13 alternate linked-list address register"
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bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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newline
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bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
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bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update"
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newline
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bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update"
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bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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newline
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
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line.long 0x4 "GPDMA_C14LBAR,GPDMA channel 14 linked-list base address register"
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
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wgroup.long 0x75C++0x3
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line.long 0x0 "GPDMA_C14FCR,GPDMA channel 14 flag clear register"
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bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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newline
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
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newline
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bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
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bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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newline
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
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rgroup.long 0x760++0x3
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line.long 0x0 "GPDMA_C14SR,GPDMA channel 14 status register"
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hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
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bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
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newline
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bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
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bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
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newline
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bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
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bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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newline
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bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
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bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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newline
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bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
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group.long 0x764++0x3
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line.long 0x0 "GPDMA_C14CR,GPDMA channel 14 control register"
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bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
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bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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newline
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
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|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
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group.long 0x790++0x1B
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line.long 0x0 "GPDMA_C14TR1,GPDMA channel 14 transfer register 1"
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bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
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newline
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bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
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hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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newline
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bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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newline
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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newline
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bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
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newline
|
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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line.long 0x4 "GPDMA_C14TR2,GPDMA channel 14 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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newline
|
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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newline
|
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hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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line.long 0x8 "GPDMA_C14BR1,GPDMA channel 14 alternate block register 1"
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bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.."
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bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.."
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newline
|
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bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
|
|
bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
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|
newline
|
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hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C14SAR,GPDMA channel 14 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C14DAR,GPDMA channel 14 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
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line.long 0x14 "GPDMA_C14TR3,GPDMA channel 14 transfer register 3"
|
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hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
|
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hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
|
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line.long 0x18 "GPDMA_C14BR2,GPDMA channel 14 block register 2"
|
|
hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
|
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hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
|
|
group.long 0x7CC++0x7
|
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line.long 0x0 "GPDMA_C14LLR,GPDMA channel 14 alternate linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
|
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
|
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
|
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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newline
|
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bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
|
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bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update"
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newline
|
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bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update"
|
|
bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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|
newline
|
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "GPDMA_C15LBAR,GPDMA channel 15 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of GPDMA channel x"
|
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wgroup.long 0x7DC++0x3
|
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line.long 0x0 "GPDMA_C15FCR,GPDMA channel 15 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x7E0++0x3
|
|
line.long 0x0 "GPDMA_C15SR,GPDMA channel 15 status register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: a half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x7E4++0x3
|
|
line.long 0x0 "GPDMA_C15CR,GPDMA channel 15 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x GPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x810++0x1B
|
|
line.long 0x0 "GPDMA_C15TR1,GPDMA channel 15 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no halfword-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
newline
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
newline
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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newline
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AHB) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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newline
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bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
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newline
|
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: user setting error reported and no transfer issued"
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line.long 0x4 "GPDMA_C15TR2,GPDMA channel 15 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when GPDMA_CxBR1.BNDT[15:0] =..,1: channel x (0 to 11) same as 00 channel x (x =12..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x (x =12..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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newline
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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newline
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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newline
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hexmask.long.byte 0x4 0.--6. 1. "REQSEL,GPDMA hardware request selection"
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line.long 0x8 "GPDMA_C15BR1,GPDMA channel 15 alternate block register 1"
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bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the GPDMA_CxDAR..,1: at the end of a block transfer the GPDMA_CxDAR.."
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bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the GPDMA_CxSAR..,1: at the end of a block transfer the GPDMA_CxSAR.."
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newline
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bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
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bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
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newline
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hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "GPDMA_C15SAR,GPDMA channel 15 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "GPDMA_C15DAR,GPDMA channel 15 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
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line.long 0x14 "GPDMA_C15TR3,GPDMA channel 15 transfer register 3"
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hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
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hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
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line.long 0x18 "GPDMA_C15BR2,GPDMA channel 15 block register 2"
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hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
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hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
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group.long 0x84C++0x3
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line.long 0x0 "GPDMA_C15LLR,GPDMA channel 15 alternate linked-list address register"
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bitfld.long 0x0 31. "UT1,Update GPDMA_CxTR1 from memory" "0: no GPDMA_CxTR1 update,1: GPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update GPDMA_CxTR2 from memory" "0: no GPDMA_CxTR2 update,1: GPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update GPDMA_CxBR1 from memory" "0: no GPDMA_CxBR1 update from memory..,1: GPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update GPDMA_CxSAR from memory" "0: no GPDMA_CxSAR update,1: GPDMA_CxSAR update"
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newline
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bitfld.long 0x0 27. "UDA,Update GPDMA_CxDAR register from memory" "0: no GPDMA_CxDAR update,1: GPDMA_CxDAR update"
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bitfld.long 0x0 26. "UT3,Update GPDMA_CxTR3 from memory" "0: no GPDMA_CxTR3 update,1: GPDMA_CxTR3 update"
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newline
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bitfld.long 0x0 25. "UB2,Update GPDMA_CxBR2 from memory" "0: no GPDMA_CxBR2 update,1: GPDMA_CxBR2 update"
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bitfld.long 0x0 16. "ULL,Update GPDMA_CxLLR register from memory" "0: no GPDMA_CxLLR update,1: GPDMA_CxLLR update"
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newline
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
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tree.end
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tree "GPIO (General Purpose Inputs/Outputs)"
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base ad:0x0
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tree "GPIOA"
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base ad:0x58020000
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group.long 0x0++0xF
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line.long 0x0 "GPIOA_MODER,GPIO port mode register"
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bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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line.long 0x4 "GPIOA_OTYPER,GPIO port output type register"
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bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
|
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bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
|
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bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
|
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bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register"
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bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
|
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
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bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register"
|
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bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
newline
|
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
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bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
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bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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|
newline
|
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bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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|
newline
|
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bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
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rgroup.long 0x10++0x3
|
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line.long 0x0 "GPIOA_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
|
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bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
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|
newline
|
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bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOA_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOA_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOA_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x58020400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOB_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOB_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOB_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOB_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOB_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOB_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
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|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOB_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOB_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOB_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOB_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x58020800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOC_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOC_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOC_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOC_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOC_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOC_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOC_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOC_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOC_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOC_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOD"
|
|
base ad:0x58020C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOD_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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line.long 0x4 "GPIOD_OTYPER,GPIO port output type register"
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bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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line.long 0x8 "GPIOD_OSPEEDR,GPIO port output speed register"
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bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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line.long 0xC "GPIOD_PUPDR,GPIO port pull-up/pull-down register"
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bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
|
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bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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rgroup.long 0x10++0x3
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line.long 0x0 "GPIOD_IDR,GPIO port input data register"
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bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
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newline
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bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
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newline
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bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
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newline
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bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
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group.long 0x14++0x3
|
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line.long 0x0 "GPIOD_ODR,GPIO port output data register"
|
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bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
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bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
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wgroup.long 0x18++0x3
|
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line.long 0x0 "GPIOD_BSRR,GPIO port bit set/reset register"
|
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bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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|
newline
|
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bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
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bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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|
newline
|
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bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
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bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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|
newline
|
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bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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|
newline
|
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bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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|
newline
|
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bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOD_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOD_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOD_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOD_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOE"
|
|
base ad:0x58021000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOE_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOE_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOE_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOE_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOE_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOE_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOE_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOE_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
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|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOE_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
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|
newline
|
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hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
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hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
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hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
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hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOE_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOE_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOF"
|
|
base ad:0x58021400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOF_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOF_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOF_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOF_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOF_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOF_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOF_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOF_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOF_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOF_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOG"
|
|
base ad:0x58021800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOG_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOG_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOG_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOG_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOG_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOG_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOG_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOG_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOG_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOG_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOG_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOH"
|
|
base ad:0x58021C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOH_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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|
newline
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bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
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|
line.long 0x4 "GPIOH_OTYPER,GPIO port output type register"
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|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
|
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bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
|
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bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
|
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bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
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line.long 0x8 "GPIOH_OSPEEDR,GPIO port output speed register"
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bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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newline
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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line.long 0xC "GPIOH_PUPDR,GPIO port pull-up/pull-down register"
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bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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newline
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bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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rgroup.long 0x10++0x3
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line.long 0x0 "GPIOH_IDR,GPIO port input data register"
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bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
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bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
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group.long 0x14++0x3
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line.long 0x0 "GPIOH_ODR,GPIO port output data register"
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bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
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newline
|
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bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
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bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
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wgroup.long 0x18++0x3
|
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line.long 0x0 "GPIOH_BSRR,GPIO port bit set/reset register"
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bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
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bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
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bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
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bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
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bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
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bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
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bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOH_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOH_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOH_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOH_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOM"
|
|
base ad:0x58023000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOM_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOM_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOM_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOM_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOM_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOM_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOM_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOM_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOM_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOM_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOM_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPION"
|
|
base ad:0x58023400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPION_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPION_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPION_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPION_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPION_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPION_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPION_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPION_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPION_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPION_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPION_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOO"
|
|
base ad:0x58023800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOO_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOO_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOO_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOO_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOO_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOO_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOO_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOO_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOO_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOO_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOO_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree "GPIOP"
|
|
base ad:0x58023C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOP_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
|
|
line.long 0x4 "GPIOP_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOP_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
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bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
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|
newline
|
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
newline
|
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very-high speed"
|
|
line.long 0xC "GPIOP_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
newline
|
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
newline
|
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bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
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|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOP_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
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|
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOP_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOP_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODy bit,1: Resets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODy bit,1: Sets the corresponding ODy bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOP_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOP_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
|
|
line.long 0x8 "GPIOP_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOP_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODy bit,1: Reset the corresponding ODy bit"
|
|
tree.end
|
|
tree.end
|
|
tree "HASH (HASH Hardware Accelerator)"
|
|
base ad:0x48020400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "HASH_CR,HASH control register"
|
|
hexmask.long.byte 0x0 17.--20. 1. "ALGO,Algorithm selection"
|
|
bitfld.long 0x0 16. "LKEY,Long key selection" "0: HMAC key is shorter or equal to the block size..,1: HMAC key is longer than the block size (long.."
|
|
newline
|
|
bitfld.long 0x0 13. "MDMAT,Multiple DMA transfers" "0: DCAL is automatically set at the end of a DMA..,1: DCAL is not automatically set at the end of a.."
|
|
rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed"
|
|
bitfld.long 0x0 6. "MODE,Mode selection" "0: Hash mode selected,1: HMAC mode selected. LKEY bit must be set if the.."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0: 32-bit data. The data written into HASH_DIN are..,1: 16-bit data or half-word. The data written into..,2: 8-bit data or bytes. The data written into..,3: bit data or bit string. The data written into.."
|
|
bitfld.long 0x0 3. "DMAE,DMA enable" "0: DMA transfers disabled,1: DMA transfers enabled. A DMA request is sent as.."
|
|
newline
|
|
bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "HASH_DIN,HASH data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DATAIN,Data input"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "HASH_STR,HASH start register"
|
|
bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word"
|
|
rgroup.long 0xC++0x13
|
|
line.long 0x0 "HASH_HRA0,HASH aliased digest register 0"
|
|
hexmask.long 0x0 0.--31. 1. "H0,Hash data x"
|
|
line.long 0x4 "HASH_HRA1,HASH aliased digest register 1"
|
|
hexmask.long 0x4 0.--31. 1. "H1,Hash data x"
|
|
line.long 0x8 "HASH_HRA2,HASH aliased digest register 2"
|
|
hexmask.long 0x8 0.--31. 1. "H2,Hash data x"
|
|
line.long 0xC "HASH_HRA3,HASH aliased digest register 3"
|
|
hexmask.long 0xC 0.--31. 1. "H3,Hash data x"
|
|
line.long 0x10 "HASH_HRA4,HASH aliased digest register 4"
|
|
hexmask.long 0x10 0.--31. 1. "H4,Hash data x"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "HASH_IMR,HASH interrupt enable register"
|
|
bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0: Digest calculation completion interrupt disabled,1: Digest calculation completion interrupt enabled."
|
|
bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0: Data input interrupt disabled,1: Data input interrupt enabled"
|
|
line.long 0x4 "HASH_SR,HASH status register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "NBWE,Number of words expected"
|
|
rbitfld.long 0x4 15. "DINNE,DIN not empty" "0: No data are present in the data input buffer,1: The input buffer contains at least one word of.."
|
|
newline
|
|
hexmask.long.byte 0x4 9.--13. 1. "NBWP,Number of words already pushed"
|
|
rbitfld.long 0x4 3. "BUSY,Busy bit" "0: No block is currently being processed,1: The hash core is processing a block of data"
|
|
newline
|
|
rbitfld.long 0x4 2. "DMAS,DMA Status" "0: DMA interface is disabled (DMAE = 0) and no..,1: DMA interface is enabled (DMAE = 1) or a.."
|
|
bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0: No digest available in the HASH_HRx registers..,1: Digest calculation complete a digest is.."
|
|
newline
|
|
bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0: Less than 16 locations are free in the input..,1: A new block can be entered into the input.."
|
|
group.long 0xF8++0x19B
|
|
line.long 0x0 "HASH_CSR0,HASH context swap register 0"
|
|
hexmask.long 0x0 0.--31. 1. "CS0,Context swap x"
|
|
line.long 0x4 "HASH_CSR1,HASH context swap register 1"
|
|
hexmask.long 0x4 0.--31. 1. "CS1,Context swap x"
|
|
line.long 0x8 "HASH_CSR2,HASH context swap register 2"
|
|
hexmask.long 0x8 0.--31. 1. "CS2,Context swap x"
|
|
line.long 0xC "HASH_CSR3,HASH context swap register 3"
|
|
hexmask.long 0xC 0.--31. 1. "CS3,Context swap x"
|
|
line.long 0x10 "HASH_CSR4,HASH context swap register 4"
|
|
hexmask.long 0x10 0.--31. 1. "CS4,Context swap x"
|
|
line.long 0x14 "HASH_CSR5,HASH context swap register 5"
|
|
hexmask.long 0x14 0.--31. 1. "CS5,Context swap x"
|
|
line.long 0x18 "HASH_CSR6,HASH context swap register 6"
|
|
hexmask.long 0x18 0.--31. 1. "CS6,Context swap x"
|
|
line.long 0x1C "HASH_CSR7,HASH context swap register 7"
|
|
hexmask.long 0x1C 0.--31. 1. "CS7,Context swap x"
|
|
line.long 0x20 "HASH_CSR8,HASH context swap register 8"
|
|
hexmask.long 0x20 0.--31. 1. "CS8,Context swap x"
|
|
line.long 0x24 "HASH_CSR9,HASH context swap register 9"
|
|
hexmask.long 0x24 0.--31. 1. "CS9,Context swap x"
|
|
line.long 0x28 "HASH_CSR10,HASH context swap register 10"
|
|
hexmask.long 0x28 0.--31. 1. "CS10,Context swap x"
|
|
line.long 0x2C "HASH_CSR11,HASH context swap register 11"
|
|
hexmask.long 0x2C 0.--31. 1. "CS11,Context swap x"
|
|
line.long 0x30 "HASH_CSR12,HASH context swap register 12"
|
|
hexmask.long 0x30 0.--31. 1. "CS12,Context swap x"
|
|
line.long 0x34 "HASH_CSR13,HASH context swap register 13"
|
|
hexmask.long 0x34 0.--31. 1. "CS13,Context swap x"
|
|
line.long 0x38 "HASH_CSR14,HASH context swap register 14"
|
|
hexmask.long 0x38 0.--31. 1. "CS14,Context swap x"
|
|
line.long 0x3C "HASH_CSR15,HASH context swap register 15"
|
|
hexmask.long 0x3C 0.--31. 1. "CS15,Context swap x"
|
|
line.long 0x40 "HASH_CSR16,HASH context swap register 16"
|
|
hexmask.long 0x40 0.--31. 1. "CS16,Context swap x"
|
|
line.long 0x44 "HASH_CSR17,HASH context swap register 17"
|
|
hexmask.long 0x44 0.--31. 1. "CS17,Context swap x"
|
|
line.long 0x48 "HASH_CSR18,HASH context swap register 18"
|
|
hexmask.long 0x48 0.--31. 1. "CS18,Context swap x"
|
|
line.long 0x4C "HASH_CSR19,HASH context swap register 19"
|
|
hexmask.long 0x4C 0.--31. 1. "CS19,Context swap x"
|
|
line.long 0x50 "HASH_CSR20,HASH context swap register 20"
|
|
hexmask.long 0x50 0.--31. 1. "CS20,Context swap x"
|
|
line.long 0x54 "HASH_CSR21,HASH context swap register 21"
|
|
hexmask.long 0x54 0.--31. 1. "CS21,Context swap x"
|
|
line.long 0x58 "HASH_CSR22,HASH context swap register 22"
|
|
hexmask.long 0x58 0.--31. 1. "CS22,Context swap x"
|
|
line.long 0x5C "HASH_CSR23,HASH context swap register 23"
|
|
hexmask.long 0x5C 0.--31. 1. "CS23,Context swap x"
|
|
line.long 0x60 "HASH_CSR24,HASH context swap register 24"
|
|
hexmask.long 0x60 0.--31. 1. "CS24,Context swap x"
|
|
line.long 0x64 "HASH_CSR25,HASH context swap register 25"
|
|
hexmask.long 0x64 0.--31. 1. "CS25,Context swap x"
|
|
line.long 0x68 "HASH_CSR26,HASH context swap register 26"
|
|
hexmask.long 0x68 0.--31. 1. "CS26,Context swap x"
|
|
line.long 0x6C "HASH_CSR27,HASH context swap register 27"
|
|
hexmask.long 0x6C 0.--31. 1. "CS27,Context swap x"
|
|
line.long 0x70 "HASH_CSR28,HASH context swap register 28"
|
|
hexmask.long 0x70 0.--31. 1. "CS28,Context swap x"
|
|
line.long 0x74 "HASH_CSR29,HASH context swap register 29"
|
|
hexmask.long 0x74 0.--31. 1. "CS29,Context swap x"
|
|
line.long 0x78 "HASH_CSR30,HASH context swap register 30"
|
|
hexmask.long 0x78 0.--31. 1. "CS30,Context swap x"
|
|
line.long 0x7C "HASH_CSR31,HASH context swap register 31"
|
|
hexmask.long 0x7C 0.--31. 1. "CS31,Context swap x"
|
|
line.long 0x80 "HASH_CSR32,HASH context swap register 32"
|
|
hexmask.long 0x80 0.--31. 1. "CS32,Context swap x"
|
|
line.long 0x84 "HASH_CSR33,HASH context swap register 33"
|
|
hexmask.long 0x84 0.--31. 1. "CS33,Context swap x"
|
|
line.long 0x88 "HASH_CSR34,HASH context swap register 34"
|
|
hexmask.long 0x88 0.--31. 1. "CS34,Context swap x"
|
|
line.long 0x8C "HASH_CSR35,HASH context swap register 35"
|
|
hexmask.long 0x8C 0.--31. 1. "CS35,Context swap x"
|
|
line.long 0x90 "HASH_CSR36,HASH context swap register 36"
|
|
hexmask.long 0x90 0.--31. 1. "CS36,Context swap x"
|
|
line.long 0x94 "HASH_CSR37,HASH context swap register 37"
|
|
hexmask.long 0x94 0.--31. 1. "CS37,Context swap x"
|
|
line.long 0x98 "HASH_CSR38,HASH context swap register 38"
|
|
hexmask.long 0x98 0.--31. 1. "CS38,Context swap x"
|
|
line.long 0x9C "HASH_CSR39,HASH context swap register 39"
|
|
hexmask.long 0x9C 0.--31. 1. "CS39,Context swap x"
|
|
line.long 0xA0 "HASH_CSR40,HASH context swap register 40"
|
|
hexmask.long 0xA0 0.--31. 1. "CS40,Context swap x"
|
|
line.long 0xA4 "HASH_CSR41,HASH context swap register 41"
|
|
hexmask.long 0xA4 0.--31. 1. "CS41,Context swap x"
|
|
line.long 0xA8 "HASH_CSR42,HASH context swap register 42"
|
|
hexmask.long 0xA8 0.--31. 1. "CS42,Context swap x"
|
|
line.long 0xAC "HASH_CSR43,HASH context swap register 43"
|
|
hexmask.long 0xAC 0.--31. 1. "CS43,Context swap x"
|
|
line.long 0xB0 "HASH_CSR44,HASH context swap register 44"
|
|
hexmask.long 0xB0 0.--31. 1. "CS44,Context swap x"
|
|
line.long 0xB4 "HASH_CSR45,HASH context swap register 45"
|
|
hexmask.long 0xB4 0.--31. 1. "CS45,Context swap x"
|
|
line.long 0xB8 "HASH_CSR46,HASH context swap register 46"
|
|
hexmask.long 0xB8 0.--31. 1. "CS46,Context swap x"
|
|
line.long 0xBC "HASH_CSR47,HASH context swap register 47"
|
|
hexmask.long 0xBC 0.--31. 1. "CS47,Context swap x"
|
|
line.long 0xC0 "HASH_CSR48,HASH context swap register 48"
|
|
hexmask.long 0xC0 0.--31. 1. "CS48,Context swap x"
|
|
line.long 0xC4 "HASH_CSR49,HASH context swap register 49"
|
|
hexmask.long 0xC4 0.--31. 1. "CS49,Context swap x"
|
|
line.long 0xC8 "HASH_CSR50,HASH context swap register 50"
|
|
hexmask.long 0xC8 0.--31. 1. "CS50,Context swap x"
|
|
line.long 0xCC "HASH_CSR51,HASH context swap register 51"
|
|
hexmask.long 0xCC 0.--31. 1. "CS51,Context swap x"
|
|
line.long 0xD0 "HASH_CSR52,HASH context swap register 52"
|
|
hexmask.long 0xD0 0.--31. 1. "CS52,Context swap x"
|
|
line.long 0xD4 "HASH_CSR53,HASH context swap register 53"
|
|
hexmask.long 0xD4 0.--31. 1. "CS53,Context swap x"
|
|
line.long 0xD8 "HASH_CSR54,HASH context swap register 54"
|
|
hexmask.long 0xD8 0.--31. 1. "CS54,Context swap x"
|
|
line.long 0xDC "HASH_CSR55,HASH context swap register 55"
|
|
hexmask.long 0xDC 0.--31. 1. "CS55,Context swap x"
|
|
line.long 0xE0 "HASH_CSR56,HASH context swap register 56"
|
|
hexmask.long 0xE0 0.--31. 1. "CS56,Context swap x"
|
|
line.long 0xE4 "HASH_CSR57,HASH context swap register 57"
|
|
hexmask.long 0xE4 0.--31. 1. "CS57,Context swap x"
|
|
line.long 0xE8 "HASH_CSR58,HASH context swap register 58"
|
|
hexmask.long 0xE8 0.--31. 1. "CS58,Context swap x"
|
|
line.long 0xEC "HASH_CSR59,HASH context swap register 59"
|
|
hexmask.long 0xEC 0.--31. 1. "CS59,Context swap x"
|
|
line.long 0xF0 "HASH_CSR60,HASH context swap register 60"
|
|
hexmask.long 0xF0 0.--31. 1. "CS60,Context swap x"
|
|
line.long 0xF4 "HASH_CSR61,HASH context swap register 61"
|
|
hexmask.long 0xF4 0.--31. 1. "CS61,Context swap x"
|
|
line.long 0xF8 "HASH_CSR62,HASH context swap register 62"
|
|
hexmask.long 0xF8 0.--31. 1. "CS62,Context swap x"
|
|
line.long 0xFC "HASH_CSR63,HASH context swap register 63"
|
|
hexmask.long 0xFC 0.--31. 1. "CS63,Context swap x"
|
|
line.long 0x100 "HASH_CSR64,HASH context swap register 64"
|
|
hexmask.long 0x100 0.--31. 1. "CS64,Context swap x"
|
|
line.long 0x104 "HASH_CSR65,HASH context swap register 65"
|
|
hexmask.long 0x104 0.--31. 1. "CS65,Context swap x"
|
|
line.long 0x108 "HASH_CSR66,HASH context swap register 66"
|
|
hexmask.long 0x108 0.--31. 1. "CS66,Context swap x"
|
|
line.long 0x10C "HASH_CSR67,HASH context swap register 67"
|
|
hexmask.long 0x10C 0.--31. 1. "CS67,Context swap x"
|
|
line.long 0x110 "HASH_CSR68,HASH context swap register 68"
|
|
hexmask.long 0x110 0.--31. 1. "CS68,Context swap x"
|
|
line.long 0x114 "HASH_CSR69,HASH context swap register 69"
|
|
hexmask.long 0x114 0.--31. 1. "CS69,Context swap x"
|
|
line.long 0x118 "HASH_CSR70,HASH context swap register 70"
|
|
hexmask.long 0x118 0.--31. 1. "CS70,Context swap x"
|
|
line.long 0x11C "HASH_CSR71,HASH context swap register 71"
|
|
hexmask.long 0x11C 0.--31. 1. "CS71,Context swap x"
|
|
line.long 0x120 "HASH_CSR72,HASH context swap register 72"
|
|
hexmask.long 0x120 0.--31. 1. "CS72,Context swap x"
|
|
line.long 0x124 "HASH_CSR73,HASH context swap register 73"
|
|
hexmask.long 0x124 0.--31. 1. "CS73,Context swap x"
|
|
line.long 0x128 "HASH_CSR74,HASH context swap register 74"
|
|
hexmask.long 0x128 0.--31. 1. "CS74,Context swap x"
|
|
line.long 0x12C "HASH_CSR75,HASH context swap register 75"
|
|
hexmask.long 0x12C 0.--31. 1. "CS75,Context swap x"
|
|
line.long 0x130 "HASH_CSR76,HASH context swap register 76"
|
|
hexmask.long 0x130 0.--31. 1. "CS76,Context swap x"
|
|
line.long 0x134 "HASH_CSR77,HASH context swap register 77"
|
|
hexmask.long 0x134 0.--31. 1. "CS77,Context swap x"
|
|
line.long 0x138 "HASH_CSR78,HASH context swap register 78"
|
|
hexmask.long 0x138 0.--31. 1. "CS78,Context swap x"
|
|
line.long 0x13C "HASH_CSR79,HASH context swap register 79"
|
|
hexmask.long 0x13C 0.--31. 1. "CS79,Context swap x"
|
|
line.long 0x140 "HASH_CSR80,HASH context swap register 80"
|
|
hexmask.long 0x140 0.--31. 1. "CS80,Context swap x"
|
|
line.long 0x144 "HASH_CSR81,HASH context swap register 81"
|
|
hexmask.long 0x144 0.--31. 1. "CS81,Context swap x"
|
|
line.long 0x148 "HASH_CSR82,HASH context swap register 82"
|
|
hexmask.long 0x148 0.--31. 1. "CS82,Context swap x"
|
|
line.long 0x14C "HASH_CSR83,HASH context swap register 83"
|
|
hexmask.long 0x14C 0.--31. 1. "CS83,Context swap x"
|
|
line.long 0x150 "HASH_CSR84,HASH context swap register 84"
|
|
hexmask.long 0x150 0.--31. 1. "CS84,Context swap x"
|
|
line.long 0x154 "HASH_CSR85,HASH context swap register 85"
|
|
hexmask.long 0x154 0.--31. 1. "CS85,Context swap x"
|
|
line.long 0x158 "HASH_CSR86,HASH context swap register 86"
|
|
hexmask.long 0x158 0.--31. 1. "CS86,Context swap x"
|
|
line.long 0x15C "HASH_CSR87,HASH context swap register 87"
|
|
hexmask.long 0x15C 0.--31. 1. "CS87,Context swap x"
|
|
line.long 0x160 "HASH_CSR88,HASH context swap register 88"
|
|
hexmask.long 0x160 0.--31. 1. "CS88,Context swap x"
|
|
line.long 0x164 "HASH_CSR89,HASH context swap register 89"
|
|
hexmask.long 0x164 0.--31. 1. "CS89,Context swap x"
|
|
line.long 0x168 "HASH_CSR90,HASH context swap register 90"
|
|
hexmask.long 0x168 0.--31. 1. "CS90,Context swap x"
|
|
line.long 0x16C "HASH_CSR91,HASH context swap register 91"
|
|
hexmask.long 0x16C 0.--31. 1. "CS91,Context swap x"
|
|
line.long 0x170 "HASH_CSR92,HASH context swap register 92"
|
|
hexmask.long 0x170 0.--31. 1. "CS92,Context swap x"
|
|
line.long 0x174 "HASH_CSR93,HASH context swap register 93"
|
|
hexmask.long 0x174 0.--31. 1. "CS93,Context swap x"
|
|
line.long 0x178 "HASH_CSR94,HASH context swap register 94"
|
|
hexmask.long 0x178 0.--31. 1. "CS94,Context swap x"
|
|
line.long 0x17C "HASH_CSR95,HASH context swap register 95"
|
|
hexmask.long 0x17C 0.--31. 1. "CS95,Context swap x"
|
|
line.long 0x180 "HASH_CSR96,HASH context swap register 96"
|
|
hexmask.long 0x180 0.--31. 1. "CS96,Context swap x"
|
|
line.long 0x184 "HASH_CSR97,HASH context swap register 97"
|
|
hexmask.long 0x184 0.--31. 1. "CS97,Context swap x"
|
|
line.long 0x188 "HASH_CSR98,HASH context swap register 98"
|
|
hexmask.long 0x188 0.--31. 1. "CS98,Context swap x"
|
|
line.long 0x18C "HASH_CSR99,HASH context swap register 99"
|
|
hexmask.long 0x18C 0.--31. 1. "CS99,Context swap x"
|
|
line.long 0x190 "HASH_CSR100,HASH context swap register 100"
|
|
hexmask.long 0x190 0.--31. 1. "CS100,Context swap x"
|
|
line.long 0x194 "HASH_CSR101,HASH context swap register 101"
|
|
hexmask.long 0x194 0.--31. 1. "CS101,Context swap x"
|
|
line.long 0x198 "HASH_CSR102,HASH context swap register 102"
|
|
hexmask.long 0x198 0.--31. 1. "CS102,Context swap x"
|
|
rgroup.long 0x310++0x3F
|
|
line.long 0x0 "HASH_HR0,HASH digest register 0"
|
|
hexmask.long 0x0 0.--31. 1. "H0,Hash data x"
|
|
line.long 0x4 "HASH_HR1,HASH digest register 1"
|
|
hexmask.long 0x4 0.--31. 1. "H1,Hash data x"
|
|
line.long 0x8 "HASH_HR2,HASH digest register 2"
|
|
hexmask.long 0x8 0.--31. 1. "H2,Hash data x"
|
|
line.long 0xC "HASH_HR3,HASH digest register 3"
|
|
hexmask.long 0xC 0.--31. 1. "H3,Hash data x"
|
|
line.long 0x10 "HASH_HR4,HASH digest register 4"
|
|
hexmask.long 0x10 0.--31. 1. "H4,Hash data x"
|
|
line.long 0x14 "HASH_HR5,HASH supplementary digest register 5"
|
|
hexmask.long 0x14 0.--31. 1. "H5,Hash data x"
|
|
line.long 0x18 "HASH_HR6,HASH supplementary digest register 6"
|
|
hexmask.long 0x18 0.--31. 1. "H6,Hash data x"
|
|
line.long 0x1C "HASH_HR7,HASH supplementary digest register 7"
|
|
hexmask.long 0x1C 0.--31. 1. "H7,Hash data x"
|
|
line.long 0x20 "HASH_HR8,HASH supplementary digest register 8"
|
|
hexmask.long 0x20 0.--31. 1. "H8,Hash data x"
|
|
line.long 0x24 "HASH_HR9,HASH supplementary digest register 9"
|
|
hexmask.long 0x24 0.--31. 1. "H9,Hash data x"
|
|
line.long 0x28 "HASH_HR10,HASH supplementary digest register 10"
|
|
hexmask.long 0x28 0.--31. 1. "H10,Hash data x"
|
|
line.long 0x2C "HASH_HR11,HASH supplementary digest register 11"
|
|
hexmask.long 0x2C 0.--31. 1. "H11,Hash data x"
|
|
line.long 0x30 "HASH_HR12,HASH supplementary digest register 12"
|
|
hexmask.long 0x30 0.--31. 1. "H12,Hash data x"
|
|
line.long 0x34 "HASH_HR13,HASH supplementary digest register 13"
|
|
hexmask.long 0x34 0.--31. 1. "H13,Hash data x"
|
|
line.long 0x38 "HASH_HR14,HASH supplementary digest register 14"
|
|
hexmask.long 0x38 0.--31. 1. "H14,Hash data x"
|
|
line.long 0x3C "HASH_HR15,HASH supplementary digest register 15"
|
|
hexmask.long 0x3C 0.--31. 1. "H15,Hash data x"
|
|
tree.end
|
|
tree "HPDMA (High-Performance Direct Memory Access Controller)"
|
|
base ad:0x52000000
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "HPDMA_PRIVCFGR,HPDMA privileged configuration register"
|
|
bitfld.long 0x0 15. "PRIV15,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 14. "PRIV14,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 13. "PRIV13,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 12. "PRIV12,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 11. "PRIV11,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 10. "PRIV10,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 9. "PRIV9,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 8. "PRIV8,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 7. "PRIV7,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 6. "PRIV6,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 5. "PRIV5,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 4. "PRIV4,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 3. "PRIV3,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 2. "PRIV2,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
newline
|
|
bitfld.long 0x0 1. "PRIV1,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
bitfld.long 0x0 0. "PRIV0,privileged state of channel x" "0: unprivileged,1: privileged"
|
|
line.long 0x4 "HPDMA_RCFGLOCKR,HPDMA configuration lock register"
|
|
bitfld.long 0x4 15. "LOCK15,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 14. "LOCK14,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 13. "LOCK13,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 12. "LOCK12,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 11. "LOCK11,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 10. "LOCK10,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 9. "LOCK9,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 8. "LOCK8,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 7. "LOCK7,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 6. "LOCK6,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK5,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 4. "LOCK4,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK3,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 2. "LOCK2,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK1,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
bitfld.long 0x4 0. "LOCK0,lock the configuration of HPDMA_PRIVCFGR.PRIVx until a global HPDMA reset" "0: privilege configuration of the channel x is..,1: privilege configuration of the channel x is not.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "HPDMA_MISR,HPDMA masked interrupt status register"
|
|
bitfld.long 0x0 15. "MIS15,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 14. "MIS14,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 13. "MIS13,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 12. "MIS12,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 11. "MIS11,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 10. "MIS10,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 9. "MIS9,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 8. "MIS8,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 7. "MIS7,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 6. "MIS6,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS5,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 4. "MIS4,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS3,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 2. "MIS2,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
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|
newline
|
|
bitfld.long 0x0 1. "MIS1,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
bitfld.long 0x0 0. "MIS0,masked interrupt status of channel x" "0: no interrupt occurred on channel x,1: an interrupt occurred on channel x"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "HPDMA_C0LBAR,HPDMA channel 0 linked-list base address register"
|
|
hexmask.long.word 0x0 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "HPDMA_C0FCR,HPDMA channel 0 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "HPDMA_C0SR,HPDMA channel 0 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "HPDMA_C0CR,HPDMA channel 0 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x90++0x13
|
|
line.long 0x0 "HPDMA_C0TR1,HPDMA channel 0 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C0TR2,HPDMA channel 0 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C0BR1,HPDMA channel 0 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C0SAR,HPDMA channel 0 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C0DAR,HPDMA channel 0 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "HPDMA_C0LLR,HPDMA channel 0 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C1LBAR,HPDMA channel 1 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0xDC++0x3
|
|
line.long 0x0 "HPDMA_C1FCR,HPDMA channel 1 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0xE0++0x3
|
|
line.long 0x0 "HPDMA_C1SR,HPDMA channel 1 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "HPDMA_C1CR,HPDMA channel 1 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x110++0x13
|
|
line.long 0x0 "HPDMA_C1TR1,HPDMA channel 1 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C1TR2,HPDMA channel 1 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C1BR1,HPDMA channel 1 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C1SAR,HPDMA channel 1 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C1DAR,HPDMA channel 1 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x14C++0x7
|
|
line.long 0x0 "HPDMA_C1LLR,HPDMA channel 1 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C2LBAR,HPDMA channel 2 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x15C++0x3
|
|
line.long 0x0 "HPDMA_C2FCR,HPDMA channel 2 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x160++0x3
|
|
line.long 0x0 "HPDMA_C2SR,HPDMA channel 2 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "HPDMA_C2CR,HPDMA channel 2 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x190++0x13
|
|
line.long 0x0 "HPDMA_C2TR1,HPDMA channel 2 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C2TR2,HPDMA channel 2 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C2BR1,HPDMA channel 2 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C2SAR,HPDMA channel 2 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C2DAR,HPDMA channel 2 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x1CC++0x7
|
|
line.long 0x0 "HPDMA_C2LLR,HPDMA channel 2 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C3LBAR,HPDMA channel 3 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x1DC++0x3
|
|
line.long 0x0 "HPDMA_C3FCR,HPDMA channel 3 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x1E0++0x3
|
|
line.long 0x0 "HPDMA_C3SR,HPDMA channel 3 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "HPDMA_C3CR,HPDMA channel 3 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x210++0x13
|
|
line.long 0x0 "HPDMA_C3TR1,HPDMA channel 3 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
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|
newline
|
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
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|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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|
newline
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bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
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|
line.long 0x4 "HPDMA_C3TR2,HPDMA channel 3 transfer register 2"
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|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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|
newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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|
newline
|
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
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|
line.long 0x8 "HPDMA_C3BR1,HPDMA channel 3 block register 1"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "HPDMA_C3SAR,HPDMA channel 3 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
|
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line.long 0x10 "HPDMA_C3DAR,HPDMA channel 3 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
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group.long 0x24C++0x7
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line.long 0x0 "HPDMA_C3LLR,HPDMA channel 3 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
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newline
|
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bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
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|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
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|
newline
|
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bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
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bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
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newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C4LBAR,HPDMA channel 4 linked-list base address register"
|
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
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wgroup.long 0x25C++0x3
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line.long 0x0 "HPDMA_C4FCR,HPDMA channel 4 flag clear register"
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|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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|
newline
|
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
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|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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|
newline
|
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x260++0x3
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line.long 0x0 "HPDMA_C4SR,HPDMA channel 4 status register"
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|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
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|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
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|
newline
|
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bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
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|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
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newline
|
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bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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|
newline
|
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bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x264++0x3
|
|
line.long 0x0 "HPDMA_C4CR,HPDMA channel 4 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
|
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
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group.long 0x290++0x13
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line.long 0x0 "HPDMA_C4TR1,HPDMA channel 4 transfer register 1"
|
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bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
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hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
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hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C4TR2,HPDMA channel 4 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C4BR1,HPDMA channel 4 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C4SAR,HPDMA channel 4 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C4DAR,HPDMA channel 4 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x2CC++0x7
|
|
line.long 0x0 "HPDMA_C4LLR,HPDMA channel 4 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C5LBAR,HPDMA channel 5 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x2DC++0x3
|
|
line.long 0x0 "HPDMA_C5FCR,HPDMA channel 5 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x2E0++0x3
|
|
line.long 0x0 "HPDMA_C5SR,HPDMA channel 5 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "HPDMA_C5CR,HPDMA channel 5 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x310++0x13
|
|
line.long 0x0 "HPDMA_C5TR1,HPDMA channel 5 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C5TR2,HPDMA channel 5 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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|
newline
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
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|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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|
newline
|
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hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
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line.long 0x8 "HPDMA_C5BR1,HPDMA channel 5 block register 1"
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hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "HPDMA_C5SAR,HPDMA channel 5 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
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line.long 0x10 "HPDMA_C5DAR,HPDMA channel 5 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
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group.long 0x34C++0x7
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line.long 0x0 "HPDMA_C5LLR,HPDMA channel 5 linked-list address register"
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|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
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newline
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bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
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bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
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newline
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hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
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line.long 0x4 "HPDMA_C6LBAR,HPDMA channel 6 linked-list base address register"
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hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
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wgroup.long 0x35C++0x3
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line.long 0x0 "HPDMA_C6FCR,HPDMA channel 6 flag clear register"
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bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
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bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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newline
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bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
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|
newline
|
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bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
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|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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newline
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
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rgroup.long 0x360++0x3
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line.long 0x0 "HPDMA_C6SR,HPDMA channel 6 status register"
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hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
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bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
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newline
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bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
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bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
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newline
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bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
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bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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newline
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bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
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bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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newline
|
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bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
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group.long 0x364++0x3
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line.long 0x0 "HPDMA_C6CR,HPDMA channel 6 control register"
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bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
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bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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newline
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
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bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
|
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bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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newline
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
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group.long 0x390++0x13
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line.long 0x0 "HPDMA_C6TR1,HPDMA channel 6 transfer register 1"
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bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
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|
newline
|
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
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|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
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newline
|
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hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
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bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
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bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
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bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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newline
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hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
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bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
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line.long 0x4 "HPDMA_C6TR2,HPDMA channel 6 transfer register 2"
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bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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|
newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
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|
newline
|
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
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|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
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line.long 0x8 "HPDMA_C6BR1,HPDMA channel 6 block register 1"
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|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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line.long 0xC "HPDMA_C6SAR,HPDMA channel 6 source address register"
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hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C6DAR,HPDMA channel 6 destination address register"
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x3CC++0x7
|
|
line.long 0x0 "HPDMA_C6LLR,HPDMA channel 6 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
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newline
|
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bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
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bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
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newline
|
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bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
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|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C7LBAR,HPDMA channel 7 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x3DC++0x3
|
|
line.long 0x0 "HPDMA_C7FCR,HPDMA channel 7 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x3E0++0x3
|
|
line.long 0x0 "HPDMA_C7SR,HPDMA channel 7 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x3E4++0x3
|
|
line.long 0x0 "HPDMA_C7CR,HPDMA channel 7 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x410++0x13
|
|
line.long 0x0 "HPDMA_C7TR1,HPDMA channel 7 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C7TR2,HPDMA channel 7 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C7BR1,HPDMA channel 7 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C7SAR,HPDMA channel 7 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C7DAR,HPDMA channel 7 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "HPDMA_C7LLR,HPDMA channel 7 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
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|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
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|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C8LBAR,HPDMA channel 8 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x45C++0x3
|
|
line.long 0x0 "HPDMA_C8FCR,HPDMA channel 8 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
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|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x460++0x3
|
|
line.long 0x0 "HPDMA_C8SR,HPDMA channel 8 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x464++0x3
|
|
line.long 0x0 "HPDMA_C8CR,HPDMA channel 8 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
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bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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newline
|
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x490++0x13
|
|
line.long 0x0 "HPDMA_C8TR1,HPDMA channel 8 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C8TR2,HPDMA channel 8 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C8BR1,HPDMA channel 8 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
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|
line.long 0xC "HPDMA_C8SAR,HPDMA channel 8 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C8DAR,HPDMA channel 8 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x4CC++0x7
|
|
line.long 0x0 "HPDMA_C8LLR,HPDMA channel 8 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
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|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C9LBAR,HPDMA channel 9 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x4DC++0x3
|
|
line.long 0x0 "HPDMA_C9FCR,HPDMA channel 9 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x4E0++0x3
|
|
line.long 0x0 "HPDMA_C9SR,HPDMA channel 9 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "HPDMA_C9CR,HPDMA channel 9 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x510++0x13
|
|
line.long 0x0 "HPDMA_C9TR1,HPDMA channel 9 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C9TR2,HPDMA channel 9 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C9BR1,HPDMA channel 9 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C9SAR,HPDMA channel 9 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C9DAR,HPDMA channel 9 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x54C++0x7
|
|
line.long 0x0 "HPDMA_C9LLR,HPDMA channel 9 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C10LBAR,HPDMA channel 10 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x55C++0x3
|
|
line.long 0x0 "HPDMA_C10FCR,HPDMA channel 10 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x560++0x3
|
|
line.long 0x0 "HPDMA_C10SR,HPDMA channel 10 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x564++0x3
|
|
line.long 0x0 "HPDMA_C10CR,HPDMA channel 10 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x590++0x13
|
|
line.long 0x0 "HPDMA_C10TR1,HPDMA channel 10 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C10TR2,HPDMA channel 10 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C10BR1,HPDMA channel 10 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C10SAR,HPDMA channel 10 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C10DAR,HPDMA channel 10 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x5CC++0x7
|
|
line.long 0x0 "HPDMA_C10LLR,HPDMA channel 10 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C11LBAR,HPDMA channel 11 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x5DC++0x3
|
|
line.long 0x0 "HPDMA_C11FCR,HPDMA channel 11 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x5E0++0x3
|
|
line.long 0x0 "HPDMA_C11SR,HPDMA channel 11 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x5E4++0x3
|
|
line.long 0x0 "HPDMA_C11CR,HPDMA channel 11 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x610++0x13
|
|
line.long 0x0 "HPDMA_C11TR1,HPDMA channel 11 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C11TR2,HPDMA channel 11 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C11BR1,HPDMA channel 11 block register 1"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C11SAR,HPDMA channel 11 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C11DAR,HPDMA channel 11 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
group.long 0x64C++0x7
|
|
line.long 0x0 "HPDMA_C11LLR,HPDMA channel 11 linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C12LBAR,HPDMA channel 12 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x65C++0x3
|
|
line.long 0x0 "HPDMA_C12FCR,HPDMA channel 12 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "HPDMA_C12SR,HPDMA channel 12 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x664++0x3
|
|
line.long 0x0 "HPDMA_C12CR,HPDMA channel 12 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
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bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
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bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
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bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x690++0x1B
|
|
line.long 0x0 "HPDMA_C12TR1,HPDMA channel 12 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
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bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
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|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
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bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
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|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C12TR2,HPDMA channel 12 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
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|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
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|
newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
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|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
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bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
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bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
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hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
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|
line.long 0x8 "HPDMA_C12BR1,HPDMA channel 12 alternate block register 1"
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|
bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.."
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bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.."
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|
newline
|
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bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
|
|
bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C12SAR,HPDMA channel 12 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
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line.long 0x10 "HPDMA_C12DAR,HPDMA channel 12 destination address register"
|
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hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
line.long 0x14 "HPDMA_C12TR3,HPDMA channel 12 transfer register 3"
|
|
hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
|
|
hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
|
|
line.long 0x18 "HPDMA_C12BR2,HPDMA channel 12 block register 2"
|
|
hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
|
|
hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
|
|
group.long 0x6CC++0x7
|
|
line.long 0x0 "HPDMA_C12LLR,HPDMA channel 12 alternate linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
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bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
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newline
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bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update"
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|
newline
|
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bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
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|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C13LBAR,HPDMA channel 13 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x6DC++0x3
|
|
line.long 0x0 "HPDMA_C13FCR,HPDMA channel 13 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
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|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
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|
newline
|
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bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x6E0++0x3
|
|
line.long 0x0 "HPDMA_C13SR,HPDMA channel 13 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
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|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
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|
newline
|
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bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x6E4++0x3
|
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line.long 0x0 "HPDMA_C13CR,HPDMA channel 13 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x710++0x1B
|
|
line.long 0x0 "HPDMA_C13TR1,HPDMA channel 13 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C13TR2,HPDMA channel 13 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C13BR1,HPDMA channel 13 alternate block register 1"
|
|
bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.."
|
|
bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.."
|
|
newline
|
|
bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
|
|
bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C13SAR,HPDMA channel 13 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C13DAR,HPDMA channel 13 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
line.long 0x14 "HPDMA_C13TR3,HPDMA channel 13 transfer register 3"
|
|
hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
|
|
hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
|
|
line.long 0x18 "HPDMA_C13BR2,HPDMA channel 13 block register 2"
|
|
hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
|
|
hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
|
|
group.long 0x74C++0x7
|
|
line.long 0x0 "HPDMA_C13LLR,HPDMA channel 13 alternate linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update"
|
|
newline
|
|
bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C14LBAR,HPDMA channel 14 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x75C++0x3
|
|
line.long 0x0 "HPDMA_C14FCR,HPDMA channel 14 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x760++0x3
|
|
line.long 0x0 "HPDMA_C14SR,HPDMA channel 14 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x764++0x3
|
|
line.long 0x0 "HPDMA_C14CR,HPDMA channel 14 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
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|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
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|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
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|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x790++0x1B
|
|
line.long 0x0 "HPDMA_C14TR1,HPDMA channel 14 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
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|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
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|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
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|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C14TR2,HPDMA channel 14 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
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|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C14BR1,HPDMA channel 14 alternate block register 1"
|
|
bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.."
|
|
bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.."
|
|
newline
|
|
bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
|
|
bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C14SAR,HPDMA channel 14 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C14DAR,HPDMA channel 14 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
line.long 0x14 "HPDMA_C14TR3,HPDMA channel 14 transfer register 3"
|
|
hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
|
|
hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
|
|
line.long 0x18 "HPDMA_C14BR2,HPDMA channel 14 block register 2"
|
|
hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
|
|
hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
|
|
group.long 0x7CC++0x7
|
|
line.long 0x0 "HPDMA_C14LLR,HPDMA channel 14 alternate linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
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|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update"
|
|
newline
|
|
bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
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|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
line.long 0x4 "HPDMA_C15LBAR,HPDMA channel 15 linked-list base address register"
|
|
hexmask.long.word 0x4 16.--31. 1. "LBA,linked-list base address of HPDMA channel x"
|
|
wgroup.long 0x7DC++0x3
|
|
line.long 0x0 "HPDMA_C15FCR,HPDMA channel 15 flag clear register"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag clear" "0: no effect,1: corresponding TOF flag cleared"
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag clear" "0: no effect,1: corresponding SUSPF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 12. "USEF,user setting error flag clear" "0: no effect,1: corresponding USEF flag cleared"
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag clear" "0: no effect,1: corresponding ULEF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag clear" "0: no effect,1: corresponding DTEF flag cleared"
|
|
bitfld.long 0x0 9. "HTF,half transfer flag clear" "0: no effect,1: corresponding HTF flag cleared"
|
|
newline
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag clear" "0: no effect,1: corresponding TCF flag cleared"
|
|
rgroup.long 0x7E0++0x3
|
|
line.long 0x0 "HPDMA_C15SR,HPDMA channel 15 status register"
|
|
hexmask.long.word 0x0 16.--24. 1. "FIFOL,monitored FIFO level"
|
|
bitfld.long 0x0 14. "TOF,trigger overrun flag" "0: no trigger overrun event,1: a trigger overrun event occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPF,completed suspension flag" "0: no completed suspension event,1: a completed suspension event occurred"
|
|
bitfld.long 0x0 12. "USEF,user setting error flag" "0: no user setting error event,1: a user setting error event occurred"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEF,update link transfer error flag" "0: no update link transfer error event,1: a master bus error event occurred while updating.."
|
|
bitfld.long 0x0 10. "DTEF,data transfer error flag" "0: no data transfer error event,1: a master bus error event occurred on a data.."
|
|
newline
|
|
bitfld.long 0x0 9. "HTF,half transfer flag" "0: no half transfer event,1: an half transfer event occurred"
|
|
bitfld.long 0x0 8. "TCF,transfer complete flag" "0: no transfer complete event,1: a transfer complete event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "IDLEF,idle flag" "0: channel not in idle state,1: channel in idle state"
|
|
group.long 0x7E4++0x3
|
|
line.long 0x0 "HPDMA_C15CR,HPDMA channel 15 control register"
|
|
bitfld.long 0x0 22.--23. "PRIO,priority level of the channel x HPDMA transfer versus others" "0: low priority low weight,1: low priority mid weight,2: low priority high weight,3: high priority"
|
|
bitfld.long 0x0 17. "LAP,linked-list allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 16. "LSM,Link step mode" "0: channel executed for the full linked-list and..,1: channel executed once for the current LLI"
|
|
bitfld.long 0x0 14. "TOIE,trigger overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "SUSPIE,completed suspension interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 12. "USEIE,user setting error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "ULEIE,update link transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 10. "DTEIE,data transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "HTIE,half transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 8. "TCIE,transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "SUSP,suspend" "0: write: resume channel read: channel not suspended,1: write: suspend channel read: channel suspended."
|
|
bitfld.long 0x0 1. "RESET,reset" "0: no channel reset,1: channel reset"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: write: ignored read: channel disabled,1: write: enable channel read: channel enabled"
|
|
group.long 0x810++0x1B
|
|
line.long 0x0 "HPDMA_C15TR1,HPDMA channel 15 transfer register 1"
|
|
bitfld.long 0x0 30. "DAP,destination allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
bitfld.long 0x0 28. "DWX,destination word exchange" "0: no word-based exchanged within double-word,1: the two consecutive (post PAM) words are.."
|
|
newline
|
|
bitfld.long 0x0 27. "DHX,destination half-word exchange" "0: no half-word-based exchanged within word,1: the two consecutive (post PAM) half-words are.."
|
|
bitfld.long 0x0 26. "DBX,destination byte exchange" "0: no byte-based exchange within half-word,1: the two consecutive (post PAM) bytes are.."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--25. 1. "DBL_1,destination burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 19. "DINC,destination incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "DDW_LOG2,binary logarithm of the destination data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If DAP = 0 (AXI) double-word (8 bytes)"
|
|
bitfld.long 0x0 14. "SAP,source allocated port" "0: port 0 (AXI) allocated,1: port 1 (AHB) allocated"
|
|
newline
|
|
bitfld.long 0x0 13. "SBX,source byte exchange within the unaligned half-word of each source word" "0: no byte-based exchange within the unaligned..,1: the two consecutive bytes within the unaligned.."
|
|
bitfld.long 0x0 11.--12. "PAM,padding/alignment mode" "0: source data is transferred as right aligned..,1: source data is transferred as right aligned sign..,2: successive source data are FIFO queued and..,3: successive source data are FIFO queued and.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--9. 1. "SBL_1,source burst length minus 1 between 0 and 63"
|
|
bitfld.long 0x0 3. "SINC,source incrementing burst" "0: fixed burst,1: contiguously incremented burst"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SDW_LOG2,binary logarithm of the source data width of a burst in bytes" "0: byte,1: half-word (2 bytes),2: word (4 bytes),3: If SAP = 0 (AXI) double-word (8 bytes)"
|
|
line.long 0x4 "HPDMA_C15TR2,HPDMA channel 15 transfer register 2"
|
|
bitfld.long 0x4 30.--31. "TCEM,transfer complete event mode" "0: at block level (when HPDMA_CxBR1.BNDT[15:0] =..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at LLI level: the complete transfer event is..,3: at channel level: the complete transfer event is.."
|
|
bitfld.long 0x4 24.--25. "TRIGPOL,trigger event polarity" "0: no trigger (masked trigger event),1: trigger on the rising edge,2: trigger on the falling edge,3: same as 00"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TRIGSEL,trigger event input selection"
|
|
bitfld.long 0x4 14.--15. "TRIGM,trigger mode" "0: at block level: the first burst read of each..,1: channel x = 0 to 11 same as 00; channel x=12 to..,2: at link level: a LLI link transfer is..,3: at programmed burst level: If SWREQ = 1 each.."
|
|
newline
|
|
bitfld.long 0x4 12. "PFREQ,Hardware request in peripheral flow control mode" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
bitfld.long 0x4 11. "BREQ,Block hardware request" "0: the selected hardware request is driven by a..,1: the selected hardware request is driven by a.."
|
|
newline
|
|
bitfld.long 0x4 10. "DREQ,destination hardware request" "0: selected hardware request driven by a source..,1: selected hardware request driven by a.."
|
|
bitfld.long 0x4 9. "SWREQ,software request" "0: no software request. The selected hardware..,1: software request for a memory-to-memory.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSEL,hardware request selection"
|
|
line.long 0x8 "HPDMA_C15BR1,HPDMA channel 15 alternate block register 1"
|
|
bitfld.long 0x8 31. "BRDDEC,Block repeat destination address decrement" "0: at the end of a block transfer the HPDMA_CxDAR..,1: at the end of a block transfer the HPDMA_CxDAR.."
|
|
bitfld.long 0x8 30. "BRSDEC,Block repeat source address decrement" "0: at the end of a block transfer the HPDMA_CxSAR..,1: at the end of a block transfer the HPDMA_CxSAR.."
|
|
newline
|
|
bitfld.long 0x8 29. "DDEC,destination address decrement" "0: At the end of a programmed burst transfer to the..,1: At the end of a programmed burst transfer to the.."
|
|
bitfld.long 0x8 28. "SDEC,source address decrement" "0: At the end of a programmed burst transfer from..,1: At the end of a programmed burst transfer from.."
|
|
newline
|
|
hexmask.long.word 0x8 16.--26. 1. "BRC,Block repeat counter"
|
|
hexmask.long.word 0x8 0.--15. 1. "BNDT,block number of data bytes to transfer from the source"
|
|
line.long 0xC "HPDMA_C15SAR,HPDMA channel 15 source address register"
|
|
hexmask.long 0xC 0.--31. 1. "SA,source address"
|
|
line.long 0x10 "HPDMA_C15DAR,HPDMA channel 15 destination address register"
|
|
hexmask.long 0x10 0.--31. 1. "DA,destination address"
|
|
line.long 0x14 "HPDMA_C15TR3,HPDMA channel 15 transfer register 3"
|
|
hexmask.long.word 0x14 16.--28. 1. "DAO,destination address offset increment"
|
|
hexmask.long.word 0x14 0.--12. 1. "SAO,source address offset increment"
|
|
line.long 0x18 "HPDMA_C15BR2,HPDMA channel 15 block register 2"
|
|
hexmask.long.word 0x18 16.--31. 1. "BRDAO,Block repeated destination address offset"
|
|
hexmask.long.word 0x18 0.--15. 1. "BRSAO,Block repeated source address offset"
|
|
group.long 0x84C++0x3
|
|
line.long 0x0 "HPDMA_C15LLR,HPDMA channel 15 alternate linked-list address register"
|
|
bitfld.long 0x0 31. "UT1,Update HPDMA_CxTR1 from memory" "0: no HPDMA_CxTR1 update,1: HPDMA_CxTR1 update"
|
|
bitfld.long 0x0 30. "UT2,Update HPDMA_CxTR2 from memory" "0: no HPDMA_CxTR2 update,1: HPDMA_CxTR2 update"
|
|
newline
|
|
bitfld.long 0x0 29. "UB1,Update HPDMA_CxBR1 from memory" "0: no HPDMA_CxBR1 update from memory..,1: HPDMA_CxBR1 update"
|
|
bitfld.long 0x0 28. "USA,update HPDMA_CxSAR from memory" "0: no HPDMA_CxSAR update,1: HPDMA_CxSAR update"
|
|
newline
|
|
bitfld.long 0x0 27. "UDA,Update HPDMA_CxDAR register from memory" "0: no HPDMA_CxDAR update,1: HPDMA_CxDAR update"
|
|
bitfld.long 0x0 26. "UT3,Update HPDMA_CxTR3 from memory" "0: no HPDMA_CxTR3 update,1: HPDMA_CxTR3 update"
|
|
newline
|
|
bitfld.long 0x0 25. "UB2,Update HPDMA_CxBR2 from memory" "0: no HPDMA_CxBR2 update,1: HPDMA_CxBR2 update"
|
|
bitfld.long 0x0 16. "ULL,Update HPDMA_CxLLR register from memory" "0: no HPDMA_CxLLR update,1: HPDMA_CxLLR update"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "LA,pointer (16-bit low-significant address) to the next linked-list data structure"
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit Interface)"
|
|
base ad:0x0
|
|
tree "I2C1_I3C1 (Inter-integrated circuit)"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.."
|
|
bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.."
|
|
newline
|
|
bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
newline
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
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line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.."
|
|
bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.."
|
|
newline
|
|
bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
newline
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware and cleared by..,1: STOPF flag remains cleared by hardware. This.."
|
|
bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware and cleared by..,1: ADDR flag remains cleared by hardware. This mode.."
|
|
newline
|
|
bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
newline
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree.end
|
|
tree "ICACHE (Texture Cache)"
|
|
base ad:0x52015000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ICACHE_CR,ICACHE control register"
|
|
bitfld.long 0x0 19. "MISSMRST,miss monitor reset" "0: no effect,1: reset cache miss monitor"
|
|
bitfld.long 0x0 18. "HITMRST,hit monitor reset" "0: no effect,1: reset cache hit monitor"
|
|
newline
|
|
bitfld.long 0x0 17. "MISSMEN,miss monitor enable" "0: cache miss monitor switched off. Stopping the..,1: cache miss monitor enabled"
|
|
bitfld.long 0x0 16. "HITMEN,hit monitor enable" "0: cache hit monitor switched off. Stopping the..,1: cache hit monitor enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "WAYSEL,cache associativity mode selection" "0: direct mapped cache (1-way cache),1: n-way set associative cache (reset value)"
|
|
bitfld.long 0x0 1. "CACHEINV,cache invalidation" "0: no effect,1: invalidate entire cache (all cache lines valid.."
|
|
newline
|
|
bitfld.long 0x0 0. "EN,enable" "0: cache disabled,1: cache enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ICACHE_SR,ICACHE status register"
|
|
bitfld.long 0x0 2. "ERRF,cache error flag" "0: no error,1: an error occurred during the operation.."
|
|
bitfld.long 0x0 1. "BSYENDF,busy end flag" "0: cache busy,1: full invalidate CACHEINV operation finished"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSYF,busy flag" "0: cache not busy on a CACHEINV operation,1: cache executing a full invalidate CACHEINV.."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ICACHE_IER,ICACHE interrupt enable register"
|
|
bitfld.long 0x0 2. "ERRIE,interrupt enable on cache error" "0: interrupt disabled on error,1: interrupt enabled on error"
|
|
bitfld.long 0x0 1. "BSYENDIE,interrupt enable on busy end" "0: interrupt disabled on busy end,1: interrupt enabled on busy end"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "ICACHE_FCR,ICACHE flag clear register"
|
|
bitfld.long 0x0 2. "CERRF,clear cache error flag" "0: no effect,1: clears ERRF flag in ICACHE_SR"
|
|
bitfld.long 0x0 1. "CBSYENDF,clear busy end flag" "0: no effect,1: clears BSYENDF flag in ICACHE_SR."
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "ICACHE_HMONR,ICACHE hit monitor register"
|
|
hexmask.long 0x0 0.--31. 1. "HITMON,cache hit monitor counter"
|
|
line.long 0x4 "ICACHE_MMONR,ICACHE miss monitor register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MISSMON,cache miss monitor counter"
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x58004800
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,IWDG key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,IWDG prescaler register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider"
|
|
line.long 0x4 "IWDG_RLR,IWDG reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,IWDG status register"
|
|
bitfld.long 0x0 14. "EWIF,Watchdog early interrupt flag" "0,1"
|
|
bitfld.long 0x0 8. "ONF,Watchdog enable status bit" "0: The IWDG is not activated,1: The IWDG is activated and needs to be refreshed.."
|
|
bitfld.long 0x0 3. "EWU,Watchdog interrupt comparator value update" "0,1"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "IWDG_WINR,IWDG window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value"
|
|
line.long 0x4 "IWDG_EWCR,IWDG early wake-up interrupt register"
|
|
bitfld.long 0x4 15. "EWIE,Watchdog early interrupt enable" "0: The early interrupt interface is disabled.,1: The early interrupt interface is enabled."
|
|
bitfld.long 0x4 14. "EWIC,Watchdog early interrupt acknowledge" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "EWIT,Watchdog counter window value"
|
|
tree.end
|
|
tree "JPEG (JPEG Codec)"
|
|
base ad:0x52003000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "JPEG_CONFR0,JPEG codec control register"
|
|
bitfld.long 0x0 0. "START,Start" "0: Stop/abort,1: Start"
|
|
group.long 0x4++0x1B
|
|
line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size"
|
|
bitfld.long 0x0 8. "HDR,Header processing" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "NS,Number of components for scan" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "COLSPACE,Color space" "0: Grayscale (1 quantization table),1: YUV (2 quantization tables),2: RGB (3 quantization tables),3: CMYK (4 quantization tables)"
|
|
newline
|
|
bitfld.long 0x0 3. "DE,Codec operation as coder or decoder" "0: Code,1: Decode"
|
|
bitfld.long 0x0 0.--1. "NF,Number of color components" "0: Grayscale (1 color component),1: - (2 color components),2: YUV or RGB (3 color components),3: CMYK (4 color components)"
|
|
line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register 2"
|
|
hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCUs"
|
|
line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size"
|
|
line.long 0xC "JPEG_CONFR4,JPEG codec configuration register 4"
|
|
hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal sampling factor"
|
|
hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical sampling factor"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "NB,Number of blocks"
|
|
bitfld.long 0xC 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3"
|
|
newline
|
|
bitfld.long 0xC 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1"
|
|
bitfld.long 0xC 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1"
|
|
line.long 0x10 "JPEG_CONFR5,JPEG codec configuration register 5"
|
|
hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal sampling factor"
|
|
hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical sampling factor"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "NB,Number of blocks"
|
|
bitfld.long 0x10 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3"
|
|
newline
|
|
bitfld.long 0x10 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1"
|
|
bitfld.long 0x10 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1"
|
|
line.long 0x14 "JPEG_CONFR6,JPEG codec configuration register 6"
|
|
hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal sampling factor"
|
|
hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical sampling factor"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "NB,Number of blocks"
|
|
bitfld.long 0x14 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3"
|
|
newline
|
|
bitfld.long 0x14 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1"
|
|
bitfld.long 0x14 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1"
|
|
line.long 0x18 "JPEG_CONFR7,JPEG codec configuration register 7"
|
|
hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal sampling factor"
|
|
hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical sampling factor"
|
|
newline
|
|
hexmask.long.byte 0x18 4.--7. 1. "NB,Number of blocks"
|
|
bitfld.long 0x18 2.--3. "QT,Quantization table" "0: Quantization table 0,1: Quantization table 1,2: Quantization table 2,3: Quantization table 3"
|
|
newline
|
|
bitfld.long 0x18 1. "HA,Huffman AC" "0: Huffman AC table 0,1: Huffman AC table 1"
|
|
bitfld.long 0x18 0. "HD,Huffman DC" "0: Huffman DC table 0,1: Huffman DC table 1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "JPEG_CR,JPEG control register"
|
|
bitfld.long 0x0 14. "OFF,Output FIFO flush" "0: No effect,1: Output FIFO is flushed"
|
|
bitfld.long 0x0 13. "IFF,Input FIFO flush" "0: No effect,1: Input FIFO is flushed"
|
|
newline
|
|
bitfld.long 0x0 12. "ODMAEN,Output DMA enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "IDMAEN,Input DMA enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "HPDIE,Header parsing done interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 5. "EOCIE,End of conversion interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "OFNEIE,Output FIFO not empty interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 3. "OFTIE,Output FIFO threshold interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "IFNFIE,Input FIFO not full interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "IFTIE,Input FIFO threshold interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "JCEN,JPEG core enable" "0: Disabled (internal registers are reset).,1: Enabled (internal registers are accessible)."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "JPEG_SR,JPEG status register"
|
|
bitfld.long 0x0 7. "COF,Codec operation flag" "0: Not in progress,1: In progress"
|
|
bitfld.long 0x0 6. "HPDF,Header parsing done flag" "0: Not completed,1: Completed"
|
|
newline
|
|
bitfld.long 0x0 5. "EOCF,End of conversion flag" "0: Not completed,1: Completed"
|
|
bitfld.long 0x0 4. "OFNEF,Output FIFO not empty flag" "0: Empty (data not available),1: Not empty (data available)"
|
|
newline
|
|
bitfld.long 0x0 3. "OFTF,Output FIFO threshold flag" "0: Below threshold,1: At or above threshold"
|
|
bitfld.long 0x0 2. "IFNFF,Input FIFO not full flag" "0: Full,1: Not full"
|
|
newline
|
|
bitfld.long 0x0 1. "IFTF,Input FIFO threshold flag" "0: At or above threshold,1: Below threshold."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "JPEG_CFR,JPEG clear flag register"
|
|
bitfld.long 0x0 6. "CHPDF,Clear header parsing done flag" "0: No effect,1: Clear"
|
|
bitfld.long 0x0 5. "CEOCF,Clear end of conversion flag" "0: No effect,1: Clear"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "JPEG_DIR,JPEG data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DATAIN,Data input FIFO"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "JPEG_DOR,JPEG data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DATAOUT,Data output FIFO"
|
|
group.long 0x50++0x4AB
|
|
line.long 0x0 "JPEG_QMEM0_0,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "QCOEF3,Quantization coefficient 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "QCOEF2,Quantization coefficient 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "QCOEF1,Quantization coefficient 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "QCOEF0,Quantization coefficient 0"
|
|
line.long 0x4 "JPEG_QMEM0_1,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "QCOEF7,Quantization coefficient 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "QCOEF6,Quantization coefficient 6"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "QCOEF5,Quantization coefficient 5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "QCOEF4,Quantization coefficient 4"
|
|
line.long 0x8 "JPEG_QMEM0_2,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x8 24.--31. 1. "QCOEF11,Quantization coefficient 11"
|
|
hexmask.long.byte 0x8 16.--23. 1. "QCOEF10,Quantization coefficient 10"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "QCOEF9,Quantization coefficient 9"
|
|
hexmask.long.byte 0x8 0.--7. 1. "QCOEF8,Quantization coefficient 8"
|
|
line.long 0xC "JPEG_QMEM0_3,JPEG quantization memory 0"
|
|
hexmask.long.byte 0xC 24.--31. 1. "QCOEF15,Quantization coefficient 15"
|
|
hexmask.long.byte 0xC 16.--23. 1. "QCOEF14,Quantization coefficient 14"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "QCOEF13,Quantization coefficient 13"
|
|
hexmask.long.byte 0xC 0.--7. 1. "QCOEF12,Quantization coefficient 12"
|
|
line.long 0x10 "JPEG_QMEM0_4,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x10 24.--31. 1. "QCOEF19,Quantization coefficient 19"
|
|
hexmask.long.byte 0x10 16.--23. 1. "QCOEF18,Quantization coefficient 18"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "QCOEF17,Quantization coefficient 17"
|
|
hexmask.long.byte 0x10 0.--7. 1. "QCOEF16,Quantization coefficient 16"
|
|
line.long 0x14 "JPEG_QMEM0_5,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x14 24.--31. 1. "QCOEF23,Quantization coefficient 23"
|
|
hexmask.long.byte 0x14 16.--23. 1. "QCOEF22,Quantization coefficient 22"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "QCOEF21,Quantization coefficient 21"
|
|
hexmask.long.byte 0x14 0.--7. 1. "QCOEF20,Quantization coefficient 20"
|
|
line.long 0x18 "JPEG_QMEM0_6,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x18 24.--31. 1. "QCOEF27,Quantization coefficient 27"
|
|
hexmask.long.byte 0x18 16.--23. 1. "QCOEF26,Quantization coefficient 26"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "QCOEF25,Quantization coefficient 25"
|
|
hexmask.long.byte 0x18 0.--7. 1. "QCOEF24,Quantization coefficient 24"
|
|
line.long 0x1C "JPEG_QMEM0_7,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "QCOEF31,Quantization coefficient 31"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "QCOEF30,Quantization coefficient 30"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "QCOEF29,Quantization coefficient 29"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "QCOEF28,Quantization coefficient 28"
|
|
line.long 0x20 "JPEG_QMEM0_8,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x20 24.--31. 1. "QCOEF35,Quantization coefficient 35"
|
|
hexmask.long.byte 0x20 16.--23. 1. "QCOEF34,Quantization coefficient 34"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--15. 1. "QCOEF33,Quantization coefficient 33"
|
|
hexmask.long.byte 0x20 0.--7. 1. "QCOEF32,Quantization coefficient 32"
|
|
line.long 0x24 "JPEG_QMEM0_9,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x24 24.--31. 1. "QCOEF39,Quantization coefficient 39"
|
|
hexmask.long.byte 0x24 16.--23. 1. "QCOEF38,Quantization coefficient 38"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--15. 1. "QCOEF37,Quantization coefficient 37"
|
|
hexmask.long.byte 0x24 0.--7. 1. "QCOEF36,Quantization coefficient 36"
|
|
line.long 0x28 "JPEG_QMEM0_10,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x28 24.--31. 1. "QCOEF43,Quantization coefficient 43"
|
|
hexmask.long.byte 0x28 16.--23. 1. "QCOEF42,Quantization coefficient 42"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--15. 1. "QCOEF41,Quantization coefficient 41"
|
|
hexmask.long.byte 0x28 0.--7. 1. "QCOEF40,Quantization coefficient 40"
|
|
line.long 0x2C "JPEG_QMEM0_11,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "QCOEF47,Quantization coefficient 47"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "QCOEF46,Quantization coefficient 46"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--15. 1. "QCOEF45,Quantization coefficient 45"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "QCOEF44,Quantization coefficient 44"
|
|
line.long 0x30 "JPEG_QMEM0_12,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x30 24.--31. 1. "QCOEF51,Quantization coefficient 51"
|
|
hexmask.long.byte 0x30 16.--23. 1. "QCOEF50,Quantization coefficient 50"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--15. 1. "QCOEF49,Quantization coefficient 49"
|
|
hexmask.long.byte 0x30 0.--7. 1. "QCOEF48,Quantization coefficient 48"
|
|
line.long 0x34 "JPEG_QMEM0_13,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x34 24.--31. 1. "QCOEF55,Quantization coefficient 55"
|
|
hexmask.long.byte 0x34 16.--23. 1. "QCOEF54,Quantization coefficient 54"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--15. 1. "QCOEF53,Quantization coefficient 53"
|
|
hexmask.long.byte 0x34 0.--7. 1. "QCOEF52,Quantization coefficient 52"
|
|
line.long 0x38 "JPEG_QMEM0_14,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x38 24.--31. 1. "QCOEF59,Quantization coefficient 59"
|
|
hexmask.long.byte 0x38 16.--23. 1. "QCOEF58,Quantization coefficient 58"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--15. 1. "QCOEF57,Quantization coefficient 57"
|
|
hexmask.long.byte 0x38 0.--7. 1. "QCOEF56,Quantization coefficient 56"
|
|
line.long 0x3C "JPEG_QMEM0_15,JPEG quantization memory 0"
|
|
hexmask.long.byte 0x3C 24.--31. 1. "QCOEF63,Quantization coefficient 63"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "QCOEF62,Quantization coefficient 62"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--15. 1. "QCOEF61,Quantization coefficient 61"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "QCOEF60,Quantization coefficient 60"
|
|
line.long 0x40 "JPEG_QMEM1_0,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x40 24.--31. 1. "QCOEF3,Quantization coefficient 3"
|
|
hexmask.long.byte 0x40 16.--23. 1. "QCOEF2,Quantization coefficient 2"
|
|
newline
|
|
hexmask.long.byte 0x40 8.--15. 1. "QCOEF1,Quantization coefficient 1"
|
|
hexmask.long.byte 0x40 0.--7. 1. "QCOEF0,Quantization coefficient 0"
|
|
line.long 0x44 "JPEG_QMEM1_1,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x44 24.--31. 1. "QCOEF7,Quantization coefficient 7"
|
|
hexmask.long.byte 0x44 16.--23. 1. "QCOEF6,Quantization coefficient 6"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--15. 1. "QCOEF5,Quantization coefficient 5"
|
|
hexmask.long.byte 0x44 0.--7. 1. "QCOEF4,Quantization coefficient 4"
|
|
line.long 0x48 "JPEG_QMEM1_2,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x48 24.--31. 1. "QCOEF11,Quantization coefficient 11"
|
|
hexmask.long.byte 0x48 16.--23. 1. "QCOEF10,Quantization coefficient 10"
|
|
newline
|
|
hexmask.long.byte 0x48 8.--15. 1. "QCOEF9,Quantization coefficient 9"
|
|
hexmask.long.byte 0x48 0.--7. 1. "QCOEF8,Quantization coefficient 8"
|
|
line.long 0x4C "JPEG_QMEM1_3,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x4C 24.--31. 1. "QCOEF15,Quantization coefficient 15"
|
|
hexmask.long.byte 0x4C 16.--23. 1. "QCOEF14,Quantization coefficient 14"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--15. 1. "QCOEF13,Quantization coefficient 13"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "QCOEF12,Quantization coefficient 12"
|
|
line.long 0x50 "JPEG_QMEM1_4,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x50 24.--31. 1. "QCOEF19,Quantization coefficient 19"
|
|
hexmask.long.byte 0x50 16.--23. 1. "QCOEF18,Quantization coefficient 18"
|
|
newline
|
|
hexmask.long.byte 0x50 8.--15. 1. "QCOEF17,Quantization coefficient 17"
|
|
hexmask.long.byte 0x50 0.--7. 1. "QCOEF16,Quantization coefficient 16"
|
|
line.long 0x54 "JPEG_QMEM1_5,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x54 24.--31. 1. "QCOEF23,Quantization coefficient 23"
|
|
hexmask.long.byte 0x54 16.--23. 1. "QCOEF22,Quantization coefficient 22"
|
|
newline
|
|
hexmask.long.byte 0x54 8.--15. 1. "QCOEF21,Quantization coefficient 21"
|
|
hexmask.long.byte 0x54 0.--7. 1. "QCOEF20,Quantization coefficient 20"
|
|
line.long 0x58 "JPEG_QMEM1_6,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x58 24.--31. 1. "QCOEF27,Quantization coefficient 27"
|
|
hexmask.long.byte 0x58 16.--23. 1. "QCOEF26,Quantization coefficient 26"
|
|
newline
|
|
hexmask.long.byte 0x58 8.--15. 1. "QCOEF25,Quantization coefficient 25"
|
|
hexmask.long.byte 0x58 0.--7. 1. "QCOEF24,Quantization coefficient 24"
|
|
line.long 0x5C "JPEG_QMEM1_7,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x5C 24.--31. 1. "QCOEF31,Quantization coefficient 31"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "QCOEF30,Quantization coefficient 30"
|
|
newline
|
|
hexmask.long.byte 0x5C 8.--15. 1. "QCOEF29,Quantization coefficient 29"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "QCOEF28,Quantization coefficient 28"
|
|
line.long 0x60 "JPEG_QMEM1_8,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x60 24.--31. 1. "QCOEF35,Quantization coefficient 35"
|
|
hexmask.long.byte 0x60 16.--23. 1. "QCOEF34,Quantization coefficient 34"
|
|
newline
|
|
hexmask.long.byte 0x60 8.--15. 1. "QCOEF33,Quantization coefficient 33"
|
|
hexmask.long.byte 0x60 0.--7. 1. "QCOEF32,Quantization coefficient 32"
|
|
line.long 0x64 "JPEG_QMEM1_9,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x64 24.--31. 1. "QCOEF39,Quantization coefficient 39"
|
|
hexmask.long.byte 0x64 16.--23. 1. "QCOEF38,Quantization coefficient 38"
|
|
newline
|
|
hexmask.long.byte 0x64 8.--15. 1. "QCOEF37,Quantization coefficient 37"
|
|
hexmask.long.byte 0x64 0.--7. 1. "QCOEF36,Quantization coefficient 36"
|
|
line.long 0x68 "JPEG_QMEM1_10,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x68 24.--31. 1. "QCOEF43,Quantization coefficient 43"
|
|
hexmask.long.byte 0x68 16.--23. 1. "QCOEF42,Quantization coefficient 42"
|
|
newline
|
|
hexmask.long.byte 0x68 8.--15. 1. "QCOEF41,Quantization coefficient 41"
|
|
hexmask.long.byte 0x68 0.--7. 1. "QCOEF40,Quantization coefficient 40"
|
|
line.long 0x6C "JPEG_QMEM1_11,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x6C 24.--31. 1. "QCOEF47,Quantization coefficient 47"
|
|
hexmask.long.byte 0x6C 16.--23. 1. "QCOEF46,Quantization coefficient 46"
|
|
newline
|
|
hexmask.long.byte 0x6C 8.--15. 1. "QCOEF45,Quantization coefficient 45"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "QCOEF44,Quantization coefficient 44"
|
|
line.long 0x70 "JPEG_QMEM1_12,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x70 24.--31. 1. "QCOEF51,Quantization coefficient 51"
|
|
hexmask.long.byte 0x70 16.--23. 1. "QCOEF50,Quantization coefficient 50"
|
|
newline
|
|
hexmask.long.byte 0x70 8.--15. 1. "QCOEF49,Quantization coefficient 49"
|
|
hexmask.long.byte 0x70 0.--7. 1. "QCOEF48,Quantization coefficient 48"
|
|
line.long 0x74 "JPEG_QMEM1_13,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x74 24.--31. 1. "QCOEF55,Quantization coefficient 55"
|
|
hexmask.long.byte 0x74 16.--23. 1. "QCOEF54,Quantization coefficient 54"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--15. 1. "QCOEF53,Quantization coefficient 53"
|
|
hexmask.long.byte 0x74 0.--7. 1. "QCOEF52,Quantization coefficient 52"
|
|
line.long 0x78 "JPEG_QMEM1_14,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x78 24.--31. 1. "QCOEF59,Quantization coefficient 59"
|
|
hexmask.long.byte 0x78 16.--23. 1. "QCOEF58,Quantization coefficient 58"
|
|
newline
|
|
hexmask.long.byte 0x78 8.--15. 1. "QCOEF57,Quantization coefficient 57"
|
|
hexmask.long.byte 0x78 0.--7. 1. "QCOEF56,Quantization coefficient 56"
|
|
line.long 0x7C "JPEG_QMEM1_15,JPEG quantization memory 1"
|
|
hexmask.long.byte 0x7C 24.--31. 1. "QCOEF63,Quantization coefficient 63"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "QCOEF62,Quantization coefficient 62"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--15. 1. "QCOEF61,Quantization coefficient 61"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "QCOEF60,Quantization coefficient 60"
|
|
line.long 0x80 "JPEG_QMEM2_0,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x80 24.--31. 1. "QCOEF3,Quantization coefficient 3"
|
|
hexmask.long.byte 0x80 16.--23. 1. "QCOEF2,Quantization coefficient 2"
|
|
newline
|
|
hexmask.long.byte 0x80 8.--15. 1. "QCOEF1,Quantization coefficient 1"
|
|
hexmask.long.byte 0x80 0.--7. 1. "QCOEF0,Quantization coefficient 0"
|
|
line.long 0x84 "JPEG_QMEM2_1,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x84 24.--31. 1. "QCOEF7,Quantization coefficient 7"
|
|
hexmask.long.byte 0x84 16.--23. 1. "QCOEF6,Quantization coefficient 6"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--15. 1. "QCOEF5,Quantization coefficient 5"
|
|
hexmask.long.byte 0x84 0.--7. 1. "QCOEF4,Quantization coefficient 4"
|
|
line.long 0x88 "JPEG_QMEM2_2,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x88 24.--31. 1. "QCOEF11,Quantization coefficient 11"
|
|
hexmask.long.byte 0x88 16.--23. 1. "QCOEF10,Quantization coefficient 10"
|
|
newline
|
|
hexmask.long.byte 0x88 8.--15. 1. "QCOEF9,Quantization coefficient 9"
|
|
hexmask.long.byte 0x88 0.--7. 1. "QCOEF8,Quantization coefficient 8"
|
|
line.long 0x8C "JPEG_QMEM2_3,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x8C 24.--31. 1. "QCOEF15,Quantization coefficient 15"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "QCOEF14,Quantization coefficient 14"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--15. 1. "QCOEF13,Quantization coefficient 13"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "QCOEF12,Quantization coefficient 12"
|
|
line.long 0x90 "JPEG_QMEM2_4,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x90 24.--31. 1. "QCOEF19,Quantization coefficient 19"
|
|
hexmask.long.byte 0x90 16.--23. 1. "QCOEF18,Quantization coefficient 18"
|
|
newline
|
|
hexmask.long.byte 0x90 8.--15. 1. "QCOEF17,Quantization coefficient 17"
|
|
hexmask.long.byte 0x90 0.--7. 1. "QCOEF16,Quantization coefficient 16"
|
|
line.long 0x94 "JPEG_QMEM2_5,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x94 24.--31. 1. "QCOEF23,Quantization coefficient 23"
|
|
hexmask.long.byte 0x94 16.--23. 1. "QCOEF22,Quantization coefficient 22"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--15. 1. "QCOEF21,Quantization coefficient 21"
|
|
hexmask.long.byte 0x94 0.--7. 1. "QCOEF20,Quantization coefficient 20"
|
|
line.long 0x98 "JPEG_QMEM2_6,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x98 24.--31. 1. "QCOEF27,Quantization coefficient 27"
|
|
hexmask.long.byte 0x98 16.--23. 1. "QCOEF26,Quantization coefficient 26"
|
|
newline
|
|
hexmask.long.byte 0x98 8.--15. 1. "QCOEF25,Quantization coefficient 25"
|
|
hexmask.long.byte 0x98 0.--7. 1. "QCOEF24,Quantization coefficient 24"
|
|
line.long 0x9C "JPEG_QMEM2_7,JPEG quantization memory 2"
|
|
hexmask.long.byte 0x9C 24.--31. 1. "QCOEF31,Quantization coefficient 31"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "QCOEF30,Quantization coefficient 30"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--15. 1. "QCOEF29,Quantization coefficient 29"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "QCOEF28,Quantization coefficient 28"
|
|
line.long 0xA0 "JPEG_QMEM2_8,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xA0 24.--31. 1. "QCOEF35,Quantization coefficient 35"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "QCOEF34,Quantization coefficient 34"
|
|
newline
|
|
hexmask.long.byte 0xA0 8.--15. 1. "QCOEF33,Quantization coefficient 33"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "QCOEF32,Quantization coefficient 32"
|
|
line.long 0xA4 "JPEG_QMEM2_9,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xA4 24.--31. 1. "QCOEF39,Quantization coefficient 39"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "QCOEF38,Quantization coefficient 38"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--15. 1. "QCOEF37,Quantization coefficient 37"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "QCOEF36,Quantization coefficient 36"
|
|
line.long 0xA8 "JPEG_QMEM2_10,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xA8 24.--31. 1. "QCOEF43,Quantization coefficient 43"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "QCOEF42,Quantization coefficient 42"
|
|
newline
|
|
hexmask.long.byte 0xA8 8.--15. 1. "QCOEF41,Quantization coefficient 41"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "QCOEF40,Quantization coefficient 40"
|
|
line.long 0xAC "JPEG_QMEM2_11,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xAC 24.--31. 1. "QCOEF47,Quantization coefficient 47"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "QCOEF46,Quantization coefficient 46"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--15. 1. "QCOEF45,Quantization coefficient 45"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "QCOEF44,Quantization coefficient 44"
|
|
line.long 0xB0 "JPEG_QMEM2_12,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xB0 24.--31. 1. "QCOEF51,Quantization coefficient 51"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "QCOEF50,Quantization coefficient 50"
|
|
newline
|
|
hexmask.long.byte 0xB0 8.--15. 1. "QCOEF49,Quantization coefficient 49"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "QCOEF48,Quantization coefficient 48"
|
|
line.long 0xB4 "JPEG_QMEM2_13,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xB4 24.--31. 1. "QCOEF55,Quantization coefficient 55"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "QCOEF54,Quantization coefficient 54"
|
|
newline
|
|
hexmask.long.byte 0xB4 8.--15. 1. "QCOEF53,Quantization coefficient 53"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "QCOEF52,Quantization coefficient 52"
|
|
line.long 0xB8 "JPEG_QMEM2_14,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xB8 24.--31. 1. "QCOEF59,Quantization coefficient 59"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "QCOEF58,Quantization coefficient 58"
|
|
newline
|
|
hexmask.long.byte 0xB8 8.--15. 1. "QCOEF57,Quantization coefficient 57"
|
|
hexmask.long.byte 0xB8 0.--7. 1. "QCOEF56,Quantization coefficient 56"
|
|
line.long 0xBC "JPEG_QMEM2_15,JPEG quantization memory 2"
|
|
hexmask.long.byte 0xBC 24.--31. 1. "QCOEF63,Quantization coefficient 63"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "QCOEF62,Quantization coefficient 62"
|
|
newline
|
|
hexmask.long.byte 0xBC 8.--15. 1. "QCOEF61,Quantization coefficient 61"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "QCOEF60,Quantization coefficient 60"
|
|
line.long 0xC0 "JPEG_QMEM3_0,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xC0 24.--31. 1. "QCOEF3,Quantization coefficient 3"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "QCOEF2,Quantization coefficient 2"
|
|
newline
|
|
hexmask.long.byte 0xC0 8.--15. 1. "QCOEF1,Quantization coefficient 1"
|
|
hexmask.long.byte 0xC0 0.--7. 1. "QCOEF0,Quantization coefficient 0"
|
|
line.long 0xC4 "JPEG_QMEM3_1,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xC4 24.--31. 1. "QCOEF7,Quantization coefficient 7"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "QCOEF6,Quantization coefficient 6"
|
|
newline
|
|
hexmask.long.byte 0xC4 8.--15. 1. "QCOEF5,Quantization coefficient 5"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "QCOEF4,Quantization coefficient 4"
|
|
line.long 0xC8 "JPEG_QMEM3_2,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xC8 24.--31. 1. "QCOEF11,Quantization coefficient 11"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "QCOEF10,Quantization coefficient 10"
|
|
newline
|
|
hexmask.long.byte 0xC8 8.--15. 1. "QCOEF9,Quantization coefficient 9"
|
|
hexmask.long.byte 0xC8 0.--7. 1. "QCOEF8,Quantization coefficient 8"
|
|
line.long 0xCC "JPEG_QMEM3_3,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xCC 24.--31. 1. "QCOEF15,Quantization coefficient 15"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "QCOEF14,Quantization coefficient 14"
|
|
newline
|
|
hexmask.long.byte 0xCC 8.--15. 1. "QCOEF13,Quantization coefficient 13"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "QCOEF12,Quantization coefficient 12"
|
|
line.long 0xD0 "JPEG_QMEM3_4,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xD0 24.--31. 1. "QCOEF19,Quantization coefficient 19"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "QCOEF18,Quantization coefficient 18"
|
|
newline
|
|
hexmask.long.byte 0xD0 8.--15. 1. "QCOEF17,Quantization coefficient 17"
|
|
hexmask.long.byte 0xD0 0.--7. 1. "QCOEF16,Quantization coefficient 16"
|
|
line.long 0xD4 "JPEG_QMEM3_5,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xD4 24.--31. 1. "QCOEF23,Quantization coefficient 23"
|
|
hexmask.long.byte 0xD4 16.--23. 1. "QCOEF22,Quantization coefficient 22"
|
|
newline
|
|
hexmask.long.byte 0xD4 8.--15. 1. "QCOEF21,Quantization coefficient 21"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "QCOEF20,Quantization coefficient 20"
|
|
line.long 0xD8 "JPEG_QMEM3_6,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xD8 24.--31. 1. "QCOEF27,Quantization coefficient 27"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "QCOEF26,Quantization coefficient 26"
|
|
newline
|
|
hexmask.long.byte 0xD8 8.--15. 1. "QCOEF25,Quantization coefficient 25"
|
|
hexmask.long.byte 0xD8 0.--7. 1. "QCOEF24,Quantization coefficient 24"
|
|
line.long 0xDC "JPEG_QMEM3_7,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xDC 24.--31. 1. "QCOEF31,Quantization coefficient 31"
|
|
hexmask.long.byte 0xDC 16.--23. 1. "QCOEF30,Quantization coefficient 30"
|
|
newline
|
|
hexmask.long.byte 0xDC 8.--15. 1. "QCOEF29,Quantization coefficient 29"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "QCOEF28,Quantization coefficient 28"
|
|
line.long 0xE0 "JPEG_QMEM3_8,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xE0 24.--31. 1. "QCOEF35,Quantization coefficient 35"
|
|
hexmask.long.byte 0xE0 16.--23. 1. "QCOEF34,Quantization coefficient 34"
|
|
newline
|
|
hexmask.long.byte 0xE0 8.--15. 1. "QCOEF33,Quantization coefficient 33"
|
|
hexmask.long.byte 0xE0 0.--7. 1. "QCOEF32,Quantization coefficient 32"
|
|
line.long 0xE4 "JPEG_QMEM3_9,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xE4 24.--31. 1. "QCOEF39,Quantization coefficient 39"
|
|
hexmask.long.byte 0xE4 16.--23. 1. "QCOEF38,Quantization coefficient 38"
|
|
newline
|
|
hexmask.long.byte 0xE4 8.--15. 1. "QCOEF37,Quantization coefficient 37"
|
|
hexmask.long.byte 0xE4 0.--7. 1. "QCOEF36,Quantization coefficient 36"
|
|
line.long 0xE8 "JPEG_QMEM3_10,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xE8 24.--31. 1. "QCOEF43,Quantization coefficient 43"
|
|
hexmask.long.byte 0xE8 16.--23. 1. "QCOEF42,Quantization coefficient 42"
|
|
newline
|
|
hexmask.long.byte 0xE8 8.--15. 1. "QCOEF41,Quantization coefficient 41"
|
|
hexmask.long.byte 0xE8 0.--7. 1. "QCOEF40,Quantization coefficient 40"
|
|
line.long 0xEC "JPEG_QMEM3_11,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xEC 24.--31. 1. "QCOEF47,Quantization coefficient 47"
|
|
hexmask.long.byte 0xEC 16.--23. 1. "QCOEF46,Quantization coefficient 46"
|
|
newline
|
|
hexmask.long.byte 0xEC 8.--15. 1. "QCOEF45,Quantization coefficient 45"
|
|
hexmask.long.byte 0xEC 0.--7. 1. "QCOEF44,Quantization coefficient 44"
|
|
line.long 0xF0 "JPEG_QMEM3_12,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xF0 24.--31. 1. "QCOEF51,Quantization coefficient 51"
|
|
hexmask.long.byte 0xF0 16.--23. 1. "QCOEF50,Quantization coefficient 50"
|
|
newline
|
|
hexmask.long.byte 0xF0 8.--15. 1. "QCOEF49,Quantization coefficient 49"
|
|
hexmask.long.byte 0xF0 0.--7. 1. "QCOEF48,Quantization coefficient 48"
|
|
line.long 0xF4 "JPEG_QMEM3_13,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xF4 24.--31. 1. "QCOEF55,Quantization coefficient 55"
|
|
hexmask.long.byte 0xF4 16.--23. 1. "QCOEF54,Quantization coefficient 54"
|
|
newline
|
|
hexmask.long.byte 0xF4 8.--15. 1. "QCOEF53,Quantization coefficient 53"
|
|
hexmask.long.byte 0xF4 0.--7. 1. "QCOEF52,Quantization coefficient 52"
|
|
line.long 0xF8 "JPEG_QMEM3_14,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xF8 24.--31. 1. "QCOEF59,Quantization coefficient 59"
|
|
hexmask.long.byte 0xF8 16.--23. 1. "QCOEF58,Quantization coefficient 58"
|
|
newline
|
|
hexmask.long.byte 0xF8 8.--15. 1. "QCOEF57,Quantization coefficient 57"
|
|
hexmask.long.byte 0xF8 0.--7. 1. "QCOEF56,Quantization coefficient 56"
|
|
line.long 0xFC "JPEG_QMEM3_15,JPEG quantization memory 3"
|
|
hexmask.long.byte 0xFC 24.--31. 1. "QCOEF63,Quantization coefficient 63"
|
|
hexmask.long.byte 0xFC 16.--23. 1. "QCOEF62,Quantization coefficient 62"
|
|
newline
|
|
hexmask.long.byte 0xFC 8.--15. 1. "QCOEF61,Quantization coefficient 61"
|
|
hexmask.long.byte 0xFC 0.--7. 1. "QCOEF60,Quantization coefficient 60"
|
|
line.long 0x100 "JPEG_HUFFMIN0_0,JPEG Huffman min"
|
|
hexmask.long 0x100 0.--31. 1. "DATA0,Minimum Huffman value"
|
|
line.long 0x104 "JPEG_HUFFMIN0_1,JPEG Huffman min"
|
|
hexmask.long 0x104 0.--31. 1. "DATA0,Minimum Huffman value"
|
|
line.long 0x108 "JPEG_HUFFMIN0_2,JPEG Huffman min"
|
|
hexmask.long 0x108 0.--31. 1. "DATA0,Minimum Huffman value"
|
|
line.long 0x10C "JPEG_HUFFMIN0_3,JPEG Huffman min 0 [alternate]"
|
|
hexmask.long.byte 0x10C 0.--3. 1. "DATA0,Minimum Huffman value"
|
|
line.long 0x110 "JPEG_HUFFMIN1_0,JPEG Huffman min"
|
|
hexmask.long 0x110 0.--31. 1. "DATA1,Minimum Huffman value"
|
|
line.long 0x114 "JPEG_HUFFMIN1_1,JPEG Huffman min"
|
|
hexmask.long 0x114 0.--31. 1. "DATA1,Minimum Huffman value"
|
|
line.long 0x118 "JPEG_HUFFMIN1_2,JPEG Huffman min"
|
|
hexmask.long 0x118 0.--31. 1. "DATA1,Minimum Huffman value"
|
|
line.long 0x11C "JPEG_HUFFMIN1_3,JPEG Huffman min 1 [alternate]"
|
|
hexmask.long.byte 0x11C 0.--3. 1. "DATA1,Minimum Huffman value"
|
|
line.long 0x120 "JPEG_HUFFMIN2_0,JPEG Huffman min"
|
|
hexmask.long 0x120 0.--31. 1. "DATA2,Minimum Huffman value"
|
|
line.long 0x124 "JPEG_HUFFMIN2_1,JPEG Huffman min"
|
|
hexmask.long 0x124 0.--31. 1. "DATA2,Minimum Huffman value"
|
|
line.long 0x128 "JPEG_HUFFMIN2_2,JPEG Huffman min"
|
|
hexmask.long 0x128 0.--31. 1. "DATA2,Minimum Huffman value"
|
|
line.long 0x12C "JPEG_HUFFMIN2_3,JPEG Huffman min 2 [alternate]"
|
|
hexmask.long.byte 0x12C 0.--3. 1. "DATA2,Minimum Huffman value"
|
|
line.long 0x130 "JPEG_HUFFMIN3_0,JPEG Huffman min"
|
|
hexmask.long 0x130 0.--31. 1. "DATA3,Minimum Huffman value"
|
|
line.long 0x134 "JPEG_HUFFMIN3_1,JPEG Huffman min"
|
|
hexmask.long 0x134 0.--31. 1. "DATA3,Minimum Huffman value"
|
|
line.long 0x138 "JPEG_HUFFMIN3_2,JPEG Huffman min"
|
|
hexmask.long 0x138 0.--31. 1. "DATA3,Minimum Huffman value"
|
|
line.long 0x13C "JPEG_HUFFMIN3_3,JPEG Huffman min 3 [alternate]"
|
|
hexmask.long.byte 0x13C 0.--3. 1. "DATA3,Minimum Huffman value"
|
|
line.long 0x140 "JPEG_HUFFBASE0,JPEG Huffman base"
|
|
hexmask.long.word 0x140 16.--24. 1. "DATA1,Data 1"
|
|
hexmask.long.word 0x140 0.--8. 1. "DATA0,Data 0"
|
|
line.long 0x144 "JPEG_HUFFBASE1,JPEG Huffman base"
|
|
hexmask.long.word 0x144 16.--24. 1. "DATA3,Data 3"
|
|
hexmask.long.word 0x144 0.--8. 1. "DATA2,Data 2"
|
|
line.long 0x148 "JPEG_HUFFBASE2,JPEG Huffman base"
|
|
hexmask.long.word 0x148 16.--24. 1. "DATA5,Data 5"
|
|
hexmask.long.word 0x148 0.--8. 1. "DATA4,Data 4"
|
|
line.long 0x14C "JPEG_HUFFBASE3,JPEG Huffman base"
|
|
hexmask.long.word 0x14C 16.--24. 1. "DATA7,Data 7"
|
|
hexmask.long.word 0x14C 0.--8. 1. "DATA6,Data 6"
|
|
line.long 0x150 "JPEG_HUFFBASE4,JPEG Huffman base"
|
|
hexmask.long.word 0x150 16.--24. 1. "DATA9,Data 9"
|
|
hexmask.long.word 0x150 0.--8. 1. "DATA8,Data 8"
|
|
line.long 0x154 "JPEG_HUFFBASE5,JPEG Huffman base"
|
|
hexmask.long.word 0x154 16.--24. 1. "DATA11,Data 11"
|
|
hexmask.long.word 0x154 0.--8. 1. "DATA10,Data 10"
|
|
line.long 0x158 "JPEG_HUFFBASE6,JPEG Huffman base"
|
|
hexmask.long.word 0x158 16.--24. 1. "DATA13,Data 13"
|
|
hexmask.long.word 0x158 0.--8. 1. "DATA12,Data 12"
|
|
line.long 0x15C "JPEG_HUFFBASE7,JPEG Huffman base"
|
|
hexmask.long.word 0x15C 16.--24. 1. "DATA15,Data 15"
|
|
hexmask.long.word 0x15C 0.--8. 1. "DATA14,Data 14"
|
|
line.long 0x160 "JPEG_HUFFBASE8,JPEG Huffman base"
|
|
hexmask.long.word 0x160 16.--24. 1. "DATA17,Data 17"
|
|
hexmask.long.word 0x160 0.--8. 1. "DATA16,Data 16"
|
|
line.long 0x164 "JPEG_HUFFBASE9,JPEG Huffman base"
|
|
hexmask.long.word 0x164 16.--24. 1. "DATA19,Data 19"
|
|
hexmask.long.word 0x164 0.--8. 1. "DATA18,Data 18"
|
|
line.long 0x168 "JPEG_HUFFBASE10,JPEG Huffman base"
|
|
hexmask.long.word 0x168 16.--24. 1. "DATA21,Data 21"
|
|
hexmask.long.word 0x168 0.--8. 1. "DATA20,Data 20"
|
|
line.long 0x16C "JPEG_HUFFBASE11,JPEG Huffman base"
|
|
hexmask.long.word 0x16C 16.--24. 1. "DATA23,Data 23"
|
|
hexmask.long.word 0x16C 0.--8. 1. "DATA22,Data 22"
|
|
line.long 0x170 "JPEG_HUFFBASE12,JPEG Huffman base"
|
|
hexmask.long.word 0x170 16.--24. 1. "DATA25,Data 25"
|
|
hexmask.long.word 0x170 0.--8. 1. "DATA24,Data 24"
|
|
line.long 0x174 "JPEG_HUFFBASE13,JPEG Huffman base"
|
|
hexmask.long.word 0x174 16.--24. 1. "DATA27,Data 27"
|
|
hexmask.long.word 0x174 0.--8. 1. "DATA26,Data 26"
|
|
line.long 0x178 "JPEG_HUFFBASE14,JPEG Huffman base"
|
|
hexmask.long.word 0x178 16.--24. 1. "DATA29,Data 29"
|
|
hexmask.long.word 0x178 0.--8. 1. "DATA28,Data 28"
|
|
line.long 0x17C "JPEG_HUFFBASE15,JPEG Huffman base"
|
|
hexmask.long.word 0x17C 16.--24. 1. "DATA31,Data 31"
|
|
hexmask.long.word 0x17C 0.--8. 1. "DATA30,Data 30"
|
|
line.long 0x180 "JPEG_HUFFBASE16,JPEG Huffman base"
|
|
hexmask.long.word 0x180 16.--24. 1. "DATA33,Data 33"
|
|
hexmask.long.word 0x180 0.--8. 1. "DATA32,Data 32"
|
|
line.long 0x184 "JPEG_HUFFBASE17,JPEG Huffman base"
|
|
hexmask.long.word 0x184 16.--24. 1. "DATA35,Data 35"
|
|
hexmask.long.word 0x184 0.--8. 1. "DATA34,Data 34"
|
|
line.long 0x188 "JPEG_HUFFBASE18,JPEG Huffman base"
|
|
hexmask.long.word 0x188 16.--24. 1. "DATA37,Data 37"
|
|
hexmask.long.word 0x188 0.--8. 1. "DATA36,Data 36"
|
|
line.long 0x18C "JPEG_HUFFBASE19,JPEG Huffman base"
|
|
hexmask.long.word 0x18C 16.--24. 1. "DATA39,Data 39"
|
|
hexmask.long.word 0x18C 0.--8. 1. "DATA38,Data 38"
|
|
line.long 0x190 "JPEG_HUFFBASE20,JPEG Huffman base"
|
|
hexmask.long.word 0x190 16.--24. 1. "DATA41,Data 41"
|
|
hexmask.long.word 0x190 0.--8. 1. "DATA40,Data 40"
|
|
line.long 0x194 "JPEG_HUFFBASE21,JPEG Huffman base"
|
|
hexmask.long.word 0x194 16.--24. 1. "DATA43,Data 43"
|
|
hexmask.long.word 0x194 0.--8. 1. "DATA42,Data 42"
|
|
line.long 0x198 "JPEG_HUFFBASE22,JPEG Huffman base"
|
|
hexmask.long.word 0x198 16.--24. 1. "DATA45,Data 45"
|
|
hexmask.long.word 0x198 0.--8. 1. "DATA44,Data 44"
|
|
line.long 0x19C "JPEG_HUFFBASE23,JPEG Huffman base"
|
|
hexmask.long.word 0x19C 16.--24. 1. "DATA47,Data 47"
|
|
hexmask.long.word 0x19C 0.--8. 1. "DATA46,Data 46"
|
|
line.long 0x1A0 "JPEG_HUFFBASE24,JPEG Huffman base"
|
|
hexmask.long.word 0x1A0 16.--24. 1. "DATA49,Data 49"
|
|
hexmask.long.word 0x1A0 0.--8. 1. "DATA48,Data 48"
|
|
line.long 0x1A4 "JPEG_HUFFBASE25,JPEG Huffman base"
|
|
hexmask.long.word 0x1A4 16.--24. 1. "DATA51,Data 51"
|
|
hexmask.long.word 0x1A4 0.--8. 1. "DATA50,Data 50"
|
|
line.long 0x1A8 "JPEG_HUFFBASE26,JPEG Huffman base"
|
|
hexmask.long.word 0x1A8 16.--24. 1. "DATA53,Data 53"
|
|
hexmask.long.word 0x1A8 0.--8. 1. "DATA52,Data 52"
|
|
line.long 0x1AC "JPEG_HUFFBASE27,JPEG Huffman base"
|
|
hexmask.long.word 0x1AC 16.--24. 1. "DATA55,Data 55"
|
|
hexmask.long.word 0x1AC 0.--8. 1. "DATA54,Data 54"
|
|
line.long 0x1B0 "JPEG_HUFFBASE28,JPEG Huffman base"
|
|
hexmask.long.word 0x1B0 16.--24. 1. "DATA57,Data 57"
|
|
hexmask.long.word 0x1B0 0.--8. 1. "DATA56,Data 56"
|
|
line.long 0x1B4 "JPEG_HUFFBASE29,JPEG Huffman base"
|
|
hexmask.long.word 0x1B4 16.--24. 1. "DATA59,Data 59"
|
|
hexmask.long.word 0x1B4 0.--8. 1. "DATA58,Data 58"
|
|
line.long 0x1B8 "JPEG_HUFFBASE30,JPEG Huffman base"
|
|
hexmask.long.word 0x1B8 16.--24. 1. "DATA61,Data 61"
|
|
hexmask.long.word 0x1B8 0.--8. 1. "DATA60,Data 60"
|
|
line.long 0x1BC "JPEG_HUFFBASE31,JPEG Huffman base"
|
|
hexmask.long.word 0x1BC 16.--24. 1. "DATA63,Data 63"
|
|
hexmask.long.word 0x1BC 0.--8. 1. "DATA62,Data 62"
|
|
line.long 0x1C0 "JPEG_HUFFSYMB0,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. "DATA3,Data 3"
|
|
hexmask.long.byte 0x1C0 16.--23. 1. "DATA2,Data 2"
|
|
newline
|
|
hexmask.long.byte 0x1C0 8.--15. 1. "DATA1,Data 1"
|
|
hexmask.long.byte 0x1C0 0.--7. 1. "DATA0,Data 0"
|
|
line.long 0x1C4 "JPEG_HUFFSYMB1,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. "DATA7,Data 7"
|
|
hexmask.long.byte 0x1C4 16.--23. 1. "DATA6,Data 6"
|
|
newline
|
|
hexmask.long.byte 0x1C4 8.--15. 1. "DATA5,Data 5"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. "DATA4,Data 4"
|
|
line.long 0x1C8 "JPEG_HUFFSYMB2,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. "DATA11,Data 11"
|
|
hexmask.long.byte 0x1C8 16.--23. 1. "DATA10,Data 10"
|
|
newline
|
|
hexmask.long.byte 0x1C8 8.--15. 1. "DATA9,Data 9"
|
|
hexmask.long.byte 0x1C8 0.--7. 1. "DATA8,Data 8"
|
|
line.long 0x1CC "JPEG_HUFFSYMB3,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. "DATA15,Data 15"
|
|
hexmask.long.byte 0x1CC 16.--23. 1. "DATA14,Data 14"
|
|
newline
|
|
hexmask.long.byte 0x1CC 8.--15. 1. "DATA13,Data 13"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. "DATA12,Data 12"
|
|
line.long 0x1D0 "JPEG_HUFFSYMB4,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. "DATA19,Data 19"
|
|
hexmask.long.byte 0x1D0 16.--23. 1. "DATA18,Data 18"
|
|
newline
|
|
hexmask.long.byte 0x1D0 8.--15. 1. "DATA17,Data 17"
|
|
hexmask.long.byte 0x1D0 0.--7. 1. "DATA16,Data 16"
|
|
line.long 0x1D4 "JPEG_HUFFSYMB5,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. "DATA23,Data 23"
|
|
hexmask.long.byte 0x1D4 16.--23. 1. "DATA22,Data 22"
|
|
newline
|
|
hexmask.long.byte 0x1D4 8.--15. 1. "DATA21,Data 21"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. "DATA20,Data 20"
|
|
line.long 0x1D8 "JPEG_HUFFSYMB6,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. "DATA27,Data 27"
|
|
hexmask.long.byte 0x1D8 16.--23. 1. "DATA26,Data 26"
|
|
newline
|
|
hexmask.long.byte 0x1D8 8.--15. 1. "DATA25,Data 25"
|
|
hexmask.long.byte 0x1D8 0.--7. 1. "DATA24,Data 24"
|
|
line.long 0x1DC "JPEG_HUFFSYMB7,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. "DATA31,Data 31"
|
|
hexmask.long.byte 0x1DC 16.--23. 1. "DATA30,Data 30"
|
|
newline
|
|
hexmask.long.byte 0x1DC 8.--15. 1. "DATA29,Data 29"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. "DATA28,Data 28"
|
|
line.long 0x1E0 "JPEG_HUFFSYMB8,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. "DATA35,Data 35"
|
|
hexmask.long.byte 0x1E0 16.--23. 1. "DATA34,Data 34"
|
|
newline
|
|
hexmask.long.byte 0x1E0 8.--15. 1. "DATA33,Data 33"
|
|
hexmask.long.byte 0x1E0 0.--7. 1. "DATA32,Data 32"
|
|
line.long 0x1E4 "JPEG_HUFFSYMB9,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. "DATA39,Data 39"
|
|
hexmask.long.byte 0x1E4 16.--23. 1. "DATA38,Data 38"
|
|
newline
|
|
hexmask.long.byte 0x1E4 8.--15. 1. "DATA37,Data 37"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. "DATA36,Data 36"
|
|
line.long 0x1E8 "JPEG_HUFFSYMB10,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. "DATA43,Data 43"
|
|
hexmask.long.byte 0x1E8 16.--23. 1. "DATA42,Data 42"
|
|
newline
|
|
hexmask.long.byte 0x1E8 8.--15. 1. "DATA41,Data 41"
|
|
hexmask.long.byte 0x1E8 0.--7. 1. "DATA40,Data 40"
|
|
line.long 0x1EC "JPEG_HUFFSYMB11,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. "DATA47,Data 47"
|
|
hexmask.long.byte 0x1EC 16.--23. 1. "DATA46,Data 46"
|
|
newline
|
|
hexmask.long.byte 0x1EC 8.--15. 1. "DATA45,Data 45"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. "DATA44,Data 44"
|
|
line.long 0x1F0 "JPEG_HUFFSYMB12,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. "DATA51,Data 51"
|
|
hexmask.long.byte 0x1F0 16.--23. 1. "DATA50,Data 50"
|
|
newline
|
|
hexmask.long.byte 0x1F0 8.--15. 1. "DATA49,Data 49"
|
|
hexmask.long.byte 0x1F0 0.--7. 1. "DATA48,Data 48"
|
|
line.long 0x1F4 "JPEG_HUFFSYMB13,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. "DATA55,Data 55"
|
|
hexmask.long.byte 0x1F4 16.--23. 1. "DATA54,Data 54"
|
|
newline
|
|
hexmask.long.byte 0x1F4 8.--15. 1. "DATA53,Data 53"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. "DATA52,Data 52"
|
|
line.long 0x1F8 "JPEG_HUFFSYMB14,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. "DATA59,Data 59"
|
|
hexmask.long.byte 0x1F8 16.--23. 1. "DATA58,Data 58"
|
|
newline
|
|
hexmask.long.byte 0x1F8 8.--15. 1. "DATA57,Data 57"
|
|
hexmask.long.byte 0x1F8 0.--7. 1. "DATA56,Data 56"
|
|
line.long 0x1FC "JPEG_HUFFSYMB15,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. "DATA63,Data 63"
|
|
hexmask.long.byte 0x1FC 16.--23. 1. "DATA62,Data 62"
|
|
newline
|
|
hexmask.long.byte 0x1FC 8.--15. 1. "DATA61,Data 61"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. "DATA60,Data 60"
|
|
line.long 0x200 "JPEG_HUFFSYMB16,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x200 24.--31. 1. "DATA67,Data 67"
|
|
hexmask.long.byte 0x200 16.--23. 1. "DATA66,Data 66"
|
|
newline
|
|
hexmask.long.byte 0x200 8.--15. 1. "DATA65,Data 65"
|
|
hexmask.long.byte 0x200 0.--7. 1. "DATA64,Data 64"
|
|
line.long 0x204 "JPEG_HUFFSYMB17,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x204 24.--31. 1. "DATA71,Data 71"
|
|
hexmask.long.byte 0x204 16.--23. 1. "DATA70,Data 70"
|
|
newline
|
|
hexmask.long.byte 0x204 8.--15. 1. "DATA69,Data 69"
|
|
hexmask.long.byte 0x204 0.--7. 1. "DATA68,Data 68"
|
|
line.long 0x208 "JPEG_HUFFSYMB18,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x208 24.--31. 1. "DATA75,Data 75"
|
|
hexmask.long.byte 0x208 16.--23. 1. "DATA74,Data 74"
|
|
newline
|
|
hexmask.long.byte 0x208 8.--15. 1. "DATA73,Data 73"
|
|
hexmask.long.byte 0x208 0.--7. 1. "DATA72,Data 72"
|
|
line.long 0x20C "JPEG_HUFFSYMB19,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x20C 24.--31. 1. "DATA79,Data 79"
|
|
hexmask.long.byte 0x20C 16.--23. 1. "DATA78,Data 78"
|
|
newline
|
|
hexmask.long.byte 0x20C 8.--15. 1. "DATA77,Data 77"
|
|
hexmask.long.byte 0x20C 0.--7. 1. "DATA76,Data 76"
|
|
line.long 0x210 "JPEG_HUFFSYMB20,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x210 24.--31. 1. "DATA83,Data 83"
|
|
hexmask.long.byte 0x210 16.--23. 1. "DATA82,Data 82"
|
|
newline
|
|
hexmask.long.byte 0x210 8.--15. 1. "DATA81,Data 81"
|
|
hexmask.long.byte 0x210 0.--7. 1. "DATA80,Data 80"
|
|
line.long 0x214 "JPEG_HUFFSYMB21,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x214 24.--31. 1. "DATA87,Data 87"
|
|
hexmask.long.byte 0x214 16.--23. 1. "DATA86,Data 86"
|
|
newline
|
|
hexmask.long.byte 0x214 8.--15. 1. "DATA85,Data 85"
|
|
hexmask.long.byte 0x214 0.--7. 1. "DATA84,Data 84"
|
|
line.long 0x218 "JPEG_HUFFSYMB22,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x218 24.--31. 1. "DATA91,Data 91"
|
|
hexmask.long.byte 0x218 16.--23. 1. "DATA90,Data 90"
|
|
newline
|
|
hexmask.long.byte 0x218 8.--15. 1. "DATA89,Data 89"
|
|
hexmask.long.byte 0x218 0.--7. 1. "DATA88,Data 88"
|
|
line.long 0x21C "JPEG_HUFFSYMB23,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x21C 24.--31. 1. "DATA95,Data 95"
|
|
hexmask.long.byte 0x21C 16.--23. 1. "DATA94,Data 94"
|
|
newline
|
|
hexmask.long.byte 0x21C 8.--15. 1. "DATA93,Data 93"
|
|
hexmask.long.byte 0x21C 0.--7. 1. "DATA92,Data 92"
|
|
line.long 0x220 "JPEG_HUFFSYMB24,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x220 24.--31. 1. "DATA99,Data 99"
|
|
hexmask.long.byte 0x220 16.--23. 1. "DATA98,Data 98"
|
|
newline
|
|
hexmask.long.byte 0x220 8.--15. 1. "DATA97,Data 97"
|
|
hexmask.long.byte 0x220 0.--7. 1. "DATA96,Data 96"
|
|
line.long 0x224 "JPEG_HUFFSYMB25,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x224 24.--31. 1. "DATA103,Data 103"
|
|
hexmask.long.byte 0x224 16.--23. 1. "DATA102,Data 102"
|
|
newline
|
|
hexmask.long.byte 0x224 8.--15. 1. "DATA101,Data 101"
|
|
hexmask.long.byte 0x224 0.--7. 1. "DATA100,Data 100"
|
|
line.long 0x228 "JPEG_HUFFSYMB26,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x228 24.--31. 1. "DATA107,Data 107"
|
|
hexmask.long.byte 0x228 16.--23. 1. "DATA106,Data 106"
|
|
newline
|
|
hexmask.long.byte 0x228 8.--15. 1. "DATA105,Data 105"
|
|
hexmask.long.byte 0x228 0.--7. 1. "DATA104,Data 104"
|
|
line.long 0x22C "JPEG_HUFFSYMB27,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x22C 24.--31. 1. "DATA111,Data 111"
|
|
hexmask.long.byte 0x22C 16.--23. 1. "DATA110,Data 110"
|
|
newline
|
|
hexmask.long.byte 0x22C 8.--15. 1. "DATA109,Data 109"
|
|
hexmask.long.byte 0x22C 0.--7. 1. "DATA108,Data 108"
|
|
line.long 0x230 "JPEG_HUFFSYMB28,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x230 24.--31. 1. "DATA115,Data 115"
|
|
hexmask.long.byte 0x230 16.--23. 1. "DATA114,Data 114"
|
|
newline
|
|
hexmask.long.byte 0x230 8.--15. 1. "DATA113,Data 113"
|
|
hexmask.long.byte 0x230 0.--7. 1. "DATA112,Data 112"
|
|
line.long 0x234 "JPEG_HUFFSYMB29,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x234 24.--31. 1. "DATA119,Data 119"
|
|
hexmask.long.byte 0x234 16.--23. 1. "DATA118,Data 118"
|
|
newline
|
|
hexmask.long.byte 0x234 8.--15. 1. "DATA117,Data 117"
|
|
hexmask.long.byte 0x234 0.--7. 1. "DATA116,Data 116"
|
|
line.long 0x238 "JPEG_HUFFSYMB30,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x238 24.--31. 1. "DATA123,Data 123"
|
|
hexmask.long.byte 0x238 16.--23. 1. "DATA122,Data 122"
|
|
newline
|
|
hexmask.long.byte 0x238 8.--15. 1. "DATA121,Data 121"
|
|
hexmask.long.byte 0x238 0.--7. 1. "DATA120,Data 120"
|
|
line.long 0x23C "JPEG_HUFFSYMB31,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x23C 24.--31. 1. "DATA127,Data 127"
|
|
hexmask.long.byte 0x23C 16.--23. 1. "DATA126,Data 126"
|
|
newline
|
|
hexmask.long.byte 0x23C 8.--15. 1. "DATA125,Data 125"
|
|
hexmask.long.byte 0x23C 0.--7. 1. "DATA124,Data 124"
|
|
line.long 0x240 "JPEG_HUFFSYMB32,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x240 24.--31. 1. "DATA131,Data 131"
|
|
hexmask.long.byte 0x240 16.--23. 1. "DATA130,Data 130"
|
|
newline
|
|
hexmask.long.byte 0x240 8.--15. 1. "DATA129,Data 129"
|
|
hexmask.long.byte 0x240 0.--7. 1. "DATA128,Data 128"
|
|
line.long 0x244 "JPEG_HUFFSYMB33,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x244 24.--31. 1. "DATA135,Data 135"
|
|
hexmask.long.byte 0x244 16.--23. 1. "DATA134,Data 134"
|
|
newline
|
|
hexmask.long.byte 0x244 8.--15. 1. "DATA133,Data 133"
|
|
hexmask.long.byte 0x244 0.--7. 1. "DATA132,Data 132"
|
|
line.long 0x248 "JPEG_HUFFSYMB34,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x248 24.--31. 1. "DATA139,Data 139"
|
|
hexmask.long.byte 0x248 16.--23. 1. "DATA138,Data 138"
|
|
newline
|
|
hexmask.long.byte 0x248 8.--15. 1. "DATA137,Data 137"
|
|
hexmask.long.byte 0x248 0.--7. 1. "DATA136,Data 136"
|
|
line.long 0x24C "JPEG_HUFFSYMB35,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x24C 24.--31. 1. "DATA143,Data 143"
|
|
hexmask.long.byte 0x24C 16.--23. 1. "DATA142,Data 142"
|
|
newline
|
|
hexmask.long.byte 0x24C 8.--15. 1. "DATA141,Data 141"
|
|
hexmask.long.byte 0x24C 0.--7. 1. "DATA140,Data 140"
|
|
line.long 0x250 "JPEG_HUFFSYMB36,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x250 24.--31. 1. "DATA147,Data 147"
|
|
hexmask.long.byte 0x250 16.--23. 1. "DATA146,Data 146"
|
|
newline
|
|
hexmask.long.byte 0x250 8.--15. 1. "DATA145,Data 145"
|
|
hexmask.long.byte 0x250 0.--7. 1. "DATA144,Data 144"
|
|
line.long 0x254 "JPEG_HUFFSYMB37,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x254 24.--31. 1. "DATA151,Data 151"
|
|
hexmask.long.byte 0x254 16.--23. 1. "DATA150,Data 150"
|
|
newline
|
|
hexmask.long.byte 0x254 8.--15. 1. "DATA149,Data 149"
|
|
hexmask.long.byte 0x254 0.--7. 1. "DATA148,Data 148"
|
|
line.long 0x258 "JPEG_HUFFSYMB38,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x258 24.--31. 1. "DATA155,Data 155"
|
|
hexmask.long.byte 0x258 16.--23. 1. "DATA154,Data 154"
|
|
newline
|
|
hexmask.long.byte 0x258 8.--15. 1. "DATA153,Data 153"
|
|
hexmask.long.byte 0x258 0.--7. 1. "DATA152,Data 152"
|
|
line.long 0x25C "JPEG_HUFFSYMB39,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x25C 24.--31. 1. "DATA159,Data 159"
|
|
hexmask.long.byte 0x25C 16.--23. 1. "DATA158,Data 158"
|
|
newline
|
|
hexmask.long.byte 0x25C 8.--15. 1. "DATA157,Data 157"
|
|
hexmask.long.byte 0x25C 0.--7. 1. "DATA156,Data 156"
|
|
line.long 0x260 "JPEG_HUFFSYMB40,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x260 24.--31. 1. "DATA163,Data 163"
|
|
hexmask.long.byte 0x260 16.--23. 1. "DATA162,Data 162"
|
|
newline
|
|
hexmask.long.byte 0x260 8.--15. 1. "DATA161,Data 161"
|
|
hexmask.long.byte 0x260 0.--7. 1. "DATA160,Data 160"
|
|
line.long 0x264 "JPEG_HUFFSYMB41,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x264 24.--31. 1. "DATA167,Data 167"
|
|
hexmask.long.byte 0x264 16.--23. 1. "DATA166,Data 166"
|
|
newline
|
|
hexmask.long.byte 0x264 8.--15. 1. "DATA165,Data 165"
|
|
hexmask.long.byte 0x264 0.--7. 1. "DATA164,Data 164"
|
|
line.long 0x268 "JPEG_HUFFSYMB42,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x268 24.--31. 1. "DATA171,Data 171"
|
|
hexmask.long.byte 0x268 16.--23. 1. "DATA170,Data 170"
|
|
newline
|
|
hexmask.long.byte 0x268 8.--15. 1. "DATA169,Data 169"
|
|
hexmask.long.byte 0x268 0.--7. 1. "DATA168,Data 168"
|
|
line.long 0x26C "JPEG_HUFFSYMB43,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x26C 24.--31. 1. "DATA175,Data 175"
|
|
hexmask.long.byte 0x26C 16.--23. 1. "DATA174,Data 174"
|
|
newline
|
|
hexmask.long.byte 0x26C 8.--15. 1. "DATA173,Data 173"
|
|
hexmask.long.byte 0x26C 0.--7. 1. "DATA172,Data 172"
|
|
line.long 0x270 "JPEG_HUFFSYMB44,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x270 24.--31. 1. "DATA179,Data 179"
|
|
hexmask.long.byte 0x270 16.--23. 1. "DATA178,Data 178"
|
|
newline
|
|
hexmask.long.byte 0x270 8.--15. 1. "DATA177,Data 177"
|
|
hexmask.long.byte 0x270 0.--7. 1. "DATA176,Data 176"
|
|
line.long 0x274 "JPEG_HUFFSYMB45,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x274 24.--31. 1. "DATA183,Data 183"
|
|
hexmask.long.byte 0x274 16.--23. 1. "DATA182,Data 182"
|
|
newline
|
|
hexmask.long.byte 0x274 8.--15. 1. "DATA181,Data 181"
|
|
hexmask.long.byte 0x274 0.--7. 1. "DATA180,Data 180"
|
|
line.long 0x278 "JPEG_HUFFSYMB46,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x278 24.--31. 1. "DATA187,Data 187"
|
|
hexmask.long.byte 0x278 16.--23. 1. "DATA186,Data 186"
|
|
newline
|
|
hexmask.long.byte 0x278 8.--15. 1. "DATA185,Data 185"
|
|
hexmask.long.byte 0x278 0.--7. 1. "DATA184,Data 184"
|
|
line.long 0x27C "JPEG_HUFFSYMB47,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x27C 24.--31. 1. "DATA191,Data 191"
|
|
hexmask.long.byte 0x27C 16.--23. 1. "DATA190,Data 190"
|
|
newline
|
|
hexmask.long.byte 0x27C 8.--15. 1. "DATA189,Data 189"
|
|
hexmask.long.byte 0x27C 0.--7. 1. "DATA188,Data 188"
|
|
line.long 0x280 "JPEG_HUFFSYMB48,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x280 24.--31. 1. "DATA195,Data 195"
|
|
hexmask.long.byte 0x280 16.--23. 1. "DATA194,Data 194"
|
|
newline
|
|
hexmask.long.byte 0x280 8.--15. 1. "DATA193,Data 193"
|
|
hexmask.long.byte 0x280 0.--7. 1. "DATA192,Data 192"
|
|
line.long 0x284 "JPEG_HUFFSYMB49,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x284 24.--31. 1. "DATA199,Data 199"
|
|
hexmask.long.byte 0x284 16.--23. 1. "DATA198,Data 198"
|
|
newline
|
|
hexmask.long.byte 0x284 8.--15. 1. "DATA197,Data 197"
|
|
hexmask.long.byte 0x284 0.--7. 1. "DATA196,Data 196"
|
|
line.long 0x288 "JPEG_HUFFSYMB50,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x288 24.--31. 1. "DATA203,Data 203"
|
|
hexmask.long.byte 0x288 16.--23. 1. "DATA202,Data 202"
|
|
newline
|
|
hexmask.long.byte 0x288 8.--15. 1. "DATA201,Data 201"
|
|
hexmask.long.byte 0x288 0.--7. 1. "DATA200,Data 200"
|
|
line.long 0x28C "JPEG_HUFFSYMB51,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x28C 24.--31. 1. "DATA207,Data 207"
|
|
hexmask.long.byte 0x28C 16.--23. 1. "DATA206,Data 206"
|
|
newline
|
|
hexmask.long.byte 0x28C 8.--15. 1. "DATA205,Data 205"
|
|
hexmask.long.byte 0x28C 0.--7. 1. "DATA204,Data 204"
|
|
line.long 0x290 "JPEG_HUFFSYMB52,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x290 24.--31. 1. "DATA211,Data 211"
|
|
hexmask.long.byte 0x290 16.--23. 1. "DATA210,Data 210"
|
|
newline
|
|
hexmask.long.byte 0x290 8.--15. 1. "DATA209,Data 209"
|
|
hexmask.long.byte 0x290 0.--7. 1. "DATA208,Data 208"
|
|
line.long 0x294 "JPEG_HUFFSYMB53,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x294 24.--31. 1. "DATA215,Data 215"
|
|
hexmask.long.byte 0x294 16.--23. 1. "DATA214,Data 214"
|
|
newline
|
|
hexmask.long.byte 0x294 8.--15. 1. "DATA213,Data 213"
|
|
hexmask.long.byte 0x294 0.--7. 1. "DATA212,Data 212"
|
|
line.long 0x298 "JPEG_HUFFSYMB54,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x298 24.--31. 1. "DATA219,Data 219"
|
|
hexmask.long.byte 0x298 16.--23. 1. "DATA218,Data 218"
|
|
newline
|
|
hexmask.long.byte 0x298 8.--15. 1. "DATA217,Data 217"
|
|
hexmask.long.byte 0x298 0.--7. 1. "DATA216,Data 216"
|
|
line.long 0x29C "JPEG_HUFFSYMB55,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x29C 24.--31. 1. "DATA223,Data 223"
|
|
hexmask.long.byte 0x29C 16.--23. 1. "DATA222,Data 222"
|
|
newline
|
|
hexmask.long.byte 0x29C 8.--15. 1. "DATA221,Data 221"
|
|
hexmask.long.byte 0x29C 0.--7. 1. "DATA220,Data 220"
|
|
line.long 0x2A0 "JPEG_HUFFSYMB56,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. "DATA227,Data 227"
|
|
hexmask.long.byte 0x2A0 16.--23. 1. "DATA226,Data 226"
|
|
newline
|
|
hexmask.long.byte 0x2A0 8.--15. 1. "DATA225,Data 225"
|
|
hexmask.long.byte 0x2A0 0.--7. 1. "DATA224,Data 224"
|
|
line.long 0x2A4 "JPEG_HUFFSYMB57,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. "DATA231,Data 231"
|
|
hexmask.long.byte 0x2A4 16.--23. 1. "DATA230,Data 230"
|
|
newline
|
|
hexmask.long.byte 0x2A4 8.--15. 1. "DATA229,Data 229"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. "DATA228,Data 228"
|
|
line.long 0x2A8 "JPEG_HUFFSYMB58,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. "DATA235,Data 235"
|
|
hexmask.long.byte 0x2A8 16.--23. 1. "DATA234,Data 234"
|
|
newline
|
|
hexmask.long.byte 0x2A8 8.--15. 1. "DATA233,Data 233"
|
|
hexmask.long.byte 0x2A8 0.--7. 1. "DATA232,Data 232"
|
|
line.long 0x2AC "JPEG_HUFFSYMB59,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. "DATA239,Data 239"
|
|
hexmask.long.byte 0x2AC 16.--23. 1. "DATA238,Data 238"
|
|
newline
|
|
hexmask.long.byte 0x2AC 8.--15. 1. "DATA237,Data 237"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. "DATA236,Data 236"
|
|
line.long 0x2B0 "JPEG_HUFFSYMB60,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. "DATA243,Data 243"
|
|
hexmask.long.byte 0x2B0 16.--23. 1. "DATA242,Data 242"
|
|
newline
|
|
hexmask.long.byte 0x2B0 8.--15. 1. "DATA241,Data 241"
|
|
hexmask.long.byte 0x2B0 0.--7. 1. "DATA240,Data 240"
|
|
line.long 0x2B4 "JPEG_HUFFSYMB61,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. "DATA247,Data 247"
|
|
hexmask.long.byte 0x2B4 16.--23. 1. "DATA246,Data 246"
|
|
newline
|
|
hexmask.long.byte 0x2B4 8.--15. 1. "DATA245,Data 245"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. "DATA244,Data 244"
|
|
line.long 0x2B8 "JPEG_HUFFSYMB62,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. "DATA251,Data 251"
|
|
hexmask.long.byte 0x2B8 16.--23. 1. "DATA250,Data 250"
|
|
newline
|
|
hexmask.long.byte 0x2B8 8.--15. 1. "DATA249,Data 249"
|
|
hexmask.long.byte 0x2B8 0.--7. 1. "DATA248,Data 248"
|
|
line.long 0x2BC "JPEG_HUFFSYMB63,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. "DATA255,Data 255"
|
|
hexmask.long.byte 0x2BC 16.--23. 1. "DATA254,Data 254"
|
|
newline
|
|
hexmask.long.byte 0x2BC 8.--15. 1. "DATA253,Data 253"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. "DATA252,Data 252"
|
|
line.long 0x2C0 "JPEG_HUFFSYMB64,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. "DATA259,Data 259"
|
|
hexmask.long.byte 0x2C0 16.--23. 1. "DATA258,Data 258"
|
|
newline
|
|
hexmask.long.byte 0x2C0 8.--15. 1. "DATA257,Data 257"
|
|
hexmask.long.byte 0x2C0 0.--7. 1. "DATA256,Data 256"
|
|
line.long 0x2C4 "JPEG_HUFFSYMB65,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. "DATA263,Data 263"
|
|
hexmask.long.byte 0x2C4 16.--23. 1. "DATA262,Data 262"
|
|
newline
|
|
hexmask.long.byte 0x2C4 8.--15. 1. "DATA261,Data 261"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. "DATA260,Data 260"
|
|
line.long 0x2C8 "JPEG_HUFFSYMB66,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. "DATA267,Data 267"
|
|
hexmask.long.byte 0x2C8 16.--23. 1. "DATA266,Data 266"
|
|
newline
|
|
hexmask.long.byte 0x2C8 8.--15. 1. "DATA265,Data 265"
|
|
hexmask.long.byte 0x2C8 0.--7. 1. "DATA264,Data 264"
|
|
line.long 0x2CC "JPEG_HUFFSYMB67,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. "DATA271,Data 271"
|
|
hexmask.long.byte 0x2CC 16.--23. 1. "DATA270,Data 270"
|
|
newline
|
|
hexmask.long.byte 0x2CC 8.--15. 1. "DATA269,Data 269"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. "DATA268,Data 268"
|
|
line.long 0x2D0 "JPEG_HUFFSYMB68,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. "DATA275,Data 275"
|
|
hexmask.long.byte 0x2D0 16.--23. 1. "DATA274,Data 274"
|
|
newline
|
|
hexmask.long.byte 0x2D0 8.--15. 1. "DATA273,Data 273"
|
|
hexmask.long.byte 0x2D0 0.--7. 1. "DATA272,Data 272"
|
|
line.long 0x2D4 "JPEG_HUFFSYMB69,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. "DATA279,Data 279"
|
|
hexmask.long.byte 0x2D4 16.--23. 1. "DATA278,Data 278"
|
|
newline
|
|
hexmask.long.byte 0x2D4 8.--15. 1. "DATA277,Data 277"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. "DATA276,Data 276"
|
|
line.long 0x2D8 "JPEG_HUFFSYMB70,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. "DATA283,Data 283"
|
|
hexmask.long.byte 0x2D8 16.--23. 1. "DATA282,Data 282"
|
|
newline
|
|
hexmask.long.byte 0x2D8 8.--15. 1. "DATA281,Data 281"
|
|
hexmask.long.byte 0x2D8 0.--7. 1. "DATA280,Data 280"
|
|
line.long 0x2DC "JPEG_HUFFSYMB71,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. "DATA287,Data 287"
|
|
hexmask.long.byte 0x2DC 16.--23. 1. "DATA286,Data 286"
|
|
newline
|
|
hexmask.long.byte 0x2DC 8.--15. 1. "DATA285,Data 285"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. "DATA284,Data 284"
|
|
line.long 0x2E0 "JPEG_HUFFSYMB72,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. "DATA291,Data 291"
|
|
hexmask.long.byte 0x2E0 16.--23. 1. "DATA290,Data 290"
|
|
newline
|
|
hexmask.long.byte 0x2E0 8.--15. 1. "DATA289,Data 289"
|
|
hexmask.long.byte 0x2E0 0.--7. 1. "DATA288,Data 288"
|
|
line.long 0x2E4 "JPEG_HUFFSYMB73,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. "DATA295,Data 295"
|
|
hexmask.long.byte 0x2E4 16.--23. 1. "DATA294,Data 294"
|
|
newline
|
|
hexmask.long.byte 0x2E4 8.--15. 1. "DATA293,Data 293"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. "DATA292,Data 292"
|
|
line.long 0x2E8 "JPEG_HUFFSYMB74,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. "DATA299,Data 299"
|
|
hexmask.long.byte 0x2E8 16.--23. 1. "DATA298,Data 298"
|
|
newline
|
|
hexmask.long.byte 0x2E8 8.--15. 1. "DATA297,Data 297"
|
|
hexmask.long.byte 0x2E8 0.--7. 1. "DATA296,Data 296"
|
|
line.long 0x2EC "JPEG_HUFFSYMB75,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. "DATA303,Data 303"
|
|
hexmask.long.byte 0x2EC 16.--23. 1. "DATA302,Data 302"
|
|
newline
|
|
hexmask.long.byte 0x2EC 8.--15. 1. "DATA301,Data 301"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. "DATA300,Data 300"
|
|
line.long 0x2F0 "JPEG_HUFFSYMB76,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. "DATA307,Data 307"
|
|
hexmask.long.byte 0x2F0 16.--23. 1. "DATA306,Data 306"
|
|
newline
|
|
hexmask.long.byte 0x2F0 8.--15. 1. "DATA305,Data 305"
|
|
hexmask.long.byte 0x2F0 0.--7. 1. "DATA304,Data 304"
|
|
line.long 0x2F4 "JPEG_HUFFSYMB77,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. "DATA311,Data 311"
|
|
hexmask.long.byte 0x2F4 16.--23. 1. "DATA310,Data 310"
|
|
newline
|
|
hexmask.long.byte 0x2F4 8.--15. 1. "DATA309,Data 309"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. "DATA308,Data 308"
|
|
line.long 0x2F8 "JPEG_HUFFSYMB78,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. "DATA315,Data 315"
|
|
hexmask.long.byte 0x2F8 16.--23. 1. "DATA314,Data 314"
|
|
newline
|
|
hexmask.long.byte 0x2F8 8.--15. 1. "DATA313,Data 313"
|
|
hexmask.long.byte 0x2F8 0.--7. 1. "DATA312,Data 312"
|
|
line.long 0x2FC "JPEG_HUFFSYMB79,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. "DATA319,Data 319"
|
|
hexmask.long.byte 0x2FC 16.--23. 1. "DATA318,Data 318"
|
|
newline
|
|
hexmask.long.byte 0x2FC 8.--15. 1. "DATA317,Data 317"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. "DATA316,Data 316"
|
|
line.long 0x300 "JPEG_HUFFSYMB80,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x300 24.--31. 1. "DATA323,Data 323"
|
|
hexmask.long.byte 0x300 16.--23. 1. "DATA322,Data 322"
|
|
newline
|
|
hexmask.long.byte 0x300 8.--15. 1. "DATA321,Data 321"
|
|
hexmask.long.byte 0x300 0.--7. 1. "DATA320,Data 320"
|
|
line.long 0x304 "JPEG_HUFFSYMB81,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x304 24.--31. 1. "DATA327,Data 327"
|
|
hexmask.long.byte 0x304 16.--23. 1. "DATA326,Data 326"
|
|
newline
|
|
hexmask.long.byte 0x304 8.--15. 1. "DATA325,Data 325"
|
|
hexmask.long.byte 0x304 0.--7. 1. "DATA324,Data 324"
|
|
line.long 0x308 "JPEG_HUFFSYMB82,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x308 24.--31. 1. "DATA331,Data 331"
|
|
hexmask.long.byte 0x308 16.--23. 1. "DATA330,Data 330"
|
|
newline
|
|
hexmask.long.byte 0x308 8.--15. 1. "DATA329,Data 329"
|
|
hexmask.long.byte 0x308 0.--7. 1. "DATA328,Data 328"
|
|
line.long 0x30C "JPEG_HUFFSYMB83,JPEG Huffman symbol"
|
|
hexmask.long.byte 0x30C 24.--31. 1. "DATA335,Data 335"
|
|
hexmask.long.byte 0x30C 16.--23. 1. "DATA334,Data 334"
|
|
newline
|
|
hexmask.long.byte 0x30C 8.--15. 1. "DATA333,Data 333"
|
|
hexmask.long.byte 0x30C 0.--7. 1. "DATA332,Data 332"
|
|
line.long 0x310 "JPEG_DHTMEM0,JPEG DHT memory"
|
|
hexmask.long.byte 0x310 24.--31. 1. "DATA3,Huffman table data 3"
|
|
hexmask.long.byte 0x310 16.--23. 1. "DATA2,Huffman table data 2"
|
|
newline
|
|
hexmask.long.byte 0x310 8.--15. 1. "DATA1,Huffman table data 1"
|
|
hexmask.long.byte 0x310 0.--7. 1. "DATA0,Huffman table data 0"
|
|
line.long 0x314 "JPEG_DHTMEM1,JPEG DHT memory"
|
|
hexmask.long.byte 0x314 24.--31. 1. "DATA7,Huffman table data 7"
|
|
hexmask.long.byte 0x314 16.--23. 1. "DATA6,Huffman table data 6"
|
|
newline
|
|
hexmask.long.byte 0x314 8.--15. 1. "DATA5,Huffman table data 5"
|
|
hexmask.long.byte 0x314 0.--7. 1. "DATA4,Huffman table data 4"
|
|
line.long 0x318 "JPEG_DHTMEM2,JPEG DHT memory"
|
|
hexmask.long.byte 0x318 24.--31. 1. "DATA11,Huffman table data 11"
|
|
hexmask.long.byte 0x318 16.--23. 1. "DATA10,Huffman table data 10"
|
|
newline
|
|
hexmask.long.byte 0x318 8.--15. 1. "DATA9,Huffman table data 9"
|
|
hexmask.long.byte 0x318 0.--7. 1. "DATA8,Huffman table data 8"
|
|
line.long 0x31C "JPEG_DHTMEM3,JPEG DHT memory"
|
|
hexmask.long.byte 0x31C 24.--31. 1. "DATA15,Huffman table data 15"
|
|
hexmask.long.byte 0x31C 16.--23. 1. "DATA14,Huffman table data 14"
|
|
newline
|
|
hexmask.long.byte 0x31C 8.--15. 1. "DATA13,Huffman table data 13"
|
|
hexmask.long.byte 0x31C 0.--7. 1. "DATA12,Huffman table data 12"
|
|
line.long 0x320 "JPEG_DHTMEM4,JPEG DHT memory"
|
|
hexmask.long.byte 0x320 24.--31. 1. "DATA19,Huffman table data 19"
|
|
hexmask.long.byte 0x320 16.--23. 1. "DATA18,Huffman table data 18"
|
|
newline
|
|
hexmask.long.byte 0x320 8.--15. 1. "DATA17,Huffman table data 17"
|
|
hexmask.long.byte 0x320 0.--7. 1. "DATA16,Huffman table data 16"
|
|
line.long 0x324 "JPEG_DHTMEM5,JPEG DHT memory"
|
|
hexmask.long.byte 0x324 24.--31. 1. "DATA23,Huffman table data 23"
|
|
hexmask.long.byte 0x324 16.--23. 1. "DATA22,Huffman table data 22"
|
|
newline
|
|
hexmask.long.byte 0x324 8.--15. 1. "DATA21,Huffman table data 21"
|
|
hexmask.long.byte 0x324 0.--7. 1. "DATA20,Huffman table data 20"
|
|
line.long 0x328 "JPEG_DHTMEM6,JPEG DHT memory"
|
|
hexmask.long.byte 0x328 24.--31. 1. "DATA27,Huffman table data 27"
|
|
hexmask.long.byte 0x328 16.--23. 1. "DATA26,Huffman table data 26"
|
|
newline
|
|
hexmask.long.byte 0x328 8.--15. 1. "DATA25,Huffman table data 25"
|
|
hexmask.long.byte 0x328 0.--7. 1. "DATA24,Huffman table data 24"
|
|
line.long 0x32C "JPEG_DHTMEM7,JPEG DHT memory"
|
|
hexmask.long.byte 0x32C 24.--31. 1. "DATA31,Huffman table data 31"
|
|
hexmask.long.byte 0x32C 16.--23. 1. "DATA30,Huffman table data 30"
|
|
newline
|
|
hexmask.long.byte 0x32C 8.--15. 1. "DATA29,Huffman table data 29"
|
|
hexmask.long.byte 0x32C 0.--7. 1. "DATA28,Huffman table data 28"
|
|
line.long 0x330 "JPEG_DHTMEM8,JPEG DHT memory"
|
|
hexmask.long.byte 0x330 24.--31. 1. "DATA35,Huffman table data 35"
|
|
hexmask.long.byte 0x330 16.--23. 1. "DATA34,Huffman table data 34"
|
|
newline
|
|
hexmask.long.byte 0x330 8.--15. 1. "DATA33,Huffman table data 33"
|
|
hexmask.long.byte 0x330 0.--7. 1. "DATA32,Huffman table data 32"
|
|
line.long 0x334 "JPEG_DHTMEM9,JPEG DHT memory"
|
|
hexmask.long.byte 0x334 24.--31. 1. "DATA39,Huffman table data 39"
|
|
hexmask.long.byte 0x334 16.--23. 1. "DATA38,Huffman table data 38"
|
|
newline
|
|
hexmask.long.byte 0x334 8.--15. 1. "DATA37,Huffman table data 37"
|
|
hexmask.long.byte 0x334 0.--7. 1. "DATA36,Huffman table data 36"
|
|
line.long 0x338 "JPEG_DHTMEM10,JPEG DHT memory"
|
|
hexmask.long.byte 0x338 24.--31. 1. "DATA43,Huffman table data 43"
|
|
hexmask.long.byte 0x338 16.--23. 1. "DATA42,Huffman table data 42"
|
|
newline
|
|
hexmask.long.byte 0x338 8.--15. 1. "DATA41,Huffman table data 41"
|
|
hexmask.long.byte 0x338 0.--7. 1. "DATA40,Huffman table data 40"
|
|
line.long 0x33C "JPEG_DHTMEM11,JPEG DHT memory"
|
|
hexmask.long.byte 0x33C 24.--31. 1. "DATA47,Huffman table data 47"
|
|
hexmask.long.byte 0x33C 16.--23. 1. "DATA46,Huffman table data 46"
|
|
newline
|
|
hexmask.long.byte 0x33C 8.--15. 1. "DATA45,Huffman table data 45"
|
|
hexmask.long.byte 0x33C 0.--7. 1. "DATA44,Huffman table data 44"
|
|
line.long 0x340 "JPEG_DHTMEM12,JPEG DHT memory"
|
|
hexmask.long.byte 0x340 24.--31. 1. "DATA51,Huffman table data 51"
|
|
hexmask.long.byte 0x340 16.--23. 1. "DATA50,Huffman table data 50"
|
|
newline
|
|
hexmask.long.byte 0x340 8.--15. 1. "DATA49,Huffman table data 49"
|
|
hexmask.long.byte 0x340 0.--7. 1. "DATA48,Huffman table data 48"
|
|
line.long 0x344 "JPEG_DHTMEM13,JPEG DHT memory"
|
|
hexmask.long.byte 0x344 24.--31. 1. "DATA55,Huffman table data 55"
|
|
hexmask.long.byte 0x344 16.--23. 1. "DATA54,Huffman table data 54"
|
|
newline
|
|
hexmask.long.byte 0x344 8.--15. 1. "DATA53,Huffman table data 53"
|
|
hexmask.long.byte 0x344 0.--7. 1. "DATA52,Huffman table data 52"
|
|
line.long 0x348 "JPEG_DHTMEM14,JPEG DHT memory"
|
|
hexmask.long.byte 0x348 24.--31. 1. "DATA59,Huffman table data 59"
|
|
hexmask.long.byte 0x348 16.--23. 1. "DATA58,Huffman table data 58"
|
|
newline
|
|
hexmask.long.byte 0x348 8.--15. 1. "DATA57,Huffman table data 57"
|
|
hexmask.long.byte 0x348 0.--7. 1. "DATA56,Huffman table data 56"
|
|
line.long 0x34C "JPEG_DHTMEM15,JPEG DHT memory"
|
|
hexmask.long.byte 0x34C 24.--31. 1. "DATA63,Huffman table data 63"
|
|
hexmask.long.byte 0x34C 16.--23. 1. "DATA62,Huffman table data 62"
|
|
newline
|
|
hexmask.long.byte 0x34C 8.--15. 1. "DATA61,Huffman table data 61"
|
|
hexmask.long.byte 0x34C 0.--7. 1. "DATA60,Huffman table data 60"
|
|
line.long 0x350 "JPEG_DHTMEM16,JPEG DHT memory"
|
|
hexmask.long.byte 0x350 24.--31. 1. "DATA67,Huffman table data 67"
|
|
hexmask.long.byte 0x350 16.--23. 1. "DATA66,Huffman table data 66"
|
|
newline
|
|
hexmask.long.byte 0x350 8.--15. 1. "DATA65,Huffman table data 65"
|
|
hexmask.long.byte 0x350 0.--7. 1. "DATA64,Huffman table data 64"
|
|
line.long 0x354 "JPEG_DHTMEM17,JPEG DHT memory"
|
|
hexmask.long.byte 0x354 24.--31. 1. "DATA71,Huffman table data 71"
|
|
hexmask.long.byte 0x354 16.--23. 1. "DATA70,Huffman table data 70"
|
|
newline
|
|
hexmask.long.byte 0x354 8.--15. 1. "DATA69,Huffman table data 69"
|
|
hexmask.long.byte 0x354 0.--7. 1. "DATA68,Huffman table data 68"
|
|
line.long 0x358 "JPEG_DHTMEM18,JPEG DHT memory"
|
|
hexmask.long.byte 0x358 24.--31. 1. "DATA75,Huffman table data 75"
|
|
hexmask.long.byte 0x358 16.--23. 1. "DATA74,Huffman table data 74"
|
|
newline
|
|
hexmask.long.byte 0x358 8.--15. 1. "DATA73,Huffman table data 73"
|
|
hexmask.long.byte 0x358 0.--7. 1. "DATA72,Huffman table data 72"
|
|
line.long 0x35C "JPEG_DHTMEM19,JPEG DHT memory"
|
|
hexmask.long.byte 0x35C 24.--31. 1. "DATA79,Huffman table data 79"
|
|
hexmask.long.byte 0x35C 16.--23. 1. "DATA78,Huffman table data 78"
|
|
newline
|
|
hexmask.long.byte 0x35C 8.--15. 1. "DATA77,Huffman table data 77"
|
|
hexmask.long.byte 0x35C 0.--7. 1. "DATA76,Huffman table data 76"
|
|
line.long 0x360 "JPEG_DHTMEM20,JPEG DHT memory"
|
|
hexmask.long.byte 0x360 24.--31. 1. "DATA83,Huffman table data 83"
|
|
hexmask.long.byte 0x360 16.--23. 1. "DATA82,Huffman table data 82"
|
|
newline
|
|
hexmask.long.byte 0x360 8.--15. 1. "DATA81,Huffman table data 81"
|
|
hexmask.long.byte 0x360 0.--7. 1. "DATA80,Huffman table data 80"
|
|
line.long 0x364 "JPEG_DHTMEM21,JPEG DHT memory"
|
|
hexmask.long.byte 0x364 24.--31. 1. "DATA87,Huffman table data 87"
|
|
hexmask.long.byte 0x364 16.--23. 1. "DATA86,Huffman table data 86"
|
|
newline
|
|
hexmask.long.byte 0x364 8.--15. 1. "DATA85,Huffman table data 85"
|
|
hexmask.long.byte 0x364 0.--7. 1. "DATA84,Huffman table data 84"
|
|
line.long 0x368 "JPEG_DHTMEM22,JPEG DHT memory"
|
|
hexmask.long.byte 0x368 24.--31. 1. "DATA91,Huffman table data 91"
|
|
hexmask.long.byte 0x368 16.--23. 1. "DATA90,Huffman table data 90"
|
|
newline
|
|
hexmask.long.byte 0x368 8.--15. 1. "DATA89,Huffman table data 89"
|
|
hexmask.long.byte 0x368 0.--7. 1. "DATA88,Huffman table data 88"
|
|
line.long 0x36C "JPEG_DHTMEM23,JPEG DHT memory"
|
|
hexmask.long.byte 0x36C 24.--31. 1. "DATA95,Huffman table data 95"
|
|
hexmask.long.byte 0x36C 16.--23. 1. "DATA94,Huffman table data 94"
|
|
newline
|
|
hexmask.long.byte 0x36C 8.--15. 1. "DATA93,Huffman table data 93"
|
|
hexmask.long.byte 0x36C 0.--7. 1. "DATA92,Huffman table data 92"
|
|
line.long 0x370 "JPEG_DHTMEM24,JPEG DHT memory"
|
|
hexmask.long.byte 0x370 24.--31. 1. "DATA99,Huffman table data 99"
|
|
hexmask.long.byte 0x370 16.--23. 1. "DATA98,Huffman table data 98"
|
|
newline
|
|
hexmask.long.byte 0x370 8.--15. 1. "DATA97,Huffman table data 97"
|
|
hexmask.long.byte 0x370 0.--7. 1. "DATA96,Huffman table data 96"
|
|
line.long 0x374 "JPEG_DHTMEM25,JPEG DHT memory"
|
|
hexmask.long.byte 0x374 24.--31. 1. "DATA103,Huffman table data 103"
|
|
hexmask.long.byte 0x374 16.--23. 1. "DATA102,Huffman table data 102"
|
|
newline
|
|
hexmask.long.byte 0x374 8.--15. 1. "DATA101,Huffman table data 101"
|
|
hexmask.long.byte 0x374 0.--7. 1. "DATA100,Huffman table data 100"
|
|
line.long 0x378 "JPEG_DHTMEM26,JPEG DHT memory"
|
|
hexmask.long.byte 0x378 24.--31. 1. "DATA107,Huffman table data 107"
|
|
hexmask.long.byte 0x378 16.--23. 1. "DATA106,Huffman table data 106"
|
|
newline
|
|
hexmask.long.byte 0x378 8.--15. 1. "DATA105,Huffman table data 105"
|
|
hexmask.long.byte 0x378 0.--7. 1. "DATA104,Huffman table data 104"
|
|
line.long 0x37C "JPEG_DHTMEM27,JPEG DHT memory"
|
|
hexmask.long.byte 0x37C 24.--31. 1. "DATA111,Huffman table data 111"
|
|
hexmask.long.byte 0x37C 16.--23. 1. "DATA110,Huffman table data 110"
|
|
newline
|
|
hexmask.long.byte 0x37C 8.--15. 1. "DATA109,Huffman table data 109"
|
|
hexmask.long.byte 0x37C 0.--7. 1. "DATA108,Huffman table data 108"
|
|
line.long 0x380 "JPEG_DHTMEM28,JPEG DHT memory"
|
|
hexmask.long.byte 0x380 24.--31. 1. "DATA115,Huffman table data 115"
|
|
hexmask.long.byte 0x380 16.--23. 1. "DATA114,Huffman table data 114"
|
|
newline
|
|
hexmask.long.byte 0x380 8.--15. 1. "DATA113,Huffman table data 113"
|
|
hexmask.long.byte 0x380 0.--7. 1. "DATA112,Huffman table data 112"
|
|
line.long 0x384 "JPEG_DHTMEM29,JPEG DHT memory"
|
|
hexmask.long.byte 0x384 24.--31. 1. "DATA119,Huffman table data 119"
|
|
hexmask.long.byte 0x384 16.--23. 1. "DATA118,Huffman table data 118"
|
|
newline
|
|
hexmask.long.byte 0x384 8.--15. 1. "DATA117,Huffman table data 117"
|
|
hexmask.long.byte 0x384 0.--7. 1. "DATA116,Huffman table data 116"
|
|
line.long 0x388 "JPEG_DHTMEM30,JPEG DHT memory"
|
|
hexmask.long.byte 0x388 24.--31. 1. "DATA123,Huffman table data 123"
|
|
hexmask.long.byte 0x388 16.--23. 1. "DATA122,Huffman table data 122"
|
|
newline
|
|
hexmask.long.byte 0x388 8.--15. 1. "DATA121,Huffman table data 121"
|
|
hexmask.long.byte 0x388 0.--7. 1. "DATA120,Huffman table data 120"
|
|
line.long 0x38C "JPEG_DHTMEM31,JPEG DHT memory"
|
|
hexmask.long.byte 0x38C 24.--31. 1. "DATA127,Huffman table data 127"
|
|
hexmask.long.byte 0x38C 16.--23. 1. "DATA126,Huffman table data 126"
|
|
newline
|
|
hexmask.long.byte 0x38C 8.--15. 1. "DATA125,Huffman table data 125"
|
|
hexmask.long.byte 0x38C 0.--7. 1. "DATA124,Huffman table data 124"
|
|
line.long 0x390 "JPEG_DHTMEM32,JPEG DHT memory"
|
|
hexmask.long.byte 0x390 24.--31. 1. "DATA131,Huffman table data 131"
|
|
hexmask.long.byte 0x390 16.--23. 1. "DATA130,Huffman table data 130"
|
|
newline
|
|
hexmask.long.byte 0x390 8.--15. 1. "DATA129,Huffman table data 129"
|
|
hexmask.long.byte 0x390 0.--7. 1. "DATA128,Huffman table data 128"
|
|
line.long 0x394 "JPEG_DHTMEM33,JPEG DHT memory"
|
|
hexmask.long.byte 0x394 24.--31. 1. "DATA135,Huffman table data 135"
|
|
hexmask.long.byte 0x394 16.--23. 1. "DATA134,Huffman table data 134"
|
|
newline
|
|
hexmask.long.byte 0x394 8.--15. 1. "DATA133,Huffman table data 133"
|
|
hexmask.long.byte 0x394 0.--7. 1. "DATA132,Huffman table data 132"
|
|
line.long 0x398 "JPEG_DHTMEM34,JPEG DHT memory"
|
|
hexmask.long.byte 0x398 24.--31. 1. "DATA139,Huffman table data 139"
|
|
hexmask.long.byte 0x398 16.--23. 1. "DATA138,Huffman table data 138"
|
|
newline
|
|
hexmask.long.byte 0x398 8.--15. 1. "DATA137,Huffman table data 137"
|
|
hexmask.long.byte 0x398 0.--7. 1. "DATA136,Huffman table data 136"
|
|
line.long 0x39C "JPEG_DHTMEM35,JPEG DHT memory"
|
|
hexmask.long.byte 0x39C 24.--31. 1. "DATA143,Huffman table data 143"
|
|
hexmask.long.byte 0x39C 16.--23. 1. "DATA142,Huffman table data 142"
|
|
newline
|
|
hexmask.long.byte 0x39C 8.--15. 1. "DATA141,Huffman table data 141"
|
|
hexmask.long.byte 0x39C 0.--7. 1. "DATA140,Huffman table data 140"
|
|
line.long 0x3A0 "JPEG_DHTMEM36,JPEG DHT memory"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. "DATA147,Huffman table data 147"
|
|
hexmask.long.byte 0x3A0 16.--23. 1. "DATA146,Huffman table data 146"
|
|
newline
|
|
hexmask.long.byte 0x3A0 8.--15. 1. "DATA145,Huffman table data 145"
|
|
hexmask.long.byte 0x3A0 0.--7. 1. "DATA144,Huffman table data 144"
|
|
line.long 0x3A4 "JPEG_DHTMEM37,JPEG DHT memory"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. "DATA151,Huffman table data 151"
|
|
hexmask.long.byte 0x3A4 16.--23. 1. "DATA150,Huffman table data 150"
|
|
newline
|
|
hexmask.long.byte 0x3A4 8.--15. 1. "DATA149,Huffman table data 149"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. "DATA148,Huffman table data 148"
|
|
line.long 0x3A8 "JPEG_DHTMEM38,JPEG DHT memory"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. "DATA155,Huffman table data 155"
|
|
hexmask.long.byte 0x3A8 16.--23. 1. "DATA154,Huffman table data 154"
|
|
newline
|
|
hexmask.long.byte 0x3A8 8.--15. 1. "DATA153,Huffman table data 153"
|
|
hexmask.long.byte 0x3A8 0.--7. 1. "DATA152,Huffman table data 152"
|
|
line.long 0x3AC "JPEG_DHTMEM39,JPEG DHT memory"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. "DATA159,Huffman table data 159"
|
|
hexmask.long.byte 0x3AC 16.--23. 1. "DATA158,Huffman table data 158"
|
|
newline
|
|
hexmask.long.byte 0x3AC 8.--15. 1. "DATA157,Huffman table data 157"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. "DATA156,Huffman table data 156"
|
|
line.long 0x3B0 "JPEG_DHTMEM40,JPEG DHT memory"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. "DATA163,Huffman table data 163"
|
|
hexmask.long.byte 0x3B0 16.--23. 1. "DATA162,Huffman table data 162"
|
|
newline
|
|
hexmask.long.byte 0x3B0 8.--15. 1. "DATA161,Huffman table data 161"
|
|
hexmask.long.byte 0x3B0 0.--7. 1. "DATA160,Huffman table data 160"
|
|
line.long 0x3B4 "JPEG_DHTMEM41,JPEG DHT memory"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. "DATA167,Huffman table data 167"
|
|
hexmask.long.byte 0x3B4 16.--23. 1. "DATA166,Huffman table data 166"
|
|
newline
|
|
hexmask.long.byte 0x3B4 8.--15. 1. "DATA165,Huffman table data 165"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. "DATA164,Huffman table data 164"
|
|
line.long 0x3B8 "JPEG_DHTMEM42,JPEG DHT memory"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. "DATA171,Huffman table data 171"
|
|
hexmask.long.byte 0x3B8 16.--23. 1. "DATA170,Huffman table data 170"
|
|
newline
|
|
hexmask.long.byte 0x3B8 8.--15. 1. "DATA169,Huffman table data 169"
|
|
hexmask.long.byte 0x3B8 0.--7. 1. "DATA168,Huffman table data 168"
|
|
line.long 0x3BC "JPEG_DHTMEM43,JPEG DHT memory"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. "DATA175,Huffman table data 175"
|
|
hexmask.long.byte 0x3BC 16.--23. 1. "DATA174,Huffman table data 174"
|
|
newline
|
|
hexmask.long.byte 0x3BC 8.--15. 1. "DATA173,Huffman table data 173"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. "DATA172,Huffman table data 172"
|
|
line.long 0x3C0 "JPEG_DHTMEM44,JPEG DHT memory"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. "DATA179,Huffman table data 179"
|
|
hexmask.long.byte 0x3C0 16.--23. 1. "DATA178,Huffman table data 178"
|
|
newline
|
|
hexmask.long.byte 0x3C0 8.--15. 1. "DATA177,Huffman table data 177"
|
|
hexmask.long.byte 0x3C0 0.--7. 1. "DATA176,Huffman table data 176"
|
|
line.long 0x3C4 "JPEG_DHTMEM45,JPEG DHT memory"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. "DATA183,Huffman table data 183"
|
|
hexmask.long.byte 0x3C4 16.--23. 1. "DATA182,Huffman table data 182"
|
|
newline
|
|
hexmask.long.byte 0x3C4 8.--15. 1. "DATA181,Huffman table data 181"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. "DATA180,Huffman table data 180"
|
|
line.long 0x3C8 "JPEG_DHTMEM46,JPEG DHT memory"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. "DATA187,Huffman table data 187"
|
|
hexmask.long.byte 0x3C8 16.--23. 1. "DATA186,Huffman table data 186"
|
|
newline
|
|
hexmask.long.byte 0x3C8 8.--15. 1. "DATA185,Huffman table data 185"
|
|
hexmask.long.byte 0x3C8 0.--7. 1. "DATA184,Huffman table data 184"
|
|
line.long 0x3CC "JPEG_DHTMEM47,JPEG DHT memory"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. "DATA191,Huffman table data 191"
|
|
hexmask.long.byte 0x3CC 16.--23. 1. "DATA190,Huffman table data 190"
|
|
newline
|
|
hexmask.long.byte 0x3CC 8.--15. 1. "DATA189,Huffman table data 189"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. "DATA188,Huffman table data 188"
|
|
line.long 0x3D0 "JPEG_DHTMEM48,JPEG DHT memory"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. "DATA195,Huffman table data 195"
|
|
hexmask.long.byte 0x3D0 16.--23. 1. "DATA194,Huffman table data 194"
|
|
newline
|
|
hexmask.long.byte 0x3D0 8.--15. 1. "DATA193,Huffman table data 193"
|
|
hexmask.long.byte 0x3D0 0.--7. 1. "DATA192,Huffman table data 192"
|
|
line.long 0x3D4 "JPEG_DHTMEM49,JPEG DHT memory"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. "DATA199,Huffman table data 199"
|
|
hexmask.long.byte 0x3D4 16.--23. 1. "DATA198,Huffman table data 198"
|
|
newline
|
|
hexmask.long.byte 0x3D4 8.--15. 1. "DATA197,Huffman table data 197"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. "DATA196,Huffman table data 196"
|
|
line.long 0x3D8 "JPEG_DHTMEM50,JPEG DHT memory"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. "DATA203,Huffman table data 203"
|
|
hexmask.long.byte 0x3D8 16.--23. 1. "DATA202,Huffman table data 202"
|
|
newline
|
|
hexmask.long.byte 0x3D8 8.--15. 1. "DATA201,Huffman table data 201"
|
|
hexmask.long.byte 0x3D8 0.--7. 1. "DATA200,Huffman table data 200"
|
|
line.long 0x3DC "JPEG_DHTMEM51,JPEG DHT memory"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. "DATA207,Huffman table data 207"
|
|
hexmask.long.byte 0x3DC 16.--23. 1. "DATA206,Huffman table data 206"
|
|
newline
|
|
hexmask.long.byte 0x3DC 8.--15. 1. "DATA205,Huffman table data 205"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. "DATA204,Huffman table data 204"
|
|
line.long 0x3E0 "JPEG_DHTMEM52,JPEG DHT memory"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. "DATA211,Huffman table data 211"
|
|
hexmask.long.byte 0x3E0 16.--23. 1. "DATA210,Huffman table data 210"
|
|
newline
|
|
hexmask.long.byte 0x3E0 8.--15. 1. "DATA209,Huffman table data 209"
|
|
hexmask.long.byte 0x3E0 0.--7. 1. "DATA208,Huffman table data 208"
|
|
line.long 0x3E4 "JPEG_DHTMEM53,JPEG DHT memory"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. "DATA215,Huffman table data 215"
|
|
hexmask.long.byte 0x3E4 16.--23. 1. "DATA214,Huffman table data 214"
|
|
newline
|
|
hexmask.long.byte 0x3E4 8.--15. 1. "DATA213,Huffman table data 213"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. "DATA212,Huffman table data 212"
|
|
line.long 0x3E8 "JPEG_DHTMEM54,JPEG DHT memory"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. "DATA219,Huffman table data 219"
|
|
hexmask.long.byte 0x3E8 16.--23. 1. "DATA218,Huffman table data 218"
|
|
newline
|
|
hexmask.long.byte 0x3E8 8.--15. 1. "DATA217,Huffman table data 217"
|
|
hexmask.long.byte 0x3E8 0.--7. 1. "DATA216,Huffman table data 216"
|
|
line.long 0x3EC "JPEG_DHTMEM55,JPEG DHT memory"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. "DATA223,Huffman table data 223"
|
|
hexmask.long.byte 0x3EC 16.--23. 1. "DATA222,Huffman table data 222"
|
|
newline
|
|
hexmask.long.byte 0x3EC 8.--15. 1. "DATA221,Huffman table data 221"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. "DATA220,Huffman table data 220"
|
|
line.long 0x3F0 "JPEG_DHTMEM56,JPEG DHT memory"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. "DATA227,Huffman table data 227"
|
|
hexmask.long.byte 0x3F0 16.--23. 1. "DATA226,Huffman table data 226"
|
|
newline
|
|
hexmask.long.byte 0x3F0 8.--15. 1. "DATA225,Huffman table data 225"
|
|
hexmask.long.byte 0x3F0 0.--7. 1. "DATA224,Huffman table data 224"
|
|
line.long 0x3F4 "JPEG_DHTMEM57,JPEG DHT memory"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. "DATA231,Huffman table data 231"
|
|
hexmask.long.byte 0x3F4 16.--23. 1. "DATA230,Huffman table data 230"
|
|
newline
|
|
hexmask.long.byte 0x3F4 8.--15. 1. "DATA229,Huffman table data 229"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. "DATA228,Huffman table data 228"
|
|
line.long 0x3F8 "JPEG_DHTMEM58,JPEG DHT memory"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. "DATA235,Huffman table data 235"
|
|
hexmask.long.byte 0x3F8 16.--23. 1. "DATA234,Huffman table data 234"
|
|
newline
|
|
hexmask.long.byte 0x3F8 8.--15. 1. "DATA233,Huffman table data 233"
|
|
hexmask.long.byte 0x3F8 0.--7. 1. "DATA232,Huffman table data 232"
|
|
line.long 0x3FC "JPEG_DHTMEM59,JPEG DHT memory"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. "DATA239,Huffman table data 239"
|
|
hexmask.long.byte 0x3FC 16.--23. 1. "DATA238,Huffman table data 238"
|
|
newline
|
|
hexmask.long.byte 0x3FC 8.--15. 1. "DATA237,Huffman table data 237"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. "DATA236,Huffman table data 236"
|
|
line.long 0x400 "JPEG_DHTMEM60,JPEG DHT memory"
|
|
hexmask.long.byte 0x400 24.--31. 1. "DATA243,Huffman table data 243"
|
|
hexmask.long.byte 0x400 16.--23. 1. "DATA242,Huffman table data 242"
|
|
newline
|
|
hexmask.long.byte 0x400 8.--15. 1. "DATA241,Huffman table data 241"
|
|
hexmask.long.byte 0x400 0.--7. 1. "DATA240,Huffman table data 240"
|
|
line.long 0x404 "JPEG_DHTMEM61,JPEG DHT memory"
|
|
hexmask.long.byte 0x404 24.--31. 1. "DATA247,Huffman table data 247"
|
|
hexmask.long.byte 0x404 16.--23. 1. "DATA246,Huffman table data 246"
|
|
newline
|
|
hexmask.long.byte 0x404 8.--15. 1. "DATA245,Huffman table data 245"
|
|
hexmask.long.byte 0x404 0.--7. 1. "DATA244,Huffman table data 244"
|
|
line.long 0x408 "JPEG_DHTMEM62,JPEG DHT memory"
|
|
hexmask.long.byte 0x408 24.--31. 1. "DATA251,Huffman table data 251"
|
|
hexmask.long.byte 0x408 16.--23. 1. "DATA250,Huffman table data 250"
|
|
newline
|
|
hexmask.long.byte 0x408 8.--15. 1. "DATA249,Huffman table data 249"
|
|
hexmask.long.byte 0x408 0.--7. 1. "DATA248,Huffman table data 248"
|
|
line.long 0x40C "JPEG_DHTMEM63,JPEG DHT memory"
|
|
hexmask.long.byte 0x40C 24.--31. 1. "DATA255,Huffman table data 255"
|
|
hexmask.long.byte 0x40C 16.--23. 1. "DATA254,Huffman table data 254"
|
|
newline
|
|
hexmask.long.byte 0x40C 8.--15. 1. "DATA253,Huffman table data 253"
|
|
hexmask.long.byte 0x40C 0.--7. 1. "DATA252,Huffman table data 252"
|
|
line.long 0x410 "JPEG_DHTMEM64,JPEG DHT memory"
|
|
hexmask.long.byte 0x410 24.--31. 1. "DATA259,Huffman table data 259"
|
|
hexmask.long.byte 0x410 16.--23. 1. "DATA258,Huffman table data 258"
|
|
newline
|
|
hexmask.long.byte 0x410 8.--15. 1. "DATA257,Huffman table data 257"
|
|
hexmask.long.byte 0x410 0.--7. 1. "DATA256,Huffman table data 256"
|
|
line.long 0x414 "JPEG_DHTMEM65,JPEG DHT memory"
|
|
hexmask.long.byte 0x414 24.--31. 1. "DATA263,Huffman table data 263"
|
|
hexmask.long.byte 0x414 16.--23. 1. "DATA262,Huffman table data 262"
|
|
newline
|
|
hexmask.long.byte 0x414 8.--15. 1. "DATA261,Huffman table data 261"
|
|
hexmask.long.byte 0x414 0.--7. 1. "DATA260,Huffman table data 260"
|
|
line.long 0x418 "JPEG_DHTMEM66,JPEG DHT memory"
|
|
hexmask.long.byte 0x418 24.--31. 1. "DATA267,Huffman table data 267"
|
|
hexmask.long.byte 0x418 16.--23. 1. "DATA266,Huffman table data 266"
|
|
newline
|
|
hexmask.long.byte 0x418 8.--15. 1. "DATA265,Huffman table data 265"
|
|
hexmask.long.byte 0x418 0.--7. 1. "DATA264,Huffman table data 264"
|
|
line.long 0x41C "JPEG_DHTMEM67,JPEG DHT memory"
|
|
hexmask.long.byte 0x41C 24.--31. 1. "DATA271,Huffman table data 271"
|
|
hexmask.long.byte 0x41C 16.--23. 1. "DATA270,Huffman table data 270"
|
|
newline
|
|
hexmask.long.byte 0x41C 8.--15. 1. "DATA269,Huffman table data 269"
|
|
hexmask.long.byte 0x41C 0.--7. 1. "DATA268,Huffman table data 268"
|
|
line.long 0x420 "JPEG_DHTMEM68,JPEG DHT memory"
|
|
hexmask.long.byte 0x420 24.--31. 1. "DATA275,Huffman table data 275"
|
|
hexmask.long.byte 0x420 16.--23. 1. "DATA274,Huffman table data 274"
|
|
newline
|
|
hexmask.long.byte 0x420 8.--15. 1. "DATA273,Huffman table data 273"
|
|
hexmask.long.byte 0x420 0.--7. 1. "DATA272,Huffman table data 272"
|
|
line.long 0x424 "JPEG_DHTMEM69,JPEG DHT memory"
|
|
hexmask.long.byte 0x424 24.--31. 1. "DATA279,Huffman table data 279"
|
|
hexmask.long.byte 0x424 16.--23. 1. "DATA278,Huffman table data 278"
|
|
newline
|
|
hexmask.long.byte 0x424 8.--15. 1. "DATA277,Huffman table data 277"
|
|
hexmask.long.byte 0x424 0.--7. 1. "DATA276,Huffman table data 276"
|
|
line.long 0x428 "JPEG_DHTMEM70,JPEG DHT memory"
|
|
hexmask.long.byte 0x428 24.--31. 1. "DATA283,Huffman table data 283"
|
|
hexmask.long.byte 0x428 16.--23. 1. "DATA282,Huffman table data 282"
|
|
newline
|
|
hexmask.long.byte 0x428 8.--15. 1. "DATA281,Huffman table data 281"
|
|
hexmask.long.byte 0x428 0.--7. 1. "DATA280,Huffman table data 280"
|
|
line.long 0x42C "JPEG_DHTMEM71,JPEG DHT memory"
|
|
hexmask.long.byte 0x42C 24.--31. 1. "DATA287,Huffman table data 287"
|
|
hexmask.long.byte 0x42C 16.--23. 1. "DATA286,Huffman table data 286"
|
|
newline
|
|
hexmask.long.byte 0x42C 8.--15. 1. "DATA285,Huffman table data 285"
|
|
hexmask.long.byte 0x42C 0.--7. 1. "DATA284,Huffman table data 284"
|
|
line.long 0x430 "JPEG_DHTMEM72,JPEG DHT memory"
|
|
hexmask.long.byte 0x430 24.--31. 1. "DATA291,Huffman table data 291"
|
|
hexmask.long.byte 0x430 16.--23. 1. "DATA290,Huffman table data 290"
|
|
newline
|
|
hexmask.long.byte 0x430 8.--15. 1. "DATA289,Huffman table data 289"
|
|
hexmask.long.byte 0x430 0.--7. 1. "DATA288,Huffman table data 288"
|
|
line.long 0x434 "JPEG_DHTMEM73,JPEG DHT memory"
|
|
hexmask.long.byte 0x434 24.--31. 1. "DATA295,Huffman table data 295"
|
|
hexmask.long.byte 0x434 16.--23. 1. "DATA294,Huffman table data 294"
|
|
newline
|
|
hexmask.long.byte 0x434 8.--15. 1. "DATA293,Huffman table data 293"
|
|
hexmask.long.byte 0x434 0.--7. 1. "DATA292,Huffman table data 292"
|
|
line.long 0x438 "JPEG_DHTMEM74,JPEG DHT memory"
|
|
hexmask.long.byte 0x438 24.--31. 1. "DATA299,Huffman table data 299"
|
|
hexmask.long.byte 0x438 16.--23. 1. "DATA298,Huffman table data 298"
|
|
newline
|
|
hexmask.long.byte 0x438 8.--15. 1. "DATA297,Huffman table data 297"
|
|
hexmask.long.byte 0x438 0.--7. 1. "DATA296,Huffman table data 296"
|
|
line.long 0x43C "JPEG_DHTMEM75,JPEG DHT memory"
|
|
hexmask.long.byte 0x43C 24.--31. 1. "DATA303,Huffman table data 303"
|
|
hexmask.long.byte 0x43C 16.--23. 1. "DATA302,Huffman table data 302"
|
|
newline
|
|
hexmask.long.byte 0x43C 8.--15. 1. "DATA301,Huffman table data 301"
|
|
hexmask.long.byte 0x43C 0.--7. 1. "DATA300,Huffman table data 300"
|
|
line.long 0x440 "JPEG_DHTMEM76,JPEG DHT memory"
|
|
hexmask.long.byte 0x440 24.--31. 1. "DATA307,Huffman table data 307"
|
|
hexmask.long.byte 0x440 16.--23. 1. "DATA306,Huffman table data 306"
|
|
newline
|
|
hexmask.long.byte 0x440 8.--15. 1. "DATA305,Huffman table data 305"
|
|
hexmask.long.byte 0x440 0.--7. 1. "DATA304,Huffman table data 304"
|
|
line.long 0x444 "JPEG_DHTMEM77,JPEG DHT memory"
|
|
hexmask.long.byte 0x444 24.--31. 1. "DATA311,Huffman table data 311"
|
|
hexmask.long.byte 0x444 16.--23. 1. "DATA310,Huffman table data 310"
|
|
newline
|
|
hexmask.long.byte 0x444 8.--15. 1. "DATA309,Huffman table data 309"
|
|
hexmask.long.byte 0x444 0.--7. 1. "DATA308,Huffman table data 308"
|
|
line.long 0x448 "JPEG_DHTMEM78,JPEG DHT memory"
|
|
hexmask.long.byte 0x448 24.--31. 1. "DATA315,Huffman table data 315"
|
|
hexmask.long.byte 0x448 16.--23. 1. "DATA314,Huffman table data 314"
|
|
newline
|
|
hexmask.long.byte 0x448 8.--15. 1. "DATA313,Huffman table data 313"
|
|
hexmask.long.byte 0x448 0.--7. 1. "DATA312,Huffman table data 312"
|
|
line.long 0x44C "JPEG_DHTMEM79,JPEG DHT memory"
|
|
hexmask.long.byte 0x44C 24.--31. 1. "DATA319,Huffman table data 319"
|
|
hexmask.long.byte 0x44C 16.--23. 1. "DATA318,Huffman table data 318"
|
|
newline
|
|
hexmask.long.byte 0x44C 8.--15. 1. "DATA317,Huffman table data 317"
|
|
hexmask.long.byte 0x44C 0.--7. 1. "DATA316,Huffman table data 316"
|
|
line.long 0x450 "JPEG_DHTMEM80,JPEG DHT memory"
|
|
hexmask.long.byte 0x450 24.--31. 1. "DATA323,Huffman table data 323"
|
|
hexmask.long.byte 0x450 16.--23. 1. "DATA322,Huffman table data 322"
|
|
newline
|
|
hexmask.long.byte 0x450 8.--15. 1. "DATA321,Huffman table data 321"
|
|
hexmask.long.byte 0x450 0.--7. 1. "DATA320,Huffman table data 320"
|
|
line.long 0x454 "JPEG_DHTMEM81,JPEG DHT memory"
|
|
hexmask.long.byte 0x454 24.--31. 1. "DATA327,Huffman table data 327"
|
|
hexmask.long.byte 0x454 16.--23. 1. "DATA326,Huffman table data 326"
|
|
newline
|
|
hexmask.long.byte 0x454 8.--15. 1. "DATA325,Huffman table data 325"
|
|
hexmask.long.byte 0x454 0.--7. 1. "DATA324,Huffman table data 324"
|
|
line.long 0x458 "JPEG_DHTMEM82,JPEG DHT memory"
|
|
hexmask.long.byte 0x458 24.--31. 1. "DATA331,Huffman table data 331"
|
|
hexmask.long.byte 0x458 16.--23. 1. "DATA330,Huffman table data 330"
|
|
newline
|
|
hexmask.long.byte 0x458 8.--15. 1. "DATA329,Huffman table data 329"
|
|
hexmask.long.byte 0x458 0.--7. 1. "DATA328,Huffman table data 328"
|
|
line.long 0x45C "JPEG_DHTMEM83,JPEG DHT memory"
|
|
hexmask.long.byte 0x45C 24.--31. 1. "DATA335,Huffman table data 335"
|
|
hexmask.long.byte 0x45C 16.--23. 1. "DATA334,Huffman table data 334"
|
|
newline
|
|
hexmask.long.byte 0x45C 8.--15. 1. "DATA333,Huffman table data 333"
|
|
hexmask.long.byte 0x45C 0.--7. 1. "DATA332,Huffman table data 332"
|
|
line.long 0x460 "JPEG_DHTMEM84,JPEG DHT memory"
|
|
hexmask.long.byte 0x460 24.--31. 1. "DATA339,Huffman table data 339"
|
|
hexmask.long.byte 0x460 16.--23. 1. "DATA338,Huffman table data 338"
|
|
newline
|
|
hexmask.long.byte 0x460 8.--15. 1. "DATA337,Huffman table data 337"
|
|
hexmask.long.byte 0x460 0.--7. 1. "DATA336,Huffman table data 336"
|
|
line.long 0x464 "JPEG_DHTMEM85,JPEG DHT memory"
|
|
hexmask.long.byte 0x464 24.--31. 1. "DATA343,Huffman table data 343"
|
|
hexmask.long.byte 0x464 16.--23. 1. "DATA342,Huffman table data 342"
|
|
newline
|
|
hexmask.long.byte 0x464 8.--15. 1. "DATA341,Huffman table data 341"
|
|
hexmask.long.byte 0x464 0.--7. 1. "DATA340,Huffman table data 340"
|
|
line.long 0x468 "JPEG_DHTMEM86,JPEG DHT memory"
|
|
hexmask.long.byte 0x468 24.--31. 1. "DATA347,Huffman table data 347"
|
|
hexmask.long.byte 0x468 16.--23. 1. "DATA346,Huffman table data 346"
|
|
newline
|
|
hexmask.long.byte 0x468 8.--15. 1. "DATA345,Huffman table data 345"
|
|
hexmask.long.byte 0x468 0.--7. 1. "DATA344,Huffman table data 344"
|
|
line.long 0x46C "JPEG_DHTMEM87,JPEG DHT memory"
|
|
hexmask.long.byte 0x46C 24.--31. 1. "DATA351,Huffman table data 351"
|
|
hexmask.long.byte 0x46C 16.--23. 1. "DATA350,Huffman table data 350"
|
|
newline
|
|
hexmask.long.byte 0x46C 8.--15. 1. "DATA349,Huffman table data 349"
|
|
hexmask.long.byte 0x46C 0.--7. 1. "DATA348,Huffman table data 348"
|
|
line.long 0x470 "JPEG_DHTMEM88,JPEG DHT memory"
|
|
hexmask.long.byte 0x470 24.--31. 1. "DATA355,Huffman table data 355"
|
|
hexmask.long.byte 0x470 16.--23. 1. "DATA354,Huffman table data 354"
|
|
newline
|
|
hexmask.long.byte 0x470 8.--15. 1. "DATA353,Huffman table data 353"
|
|
hexmask.long.byte 0x470 0.--7. 1. "DATA352,Huffman table data 352"
|
|
line.long 0x474 "JPEG_DHTMEM89,JPEG DHT memory"
|
|
hexmask.long.byte 0x474 24.--31. 1. "DATA359,Huffman table data 359"
|
|
hexmask.long.byte 0x474 16.--23. 1. "DATA358,Huffman table data 358"
|
|
newline
|
|
hexmask.long.byte 0x474 8.--15. 1. "DATA357,Huffman table data 357"
|
|
hexmask.long.byte 0x474 0.--7. 1. "DATA356,Huffman table data 356"
|
|
line.long 0x478 "JPEG_DHTMEM90,JPEG DHT memory"
|
|
hexmask.long.byte 0x478 24.--31. 1. "DATA363,Huffman table data 363"
|
|
hexmask.long.byte 0x478 16.--23. 1. "DATA362,Huffman table data 362"
|
|
newline
|
|
hexmask.long.byte 0x478 8.--15. 1. "DATA361,Huffman table data 361"
|
|
hexmask.long.byte 0x478 0.--7. 1. "DATA360,Huffman table data 360"
|
|
line.long 0x47C "JPEG_DHTMEM91,JPEG DHT memory"
|
|
hexmask.long.byte 0x47C 24.--31. 1. "DATA367,Huffman table data 367"
|
|
hexmask.long.byte 0x47C 16.--23. 1. "DATA366,Huffman table data 366"
|
|
newline
|
|
hexmask.long.byte 0x47C 8.--15. 1. "DATA365,Huffman table data 365"
|
|
hexmask.long.byte 0x47C 0.--7. 1. "DATA364,Huffman table data 364"
|
|
line.long 0x480 "JPEG_DHTMEM92,JPEG DHT memory"
|
|
hexmask.long.byte 0x480 24.--31. 1. "DATA371,Huffman table data 371"
|
|
hexmask.long.byte 0x480 16.--23. 1. "DATA370,Huffman table data 370"
|
|
newline
|
|
hexmask.long.byte 0x480 8.--15. 1. "DATA369,Huffman table data 369"
|
|
hexmask.long.byte 0x480 0.--7. 1. "DATA368,Huffman table data 368"
|
|
line.long 0x484 "JPEG_DHTMEM93,JPEG DHT memory"
|
|
hexmask.long.byte 0x484 24.--31. 1. "DATA375,Huffman table data 375"
|
|
hexmask.long.byte 0x484 16.--23. 1. "DATA374,Huffman table data 374"
|
|
newline
|
|
hexmask.long.byte 0x484 8.--15. 1. "DATA373,Huffman table data 373"
|
|
hexmask.long.byte 0x484 0.--7. 1. "DATA372,Huffman table data 372"
|
|
line.long 0x488 "JPEG_DHTMEM94,JPEG DHT memory"
|
|
hexmask.long.byte 0x488 24.--31. 1. "DATA379,Huffman table data 379"
|
|
hexmask.long.byte 0x488 16.--23. 1. "DATA378,Huffman table data 378"
|
|
newline
|
|
hexmask.long.byte 0x488 8.--15. 1. "DATA377,Huffman table data 377"
|
|
hexmask.long.byte 0x488 0.--7. 1. "DATA376,Huffman table data 376"
|
|
line.long 0x48C "JPEG_DHTMEM95,JPEG DHT memory"
|
|
hexmask.long.byte 0x48C 24.--31. 1. "DATA383,Huffman table data 383"
|
|
hexmask.long.byte 0x48C 16.--23. 1. "DATA382,Huffman table data 382"
|
|
newline
|
|
hexmask.long.byte 0x48C 8.--15. 1. "DATA381,Huffman table data 381"
|
|
hexmask.long.byte 0x48C 0.--7. 1. "DATA380,Huffman table data 380"
|
|
line.long 0x490 "JPEG_DHTMEM96,JPEG DHT memory"
|
|
hexmask.long.byte 0x490 24.--31. 1. "DATA387,Huffman table data 387"
|
|
hexmask.long.byte 0x490 16.--23. 1. "DATA386,Huffman table data 386"
|
|
newline
|
|
hexmask.long.byte 0x490 8.--15. 1. "DATA385,Huffman table data 385"
|
|
hexmask.long.byte 0x490 0.--7. 1. "DATA384,Huffman table data 384"
|
|
line.long 0x494 "JPEG_DHTMEM97,JPEG DHT memory"
|
|
hexmask.long.byte 0x494 24.--31. 1. "DATA391,Huffman table data 391"
|
|
hexmask.long.byte 0x494 16.--23. 1. "DATA390,Huffman table data 390"
|
|
newline
|
|
hexmask.long.byte 0x494 8.--15. 1. "DATA389,Huffman table data 389"
|
|
hexmask.long.byte 0x494 0.--7. 1. "DATA388,Huffman table data 388"
|
|
line.long 0x498 "JPEG_DHTMEM98,JPEG DHT memory"
|
|
hexmask.long.byte 0x498 24.--31. 1. "DATA395,Huffman table data 395"
|
|
hexmask.long.byte 0x498 16.--23. 1. "DATA394,Huffman table data 394"
|
|
newline
|
|
hexmask.long.byte 0x498 8.--15. 1. "DATA393,Huffman table data 393"
|
|
hexmask.long.byte 0x498 0.--7. 1. "DATA392,Huffman table data 392"
|
|
line.long 0x49C "JPEG_DHTMEM99,JPEG DHT memory"
|
|
hexmask.long.byte 0x49C 24.--31. 1. "DATA399,Huffman table data 399"
|
|
hexmask.long.byte 0x49C 16.--23. 1. "DATA398,Huffman table data 398"
|
|
newline
|
|
hexmask.long.byte 0x49C 8.--15. 1. "DATA397,Huffman table data 397"
|
|
hexmask.long.byte 0x49C 0.--7. 1. "DATA396,Huffman table data 396"
|
|
line.long 0x4A0 "JPEG_DHTMEM100,JPEG DHT memory"
|
|
hexmask.long.byte 0x4A0 24.--31. 1. "DATA403,Huffman table data 403"
|
|
hexmask.long.byte 0x4A0 16.--23. 1. "DATA402,Huffman table data 402"
|
|
newline
|
|
hexmask.long.byte 0x4A0 8.--15. 1. "DATA401,Huffman table data 401"
|
|
hexmask.long.byte 0x4A0 0.--7. 1. "DATA400,Huffman table data 400"
|
|
line.long 0x4A4 "JPEG_DHTMEM101,JPEG DHT memory"
|
|
hexmask.long.byte 0x4A4 24.--31. 1. "DATA407,Huffman table data 407"
|
|
hexmask.long.byte 0x4A4 16.--23. 1. "DATA406,Huffman table data 406"
|
|
newline
|
|
hexmask.long.byte 0x4A4 8.--15. 1. "DATA405,Huffman table data 405"
|
|
hexmask.long.byte 0x4A4 0.--7. 1. "DATA404,Huffman table data 404"
|
|
line.long 0x4A8 "JPEG_DHTMEM102,JPEG DHT memory"
|
|
hexmask.long.byte 0x4A8 24.--31. 1. "DATA411,Huffman table data 411"
|
|
hexmask.long.byte 0x4A8 16.--23. 1. "DATA410,Huffman table data 410"
|
|
newline
|
|
hexmask.long.byte 0x4A8 8.--15. 1. "DATA409,Huffman table data 409"
|
|
hexmask.long.byte 0x4A8 0.--7. 1. "DATA408,Huffman table data 408"
|
|
group.long 0x500++0xDF
|
|
line.long 0x0 "JPEG_HUFFENC_AC0_0,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_1,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2"
|
|
line.long 0x8 "JPEG_HUFFENC_AC0_2,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4"
|
|
hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4"
|
|
line.long 0xC "JPEG_HUFFENC_AC0_3,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6"
|
|
hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6"
|
|
line.long 0x10 "JPEG_HUFFENC_AC0_4,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9"
|
|
hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8"
|
|
hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8"
|
|
line.long 0x14 "JPEG_HUFFENC_AC0_5,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11"
|
|
hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10"
|
|
hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10"
|
|
line.long 0x18 "JPEG_HUFFENC_AC0_6,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13"
|
|
hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12"
|
|
hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12"
|
|
line.long 0x1C "JPEG_HUFFENC_AC0_7,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14"
|
|
line.long 0x20 "JPEG_HUFFENC_AC0_8,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x20 24.--27. 1. "HLEN17,Huffman length 17"
|
|
hexmask.long.byte 0x20 16.--23. 1. "HCODE17,Huffman code 17"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--11. 1. "HLEN16,Huffman length 16"
|
|
hexmask.long.byte 0x20 0.--7. 1. "HCODE16,Huffman code 16"
|
|
line.long 0x24 "JPEG_HUFFENC_AC0_9,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x24 24.--27. 1. "HLEN19,Huffman length 19"
|
|
hexmask.long.byte 0x24 16.--23. 1. "HCODE19,Huffman code 19"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--11. 1. "HLEN18,Huffman length 18"
|
|
hexmask.long.byte 0x24 0.--7. 1. "HCODE18,Huffman code 18"
|
|
line.long 0x28 "JPEG_HUFFENC_AC0_10,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x28 24.--27. 1. "HLEN21,Huffman length 21"
|
|
hexmask.long.byte 0x28 16.--23. 1. "HCODE21,Huffman code 21"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--11. 1. "HLEN20,Huffman length 20"
|
|
hexmask.long.byte 0x28 0.--7. 1. "HCODE20,Huffman code 20"
|
|
line.long 0x2C "JPEG_HUFFENC_AC0_11,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x2C 24.--27. 1. "HLEN23,Huffman length 23"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "HCODE23,Huffman code 23"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--11. 1. "HLEN22,Huffman length 22"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "HCODE22,Huffman code 22"
|
|
line.long 0x30 "JPEG_HUFFENC_AC0_12,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x30 24.--27. 1. "HLEN25,Huffman length 25"
|
|
hexmask.long.byte 0x30 16.--23. 1. "HCODE25,Huffman code 25"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--11. 1. "HLEN24,Huffman length 24"
|
|
hexmask.long.byte 0x30 0.--7. 1. "HCODE24,Huffman code 24"
|
|
line.long 0x34 "JPEG_HUFFENC_AC0_13,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x34 24.--27. 1. "HLEN27,Huffman length 27"
|
|
hexmask.long.byte 0x34 16.--23. 1. "HCODE27,Huffman code 27"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--11. 1. "HLEN26,Huffman length 26"
|
|
hexmask.long.byte 0x34 0.--7. 1. "HCODE26,Huffman code 26"
|
|
line.long 0x38 "JPEG_HUFFENC_AC0_14,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x38 24.--27. 1. "HLEN29,Huffman length 29"
|
|
hexmask.long.byte 0x38 16.--23. 1. "HCODE29,Huffman code 29"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--11. 1. "HLEN28,Huffman length 28"
|
|
hexmask.long.byte 0x38 0.--7. 1. "HCODE28,Huffman code 28"
|
|
line.long 0x3C "JPEG_HUFFENC_AC0_15,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x3C 24.--27. 1. "HLEN31,Huffman length 31"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "HCODE31,Huffman code 31"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--11. 1. "HLEN30,Huffman length 30"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "HCODE30,Huffman code 30"
|
|
line.long 0x40 "JPEG_HUFFENC_AC0_16,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x40 24.--27. 1. "HLEN33,Huffman length 33"
|
|
hexmask.long.byte 0x40 16.--23. 1. "HCODE33,Huffman code 33"
|
|
newline
|
|
hexmask.long.byte 0x40 8.--11. 1. "HLEN32,Huffman length 32"
|
|
hexmask.long.byte 0x40 0.--7. 1. "HCODE32,Huffman code 32"
|
|
line.long 0x44 "JPEG_HUFFENC_AC0_17,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x44 24.--27. 1. "HLEN35,Huffman length 35"
|
|
hexmask.long.byte 0x44 16.--23. 1. "HCODE35,Huffman code 35"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--11. 1. "HLEN34,Huffman length 34"
|
|
hexmask.long.byte 0x44 0.--7. 1. "HCODE34,Huffman code 34"
|
|
line.long 0x48 "JPEG_HUFFENC_AC0_18,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x48 24.--27. 1. "HLEN37,Huffman length 37"
|
|
hexmask.long.byte 0x48 16.--23. 1. "HCODE37,Huffman code 37"
|
|
newline
|
|
hexmask.long.byte 0x48 8.--11. 1. "HLEN36,Huffman length 36"
|
|
hexmask.long.byte 0x48 0.--7. 1. "HCODE36,Huffman code 36"
|
|
line.long 0x4C "JPEG_HUFFENC_AC0_19,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "HLEN39,Huffman length 39"
|
|
hexmask.long.byte 0x4C 16.--23. 1. "HCODE39,Huffman code 39"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "HLEN38,Huffman length 38"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "HCODE38,Huffman code 38"
|
|
line.long 0x50 "JPEG_HUFFENC_AC0_20,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x50 24.--27. 1. "HLEN41,Huffman length 41"
|
|
hexmask.long.byte 0x50 16.--23. 1. "HCODE41,Huffman code 41"
|
|
newline
|
|
hexmask.long.byte 0x50 8.--11. 1. "HLEN40,Huffman length 40"
|
|
hexmask.long.byte 0x50 0.--7. 1. "HCODE40,Huffman code 40"
|
|
line.long 0x54 "JPEG_HUFFENC_AC0_21,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x54 24.--27. 1. "HLEN43,Huffman length 43"
|
|
hexmask.long.byte 0x54 16.--23. 1. "HCODE43,Huffman code 43"
|
|
newline
|
|
hexmask.long.byte 0x54 8.--11. 1. "HLEN42,Huffman length 42"
|
|
hexmask.long.byte 0x54 0.--7. 1. "HCODE42,Huffman code 42"
|
|
line.long 0x58 "JPEG_HUFFENC_AC0_22,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x58 24.--27. 1. "HLEN45,Huffman length 45"
|
|
hexmask.long.byte 0x58 16.--23. 1. "HCODE45,Huffman code 45"
|
|
newline
|
|
hexmask.long.byte 0x58 8.--11. 1. "HLEN44,Huffman length 44"
|
|
hexmask.long.byte 0x58 0.--7. 1. "HCODE44,Huffman code 44"
|
|
line.long 0x5C "JPEG_HUFFENC_AC0_23,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x5C 24.--27. 1. "HLEN47,Huffman length 47"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "HCODE47,Huffman code 47"
|
|
newline
|
|
hexmask.long.byte 0x5C 8.--11. 1. "HLEN46,Huffman length 46"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "HCODE46,Huffman code 46"
|
|
line.long 0x60 "JPEG_HUFFENC_AC0_24,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x60 24.--27. 1. "HLEN49,Huffman length 49"
|
|
hexmask.long.byte 0x60 16.--23. 1. "HCODE49,Huffman code 49"
|
|
newline
|
|
hexmask.long.byte 0x60 8.--11. 1. "HLEN48,Huffman length 48"
|
|
hexmask.long.byte 0x60 0.--7. 1. "HCODE48,Huffman code 48"
|
|
line.long 0x64 "JPEG_HUFFENC_AC0_25,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x64 24.--27. 1. "HLEN51,Huffman length 51"
|
|
hexmask.long.byte 0x64 16.--23. 1. "HCODE51,Huffman code 51"
|
|
newline
|
|
hexmask.long.byte 0x64 8.--11. 1. "HLEN50,Huffman length 50"
|
|
hexmask.long.byte 0x64 0.--7. 1. "HCODE50,Huffman code 50"
|
|
line.long 0x68 "JPEG_HUFFENC_AC0_26,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x68 24.--27. 1. "HLEN53,Huffman length 53"
|
|
hexmask.long.byte 0x68 16.--23. 1. "HCODE53,Huffman code 53"
|
|
newline
|
|
hexmask.long.byte 0x68 8.--11. 1. "HLEN52,Huffman length 52"
|
|
hexmask.long.byte 0x68 0.--7. 1. "HCODE52,Huffman code 52"
|
|
line.long 0x6C "JPEG_HUFFENC_AC0_27,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x6C 24.--27. 1. "HLEN55,Huffman length 55"
|
|
hexmask.long.byte 0x6C 16.--23. 1. "HCODE55,Huffman code 55"
|
|
newline
|
|
hexmask.long.byte 0x6C 8.--11. 1. "HLEN54,Huffman length 54"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "HCODE54,Huffman code 54"
|
|
line.long 0x70 "JPEG_HUFFENC_AC0_28,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x70 24.--27. 1. "HLEN57,Huffman length 57"
|
|
hexmask.long.byte 0x70 16.--23. 1. "HCODE57,Huffman code 57"
|
|
newline
|
|
hexmask.long.byte 0x70 8.--11. 1. "HLEN56,Huffman length 56"
|
|
hexmask.long.byte 0x70 0.--7. 1. "HCODE56,Huffman code 56"
|
|
line.long 0x74 "JPEG_HUFFENC_AC0_29,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x74 24.--27. 1. "HLEN59,Huffman length 59"
|
|
hexmask.long.byte 0x74 16.--23. 1. "HCODE59,Huffman code 59"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--11. 1. "HLEN58,Huffman length 58"
|
|
hexmask.long.byte 0x74 0.--7. 1. "HCODE58,Huffman code 58"
|
|
line.long 0x78 "JPEG_HUFFENC_AC0_30,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x78 24.--27. 1. "HLEN61,Huffman length 61"
|
|
hexmask.long.byte 0x78 16.--23. 1. "HCODE61,Huffman code 61"
|
|
newline
|
|
hexmask.long.byte 0x78 8.--11. 1. "HLEN60,Huffman length 60"
|
|
hexmask.long.byte 0x78 0.--7. 1. "HCODE60,Huffman code 60"
|
|
line.long 0x7C "JPEG_HUFFENC_AC0_31,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x7C 24.--27. 1. "HLEN63,Huffman length 63"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "HCODE63,Huffman code 63"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--11. 1. "HLEN62,Huffman length 62"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "HCODE62,Huffman code 62"
|
|
line.long 0x80 "JPEG_HUFFENC_AC0_32,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x80 24.--27. 1. "HLEN65,Huffman length 65"
|
|
hexmask.long.byte 0x80 16.--23. 1. "HCODE65,Huffman code 65"
|
|
newline
|
|
hexmask.long.byte 0x80 8.--11. 1. "HLEN64,Huffman length 64"
|
|
hexmask.long.byte 0x80 0.--7. 1. "HCODE64,Huffman code 64"
|
|
line.long 0x84 "JPEG_HUFFENC_AC0_33,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x84 24.--27. 1. "HLEN67,Huffman length 67"
|
|
hexmask.long.byte 0x84 16.--23. 1. "HCODE67,Huffman code 67"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--11. 1. "HLEN66,Huffman length 66"
|
|
hexmask.long.byte 0x84 0.--7. 1. "HCODE66,Huffman code 66"
|
|
line.long 0x88 "JPEG_HUFFENC_AC0_34,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x88 24.--27. 1. "HLEN69,Huffman length 69"
|
|
hexmask.long.byte 0x88 16.--23. 1. "HCODE69,Huffman code 69"
|
|
newline
|
|
hexmask.long.byte 0x88 8.--11. 1. "HLEN68,Huffman length 68"
|
|
hexmask.long.byte 0x88 0.--7. 1. "HCODE68,Huffman code 68"
|
|
line.long 0x8C "JPEG_HUFFENC_AC0_35,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x8C 24.--27. 1. "HLEN71,Huffman length 71"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "HCODE71,Huffman code 71"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--11. 1. "HLEN70,Huffman length 70"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "HCODE70,Huffman code 70"
|
|
line.long 0x90 "JPEG_HUFFENC_AC0_36,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x90 24.--27. 1. "HLEN73,Huffman length 73"
|
|
hexmask.long.byte 0x90 16.--23. 1. "HCODE73,Huffman code 73"
|
|
newline
|
|
hexmask.long.byte 0x90 8.--11. 1. "HLEN72,Huffman length 72"
|
|
hexmask.long.byte 0x90 0.--7. 1. "HCODE72,Huffman code 72"
|
|
line.long 0x94 "JPEG_HUFFENC_AC0_37,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x94 24.--27. 1. "HLEN75,Huffman length 75"
|
|
hexmask.long.byte 0x94 16.--23. 1. "HCODE75,Huffman code 75"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--11. 1. "HLEN74,Huffman length 74"
|
|
hexmask.long.byte 0x94 0.--7. 1. "HCODE74,Huffman code 74"
|
|
line.long 0x98 "JPEG_HUFFENC_AC0_38,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x98 24.--27. 1. "HLEN77,Huffman length 77"
|
|
hexmask.long.byte 0x98 16.--23. 1. "HCODE77,Huffman code 77"
|
|
newline
|
|
hexmask.long.byte 0x98 8.--11. 1. "HLEN76,Huffman length 76"
|
|
hexmask.long.byte 0x98 0.--7. 1. "HCODE76,Huffman code 76"
|
|
line.long 0x9C "JPEG_HUFFENC_AC0_39,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x9C 24.--27. 1. "HLEN79,Huffman length 79"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "HCODE79,Huffman code 79"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--11. 1. "HLEN78,Huffman length 78"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "HCODE78,Huffman code 78"
|
|
line.long 0xA0 "JPEG_HUFFENC_AC0_40,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xA0 24.--27. 1. "HLEN81,Huffman length 81"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "HCODE81,Huffman code 81"
|
|
newline
|
|
hexmask.long.byte 0xA0 8.--11. 1. "HLEN80,Huffman length 80"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "HCODE80,Huffman code 80"
|
|
line.long 0xA4 "JPEG_HUFFENC_AC0_41,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xA4 24.--27. 1. "HLEN83,Huffman length 83"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "HCODE83,Huffman code 83"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--11. 1. "HLEN82,Huffman length 82"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "HCODE82,Huffman code 82"
|
|
line.long 0xA8 "JPEG_HUFFENC_AC0_42,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xA8 24.--27. 1. "HLEN85,Huffman length 85"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "HCODE85,Huffman code 85"
|
|
newline
|
|
hexmask.long.byte 0xA8 8.--11. 1. "HLEN84,Huffman length 84"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "HCODE84,Huffman code 84"
|
|
line.long 0xAC "JPEG_HUFFENC_AC0_43,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xAC 24.--27. 1. "HLEN87,Huffman length 87"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "HCODE87,Huffman code 87"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--11. 1. "HLEN86,Huffman length 86"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "HCODE86,Huffman code 86"
|
|
line.long 0xB0 "JPEG_HUFFENC_AC0_44,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xB0 24.--27. 1. "HLEN89,Huffman length 89"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "HCODE89,Huffman code 89"
|
|
newline
|
|
hexmask.long.byte 0xB0 8.--11. 1. "HLEN88,Huffman length 88"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "HCODE88,Huffman code 88"
|
|
line.long 0xB4 "JPEG_HUFFENC_AC0_45,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xB4 24.--27. 1. "HLEN91,Huffman length 91"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "HCODE91,Huffman code 91"
|
|
newline
|
|
hexmask.long.byte 0xB4 8.--11. 1. "HLEN90,Huffman length 90"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "HCODE90,Huffman code 90"
|
|
line.long 0xB8 "JPEG_HUFFENC_AC0_46,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xB8 24.--27. 1. "HLEN93,Huffman length 93"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "HCODE93,Huffman code 93"
|
|
newline
|
|
hexmask.long.byte 0xB8 8.--11. 1. "HLEN92,Huffman length 92"
|
|
hexmask.long.byte 0xB8 0.--7. 1. "HCODE92,Huffman code 92"
|
|
line.long 0xBC "JPEG_HUFFENC_AC0_47,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xBC 24.--27. 1. "HLEN95,Huffman length 95"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "HCODE95,Huffman code 95"
|
|
newline
|
|
hexmask.long.byte 0xBC 8.--11. 1. "HLEN94,Huffman length 94"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "HCODE94,Huffman code 94"
|
|
line.long 0xC0 "JPEG_HUFFENC_AC0_48,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xC0 24.--27. 1. "HLEN97,Huffman length 97"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "HCODE97,Huffman code 97"
|
|
newline
|
|
hexmask.long.byte 0xC0 8.--11. 1. "HLEN96,Huffman length 96"
|
|
hexmask.long.byte 0xC0 0.--7. 1. "HCODE96,Huffman code 96"
|
|
line.long 0xC4 "JPEG_HUFFENC_AC0_49,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xC4 24.--27. 1. "HLEN99,Huffman length 99"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "HCODE99,Huffman code 99"
|
|
newline
|
|
hexmask.long.byte 0xC4 8.--11. 1. "HLEN98,Huffman length 98"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "HCODE98,Huffman code 98"
|
|
line.long 0xC8 "JPEG_HUFFENC_AC0_50,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xC8 24.--27. 1. "HLEN101,Huffman length 101"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "HCODE101,Huffman code 101"
|
|
newline
|
|
hexmask.long.byte 0xC8 8.--11. 1. "HLEN100,Huffman length 100"
|
|
hexmask.long.byte 0xC8 0.--7. 1. "HCODE100,Huffman code 100"
|
|
line.long 0xCC "JPEG_HUFFENC_AC0_51,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xCC 24.--27. 1. "HLEN103,Huffman length 103"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "HCODE103,Huffman code 103"
|
|
newline
|
|
hexmask.long.byte 0xCC 8.--11. 1. "HLEN102,Huffman length 102"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "HCODE102,Huffman code 102"
|
|
line.long 0xD0 "JPEG_HUFFENC_AC0_52,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xD0 24.--27. 1. "HLEN105,Huffman length 105"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "HCODE105,Huffman code 105"
|
|
newline
|
|
hexmask.long.byte 0xD0 8.--11. 1. "HLEN104,Huffman length 104"
|
|
hexmask.long.byte 0xD0 0.--7. 1. "HCODE104,Huffman code 104"
|
|
line.long 0xD4 "JPEG_HUFFENC_AC0_53,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xD4 24.--27. 1. "HLEN107,Huffman length 107"
|
|
hexmask.long.byte 0xD4 16.--23. 1. "HCODE107,Huffman code 107"
|
|
newline
|
|
hexmask.long.byte 0xD4 8.--11. 1. "HLEN106,Huffman length 106"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "HCODE106,Huffman code 106"
|
|
line.long 0xD8 "JPEG_HUFFENC_AC0_54,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xD8 24.--27. 1. "HLEN109,Huffman length 109"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "HCODE109,Huffman code 109"
|
|
newline
|
|
hexmask.long.byte 0xD8 8.--11. 1. "HLEN108,Huffman length 108"
|
|
hexmask.long.byte 0xD8 0.--7. 1. "HCODE108,Huffman code 108"
|
|
line.long 0xDC "JPEG_HUFFENC_AC0_55,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0xDC 24.--27. 1. "HLEN111,Huffman length 111"
|
|
hexmask.long.byte 0xDC 16.--23. 1. "HCODE111,Huffman code 111"
|
|
newline
|
|
hexmask.long.byte 0xDC 8.--11. 1. "HLEN110,Huffman length 110"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "HCODE110,Huffman code 110"
|
|
group.long 0x5DC++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_0,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_56,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN113,Huffman length 113"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE113,Huffman code 113"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN112,Huffman length 112"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE112,Huffman code 112"
|
|
group.long 0x5E0++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_1,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN3,Huffman length 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE3,Huffman code 3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN2,Huffman length 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE2,Huffman code 2"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_57,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN115,Huffman length 115"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE115,Huffman code 115"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN114,Huffman length 114"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE114,Huffman code 114"
|
|
group.long 0x5E4++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_2,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN5,Huffman length 5"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE5,Huffman code 5"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN4,Huffman length 4"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE4,Huffman code 4"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_58,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN117,Huffman length 117"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE117,Huffman code 117"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN116,Huffman length 116"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE116,Huffman code 116"
|
|
group.long 0x5E8++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_3,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN7,Huffman length 7"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE7,Huffman code 7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN6,Huffman length 6"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE6,Huffman code 6"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_59,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN119,Huffman length 119"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE119,Huffman code 119"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN118,Huffman length 118"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE118,Huffman code 118"
|
|
group.long 0x5EC++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_4,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN9,Huffman length 9"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE9,Huffman code 9"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN8,Huffman length 8"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE8,Huffman code 8"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_60,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN121,Huffman length 121"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE121,Huffman code 121"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN120,Huffman length 120"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE120,Huffman code 120"
|
|
group.long 0x5F0++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_5,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN11,Huffman length 11"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE11,Huffman code 11"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN10,Huffman length 10"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE10,Huffman code 10"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_61,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN123,Huffman length 123"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE123,Huffman code 123"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN122,Huffman length 122"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE122,Huffman code 122"
|
|
group.long 0x5F4++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_6,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN13,Huffman length 13"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE13,Huffman code 13"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN12,Huffman length 12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE12,Huffman code 12"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_62,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN125,Huffman length 125"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE125,Huffman code 125"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN124,Huffman length 124"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE124,Huffman code 124"
|
|
group.long 0x5F8++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_7,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN15,Huffman length 15"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE15,Huffman code 15"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN14,Huffman length 14"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE14,Huffman code 14"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_63,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN127,Huffman length 127"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE127,Huffman code 127"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN126,Huffman length 126"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE126,Huffman code 126"
|
|
group.long 0x5FC++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_8,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN17,Huffman length 17"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE17,Huffman code 17"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN16,Huffman length 16"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE16,Huffman code 16"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_64,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN129,Huffman length 129"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE129,Huffman code 129"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN128,Huffman length 128"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE128,Huffman code 128"
|
|
group.long 0x600++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_9,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN19,Huffman length 19"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE19,Huffman code 19"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN18,Huffman length 18"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE18,Huffman code 18"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_65,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN131,Huffman length 131"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE131,Huffman code 131"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN130,Huffman length 130"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE130,Huffman code 130"
|
|
group.long 0x604++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_10,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN21,Huffman length 21"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE21,Huffman code 21"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN20,Huffman length 20"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE20,Huffman code 20"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_66,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN133,Huffman length 133"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE133,Huffman code 133"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN132,Huffman length 132"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE132,Huffman code 132"
|
|
group.long 0x608++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_11,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN23,Huffman length 23"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE23,Huffman code 23"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN22,Huffman length 22"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE22,Huffman code 22"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_67,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN135,Huffman length 135"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE135,Huffman code 135"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN134,Huffman length 134"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE134,Huffman code 134"
|
|
group.long 0x60C++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_12,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN25,Huffman length 25"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE25,Huffman code 25"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN24,Huffman length 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE24,Huffman code 24"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_68,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN137,Huffman length 137"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE137,Huffman code 137"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN136,Huffman length 136"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE136,Huffman code 136"
|
|
group.long 0x610++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_13,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN27,Huffman length 27"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE27,Huffman code 27"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN26,Huffman length 26"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE26,Huffman code 26"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_69,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN139,Huffman length 139"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE139,Huffman code 139"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN138,Huffman length 138"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE138,Huffman code 138"
|
|
group.long 0x614++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_14,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN29,Huffman length 29"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE29,Huffman code 29"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN28,Huffman length 28"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE28,Huffman code 28"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_70,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN141,Huffman length 141"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE141,Huffman code 141"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN140,Huffman length 140"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE140,Huffman code 140"
|
|
group.long 0x618++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_15,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN31,Huffman length 31"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE31,Huffman code 31"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN30,Huffman length 30"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE30,Huffman code 30"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_71,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN143,Huffman length 143"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE143,Huffman code 143"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN142,Huffman length 142"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE142,Huffman code 142"
|
|
group.long 0x61C++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_16,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN33,Huffman length 33"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE33,Huffman code 33"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN32,Huffman length 32"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE32,Huffman code 32"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_72,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN145,Huffman length 145"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE145,Huffman code 145"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN144,Huffman length 144"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE144,Huffman code 144"
|
|
group.long 0x620++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_17,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN35,Huffman length 35"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE35,Huffman code 35"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN34,Huffman length 34"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE34,Huffman code 34"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_73,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN147,Huffman length 147"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE147,Huffman code 147"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN146,Huffman length 146"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE146,Huffman code 146"
|
|
group.long 0x624++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_18,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN37,Huffman length 37"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE37,Huffman code 37"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN36,Huffman length 36"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE36,Huffman code 36"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_74,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN149,Huffman length 149"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE149,Huffman code 149"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN148,Huffman length 148"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE148,Huffman code 148"
|
|
group.long 0x628++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_19,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN39,Huffman length 39"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE39,Huffman code 39"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN38,Huffman length 38"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE38,Huffman code 38"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_75,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN151,Huffman length 151"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE151,Huffman code 151"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN150,Huffman length 150"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE150,Huffman code 150"
|
|
group.long 0x62C++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_20,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN41,Huffman length 41"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE41,Huffman code 41"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN40,Huffman length 40"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE40,Huffman code 40"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_76,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN153,Huffman length 153"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE153,Huffman code 153"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN152,Huffman length 152"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE152,Huffman code 152"
|
|
group.long 0x630++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_21,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN43,Huffman length 43"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE43,Huffman code 43"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN42,Huffman length 42"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE42,Huffman code 42"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_77,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN155,Huffman length 155"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE155,Huffman code 155"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN154,Huffman length 154"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE154,Huffman code 154"
|
|
group.long 0x634++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_22,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN45,Huffman length 45"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE45,Huffman code 45"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN44,Huffman length 44"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE44,Huffman code 44"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_78,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN157,Huffman length 157"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE157,Huffman code 157"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN156,Huffman length 156"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE156,Huffman code 156"
|
|
group.long 0x638++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_23,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN47,Huffman length 47"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE47,Huffman code 47"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN46,Huffman length 46"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE46,Huffman code 46"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_79,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN159,Huffman length 159"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE159,Huffman code 159"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN158,Huffman length 158"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE158,Huffman code 158"
|
|
group.long 0x63C++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_24,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN49,Huffman length 49"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE49,Huffman code 49"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN48,Huffman length 48"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE48,Huffman code 48"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_80,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN161,Huffman length 161"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE161,Huffman code 161"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN160,Huffman length 160"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE160,Huffman code 160"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_25,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN51,Huffman length 51"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE51,Huffman code 51"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN50,Huffman length 50"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE50,Huffman code 50"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_81,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN163,Huffman length 163"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE163,Huffman code 163"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN162,Huffman length 162"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE162,Huffman code 162"
|
|
group.long 0x644++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_26,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN53,Huffman length 53"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE53,Huffman code 53"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN52,Huffman length 52"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE52,Huffman code 52"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_82,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN165,Huffman length 165"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE165,Huffman code 165"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN164,Huffman length 164"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE164,Huffman code 164"
|
|
group.long 0x648++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_27,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN55,Huffman length 55"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE55,Huffman code 55"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN54,Huffman length 54"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE54,Huffman code 54"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_83,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN167,Huffman length 167"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE167,Huffman code 167"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN166,Huffman length 166"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE166,Huffman code 166"
|
|
group.long 0x64C++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_28,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN57,Huffman length 57"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE57,Huffman code 57"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN56,Huffman length 56"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE56,Huffman code 56"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_84,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN169,Huffman length 169"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE169,Huffman code 169"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN168,Huffman length 168"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE168,Huffman code 168"
|
|
group.long 0x650++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_29,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN59,Huffman length 59"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE59,Huffman code 59"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN58,Huffman length 58"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE58,Huffman code 58"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_85,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN171,Huffman length 171"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE171,Huffman code 171"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN170,Huffman length 170"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE170,Huffman code 170"
|
|
group.long 0x654++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_30,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN61,Huffman length 61"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE61,Huffman code 61"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN60,Huffman length 60"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE60,Huffman code 60"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_86,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN173,Huffman length 173"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE173,Huffman code 173"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN172,Huffman length 172"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE172,Huffman code 172"
|
|
group.long 0x658++0x7
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_31,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN63,Huffman length 63"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE63,Huffman code 63"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN62,Huffman length 62"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE62,Huffman code 62"
|
|
line.long 0x4 "JPEG_HUFFENC_AC0_87,JPEG Huffman encoder AC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN175,Huffman length 175"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE175,Huffman code 175"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN174,Huffman length 174"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE174,Huffman code 174"
|
|
group.long 0x65C++0xDF
|
|
line.long 0x0 "JPEG_HUFFENC_AC1_32,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN65,Huffman length 65"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE65,Huffman code 65"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN64,Huffman length 64"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE64,Huffman code 64"
|
|
line.long 0x4 "JPEG_HUFFENC_AC1_33,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN67,Huffman length 67"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE67,Huffman code 67"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN66,Huffman length 66"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE66,Huffman code 66"
|
|
line.long 0x8 "JPEG_HUFFENC_AC1_34,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x8 24.--27. 1. "HLEN69,Huffman length 69"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HCODE69,Huffman code 69"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "HLEN68,Huffman length 68"
|
|
hexmask.long.byte 0x8 0.--7. 1. "HCODE68,Huffman code 68"
|
|
line.long 0xC "JPEG_HUFFENC_AC1_35,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xC 24.--27. 1. "HLEN71,Huffman length 71"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HCODE71,Huffman code 71"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "HLEN70,Huffman length 70"
|
|
hexmask.long.byte 0xC 0.--7. 1. "HCODE70,Huffman code 70"
|
|
line.long 0x10 "JPEG_HUFFENC_AC1_36,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x10 24.--27. 1. "HLEN73,Huffman length 73"
|
|
hexmask.long.byte 0x10 16.--23. 1. "HCODE73,Huffman code 73"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "HLEN72,Huffman length 72"
|
|
hexmask.long.byte 0x10 0.--7. 1. "HCODE72,Huffman code 72"
|
|
line.long 0x14 "JPEG_HUFFENC_AC1_37,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x14 24.--27. 1. "HLEN75,Huffman length 75"
|
|
hexmask.long.byte 0x14 16.--23. 1. "HCODE75,Huffman code 75"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "HLEN74,Huffman length 74"
|
|
hexmask.long.byte 0x14 0.--7. 1. "HCODE74,Huffman code 74"
|
|
line.long 0x18 "JPEG_HUFFENC_AC1_38,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x18 24.--27. 1. "HLEN77,Huffman length 77"
|
|
hexmask.long.byte 0x18 16.--23. 1. "HCODE77,Huffman code 77"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--11. 1. "HLEN76,Huffman length 76"
|
|
hexmask.long.byte 0x18 0.--7. 1. "HCODE76,Huffman code 76"
|
|
line.long 0x1C "JPEG_HUFFENC_AC1_39,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "HLEN79,Huffman length 79"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "HCODE79,Huffman code 79"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--11. 1. "HLEN78,Huffman length 78"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "HCODE78,Huffman code 78"
|
|
line.long 0x20 "JPEG_HUFFENC_AC1_40,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x20 24.--27. 1. "HLEN81,Huffman length 81"
|
|
hexmask.long.byte 0x20 16.--23. 1. "HCODE81,Huffman code 81"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--11. 1. "HLEN80,Huffman length 80"
|
|
hexmask.long.byte 0x20 0.--7. 1. "HCODE80,Huffman code 80"
|
|
line.long 0x24 "JPEG_HUFFENC_AC1_41,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x24 24.--27. 1. "HLEN83,Huffman length 83"
|
|
hexmask.long.byte 0x24 16.--23. 1. "HCODE83,Huffman code 83"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--11. 1. "HLEN82,Huffman length 82"
|
|
hexmask.long.byte 0x24 0.--7. 1. "HCODE82,Huffman code 82"
|
|
line.long 0x28 "JPEG_HUFFENC_AC1_42,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x28 24.--27. 1. "HLEN85,Huffman length 85"
|
|
hexmask.long.byte 0x28 16.--23. 1. "HCODE85,Huffman code 85"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--11. 1. "HLEN84,Huffman length 84"
|
|
hexmask.long.byte 0x28 0.--7. 1. "HCODE84,Huffman code 84"
|
|
line.long 0x2C "JPEG_HUFFENC_AC1_43,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x2C 24.--27. 1. "HLEN87,Huffman length 87"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "HCODE87,Huffman code 87"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--11. 1. "HLEN86,Huffman length 86"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "HCODE86,Huffman code 86"
|
|
line.long 0x30 "JPEG_HUFFENC_AC1_44,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x30 24.--27. 1. "HLEN89,Huffman length 89"
|
|
hexmask.long.byte 0x30 16.--23. 1. "HCODE89,Huffman code 89"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--11. 1. "HLEN88,Huffman length 88"
|
|
hexmask.long.byte 0x30 0.--7. 1. "HCODE88,Huffman code 88"
|
|
line.long 0x34 "JPEG_HUFFENC_AC1_45,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x34 24.--27. 1. "HLEN91,Huffman length 91"
|
|
hexmask.long.byte 0x34 16.--23. 1. "HCODE91,Huffman code 91"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--11. 1. "HLEN90,Huffman length 90"
|
|
hexmask.long.byte 0x34 0.--7. 1. "HCODE90,Huffman code 90"
|
|
line.long 0x38 "JPEG_HUFFENC_AC1_46,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x38 24.--27. 1. "HLEN93,Huffman length 93"
|
|
hexmask.long.byte 0x38 16.--23. 1. "HCODE93,Huffman code 93"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--11. 1. "HLEN92,Huffman length 92"
|
|
hexmask.long.byte 0x38 0.--7. 1. "HCODE92,Huffman code 92"
|
|
line.long 0x3C "JPEG_HUFFENC_AC1_47,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x3C 24.--27. 1. "HLEN95,Huffman length 95"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "HCODE95,Huffman code 95"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--11. 1. "HLEN94,Huffman length 94"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "HCODE94,Huffman code 94"
|
|
line.long 0x40 "JPEG_HUFFENC_AC1_48,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x40 24.--27. 1. "HLEN97,Huffman length 97"
|
|
hexmask.long.byte 0x40 16.--23. 1. "HCODE97,Huffman code 97"
|
|
newline
|
|
hexmask.long.byte 0x40 8.--11. 1. "HLEN96,Huffman length 96"
|
|
hexmask.long.byte 0x40 0.--7. 1. "HCODE96,Huffman code 96"
|
|
line.long 0x44 "JPEG_HUFFENC_AC1_49,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x44 24.--27. 1. "HLEN99,Huffman length 99"
|
|
hexmask.long.byte 0x44 16.--23. 1. "HCODE99,Huffman code 99"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--11. 1. "HLEN98,Huffman length 98"
|
|
hexmask.long.byte 0x44 0.--7. 1. "HCODE98,Huffman code 98"
|
|
line.long 0x48 "JPEG_HUFFENC_AC1_50,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x48 24.--27. 1. "HLEN101,Huffman length 101"
|
|
hexmask.long.byte 0x48 16.--23. 1. "HCODE101,Huffman code 101"
|
|
newline
|
|
hexmask.long.byte 0x48 8.--11. 1. "HLEN100,Huffman length 100"
|
|
hexmask.long.byte 0x48 0.--7. 1. "HCODE100,Huffman code 100"
|
|
line.long 0x4C "JPEG_HUFFENC_AC1_51,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "HLEN103,Huffman length 103"
|
|
hexmask.long.byte 0x4C 16.--23. 1. "HCODE103,Huffman code 103"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "HLEN102,Huffman length 102"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "HCODE102,Huffman code 102"
|
|
line.long 0x50 "JPEG_HUFFENC_AC1_52,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x50 24.--27. 1. "HLEN105,Huffman length 105"
|
|
hexmask.long.byte 0x50 16.--23. 1. "HCODE105,Huffman code 105"
|
|
newline
|
|
hexmask.long.byte 0x50 8.--11. 1. "HLEN104,Huffman length 104"
|
|
hexmask.long.byte 0x50 0.--7. 1. "HCODE104,Huffman code 104"
|
|
line.long 0x54 "JPEG_HUFFENC_AC1_53,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x54 24.--27. 1. "HLEN107,Huffman length 107"
|
|
hexmask.long.byte 0x54 16.--23. 1. "HCODE107,Huffman code 107"
|
|
newline
|
|
hexmask.long.byte 0x54 8.--11. 1. "HLEN106,Huffman length 106"
|
|
hexmask.long.byte 0x54 0.--7. 1. "HCODE106,Huffman code 106"
|
|
line.long 0x58 "JPEG_HUFFENC_AC1_54,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x58 24.--27. 1. "HLEN109,Huffman length 109"
|
|
hexmask.long.byte 0x58 16.--23. 1. "HCODE109,Huffman code 109"
|
|
newline
|
|
hexmask.long.byte 0x58 8.--11. 1. "HLEN108,Huffman length 108"
|
|
hexmask.long.byte 0x58 0.--7. 1. "HCODE108,Huffman code 108"
|
|
line.long 0x5C "JPEG_HUFFENC_AC1_55,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x5C 24.--27. 1. "HLEN111,Huffman length 111"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "HCODE111,Huffman code 111"
|
|
newline
|
|
hexmask.long.byte 0x5C 8.--11. 1. "HLEN110,Huffman length 110"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "HCODE110,Huffman code 110"
|
|
line.long 0x60 "JPEG_HUFFENC_AC1_56,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x60 24.--27. 1. "HLEN113,Huffman length 113"
|
|
hexmask.long.byte 0x60 16.--23. 1. "HCODE113,Huffman code 113"
|
|
newline
|
|
hexmask.long.byte 0x60 8.--11. 1. "HLEN112,Huffman length 112"
|
|
hexmask.long.byte 0x60 0.--7. 1. "HCODE112,Huffman code 112"
|
|
line.long 0x64 "JPEG_HUFFENC_AC1_57,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x64 24.--27. 1. "HLEN115,Huffman length 115"
|
|
hexmask.long.byte 0x64 16.--23. 1. "HCODE115,Huffman code 115"
|
|
newline
|
|
hexmask.long.byte 0x64 8.--11. 1. "HLEN114,Huffman length 114"
|
|
hexmask.long.byte 0x64 0.--7. 1. "HCODE114,Huffman code 114"
|
|
line.long 0x68 "JPEG_HUFFENC_AC1_58,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x68 24.--27. 1. "HLEN117,Huffman length 117"
|
|
hexmask.long.byte 0x68 16.--23. 1. "HCODE117,Huffman code 117"
|
|
newline
|
|
hexmask.long.byte 0x68 8.--11. 1. "HLEN116,Huffman length 116"
|
|
hexmask.long.byte 0x68 0.--7. 1. "HCODE116,Huffman code 116"
|
|
line.long 0x6C "JPEG_HUFFENC_AC1_59,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x6C 24.--27. 1. "HLEN119,Huffman length 119"
|
|
hexmask.long.byte 0x6C 16.--23. 1. "HCODE119,Huffman code 119"
|
|
newline
|
|
hexmask.long.byte 0x6C 8.--11. 1. "HLEN118,Huffman length 118"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "HCODE118,Huffman code 118"
|
|
line.long 0x70 "JPEG_HUFFENC_AC1_60,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x70 24.--27. 1. "HLEN121,Huffman length 121"
|
|
hexmask.long.byte 0x70 16.--23. 1. "HCODE121,Huffman code 121"
|
|
newline
|
|
hexmask.long.byte 0x70 8.--11. 1. "HLEN120,Huffman length 120"
|
|
hexmask.long.byte 0x70 0.--7. 1. "HCODE120,Huffman code 120"
|
|
line.long 0x74 "JPEG_HUFFENC_AC1_61,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x74 24.--27. 1. "HLEN123,Huffman length 123"
|
|
hexmask.long.byte 0x74 16.--23. 1. "HCODE123,Huffman code 123"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--11. 1. "HLEN122,Huffman length 122"
|
|
hexmask.long.byte 0x74 0.--7. 1. "HCODE122,Huffman code 122"
|
|
line.long 0x78 "JPEG_HUFFENC_AC1_62,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x78 24.--27. 1. "HLEN125,Huffman length 125"
|
|
hexmask.long.byte 0x78 16.--23. 1. "HCODE125,Huffman code 125"
|
|
newline
|
|
hexmask.long.byte 0x78 8.--11. 1. "HLEN124,Huffman length 124"
|
|
hexmask.long.byte 0x78 0.--7. 1. "HCODE124,Huffman code 124"
|
|
line.long 0x7C "JPEG_HUFFENC_AC1_63,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x7C 24.--27. 1. "HLEN127,Huffman length 127"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "HCODE127,Huffman code 127"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--11. 1. "HLEN126,Huffman length 126"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "HCODE126,Huffman code 126"
|
|
line.long 0x80 "JPEG_HUFFENC_AC1_64,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x80 24.--27. 1. "HLEN129,Huffman length 129"
|
|
hexmask.long.byte 0x80 16.--23. 1. "HCODE129,Huffman code 129"
|
|
newline
|
|
hexmask.long.byte 0x80 8.--11. 1. "HLEN128,Huffman length 128"
|
|
hexmask.long.byte 0x80 0.--7. 1. "HCODE128,Huffman code 128"
|
|
line.long 0x84 "JPEG_HUFFENC_AC1_65,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x84 24.--27. 1. "HLEN131,Huffman length 131"
|
|
hexmask.long.byte 0x84 16.--23. 1. "HCODE131,Huffman code 131"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--11. 1. "HLEN130,Huffman length 130"
|
|
hexmask.long.byte 0x84 0.--7. 1. "HCODE130,Huffman code 130"
|
|
line.long 0x88 "JPEG_HUFFENC_AC1_66,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x88 24.--27. 1. "HLEN133,Huffman length 133"
|
|
hexmask.long.byte 0x88 16.--23. 1. "HCODE133,Huffman code 133"
|
|
newline
|
|
hexmask.long.byte 0x88 8.--11. 1. "HLEN132,Huffman length 132"
|
|
hexmask.long.byte 0x88 0.--7. 1. "HCODE132,Huffman code 132"
|
|
line.long 0x8C "JPEG_HUFFENC_AC1_67,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x8C 24.--27. 1. "HLEN135,Huffman length 135"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "HCODE135,Huffman code 135"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--11. 1. "HLEN134,Huffman length 134"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "HCODE134,Huffman code 134"
|
|
line.long 0x90 "JPEG_HUFFENC_AC1_68,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x90 24.--27. 1. "HLEN137,Huffman length 137"
|
|
hexmask.long.byte 0x90 16.--23. 1. "HCODE137,Huffman code 137"
|
|
newline
|
|
hexmask.long.byte 0x90 8.--11. 1. "HLEN136,Huffman length 136"
|
|
hexmask.long.byte 0x90 0.--7. 1. "HCODE136,Huffman code 136"
|
|
line.long 0x94 "JPEG_HUFFENC_AC1_69,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x94 24.--27. 1. "HLEN139,Huffman length 139"
|
|
hexmask.long.byte 0x94 16.--23. 1. "HCODE139,Huffman code 139"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--11. 1. "HLEN138,Huffman length 138"
|
|
hexmask.long.byte 0x94 0.--7. 1. "HCODE138,Huffman code 138"
|
|
line.long 0x98 "JPEG_HUFFENC_AC1_70,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x98 24.--27. 1. "HLEN141,Huffman length 141"
|
|
hexmask.long.byte 0x98 16.--23. 1. "HCODE141,Huffman code 141"
|
|
newline
|
|
hexmask.long.byte 0x98 8.--11. 1. "HLEN140,Huffman length 140"
|
|
hexmask.long.byte 0x98 0.--7. 1. "HCODE140,Huffman code 140"
|
|
line.long 0x9C "JPEG_HUFFENC_AC1_71,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0x9C 24.--27. 1. "HLEN143,Huffman length 143"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "HCODE143,Huffman code 143"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--11. 1. "HLEN142,Huffman length 142"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "HCODE142,Huffman code 142"
|
|
line.long 0xA0 "JPEG_HUFFENC_AC1_72,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xA0 24.--27. 1. "HLEN145,Huffman length 145"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "HCODE145,Huffman code 145"
|
|
newline
|
|
hexmask.long.byte 0xA0 8.--11. 1. "HLEN144,Huffman length 144"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "HCODE144,Huffman code 144"
|
|
line.long 0xA4 "JPEG_HUFFENC_AC1_73,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xA4 24.--27. 1. "HLEN147,Huffman length 147"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "HCODE147,Huffman code 147"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--11. 1. "HLEN146,Huffman length 146"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "HCODE146,Huffman code 146"
|
|
line.long 0xA8 "JPEG_HUFFENC_AC1_74,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xA8 24.--27. 1. "HLEN149,Huffman length 149"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "HCODE149,Huffman code 149"
|
|
newline
|
|
hexmask.long.byte 0xA8 8.--11. 1. "HLEN148,Huffman length 148"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "HCODE148,Huffman code 148"
|
|
line.long 0xAC "JPEG_HUFFENC_AC1_75,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xAC 24.--27. 1. "HLEN151,Huffman length 151"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "HCODE151,Huffman code 151"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--11. 1. "HLEN150,Huffman length 150"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "HCODE150,Huffman code 150"
|
|
line.long 0xB0 "JPEG_HUFFENC_AC1_76,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xB0 24.--27. 1. "HLEN153,Huffman length 153"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "HCODE153,Huffman code 153"
|
|
newline
|
|
hexmask.long.byte 0xB0 8.--11. 1. "HLEN152,Huffman length 152"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "HCODE152,Huffman code 152"
|
|
line.long 0xB4 "JPEG_HUFFENC_AC1_77,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xB4 24.--27. 1. "HLEN155,Huffman length 155"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "HCODE155,Huffman code 155"
|
|
newline
|
|
hexmask.long.byte 0xB4 8.--11. 1. "HLEN154,Huffman length 154"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "HCODE154,Huffman code 154"
|
|
line.long 0xB8 "JPEG_HUFFENC_AC1_78,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xB8 24.--27. 1. "HLEN157,Huffman length 157"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "HCODE157,Huffman code 157"
|
|
newline
|
|
hexmask.long.byte 0xB8 8.--11. 1. "HLEN156,Huffman length 156"
|
|
hexmask.long.byte 0xB8 0.--7. 1. "HCODE156,Huffman code 156"
|
|
line.long 0xBC "JPEG_HUFFENC_AC1_79,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xBC 24.--27. 1. "HLEN159,Huffman length 159"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "HCODE159,Huffman code 159"
|
|
newline
|
|
hexmask.long.byte 0xBC 8.--11. 1. "HLEN158,Huffman length 158"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "HCODE158,Huffman code 158"
|
|
line.long 0xC0 "JPEG_HUFFENC_AC1_80,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xC0 24.--27. 1. "HLEN161,Huffman length 161"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "HCODE161,Huffman code 161"
|
|
newline
|
|
hexmask.long.byte 0xC0 8.--11. 1. "HLEN160,Huffman length 160"
|
|
hexmask.long.byte 0xC0 0.--7. 1. "HCODE160,Huffman code 160"
|
|
line.long 0xC4 "JPEG_HUFFENC_AC1_81,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xC4 24.--27. 1. "HLEN163,Huffman length 163"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "HCODE163,Huffman code 163"
|
|
newline
|
|
hexmask.long.byte 0xC4 8.--11. 1. "HLEN162,Huffman length 162"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "HCODE162,Huffman code 162"
|
|
line.long 0xC8 "JPEG_HUFFENC_AC1_82,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xC8 24.--27. 1. "HLEN165,Huffman length 165"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "HCODE165,Huffman code 165"
|
|
newline
|
|
hexmask.long.byte 0xC8 8.--11. 1. "HLEN164,Huffman length 164"
|
|
hexmask.long.byte 0xC8 0.--7. 1. "HCODE164,Huffman code 164"
|
|
line.long 0xCC "JPEG_HUFFENC_AC1_83,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xCC 24.--27. 1. "HLEN167,Huffman length 167"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "HCODE167,Huffman code 167"
|
|
newline
|
|
hexmask.long.byte 0xCC 8.--11. 1. "HLEN166,Huffman length 166"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "HCODE166,Huffman code 166"
|
|
line.long 0xD0 "JPEG_HUFFENC_AC1_84,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xD0 24.--27. 1. "HLEN169,Huffman length 169"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "HCODE169,Huffman code 169"
|
|
newline
|
|
hexmask.long.byte 0xD0 8.--11. 1. "HLEN168,Huffman length 168"
|
|
hexmask.long.byte 0xD0 0.--7. 1. "HCODE168,Huffman code 168"
|
|
line.long 0xD4 "JPEG_HUFFENC_AC1_85,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xD4 24.--27. 1. "HLEN171,Huffman length 171"
|
|
hexmask.long.byte 0xD4 16.--23. 1. "HCODE171,Huffman code 171"
|
|
newline
|
|
hexmask.long.byte 0xD4 8.--11. 1. "HLEN170,Huffman length 170"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "HCODE170,Huffman code 170"
|
|
line.long 0xD8 "JPEG_HUFFENC_AC1_86,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xD8 24.--27. 1. "HLEN173,Huffman length 173"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "HCODE173,Huffman code 173"
|
|
newline
|
|
hexmask.long.byte 0xD8 8.--11. 1. "HLEN172,Huffman length 172"
|
|
hexmask.long.byte 0xD8 0.--7. 1. "HCODE172,Huffman code 172"
|
|
line.long 0xDC "JPEG_HUFFENC_AC1_87,JPEG Huffman encoder AC1"
|
|
hexmask.long.byte 0xDC 24.--27. 1. "HLEN175,Huffman length 175"
|
|
hexmask.long.byte 0xDC 16.--23. 1. "HCODE175,Huffman code 175"
|
|
newline
|
|
hexmask.long.byte 0xDC 8.--11. 1. "HLEN174,Huffman length 174"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "HCODE174,Huffman code 174"
|
|
group.long 0x7C0++0x1F
|
|
line.long 0x0 "JPEG_HUFFENC_DC0_0,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0"
|
|
line.long 0x4 "JPEG_HUFFENC_DC0_1,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2"
|
|
line.long 0x8 "JPEG_HUFFENC_DC0_2,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4"
|
|
hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4"
|
|
line.long 0xC "JPEG_HUFFENC_DC0_3,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6"
|
|
hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6"
|
|
line.long 0x10 "JPEG_HUFFENC_DC0_4,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9"
|
|
hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8"
|
|
hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8"
|
|
line.long 0x14 "JPEG_HUFFENC_DC0_5,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11"
|
|
hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10"
|
|
hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10"
|
|
line.long 0x18 "JPEG_HUFFENC_DC0_6,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13"
|
|
hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12"
|
|
hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12"
|
|
line.long 0x1C "JPEG_HUFFENC_DC0_7,JPEG Huffman encoder DC0"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14"
|
|
group.long 0x89C++0x1F
|
|
line.long 0x0 "JPEG_HUFFENC_DC1_0,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HLEN1,Huffman length 1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "HCODE1,Huffman code 1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HLEN0,Huffman length 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HCODE0,Huffman code 0"
|
|
line.long 0x4 "JPEG_HUFFENC_DC1_1,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HLEN3,Huffman length 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HCODE3,Huffman code 3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "HLEN2,Huffman length 2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HCODE2,Huffman code 2"
|
|
line.long 0x8 "JPEG_HUFFENC_DC1_2,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x8 24.--27. 1. "HLEN5,Huffman length 5"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HCODE5,Huffman code 5"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "HLEN4,Huffman length 4"
|
|
hexmask.long.byte 0x8 0.--7. 1. "HCODE4,Huffman code 4"
|
|
line.long 0xC "JPEG_HUFFENC_DC1_3,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0xC 24.--27. 1. "HLEN7,Huffman length 7"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HCODE7,Huffman code 7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "HLEN6,Huffman length 6"
|
|
hexmask.long.byte 0xC 0.--7. 1. "HCODE6,Huffman code 6"
|
|
line.long 0x10 "JPEG_HUFFENC_DC1_4,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x10 24.--27. 1. "HLEN9,Huffman length 9"
|
|
hexmask.long.byte 0x10 16.--23. 1. "HCODE9,Huffman code 9"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "HLEN8,Huffman length 8"
|
|
hexmask.long.byte 0x10 0.--7. 1. "HCODE8,Huffman code 8"
|
|
line.long 0x14 "JPEG_HUFFENC_DC1_5,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x14 24.--27. 1. "HLEN11,Huffman length 11"
|
|
hexmask.long.byte 0x14 16.--23. 1. "HCODE11,Huffman code 11"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "HLEN10,Huffman length 10"
|
|
hexmask.long.byte 0x14 0.--7. 1. "HCODE10,Huffman code 10"
|
|
line.long 0x18 "JPEG_HUFFENC_DC1_6,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x18 24.--27. 1. "HLEN13,Huffman length 13"
|
|
hexmask.long.byte 0x18 16.--23. 1. "HCODE13,Huffman code 13"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--11. 1. "HLEN12,Huffman length 12"
|
|
hexmask.long.byte 0x18 0.--7. 1. "HCODE12,Huffman code 12"
|
|
line.long 0x1C "JPEG_HUFFENC_DC1_7,JPEG Huffman encoder DC1"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "HLEN15,Huffman length 15"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "HCODE15,Huffman code 15"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--11. 1. "HLEN14,Huffman length 14"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "HCODE14,Huffman code 14"
|
|
tree.end
|
|
tree "LPTIM (Low Power Timer)"
|
|
base ad:0x0
|
|
tree "LPTIM1"
|
|
base ad:0x40002400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
|
|
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
|
|
newline
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register"
|
|
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
|
|
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register"
|
|
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
|
|
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
|
|
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x58002400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
|
|
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
|
|
newline
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register"
|
|
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
|
|
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM2 interrupt enable register"
|
|
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
|
|
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
|
|
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
tree.end
|
|
tree "LPTIM3"
|
|
base ad:0x58002800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
|
|
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
|
|
newline
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register"
|
|
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
|
|
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register"
|
|
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
|
|
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
|
|
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
tree.end
|
|
tree "LPTIM4"
|
|
base ad:0x58002C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM4_ISR,LPTIM4 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM4_ICR,LPTIM4 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM4_DIER,LPTIM4 interrupt enable register"
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
|
|
tree.end
|
|
tree "LPTIM5"
|
|
base ad:0x58003000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM5_ISR,LPTIM5 interrupt and status register"
|
|
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
|
|
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM5_ICR,LPTIM5 interrupt clear register"
|
|
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "LPTIM5_DIER,LPTIM5 interrupt enable register"
|
|
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
|
|
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
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tree.end
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tree.end
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|
tree "LPUART (Low-Power Universal Asynchronous Receiver/Transmitter)"
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base ad:0x58000C00
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group.long 0x0++0x3
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line.long 0x0 "LPUART_CR1_ENABLED,LPUART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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newline
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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newline
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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newline
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.."
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newline
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
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newline
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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newline
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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newline
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bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
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group.long 0x0++0xF
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line.long 0x0 "LPUART_CR1_DISABLED,LPUART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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newline
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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newline
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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newline
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.."
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newline
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
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newline
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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newline
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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newline
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bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
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line.long 0x4 "LPUART_CR2,LPUART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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newline
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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newline
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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newline
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bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,1: Reserved.,2: 2 stop bits,3: FIELD Reserved"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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line.long 0x8 "LPUART_CR3,LPUART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
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newline
|
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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newline
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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newline
|
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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newline
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.."
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line.long 0xC "LPUART_BRR,LPUART baud rate register"
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hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)"
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wgroup.long 0x18++0x3
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line.long 0x0 "LPUART_RQR,LPUART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "LPUART_ISR_ENABLED,LPUART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty."
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newline
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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newline
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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newline
|
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
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newline
|
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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newline
|
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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newline
|
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bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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newline
|
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "LPUART_ISR_DISABLED,LPUART interrupt and status register"
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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newline
|
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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newline
|
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
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newline
|
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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newline
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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newline
|
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bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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newline
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "LPUART_RDR,LPUART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "LPUART_TDR,LPUART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
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tree.end
|
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tree "LTDC (LCD-TFT Display Controller)"
|
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base ad:0x50001000
|
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group.long 0x8++0x13
|
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line.long 0x0 "LTDC_SSCR,LTDC synchronization size configuration register"
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hexmask.long.word 0x0 16.--27. 1. "HSW,horizontal synchronization width (in units of pixel clock period)"
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hexmask.long.word 0x0 0.--10. 1. "VSH,vertical synchronization height (in units of horizontal scan line)"
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line.long 0x4 "LTDC_BPCR,LTDC back porch configuration register"
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hexmask.long.word 0x4 16.--27. 1. "AHBP,accumulated horizontal back porch (in units of pixel clock period)"
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hexmask.long.word 0x4 0.--10. 1. "AVBP,accumulated Vertical back porch (in units of horizontal scan line)"
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line.long 0x8 "LTDC_AWCR,LTDC active width configuration register"
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hexmask.long.word 0x8 16.--27. 1. "AAW,accumulated active width (in units of pixel clock period)"
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hexmask.long.word 0x8 0.--10. 1. "AAH,accumulated active height (in units of horizontal scan line)"
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line.long 0xC "LTDC_TWCR,LTDC total width configuration register"
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hexmask.long.word 0xC 16.--27. 1. "TOTALW,total width (in units of pixel clock period)"
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hexmask.long.word 0xC 0.--10. 1. "TOTALH,total height (in units of horizontal scan line)"
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line.long 0x10 "LTDC_GCR,LTDC global control register"
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bitfld.long 0x10 31. "HSPOL,horizontal synchronization polarity" "0: horizontal synchronization polarity is active low.,1: horizontal synchronization polarity is active.."
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bitfld.long 0x10 30. "VSPOL,vertical synchronization polarity" "0: vertical synchronization is active low.,1: vertical synchronization is active high."
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newline
|
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bitfld.long 0x10 29. "DEPOL,not data enable polarity" "0: not data enable polarity is active low.,1: not data enable polarity is active high."
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bitfld.long 0x10 28. "PCPOL,pixel clock polarity" "0: pixel clock polarity is active low.,1: pixel clock is active high."
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newline
|
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bitfld.long 0x10 16. "DEN,dither enable" "0: dither disabled,1: dither enabled"
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rbitfld.long 0x10 12.--14. "DRW,dither red width" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x10 8.--10. "DGW,dither green width" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x10 4.--6. "DBW,dither blue width" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x10 0. "LTDCEN,LCD-TFT controller enable" "0: LTDC disabled,1: LTDC enabled"
|
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group.long 0x24++0x3
|
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line.long 0x0 "LTDC_SRCR,LTDC shadow reload configuration register"
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bitfld.long 0x0 1. "VBR,vertical blanking reload" "0: no effect,1: The shadow registers are reloaded during the.."
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bitfld.long 0x0 0. "IMR,immediate reload" "0: no effect,1: The shadow registers are reloaded immediately."
|
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group.long 0x2C++0x3
|
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line.long 0x0 "LTDC_BCCR,LTDC background color configuration register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BCRED,background color red value"
|
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hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,background color green value"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,background color blue value"
|
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group.long 0x34++0x3
|
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line.long 0x0 "LTDC_IER,LTDC interrupt enable register"
|
|
bitfld.long 0x0 3. "RRIE,register reload interrupt enable" "0: register reload interrupt disable,1: register reload interrupt enable"
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bitfld.long 0x0 2. "TERRIE,transfer error interrupt enable" "0: transfer error interrupt disable,1: transfer error interrupt enable"
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newline
|
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bitfld.long 0x0 1. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disable,1: FIFO underrun Interrupt enable"
|
|
bitfld.long 0x0 0. "LIE,line interrupt enable" "0: line interrupt disable,1: line interrupt enable"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "LTDC_ISR,LTDC interrupt status register"
|
|
bitfld.long 0x0 3. "RRIF,register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.."
|
|
bitfld.long 0x0 2. "TERRIF,transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.."
|
|
newline
|
|
bitfld.long 0x0 1. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated.,1: FIFO underrun interrupt generated if one of the.."
|
|
bitfld.long 0x0 0. "LIF,line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.."
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "LTDC_ICR,LTDC interrupt clear register"
|
|
bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in the LTDC_ISR register"
|
|
bitfld.long 0x0 2. "CTERRIF,clears the transfer error interrupt flag" "0: no effect,1: clears the TERRIF flag in the LTDC_ISR register."
|
|
newline
|
|
bitfld.long 0x0 1. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUDERRIF flag in the LTDC_ISR register."
|
|
bitfld.long 0x0 0. "CLIF,clears the line interrupt flag" "0: no effect,1: clears the LIF flag in the LTDC_ISR register."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "LTDC_LIPCR,LTDC line interrupt position configuration register"
|
|
hexmask.long.word 0x0 0.--10. 1. "LIPOS,line interrupt position"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "LTDC_CPSR,LTDC current position status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CXPOS,current X position"
|
|
hexmask.long.word 0x0 0.--15. 1. "CYPOS,current Y position"
|
|
line.long 0x4 "LTDC_CDSR,LTDC current display status register"
|
|
bitfld.long 0x4 3. "HSYNCS,horizontal synchronization display status" "0: active low,1: active high"
|
|
bitfld.long 0x4 2. "VSYNCS,vertical synchronization display status" "0: active low,1: active high"
|
|
newline
|
|
bitfld.long 0x4 1. "HDES,horizontal data enable display status" "0: active low,1: active high"
|
|
bitfld.long 0x4 0. "VDES,vertical data enable display status" "0: active low,1: active high"
|
|
group.long 0x84++0x1F
|
|
line.long 0x0 "LTDC_L1CR,LTDC layer 1 control register"
|
|
bitfld.long 0x0 4. "CLUTEN,color look-up table enable" "0: color look-up table disable,1: color look-up table enable"
|
|
bitfld.long 0x0 1. "COLKEN,color keying enable" "0: color keying disable,1: color keying enable"
|
|
newline
|
|
bitfld.long 0x0 0. "LEN,layer enable" "0: layer disable,1: layer enable"
|
|
line.long 0x4 "LTDC_L1WHPCR,LTDC layer 1 window horizontal position configuration register"
|
|
hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,window horizontal stop position"
|
|
hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,window horizontal start position"
|
|
line.long 0x8 "LTDC_L1WVPCR,LTDC layer 1 window vertical position configuration register"
|
|
hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,window vertical stop position"
|
|
hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,window vertical start position"
|
|
line.long 0xC "LTDC_L1CKCR,LTDC layer 1 color keying configuration register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CKRED,color key red value"
|
|
hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,color key green value"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,color key blue value"
|
|
line.long 0x10 "LTDC_L1PFCR,LTDC layer 1 pixel format configuration register"
|
|
bitfld.long 0x10 0.--2. "PF,pixel format" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,5: L8 (8-bit luminance),6: AL44 (4-bit alpha 4-bit luminance),7: AL88 (8-bit alpha 8-bit luminance)"
|
|
line.long 0x14 "LTDC_L1CACR,LTDC layer 1 constant alpha configuration register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "CONSTA,constant alpha"
|
|
line.long 0x18 "LTDC_L1DCCR,LTDC layer 1 default color configuration register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,default color alpha"
|
|
hexmask.long.byte 0x18 16.--23. 1. "DCRED,default color red"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,default color green"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,default color blue"
|
|
line.long 0x1C "LTDC_L1BFCR,LTDC layer 1 blending factors configuration register"
|
|
bitfld.long 0x1C 8.--10. "BF1,blending factor 1" "0: FIELD Reserved,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: constant alpha,5: FIELD Reserved,6: pixel alpha x constant alpha,7: FIELD Reserved"
|
|
bitfld.long 0x1C 0.--2. "BF2,blending factor 2" "0: FIELD Reserved,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: FIELD Reserved,5: 1 - constant alpha,6: FIELD Reserved,7: 1 - (pixel alpha x constant alpha)"
|
|
group.long 0xAC++0xB
|
|
line.long 0x0 "LTDC_L1CFBAR,LTDC layer 1 color frame buffer address register"
|
|
hexmask.long 0x0 0.--31. 1. "CFBADD,color frame buffer start address"
|
|
line.long 0x4 "LTDC_L1CFBLR,LTDC layer 1 color frame buffer length register"
|
|
hexmask.long.word 0x4 16.--28. 1. "CFBP,color frame buffer pitch in bytes"
|
|
hexmask.long.word 0x4 0.--12. 1. "CFBLL,color frame buffer line length"
|
|
line.long 0x8 "LTDC_L1CFBLNR,LTDC layer 1 color frame buffer line number register"
|
|
hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,frame buffer line number"
|
|
wgroup.long 0xC4++0x3
|
|
line.long 0x0 "LTDC_L1CLUTWR,LTDC layer 1 CLUT write register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED,red value"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value"
|
|
group.long 0x104++0x1F
|
|
line.long 0x0 "LTDC_L2CR,LTDC layer 2 control register"
|
|
bitfld.long 0x0 4. "CLUTEN,color look-up table enable" "0: color look-up table disable,1: color look-up table enable"
|
|
bitfld.long 0x0 1. "COLKEN,color keying enable" "0: color keying disable,1: color keying enable"
|
|
newline
|
|
bitfld.long 0x0 0. "LEN,layer enable" "0: layer disable,1: layer enable"
|
|
line.long 0x4 "LTDC_L2WHPCR,LTDC layer 2 window horizontal position configuration register"
|
|
hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,window horizontal stop position"
|
|
hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,window horizontal start position"
|
|
line.long 0x8 "LTDC_L2WVPCR,LTDC layer 2 window vertical position configuration register"
|
|
hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,window vertical stop position"
|
|
hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,window vertical start position"
|
|
line.long 0xC "LTDC_L2CKCR,LTDC layer 2 color keying configuration register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CKRED,color key red value"
|
|
hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,color key green value"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,color key blue value"
|
|
line.long 0x10 "LTDC_L2PFCR,LTDC layer 2 pixel format configuration register"
|
|
bitfld.long 0x10 0.--2. "PF,pixel format" "0: ARGB8888,1: RGB888,2: RGB565,3: ARGB1555,4: ARGB4444,5: L8 (8-bit luminance),6: AL44 (4-bit alpha 4-bit luminance),7: AL88 (8-bit alpha 8-bit luminance)"
|
|
line.long 0x14 "LTDC_L2CACR,LTDC layer 2 constant alpha configuration register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "CONSTA,constant alpha"
|
|
line.long 0x18 "LTDC_L2DCCR,LTDC layer 2 default color configuration register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,default color alpha"
|
|
hexmask.long.byte 0x18 16.--23. 1. "DCRED,default color red"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,default color green"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,default color blue"
|
|
line.long 0x1C "LTDC_L2BFCR,LTDC layer 2 blending factors configuration register"
|
|
bitfld.long 0x1C 8.--10. "BF1,blending factor 1" "0: FIELD Reserved,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: constant alpha,5: FIELD Reserved,6: pixel alpha x constant alpha,7: FIELD Reserved"
|
|
bitfld.long 0x1C 0.--2. "BF2,blending factor 2" "0: FIELD Reserved,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: FIELD Reserved,5: 1 - constant alpha,6: FIELD Reserved,7: 1 - (pixel alpha x constant alpha)"
|
|
group.long 0x12C++0xB
|
|
line.long 0x0 "LTDC_L2CFBAR,LTDC layer 2 color frame buffer address register"
|
|
hexmask.long 0x0 0.--31. 1. "CFBADD,color frame buffer start address"
|
|
line.long 0x4 "LTDC_L2CFBLR,LTDC layer 2 color frame buffer length register"
|
|
hexmask.long.word 0x4 16.--28. 1. "CFBP,color frame buffer pitch in bytes"
|
|
hexmask.long.word 0x4 0.--12. 1. "CFBLL,color frame buffer line length"
|
|
line.long 0x8 "LTDC_L2CFBLNR,LTDC layer 2 color frame buffer line number register"
|
|
hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,frame buffer line number"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "LTDC_L2CLUTWR,LTDC layer 2 CLUT write register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED,red value"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value"
|
|
tree.end
|
|
tree "MCE (Memory Cipher Engine)"
|
|
base ad:0x0
|
|
tree "MCE1"
|
|
base ad:0x5200B800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MCE_CR,MCE configuration register"
|
|
bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.."
|
|
bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.."
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "MCE_SR,MCE status register"
|
|
bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.."
|
|
bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.."
|
|
newline
|
|
bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.."
|
|
line.long 0x4 "MCE_IASR,MCE illegal access status register"
|
|
bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1"
|
|
bitfld.long 0x4 0. "CAEF,Configuration access error flag" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "MCE_IACR,MCE illegal access clear register"
|
|
bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "CAEF,Configuration access error flag clear" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register"
|
|
rbitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.."
|
|
bitfld.long 0x0 0. "CAEIE,Configuration access error interrupt enable" "0: Interrupt generation on configuration access..,1: Interrupt generation when a configuration access.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "MCE_PRIVCFGR,MCE privileged configuration register"
|
|
bitfld.long 0x0 0. "PRIV,Privileged configuration" "0: Privileged and unprivileged access are granted..,1: Only privileged access are granted to MCE.."
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "MCE_IAESR,MCE illegal access error status register"
|
|
bitfld.long 0x0 7. "IANRW,Illegal access read/write" "0: Illegal access was a data read or an instruction..,1: Illegal access was a data write."
|
|
bitfld.long 0x0 4. "IAPRIV,Illegal access privilege" "0: Illegal access was unprivileged.,1: Illegal access was privileged."
|
|
line.long 0x4 "MCE_IADDR,MCE illegal address register"
|
|
hexmask.long 0x4 0.--31. 1. "IADD,Illegal address"
|
|
group.long 0x40++0x3F
|
|
line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register"
|
|
bitfld.long 0x0 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register"
|
|
hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register"
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0xC "MCE_ATTR1,MCE attribute for region 1 register"
|
|
bitfld.long 0xC 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x10 "MCE_REGCR2,MCE region 2 configuration register"
|
|
bitfld.long 0x10 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x10 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x10 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x10 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x14 "MCE_SADDR2,MCE start address for region 2 register"
|
|
hexmask.long.tbyte 0x14 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x18 "MCE_EADDR2,MCE end address for region 2 register"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x1C "MCE_ATTR2,MCE attribute for region 2 register"
|
|
bitfld.long 0x1C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x20 "MCE_REGCR3,MCE region 3 configuration register"
|
|
bitfld.long 0x20 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x20 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x20 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x20 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x24 "MCE_SADDR3,MCE start address for region 3 register"
|
|
hexmask.long.tbyte 0x24 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x28 "MCE_EADDR3,MCE end address for region 3 register"
|
|
hexmask.long.tbyte 0x28 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x2C "MCE_ATTR3,MCE attribute for region 3 register"
|
|
bitfld.long 0x2C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x30 "MCE_REGCR4,MCE region 4 configuration register"
|
|
bitfld.long 0x30 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x30 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x30 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x30 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x34 "MCE_SADDR4,MCE start address for region 4 register"
|
|
hexmask.long.tbyte 0x34 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x38 "MCE_EADDR4,MCE end address for region 4 register"
|
|
hexmask.long.tbyte 0x38 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x3C "MCE_ATTR4,MCE attribute for region 4 register"
|
|
bitfld.long 0x3C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
wgroup.long 0x200++0xF
|
|
line.long 0x0 "MCE_MKEYR0,MCE master key 0"
|
|
bitfld.long 0x0 31. "MKEY31,Master key bit 31" "0,1"
|
|
bitfld.long 0x0 30. "MKEY30,Master key bit 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MKEY29,Master key bit 29" "0,1"
|
|
bitfld.long 0x0 28. "MKEY28,Master key bit 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MKEY27,Master key bit 27" "0,1"
|
|
bitfld.long 0x0 26. "MKEY26,Master key bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MKEY25,Master key bit 25" "0,1"
|
|
bitfld.long 0x0 24. "MKEY24,Master key bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MKEY23,Master key bit 23" "0,1"
|
|
bitfld.long 0x0 22. "MKEY22,Master key bit 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MKEY21,Master key bit 21" "0,1"
|
|
bitfld.long 0x0 20. "MKEY20,Master key bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MKEY19,Master key bit 19" "0,1"
|
|
bitfld.long 0x0 18. "MKEY18,Master key bit 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MKEY17,Master key bit 17" "0,1"
|
|
bitfld.long 0x0 16. "MKEY16,Master key bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MKEY15,Master key bit 15" "0,1"
|
|
bitfld.long 0x0 14. "MKEY14,Master key bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MKEY13,Master key bit 13" "0,1"
|
|
bitfld.long 0x0 12. "MKEY12,Master key bit 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MKEY11,Master key bit 11" "0,1"
|
|
bitfld.long 0x0 10. "MKEY10,Master key bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MKEY9,Master key bit 9" "0,1"
|
|
bitfld.long 0x0 8. "MKEY8,Master key bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MKEY7,Master key bit 7" "0,1"
|
|
bitfld.long 0x0 6. "MKEY6,Master key bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MKEY5,Master key bit 5" "0,1"
|
|
bitfld.long 0x0 4. "MKEY4,Master key bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MKEY3,Master key bit 3" "0,1"
|
|
bitfld.long 0x0 2. "MKEY2,Master key bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MKEY1,Master key bit 1" "0,1"
|
|
bitfld.long 0x0 0. "MKEY0,Master key bit 0" "0,1"
|
|
line.long 0x4 "MCE_MKEYR1,MCE master key 1"
|
|
bitfld.long 0x4 31. "MKEY63,Master key bit 63" "0,1"
|
|
bitfld.long 0x4 30. "MKEY62,Master key bit 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MKEY61,Master key bit 61" "0,1"
|
|
bitfld.long 0x4 28. "MKEY60,Master key bit 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MKEY59,Master key bit 59" "0,1"
|
|
bitfld.long 0x4 26. "MKEY58,Master key bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MKEY57,Master key bit 57" "0,1"
|
|
bitfld.long 0x4 24. "MKEY56,Master key bit 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MKEY55,Master key bit 55" "0,1"
|
|
bitfld.long 0x4 22. "MKEY54,Master key bit 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MKEY53,Master key bit 53" "0,1"
|
|
bitfld.long 0x4 20. "MKEY52,Master key bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MKEY51,Master key bit 51" "0,1"
|
|
bitfld.long 0x4 18. "MKEY50,Master key bit 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MKEY49,Master key bit 49" "0,1"
|
|
bitfld.long 0x4 16. "MKEY48,Master key bit 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MKEY47,Master key bit 47" "0,1"
|
|
bitfld.long 0x4 14. "MKEY46,Master key bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MKEY45,Master key bit 45" "0,1"
|
|
bitfld.long 0x4 12. "MKEY44,Master key bit 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MKEY43,Master key bit 43" "0,1"
|
|
bitfld.long 0x4 10. "MKEY42,Master key bit 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MKEY41,Master key bit 41" "0,1"
|
|
bitfld.long 0x4 8. "MKEY40,Master key bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MKEY39,Master key bit 39" "0,1"
|
|
bitfld.long 0x4 6. "MKEY38,Master key bit 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MKEY37,Master key bit 37" "0,1"
|
|
bitfld.long 0x4 4. "MKEY36,Master key bit 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MKEY35,Master key bit 35" "0,1"
|
|
bitfld.long 0x4 2. "MKEY34,Master key bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MKEY33,Master key bit 33" "0,1"
|
|
bitfld.long 0x4 0. "MKEY32,Master key bit 32" "0,1"
|
|
line.long 0x8 "MCE_MKEYR2,MCE master key 2"
|
|
bitfld.long 0x8 31. "MKEY95,Master key bit 95" "0,1"
|
|
bitfld.long 0x8 30. "MKEY94,Master key bit 94" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "MKEY93,Master key bit 93" "0,1"
|
|
bitfld.long 0x8 28. "MKEY92,Master key bit 92" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "MKEY91,Master key bit 91" "0,1"
|
|
bitfld.long 0x8 26. "MKEY90,Master key bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "MKEY89,Master key bit 89" "0,1"
|
|
bitfld.long 0x8 24. "MKEY88,Master key bit 88" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "MKEY87,Master key bit 87" "0,1"
|
|
bitfld.long 0x8 22. "MKEY86,Master key bit 86" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "MKEY85,Master key bit 85" "0,1"
|
|
bitfld.long 0x8 20. "MKEY84,Master key bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MKEY83,Master key bit 83" "0,1"
|
|
bitfld.long 0x8 18. "MKEY82,Master key bit 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MKEY81,Master key bit 81" "0,1"
|
|
bitfld.long 0x8 16. "MKEY80,Master key bit 80" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "MKEY79,Master key bit 79" "0,1"
|
|
bitfld.long 0x8 14. "MKEY78,Master key bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "MKEY77,Master key bit 77" "0,1"
|
|
bitfld.long 0x8 12. "MKEY76,Master key bit 76" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "MKEY75,Master key bit 75" "0,1"
|
|
bitfld.long 0x8 10. "MKEY74,Master key bit 74" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "MKEY73,Master key bit 73" "0,1"
|
|
bitfld.long 0x8 8. "MKEY72,Master key bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MKEY71,Master key bit 71" "0,1"
|
|
bitfld.long 0x8 6. "MKEY70,Master key bit 70" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "MKEY69,Master key bit 69" "0,1"
|
|
bitfld.long 0x8 4. "MKEY68,Master key bit 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "MKEY67,Master key bit 67" "0,1"
|
|
bitfld.long 0x8 2. "MKEY66,Master key bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "MKEY65,Master key bit 65" "0,1"
|
|
bitfld.long 0x8 0. "MKEY64,Master key bit 64" "0,1"
|
|
line.long 0xC "MCE_MKEYR3,MCE master key 3"
|
|
bitfld.long 0xC 31. "MKEY127,Master key bit 127" "0,1"
|
|
bitfld.long 0xC 30. "MKEY126,Master key bit 126" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "MKEY125,Master key bit 125" "0,1"
|
|
bitfld.long 0xC 28. "MKEY124,Master key bit 124" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "MKEY123,Master key bit 123" "0,1"
|
|
bitfld.long 0xC 26. "MKEY122,Master key bit 122" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "MKEY121,Master key bit 121" "0,1"
|
|
bitfld.long 0xC 24. "MKEY120,Master key bit 120" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "MKEY119,Master key bit 119" "0,1"
|
|
bitfld.long 0xC 22. "MKEY118,Master key bit 118" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "MKEY117,Master key bit 117" "0,1"
|
|
bitfld.long 0xC 20. "MKEY116,Master key bit 116" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MKEY115,Master key bit 115" "0,1"
|
|
bitfld.long 0xC 18. "MKEY114,Master key bit 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MKEY113,Master key bit 113" "0,1"
|
|
bitfld.long 0xC 16. "MKEY112,Master key bit 112" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "MKEY111,Master key bit 111" "0,1"
|
|
bitfld.long 0xC 14. "MKEY110,Master key bit 110" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "MKEY109,Master key bit 109" "0,1"
|
|
bitfld.long 0xC 12. "MKEY108,Master key bit 108" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "MKEY107,Master key bit 107" "0,1"
|
|
bitfld.long 0xC 10. "MKEY106,Master key bit 106" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "MKEY105,Master key bit 105" "0,1"
|
|
bitfld.long 0xC 8. "MKEY104,Master key bit 104" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "MKEY103,Master key bit 103" "0,1"
|
|
bitfld.long 0xC 6. "MKEY102,Master key bit 102" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MKEY101,Master key bit 101" "0,1"
|
|
bitfld.long 0xC 4. "MKEY100,Master key bit 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "MKEY99,Master key bit 99" "0,1"
|
|
bitfld.long 0xC 2. "MKEY98,Master key bit 98" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "MKEY97,Master key bit 97" "0,1"
|
|
bitfld.long 0xC 0. "MKEY96,Master key bit 96" "0,1"
|
|
wgroup.long 0x220++0xF
|
|
line.long 0x0 "MCE_FMKEYR0,MCE fast master key 0"
|
|
bitfld.long 0x0 31. "FMKEY31,Fast master key bit 31" "0,1"
|
|
bitfld.long 0x0 30. "FMKEY30,Fast master key bit 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FMKEY29,Fast master key bit 29" "0,1"
|
|
bitfld.long 0x0 28. "FMKEY28,Fast master key bit 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "FMKEY27,Fast master key bit 27" "0,1"
|
|
bitfld.long 0x0 26. "FMKEY26,Fast master key bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "FMKEY25,Fast master key bit 25" "0,1"
|
|
bitfld.long 0x0 24. "FMKEY24,Fast master key bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "FMKEY23,Fast master key bit 23" "0,1"
|
|
bitfld.long 0x0 22. "FMKEY22,Fast master key bit 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "FMKEY21,Fast master key bit 21" "0,1"
|
|
bitfld.long 0x0 20. "FMKEY20,Fast master key bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "FMKEY19,Fast master key bit 19" "0,1"
|
|
bitfld.long 0x0 18. "FMKEY18,Fast master key bit 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FMKEY17,Fast master key bit 17" "0,1"
|
|
bitfld.long 0x0 16. "FMKEY16,Fast master key bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "FMKEY15,Fast master key bit 15" "0,1"
|
|
bitfld.long 0x0 14. "FMKEY14,Fast master key bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "FMKEY13,Fast master key bit 13" "0,1"
|
|
bitfld.long 0x0 12. "FMKEY12,Fast master key bit 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "FMKEY11,Fast master key bit 11" "0,1"
|
|
bitfld.long 0x0 10. "FMKEY10,Fast master key bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "FMKEY9,Fast master key bit 9" "0,1"
|
|
bitfld.long 0x0 8. "FMKEY8,Fast master key bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "FMKEY7,Fast master key bit 7" "0,1"
|
|
bitfld.long 0x0 6. "FMKEY6,Fast master key bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FMKEY5,Fast master key bit 5" "0,1"
|
|
bitfld.long 0x0 4. "FMKEY4,Fast master key bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FMKEY3,Fast master key bit 3" "0,1"
|
|
bitfld.long 0x0 2. "FMKEY2,Fast master key bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FMKEY1,Fast master key bit 1" "0,1"
|
|
bitfld.long 0x0 0. "FMKEY0,Fast master key bit 0" "0,1"
|
|
line.long 0x4 "MCE_FMKEYR1,MCE fast master key 1"
|
|
bitfld.long 0x4 31. "FMKEY63,Fast master key bit 63" "0,1"
|
|
bitfld.long 0x4 30. "FMKEY62,Fast master key bit 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "FMKEY61,Fast master key bit 61" "0,1"
|
|
bitfld.long 0x4 28. "FMKEY60,Fast master key bit 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "FMKEY59,Fast master key bit 59" "0,1"
|
|
bitfld.long 0x4 26. "FMKEY58,Fast master key bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "FMKEY57,Fast master key bit 57" "0,1"
|
|
bitfld.long 0x4 24. "FMKEY56,Fast master key bit 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "FMKEY55,Fast master key bit 55" "0,1"
|
|
bitfld.long 0x4 22. "FMKEY54,Fast master key bit 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "FMKEY53,Fast master key bit 53" "0,1"
|
|
bitfld.long 0x4 20. "FMKEY52,Fast master key bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "FMKEY51,Fast master key bit 51" "0,1"
|
|
bitfld.long 0x4 18. "FMKEY50,Fast master key bit 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FMKEY49,Fast master key bit 49" "0,1"
|
|
bitfld.long 0x4 16. "FMKEY48,Fast master key bit 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FMKEY47,Fast master key bit 47" "0,1"
|
|
bitfld.long 0x4 14. "FMKEY46,Fast master key bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FMKEY45,Fast master key bit 45" "0,1"
|
|
bitfld.long 0x4 12. "FMKEY44,Fast master key bit 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "FMKEY43,Fast master key bit 43" "0,1"
|
|
bitfld.long 0x4 10. "FMKEY42,Fast master key bit 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "FMKEY41,Fast master key bit 41" "0,1"
|
|
bitfld.long 0x4 8. "FMKEY40,Fast master key bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "FMKEY39,Fast master key bit 39" "0,1"
|
|
bitfld.long 0x4 6. "FMKEY38,Fast master key bit 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FMKEY37,Fast master key bit 37" "0,1"
|
|
bitfld.long 0x4 4. "FMKEY36,Fast master key bit 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FMKEY35,Fast master key bit 35" "0,1"
|
|
bitfld.long 0x4 2. "FMKEY34,Fast master key bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FMKEY33,Fast master key bit 33" "0,1"
|
|
bitfld.long 0x4 0. "FMKEY32,Fast master key bit 32" "0,1"
|
|
line.long 0x8 "MCE_FMKEYR2,MCE fast master key 2"
|
|
bitfld.long 0x8 31. "FMKEY95,Fast master key bit 95" "0,1"
|
|
bitfld.long 0x8 30. "FMKEY94,Fast master key bit 94" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "FMKEY93,Fast master key bit 93" "0,1"
|
|
bitfld.long 0x8 28. "FMKEY92,Fast master key bit 92" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "FMKEY91,Fast master key bit 91" "0,1"
|
|
bitfld.long 0x8 26. "FMKEY90,Fast master key bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "FMKEY89,Fast master key bit 89" "0,1"
|
|
bitfld.long 0x8 24. "FMKEY88,Fast master key bit 88" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "FMKEY87,Fast master key bit 87" "0,1"
|
|
bitfld.long 0x8 22. "FMKEY86,Fast master key bit 86" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "FMKEY85,Fast master key bit 85" "0,1"
|
|
bitfld.long 0x8 20. "FMKEY84,Fast master key bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "FMKEY83,Fast master key bit 83" "0,1"
|
|
bitfld.long 0x8 18. "FMKEY82,Fast master key bit 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMKEY81,Fast master key bit 81" "0,1"
|
|
bitfld.long 0x8 16. "FMKEY80,Fast master key bit 80" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FMKEY79,Fast master key bit 79" "0,1"
|
|
bitfld.long 0x8 14. "FMKEY78,Fast master key bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FMKEY77,Fast master key bit 77" "0,1"
|
|
bitfld.long 0x8 12. "FMKEY76,Fast master key bit 76" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "FMKEY75,Fast master key bit 75" "0,1"
|
|
bitfld.long 0x8 10. "FMKEY74,Fast master key bit 74" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "FMKEY73,Fast master key bit 73" "0,1"
|
|
bitfld.long 0x8 8. "FMKEY72,Fast master key bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "FMKEY71,Fast master key bit 71" "0,1"
|
|
bitfld.long 0x8 6. "FMKEY70,Fast master key bit 70" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "FMKEY69,Fast master key bit 69" "0,1"
|
|
bitfld.long 0x8 4. "FMKEY68,Fast master key bit 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FMKEY67,Fast master key bit 67" "0,1"
|
|
bitfld.long 0x8 2. "FMKEY66,Fast master key bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "FMKEY65,Fast master key bit 65" "0,1"
|
|
bitfld.long 0x8 0. "FMKEY64,Fast master key bit 64" "0,1"
|
|
line.long 0xC "MCE_FMKEYR3,MCE fast master key 3"
|
|
bitfld.long 0xC 31. "FMKEY127,Fast master key bit 127" "0,1"
|
|
bitfld.long 0xC 30. "FMKEY126,Fast master key bit 126" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "FMKEY125,Fast master key bit 125" "0,1"
|
|
bitfld.long 0xC 28. "FMKEY124,Fast master key bit 124" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "FMKEY123,Fast master key bit 123" "0,1"
|
|
bitfld.long 0xC 26. "FMKEY122,Fast master key bit 122" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "FMKEY121,Fast master key bit 121" "0,1"
|
|
bitfld.long 0xC 24. "FMKEY120,Fast master key bit 120" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "FMKEY119,Fast master key bit 119" "0,1"
|
|
bitfld.long 0xC 22. "FMKEY118,Fast master key bit 118" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "FMKEY117,Fast master key bit 117" "0,1"
|
|
bitfld.long 0xC 20. "FMKEY116,Fast master key bit 116" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "FMKEY115,Fast master key bit 115" "0,1"
|
|
bitfld.long 0xC 18. "FMKEY114,Fast master key bit 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "FMKEY113,Fast master key bit 113" "0,1"
|
|
bitfld.long 0xC 16. "FMKEY112,Fast master key bit 112" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FMKEY111,Fast master key bit 111" "0,1"
|
|
bitfld.long 0xC 14. "FMKEY110,Fast master key bit 110" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FMKEY109,Fast master key bit 109" "0,1"
|
|
bitfld.long 0xC 12. "FMKEY108,Fast master key bit 108" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "FMKEY107,Fast master key bit 107" "0,1"
|
|
bitfld.long 0xC 10. "FMKEY106,Fast master key bit 106" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "FMKEY105,Fast master key bit 105" "0,1"
|
|
bitfld.long 0xC 8. "FMKEY104,Fast master key bit 104" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "FMKEY103,Fast master key bit 103" "0,1"
|
|
bitfld.long 0xC 6. "FMKEY102,Fast master key bit 102" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "FMKEY101,Fast master key bit 101" "0,1"
|
|
bitfld.long 0xC 4. "FMKEY100,Fast master key bit 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FMKEY99,Fast master key bit 99" "0,1"
|
|
bitfld.long 0xC 2. "FMKEY98,Fast master key bit 98" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "FMKEY97,Fast master key bit 97" "0,1"
|
|
bitfld.long 0xC 0. "FMKEY96,Fast master key bit 96" "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VERSION,Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC"
|
|
newline
|
|
bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.."
|
|
bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.."
|
|
line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0"
|
|
hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]"
|
|
line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1"
|
|
hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]"
|
|
wgroup.long 0x24C++0xF
|
|
line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]"
|
|
line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]"
|
|
line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]"
|
|
line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VERSION,Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC"
|
|
newline
|
|
bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.."
|
|
bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.."
|
|
line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0"
|
|
hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]"
|
|
line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1"
|
|
hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]"
|
|
wgroup.long 0x27C++0xF
|
|
line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]"
|
|
line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]"
|
|
line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]"
|
|
line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]"
|
|
tree.end
|
|
tree "MCE2"
|
|
base ad:0x5200BC00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MCE_CR,MCE configuration register"
|
|
bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.."
|
|
bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.."
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "MCE_SR,MCE status register"
|
|
bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.."
|
|
bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.."
|
|
newline
|
|
bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.."
|
|
line.long 0x4 "MCE_IASR,MCE illegal access status register"
|
|
bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1"
|
|
bitfld.long 0x4 0. "CAEF,Configuration access error flag" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "MCE_IACR,MCE illegal access clear register"
|
|
bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "CAEF,Configuration access error flag clear" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register"
|
|
rbitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.."
|
|
bitfld.long 0x0 0. "CAEIE,Configuration access error interrupt enable" "0: Interrupt generation on configuration access..,1: Interrupt generation when a configuration access.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "MCE_PRIVCFGR,MCE privileged configuration register"
|
|
bitfld.long 0x0 0. "PRIV,Privileged configuration" "0: Privileged and unprivileged access are granted..,1: Only privileged access are granted to MCE.."
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "MCE_IAESR,MCE illegal access error status register"
|
|
bitfld.long 0x0 7. "IANRW,Illegal access read/write" "0: Illegal access was a data read or an instruction..,1: Illegal access was a data write."
|
|
bitfld.long 0x0 4. "IAPRIV,Illegal access privilege" "0: Illegal access was unprivileged.,1: Illegal access was privileged."
|
|
line.long 0x4 "MCE_IADDR,MCE illegal address register"
|
|
hexmask.long 0x4 0.--31. 1. "IADD,Illegal address"
|
|
group.long 0x40++0x3F
|
|
line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register"
|
|
bitfld.long 0x0 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register"
|
|
hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register"
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0xC "MCE_ATTR1,MCE attribute for region 1 register"
|
|
bitfld.long 0xC 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x10 "MCE_REGCR2,MCE region 2 configuration register"
|
|
bitfld.long 0x10 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x10 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x10 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x10 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x14 "MCE_SADDR2,MCE start address for region 2 register"
|
|
hexmask.long.tbyte 0x14 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x18 "MCE_EADDR2,MCE end address for region 2 register"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x1C "MCE_ATTR2,MCE attribute for region 2 register"
|
|
bitfld.long 0x1C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x20 "MCE_REGCR3,MCE region 3 configuration register"
|
|
bitfld.long 0x20 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x20 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x20 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x20 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x24 "MCE_SADDR3,MCE start address for region 3 register"
|
|
hexmask.long.tbyte 0x24 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x28 "MCE_EADDR3,MCE end address for region 3 register"
|
|
hexmask.long.tbyte 0x28 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x2C "MCE_ATTR3,MCE attribute for region 3 register"
|
|
bitfld.long 0x2C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x30 "MCE_REGCR4,MCE region 4 configuration register"
|
|
bitfld.long 0x30 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x30 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x30 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x30 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x34 "MCE_SADDR4,MCE start address for region 4 register"
|
|
hexmask.long.tbyte 0x34 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x38 "MCE_EADDR4,MCE end address for region 4 register"
|
|
hexmask.long.tbyte 0x38 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x3C "MCE_ATTR4,MCE attribute for region 4 register"
|
|
bitfld.long 0x3C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
wgroup.long 0x200++0xF
|
|
line.long 0x0 "MCE_MKEYR0,MCE master key 0"
|
|
bitfld.long 0x0 31. "MKEY31,Master key bit 31" "0,1"
|
|
bitfld.long 0x0 30. "MKEY30,Master key bit 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MKEY29,Master key bit 29" "0,1"
|
|
bitfld.long 0x0 28. "MKEY28,Master key bit 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MKEY27,Master key bit 27" "0,1"
|
|
bitfld.long 0x0 26. "MKEY26,Master key bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MKEY25,Master key bit 25" "0,1"
|
|
bitfld.long 0x0 24. "MKEY24,Master key bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MKEY23,Master key bit 23" "0,1"
|
|
bitfld.long 0x0 22. "MKEY22,Master key bit 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MKEY21,Master key bit 21" "0,1"
|
|
bitfld.long 0x0 20. "MKEY20,Master key bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MKEY19,Master key bit 19" "0,1"
|
|
bitfld.long 0x0 18. "MKEY18,Master key bit 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MKEY17,Master key bit 17" "0,1"
|
|
bitfld.long 0x0 16. "MKEY16,Master key bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MKEY15,Master key bit 15" "0,1"
|
|
bitfld.long 0x0 14. "MKEY14,Master key bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MKEY13,Master key bit 13" "0,1"
|
|
bitfld.long 0x0 12. "MKEY12,Master key bit 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MKEY11,Master key bit 11" "0,1"
|
|
bitfld.long 0x0 10. "MKEY10,Master key bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MKEY9,Master key bit 9" "0,1"
|
|
bitfld.long 0x0 8. "MKEY8,Master key bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MKEY7,Master key bit 7" "0,1"
|
|
bitfld.long 0x0 6. "MKEY6,Master key bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MKEY5,Master key bit 5" "0,1"
|
|
bitfld.long 0x0 4. "MKEY4,Master key bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MKEY3,Master key bit 3" "0,1"
|
|
bitfld.long 0x0 2. "MKEY2,Master key bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MKEY1,Master key bit 1" "0,1"
|
|
bitfld.long 0x0 0. "MKEY0,Master key bit 0" "0,1"
|
|
line.long 0x4 "MCE_MKEYR1,MCE master key 1"
|
|
bitfld.long 0x4 31. "MKEY63,Master key bit 63" "0,1"
|
|
bitfld.long 0x4 30. "MKEY62,Master key bit 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MKEY61,Master key bit 61" "0,1"
|
|
bitfld.long 0x4 28. "MKEY60,Master key bit 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MKEY59,Master key bit 59" "0,1"
|
|
bitfld.long 0x4 26. "MKEY58,Master key bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MKEY57,Master key bit 57" "0,1"
|
|
bitfld.long 0x4 24. "MKEY56,Master key bit 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MKEY55,Master key bit 55" "0,1"
|
|
bitfld.long 0x4 22. "MKEY54,Master key bit 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MKEY53,Master key bit 53" "0,1"
|
|
bitfld.long 0x4 20. "MKEY52,Master key bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MKEY51,Master key bit 51" "0,1"
|
|
bitfld.long 0x4 18. "MKEY50,Master key bit 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MKEY49,Master key bit 49" "0,1"
|
|
bitfld.long 0x4 16. "MKEY48,Master key bit 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MKEY47,Master key bit 47" "0,1"
|
|
bitfld.long 0x4 14. "MKEY46,Master key bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MKEY45,Master key bit 45" "0,1"
|
|
bitfld.long 0x4 12. "MKEY44,Master key bit 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MKEY43,Master key bit 43" "0,1"
|
|
bitfld.long 0x4 10. "MKEY42,Master key bit 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MKEY41,Master key bit 41" "0,1"
|
|
bitfld.long 0x4 8. "MKEY40,Master key bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MKEY39,Master key bit 39" "0,1"
|
|
bitfld.long 0x4 6. "MKEY38,Master key bit 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MKEY37,Master key bit 37" "0,1"
|
|
bitfld.long 0x4 4. "MKEY36,Master key bit 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MKEY35,Master key bit 35" "0,1"
|
|
bitfld.long 0x4 2. "MKEY34,Master key bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MKEY33,Master key bit 33" "0,1"
|
|
bitfld.long 0x4 0. "MKEY32,Master key bit 32" "0,1"
|
|
line.long 0x8 "MCE_MKEYR2,MCE master key 2"
|
|
bitfld.long 0x8 31. "MKEY95,Master key bit 95" "0,1"
|
|
bitfld.long 0x8 30. "MKEY94,Master key bit 94" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "MKEY93,Master key bit 93" "0,1"
|
|
bitfld.long 0x8 28. "MKEY92,Master key bit 92" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "MKEY91,Master key bit 91" "0,1"
|
|
bitfld.long 0x8 26. "MKEY90,Master key bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "MKEY89,Master key bit 89" "0,1"
|
|
bitfld.long 0x8 24. "MKEY88,Master key bit 88" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "MKEY87,Master key bit 87" "0,1"
|
|
bitfld.long 0x8 22. "MKEY86,Master key bit 86" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "MKEY85,Master key bit 85" "0,1"
|
|
bitfld.long 0x8 20. "MKEY84,Master key bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MKEY83,Master key bit 83" "0,1"
|
|
bitfld.long 0x8 18. "MKEY82,Master key bit 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MKEY81,Master key bit 81" "0,1"
|
|
bitfld.long 0x8 16. "MKEY80,Master key bit 80" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "MKEY79,Master key bit 79" "0,1"
|
|
bitfld.long 0x8 14. "MKEY78,Master key bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "MKEY77,Master key bit 77" "0,1"
|
|
bitfld.long 0x8 12. "MKEY76,Master key bit 76" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "MKEY75,Master key bit 75" "0,1"
|
|
bitfld.long 0x8 10. "MKEY74,Master key bit 74" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "MKEY73,Master key bit 73" "0,1"
|
|
bitfld.long 0x8 8. "MKEY72,Master key bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MKEY71,Master key bit 71" "0,1"
|
|
bitfld.long 0x8 6. "MKEY70,Master key bit 70" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "MKEY69,Master key bit 69" "0,1"
|
|
bitfld.long 0x8 4. "MKEY68,Master key bit 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "MKEY67,Master key bit 67" "0,1"
|
|
bitfld.long 0x8 2. "MKEY66,Master key bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "MKEY65,Master key bit 65" "0,1"
|
|
bitfld.long 0x8 0. "MKEY64,Master key bit 64" "0,1"
|
|
line.long 0xC "MCE_MKEYR3,MCE master key 3"
|
|
bitfld.long 0xC 31. "MKEY127,Master key bit 127" "0,1"
|
|
bitfld.long 0xC 30. "MKEY126,Master key bit 126" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "MKEY125,Master key bit 125" "0,1"
|
|
bitfld.long 0xC 28. "MKEY124,Master key bit 124" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "MKEY123,Master key bit 123" "0,1"
|
|
bitfld.long 0xC 26. "MKEY122,Master key bit 122" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "MKEY121,Master key bit 121" "0,1"
|
|
bitfld.long 0xC 24. "MKEY120,Master key bit 120" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "MKEY119,Master key bit 119" "0,1"
|
|
bitfld.long 0xC 22. "MKEY118,Master key bit 118" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "MKEY117,Master key bit 117" "0,1"
|
|
bitfld.long 0xC 20. "MKEY116,Master key bit 116" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MKEY115,Master key bit 115" "0,1"
|
|
bitfld.long 0xC 18. "MKEY114,Master key bit 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MKEY113,Master key bit 113" "0,1"
|
|
bitfld.long 0xC 16. "MKEY112,Master key bit 112" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "MKEY111,Master key bit 111" "0,1"
|
|
bitfld.long 0xC 14. "MKEY110,Master key bit 110" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "MKEY109,Master key bit 109" "0,1"
|
|
bitfld.long 0xC 12. "MKEY108,Master key bit 108" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "MKEY107,Master key bit 107" "0,1"
|
|
bitfld.long 0xC 10. "MKEY106,Master key bit 106" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "MKEY105,Master key bit 105" "0,1"
|
|
bitfld.long 0xC 8. "MKEY104,Master key bit 104" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "MKEY103,Master key bit 103" "0,1"
|
|
bitfld.long 0xC 6. "MKEY102,Master key bit 102" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MKEY101,Master key bit 101" "0,1"
|
|
bitfld.long 0xC 4. "MKEY100,Master key bit 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "MKEY99,Master key bit 99" "0,1"
|
|
bitfld.long 0xC 2. "MKEY98,Master key bit 98" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "MKEY97,Master key bit 97" "0,1"
|
|
bitfld.long 0xC 0. "MKEY96,Master key bit 96" "0,1"
|
|
wgroup.long 0x220++0xF
|
|
line.long 0x0 "MCE_FMKEYR0,MCE fast master key 0"
|
|
bitfld.long 0x0 31. "FMKEY31,Fast master key bit 31" "0,1"
|
|
bitfld.long 0x0 30. "FMKEY30,Fast master key bit 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FMKEY29,Fast master key bit 29" "0,1"
|
|
bitfld.long 0x0 28. "FMKEY28,Fast master key bit 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "FMKEY27,Fast master key bit 27" "0,1"
|
|
bitfld.long 0x0 26. "FMKEY26,Fast master key bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "FMKEY25,Fast master key bit 25" "0,1"
|
|
bitfld.long 0x0 24. "FMKEY24,Fast master key bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "FMKEY23,Fast master key bit 23" "0,1"
|
|
bitfld.long 0x0 22. "FMKEY22,Fast master key bit 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "FMKEY21,Fast master key bit 21" "0,1"
|
|
bitfld.long 0x0 20. "FMKEY20,Fast master key bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "FMKEY19,Fast master key bit 19" "0,1"
|
|
bitfld.long 0x0 18. "FMKEY18,Fast master key bit 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FMKEY17,Fast master key bit 17" "0,1"
|
|
bitfld.long 0x0 16. "FMKEY16,Fast master key bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "FMKEY15,Fast master key bit 15" "0,1"
|
|
bitfld.long 0x0 14. "FMKEY14,Fast master key bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "FMKEY13,Fast master key bit 13" "0,1"
|
|
bitfld.long 0x0 12. "FMKEY12,Fast master key bit 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "FMKEY11,Fast master key bit 11" "0,1"
|
|
bitfld.long 0x0 10. "FMKEY10,Fast master key bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "FMKEY9,Fast master key bit 9" "0,1"
|
|
bitfld.long 0x0 8. "FMKEY8,Fast master key bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "FMKEY7,Fast master key bit 7" "0,1"
|
|
bitfld.long 0x0 6. "FMKEY6,Fast master key bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FMKEY5,Fast master key bit 5" "0,1"
|
|
bitfld.long 0x0 4. "FMKEY4,Fast master key bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FMKEY3,Fast master key bit 3" "0,1"
|
|
bitfld.long 0x0 2. "FMKEY2,Fast master key bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FMKEY1,Fast master key bit 1" "0,1"
|
|
bitfld.long 0x0 0. "FMKEY0,Fast master key bit 0" "0,1"
|
|
line.long 0x4 "MCE_FMKEYR1,MCE fast master key 1"
|
|
bitfld.long 0x4 31. "FMKEY63,Fast master key bit 63" "0,1"
|
|
bitfld.long 0x4 30. "FMKEY62,Fast master key bit 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "FMKEY61,Fast master key bit 61" "0,1"
|
|
bitfld.long 0x4 28. "FMKEY60,Fast master key bit 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "FMKEY59,Fast master key bit 59" "0,1"
|
|
bitfld.long 0x4 26. "FMKEY58,Fast master key bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "FMKEY57,Fast master key bit 57" "0,1"
|
|
bitfld.long 0x4 24. "FMKEY56,Fast master key bit 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "FMKEY55,Fast master key bit 55" "0,1"
|
|
bitfld.long 0x4 22. "FMKEY54,Fast master key bit 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "FMKEY53,Fast master key bit 53" "0,1"
|
|
bitfld.long 0x4 20. "FMKEY52,Fast master key bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "FMKEY51,Fast master key bit 51" "0,1"
|
|
bitfld.long 0x4 18. "FMKEY50,Fast master key bit 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FMKEY49,Fast master key bit 49" "0,1"
|
|
bitfld.long 0x4 16. "FMKEY48,Fast master key bit 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FMKEY47,Fast master key bit 47" "0,1"
|
|
bitfld.long 0x4 14. "FMKEY46,Fast master key bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FMKEY45,Fast master key bit 45" "0,1"
|
|
bitfld.long 0x4 12. "FMKEY44,Fast master key bit 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "FMKEY43,Fast master key bit 43" "0,1"
|
|
bitfld.long 0x4 10. "FMKEY42,Fast master key bit 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "FMKEY41,Fast master key bit 41" "0,1"
|
|
bitfld.long 0x4 8. "FMKEY40,Fast master key bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "FMKEY39,Fast master key bit 39" "0,1"
|
|
bitfld.long 0x4 6. "FMKEY38,Fast master key bit 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FMKEY37,Fast master key bit 37" "0,1"
|
|
bitfld.long 0x4 4. "FMKEY36,Fast master key bit 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FMKEY35,Fast master key bit 35" "0,1"
|
|
bitfld.long 0x4 2. "FMKEY34,Fast master key bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FMKEY33,Fast master key bit 33" "0,1"
|
|
bitfld.long 0x4 0. "FMKEY32,Fast master key bit 32" "0,1"
|
|
line.long 0x8 "MCE_FMKEYR2,MCE fast master key 2"
|
|
bitfld.long 0x8 31. "FMKEY95,Fast master key bit 95" "0,1"
|
|
bitfld.long 0x8 30. "FMKEY94,Fast master key bit 94" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "FMKEY93,Fast master key bit 93" "0,1"
|
|
bitfld.long 0x8 28. "FMKEY92,Fast master key bit 92" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "FMKEY91,Fast master key bit 91" "0,1"
|
|
bitfld.long 0x8 26. "FMKEY90,Fast master key bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "FMKEY89,Fast master key bit 89" "0,1"
|
|
bitfld.long 0x8 24. "FMKEY88,Fast master key bit 88" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "FMKEY87,Fast master key bit 87" "0,1"
|
|
bitfld.long 0x8 22. "FMKEY86,Fast master key bit 86" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "FMKEY85,Fast master key bit 85" "0,1"
|
|
bitfld.long 0x8 20. "FMKEY84,Fast master key bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "FMKEY83,Fast master key bit 83" "0,1"
|
|
bitfld.long 0x8 18. "FMKEY82,Fast master key bit 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMKEY81,Fast master key bit 81" "0,1"
|
|
bitfld.long 0x8 16. "FMKEY80,Fast master key bit 80" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FMKEY79,Fast master key bit 79" "0,1"
|
|
bitfld.long 0x8 14. "FMKEY78,Fast master key bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FMKEY77,Fast master key bit 77" "0,1"
|
|
bitfld.long 0x8 12. "FMKEY76,Fast master key bit 76" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "FMKEY75,Fast master key bit 75" "0,1"
|
|
bitfld.long 0x8 10. "FMKEY74,Fast master key bit 74" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "FMKEY73,Fast master key bit 73" "0,1"
|
|
bitfld.long 0x8 8. "FMKEY72,Fast master key bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "FMKEY71,Fast master key bit 71" "0,1"
|
|
bitfld.long 0x8 6. "FMKEY70,Fast master key bit 70" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "FMKEY69,Fast master key bit 69" "0,1"
|
|
bitfld.long 0x8 4. "FMKEY68,Fast master key bit 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FMKEY67,Fast master key bit 67" "0,1"
|
|
bitfld.long 0x8 2. "FMKEY66,Fast master key bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "FMKEY65,Fast master key bit 65" "0,1"
|
|
bitfld.long 0x8 0. "FMKEY64,Fast master key bit 64" "0,1"
|
|
line.long 0xC "MCE_FMKEYR3,MCE fast master key 3"
|
|
bitfld.long 0xC 31. "FMKEY127,Fast master key bit 127" "0,1"
|
|
bitfld.long 0xC 30. "FMKEY126,Fast master key bit 126" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "FMKEY125,Fast master key bit 125" "0,1"
|
|
bitfld.long 0xC 28. "FMKEY124,Fast master key bit 124" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "FMKEY123,Fast master key bit 123" "0,1"
|
|
bitfld.long 0xC 26. "FMKEY122,Fast master key bit 122" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "FMKEY121,Fast master key bit 121" "0,1"
|
|
bitfld.long 0xC 24. "FMKEY120,Fast master key bit 120" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "FMKEY119,Fast master key bit 119" "0,1"
|
|
bitfld.long 0xC 22. "FMKEY118,Fast master key bit 118" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "FMKEY117,Fast master key bit 117" "0,1"
|
|
bitfld.long 0xC 20. "FMKEY116,Fast master key bit 116" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "FMKEY115,Fast master key bit 115" "0,1"
|
|
bitfld.long 0xC 18. "FMKEY114,Fast master key bit 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "FMKEY113,Fast master key bit 113" "0,1"
|
|
bitfld.long 0xC 16. "FMKEY112,Fast master key bit 112" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FMKEY111,Fast master key bit 111" "0,1"
|
|
bitfld.long 0xC 14. "FMKEY110,Fast master key bit 110" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FMKEY109,Fast master key bit 109" "0,1"
|
|
bitfld.long 0xC 12. "FMKEY108,Fast master key bit 108" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "FMKEY107,Fast master key bit 107" "0,1"
|
|
bitfld.long 0xC 10. "FMKEY106,Fast master key bit 106" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "FMKEY105,Fast master key bit 105" "0,1"
|
|
bitfld.long 0xC 8. "FMKEY104,Fast master key bit 104" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "FMKEY103,Fast master key bit 103" "0,1"
|
|
bitfld.long 0xC 6. "FMKEY102,Fast master key bit 102" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "FMKEY101,Fast master key bit 101" "0,1"
|
|
bitfld.long 0xC 4. "FMKEY100,Fast master key bit 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FMKEY99,Fast master key bit 99" "0,1"
|
|
bitfld.long 0xC 2. "FMKEY98,Fast master key bit 98" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "FMKEY97,Fast master key bit 97" "0,1"
|
|
bitfld.long 0xC 0. "FMKEY96,Fast master key bit 96" "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VERSION,Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC"
|
|
newline
|
|
bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.."
|
|
bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.."
|
|
line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0"
|
|
hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]"
|
|
line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1"
|
|
hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]"
|
|
wgroup.long 0x24C++0xF
|
|
line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]"
|
|
line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]"
|
|
line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]"
|
|
line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VERSION,Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC"
|
|
newline
|
|
bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.."
|
|
bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.."
|
|
line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0"
|
|
hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]"
|
|
line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1"
|
|
hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]"
|
|
wgroup.long 0x27C++0xF
|
|
line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]"
|
|
line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]"
|
|
line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]"
|
|
line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]"
|
|
tree.end
|
|
tree "MCE3"
|
|
base ad:0x5200C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MCE_CR,MCE configuration register"
|
|
bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx and MCE_FMKEYRx registers..,1: Writes to MCE_MKEYRx and MCE_FMKEYRx registers.."
|
|
bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.."
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "MCE_SR,MCE status register"
|
|
bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCRx all..,1: When ENC bit and BREN are set in any MCE_REGCRx.."
|
|
bitfld.long 0x0 2. "FMKVALID,Fast master key valid" "0: A valid key has not been written in MCE_FMKEYRx..,1: A valid key has been written in MCE_FMKEYRx.."
|
|
newline
|
|
bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.."
|
|
line.long 0x4 "MCE_IASR,MCE illegal access status register"
|
|
bitfld.long 0x4 1. "IAEF,Illegal access error flag" "0,1"
|
|
bitfld.long 0x4 0. "CAEF,Configuration access error flag" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "MCE_IACR,MCE illegal access clear register"
|
|
bitfld.long 0x0 1. "IAEF,Illegal access error flag clear" "0,1"
|
|
bitfld.long 0x0 0. "CAEF,Configuration access error flag clear" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register"
|
|
rbitfld.long 0x0 1. "IAEIE,Illegal access error interrupt enable" "0: Interrupt generation on illegal access errors is..,1: Interrupt generation when an illegal access.."
|
|
bitfld.long 0x0 0. "CAEIE,Configuration access error interrupt enable" "0: Interrupt generation on configuration access..,1: Interrupt generation when a configuration access.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "MCE_PRIVCFGR,MCE privileged configuration register"
|
|
bitfld.long 0x0 0. "PRIV,Privileged configuration" "0: Privileged and unprivileged access are granted..,1: Only privileged access are granted to MCE.."
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "MCE_IAESR,MCE illegal access error status register"
|
|
bitfld.long 0x0 7. "IANRW,Illegal access read/write" "0: Illegal access was a data read or an instruction..,1: Illegal access was a data write."
|
|
bitfld.long 0x0 4. "IAPRIV,Illegal access privilege" "0: Illegal access was unprivileged.,1: Illegal access was privileged."
|
|
line.long 0x4 "MCE_IADDR,MCE illegal address register"
|
|
hexmask.long 0x4 0.--31. 1. "IADD,Illegal address"
|
|
group.long 0x40++0x3F
|
|
line.long 0x0 "MCE_REGCR1,MCE region 1 configuration register"
|
|
bitfld.long 0x0 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x0 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x0 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x4 "MCE_SADDR1,MCE start address for region 1 register"
|
|
hexmask.long.tbyte 0x4 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x8 "MCE_EADDR1,MCE end address for region 1 register"
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0xC "MCE_ATTR1,MCE attribute for region 1 register"
|
|
bitfld.long 0xC 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x10 "MCE_REGCR2,MCE region 2 configuration register"
|
|
bitfld.long 0x10 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x10 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x10 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x10 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x14 "MCE_SADDR2,MCE start address for region 2 register"
|
|
hexmask.long.tbyte 0x14 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x18 "MCE_EADDR2,MCE end address for region 2 register"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x1C "MCE_ATTR2,MCE attribute for region 2 register"
|
|
bitfld.long 0x1C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x20 "MCE_REGCR3,MCE region 3 configuration register"
|
|
bitfld.long 0x20 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x20 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x20 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x20 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x24 "MCE_SADDR3,MCE start address for region 3 register"
|
|
hexmask.long.tbyte 0x24 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x28 "MCE_EADDR3,MCE end address for region 3 register"
|
|
hexmask.long.tbyte 0x28 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x2C "MCE_ATTR3,MCE attribute for region 3 register"
|
|
bitfld.long 0x2C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
line.long 0x30 "MCE_REGCR4,MCE region 4 configuration register"
|
|
bitfld.long 0x30 16. "PRIV,Privileged region" "0: Application can access to region x in privileged..,1: Application can access to region x in privileged.."
|
|
bitfld.long 0x30 14.--15. "ENC,Encrypted region" "0: No effects,1: Stream cipher - All allowed read (resp. write)..,2: Block cipher - All allowed read (resp. write)..,3: MCE implementation"
|
|
newline
|
|
bitfld.long 0x30 9.--10. "CTXID,Context ID" "0: If ENC=10 (resp. 11) the key stored in MCE_MKEYR..,1: If ENC=10 or 11 the key stored in MCE_CC1KEYR is..,2: If ENC=10 or 11 the key stored in MCE_CC2KEYR is..,3: FIELD Reserved"
|
|
bitfld.long 0x30 0. "BREN,Base region enable" "0: Region x is disabled. Access control of primary..,1: Region x is enable. Access controls and.."
|
|
line.long 0x34 "MCE_SADDR4,MCE start address for region 4 register"
|
|
hexmask.long.tbyte 0x34 12.--31. 1. "BADDSTART,Region address start"
|
|
line.long 0x38 "MCE_EADDR4,MCE end address for region 4 register"
|
|
hexmask.long.tbyte 0x38 12.--31. 1. "BADDEND,Region address end"
|
|
line.long 0x3C "MCE_ATTR4,MCE attribute for region 4 register"
|
|
bitfld.long 0x3C 16. "WREN,Write enable" "0: Writes to region x are ignored. Reads are allowed.,1: Region x can be read and written. Restrictions.."
|
|
wgroup.long 0x200++0xF
|
|
line.long 0x0 "MCE_MKEYR0,MCE master key 0"
|
|
bitfld.long 0x0 31. "MKEY31,Master key bit 31" "0,1"
|
|
bitfld.long 0x0 30. "MKEY30,Master key bit 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MKEY29,Master key bit 29" "0,1"
|
|
bitfld.long 0x0 28. "MKEY28,Master key bit 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MKEY27,Master key bit 27" "0,1"
|
|
bitfld.long 0x0 26. "MKEY26,Master key bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MKEY25,Master key bit 25" "0,1"
|
|
bitfld.long 0x0 24. "MKEY24,Master key bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MKEY23,Master key bit 23" "0,1"
|
|
bitfld.long 0x0 22. "MKEY22,Master key bit 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MKEY21,Master key bit 21" "0,1"
|
|
bitfld.long 0x0 20. "MKEY20,Master key bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MKEY19,Master key bit 19" "0,1"
|
|
bitfld.long 0x0 18. "MKEY18,Master key bit 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MKEY17,Master key bit 17" "0,1"
|
|
bitfld.long 0x0 16. "MKEY16,Master key bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MKEY15,Master key bit 15" "0,1"
|
|
bitfld.long 0x0 14. "MKEY14,Master key bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MKEY13,Master key bit 13" "0,1"
|
|
bitfld.long 0x0 12. "MKEY12,Master key bit 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MKEY11,Master key bit 11" "0,1"
|
|
bitfld.long 0x0 10. "MKEY10,Master key bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MKEY9,Master key bit 9" "0,1"
|
|
bitfld.long 0x0 8. "MKEY8,Master key bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MKEY7,Master key bit 7" "0,1"
|
|
bitfld.long 0x0 6. "MKEY6,Master key bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MKEY5,Master key bit 5" "0,1"
|
|
bitfld.long 0x0 4. "MKEY4,Master key bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MKEY3,Master key bit 3" "0,1"
|
|
bitfld.long 0x0 2. "MKEY2,Master key bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MKEY1,Master key bit 1" "0,1"
|
|
bitfld.long 0x0 0. "MKEY0,Master key bit 0" "0,1"
|
|
line.long 0x4 "MCE_MKEYR1,MCE master key 1"
|
|
bitfld.long 0x4 31. "MKEY63,Master key bit 63" "0,1"
|
|
bitfld.long 0x4 30. "MKEY62,Master key bit 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MKEY61,Master key bit 61" "0,1"
|
|
bitfld.long 0x4 28. "MKEY60,Master key bit 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MKEY59,Master key bit 59" "0,1"
|
|
bitfld.long 0x4 26. "MKEY58,Master key bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MKEY57,Master key bit 57" "0,1"
|
|
bitfld.long 0x4 24. "MKEY56,Master key bit 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MKEY55,Master key bit 55" "0,1"
|
|
bitfld.long 0x4 22. "MKEY54,Master key bit 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MKEY53,Master key bit 53" "0,1"
|
|
bitfld.long 0x4 20. "MKEY52,Master key bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MKEY51,Master key bit 51" "0,1"
|
|
bitfld.long 0x4 18. "MKEY50,Master key bit 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MKEY49,Master key bit 49" "0,1"
|
|
bitfld.long 0x4 16. "MKEY48,Master key bit 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MKEY47,Master key bit 47" "0,1"
|
|
bitfld.long 0x4 14. "MKEY46,Master key bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MKEY45,Master key bit 45" "0,1"
|
|
bitfld.long 0x4 12. "MKEY44,Master key bit 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MKEY43,Master key bit 43" "0,1"
|
|
bitfld.long 0x4 10. "MKEY42,Master key bit 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MKEY41,Master key bit 41" "0,1"
|
|
bitfld.long 0x4 8. "MKEY40,Master key bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MKEY39,Master key bit 39" "0,1"
|
|
bitfld.long 0x4 6. "MKEY38,Master key bit 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MKEY37,Master key bit 37" "0,1"
|
|
bitfld.long 0x4 4. "MKEY36,Master key bit 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MKEY35,Master key bit 35" "0,1"
|
|
bitfld.long 0x4 2. "MKEY34,Master key bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MKEY33,Master key bit 33" "0,1"
|
|
bitfld.long 0x4 0. "MKEY32,Master key bit 32" "0,1"
|
|
line.long 0x8 "MCE_MKEYR2,MCE master key 2"
|
|
bitfld.long 0x8 31. "MKEY95,Master key bit 95" "0,1"
|
|
bitfld.long 0x8 30. "MKEY94,Master key bit 94" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "MKEY93,Master key bit 93" "0,1"
|
|
bitfld.long 0x8 28. "MKEY92,Master key bit 92" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "MKEY91,Master key bit 91" "0,1"
|
|
bitfld.long 0x8 26. "MKEY90,Master key bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "MKEY89,Master key bit 89" "0,1"
|
|
bitfld.long 0x8 24. "MKEY88,Master key bit 88" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "MKEY87,Master key bit 87" "0,1"
|
|
bitfld.long 0x8 22. "MKEY86,Master key bit 86" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "MKEY85,Master key bit 85" "0,1"
|
|
bitfld.long 0x8 20. "MKEY84,Master key bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MKEY83,Master key bit 83" "0,1"
|
|
bitfld.long 0x8 18. "MKEY82,Master key bit 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MKEY81,Master key bit 81" "0,1"
|
|
bitfld.long 0x8 16. "MKEY80,Master key bit 80" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "MKEY79,Master key bit 79" "0,1"
|
|
bitfld.long 0x8 14. "MKEY78,Master key bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "MKEY77,Master key bit 77" "0,1"
|
|
bitfld.long 0x8 12. "MKEY76,Master key bit 76" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "MKEY75,Master key bit 75" "0,1"
|
|
bitfld.long 0x8 10. "MKEY74,Master key bit 74" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "MKEY73,Master key bit 73" "0,1"
|
|
bitfld.long 0x8 8. "MKEY72,Master key bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MKEY71,Master key bit 71" "0,1"
|
|
bitfld.long 0x8 6. "MKEY70,Master key bit 70" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "MKEY69,Master key bit 69" "0,1"
|
|
bitfld.long 0x8 4. "MKEY68,Master key bit 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "MKEY67,Master key bit 67" "0,1"
|
|
bitfld.long 0x8 2. "MKEY66,Master key bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "MKEY65,Master key bit 65" "0,1"
|
|
bitfld.long 0x8 0. "MKEY64,Master key bit 64" "0,1"
|
|
line.long 0xC "MCE_MKEYR3,MCE master key 3"
|
|
bitfld.long 0xC 31. "MKEY127,Master key bit 127" "0,1"
|
|
bitfld.long 0xC 30. "MKEY126,Master key bit 126" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "MKEY125,Master key bit 125" "0,1"
|
|
bitfld.long 0xC 28. "MKEY124,Master key bit 124" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "MKEY123,Master key bit 123" "0,1"
|
|
bitfld.long 0xC 26. "MKEY122,Master key bit 122" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "MKEY121,Master key bit 121" "0,1"
|
|
bitfld.long 0xC 24. "MKEY120,Master key bit 120" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "MKEY119,Master key bit 119" "0,1"
|
|
bitfld.long 0xC 22. "MKEY118,Master key bit 118" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "MKEY117,Master key bit 117" "0,1"
|
|
bitfld.long 0xC 20. "MKEY116,Master key bit 116" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MKEY115,Master key bit 115" "0,1"
|
|
bitfld.long 0xC 18. "MKEY114,Master key bit 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MKEY113,Master key bit 113" "0,1"
|
|
bitfld.long 0xC 16. "MKEY112,Master key bit 112" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "MKEY111,Master key bit 111" "0,1"
|
|
bitfld.long 0xC 14. "MKEY110,Master key bit 110" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "MKEY109,Master key bit 109" "0,1"
|
|
bitfld.long 0xC 12. "MKEY108,Master key bit 108" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "MKEY107,Master key bit 107" "0,1"
|
|
bitfld.long 0xC 10. "MKEY106,Master key bit 106" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "MKEY105,Master key bit 105" "0,1"
|
|
bitfld.long 0xC 8. "MKEY104,Master key bit 104" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "MKEY103,Master key bit 103" "0,1"
|
|
bitfld.long 0xC 6. "MKEY102,Master key bit 102" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MKEY101,Master key bit 101" "0,1"
|
|
bitfld.long 0xC 4. "MKEY100,Master key bit 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "MKEY99,Master key bit 99" "0,1"
|
|
bitfld.long 0xC 2. "MKEY98,Master key bit 98" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "MKEY97,Master key bit 97" "0,1"
|
|
bitfld.long 0xC 0. "MKEY96,Master key bit 96" "0,1"
|
|
wgroup.long 0x220++0xF
|
|
line.long 0x0 "MCE_FMKEYR0,MCE fast master key 0"
|
|
bitfld.long 0x0 31. "FMKEY31,Fast master key bit 31" "0,1"
|
|
bitfld.long 0x0 30. "FMKEY30,Fast master key bit 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FMKEY29,Fast master key bit 29" "0,1"
|
|
bitfld.long 0x0 28. "FMKEY28,Fast master key bit 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "FMKEY27,Fast master key bit 27" "0,1"
|
|
bitfld.long 0x0 26. "FMKEY26,Fast master key bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "FMKEY25,Fast master key bit 25" "0,1"
|
|
bitfld.long 0x0 24. "FMKEY24,Fast master key bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "FMKEY23,Fast master key bit 23" "0,1"
|
|
bitfld.long 0x0 22. "FMKEY22,Fast master key bit 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "FMKEY21,Fast master key bit 21" "0,1"
|
|
bitfld.long 0x0 20. "FMKEY20,Fast master key bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "FMKEY19,Fast master key bit 19" "0,1"
|
|
bitfld.long 0x0 18. "FMKEY18,Fast master key bit 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FMKEY17,Fast master key bit 17" "0,1"
|
|
bitfld.long 0x0 16. "FMKEY16,Fast master key bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "FMKEY15,Fast master key bit 15" "0,1"
|
|
bitfld.long 0x0 14. "FMKEY14,Fast master key bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "FMKEY13,Fast master key bit 13" "0,1"
|
|
bitfld.long 0x0 12. "FMKEY12,Fast master key bit 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "FMKEY11,Fast master key bit 11" "0,1"
|
|
bitfld.long 0x0 10. "FMKEY10,Fast master key bit 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "FMKEY9,Fast master key bit 9" "0,1"
|
|
bitfld.long 0x0 8. "FMKEY8,Fast master key bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "FMKEY7,Fast master key bit 7" "0,1"
|
|
bitfld.long 0x0 6. "FMKEY6,Fast master key bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FMKEY5,Fast master key bit 5" "0,1"
|
|
bitfld.long 0x0 4. "FMKEY4,Fast master key bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FMKEY3,Fast master key bit 3" "0,1"
|
|
bitfld.long 0x0 2. "FMKEY2,Fast master key bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FMKEY1,Fast master key bit 1" "0,1"
|
|
bitfld.long 0x0 0. "FMKEY0,Fast master key bit 0" "0,1"
|
|
line.long 0x4 "MCE_FMKEYR1,MCE fast master key 1"
|
|
bitfld.long 0x4 31. "FMKEY63,Fast master key bit 63" "0,1"
|
|
bitfld.long 0x4 30. "FMKEY62,Fast master key bit 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "FMKEY61,Fast master key bit 61" "0,1"
|
|
bitfld.long 0x4 28. "FMKEY60,Fast master key bit 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "FMKEY59,Fast master key bit 59" "0,1"
|
|
bitfld.long 0x4 26. "FMKEY58,Fast master key bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "FMKEY57,Fast master key bit 57" "0,1"
|
|
bitfld.long 0x4 24. "FMKEY56,Fast master key bit 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "FMKEY55,Fast master key bit 55" "0,1"
|
|
bitfld.long 0x4 22. "FMKEY54,Fast master key bit 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "FMKEY53,Fast master key bit 53" "0,1"
|
|
bitfld.long 0x4 20. "FMKEY52,Fast master key bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "FMKEY51,Fast master key bit 51" "0,1"
|
|
bitfld.long 0x4 18. "FMKEY50,Fast master key bit 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FMKEY49,Fast master key bit 49" "0,1"
|
|
bitfld.long 0x4 16. "FMKEY48,Fast master key bit 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FMKEY47,Fast master key bit 47" "0,1"
|
|
bitfld.long 0x4 14. "FMKEY46,Fast master key bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FMKEY45,Fast master key bit 45" "0,1"
|
|
bitfld.long 0x4 12. "FMKEY44,Fast master key bit 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "FMKEY43,Fast master key bit 43" "0,1"
|
|
bitfld.long 0x4 10. "FMKEY42,Fast master key bit 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "FMKEY41,Fast master key bit 41" "0,1"
|
|
bitfld.long 0x4 8. "FMKEY40,Fast master key bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "FMKEY39,Fast master key bit 39" "0,1"
|
|
bitfld.long 0x4 6. "FMKEY38,Fast master key bit 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FMKEY37,Fast master key bit 37" "0,1"
|
|
bitfld.long 0x4 4. "FMKEY36,Fast master key bit 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FMKEY35,Fast master key bit 35" "0,1"
|
|
bitfld.long 0x4 2. "FMKEY34,Fast master key bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FMKEY33,Fast master key bit 33" "0,1"
|
|
bitfld.long 0x4 0. "FMKEY32,Fast master key bit 32" "0,1"
|
|
line.long 0x8 "MCE_FMKEYR2,MCE fast master key 2"
|
|
bitfld.long 0x8 31. "FMKEY95,Fast master key bit 95" "0,1"
|
|
bitfld.long 0x8 30. "FMKEY94,Fast master key bit 94" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "FMKEY93,Fast master key bit 93" "0,1"
|
|
bitfld.long 0x8 28. "FMKEY92,Fast master key bit 92" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "FMKEY91,Fast master key bit 91" "0,1"
|
|
bitfld.long 0x8 26. "FMKEY90,Fast master key bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "FMKEY89,Fast master key bit 89" "0,1"
|
|
bitfld.long 0x8 24. "FMKEY88,Fast master key bit 88" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "FMKEY87,Fast master key bit 87" "0,1"
|
|
bitfld.long 0x8 22. "FMKEY86,Fast master key bit 86" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "FMKEY85,Fast master key bit 85" "0,1"
|
|
bitfld.long 0x8 20. "FMKEY84,Fast master key bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "FMKEY83,Fast master key bit 83" "0,1"
|
|
bitfld.long 0x8 18. "FMKEY82,Fast master key bit 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMKEY81,Fast master key bit 81" "0,1"
|
|
bitfld.long 0x8 16. "FMKEY80,Fast master key bit 80" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FMKEY79,Fast master key bit 79" "0,1"
|
|
bitfld.long 0x8 14. "FMKEY78,Fast master key bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FMKEY77,Fast master key bit 77" "0,1"
|
|
bitfld.long 0x8 12. "FMKEY76,Fast master key bit 76" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "FMKEY75,Fast master key bit 75" "0,1"
|
|
bitfld.long 0x8 10. "FMKEY74,Fast master key bit 74" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "FMKEY73,Fast master key bit 73" "0,1"
|
|
bitfld.long 0x8 8. "FMKEY72,Fast master key bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "FMKEY71,Fast master key bit 71" "0,1"
|
|
bitfld.long 0x8 6. "FMKEY70,Fast master key bit 70" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "FMKEY69,Fast master key bit 69" "0,1"
|
|
bitfld.long 0x8 4. "FMKEY68,Fast master key bit 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FMKEY67,Fast master key bit 67" "0,1"
|
|
bitfld.long 0x8 2. "FMKEY66,Fast master key bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "FMKEY65,Fast master key bit 65" "0,1"
|
|
bitfld.long 0x8 0. "FMKEY64,Fast master key bit 64" "0,1"
|
|
line.long 0xC "MCE_FMKEYR3,MCE fast master key 3"
|
|
bitfld.long 0xC 31. "FMKEY127,Fast master key bit 127" "0,1"
|
|
bitfld.long 0xC 30. "FMKEY126,Fast master key bit 126" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "FMKEY125,Fast master key bit 125" "0,1"
|
|
bitfld.long 0xC 28. "FMKEY124,Fast master key bit 124" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "FMKEY123,Fast master key bit 123" "0,1"
|
|
bitfld.long 0xC 26. "FMKEY122,Fast master key bit 122" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "FMKEY121,Fast master key bit 121" "0,1"
|
|
bitfld.long 0xC 24. "FMKEY120,Fast master key bit 120" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "FMKEY119,Fast master key bit 119" "0,1"
|
|
bitfld.long 0xC 22. "FMKEY118,Fast master key bit 118" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "FMKEY117,Fast master key bit 117" "0,1"
|
|
bitfld.long 0xC 20. "FMKEY116,Fast master key bit 116" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "FMKEY115,Fast master key bit 115" "0,1"
|
|
bitfld.long 0xC 18. "FMKEY114,Fast master key bit 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "FMKEY113,Fast master key bit 113" "0,1"
|
|
bitfld.long 0xC 16. "FMKEY112,Fast master key bit 112" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FMKEY111,Fast master key bit 111" "0,1"
|
|
bitfld.long 0xC 14. "FMKEY110,Fast master key bit 110" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FMKEY109,Fast master key bit 109" "0,1"
|
|
bitfld.long 0xC 12. "FMKEY108,Fast master key bit 108" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "FMKEY107,Fast master key bit 107" "0,1"
|
|
bitfld.long 0xC 10. "FMKEY106,Fast master key bit 106" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "FMKEY105,Fast master key bit 105" "0,1"
|
|
bitfld.long 0xC 8. "FMKEY104,Fast master key bit 104" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "FMKEY103,Fast master key bit 103" "0,1"
|
|
bitfld.long 0xC 6. "FMKEY102,Fast master key bit 102" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "FMKEY101,Fast master key bit 101" "0,1"
|
|
bitfld.long 0xC 4. "FMKEY100,Fast master key bit 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FMKEY99,Fast master key bit 99" "0,1"
|
|
bitfld.long 0xC 2. "FMKEY98,Fast master key bit 98" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "FMKEY97,Fast master key bit 97" "0,1"
|
|
bitfld.long 0xC 0. "FMKEY96,Fast master key bit 96" "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "MCE_CC1CFGR,MCE cipher context 1 configuration register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VERSION,Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC"
|
|
newline
|
|
bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.."
|
|
bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.."
|
|
line.long 0x4 "MCE_CC1NR0,MCE cipher context 1 nonce register 0"
|
|
hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]"
|
|
line.long 0x8 "MCE_CC1NR1,MCE cipher context 1 nonce register 1"
|
|
hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]"
|
|
wgroup.long 0x24C++0xF
|
|
line.long 0x0 "MCE_CC1KEYR0,MCE cipher context 1 key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]"
|
|
line.long 0x4 "MCE_CC1KEYR1,MCE cipher context 1 key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]"
|
|
line.long 0x8 "MCE_CC1KEYR2,MCE cipher context 1 key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]"
|
|
line.long 0xC "MCE_CC1KEYR3,MCE cipher context 1 key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "MCE_CC2CFGR,MCE cipher context 2 configuration register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VERSION,Version"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,Key CRC"
|
|
newline
|
|
bitfld.long 0x0 2. "KEYLOCK,Key lock" "0: Writes to MCE_CCzKEYR registers are allowed,1: Writes to MCE_CCzKEYR registers are ignored.."
|
|
bitfld.long 0x0 1. "CCLOCK,Cipher context lock" "0: Writes to MCE_CCzCFGR and MCE_CCzNR registers..,1: Writes to MCE_CCzCFGR and MCE_CCzNR registers.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCEN,Cipher context enable" "0: If an enabled region selects CTXID=z bypass mode..,1: If an enabled region selects CTXID=z with ENC=01.."
|
|
line.long 0x4 "MCE_CC2NR0,MCE cipher context 2 nonce register 0"
|
|
hexmask.long 0x4 0.--31. 1. "SCNONCE,Stream cipher nonce bits [31:0]"
|
|
line.long 0x8 "MCE_CC2NR1,MCE cipher context 2 nonce register 1"
|
|
hexmask.long 0x8 0.--31. 1. "SCNONCE,Stream cipher nonce bits [63:32]"
|
|
wgroup.long 0x27C++0xF
|
|
line.long 0x0 "MCE_CC2KEYR0,MCE cipher context 2 key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,cipher key bits [31:0]"
|
|
line.long 0x4 "MCE_CC2KEYR1,MCE cipher context 2 key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,cipher key bits [63:32]"
|
|
line.long 0x8 "MCE_CC2KEYR2,MCE cipher context 2 key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,cipher key bits [95:64]"
|
|
line.long 0xC "MCE_CC2KEYR3,MCE cipher context 2 key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,cipher key bits [127:96]"
|
|
tree.end
|
|
tree.end
|
|
tree "MDIOS (Management Data Input/Output Slave)"
|
|
base ad:0x40009400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MDIOS_CR,MDIOS configuration register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,slave address"
|
|
bitfld.long 0x0 7. "DPC,disable preamble check" "0: MDIO master must give preamble before each frame.,1: MDIO master can send each frame without a.."
|
|
newline
|
|
bitfld.long 0x0 3. "EIE,error interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x0 2. "RDIE,register read interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "WRIE,register write interrupt enable" "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x0 0. "EN,peripheral enable" "0: MDIOS is disabled.,1: MDIOS is enabled and monitoring the MDIO bus.."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "MDIOS_WRFR,MDIOS write flag register"
|
|
hexmask.long 0x0 0.--31. 1. "WRF,write flags for MDIOS registers 0 to 31."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag register"
|
|
hexmask.long 0x0 0.--31. 1. "CWRF,clear the write flag"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "MDIOS_RDFR,MDIOS read flag register"
|
|
hexmask.long 0x0 0.--31. 1. "RDF,read flags for MDIOS registers 0 to 31."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register"
|
|
hexmask.long 0x0 0.--31. 1. "CRDF,clear the read flag"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "MDIOS_SR,MDIOS status register"
|
|
bitfld.long 0x0 2. "TERF,turnaround error flag" "0: No turnaround error has occurred.,1: A turnaround error has occurred."
|
|
bitfld.long 0x0 1. "SERF,start error flag" "0: No start error has occurred.,1: A start error has occurred."
|
|
newline
|
|
bitfld.long 0x0 0. "PERF,preamble error flag" "0: No preamble error has occurred.,1: A preamble error has occurred."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register"
|
|
bitfld.long 0x0 2. "CTERF,clear the turnaround error flag" "0,1"
|
|
bitfld.long 0x0 1. "CSERF,clear the start error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPERF,clear the preamble error flag" "0,1"
|
|
rgroup.long 0x100++0x7F
|
|
line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0xC "MDIOS_DINR3,MDIOS input data register 3"
|
|
hexmask.long.word 0xC 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4"
|
|
hexmask.long.word 0x10 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5"
|
|
hexmask.long.word 0x14 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6"
|
|
hexmask.long.word 0x18 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8"
|
|
hexmask.long.word 0x20 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9"
|
|
hexmask.long.word 0x24 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10"
|
|
hexmask.long.word 0x28 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11"
|
|
hexmask.long.word 0x2C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12"
|
|
hexmask.long.word 0x30 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13"
|
|
hexmask.long.word 0x34 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14"
|
|
hexmask.long.word 0x38 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15"
|
|
hexmask.long.word 0x3C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16"
|
|
hexmask.long.word 0x40 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17"
|
|
hexmask.long.word 0x44 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18"
|
|
hexmask.long.word 0x48 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19"
|
|
hexmask.long.word 0x4C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20"
|
|
hexmask.long.word 0x50 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21"
|
|
hexmask.long.word 0x54 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22"
|
|
hexmask.long.word 0x58 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23"
|
|
hexmask.long.word 0x5C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24"
|
|
hexmask.long.word 0x60 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25"
|
|
hexmask.long.word 0x64 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26"
|
|
hexmask.long.word 0x68 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27"
|
|
hexmask.long.word 0x6C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28"
|
|
hexmask.long.word 0x70 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29"
|
|
hexmask.long.word 0x74 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30"
|
|
hexmask.long.word 0x78 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31"
|
|
hexmask.long.word 0x7C 0.--15. 1. "DIN,input data received from MDIO master during write frames"
|
|
group.long 0x180++0x7F
|
|
line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3"
|
|
hexmask.long.word 0xC 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4"
|
|
hexmask.long.word 0x10 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5"
|
|
hexmask.long.word 0x14 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6"
|
|
hexmask.long.word 0x18 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8"
|
|
hexmask.long.word 0x20 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9"
|
|
hexmask.long.word 0x24 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10"
|
|
hexmask.long.word 0x28 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11"
|
|
hexmask.long.word 0x2C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12"
|
|
hexmask.long.word 0x30 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13"
|
|
hexmask.long.word 0x34 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14"
|
|
hexmask.long.word 0x38 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15"
|
|
hexmask.long.word 0x3C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16"
|
|
hexmask.long.word 0x40 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17"
|
|
hexmask.long.word 0x44 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18"
|
|
hexmask.long.word 0x48 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19"
|
|
hexmask.long.word 0x4C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20"
|
|
hexmask.long.word 0x50 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21"
|
|
hexmask.long.word 0x54 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22"
|
|
hexmask.long.word 0x58 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23"
|
|
hexmask.long.word 0x5C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24"
|
|
hexmask.long.word 0x60 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25"
|
|
hexmask.long.word 0x64 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26"
|
|
hexmask.long.word 0x68 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27"
|
|
hexmask.long.word 0x6C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28"
|
|
hexmask.long.word 0x70 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29"
|
|
hexmask.long.word 0x74 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30"
|
|
hexmask.long.word 0x78 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31"
|
|
hexmask.long.word 0x7C 0.--15. 1. "DOUT,output data sent to MDIO Master during read frames"
|
|
tree.end
|
|
tree "OTG (On-the-Go)"
|
|
base ad:0x0
|
|
tree "OTG_FS"
|
|
base ad:0x40080000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "OTG_GOTGCTL,OTG control and status register"
|
|
rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode"
|
|
bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.."
|
|
newline
|
|
rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid."
|
|
rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid"
|
|
newline
|
|
rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.."
|
|
rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG_HS controller is in A-device mode,1: The OTG_HS controller is in B-device mode"
|
|
newline
|
|
bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected"
|
|
bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1"
|
|
newline
|
|
bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,?"
|
|
bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1"
|
|
newline
|
|
bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.."
|
|
bitfld.long 0x0 3. "VBVALOVAL,V<sub>BUS</sub> valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1"
|
|
newline
|
|
bitfld.long 0x0 2. "VBVALOEN,V<sub>BUS</sub> valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.."
|
|
line.long 0x4 "OTG_GOTGINT,OTG interrupt register"
|
|
bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1"
|
|
bitfld.long 0x4 2. "SEDET,Session end detected" "0,1"
|
|
line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register"
|
|
bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.."
|
|
bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The TXFE (in OTG_DIEPINTx) interrupt indicates..,1: The TXFE (in OTG_DIEPINTx) interrupt indicates.."
|
|
newline
|
|
bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode"
|
|
hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type"
|
|
newline
|
|
bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application."
|
|
line.long 0xC "OTG_GUSBCFG,OTG USB configuration register"
|
|
bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode"
|
|
bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode"
|
|
newline
|
|
bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel"
|
|
bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock"
|
|
newline
|
|
hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time"
|
|
bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "OTG_GRSTCTL,OTG reset register"
|
|
rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1"
|
|
rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1"
|
|
bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1"
|
|
bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1"
|
|
line.long 0x14 "OTG_GINTSTS_HOST,OTG core interrupt register"
|
|
bitfld.long 0x14 31. "WKUPINT,Resume/remote wakeup detected interrupt" "0,1"
|
|
bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1"
|
|
bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1"
|
|
rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1"
|
|
rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1"
|
|
bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1"
|
|
bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1"
|
|
rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1"
|
|
bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1"
|
|
bitfld.long 0x14 12. "USBRST,USB reset" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1"
|
|
bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1"
|
|
rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1"
|
|
rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "SOF,Start of frame" "0,1"
|
|
rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1"
|
|
rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "OTG_GINTSTS_DEVICE,OTG core interrupt register"
|
|
bitfld.long 0x0 31. "WKUPINT,Resume/remote wakeup detected interrupt" "0,1"
|
|
bitfld.long 0x0 30. "SRQINT,Session request/new session detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DISCINT,Disconnect detected interrupt" "0,1"
|
|
bitfld.long 0x0 28. "CIDSCHG,Connector ID status change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LPMINT,LPM interrupt" "0,1"
|
|
rbitfld.long 0x0 26. "PTXFE,Periodic Tx FIFO empty" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 25. "HCINT,Host channels interrupt" "0,1"
|
|
rbitfld.long 0x0 24. "HPRTINT,Host port interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RSTDET,Reset detected interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DATAFSUSP,Data fetch suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "INCOMPISOOUT,Incomplete isochronous OUT transfer" "0,1"
|
|
bitfld.long 0x0 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 19. "OEPINT,OUT endpoint interrupt" "0,1"
|
|
rbitfld.long 0x0 18. "IEPINT,IN endpoint interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EOPF,End of periodic frame interrupt" "0,1"
|
|
bitfld.long 0x0 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENUMDNE,Enumeration done" "0,1"
|
|
bitfld.long 0x0 12. "USBRST,USB reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USBSUSP,USB suspend" "0,1"
|
|
bitfld.long 0x0 10. "ESUSP,Early suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 7. "GONAKEFF,Global OUT NAK effective" "0,1"
|
|
rbitfld.long 0x0 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1"
|
|
rbitfld.long 0x0 4. "RXFLVL,Rx FIFO non-empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SOF,Start of frame" "0,1"
|
|
rbitfld.long 0x0 2. "OTGINT,OTG interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MMIS,Mode mismatch interrupt" "0,1"
|
|
rbitfld.long 0x0 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode"
|
|
line.long 0x4 "OTG_GINTMSK_HOST,OTG interrupt mask register"
|
|
bitfld.long 0x4 31. "WUIM,Resume/remote wakeup detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
rbitfld.long 0x4 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OTG_GINTMSK_DEVICE,OTG interrupt mask register"
|
|
bitfld.long 0x0 31. "WUIM,Resume/remote wakeup detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 21. "IISOOXFRM,Incomplete isochronous OUT transfer mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "OTG_GRXSTSR_DEVICE,OTG receive status debug read register"
|
|
bitfld.long 0x0 27. "STSPHST,Status phase start" "0,1"
|
|
hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "OTG_GRXSTSR_HOST,OTG receive status debug read register"
|
|
hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number"
|
|
line.long 0x4 "OTG_GRXSTSP_DEVICE,OTG status read and pop registers"
|
|
bitfld.long 0x4 27. "STSPHST,Status phase start" "0,1"
|
|
hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number"
|
|
newline
|
|
hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x4 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "OTG_GRXSTSP_HOST,OTG status read and pop registers"
|
|
hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "OTG_GRXFSIZ,OTG receive FIFO size register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth"
|
|
line.long 0x4 "OTG_HNPTXFSIZ_HOST,OTG host non-periodic transmit FIFO size register [alternate]"
|
|
hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "OTG_HNPTXFSIZ_DEVICE,OTG host non-periodic transmit FIFO size register [alternate]"
|
|
hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 Tx FIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start address"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register"
|
|
hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "OTG_GCCFG,OTG general core configuration register"
|
|
bitfld.long 0x0 25. "FORCEHOSTPD,Force host mode pull-downs" "0: Do not force host mode pull-downs,1: Force host mode pull-downs"
|
|
bitfld.long 0x0 24. "VBVALOVEN,Enables a software override of the VBUS B-session detection." "0: Use hardware,1: Use VBVALOVAL to indicate B-session active"
|
|
newline
|
|
bitfld.long 0x0 23. "VBVALOVAL,Software override value of the VBUS B-session detection" "0: B-session inactive,1: B-session active"
|
|
bitfld.long 0x0 22. "SDEN,Secondary detection enable" "0: Secondary detection disabled,1: Secondary detection enabled"
|
|
newline
|
|
bitfld.long 0x0 21. "VBDEN,VBUS detection enable" "0: VBUS detection disabled,1: VBUS detection enabled"
|
|
bitfld.long 0x0 20. "PDEN,Primary detection enable" "0: Primary detection disabled,1: Primary detection enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "DCDEN,Data Contact Detection enable" "0: Data Contact Detection disabled,1: Data Contact Detection enabled"
|
|
bitfld.long 0x0 18. "HVDMSRCEN,Host CDP port Voltage source enable on DM" "0: DM voltage source disabled,1: DM Voltage source enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "HCDPDETEN,Host CDP port voltage detector enable on DP" "0: DP voltage detection disabled,1: DP voltage detection enabled"
|
|
bitfld.long 0x0 16. "HCDPEN,Host CDP behavior enable" "0: Disable CDP behavior,1: Enable CDP behavior"
|
|
newline
|
|
rbitfld.long 0x0 3. "SESSVLD,VBUS session indicator" "0: VBUS is below VBUS session threshold,1: VBUS is above VBUS session threshold"
|
|
rbitfld.long 0x0 2. "FSVMINUS,Single-Ended DM indicator" "0: DM voltage at low level,1: DM voltage at high level"
|
|
newline
|
|
rbitfld.long 0x0 1. "FSVPLUS,Single-Ended DP indicator" "0: DM voltage at low level,1: DM voltage at high level"
|
|
rbitfld.long 0x0 0. "CHGDET,Charger detection result of the current mode (primary or secondary)." "0: Low value on pin,1: High value on pin"
|
|
line.long 0x4 "OTG_CID,OTG core ID register"
|
|
hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "OTG_GLPMCFG,OTG core LPM configuration register"
|
|
bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:"
|
|
rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1"
|
|
bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index"
|
|
rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.."
|
|
newline
|
|
rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1"
|
|
rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK"
|
|
newline
|
|
bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1"
|
|
bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency Host mode"
|
|
bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK"
|
|
newline
|
|
bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled"
|
|
group.long 0x100++0x23
|
|
line.long 0x0 "OTG_HPTXFSIZ,OTG host periodic transmit FIFO size register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address"
|
|
line.long 0x4 "OTG_DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register"
|
|
hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x8 "OTG_DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register"
|
|
hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0xC "OTG_DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register"
|
|
hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x10 "OTG_DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register"
|
|
hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x14 "OTG_DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register"
|
|
hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x18 "OTG_DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register"
|
|
hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x1C "OTG_DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x20 "OTG_DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register"
|
|
hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "OTG_HCFG,OTG host configuration register"
|
|
rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1"
|
|
bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "0: FIELD Reserved,1: PHY clock is running at 48 MHz,2: Select 6 MHz PHY clock frequency,3: FIELD Reserved"
|
|
line.long 0x4 "OTG_HFIR,OTG host frame interval register"
|
|
bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.."
|
|
hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "OTG_HFNUM,OTG host frame number/frame time remaining register"
|
|
hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining"
|
|
hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number"
|
|
rgroup.long 0x410++0x7
|
|
line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available"
|
|
line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register"
|
|
hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts"
|
|
group.long 0x418++0x3
|
|
line.long 0x0 "OTG_HAINTMSK,OTG host all channels interrupt mask register"
|
|
hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask"
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "OTG_HPRT,OTG host port control and status register"
|
|
rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,3: FIELD Reserved"
|
|
hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control"
|
|
newline
|
|
bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on"
|
|
rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset"
|
|
bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode"
|
|
newline
|
|
bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven"
|
|
bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition"
|
|
bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled"
|
|
bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port"
|
|
group.long 0x500++0x17
|
|
line.long 0x0 "OTG_HCCHAR0,OTG host channel 0 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT0,OTG host channel 0 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ0,OTG host channel 0 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA0,OTG host channel 0 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x520++0x17
|
|
line.long 0x0 "OTG_HCCHAR1,OTG host channel 1 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT1,OTG host channel 1 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT1,OTG host channel 1 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ1,OTG host channel 1 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA1,OTG host channel 1 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x540++0x17
|
|
line.long 0x0 "OTG_HCCHAR2,OTG host channel 2 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT2,OTG host channel 2 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT2,OTG host channel 2 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ2,OTG host channel 2 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA2,OTG host channel 2 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x560++0x17
|
|
line.long 0x0 "OTG_HCCHAR3,OTG host channel 3 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT3,OTG host channel 3 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT3,OTG host channel 3 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ3,OTG host channel 3 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA3,OTG host channel 3 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x580++0x17
|
|
line.long 0x0 "OTG_HCCHAR4,OTG host channel 4 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT4,OTG host channel 4 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT4,OTG host channel 4 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ4,OTG host channel 4 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA4,OTG host channel 4 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x5A0++0x17
|
|
line.long 0x0 "OTG_HCCHAR5,OTG host channel 5 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT5,OTG host channel 5 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT5,OTG host channel 5 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ5,OTG host channel 5 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA5,OTG host channel 5 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x5C0++0x17
|
|
line.long 0x0 "OTG_HCCHAR6,OTG host channel 6 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT6,OTG host channel 6 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT6,OTG host channel 6 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ6,OTG host channel 6 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA6,OTG host channel 6 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x5E0++0x17
|
|
line.long 0x0 "OTG_HCCHAR7,OTG host channel 7 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT7,OTG host channel 7 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT7,OTG host channel 7 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ7,OTG host channel 7 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA7,OTG host channel 7 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x600++0x17
|
|
line.long 0x0 "OTG_HCCHAR8,OTG host channel 8 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT8,OTG host channel 8 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT8,OTG host channel 8 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ8,OTG host channel 8 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA8,OTG host channel 8 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x620++0x17
|
|
line.long 0x0 "OTG_HCCHAR9,OTG host channel 9 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT9,OTG host channel 9 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT9,OTG host channel 9 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ9,OTG host channel 9 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA9,OTG host channel 9 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x640++0x17
|
|
line.long 0x0 "OTG_HCCHAR10,OTG host channel 10 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT10,OTG host channel 10 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT10,OTG host channel 10 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ10,OTG host channel 10 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA10,OTG host channel 10 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x660++0x17
|
|
line.long 0x0 "OTG_HCCHAR11,OTG host channel 11 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT11,OTG host channel 11 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT11,OTG host channel 11 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ11,OTG host channel 11 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA11,OTG host channel 11 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x680++0x17
|
|
line.long 0x0 "OTG_HCCHAR12,OTG host channel 12 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT12,OTG host channel 12 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT12,OTG host channel 12 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ12,OTG host channel 12 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA12,OTG host channel 12 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x6A0++0x17
|
|
line.long 0x0 "OTG_HCCHAR13,OTG host channel 13 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT13,OTG host channel 13 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT13,OTG host channel 13 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ13,OTG host channel 13 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA13,OTG host channel 13 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x6C0++0x17
|
|
line.long 0x0 "OTG_HCCHAR14,OTG host channel 14 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT14,OTG host channel 14 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT14,OTG host channel 14 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ14,OTG host channel 14 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA14,OTG host channel 14 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x6E0++0x17
|
|
line.long 0x0 "OTG_HCCHAR15,OTG host channel 15 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT15,OTG host channel 15 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT15,OTG host channel 15 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ15,OTG host channel 15 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA15,OTG host channel 15 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x800++0x7
|
|
line.long 0x0 "OTG_DCFG,OTG device configuration register"
|
|
bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,3: FIELD Reserved"
|
|
bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error"
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval"
|
|
hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.."
|
|
bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,2: FIELD Reserved,3: FIELD Reserved"
|
|
line.long 0x4 "OTG_DCTL,OTG device control register"
|
|
bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1"
|
|
bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1"
|
|
bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1"
|
|
bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?"
|
|
rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.."
|
|
newline
|
|
rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.."
|
|
bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.."
|
|
newline
|
|
bitfld.long 0x4 0. "RWUSIG,Remote wakeup signaling" "0,1"
|
|
rgroup.long 0x808++0x3
|
|
line.long 0x0 "OTG_DSTS,OTG device status register"
|
|
bitfld.long 0x0 22.--23. "DEVLNSTS,Device line status" "0,1,2,3"
|
|
hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received SOF"
|
|
newline
|
|
bitfld.long 0x0 3. "EERR,Erratic error" "0,1"
|
|
bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1"
|
|
group.long 0x810++0x7
|
|
line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register"
|
|
bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register"
|
|
bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
rgroup.long 0x818++0x3
|
|
line.long 0x0 "OTG_DAINT,OTG device all endpoints interrupt register"
|
|
hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits"
|
|
group.long 0x81C++0x3
|
|
line.long 0x0 "OTG_DAINTMSK,OTG all endpoints interrupt mask register"
|
|
hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits"
|
|
group.long 0x830++0x7
|
|
line.long 0x0 "OTG_DTHRCTL,OTG device threshold control register"
|
|
bitfld.long 0x0 27. "ARPEN,Arbiter parking enable" "0,1"
|
|
hexmask.long.word 0x0 17.--25. 1. "RXTHRLEN,Receive threshold length"
|
|
newline
|
|
bitfld.long 0x0 16. "RXTHREN,Receive threshold enable" "0,1"
|
|
hexmask.long.word 0x0 2.--10. 1. "TXTHRLEN,Transmit threshold length"
|
|
newline
|
|
bitfld.long 0x0 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1"
|
|
bitfld.long 0x0 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1"
|
|
line.long 0x4 "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register"
|
|
hexmask.long.word 0x4 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits"
|
|
group.long 0x900++0x3
|
|
line.long 0x0 "OTG_DIEPCTL0_INT_BULK,OTG device IN endpoint 0 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x900++0x3
|
|
line.long 0x0 "OTG_DIEPCTL0_ISO,OTG device IN endpoint 0 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x908++0x3
|
|
line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x910++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register"
|
|
bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA0,OTG device IN endpoint 0 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x918++0x3
|
|
line.long 0x0 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x920++0x3
|
|
line.long 0x0 "OTG_DIEPCTL1_INT_BULK,OTG device IN endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x920++0x3
|
|
line.long 0x0 "OTG_DIEPCTL1_ISO,OTG device IN endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x928++0x3
|
|
line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x930++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA1,OTG device IN endpoint 1 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x938++0x3
|
|
line.long 0x0 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x940++0x3
|
|
line.long 0x0 "OTG_DIEPCTL2_INT_BULK,OTG device IN endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x940++0x3
|
|
line.long 0x0 "OTG_DIEPCTL2_ISO,OTG device IN endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x948++0x3
|
|
line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x950++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA2,OTG device IN endpoint 2 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x958++0x3
|
|
line.long 0x0 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x960++0x3
|
|
line.long 0x0 "OTG_DIEPCTL3_INT_BULK,OTG device IN endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x960++0x3
|
|
line.long 0x0 "OTG_DIEPCTL3_ISO,OTG device IN endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x968++0x3
|
|
line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x970++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA3,OTG device IN endpoint 3 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x978++0x3
|
|
line.long 0x0 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x980++0x3
|
|
line.long 0x0 "OTG_DIEPCTL4_INT_BULK,OTG device IN endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x980++0x3
|
|
line.long 0x0 "OTG_DIEPCTL4_ISO,OTG device IN endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x988++0x3
|
|
line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x990++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA4,OTG device IN endpoint 4 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x998++0x3
|
|
line.long 0x0 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x9A0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL5_INT_BULK,OTG device IN endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9A0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL5_ISO,OTG device IN endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9A8++0x3
|
|
line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x9B0++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA5,OTG device IN endpoint 5 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x9B8++0x3
|
|
line.long 0x0 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL6_INT_BULK,OTG device IN endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL6_ISO,OTG device IN endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9C8++0x3
|
|
line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x9D0++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA6,OTG device IN endpoint 6 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x9D8++0x3
|
|
line.long 0x0 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL7_INT_BULK,OTG device IN endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL7_ISO,OTG device IN endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9E8++0x3
|
|
line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x9F0++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA7,OTG device IN endpoint 7 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x9F8++0x3
|
|
line.long 0x0 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "OTG_DIEPCTL8_INT_BULK,OTG device IN endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "OTG_DIEPCTL8_ISO,OTG device IN endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xA08++0x3
|
|
line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xA10++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA8,OTG device IN endpoint 8 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0xA18++0x3
|
|
line.long 0x0 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0xB00++0x3
|
|
line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
|
|
group.long 0xB08++0x3
|
|
line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB10++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register"
|
|
bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA0,OTG device OUT endpoint 0 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB20++0x3
|
|
line.long 0x0 "OTG_DOEPCTL1_INT_BULK,OTG device OUT endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB20++0x3
|
|
line.long 0x0 "OTG_DOEPCTL1_ISO,OTG device OUT endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB28++0x3
|
|
line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB30++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA1,OTG device OUT endpoint 1 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB40++0x3
|
|
line.long 0x0 "OTG_DOEPCTL2_INT_BULK,OTG device OUT endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB40++0x3
|
|
line.long 0x0 "OTG_DOEPCTL2_ISO,OTG device OUT endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB48++0x3
|
|
line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB50++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA2,OTG device OUT endpoint 2 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB60++0x3
|
|
line.long 0x0 "OTG_DOEPCTL3_INT_BULK,OTG device OUT endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB60++0x3
|
|
line.long 0x0 "OTG_DOEPCTL3_ISO,OTG device OUT endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB68++0x3
|
|
line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB70++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA3,OTG device OUT endpoint 3 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB80++0x3
|
|
line.long 0x0 "OTG_DOEPCTL4_INT_BULK,OTG device OUT endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB80++0x3
|
|
line.long 0x0 "OTG_DOEPCTL4_ISO,OTG device OUT endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB88++0x3
|
|
line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB90++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA4,OTG device OUT endpoint 4 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xBA0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL5_INT_BULK,OTG device OUT endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBA0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL5_ISO,OTG device OUT endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBA8++0x3
|
|
line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xBB0++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA5,OTG device OUT endpoint 5 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL6_INT_BULK,OTG device OUT endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL6_ISO,OTG device OUT endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBC8++0x3
|
|
line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xBD0++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA6,OTG device OUT endpoint 6 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xBE0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL7_INT_BULK,OTG device OUT endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBE0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL7_ISO,OTG device OUT endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBE8++0x3
|
|
line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xBF0++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA7,OTG device OUT endpoint 7 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xC00++0x3
|
|
line.long 0x0 "OTG_DOEPCTL8_INT_BULK,OTG device OUT endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xC00++0x3
|
|
line.long 0x0 "OTG_DOEPCTL8_ISO,OTG device OUT endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xC08++0x3
|
|
line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xC10++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA8,OTG device OUT endpoint 8 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xE00++0x7
|
|
line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register"
|
|
rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1"
|
|
rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1"
|
|
rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1"
|
|
bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1"
|
|
line.long 0x4 "OTG_PCGCCTL1,OTG power and clock gating control register 1"
|
|
bitfld.long 0x4 3. "RAMGATEEN,Enable RAM clock gating" "0,1"
|
|
bitfld.long 0x4 1.--2. "CNTGATECLK,Counter for clock gating" "0: 64 clocks,1: 128 clocks,2: FIELD Reserved,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x4 0. "GATEEN,Enable active clock gating" "0,1"
|
|
tree.end
|
|
tree "OTG_HS"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "OTG_GOTGCTL,OTG control and status register"
|
|
rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode"
|
|
bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.."
|
|
newline
|
|
rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid."
|
|
rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid"
|
|
newline
|
|
rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.."
|
|
rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG_HS controller is in A-device mode,1: The OTG_HS controller is in B-device mode"
|
|
newline
|
|
bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected"
|
|
bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1"
|
|
newline
|
|
bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,?"
|
|
bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1"
|
|
newline
|
|
bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.."
|
|
bitfld.long 0x0 3. "VBVALOVAL,V<sub>BUS</sub> valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1"
|
|
newline
|
|
bitfld.long 0x0 2. "VBVALOEN,V<sub>BUS</sub> valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.."
|
|
line.long 0x4 "OTG_GOTGINT,OTG interrupt register"
|
|
bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1"
|
|
bitfld.long 0x4 2. "SEDET,Session end detected" "0,1"
|
|
line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register"
|
|
bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.."
|
|
bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The TXFE (in OTG_DIEPINTx) interrupt indicates..,1: The TXFE (in OTG_DIEPINTx) interrupt indicates.."
|
|
newline
|
|
bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode"
|
|
hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type"
|
|
newline
|
|
bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application."
|
|
line.long 0xC "OTG_GUSBCFG,OTG USB configuration register"
|
|
bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode"
|
|
bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode"
|
|
newline
|
|
bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel"
|
|
bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock"
|
|
newline
|
|
hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time"
|
|
bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "OTG_GRSTCTL,OTG reset register"
|
|
rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1"
|
|
rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1"
|
|
bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1"
|
|
bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1"
|
|
line.long 0x14 "OTG_GINTSTS_HOST,OTG core interrupt register"
|
|
bitfld.long 0x14 31. "WKUPINT,Resume/remote wakeup detected interrupt" "0,1"
|
|
bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1"
|
|
bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1"
|
|
rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1"
|
|
rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1"
|
|
bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1"
|
|
bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1"
|
|
rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1"
|
|
bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1"
|
|
bitfld.long 0x14 12. "USBRST,USB reset" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1"
|
|
bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1"
|
|
rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1"
|
|
rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "SOF,Start of frame" "0,1"
|
|
rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1"
|
|
rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "OTG_GINTSTS_DEVICE,OTG core interrupt register"
|
|
bitfld.long 0x0 31. "WKUPINT,Resume/remote wakeup detected interrupt" "0,1"
|
|
bitfld.long 0x0 30. "SRQINT,Session request/new session detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DISCINT,Disconnect detected interrupt" "0,1"
|
|
bitfld.long 0x0 28. "CIDSCHG,Connector ID status change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LPMINT,LPM interrupt" "0,1"
|
|
rbitfld.long 0x0 26. "PTXFE,Periodic Tx FIFO empty" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 25. "HCINT,Host channels interrupt" "0,1"
|
|
rbitfld.long 0x0 24. "HPRTINT,Host port interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RSTDET,Reset detected interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DATAFSUSP,Data fetch suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "INCOMPISOOUT,Incomplete isochronous OUT transfer" "0,1"
|
|
bitfld.long 0x0 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 19. "OEPINT,OUT endpoint interrupt" "0,1"
|
|
rbitfld.long 0x0 18. "IEPINT,IN endpoint interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EOPF,End of periodic frame interrupt" "0,1"
|
|
bitfld.long 0x0 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENUMDNE,Enumeration done" "0,1"
|
|
bitfld.long 0x0 12. "USBRST,USB reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USBSUSP,USB suspend" "0,1"
|
|
bitfld.long 0x0 10. "ESUSP,Early suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 7. "GONAKEFF,Global OUT NAK effective" "0,1"
|
|
rbitfld.long 0x0 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1"
|
|
rbitfld.long 0x0 4. "RXFLVL,Rx FIFO non-empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SOF,Start of frame" "0,1"
|
|
rbitfld.long 0x0 2. "OTGINT,OTG interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MMIS,Mode mismatch interrupt" "0,1"
|
|
rbitfld.long 0x0 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode"
|
|
line.long 0x4 "OTG_GINTMSK_HOST,OTG interrupt mask register"
|
|
bitfld.long 0x4 31. "WUIM,Resume/remote wakeup detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
rbitfld.long 0x4 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "OTG_GINTMSK_DEVICE,OTG interrupt mask register"
|
|
bitfld.long 0x0 31. "WUIM,Resume/remote wakeup detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 21. "IISOOXFRM,Incomplete isochronous OUT transfer mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "OTG_GRXSTSR_DEVICE,OTG receive status debug read register"
|
|
bitfld.long 0x0 27. "STSPHST,Status phase start" "0,1"
|
|
hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "OTG_GRXSTSR_HOST,OTG receive status debug read register"
|
|
hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number"
|
|
line.long 0x4 "OTG_GRXSTSP_DEVICE,OTG status read and pop registers"
|
|
bitfld.long 0x4 27. "STSPHST,Status phase start" "0,1"
|
|
hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number"
|
|
newline
|
|
hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x4 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "OTG_GRXSTSP_HOST,OTG status read and pop registers"
|
|
hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status"
|
|
bitfld.long 0x0 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
newline
|
|
hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "OTG_GRXFSIZ,OTG receive FIFO size register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXFD,Rx FIFO depth"
|
|
line.long 0x4 "OTG_HNPTXFSIZ_HOST,OTG host non-periodic transmit FIFO size register [alternate]"
|
|
hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "OTG_HNPTXFSIZ_DEVICE,OTG host non-periodic transmit FIFO size register [alternate]"
|
|
hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 Tx FIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start address"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register"
|
|
hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "OTG_GCCFG,OTG general core configuration register"
|
|
bitfld.long 0x0 25. "FORCEHOSTPD,Force host mode pull-downs" "0: Do not force host mode pull-downs,1: Force host mode pull-downs"
|
|
bitfld.long 0x0 24. "VBVALOVEN,Enables a software override of the VBUS B-session detection." "0: Use hardware,1: Use VBVALOVAL to indicate B-session active"
|
|
newline
|
|
bitfld.long 0x0 23. "VBVALOVAL,Software override value of the VBUS B-session detection" "0: B-session inactive,1: B-session active"
|
|
bitfld.long 0x0 22. "SDEN,Secondary detection enable" "0: Secondary detection disabled,1: Secondary detection enabled"
|
|
newline
|
|
bitfld.long 0x0 21. "VBDEN,VBUS detection enable" "0: VBUS detection disabled,1: VBUS detection enabled"
|
|
bitfld.long 0x0 20. "PDEN,Primary detection enable" "0: Primary detection disabled,1: Primary detection enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "DCDEN,Data Contact Detection enable" "0: Data Contact Detection disabled,1: Data Contact Detection enabled"
|
|
bitfld.long 0x0 18. "HVDMSRCEN,Host CDP port Voltage source enable on DM" "0: DM voltage source disabled,1: DM Voltage source enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "HCDPDETEN,Host CDP port voltage detector enable on DP" "0: DP voltage detection disabled,1: DP voltage detection enabled"
|
|
bitfld.long 0x0 16. "HCDPEN,Host CDP behavior enable" "0: Disable CDP behavior,1: Enable CDP behavior"
|
|
newline
|
|
rbitfld.long 0x0 3. "SESSVLD,VBUS session indicator" "0: VBUS is below VBUS session threshold,1: VBUS is above VBUS session threshold"
|
|
rbitfld.long 0x0 2. "FSVMINUS,Single-Ended DM indicator" "0: DM voltage at low level,1: DM voltage at high level"
|
|
newline
|
|
rbitfld.long 0x0 1. "FSVPLUS,Single-Ended DP indicator" "0: DM voltage at low level,1: DM voltage at high level"
|
|
rbitfld.long 0x0 0. "CHGDET,Charger detection result of the current mode (primary or secondary)." "0: Low value on pin,1: High value on pin"
|
|
line.long 0x4 "OTG_CID,OTG core ID register"
|
|
hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "OTG_GLPMCFG,OTG core LPM configuration register"
|
|
bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:"
|
|
rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1"
|
|
bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index"
|
|
rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.."
|
|
newline
|
|
rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1"
|
|
rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK"
|
|
newline
|
|
bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1"
|
|
bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency Host mode"
|
|
bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK"
|
|
newline
|
|
bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled"
|
|
group.long 0x100++0x23
|
|
line.long 0x0 "OTG_HPTXFSIZ,OTG host periodic transmit FIFO size register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth"
|
|
hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address"
|
|
line.long 0x4 "OTG_DIEPTXF1,OTG device IN endpoint transmit FIFO 1 size register"
|
|
hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x8 "OTG_DIEPTXF2,OTG device IN endpoint transmit FIFO 2 size register"
|
|
hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0xC "OTG_DIEPTXF3,OTG device IN endpoint transmit FIFO 3 size register"
|
|
hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x10 "OTG_DIEPTXF4,OTG device IN endpoint transmit FIFO 4 size register"
|
|
hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x14 "OTG_DIEPTXF5,OTG device IN endpoint transmit FIFO 5 size register"
|
|
hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x18 "OTG_DIEPTXF6,OTG device IN endpoint transmit FIFO 6 size register"
|
|
hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x1C "OTG_DIEPTXF7,OTG device IN endpoint transmit FIFO 7 size register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
line.long 0x20 "OTG_DIEPTXF8,OTG device IN endpoint transmit FIFO 8 size register"
|
|
hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth"
|
|
hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "OTG_HCFG,OTG host configuration register"
|
|
rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1"
|
|
bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "0: FIELD Reserved,1: PHY clock is running at 48 MHz,2: Select 6 MHz PHY clock frequency,3: FIELD Reserved"
|
|
line.long 0x4 "OTG_HFIR,OTG host frame interval register"
|
|
bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.."
|
|
hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "OTG_HFNUM,OTG host frame number/frame time remaining register"
|
|
hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining"
|
|
hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number"
|
|
rgroup.long 0x410++0x7
|
|
line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available"
|
|
line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register"
|
|
hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts"
|
|
group.long 0x418++0x3
|
|
line.long 0x0 "OTG_HAINTMSK,OTG host all channels interrupt mask register"
|
|
hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask"
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "OTG_HPRT,OTG host port control and status register"
|
|
rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,3: FIELD Reserved"
|
|
hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control"
|
|
newline
|
|
bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on"
|
|
rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset"
|
|
bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode"
|
|
newline
|
|
bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven"
|
|
bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition"
|
|
bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled"
|
|
bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port"
|
|
group.long 0x500++0x17
|
|
line.long 0x0 "OTG_HCCHAR0,OTG host channel 0 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT0,OTG host channel 0 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ0,OTG host channel 0 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA0,OTG host channel 0 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x520++0x17
|
|
line.long 0x0 "OTG_HCCHAR1,OTG host channel 1 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT1,OTG host channel 1 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT1,OTG host channel 1 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ1,OTG host channel 1 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA1,OTG host channel 1 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x540++0x17
|
|
line.long 0x0 "OTG_HCCHAR2,OTG host channel 2 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT2,OTG host channel 2 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT2,OTG host channel 2 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ2,OTG host channel 2 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA2,OTG host channel 2 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x560++0x17
|
|
line.long 0x0 "OTG_HCCHAR3,OTG host channel 3 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT3,OTG host channel 3 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT3,OTG host channel 3 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ3,OTG host channel 3 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA3,OTG host channel 3 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x580++0x17
|
|
line.long 0x0 "OTG_HCCHAR4,OTG host channel 4 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT4,OTG host channel 4 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT4,OTG host channel 4 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ4,OTG host channel 4 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA4,OTG host channel 4 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x5A0++0x17
|
|
line.long 0x0 "OTG_HCCHAR5,OTG host channel 5 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT5,OTG host channel 5 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT5,OTG host channel 5 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ5,OTG host channel 5 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA5,OTG host channel 5 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x5C0++0x17
|
|
line.long 0x0 "OTG_HCCHAR6,OTG host channel 6 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT6,OTG host channel 6 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT6,OTG host channel 6 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ6,OTG host channel 6 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA6,OTG host channel 6 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x5E0++0x17
|
|
line.long 0x0 "OTG_HCCHAR7,OTG host channel 7 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT7,OTG host channel 7 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT7,OTG host channel 7 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ7,OTG host channel 7 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA7,OTG host channel 7 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x600++0x17
|
|
line.long 0x0 "OTG_HCCHAR8,OTG host channel 8 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT8,OTG host channel 8 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT8,OTG host channel 8 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ8,OTG host channel 8 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA8,OTG host channel 8 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x620++0x17
|
|
line.long 0x0 "OTG_HCCHAR9,OTG host channel 9 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT9,OTG host channel 9 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT9,OTG host channel 9 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ9,OTG host channel 9 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA9,OTG host channel 9 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x640++0x17
|
|
line.long 0x0 "OTG_HCCHAR10,OTG host channel 10 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT10,OTG host channel 10 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT10,OTG host channel 10 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ10,OTG host channel 10 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA10,OTG host channel 10 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x660++0x17
|
|
line.long 0x0 "OTG_HCCHAR11,OTG host channel 11 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT11,OTG host channel 11 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT11,OTG host channel 11 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ11,OTG host channel 11 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA11,OTG host channel 11 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x680++0x17
|
|
line.long 0x0 "OTG_HCCHAR12,OTG host channel 12 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT12,OTG host channel 12 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT12,OTG host channel 12 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ12,OTG host channel 12 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA12,OTG host channel 12 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x6A0++0x17
|
|
line.long 0x0 "OTG_HCCHAR13,OTG host channel 13 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT13,OTG host channel 13 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT13,OTG host channel 13 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ13,OTG host channel 13 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA13,OTG host channel 13 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x6C0++0x17
|
|
line.long 0x0 "OTG_HCCHAR14,OTG host channel 14 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT14,OTG host channel 14 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT14,OTG host channel 14 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ14,OTG host channel 14 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA14,OTG host channel 14 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x6E0++0x17
|
|
line.long 0x0 "OTG_HCCHAR15,OTG host channel 15 characteristics register"
|
|
bitfld.long 0x0 31. "CHENA,Channel enable" "0: Channel disabled,1: Channel enabled"
|
|
bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame"
|
|
hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.."
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1"
|
|
bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number"
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
line.long 0x4 "OTG_HCSPLT15,OTG host channel 15 split control register"
|
|
bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1"
|
|
bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.."
|
|
hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address"
|
|
line.long 0x8 "OTG_HCINT15,OTG host channel 15 interrupt register"
|
|
bitfld.long 0x8 10. "DTERR,Data toggle error." "0,1"
|
|
bitfld.long 0x8 9. "FRMOR,Frame overrun." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "BBERR,Babble error." "0,1"
|
|
bitfld.long 0x8 7. "TXERR,Transaction error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt." "0,1"
|
|
bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "NAK,NAK response received interrupt." "0,1"
|
|
bitfld.long 0x8 3. "STALL,STALL response received interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x8 1. "CHH,Channel halted." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1"
|
|
line.long 0xC "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register"
|
|
bitfld.long 0xC 10. "DTERRM,Data toggle error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 9. "FRMORM,Frame overrun mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 8. "BBERRM,Babble error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 7. "TXERRM,Transaction error mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 6. "NYET,response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 2. "AHBERRM,AHB error." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x10 "OTG_HCTSIZ15,OTG host channel 15 transfer size register"
|
|
bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1"
|
|
bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)"
|
|
newline
|
|
hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x14 "OTG_HCDMA15,OTG host channel 15 DMA address register"
|
|
hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address"
|
|
group.long 0x800++0x7
|
|
line.long 0x0 "OTG_DCFG,OTG device configuration register"
|
|
bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,3: FIELD Reserved"
|
|
bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error"
|
|
newline
|
|
bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval"
|
|
hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address"
|
|
newline
|
|
bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.."
|
|
bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,2: FIELD Reserved,3: FIELD Reserved"
|
|
line.long 0x4 "OTG_DCTL,OTG device control register"
|
|
bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1"
|
|
bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1"
|
|
bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1"
|
|
bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?"
|
|
rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.."
|
|
newline
|
|
rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.."
|
|
bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.."
|
|
newline
|
|
bitfld.long 0x4 0. "RWUSIG,Remote wakeup signaling" "0,1"
|
|
rgroup.long 0x808++0x3
|
|
line.long 0x0 "OTG_DSTS,OTG device status register"
|
|
bitfld.long 0x0 22.--23. "DEVLNSTS,Device line status" "0,1,2,3"
|
|
hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received SOF"
|
|
newline
|
|
bitfld.long 0x0 3. "EERR,Erratic error" "0,1"
|
|
bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1"
|
|
group.long 0x810++0x7
|
|
line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register"
|
|
bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register"
|
|
bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
newline
|
|
bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt"
|
|
rgroup.long 0x818++0x3
|
|
line.long 0x0 "OTG_DAINT,OTG device all endpoints interrupt register"
|
|
hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits"
|
|
group.long 0x81C++0x3
|
|
line.long 0x0 "OTG_DAINTMSK,OTG all endpoints interrupt mask register"
|
|
hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits"
|
|
hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits"
|
|
group.long 0x830++0x7
|
|
line.long 0x0 "OTG_DTHRCTL,OTG device threshold control register"
|
|
bitfld.long 0x0 27. "ARPEN,Arbiter parking enable" "0,1"
|
|
hexmask.long.word 0x0 17.--25. 1. "RXTHRLEN,Receive threshold length"
|
|
newline
|
|
bitfld.long 0x0 16. "RXTHREN,Receive threshold enable" "0,1"
|
|
hexmask.long.word 0x0 2.--10. 1. "TXTHRLEN,Transmit threshold length"
|
|
newline
|
|
bitfld.long 0x0 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1"
|
|
bitfld.long 0x0 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1"
|
|
line.long 0x4 "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register"
|
|
hexmask.long.word 0x4 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits"
|
|
group.long 0x900++0x3
|
|
line.long 0x0 "OTG_DIEPCTL0_INT_BULK,OTG device IN endpoint 0 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x900++0x3
|
|
line.long 0x0 "OTG_DIEPCTL0_ISO,OTG device IN endpoint 0 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x908++0x3
|
|
line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x910++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register"
|
|
bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA0,OTG device IN endpoint 0 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x918++0x3
|
|
line.long 0x0 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x920++0x3
|
|
line.long 0x0 "OTG_DIEPCTL1_INT_BULK,OTG device IN endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x920++0x3
|
|
line.long 0x0 "OTG_DIEPCTL1_ISO,OTG device IN endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x928++0x3
|
|
line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x930++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA1,OTG device IN endpoint 1 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x938++0x3
|
|
line.long 0x0 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x940++0x3
|
|
line.long 0x0 "OTG_DIEPCTL2_INT_BULK,OTG device IN endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x940++0x3
|
|
line.long 0x0 "OTG_DIEPCTL2_ISO,OTG device IN endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x948++0x3
|
|
line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x950++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA2,OTG device IN endpoint 2 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x958++0x3
|
|
line.long 0x0 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x960++0x3
|
|
line.long 0x0 "OTG_DIEPCTL3_INT_BULK,OTG device IN endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x960++0x3
|
|
line.long 0x0 "OTG_DIEPCTL3_ISO,OTG device IN endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x968++0x3
|
|
line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x970++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA3,OTG device IN endpoint 3 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x978++0x3
|
|
line.long 0x0 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x980++0x3
|
|
line.long 0x0 "OTG_DIEPCTL4_INT_BULK,OTG device IN endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x980++0x3
|
|
line.long 0x0 "OTG_DIEPCTL4_ISO,OTG device IN endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x988++0x3
|
|
line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x990++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA4,OTG device IN endpoint 4 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x998++0x3
|
|
line.long 0x0 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x9A0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL5_INT_BULK,OTG device IN endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9A0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL5_ISO,OTG device IN endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9A8++0x3
|
|
line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x9B0++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA5,OTG device IN endpoint 5 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x9B8++0x3
|
|
line.long 0x0 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL6_INT_BULK,OTG device IN endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL6_ISO,OTG device IN endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9C8++0x3
|
|
line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x9D0++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA6,OTG device IN endpoint 6 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x9D8++0x3
|
|
line.long 0x0 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL7_INT_BULK,OTG device IN endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x0 "OTG_DIEPCTL7_ISO,OTG device IN endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0x9E8++0x3
|
|
line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0x9F0++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA7,OTG device IN endpoint 7 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0x9F8++0x3
|
|
line.long 0x0 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "OTG_DIEPCTL8_INT_BULK,OTG device IN endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "OTG_DIEPCTL8_ISO,OTG device IN endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number"
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xA08++0x3
|
|
line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register"
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1"
|
|
rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1"
|
|
bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1"
|
|
bitfld.long 0x0 3. "TOC,Timeout condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xA10++0x7
|
|
line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register"
|
|
bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DIEPDMA8,OTG device IN endpoint 8 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
rgroup.long 0xA18++0x3
|
|
line.long 0x0 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available"
|
|
group.long 0xB00++0x3
|
|
line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
|
|
group.long 0xB08++0x3
|
|
line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB10++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register"
|
|
bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets"
|
|
bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA0,OTG device OUT endpoint 0 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB20++0x3
|
|
line.long 0x0 "OTG_DOEPCTL1_INT_BULK,OTG device OUT endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB20++0x3
|
|
line.long 0x0 "OTG_DOEPCTL1_ISO,OTG device OUT endpoint 1 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB28++0x3
|
|
line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB30++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA1,OTG device OUT endpoint 1 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB40++0x3
|
|
line.long 0x0 "OTG_DOEPCTL2_INT_BULK,OTG device OUT endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB40++0x3
|
|
line.long 0x0 "OTG_DOEPCTL2_ISO,OTG device OUT endpoint 2 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB48++0x3
|
|
line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB50++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA2,OTG device OUT endpoint 2 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB60++0x3
|
|
line.long 0x0 "OTG_DOEPCTL3_INT_BULK,OTG device OUT endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB60++0x3
|
|
line.long 0x0 "OTG_DOEPCTL3_ISO,OTG device OUT endpoint 3 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB68++0x3
|
|
line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB70++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA3,OTG device OUT endpoint 3 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xB80++0x3
|
|
line.long 0x0 "OTG_DOEPCTL4_INT_BULK,OTG device OUT endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB80++0x3
|
|
line.long 0x0 "OTG_DOEPCTL4_ISO,OTG device OUT endpoint 4 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xB88++0x3
|
|
line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xB90++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA4,OTG device OUT endpoint 4 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xBA0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL5_INT_BULK,OTG device OUT endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBA0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL5_ISO,OTG device OUT endpoint 5 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBA8++0x3
|
|
line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xBB0++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA5,OTG device OUT endpoint 5 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL6_INT_BULK,OTG device OUT endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL6_ISO,OTG device OUT endpoint 6 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBC8++0x3
|
|
line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xBD0++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA6,OTG device OUT endpoint 6 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xBE0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL7_INT_BULK,OTG device OUT endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBE0++0x3
|
|
line.long 0x0 "OTG_DOEPCTL7_ISO,OTG device OUT endpoint 7 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xBE8++0x3
|
|
line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xBF0++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA7,OTG device OUT endpoint 7 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xC00++0x3
|
|
line.long 0x0 "OTG_DOEPCTL8_INT_BULK,OTG device OUT endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1"
|
|
bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xC00++0x3
|
|
line.long 0x0 "OTG_DOEPCTL8_ISO,OTG device OUT endpoint 8 control register"
|
|
bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1"
|
|
bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1"
|
|
bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SNAK,Set NAK" "0,1"
|
|
bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "STALL,STALL handshake" "0,1"
|
|
bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
|
|
rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
|
|
newline
|
|
rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame"
|
|
bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size"
|
|
group.long 0xC08++0x3
|
|
line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register"
|
|
bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1"
|
|
bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NAK,NAK input" "0,1"
|
|
bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1"
|
|
bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1"
|
|
bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1"
|
|
bitfld.long 0x0 2. "AHBERR,AHB error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1"
|
|
bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1"
|
|
group.long 0xC10++0x7
|
|
line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register"
|
|
bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
|
|
hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size"
|
|
line.long 0x4 "OTG_DOEPDMA8,OTG device OUT endpoint 8 DMA address register"
|
|
hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address"
|
|
group.long 0xE00++0x7
|
|
line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register"
|
|
rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1"
|
|
rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1"
|
|
rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1"
|
|
bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1"
|
|
line.long 0x4 "OTG_PCGCCTL1,OTG power and clock gating control register 1"
|
|
bitfld.long 0x4 3. "RAMGATEEN,Enable RAM clock gating" "0,1"
|
|
bitfld.long 0x4 1.--2. "CNTGATECLK,Counter for clock gating" "0: 64 clocks,1: 128 clocks,2: FIELD Reserved,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x4 0. "GATEEN,Enable active clock gating" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PKA (Public Key Accelerator)"
|
|
base ad:0x48022000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PKA_CR,PKA control register"
|
|
bitfld.long 0x0 21. "OPERRIE,Operation error interrupt enable" "0: No interrupt is generated when OPERRF flag is..,1: An interrupt is generated when OPERRF flag is.."
|
|
bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0: No interrupt is generated when ADDRERRF flag is..,1: An interrupt is generated when ADDRERRF flag is.."
|
|
newline
|
|
bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0: No interrupt is generated when RAMERRF flag is..,1: An interrupt is generated when RAMERRF flag is.."
|
|
bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0: No interrupt is generated when PROCENDF flag is..,1: An interrupt is generated when PROCENDF flag is.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA operation code"
|
|
bitfld.long 0x0 1. "START,start the operation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,PKA enable." "0: Disable PKA,1: Enable PKA.PKA becomes functional when INITOK is.."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PKA_SR,PKA status register"
|
|
bitfld.long 0x0 21. "OPERRF,Operation error flag" "0: No event error,1: An illegal or unknown operation has been.."
|
|
bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0: No address error,1: Address access is out of range (unmapped address)"
|
|
newline
|
|
bitfld.long 0x0 19. "RAMERRF,PKA RAM error flag" "0: No PKA RAM access error,1: An AHB access to the PKA RAM occurred while the.."
|
|
bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0: Operation in progress,1: PKA operation is completed. This flag is set.."
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,PKA operation is in progress" "0: No operation is in progress (default),1: An operation is in progress"
|
|
bitfld.long 0x0 1. "LMF,Limited mode flag" "0: All values documented in MODE bitfield can be..,1: Only ECDSA verification (MODE = 0x26) is.."
|
|
newline
|
|
bitfld.long 0x0 0. "INITOK,PKA initialization OK" "0: PKA is not initialized correctly. START bit..,1: PKA is initialized correctly and can be used.."
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PKA_CLRFR,PKA clear flag register"
|
|
bitfld.long 0x0 21. "OPERRFC,Clear operation error flag" "0: No action,1: Clear the OPERRF flag in PKA_SR"
|
|
bitfld.long 0x0 20. "ADDRERRFC,Clear address error flag" "0: No action,1: Clear the ADDRERRF flag in PKA_SR"
|
|
newline
|
|
bitfld.long 0x0 19. "RAMERRFC,Clear PKA RAM error flag" "0: No action,1: Clear the RAMERRF flag in PKA_SR"
|
|
bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0: No action,1: Clear the PROCENDF flag in PKA_SR"
|
|
tree.end
|
|
tree "PSSI (Parallel Synchronous Slave Interface)"
|
|
base ad:0x48000400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PSSI_CR,PSSI control register"
|
|
bitfld.long 0x0 31. "OUTEN,Data direction selection bit" "0: Receive mode: data is input synchronously with..,1: Transmit mode: data is output synchronously with.."
|
|
bitfld.long 0x0 30. "DMAEN,DMA enable bit" "0: DMA transfers are disabled. The user application..,1: DMA transfers are enabled (default.."
|
|
newline
|
|
bitfld.long 0x0 29. "CKSRC,Clock source" "0: External clock (PSSI_PDCK in input),1: Internal clock (PSSI_PDCK in output)"
|
|
bitfld.long 0x0 18.--20. "DERDYCFG,Data enable and ready configuration" "0: PSSI_DE and PSSI_RDY both disabled,1: Only PSSI_RDY enabled,2: Only PSSI_DE enabled,3: Both PSSI_RDY and PSSI_DE alternate functions..,4: Both PSSI_RDY and PSSI_DE features enabled -..,5: Only PSSI_RDY function enabled but mapped to..,6: Only PSSI_DE function enabled but mapped to..,7: Both PSSI_RDY and PSSI_DE features enabled -.."
|
|
newline
|
|
bitfld.long 0x0 14. "ENABLE,PSSI enable" "0: PSSI disabled,1: PSSI enabled"
|
|
bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0: Interface captures 8-bit data on every parallel..,1: Reserved must not be selected,2: Reserved must not be selected,3: The interface captures 16-bit data on every.."
|
|
newline
|
|
bitfld.long 0x0 8. "RDYPOL,Ready (PSSI_RDY) polarity" "0: PSSI_RDY active low (0 indicates that the..,1: PSSI_RDY active high (1 indicates that the.."
|
|
bitfld.long 0x0 6. "DEPOL,Data enable (PSSI_DE) polarity" "0: PSSI_DE active low (0 indicates that data is..,1: PSSI_DE active high (1 indicates that data is.."
|
|
newline
|
|
bitfld.long 0x0 5. "CKPOL,Parallel data clock polarity" "0: Falling edge active for inputs or rising edge..,1: Rising edge active for inputs or falling edge.."
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "PSSI_SR,PSSI status register"
|
|
bitfld.long 0x0 3. "RTT1B,FIFO is ready to transfer one byte" "0: FIFO is not ready for a 1-byte transfer,1: FIFO is ready for a one byte (32-bit) transfer."
|
|
bitfld.long 0x0 2. "RTT4B,FIFO is ready to transfer four bytes" "0: FIFO is not ready for a four-byte transfer,1: FIFO is ready for a four-byte (32-bit) transfer."
|
|
line.long 0x4 "PSSI_RIS,PSSI raw interrupt status register"
|
|
bitfld.long 0x4 1. "OVR_RIS,Data buffer overrun/underrun raw interrupt status" "0: No overrun/underrun occurred,1: An overrun/underrun occurred: overrun in receive.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PSSI_IER,PSSI interrupt enable register"
|
|
bitfld.long 0x0 1. "OVR_IE,Data buffer overrun/underrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if either an overrun.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "PSSI_MIS,PSSI masked interrupt status register"
|
|
bitfld.long 0x0 1. "OVR_MIS,Data buffer overrun/underrun masked interrupt status" "0: No interrupt is generated when an..,1: An interrupt is generated if there is either an.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "PSSI_ICR,PSSI interrupt clear register"
|
|
bitfld.long 0x0 1. "OVR_ISC,Data buffer overrun/underrun interrupt status clear" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PSSI_DR,PSSI data register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0"
|
|
tree.end
|
|
tree "PWR (Power Control)"
|
|
base ad:0x58024800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PWR_CR1,PWR control register 1"
|
|
bitfld.long 0x0 14.--15. "ALS,Analog voltage detector level selection" "0: AVD level 1,1: AVD level 2,2: AVD level 3,3: AVD level 4"
|
|
bitfld.long 0x0 13. "AVDEN,Peripheral voltage monitor on VDDA enable" "0: Peripheral voltage monitor on VDDA disabled,1: Peripheral voltage monitor on VDDA enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "AVDREADY,analog voltage ready" "0: peripheral analog voltage VDDA not ready (default),1: peripheral analog voltage VDDA ready"
|
|
bitfld.long 0x0 11. "BOOSTE,analog switch VBoost control" "0: booster disabled (default),1: booster enabled if analog voltage ready.."
|
|
newline
|
|
bitfld.long 0x0 10. "RLPSN,RAM low power mode disable in STOP." "0: RAM enters to low power mode when system enters..,1: RAM remains in normal mode when system enters to.."
|
|
bitfld.long 0x0 9. "FLPS,Flash low-power mode in Stop mode" "0: Flash memory remains in normal mode when device..,1: Flash memory enters low-power mode when device.."
|
|
newline
|
|
bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0: Access to RTC RTC backup registers and backup..,1: Access to RTC RTC backup registers and backup.."
|
|
bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level selection" "0: PVD level 1,1: PVD level 2,2: PVD level 3,3: PVD level 4,4: PVD level 5,5: PVD level 6,6: PVD level 7,7: External voltage level on PVD_IN pin compared to.."
|
|
newline
|
|
bitfld.long 0x0 4. "PVDE,Programmable voltage detector enable" "0: Programmable voltage detector disabled.,1: Programmable voltage detector enabled"
|
|
bitfld.long 0x0 0. "SVOS,System Stop mode voltage scaling selection." "0: SVOS Low,1: SVOS High (default)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PWR_SR1,PWR control status register 1"
|
|
bitfld.long 0x0 13. "AVDO,Analog voltage detector output on VDDA" "0: VDDA is equal or higher than the AVD threshold..,1: VDDA is lower than the AVD threshold selected.."
|
|
bitfld.long 0x0 4. "PVDO,Programmable voltage detect output" "0: VDD or PVD_IN voltage is equal or higher than..,1: VDD or PVD_IN voltage is lower than the PVD.."
|
|
newline
|
|
bitfld.long 0x0 1. "ACTVOSRDY,Voltage levels ready bit for currently used ACTVOS and SDHILEVEL" "0: Voltage level invalid above or below current..,1: Voltage level valid at current ACTVOS and.."
|
|
bitfld.long 0x0 0. "ACTVOS,VOS currently applied for V<sub>CORE</sub> voltage scaling selection." "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "PWR_CSR1,PWR control status register 1"
|
|
rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high threshold" "0: Temperature below high threshold level.,1: Temperature equal or above high threshold level."
|
|
rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low threshold" "0: Temperature above low threshold level.,1: Temperature equal or below low threshold level."
|
|
newline
|
|
rbitfld.long 0x0 21. "VBATH,V<sub>BAT</sub> level monitoring versus high threshold" "0: V<sub>BAT</sub> level below high threshold level.,1: V<sub>BAT</sub> level equal or above high.."
|
|
rbitfld.long 0x0 20. "VBATL,V<sub>BAT</sub> level monitoring versus low threshold" "0: V<sub>BAT</sub> level above low threshold level.,1: V<sub>BAT</sub> level equal or below low.."
|
|
newline
|
|
rbitfld.long 0x0 16. "BRRDY,Backup regulator ready" "0: Backup regulator not ready.,1: Backup regulator ready."
|
|
bitfld.long 0x0 4. "MONEN,V<sub>BAT</sub> and temperature monitoring enable" "0: V<sub>BAT</sub> and temperature monitoring..,1: V<sub>BAT</sub> and temperature monitoring.."
|
|
newline
|
|
bitfld.long 0x0 0. "BREN,Backup regulator enable" "0: Backup regulator disabled.,1: Backup regulator enabled."
|
|
line.long 0x4 "PWR_CSR2,PWR control register 2"
|
|
bitfld.long 0x4 27. "USBHSREGEN,USB HS regulator enable." "0: USB HS PHY regulator disabled (default),1: USB HS PHY regulator enabled"
|
|
rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0: USB33 supply not ready,1: USB33 supply ready."
|
|
newline
|
|
bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0: USB regulator disabled,1: USB regulator enabled."
|
|
bitfld.long 0x4 24. "USB33DEN,VDD33_USB voltage level detector enable" "0: VDD33_USB voltage level detector disabled,1: VDD33_USB voltage level detector enabled."
|
|
newline
|
|
rbitfld.long 0x4 16. "SDEXTRDY,SMPS step-down converter external supply ready" "0: External supply not ready.,1: External supply ready."
|
|
bitfld.long 0x4 15. "EN_XSPIM2,EN_XSPIM2: this bit allows the SW to enable the XSPI interface when" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "EN_XSPIM1,EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1" "0,1"
|
|
bitfld.long 0x4 12.--13. "XSPICAP2,XSPI port 2 capacitor control bits" "0: XSPI Capacitor OFF (default) note: to confirm..,1: XSPI Capacitor set to 1/3,2: XSPI Capacitor set to 2/3,3: XSPI Capacitor set to full capacitance"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "XSPICAP1,XSPI port 1 capacitor control bits" "0: XSPI Capacitor OFF (default) note: to confirm..,1: XSPI Capacitor set to 1/3,2: XSPI Capacitor set to 2/3,3: XSPI Capacitor set to full capacitance"
|
|
bitfld.long 0x4 9. "VBRS,VBAT charging resistor selection" "0: Charge VBAT through a 5 k resistor.,1: Charge VBAT through a 1.5 k resistor."
|
|
newline
|
|
bitfld.long 0x4 8. "VBE,VBAT charging enable" "0: VBAT battery charging disabled.,1: VBAT battery charging enabled."
|
|
bitfld.long 0x4 4. "SDHILEVEL,SMPS step-down converter voltage output for LDO or external supply" "0: Reset value,1: 1.8V"
|
|
newline
|
|
bitfld.long 0x4 3. "SMPSEXTHP,SMPS external power delivery selection" "0: SMPS normal operating mode no power delivery to..,1: SMPS external operating mode power delivery to.."
|
|
bitfld.long 0x4 2. "SDEN,SMPS step-down converter enable" "0: SMPS step-down converter disabled,?"
|
|
newline
|
|
bitfld.long 0x4 1. "LDOEN,Low drop-out regulator enable" "0: Low drop-out regulator disabled.,1: Low drop-out regulator enabled (default)"
|
|
bitfld.long 0x4 0. "BYPASS,Power management unit bypass" "0: Power management unit normal operation.,1: Power management unit bypassed voltage.."
|
|
line.long 0x8 "PWR_CSR3,PWR CPU control register 3"
|
|
rbitfld.long 0x8 9. "SBF,System Standby flag" "0: System has not been in Standby mode,1: System has been in Standby mode"
|
|
rbitfld.long 0x8 8. "STOPF,STOP flag" "0: System has not been in Stop mode,1: System has been in Stop mode"
|
|
newline
|
|
bitfld.long 0x8 1. "CSSF,Clear Standby and Stop flags (always read as 0)" "0: No effect.,1: flags (STOPF SBF) are cleared."
|
|
bitfld.long 0x8 0. "PDDS,Power Down Deepsleep." "0: Stop mode when device enters Deepsleep.,1: Standby mode when device enters Deepsleep."
|
|
line.long 0xC "PWR_CSR4,PWR control status register 4"
|
|
rbitfld.long 0xC 1. "VOSRDY,VOS Ready bit" "0: Not ready voltage level below VOS selected level.,1: Ready voltage level at or above VOS selected.."
|
|
bitfld.long 0xC 0. "VOS,Voltage scaling selection according to performance" "0: VOS Low level (default),1: VOS High level"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PWR_WKUPCR,PWR wakeup clear register"
|
|
bitfld.long 0x0 3. "WKUPC4,Clear Wakeup pin flag for WKUP4" "0: No effect,1: Writing 1 clears the WKUPF4 Wakeup pin flag (bit.."
|
|
bitfld.long 0x0 2. "WKUPC3,Clear Wakeup pin flag for WKUP3" "0: No effect,1: Writing 1 clears the WKUPF3 Wakeup pin flag (bit.."
|
|
newline
|
|
bitfld.long 0x0 1. "WKUPC2,Clear Wakeup pin flag for WKUP2" "0: No effect,1: Writing 1 clears the WKUPF2 Wakeup pin flag (bit.."
|
|
bitfld.long 0x0 0. "WKUPC1,Clear Wakeup pin flag for WKUP1" "0: No effect,1: Writing 1 clears the WKUPF1 Wakeup pin flag (bit.."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PWR_WKUPFR,PWR wakeup flag register"
|
|
bitfld.long 0x0 3. "WKUPF4,Wakeup pin WKUP4 flag." "0: No wakeup event occurred,1: A wakeup event was received from WKUP4 pin"
|
|
bitfld.long 0x0 2. "WKUPF3,Wakeup pin WKUP3 flag." "0: No wakeup event occurred,1: A wakeup event was received from WKUP3 pin"
|
|
newline
|
|
bitfld.long 0x0 1. "WKUPF2,Wakeup pin WKUP2 flag." "0: No wakeup event occurred,1: A wakeup event was received from WKUP2 pin"
|
|
bitfld.long 0x0 0. "WKUPF1,Wakeup pin WKUP1 flag." "0: No wakeup event occurred,1: A wakeup event was received from WKUP1 pin"
|
|
group.long 0x28++0x1F
|
|
line.long 0x0 "PWR_WKUPEPR,PWR wakeup enable and polarity register"
|
|
bitfld.long 0x0 22.--23. "WKUPPUPD4,Wakeup pin pull configuration for WKUPn " "0: No pull-up,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0x0 20.--21. "WKUPPUPD3,Wakeup pin pull configuration for WKUPn " "0: No pull-up,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "WKUPPUPD2,Wakeup pin pull configuration for WKUPn " "0: No pull-up,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
bitfld.long 0x0 16.--17. "WKUPPUPD1,Wakeup pin pull configuration for WKUPn " "0: No pull-up,1: Pull-up,2: Pull-down,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 11. "WKUPP4,Wakeup pin polarity bit for WKUPn (n = 4 3 2 1)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
|
|
bitfld.long 0x0 10. "WKUPP3,Wakeup pin polarity bit for WKUPn (n = 4 3 2 1)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
|
|
newline
|
|
bitfld.long 0x0 9. "WKUPP2,Wakeup pin polarity bit for WKUPn (n = 4 3 2 1)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
|
|
bitfld.long 0x0 8. "WKUPP1,Wakeup pin polarity bit for WKUPn (n = 4 3 2 1)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
|
|
newline
|
|
bitfld.long 0x0 3. "WKUPEN4,Enable Wakeup Pin WKUPn (n = 4 3 2 1)" "0: An event on WKUPn pin does not wakeup the system..,1: A rising or falling edge on WKUPn pin wakes-up.."
|
|
bitfld.long 0x0 2. "WKUPEN3,Enable Wakeup Pin WKUPn (n = 4 3 2 1)" "0: An event on WKUPn pin does not wakeup the system..,1: A rising or falling edge on WKUPn pin wakes-up.."
|
|
newline
|
|
bitfld.long 0x0 1. "WKUPEN2,Enable Wakeup Pin WKUPn (n = 4 3 2 1)" "0: An event on WKUPn pin does not wakeup the system..,1: A rising or falling edge on WKUPn pin wakes-up.."
|
|
bitfld.long 0x0 0. "WKUPEN1,Enable Wakeup Pin WKUPn (n = 4 3 2 1)" "0: An event on WKUPn pin does not wakeup the system..,1: A rising or falling edge on WKUPn pin wakes-up.."
|
|
line.long 0x4 "PWR_UCPDR,PWR USB Type-C and Power Delivery register"
|
|
bitfld.long 0x4 1. "UCPD_STBY,UCPD Standby mode" "0,1"
|
|
bitfld.long 0x4 0. "UCPD_DBDIS,UCPD dead battery disable" "0: UCPD dead battery pull-down behavior enabled on..,1: UCPD dead battery pull-down behavior disabled.."
|
|
line.long 0x8 "PWR_APCR,PWR apply pull configuration register"
|
|
bitfld.long 0x8 31. "I3CPB9_PU,Port PB9 I3C pull-up bit" "0,1"
|
|
bitfld.long 0x8 30. "I3CPB8_PU,Port PB8 I3C pull-up bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I3CPB7_PU,Port PB7 I3C pull-up bit" "0,1"
|
|
bitfld.long 0x8 28. "I3CPB6_PU,Port PB6 I3C pull-up bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PO5_PUPD,Port O bit 5 pull-up/down configuration" "0,1"
|
|
bitfld.long 0x8 16. "PN7_PUPD,Port N bit 7 pull-up/down configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "APC,Apply pull-up and pull-down configuration" "0,1"
|
|
line.long 0xC "PWR_PUCRN,PWR port N pull-up control register"
|
|
bitfld.long 0xC 12. "PUN12,Port N pull-up bit 12" "0,1"
|
|
bitfld.long 0xC 6. "PUN6,Port N pull-up bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PUN1,Port N pull-up bit 1" "0,1"
|
|
line.long 0x10 "PWR_PDCRN,PWR port N pull-down control register"
|
|
bitfld.long 0x10 12. "PDN12,Port N pull-down bit 12" "0,1"
|
|
bitfld.long 0x10 8. "PDN8N11,Port N - PN8 to PN11 pull-down activation" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "PDN6,Port N pull-down bit 6" "0,1"
|
|
bitfld.long 0x10 2. "PDN2N5,Port N PN2 to PN5 pull-down activation" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PDN1,Port N pull-down bit 1" "0,1"
|
|
bitfld.long 0x10 0. "PDN0,Port N pull-down bit 0" "0,1"
|
|
line.long 0x14 "PWR_PUCRO,PWR port O pull-up control register"
|
|
bitfld.long 0x14 4. "PUO4,Port O pull-up bit 4" "0,1"
|
|
bitfld.long 0x14 1. "PUO1,(n = 1 to 0) Port O pull-up bits" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "PUO0,(n = 1 to 0) Port O pull-up bits" "0,1"
|
|
line.long 0x18 "PWR_PDCRO,PWR port O pull-down control register"
|
|
bitfld.long 0x18 4. "PDO4,Port O pull-down bit y" "0,1"
|
|
bitfld.long 0x18 3. "PDO3,Port O pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "PDO2,Port O pull-down bit y" "0,1"
|
|
bitfld.long 0x18 1. "PDO1,Port O pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "PDO0,Port O pull-down bit y" "0,1"
|
|
line.long 0x1C "PWR_PDCRP,PWR port P pull-down control register"
|
|
bitfld.long 0x1C 12. "PDP12P15,Port P12-P15 pull-down activation" "0,1"
|
|
bitfld.long 0x1C 8. "PDP8P11,Port P8-P11 pull-down activation" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "PDP4P7,Port P4-P7 pull-down activation" "0,1"
|
|
bitfld.long 0x1C 0. "PDP0P3,Port P0-P3 pull-down activation" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PWR_PDR1,PWR debug register 1"
|
|
bitfld.long 0x0 16. "SYNC_ADC,(Non-User bit)" "0: SD_Converter clock free running,1: SD_Converter clock synchronised to ADC."
|
|
bitfld.long 0x0 3. "SDFPWMEN,Step down converter force PWM mode" "0: SD_Converter Normal mode,1: SD_Converter forced PWM mode"
|
|
newline
|
|
bitfld.long 0x0 0. "UNLOCKED,Debug Register Unlocked." "0: accessed locked: key was not written and after..,1: after key 0xCAFECAFE was written in this register"
|
|
tree.end
|
|
tree "RAMCFG (RAM Configuration)"
|
|
base ad:0x58027000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "RAMECC_IER,RAMECC interrupt enable register"
|
|
bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write (BW) interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 1. "GECCSEIE,Global ECC single error interrupt enable" "0: no interrupt generated when an ECC single error..,1: interrupt generated when an ECC single error.."
|
|
bitfld.long 0x0 0. "GIE,Global interrupt enable" "0: no interrupt generated when an ECC error occurs,1: interrupt generated when an ECC error occurs"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "RAMECC_M1CR,RAMECC monitor 1 configuration register"
|
|
bitfld.long 0x0 16.--17. "ECCTEA,ECC Test ECC access" "0: inactive,1: write and read access blocked on data memory,2: write and read access blocked on ECC memory,3: inactive"
|
|
bitfld.long 0x0 8. "ECCDEBWCEN,ECC double error on byte write (BW) counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 7. "ECCDECEN,ECC double error counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
bitfld.long 0x0 6. "ECCSECEN,ECC single error counter enable" "0: no counter increment when an ECC single error..,1: counter increment when an ECC single error occurs"
|
|
newline
|
|
bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0: no error context preserved when an ECC error..,1: error context preserved when an ECC error occurs"
|
|
bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW) interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt enable" "0: no interrupt generated when an ECC single error..,1: interrupt generated when an ECC single error.."
|
|
line.long 0x4 "RAMECC_M1SR,RAMECC monitor 1 status register"
|
|
bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW) detected flag" "0: no error detected,1: error detected"
|
|
bitfld.long 0x4 1. "DEDF,ECC double error detected flag" "0: no error detected,1: error detected"
|
|
newline
|
|
bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected flag" "0: no error detected and corrected,1: error detected and corrected"
|
|
rgroup.long 0x28++0xF
|
|
line.long 0x0 "RAMECC_M1FAR,RAMECC monitor 1 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address"
|
|
line.long 0x4 "RAMECC_M1FDRL,RAMECC monitor 1 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low"
|
|
line.long 0x8 "RAMECC_M1FDRH,RAMECC monitor 1 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "FDATAH,Failing data high (64-bit memory)"
|
|
line.long 0xC "RAMECC_M1FECR,RAMECC monitor 1 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "FEC,Failing error code"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "RAMECC_M2CR,RAMECC monitor 2 configuration register"
|
|
bitfld.long 0x0 16.--17. "ECCTEA,ECC Test ECC access" "0: inactive,1: write and read access blocked on data memory,2: write and read access blocked on ECC memory,3: inactive"
|
|
bitfld.long 0x0 8. "ECCDEBWCEN,ECC double error on byte write (BW) counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 7. "ECCDECEN,ECC double error counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
bitfld.long 0x0 6. "ECCSECEN,ECC single error counter enable" "0: no counter increment when an ECC single error..,1: counter increment when an ECC single error occurs"
|
|
newline
|
|
bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0: no error context preserved when an ECC error..,1: error context preserved when an ECC error occurs"
|
|
bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW) interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt enable" "0: no interrupt generated when an ECC single error..,1: interrupt generated when an ECC single error.."
|
|
line.long 0x4 "RAMECC_M2SR,RAMECC monitor 2 status register"
|
|
bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW) detected flag" "0: no error detected,1: error detected"
|
|
bitfld.long 0x4 1. "DEDF,ECC double error detected flag" "0: no error detected,1: error detected"
|
|
newline
|
|
bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected flag" "0: no error detected and corrected,1: error detected and corrected"
|
|
rgroup.long 0x48++0xF
|
|
line.long 0x0 "RAMECC_M2FAR,RAMECC monitor 2 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address"
|
|
line.long 0x4 "RAMECC_M2FDRL,RAMECC monitor 2 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low"
|
|
line.long 0x8 "RAMECC_M2FDRH,RAMECC monitor 2 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "FDATAH,Failing data high (64-bit memory)"
|
|
line.long 0xC "RAMECC_M2FECR,RAMECC monitor 2 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "FEC,Failing error code"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "RAMECC_M3CR,RAMECC monitor 3 configuration register"
|
|
bitfld.long 0x0 16.--17. "ECCTEA,ECC Test ECC access" "0: inactive,1: write and read access blocked on data memory,2: write and read access blocked on ECC memory,3: inactive"
|
|
bitfld.long 0x0 8. "ECCDEBWCEN,ECC double error on byte write (BW) counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 7. "ECCDECEN,ECC double error counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
bitfld.long 0x0 6. "ECCSECEN,ECC single error counter enable" "0: no counter increment when an ECC single error..,1: counter increment when an ECC single error occurs"
|
|
newline
|
|
bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0: no error context preserved when an ECC error..,1: error context preserved when an ECC error occurs"
|
|
bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW) interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt enable" "0: no interrupt generated when an ECC single error..,1: interrupt generated when an ECC single error.."
|
|
line.long 0x4 "RAMECC_M3SR,RAMECC monitor 3 status register"
|
|
bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW) detected flag" "0: no error detected,1: error detected"
|
|
bitfld.long 0x4 1. "DEDF,ECC double error detected flag" "0: no error detected,1: error detected"
|
|
newline
|
|
bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected flag" "0: no error detected and corrected,1: error detected and corrected"
|
|
rgroup.long 0x68++0xF
|
|
line.long 0x0 "RAMECC_M3FAR,RAMECC monitor 3 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address"
|
|
line.long 0x4 "RAMECC_M3FDRL,RAMECC monitor 3 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low"
|
|
line.long 0x8 "RAMECC_M3FDRH,RAMECC monitor 3 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "FDATAH,Failing data high (64-bit memory)"
|
|
line.long 0xC "RAMECC_M3FECR,RAMECC monitor 3 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "FEC,Failing error code"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "RAMECC_M4CR,RAMECC monitor 4 configuration register"
|
|
bitfld.long 0x0 16.--17. "ECCTEA,ECC Test ECC access" "0: inactive,1: write and read access blocked on data memory,2: write and read access blocked on ECC memory,3: inactive"
|
|
bitfld.long 0x0 8. "ECCDEBWCEN,ECC double error on byte write (BW) counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 7. "ECCDECEN,ECC double error counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
bitfld.long 0x0 6. "ECCSECEN,ECC single error counter enable" "0: no counter increment when an ECC single error..,1: counter increment when an ECC single error occurs"
|
|
newline
|
|
bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0: no error context preserved when an ECC error..,1: error context preserved when an ECC error occurs"
|
|
bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW) interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt enable" "0: no interrupt generated when an ECC single error..,1: interrupt generated when an ECC single error.."
|
|
line.long 0x4 "RAMECC_M4SR,RAMECC monitor 4 status register"
|
|
bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW) detected flag" "0: no error detected,1: error detected"
|
|
bitfld.long 0x4 1. "DEDF,ECC double error detected flag" "0: no error detected,1: error detected"
|
|
newline
|
|
bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected flag" "0: no error detected and corrected,1: error detected and corrected"
|
|
rgroup.long 0x88++0xF
|
|
line.long 0x0 "RAMECC_M4FAR,RAMECC monitor 4 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address"
|
|
line.long 0x4 "RAMECC_M4FDRL,RAMECC monitor 4 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low"
|
|
line.long 0x8 "RAMECC_M4FDRH,RAMECC monitor 4 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "FDATAH,Failing data high (64-bit memory)"
|
|
line.long 0xC "RAMECC_M4FECR,RAMECC monitor 4 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "FEC,Failing error code"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RAMECC_M5CR,RAMECC monitor 5 configuration register"
|
|
bitfld.long 0x0 16.--17. "ECCTEA,ECC Test ECC access" "0: inactive,1: write and read access blocked on data memory,2: write and read access blocked on ECC memory,3: inactive"
|
|
bitfld.long 0x0 8. "ECCDEBWCEN,ECC double error on byte write (BW) counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 7. "ECCDECEN,ECC double error counter enable" "0: no counter increment when an ECC double..,1: counter increment when an ECC double detection.."
|
|
bitfld.long 0x0 6. "ECCSECEN,ECC single error counter enable" "0: no counter increment when an ECC single error..,1: counter increment when an ECC single error occurs"
|
|
newline
|
|
bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0: no error context preserved when an ECC error..,1: error context preserved when an ECC error occurs"
|
|
bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW) interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
newline
|
|
bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt enable" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.."
|
|
bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt enable" "0: no interrupt generated when an ECC single error..,1: interrupt generated when an ECC single error.."
|
|
line.long 0x4 "RAMECC_M5SR,RAMECC monitor 5 status register"
|
|
bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW) detected flag" "0: no error detected,1: error detected"
|
|
bitfld.long 0x4 1. "DEDF,ECC double error detected flag" "0: no error detected,1: error detected"
|
|
newline
|
|
bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected flag" "0: no error detected and corrected,1: error detected and corrected"
|
|
rgroup.long 0xA8++0xF
|
|
line.long 0x0 "RAMECC_M5FAR,RAMECC monitor 5 failing address register"
|
|
hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address"
|
|
line.long 0x4 "RAMECC_M5FDRL,RAMECC monitor 5 failing data low register"
|
|
hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low"
|
|
line.long 0x8 "RAMECC_M5FDRH,RAMECC monitor 5 failing data high register"
|
|
hexmask.long 0x8 0.--31. 1. "FDATAH,Failing data high (64-bit memory)"
|
|
line.long 0xC "RAMECC_M5FECR,RAMECC monitor 5 failing ECC error code register"
|
|
hexmask.long 0xC 0.--31. 1. "FEC,Failing error code"
|
|
tree.end
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x58024400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RCC_CR,RCC source control register"
|
|
rbitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked"
|
|
newline
|
|
bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0: PLL3 OFF (default after reset),1: PLL3 ON"
|
|
newline
|
|
rbitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked"
|
|
newline
|
|
bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0: PLL2 OFF (default after reset),1: PLL2 ON"
|
|
newline
|
|
rbitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked"
|
|
newline
|
|
bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0: PLL1 OFF (default after reset),1: PLL1 ON"
|
|
newline
|
|
bitfld.long 0x0 20. "HSECSSON,HSE clock security system enable" "0: CSS on HSE OFF (clock detector OFF) (default..,1: CSS on HSE ON (clock detector ON if the HSE.."
|
|
newline
|
|
bitfld.long 0x0 19. "HSEEXT,external high speed clock type in Bypass mode" "0: HSE in analog mode (default after reset),1: HSE in digital mode"
|
|
newline
|
|
bitfld.long 0x0 18. "HSEBYP,HSE clock bypass" "0: HSE oscillator not bypassed (default after reset),1: HSE oscillator bypassed with an external clock"
|
|
newline
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rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE clock is not ready (default after reset),1: HSE clock is ready"
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bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE is OFF (default after reset),1: HSE is ON"
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rbitfld.long 0x0 13. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 clock is not ready (default after reset),1: HSI48 clock is ready"
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bitfld.long 0x0 12. "HSI48ON,HSI48 clock enable" "0: HSI48 is OFF (default after reset),1: HSI48 is ON"
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bitfld.long 0x0 9. "CSIKERON,CSI clock enable in Stop mode" "0: no effect on CSI (default after reset),1: CSI is forced to ON even in Stop mode"
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rbitfld.long 0x0 8. "CSIRDY,CSI clock ready flag" "0: CSI clock is not ready (default after reset),1: CSI clock is ready"
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bitfld.long 0x0 7. "CSION,CSI clock enable" "0: CSI is OFF (default after reset),1: CSI is ON"
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rbitfld.long 0x0 5. "HSIDIVF,HSI divider flag" "0: new division ratio not yet propagated to..,1: hsi(_ker)_ck clock frequency reflects the new.."
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bitfld.long 0x0 3.--4. "HSIDIV,HSI clock divider" "0: division by 1 hsi(_ker)_ck = 64 MHz (default..,1: division by 2 hsi(_ker)_ck = 32 MHz,2: division by 4 hsi(_ker)_ck = 16 MHz,3: division by 8 hsi(_ker)_ck = 8 MHz"
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rbitfld.long 0x0 2. "HSIRDY,HSI clock ready flag" "0: HSI clock is not ready (default after reset),1: HSI clock is ready"
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bitfld.long 0x0 1. "HSIKERON,HSI clock enable in Stop mode" "0: no effect on HSI (default after reset),1: HSI is forced to ON even in Stop mode"
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bitfld.long 0x0 0. "HSION,HSI clock enable" "0: HSI is OFF,1: HSI is ON (default after reset)"
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line.long 0x4 "RCC_HSICFGR,RCC HSI calibration register"
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hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI clock trimming"
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hexmask.long.word 0x4 0.--11. 1. "HSICAL,HSI clock calibration"
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rgroup.long 0x8++0x3
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line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register"
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hexmask.long.word 0x0 0.--9. 1. "HSI48CAL,Internal RC 48 MHz clock calibration"
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group.long 0xC++0x7
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line.long 0x0 "RCC_CSICFGR,RCC CSI calibration register"
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hexmask.long.byte 0x0 24.--29. 1. "CSITRIM,CSI clock trimming"
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hexmask.long.byte 0x0 0.--7. 1. "CSICAL,CSI clock calibration"
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line.long 0x4 "RCC_CFGR,RCC clock configuration register"
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bitfld.long 0x4 29.--31. "MCO2SEL,microcontroller clock output 2" "0: system clock selected (sys_ck) (default after..,1: PLL2 oscillator clock selected (pll2_p_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_p_ck),4: CSI clock selected (csi_ck),5: LSI clock selected (lsi_ck),?,?"
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hexmask.long.byte 0x4 25.--28. 1. "MCO2PRE,MCO2 prescaler"
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bitfld.long 0x4 22.--24. "MCO1SEL,Microcontroller clock output 1" "0: HSI clock selected (hsi_ck) (default after reset),1: LSE oscillator clock selected (lse_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_q_ck),4: HSI48 clock selected (hsi48_ck),?,?,?"
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hexmask.long.byte 0x4 18.--21. 1. "MCO1PRE,MCO1 prescaler"
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bitfld.long 0x4 15. "TIMPRE,timers clocks prescaler selection" "0: The timers kernel clock is equal to rcc_hclk1 if..,1: The timers kernel clock is equal to rcc_hclk1 if.."
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hexmask.long.byte 0x4 8.--13. 1. "RTCPRE,HSE division factor for RTC clock"
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bitfld.long 0x4 7. "STOPKERWUCK,kernel clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop"
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bitfld.long 0x4 6. "STOPWUCK,system clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop"
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rbitfld.long 0x4 3.--5. "SWS,system clock switch status" "0: HSI used as system clock (hsi_ck) (default after..,1: CSI used as system clock (csi_ck),2: HSE used as system clock (hse_ck),3: PLL1 used as system clock (pll1_p_ck),?,?,?,?"
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bitfld.long 0x4 0.--2. "SW,system clock switch" "0: HSI selected as system clock (hsi_ck) (default..,1: CSI selected as system clock (csi_ck),2: HSE selected as system clock (hse_ck),3: PLL1 selected as system clock (pll1_p_ck),?,?,?,?"
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group.long 0x18++0xB
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line.long 0x0 "RCC_CDCFGR,RCC CPU domain clock configuration register"
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hexmask.long.byte 0x0 0.--3. 1. "CPRE,CPU domain core prescaler"
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line.long 0x4 "RCC_BMCFGR,RCC AHB clock configuration register"
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hexmask.long.byte 0x4 0.--3. 1. "BMPRE,Bus matrix clock prescaler"
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line.long 0x8 "RCC_APBCFGR,RCC APB clocks configuration register"
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bitfld.long 0x8 12.--14. "PPRE5,CPU domain APB5 prescaler" "?,?,?,?,4: rcc_pclk5 = sys_bus_ck / 2,5: rcc_pclk5 = sys_bus_ck / 4,6: rcc_pclk5 = sys_bus_ck / 8,7: rcc_pclk5 = sys_bus_ck / 16"
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bitfld.long 0x8 8.--10. "PPRE4,CPU domain APB4 prescaler" "?,?,?,?,4: rcc_pclk4 = sys_bus_ck / 2,5: rcc_pclk4 = sys_bus_ck / 4,6: rcc_pclk4 = sys_bus_ck / 8,7: rcc_pclk4 = sys_bus_ck / 16"
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bitfld.long 0x8 4.--6. "PPRE2,CPU domain APB2 prescaler" "?,?,?,?,4: rcc_pclk2 = sys_bus_ck / 2,5: rcc_pclk2 = sys_bus_ck / 4,6: rcc_pclk2 = sys_bus_ck / 8,7: rcc_pclk2 = sys_bus_ck / 16"
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bitfld.long 0x8 0.--2. "PPRE1,CPU domain APB1 prescaler" "?,?,?,?,4: rcc_pclk1 = sys_bus_ck / 2,5: rcc_pclk1 = sys_bus_ck / 4,6: rcc_pclk1 = sys_bus_ck / 8,7: rcc_pclk1 = sys_bus_ck / 16"
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group.long 0x28++0x1F
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line.long 0x0 "RCC_PLLCKSELR,RCC PLLs clock source selection register"
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hexmask.long.byte 0x0 20.--25. 1. "DIVM3,prescaler for PLL3"
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hexmask.long.byte 0x0 12.--17. 1. "DIVM2,prescaler for PLL2"
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hexmask.long.byte 0x0 4.--9. 1. "DIVM1,prescaler for PLL1"
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bitfld.long 0x0 0.--1. "PLLSRC,DIVMx and PLLs clock source selection" "0: HSI selected as PLL clock (hsi_ck) (default..,1: CSI selected as PLL clock (csi_ck),2: HSE selected as PLL clock (hse_ck),3: no clock send to DIVMx divider and PLLs"
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line.long 0x4 "RCC_PLLCFGR,RCC PLLs configuration register"
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bitfld.long 0x4 31. "PLL3DIVTEN,PLL3 DIVT divider output enable" "0: pll3_t_ck output disabled (default after reset),1: pll3_t_ck output enabled"
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bitfld.long 0x4 30. "PLL3DIVSEN,PLL3 DIVS divider output enable" "0: pll3_s_ck output disabled (default after reset),1: pll3_s_ck output enabled"
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bitfld.long 0x4 29. "PLL3DIVREN,PLL3 DIVR divider output enable" "0: pll3_r_ck output disabled (default after reset),1: pll3_r_ck output enabled"
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bitfld.long 0x4 28. "PLL3DIVQEN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output disabled (default after reset),1: pll3_q_ck output enabled"
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bitfld.long 0x4 27. "PLL3DIVPEN,PLL3 DIVP divider output enable" "0: pll3_p_ck output disabled (default after reset),1: pll3_p_ck output enabled"
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bitfld.long 0x4 25.--26. "PLL3RGE,PLL3 input frequency range" "0: PLL3 input (ref3_ck) clock range frequency..,1: PLL3 input (ref3_ck) clock range frequency..,2: PLL3 input (ref3_ck) clock range frequency..,3: PLL3 input (ref3_ck) clock range frequency.."
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bitfld.long 0x4 24. "PLL3SSCGEN,PLL3 SSCG enable" "0: SSCG disabled (default after reset),1: SSCG enabled"
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bitfld.long 0x4 23. "PLL3VCOSEL,PLL3 VCO selection" "0: VCOH selected (default after reset),1: VCOL selected"
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bitfld.long 0x4 22. "PLL3FRACLE,PLL3 fractional latch enable" "0,1"
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bitfld.long 0x4 20. "PLL2DIVTEN,PLL2 DIVT divider output enable" "0: pll2_t_ck output disabled (default after reset),1: pll2_t_ck output enabled"
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newline
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bitfld.long 0x4 19. "PLL2DIVSEN,PLL2 DIVS divider output enable" "0: pll2_s_ck output disabled (default after reset),1: pll2_s_ck output enabled"
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newline
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bitfld.long 0x4 18. "PLL2DIVREN,PLL2 DIVR divider output enable" "0: pll2_r_ck output disabled (default after reset),1: pll2_r_ck output enabled"
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newline
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bitfld.long 0x4 17. "PLL2DIVQEN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output disabled (default after reset),1: pll2_q_ck output enabled"
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newline
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bitfld.long 0x4 16. "PLL2DIVPEN,PLL2 DIVP divider output enable" "0: pll2_p_ck output disabled (default after reset),1: pll2_p_ck output enabled"
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newline
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bitfld.long 0x4 14.--15. "PLL2RGE,PLL2 input frequency range" "0: PLL3 input (ref2_ck) clock range frequency..,1: PLL3 input (ref2_ck) clock range frequency..,2: PLL3 input (ref2_ck) clock range frequency..,3: PLL3 input (ref2_ck) clock range frequency.."
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newline
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bitfld.long 0x4 13. "PLL2SSCGEN,PLL2 SSCG enable" "0: SSCG disabled (default after reset),1: SSCG enabled"
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newline
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bitfld.long 0x4 12. "PLL2VCOSEL,PLL2 VCO selection" "0: VCOH selected (default after reset),1: VCOL selected"
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newline
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bitfld.long 0x4 11. "PLL2FRACLE,PLL2 fractional latch enable" "0,1"
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newline
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bitfld.long 0x4 9. "PLL1DIVTEN,PLL1 DIVT divider output enable" "0: pll1_t_ck output disabled (default after reset),1: pll1_t_ck output enabled"
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newline
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bitfld.long 0x4 8. "PLL1DIVSEN,PLL1 DIVS divider output enable" "0: pll1_s_ck output disabled (default after reset),1: pll1_s_ck output enabled"
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newline
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bitfld.long 0x4 7. "PLL1DIVREN,PLL1 DIVR divider output enable" "0: pll1_r_ck output disabled (default after reset),1: pll1_r_ck output enabled"
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newline
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bitfld.long 0x4 6. "PLL1DIVQEN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output disabled (default after reset),1: pll1_q_ck output enabled"
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newline
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bitfld.long 0x4 5. "PLL1DIVPEN,PLL1 DIVP divider output enable" "0: pll1_p_ck output disabled (default after reset),1: pll1_p_ck output enabled"
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newline
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bitfld.long 0x4 3.--4. "PLL1RGE,PLL1 input frequency range" "0: PLL1 input (ref1_ck) clock range frequency..,1: PLL1 input (ref1_ck) clock range frequency..,2: PLL1 input (ref1_ck) clock range frequency..,3: PLL1 input (ref1_ck) clock range frequency.."
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newline
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bitfld.long 0x4 2. "PLL1SSCGEN,PLL1 SSCG enable" "0: SSCG disabled (default after reset),1: SSCG enabled"
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newline
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bitfld.long 0x4 1. "PLL1VCOSEL,PLL1 VCO selection" "0: VCOH selected (default after reset),1: VCOL selected"
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newline
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bitfld.long 0x4 0. "PLL1FRACLE,PLL1 fractional latch enable" "0,1"
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line.long 0x8 "RCC_PLL1DIVR1,RCC PLL1 dividers configuration register 1"
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hexmask.long.byte 0x8 24.--30. 1. "DIVR1,PLL1 DIVR division factor"
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newline
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hexmask.long.byte 0x8 16.--22. 1. "DIVQ,PLL1 DIVQ division factor"
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newline
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hexmask.long.byte 0x8 9.--15. 1. "DIVP,PLL1 DIVP division factor"
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newline
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hexmask.long.word 0x8 0.--8. 1. "DIVN1,multiplication factor for PLL1 VCO"
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line.long 0xC "RCC_PLL1FRACR,RCC PLL1 fractional divider register"
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hexmask.long.word 0xC 3.--15. 1. "FRACN,fractional part of the multiplication factor for PLL1 VCO"
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line.long 0x10 "RCC_PLL2DIVR1,RCC PLL2 dividers configuration register 1"
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hexmask.long.byte 0x10 24.--30. 1. "DIVR2,PLL2 DIVR division factor"
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newline
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hexmask.long.byte 0x10 16.--22. 1. "DIVQ,PLL2 DIVQ division factor"
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newline
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hexmask.long.byte 0x10 9.--15. 1. "DIVP,PLL2 DIVP division factor"
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newline
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hexmask.long.word 0x10 0.--8. 1. "DIVN2,multiplication factor for PLL2 VCO"
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line.long 0x14 "RCC_PLL2FRACR,RCC PLL2 fractional divider register"
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hexmask.long.word 0x14 3.--15. 1. "FRACN,fractional part of the multiplication factor for PLL2 VCO"
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line.long 0x18 "RCC_PLL3DIVR1,RCC PLL3 dividers configuration register 1"
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hexmask.long.byte 0x18 24.--30. 1. "DIVR3,PLL3 DIVR division factor"
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newline
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hexmask.long.byte 0x18 16.--22. 1. "DIVQ,PLL3 DIVQ division factor"
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newline
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hexmask.long.byte 0x18 9.--15. 1. "DIVP,PLL3 DIVP division factor"
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newline
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hexmask.long.word 0x18 0.--8. 1. "DIVN3,Multiplication factor for PLL3 VCO"
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line.long 0x1C "RCC_PLL3FRACR,RCC PLL3 fractional divider register"
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hexmask.long.word 0x1C 3.--15. 1. "FRACN,fractional part of the multiplication factor for PLL3 VCO"
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group.long 0x4C++0xF
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line.long 0x0 "RCC_AHBPERCKSELR,RCC AHB peripheral kernel clock selection register"
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bitfld.long 0x0 28.--29. "CKPERSEL,per_ck clock source selection" "0: hsi_ker_ck selected as per_ck clock (default..,1: csi_ker_ck selected as per_ck clock,2: hse_ker_ck selected as per_ck clock,3: reserved the ck_per clock is disabled"
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bitfld.long 0x0 27. "PSSISEL,PSSI kernel clock source selection" "0: pll3_r_ck selected as kernel peripheral clock..,1: per_ck selected as kernel peripheral clock"
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bitfld.long 0x0 24.--25. "ADCSEL,SAR ADC kernel clock source selection" "0: pll2_p_ck selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: per_ck selected as kernel peripheral clock,?"
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bitfld.long 0x0 20.--22. "ADFSEL,ADF kernel clock source selection" "0: hclk1 selected as ADF kernel clock (default..,1: pll2_p_ck selected as ADF kernel clock,?,?,?,?,?,?"
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bitfld.long 0x0 18. "ETHPHY_CLK_SEL,Clock source selection for external Ethernet PHY" "0: hse_ker_ck selected as clock source (default..,1: pll3_s_ck selected clock source"
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bitfld.long 0x0 16.--17. "ETH1_REF_CLK_SEL,Ethernet reference clock source selection" "0: PAD ETH_RMII_REF_CLK selected as kernel..,1: hse_ker_ck selected as kernel peripheral clock,2: eth_clk_fb selected as kernel peripheral clock,?"
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bitfld.long 0x0 14.--15. "OTGFSSEL,OTGFS kernel clock source selection" "0: hsi48_ker_ck (default after reset),1: pll3_q_ck,2: hse_ker_ck,3: clk48mohci"
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newline
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bitfld.long 0x0 12.--13. "USBPHYCSEL,USBPHYC kernel clock source selection" "0: hse_ker_ck (default after reset),1: hse_ker_ck / 2,2: pll3_q_ck,3: reserved the kernel clock is disabled"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "USBREFCKSEL,USBPHYC kernel clock frequency selection"
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newline
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bitfld.long 0x0 6.--7. "OCTOSPI2SEL,XSPI2 kernel clock source selection" "0: hclk5 selected as kernel peripheral clock..,1: pll2_s_ck selected as kernel peripheral clock,?,?"
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newline
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bitfld.long 0x0 4.--5. "OCTOSPI1SEL,XSPI1 kernel clock source selection" "0: hclk5 selected as kernel peripheral clock..,1: pll2_s_ck selected as kernel peripheral clock,?,?"
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newline
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bitfld.long 0x0 2. "SDMMCSEL,SDMMC1 and SDMMC2 kernel clock source selection" "0: pll2_s_ck selected as kernel peripheral clock..,1: pll2_t_ck selected as kernel peripheral clock"
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bitfld.long 0x0 0.--1. "FMCSEL,FMC kernel clock source selection" "0: hclk5 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock"
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line.long 0x4 "RCC_APB1PERCKSELR,RCC APB1 peripherals kernel clock selection register"
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bitfld.long 0x4 28.--29. "CECSEL,HDMI-CEC kernel clock source selection" "0: lse_ck selected as kernel clock (default after..,1: lsi_ck selected as kernel clock,2: csi_ker_ck divided by 122 selected as kernel clock,3: reserved the kernel clock is disabled"
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bitfld.long 0x4 24.--25. "SPDIFRXSEL,SPDIFRX kernel clock source selection" "0: pll1_q_ck selected as SPDIFRX kernel clock..,1: pll2_r_ck selected as SPDIFRX kernel clock,2: pll3_r_ck selected as SPDIFRX kernel clock,3: hsi_ker_ck selected as SPDIFRX kernel clock"
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bitfld.long 0x4 22.--23. "FDCANSEL,FDCAN kernel clock source selection" "0: hse_ker_ck selected as FDCAN kernel clock..,1: pll1_q_ck selected as FDCAN kernel clock,2: pll2_p_ck selected as FDCAN kernel clock,3: reserved the kernel clock is disabled"
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bitfld.long 0x4 16.--18. "LPTIM1SEL,LPTIM1 kernel clock source selection" "0: pclk1 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?"
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bitfld.long 0x4 12.--13. "I2C1_I3C1SEL,I2C1 or I3C1 kernel clock source selection" "0: pclk1 selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: hsi_ker_ck selected as kernel peripheral clock,3: csi_ker_ck selected as kernel peripheral clock"
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bitfld.long 0x4 8.--9. "I2C23SEL,I2C2 I2C3 kernel clock source selection" "0: pclk1 selected as kernel clock (default after..,1: pll3_r_ck selected as kernel clock,2: hsi_ker_ck selected as kernel clock,3: csi_ker_ck selected as kernel clock"
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bitfld.long 0x4 4.--6. "SPI23SEL,SPI/I2S2 and SPI/I2S3 kernel clock source selection" "0: pll1_q_ck selected as kernel clock (default..,1: pll2_p_ck selected as kernel clock,2: pll3_p_ck selected as kernel clock,3: I2S_CKIN selected as kernel clock,4: per_ck selected as kernel clock,?,?,?"
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newline
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bitfld.long 0x4 0.--2. "UART234578SEL,USART2 3 UART4 5 7 8 (APB1) kernel clock source selection" "0: pclk1 selected as kernel clock (default after..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?"
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line.long 0x8 "RCC_APB2PERCKSELR,RCC APB2 peripherals kernel clock selection register"
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bitfld.long 0x8 20.--22. "SAI2SEL,SAI2 kernel clock source selection" "0: pll1_q_ck selected as SAI2 kernel clock (default..,1: pll2_p_ck selected as SAI2 kernel clock,2: pll3_p_ck selected as SAI2 kernel clock,3: I2S_CKIN selected as SAI2 kernel clock,4: per_ck selected as SAI2 kernel clock,5: spdifrx_symb_ck selected as SAI2 kernel clock,?,?"
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bitfld.long 0x8 16.--18. "SAI1SEL,SAI1 kernel clock source selection" "0: pll1_q_ck selected as SAI1 kernel clock (default..,1: pll2_p_ck selected as SAI1 kernel clock,2: pll3_p_ck selected as SAI1 kernel clock,3: I2S_CKIN selected as SAI1 kernel clock,4: per_ck selected as SAI1 kernel clock,?,?,?"
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bitfld.long 0x8 8.--10. "SPI1SEL,SPI/I2S1 kernel clock source selection" "0: pll1_q_ck selected as SPI/I2S1 and 7 kernel..,1: pll2_p_ck selected as SPI/I2S1 and 7 kernel clock,2: pll3_p_ck selected as SPI/I2S1 and 7 kernel clock,3: I2S_CKIN selected as SPI/I2S1 and 7 kernel clock,4: per_ck selected as SPI/I2S1 and 7 kernel clock,?,?,?"
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newline
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bitfld.long 0x8 4.--6. "SPI45SEL,SPI4 and 5 kernel clock source selection" "0: pclk2 selected as kernel clock (default after..,1: pll2_q_ck is selected as kernel clock,2: pll3_q_ck is selected as kernel clock,3: hsi_ker_ck is selected as kernel clock,4: csi_ker_ck is selected as kernel clock,5: hse_ker_ck is selected as kernel clock,?,?"
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bitfld.long 0x8 0.--2. "USART1SEL,USART1 kernel clock source selection" "0: pclk2 selected as kernel clock (default after..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?"
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line.long 0xC "RCC_APB45PERCKSELR,RCC APB4.5 peripherals kernel clock selection register"
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bitfld.long 0xC 12.--14. "LPTIM45SEL,LPTIM4 and LPTIM5 kernel clock source selection" "0: pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?"
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bitfld.long 0xC 8.--10. "LPTIM23SEL,LPTIM2 and LPTIM3 kernel clock source selection" "0: pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?"
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bitfld.long 0xC 4.--6. "SPI6SEL,SPI/I2S6 kernel clock source selection" "0: pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: hse_ker_ck selected as kernel peripheral clock,?,?"
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bitfld.long 0xC 0.--2. "LPUART1SEL,LPUART1 kernel clock source selection" "0: pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: lse_ck selected as kernel peripheral clock,?,?"
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group.long 0x60++0x3
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line.long 0x0 "RCC_CIER,RCC clock source interrupt enable register"
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bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled"
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bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled"
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bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled"
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bitfld.long 0x0 6. "PLL1RDYIE,PLL1 ready interrupt enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled"
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bitfld.long 0x0 5. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled (default after..,1: HSI48 ready interrupt enabled"
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bitfld.long 0x0 4. "CSIRDYIE,CSI ready interrupt enable" "0: CSI ready interrupt disabled (default after reset),1: CSI ready interrupt enabled"
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bitfld.long 0x0 3. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled"
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bitfld.long 0x0 2. "HSIRDYIE,HSI ready interrupt enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled"
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bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled"
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bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled"
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rgroup.long 0x64++0x3
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line.long 0x0 "RCC_CIFR,RCC clock source interrupt flag register"
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bitfld.long 0x0 10. "HSECSSF,HSE clock security system interrupt flag" "0: no clock security interrupt caused by HSE clock..,1: clock security interrupt caused by HSE clock.."
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bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: no failure detected on the external 32 kHz..,1: failure detected on the external 32 kHz oscillator"
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bitfld.long 0x0 8. "PLL3RDYF,PLL3 ready interrupt flag" "0: no clock ready interrupt caused by PLL3 lock..,1: clock ready interrupt caused by PLL3 lock"
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bitfld.long 0x0 7. "PLL2RDYF,PLL2 ready interrupt flag" "0: no clock ready interrupt caused by PLL2 lock..,1: clock ready interrupt caused by PLL2 lock"
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bitfld.long 0x0 6. "PLL1RDYF,PLL1 ready interrupt flag" "0: no clock ready interrupt caused by PLL1 lock..,1: clock ready interrupt caused by PLL1 lock"
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bitfld.long 0x0 5. "HSI48RDYF,HSI48 ready interrupt flag" "0: no clock ready interrupt caused by the HSI48..,1: clock ready interrupt caused by the HSI48.."
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bitfld.long 0x0 4. "CSIRDYF,CSI ready interrupt flag" "0: no clock ready interrupt caused by the CSI..,1: clock ready interrupt caused by the CSI"
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bitfld.long 0x0 3. "HSERDYF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE"
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bitfld.long 0x0 2. "HSIRDYF,HSI ready interrupt flag" "0: no clock ready interrupt caused by the HSI..,1: clock ready interrupt caused by the HSI"
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bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE"
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bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: no clock ready interrupt caused by the LSI..,1: clock ready interrupt caused by the LSI"
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group.long 0x68++0x3
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line.long 0x0 "RCC_CICR,RCC clock source interrupt clear register"
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bitfld.long 0x0 10. "HSECSSC,HSE clock security system interrupt clear" "0: HSECSSF no effect (default after reset),1: HSECSSF cleared"
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bitfld.long 0x0 9. "LSECSSC,LSE clock security system interrupt clear" "0: LSECSSF no effect (default after reset),1: LSECSSF cleared"
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bitfld.long 0x0 8. "PLL3RDYC,PLL3 ready interrupt clear" "0: PLL3RDYF no effect (default after reset),1: PLL3RDYF cleared"
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bitfld.long 0x0 7. "PLL2RDYC,PLL2 ready interrupt clear" "0: PLL2RDYF no effect (default after reset),1: PLL2RDYF cleared"
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bitfld.long 0x0 6. "PLL1RDYC,PLL1 ready interrupt clear" "0: PLL1RDYF no effect (default after reset),1: PLL1RDYF cleared"
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bitfld.long 0x0 5. "HSI48RDYC,HSI48 ready interrupt clear" "0: HSI48RDYF no effect (default after reset),1: HSI48RDYF cleared"
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bitfld.long 0x0 4. "CSIRDYC,CSI ready interrupt clear" "0: CSIRDYF no effect (default after reset),1: CSIRDYF cleared"
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bitfld.long 0x0 3. "HSERDYC,HSE ready interrupt clear" "0: HSERDYF no effect (default after reset),1: HSERDYF cleared"
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bitfld.long 0x0 2. "HSIRDYC,HSI ready interrupt clear" "0: HSIRDYF no effect (default after reset),1: HSIRDYF cleared"
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bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: LSERDYF no effect (default after reset),1: LSERDYF cleared"
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bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: LSIRDYF no effect (default after reset),1: LSIRDYF cleared"
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group.long 0x70++0x7
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line.long 0x0 "RCC_BDCR,RCC Backup domain control register"
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bitfld.long 0x0 16. "VSWRST,VSwitch domain software reset" "0: reset not activated (default after Backup domain..,1: generates a reset pulse resetting the entire VSW.."
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bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: rtc_ck disabled (default after Backup domain..,1: rtc_ck enabled"
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bitfld.long 0x0 12. "LSECSSRA,Re-Arm the LSECSS function" "0: Writing 0 has no effect (default after Backup..,1: Writing 1 generates a re-arm pulse for the.."
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bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: no clock (default after Backup domain reset),1: LSE selected as RTC clock,2: LSI selected as RTC clock,3: HSE divided by RTCPRE value selected as RTC clock"
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bitfld.long 0x0 7. "LSEEXT,low-speed external clock type in Bypass mode" "0: LSE in analog mode (default after Backup domain..,1: LSE in digital mode (do not use if RTC is active)."
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rbitfld.long 0x0 6. "LSECSSD,LSE clock security system failure detection" "0: no failure detected on 32 kHz oscillator..,1: failure detected on 32 kHz oscillator"
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bitfld.long 0x0 5. "LSECSSON,LSE clock security system enable" "0: CSS on 32 kHz oscillator OFF (default after..,1: CSS on 32 kHz oscillator ON"
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bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator driving capability" "0: lowest drive (default after Backup domain reset),1: medium-low drive,2: medium-high drive,3: highest drive"
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bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed (default after..,1: LSE oscillator bypassed"
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rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready (default after Backup..,1: LSE oscillator ready"
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bitfld.long 0x0 0. "LSEON,LSE oscillator enabled" "0: LSE oscillator OFF (default after Backup domain..,1: LSE oscillator ON"
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line.long 0x4 "RCC_CSR,RCC clock control and status register"
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rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: LSI clock is not ready (default after reset),1: LSI clock is ready"
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bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: LSI is OFF (default after reset),1: LSI is ON"
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group.long 0x7C++0x23
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line.long 0x0 "RCC_AHB5RSTR,RCC AHB5 peripheral reset register"
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bitfld.long 0x0 20. "GPURST,GPU block reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 19. "GFXMMURST,GFXMMU block reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 14. "IOMNGRRST,XSPIM reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 12. "XSPI2RST,XSPI2 and MCE2 blocks reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 8. "SDMMC1RST,SDMMC1 and DB_SDMMC1 blocks reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 5. "XSPI1RST,XSPI1 and MCE1 blocks reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 4. "FMCRST,FMC and MCE3 blocks reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 3. "JPEGRST,JPEG block reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 1. "DMA2DRST,DMA2D block reset" "0: reset is released (default after reset),1: reset is asserted"
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bitfld.long 0x0 0. "HPDMA1RST,HPDMA1 block reset" "0: reset is released (default after reset),1: reset is asserted"
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line.long 0x4 "RCC_AHB1RSTR,RCC AHB1 peripheral reset register"
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bitfld.long 0x4 31. "ADFRST,ADF block reset" "0: does not reset ADF block (default after reset),1: resets ADF block"
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bitfld.long 0x4 27. "OTGFSRST,OTGFS block reset" "0: does not reset OTGFS block (default after reset),1: resets OTGFS block"
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bitfld.long 0x4 26. "USBPHYCRST,USBPHYC block reset" "0: does not reset USBPHYC block (default after reset),1: resets USBPHYC block"
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bitfld.long 0x4 25. "OTGHSRST,OTGHS block reset" "0: does not reset OTGHS block (default after reset),1: resets OTGHS block"
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bitfld.long 0x4 15. "ETH1RST,ETH1 block reset" "0: does not reset ETH1 block (default after reset),1: resets ETH1 block"
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bitfld.long 0x4 5. "ADC12RST,ADC1 and 2 blocks reset" "0: does not reset ADC1 and 2 blocks (default after..,1: resets ADC1 and 2 blocks"
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bitfld.long 0x4 4. "GPDMA1RST,GPDMA1 blocks reset" "0: does not reset GPDMA1 block (default after reset),1: resets GPDMA1 block"
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line.long 0x8 "RCC_AHB2RSTR,RCC AHB2 peripheral reset register"
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bitfld.long 0x8 14. "CORDICRST,CORDIC reset" "0: does not reset CORDIC block (default after reset),1: resets CORDIC block"
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bitfld.long 0x8 9. "SDMMC2RST,SDMMC2 and SDMMC2 delay blocks reset" "0: does not reset SDMMC2 and SDMMC2 delay blocks..,1: resets SDMMC2 and SDMMC2 delay blocks"
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bitfld.long 0x8 1. "PSSIRST,PSSI block reset" "0: does not reset PSSI block (default after reset),1: resets PSSI block"
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line.long 0xC "RCC_AHB4RSTR,RCC AHB4 peripheral reset register"
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bitfld.long 0xC 19. "CRCRST,CRC block reset" "0: does not reset the CRC block (default after reset),1: resets the CRC block"
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bitfld.long 0xC 15. "GPIOPRST,GPIOP block reset" "0: does not reset the GPIOP block (default after..,1: resets the GPIOP block"
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bitfld.long 0xC 14. "GPIOORST,GPIOO block reset" "0: does not reset the GPIOO block (default after..,1: resets the GPIOO block"
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bitfld.long 0xC 13. "GPIONRST,GPION block reset" "0: does not reset the GPION block (default after..,1: resets the GPION block"
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bitfld.long 0xC 12. "GPIOMRST,GPIOM block reset" "0: does not reset the GPIOM block (default after..,1: resets the GPIOM block"
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bitfld.long 0xC 7. "GPIOHRST,GPIOH block reset" "0: does not reset the GPIOH block (default after..,1: resets the GPIOH block"
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bitfld.long 0xC 6. "GPIOGRST,GPIOG block reset" "0: does not reset the GPIOG block (default after..,1: resets the GPIOG block"
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bitfld.long 0xC 5. "GPIOFRST,GPIOF block reset" "0: does not reset the GPIOF block (default after..,1: resets the GPIOF block"
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bitfld.long 0xC 4. "GPIOERST,GPIOE block reset" "0: does not reset the GPIOE block (default after..,1: resets the GPIOE block"
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bitfld.long 0xC 3. "GPIODRST,GPIOD block reset" "0: does not reset the GPIOD block (default after..,1: resets the GPIOD block"
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bitfld.long 0xC 2. "GPIOCRST,GPIOC block reset" "0: does not reset the GPIOC block (default after..,1: resets the GPIOC block"
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newline
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bitfld.long 0xC 1. "GPIOBRST,GPIOB block reset" "0: does not reset the GPIOB block (default after..,1: resets the GPIOB block"
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bitfld.long 0xC 0. "GPIOARST,GPIOA block reset" "0: does not reset the GPIOA block (default after..,1: resets the GPIOA block"
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line.long 0x10 "RCC_APB5RSTR,RCC APB5 peripheral reset register"
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bitfld.long 0x10 4. "GFXTIMRST,GFXTIM block reset" "0: does not reset the GFXTIM block (default after..,1: resets the GFXTIM block"
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bitfld.long 0x10 2. "DCMIPPRST,DCMIPP block reset" "0: does not reset the DCMIPP block (default after..,1: resets the DCMIPP block"
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bitfld.long 0x10 1. "LTDCRST,LTDC block reset" "0: does not reset the LTDC block (default after..,1: resets the LTDC block"
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line.long 0x14 "RCC_APB1RSTR1,RCC APB1 peripheral reset register 1"
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bitfld.long 0x14 31. "UART8RST,UART8 block reset" "0: does not reset the UART8 block (default after..,1: resets the UART8 block"
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bitfld.long 0x14 30. "UART7RST,UART7 block reset" "0: does not reset the UART7 block (default after..,1: resets the UART7 block"
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bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0: does not reset the HDMI-CEC block (default after..,1: resets the HDMI-CEC block"
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bitfld.long 0x14 23. "I2C3RST,I2C3 block reset" "0: does not reset the I2C3 block (default after..,1: resets the I2C3 block"
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bitfld.long 0x14 22. "I2C2RST,I2C2 block reset" "0: does not reset the I2C2 block (default after..,1: resets the I2C2 block"
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bitfld.long 0x14 21. "I2C1_I3C1RST,I2C1/I3C1 block reset" "0: does not reset the I2C1/I3C1 block (default..,1: resets the I2C1/I3C1 block"
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bitfld.long 0x14 20. "UART5RST,UART5 block reset" "0: does not reset the UART5 block (default after..,1: resets the UART5 block"
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bitfld.long 0x14 19. "UART4RST,UART4 block reset" "0: does not reset the UART4 block (default after..,1: resets the UART4 block"
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bitfld.long 0x14 18. "USART3RST,USART3 block reset" "0: does not reset the USART3 block (default after..,1: resets the USART3 block"
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bitfld.long 0x14 17. "USART2RST,USART2 block reset" "0: does not reset the USART2 block (default after..,1: resets the USART2 block"
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bitfld.long 0x14 16. "SPDIFRXRST,SPDIFRX block reset" "0: does not reset the SPDIFRX block (default after..,1: resets the SPDIFRX block"
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bitfld.long 0x14 15. "SPI3RST,SPI2S3 block reset" "0: does not reset the SPI2S3 block (default after..,1: resets the SPI2S3 block"
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bitfld.long 0x14 14. "SPI2RST,SPI2S2 block reset" "0: does not reset the SPI2S2 block (default after..,1: resets the SPI2S2 block"
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bitfld.long 0x14 9. "LPTIM1RST,LPTIM1 block reset" "0: does not reset the LPTIM1 block (default after..,1: resets the LPTIM1 block"
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bitfld.long 0x14 8. "TIM14RST,TIM14 block reset" "0: does not reset the TIM14 block (default after..,1: resets the TIM14 block"
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bitfld.long 0x14 7. "TIM13RST,TIM13 block reset" "0: does not reset the TIM13 block (default after..,1: resets the TIM13 block"
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bitfld.long 0x14 6. "TIM12RST,TIM12 block reset" "0: does not reset the TIM12 block (default after..,1: resets the TIM12 block"
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bitfld.long 0x14 5. "TIM7RST,TIM7 block reset" "0: does not reset the TIM7 block (default after..,1: resets the TIM7 block"
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bitfld.long 0x14 4. "TIM6RST,TIM6 block reset" "0: does not reset the TIM6 block (default after..,1: resets the TIM6 block"
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bitfld.long 0x14 3. "TIM5RST,TIM5 block reset" "0: does not reset the TIM5 block (default after..,1: resets the TIM5 block"
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bitfld.long 0x14 2. "TIM4RST,TIM4 block reset" "0: does not reset the TIM4 block (default after..,1: resets the TIM4 block"
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bitfld.long 0x14 1. "TIM3RST,TIM3 block reset" "0: does not reset the TIM3 block (default after..,1: resets the TIM3 block"
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bitfld.long 0x14 0. "TIM2RST,TIM2 block reset" "0: does not reset the TIM2 block (default after..,1: resets the TIM2 block"
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line.long 0x18 "RCC_APB1RSTR2,RCC APB1 peripheral reset register 2"
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bitfld.long 0x18 27. "UCPDRST,UCPD block reset" "0: does not reset the UCPD block (default after..,1: resets the UCPD block"
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bitfld.long 0x18 8. "FDCANRST,FDCAN block reset" "0: does not reset the FDCAN block (default after..,1: resets the FDCAN block"
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bitfld.long 0x18 5. "MDIOSRST,MDIOS block reset" "0: does not reset the MDIOS block (default after..,1: resets the MDIOS block"
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bitfld.long 0x18 1. "CRSRST,clock recovery system reset" "0: does not reset CRS (default after reset),1: resets CRS"
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line.long 0x1C "RCC_APB2RSTR,RCC APB2 peripheral reset register"
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bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0: does not reset the SAI2 (default after reset),1: resets the SAI2"
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newline
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bitfld.long 0x1C 22. "SAI1RST,SAI1 block reset" "0: does not reset the SAI1 (default after reset),1: resets the SAI1"
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newline
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bitfld.long 0x1C 20. "SPI5RST,SPI5 block reset" "0: does not reset the SPI5 block (default after..,1: resets the SPI5 block"
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bitfld.long 0x1C 19. "TIM9RST,TIM9 block reset" "0: does not reset the TIM9 block (default after..,1: resets the TIM9 block"
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bitfld.long 0x1C 18. "TIM17RST,TIM17 block reset" "0: does not reset the TIM17 block (default after..,1: resets the TIM17 block"
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bitfld.long 0x1C 17. "TIM16RST,TIM16 block reset" "0: does not reset the TIM16 block (default after..,1: resets the TIM16 block"
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bitfld.long 0x1C 16. "TIM15RST,TIM15 block reset" "0: does not reset the TIM15 block (default after..,1: resets the TIM15 block"
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bitfld.long 0x1C 13. "SPI4RST,SPI4 block reset" "0: does not reset the SPI4 block (default after..,1: resets the SPI4 block"
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newline
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bitfld.long 0x1C 12. "SPI1RST,SPI2S1 block reset" "0: does not reset the SPI2S1 block (default after..,1: resets the SPI2S1 block"
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bitfld.long 0x1C 4. "USART1RST,USART1 block reset" "0: does not reset the USART1 block (default after..,1: resets the USART1 block"
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newline
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bitfld.long 0x1C 0. "TIM1RST,TIM1 block reset" "0: does not reset the TIM1 block (default after..,1: resets the TIM1 block"
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line.long 0x20 "RCC_APB4RSTR,RCC APB4 peripheral reset register"
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bitfld.long 0x20 26. "TMPSENSRST,TMPSENS block reset" "0: does not reset the TMPSENS block (default after..,1: resets the TMPSENS block"
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bitfld.long 0x20 15. "VREFRST,VREF block reset" "0: does not reset the VREF block (default after..,1: resets the VREF block"
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bitfld.long 0x20 12. "LPTIM5RST,LPTIM5 block reset" "0: does not reset the LPTIM5 block (default after..,1: resets the LPTIM5 block"
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bitfld.long 0x20 11. "LPTIM4RST,LPTIM4 block reset" "0: does not reset the LPTIM4 block (default after..,1: resets the LPTIM4 block"
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bitfld.long 0x20 10. "LPTIM3RST,LPTIM3 block reset" "0: does not reset the LPTIM3 block (default after..,1: resets the LPTIM3 block"
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bitfld.long 0x20 9. "LPTIM2RST,LPTIM2 block reset" "0: does not reset the LPTIM2 block (default after..,1: resets the LPTIM2 block"
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bitfld.long 0x20 5. "SPI6RST,SPI/I2S6 block reset" "0: does not reset the SPI/I2S6 block (default after..,1: resets the SPI/I2S6 block"
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bitfld.long 0x20 3. "LPUART1RST,LPUART1 block reset" "0: does not reset the LPUART1 block (default after..,1: resets the LPUART1 block"
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newline
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bitfld.long 0x20 1. "SBSRST,SBS block reset" "0: does not reset the SBS block (default after reset),1: resets the SBS block"
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group.long 0xA4++0x3
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line.long 0x0 "RCC_AHB3RSTR,RCC AHB3 peripheral reset register"
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bitfld.long 0x0 6. "PKARST,PKA block reset" "0: does not reset PKA block (default after reset),1: resets PKA block"
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bitfld.long 0x0 4. "SAESRST,SAES block reset" "0: does not reset SAES block (default after reset),1: resets SAES block"
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newline
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bitfld.long 0x0 2. "CRYPRST,CRYP block reset" "0: does not reset CRYP block (default after reset),1: resets CRYP block"
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newline
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bitfld.long 0x0 1. "HASHRST,HASH block reset" "0: does not reset HASH block (default after reset),1: resets HASH block"
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bitfld.long 0x0 0. "RNGRST,random number generator block reset" "0: does not reset RNG block (default after reset),1: resets RNG block"
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group.long 0xB0++0x3
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line.long 0x0 "RCC_CKGDISR,RCC AXI clocks gating disable register"
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bitfld.long 0x0 31. "JTAGCKG,JTAG automatic clock gating disabling" "0: The clock gating is enabled. The clock is..,?"
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bitfld.long 0x0 30. "EXTICKG,EXTI clock gating disable" "0: The clock gating is enabled. The clock is..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 21. "FLITFCKG,AXI slave Flash interface (FLIFT) clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 20. "AXIRAM1CKG,AXI slave SRAM1 / error code correction (ECC) clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 19. "AXIRAM2CKG,AXI slave SRAM2 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 18. "AXIRAM3CKG,AXI matrix slave SRAM3 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 17. "AXIRAM4CKG,AXI matrix slave SRAM4 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 16. "XSPI2CKG,AXI slave XSPI2 and MCE2 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 15. "XSPI1CKG,AXI slave XSPI1 and MCE1 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 14. "FMCCKG,AXI slave FMC and MCE3 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 13. "AHBSCKG,AXI slave AHB clock gating disable" "0: The clock gating is enabled. The AXI matrix..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 12. "GFXMMUMCKG,AXI master GFXMMU clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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bitfld.long 0x0 11. "LTDCCKG,AXI master LTDC clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 10. "GFXMMUSCKG,AXI matrix slave GFXMMU clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 9. "DMA2DCKG,AXI master DMA2D clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 8. "DCMIPPCKG,AXI master DCMIPP clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 7. "GPUCLCKG,AXI master cache GPU clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 6. "GPUS1CKG,AXI master 1 GPU clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 5. "GPUS0CKG,AXI master 0 GPU clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 4. "CPUCKG,AXI master CPU clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 3. "HPDMA1CKG,AXI master HPDMA1 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 2. "SDMMC1CKG,AXI master SDMMC1 clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 1. "AHBMCKG,AXI master AHB clock gating disable" "0: The clock gating is enabled. The clock of the..,1: The clock gating is disabled. The clock is.."
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newline
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bitfld.long 0x0 0. "AXICKG,AXI interconnect matrix clock gating disable" "0: The clock gating is enabled. The AXI..,1: The clock gating is disabled. The clock is.."
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group.long 0xC0++0x17
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line.long 0x0 "RCC_PLL1DIVR2,RCC PLL1 dividers configuration register 2"
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bitfld.long 0x0 8.--10. "DIVT,PLL1 DIVT division factor" "0: pll1_t_ck = vco1_ck,1: pll1_t_ck = vco1_ck / 2 (default after reset),2: pll1_t_ck = vco1_ck / 3,3: pll1_t_ck = vco1_ck / 4,4: pll1_t_ck = vco1_ck / 5,5: pll1_t_ck = vco1_ck / 6,6: pll1_t_ck = vco1_ck / 7,7: pll1_t_ck = vco1_ck / 8"
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newline
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bitfld.long 0x0 0.--2. "DIVS,PLL1 DIVS division factor" "0: pll1_s_ck = vco1_ck,1: pll1_s_ck = vco1_ck / 2 (default after reset),2: pll1_s_ck = vco1_ck / 3,3: pll1_s_ck = vco1_ck / 4,4: pll1_s_ck = vco1_ck / 5,5: pll1_s_ck = vco1_ck / 6,6: pll1_s_ck = vco1_ck / 7,7: pll1_s_ck = vco1_ck / 8"
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line.long 0x4 "RCC_PLL2DIVR2,RCC PLL2 dividers configuration register 2"
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bitfld.long 0x4 8.--10. "DIVT,PLL2 DIVT division factor" "0: pll2_t_ck = vco2_ck,1: pll2_t_ck = vco2_ck / 2 (default after reset),2: pll2_t_ck = vco2_ck / 3,3: pll2_t_ck = vco2_ck / 4,4: pll2_t_ck = vco2_ck / 5,5: pll2_t_ck = vco2_ck / 6,6: pll2_t_ck = vco2_ck / 7,7: pll2_t_ck = vco2_ck / 8"
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newline
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bitfld.long 0x4 0.--2. "DIVS,PLL2 DIVS division factor" "0: pll2_s_ck = vco2_ck,1: pll2_s_ck = vco2_ck / 2 (default after reset),2: pll2_s_ck = vco2_ck / 3,3: pll2_s_ck = vco2_ck / 4,4: pll2_s_ck = vco2_ck / 5,5: pll2_s_ck = vco2_ck / 6,6: pll2_s_ck = vco2_ck / 7,7: pll2_s_ck = vco2_ck / 8"
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line.long 0x8 "RCC_PLL3DIVR2,RCC PLL3 dividers configuration register 2"
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bitfld.long 0x8 8.--10. "DIVT,PLL3 DIVT division factor" "0: pll3_t_ck = vco3_ck,1: pll3_t_ck = vco3_ck / 2 (default after reset),2: pll3_t_ck = vco3_ck / 3,3: pll3_t_ck = vco3_ck / 4,4: pll3_t_ck = vco3_ck / 5,5: pll3_t_ck = vco3_ck / 6,6: pll3_t_ck = vco3_ck / 7,7: pll3_t_ck = vco3_ck / 8"
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newline
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bitfld.long 0x8 0.--2. "DIVS,PLL3 DIVS division factor" "0: pll3_s_ck = vco3_ck,1: pll3_s_ck = vco3_ck / 2 (default after reset),2: pll3_s_ck = vco3_ck / 3,3: pll3_s_ck = vco3_ck / 4,4: pll3_s_ck = vco3_ck / 5,5: pll3_s_ck = vco3_ck / 6,6: pll3_s_ck = vco3_ck / 7,7: pll3_s_ck = vco3_ck / 8"
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line.long 0xC "RCC_PLL1SSCGR,RCC PLL1 Spread Spectrum Clock Generator register"
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hexmask.long.word 0xC 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL1"
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newline
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bitfld.long 0xC 15. "DWNSPREAD1,Spread spectrum clock generator mode for PLL1" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected"
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newline
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bitfld.long 0xC 14. "RPDFN_DIS1,Dithering RPDF noise control for PLL1" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled"
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newline
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bitfld.long 0xC 13. "TPDFN_DIS1,Dithering TPDF noise control for PLL1" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled"
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newline
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hexmask.long.word 0xC 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL1"
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line.long 0x10 "RCC_PLL2SSCGR,RCC PLL2 Spread Spectrum Clock Generator register"
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hexmask.long.word 0x10 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL2"
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newline
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bitfld.long 0x10 15. "DWNSPREAD2,Spread spectrum clock generator mode for PLL2" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected"
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newline
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bitfld.long 0x10 14. "RPDFN_DIS2,Dithering RPDF noise control for PLL2" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled"
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newline
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bitfld.long 0x10 13. "TPDFN_DIS2,Dithering TPDF noise control for PLL2" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled"
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newline
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hexmask.long.word 0x10 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL2"
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line.long 0x14 "RCC_PLL3SSCGR,RCC PLL3 Spread Spectrum Clock Generator register"
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hexmask.long.word 0x14 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL3"
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newline
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bitfld.long 0x14 15. "DWNSPREAD3,Spread spectrum clock generator mode for PLL3" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected"
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newline
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bitfld.long 0x14 14. "RPDFN_DIS3,Dithering RPDF noise control for PLL3" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled"
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newline
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bitfld.long 0x14 13. "TPDFN_DIS3,Dithering TPDF noise control for PLL3" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled"
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newline
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hexmask.long.word 0x14 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL3"
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group.long 0x100++0x3
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line.long 0x0 "RCC_CKPROTR,RCC clock protection register"
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rbitfld.long 0x0 12.--14. "FMCSWP,FMC kernel clock switch position" "0: The switch is in neutral mode and output clock..,1: The switch is selecting hclk5,2: The switch is selecting pll1_q_ck,3: The switch is selecting pll2_r_ck,4: The switch is selecting hsi_ker_ck,5: The switch is in recovery position (hclk5/4),?,?"
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newline
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rbitfld.long 0x0 8.--10. "XSPI2SWP,XSPI2 kernel clock switch position" "0: The switch is in neutral mode and output clock..,1: The switch is selecting hclk5,2: The switch is selecting pll2_s_ck,3: The switch is selecting pll2_t_ck,4: The switch is in recovery position (hclk5/4),?,?,?"
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newline
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rbitfld.long 0x0 4.--6. "XSPI1SWP,XSPI1 kernel clock switch position" "0: The switch is in neutral mode and output clock..,1: The switch is selecting hclk5,2: The switch is selecting pll2_s_ck,3: The switch is selecting pll2_t_ck,4: The switch is in recovery position (hclk5/4),?,?,?"
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newline
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bitfld.long 0x0 1. "FMCCKP,FMC clock protection" "0: Clock protection is disabled (default after reset),1: PLL1ON"
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newline
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bitfld.long 0x0 0. "XSPICKP,XSPI clock protection" "0: Clock protection is disabled (default after reset),1: PLL2ON"
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group.long 0x130++0x53
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line.long 0x0 "RCC_RSR,RCC Reset status register"
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rbitfld.long 0x0 30. "LPWRRSTF,reset due to illegal Stop or Standby flag" "0: no illegal reset occurred (default after..,1: illegal Stop or Standby reset occurred"
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newline
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rbitfld.long 0x0 28. "WWDGRSTF,window watchdog reset flag <sup>(1)</sup>" "0: no window watchdog reset occurred from WWDG..,1: window watchdog reset occurred from WWDG"
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newline
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rbitfld.long 0x0 26. "IWDGRSTF,independent watchdog reset flag <sup>(1)</sup>" "0: no independent watchdog reset occurred (default..,1: independent watchdog reset occurred"
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newline
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rbitfld.long 0x0 24. "SFTRSTF,system reset from CPU reset flag <sup>(1)</sup>" "0: no CPU software reset occurred (default after..,1: a system reset has been generated by the CPU"
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newline
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rbitfld.long 0x0 23. "PORRSTF,POR/PDR reset flag <sup>(1)</sup>" "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.."
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newline
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rbitfld.long 0x0 22. "PINRSTF,pin reset flag (NRST) <sup>(1)</sup>" "0: no reset from pin occurred,1: reset from pin occurred (default after power-on.."
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newline
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rbitfld.long 0x0 21. "BORRSTF,BOR reset flag <sup>(1)</sup>" "0: no BOR reset occurred,1: BOR reset occurred (default after power-on reset)"
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newline
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rbitfld.long 0x0 17. "OBLRSTF,Option byte loading reset flag <sup>(1)</sup>" "0: No reset from option byte loading occurred,1: Reset from option byte loading occurred"
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newline
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bitfld.long 0x0 16. "RMVF,remove reset flag" "0: reset of the reset flags not activated (default..,1: resets the value of the reset flags"
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line.long 0x4 "RCC_AHB5ENR,RCC AHB5 clock enable register"
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bitfld.long 0x4 20. "GPUEN,GPU peripheral clock enable" "0: GPU peripheral clock disabled (default after..,1: GPU peripheral clock enabled"
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newline
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bitfld.long 0x4 19. "GFXMMUEN,GFXMMU peripheral clock enable" "0: GFXMMU peripheral clock disabled (default after..,1: GFXMMU peripheral clock enabled"
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newline
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bitfld.long 0x4 14. "IOMNGREN,XSPIM peripheral clock enable" "0: XSPIM peripheral clock disabled (default after..,1: XSPIM peripheral clock enabled"
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newline
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bitfld.long 0x4 12. "XSPI2EN,XSPI2 and MCE2 peripheral clocks enable" "0: XSPI2 and MCE2 peripheral clocks disabled..,1: XSPI2 and MCE2 peripheral clocks enabled"
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newline
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bitfld.long 0x4 8. "SDMMC1EN,SDMMC1 and DB_SDMMC1 peripheral clocks enable" "0: SDMMC1 and DB_SDMMC1 peripheral clocks disabled..,1: SDMMC1 and DB_SDMMC1 peripheral clocks enabled"
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newline
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bitfld.long 0x4 5. "XSPI1EN,XSPI1 and MCE1 peripheral clocks enable" "0: XSPI1 and MCE1 peripheral clocks disabled..,1: XSPI1 and MCE1 peripheral clocks enabled"
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newline
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bitfld.long 0x4 4. "FMCEN,FMC and MCE3 peripheral clocks enable" "0: FMC and MCE3 peripheral clocks disabled (default..,1: FMC and MCE3 peripheral clocks enabled"
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newline
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bitfld.long 0x4 3. "JPEGEN,JPEG peripheral clock enable" "0: JPEG peripheral clock disabled (default after..,1: JPEG peripheral clock enabled"
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newline
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bitfld.long 0x4 1. "DMA2DEN,DMA2D peripheral clock enable" "0: DMA2D peripheral clock disabled (default after..,1: DMA2D peripheral clock enabled"
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newline
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bitfld.long 0x4 0. "HPDMA1EN,HPDMA1 peripheral clock enable" "0: HPDMA1 peripheral clock disabled (default after..,1: HPDMA1 peripheral clock enabled"
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line.long 0x8 "RCC_AHB1ENR,RCC AHB1 clock enable register"
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bitfld.long 0x8 31. "ADFEN,ADF clocks enable" "0: ADF clocks disabled (default after reset),1: ADF clocks enabled"
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newline
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bitfld.long 0x8 27. "OTGFSEN,OTGFS peripheral clocks enable" "0: OTGFS peripheral clocks disabled (default after..,1: OTGFS peripheral clocks enabled"
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newline
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bitfld.long 0x8 26. "USBPHYCEN,USBPHYC clocks enable" "0: USBPHYC clocks disabled (default after reset),1: USBPHYC clocks enabled"
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newline
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bitfld.long 0x8 25. "OTGHSEN,OTGHS clocks enable" "0: OTGHS clocks disabled (default after reset),1: OTGHS clocks enabled"
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newline
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bitfld.long 0x8 17. "ETH1RXEN,ETH1 reception clock enable" "0: ETH1 reception clock disabled (default after..,1: ETH1 reception clock enabled"
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newline
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bitfld.long 0x8 16. "ETH1TXEN,ETH1 transmission clock enable" "0: ETH1 transmission clock disabled (default after..,1: ETH1 transmission clock enabled"
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newline
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bitfld.long 0x8 15. "ETH1MACEN,ETH1 MAC peripheral clock enable" "0: ETH1 MAC peripheral clock disabled (default..,1: ETH1 MAC peripheral clock enabled"
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newline
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bitfld.long 0x8 5. "ADC12EN,ADC1 and 2 peripheral clocks enable" "0: ADC1 and 2 peripheral clocks disabled (default..,1: ADC1 and 2 peripheral clocks enabled"
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newline
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bitfld.long 0x8 4. "GPDMA1EN,GPDMA1 clock enable" "0: GPDMA1 clock disabled (default after reset),1: GPDMA1 clock enabled"
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line.long 0xC "RCC_AHB2ENR,RCC AHB2 clock enable register"
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bitfld.long 0xC 30. "SRAM2EN,SRAM2 clock enable" "0: SRAM2 clock disabled (default after reset),1: SRAM2 clock enabled"
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bitfld.long 0xC 29. "SRAM1EN,SRAM1 clock enable" "0: SRAM1 clock disabled (default after reset),1: SRAM1 clock enabled"
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bitfld.long 0xC 14. "CORDICEN,CORDIC clock enable" "0: CORDIC clock disabled (default after reset),1: CORDIC clock enabled"
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bitfld.long 0xC 9. "SDMMC2EN,SDMMC2 and SDMMC2 delay clock enable" "0: SDMMC2 and SDMMC2 delay clock disabled (default..,1: SDMMC2 and SDMMC2 delay clock enabled"
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bitfld.long 0xC 1. "PSSIEN,PSSI peripheral clocks enable" "0: PSSI peripheral clocks disabled (default after..,1: PSSI peripheral clocks enabled:"
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line.long 0x10 "RCC_AHB4ENR,RCC AHB4 clock enable register"
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bitfld.long 0x10 28. "BKPRAMEN,Backup RAM clock enable" "0: Backup RAM clock disabled (default after reset),1: Backup RAM clock enabled"
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bitfld.long 0x10 19. "CRCEN,CRC clock enable" "0: CRC clock disabled (default after reset),1: CRC clock enabled"
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bitfld.long 0x10 15. "GPIOPEN,GPIOP peripheral clock enable" "0: GPIOP peripheral clock disabled (default after..,1: GPIOP peripheral clock enabled"
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bitfld.long 0x10 14. "GPIOOEN,GPIOO peripheral clock enable" "0: GPIOO peripheral clock disabled (default after..,1: GPIOO peripheral clock enabled"
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bitfld.long 0x10 13. "GPIONEN,GPION peripheral clock enable" "0: GPION peripheral clock disabled (default after..,1: GPION peripheral clock enabled"
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bitfld.long 0x10 12. "GPIOMEN,GPIOM peripheral clock enable" "0: GPIOM peripheral clock disabled (default after..,1: GPIOM peripheral clock enabled"
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bitfld.long 0x10 7. "GPIOHEN,GPIOH peripheral clock enable" "0: GPIOH peripheral clock disabled (default after..,1: GPIOH peripheral clock enabled"
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bitfld.long 0x10 6. "GPIOGEN,GPIOG peripheral clock enable" "0: GPIOG peripheral clock disabled (default after..,1: GPIOG peripheral clock enabled"
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bitfld.long 0x10 5. "GPIOFEN,GPIOF peripheral clock enable" "0: GPIOF peripheral clock disabled (default after..,1: GPIOF peripheral clock enabled"
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bitfld.long 0x10 4. "GPIOEEN,GPIOE peripheral clock enable" "0: GPIOE peripheral clock disabled (default after..,1: GPIOE peripheral clock enabled"
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bitfld.long 0x10 3. "GPIODEN,GPIOD peripheral clock enable" "0: GPIOD peripheral clock disabled (default after..,1: GPIOD peripheral clock enabled"
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bitfld.long 0x10 2. "GPIOCEN,GPIOC peripheral clock enable" "0: GPIOC peripheral clock disabled (default after..,1: GPIOC peripheral clock enabled"
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bitfld.long 0x10 1. "GPIOBEN,GPIOB peripheral clock enable" "0: GPIOB peripheral clock disabled (default after..,1: GPIOB peripheral clock enabled"
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bitfld.long 0x10 0. "GPIOAEN,GPIOA peripheral clock enable" "0: GPIOA peripheral clock disabled (default after..,1: GPIOA peripheral clock enabled"
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line.long 0x14 "RCC_APB5ENR,RCC APB5 clock enable register"
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bitfld.long 0x14 4. "GFXTIMEN,GFXTIM peripheral clock enable" "0: GFXTIM peripheral clock disabled (default after..,1: GFXTIM peripheral clock provided"
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bitfld.long 0x14 2. "DCMIPPEN,DCMIPP peripheral clock enable" "0: DCMIPP peripheral clock disabled (default after..,1: DCMIPP peripheral clock provided"
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bitfld.long 0x14 1. "LTDCEN,LTDC peripheral clock enable" "0: LTDC peripheral clock disabled (default after..,1: LTDC peripheral clock provided to the LTDC block"
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line.long 0x18 "RCC_APB1ENR1,RCC APB1 clock enable register 1"
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bitfld.long 0x18 31. "UART8EN,UART8 peripheral clocks enable" "0: UART8 peripheral clocks disabled (default after..,1: UART8 peripheral clocks enabled"
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bitfld.long 0x18 30. "UART7EN,UART7 peripheral clocks enable" "0: UART7 peripheral clocks disabled (default after..,1: UART7 peripheral clocks enabled"
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bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock enable" "0: HDMI-CEC peripheral clock disabled (default..,1: HDMI-CEC peripheral clock enabled"
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bitfld.long 0x18 23. "I2C3EN,I2C3 peripheral clocks enable" "0: I2C3 peripheral clocks disabled (default after..,1: I2C3 peripheral clocks enabled"
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bitfld.long 0x18 22. "I2C2EN,I2C2 peripheral clocks enable" "0: I2C2 peripheral clocks disabled (default after..,1: I2C2 peripheral clocks enabled"
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bitfld.long 0x18 21. "I2C1_I3C1EN,I2C1/I3C1 peripheral clocks enable" "0: I2C1/I3C1 peripheral clocks disabled (default..,1: I2C1/I3C1 peripheral clocks enabled"
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bitfld.long 0x18 20. "UART5EN,UART5 peripheral clocks enable" "0: UART5 peripheral clocks disabled (default after..,1: UART5 peripheral clocks enabled"
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bitfld.long 0x18 19. "UART4EN,UART4 peripheral clocks enable" "0: UART4 peripheral clocks disabled (default after..,1: UART4 peripheral clocks enabled"
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bitfld.long 0x18 18. "USART3EN,USART3 peripheral clocks enable" "0: USART3 peripheral clocks disabled (default after..,1: USART3 peripheral clocks enabled"
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bitfld.long 0x18 17. "USART2EN,USART2peripheral clocks enable" "0: USART2 peripheral clocks disabled (default after..,1: USART2 peripheral clocks enabled"
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bitfld.long 0x18 16. "SPDIFRXEN,SPDIFRX peripheral clocks enable" "0: SPDIFRX peripheral clocks disabled (default..,1: SPDIFRX peripheral clocks enabled"
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bitfld.long 0x18 15. "SPI3EN,SPI3 peripheral clocks enable" "0: SPI3 peripheral clocks disabled (default after..,1: SPI3 peripheral clocks enabled"
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bitfld.long 0x18 14. "SPI2EN,SPI2 peripheral clocks enable" "0: SPI2 peripheral clocks disabled (default after..,1: SPI2 peripheral clocks enabled"
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bitfld.long 0x18 11. "WWDGEN,WWDG clock enable" "0: WWDG peripheral clock disable (default after..,1: WWDG peripheral clock enabled"
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bitfld.long 0x18 9. "LPTIM1EN,LPTIM1 peripheral clocks enable" "0: LPTIM1 peripheral clocks disabled (default after..,1: LPTIM1 peripheral clocks enabled"
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bitfld.long 0x18 8. "TIM14EN,TIM14 peripheral clock enable" "0: TIM14 peripheral clock disabled (default after..,1: TIM14 peripheral clock enabled"
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bitfld.long 0x18 7. "TIM13EN,TIM13 peripheral clock enable" "0: TIM13 peripheral clock disabled (default after..,1: TIM13 peripheral clock enabled"
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bitfld.long 0x18 6. "TIM12EN,TIM12 peripheral clock enable" "0: TIM12 peripheral clock disabled (default after..,1: TIM12 peripheral clock enabled"
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bitfld.long 0x18 5. "TIM7EN,TIM7 peripheral clock enable" "0: TIM7 peripheral clock disabled (default after..,1: TIM7 peripheral clock enabled"
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bitfld.long 0x18 4. "TIM6EN,TIM6 peripheral clock enable" "0: TIM6 peripheral clock disabled (default after..,1: TIM6 peripheral clock enabled"
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bitfld.long 0x18 3. "TIM5EN,TIM5 peripheral clock enable" "0: TIM5 peripheral clock disabled (default after..,1: TIM5 peripheral clock enabled"
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bitfld.long 0x18 2. "TIM4EN,TIM4 peripheral clock enable" "0: TIM4 peripheral clock disable (default after..,1: TIM4 peripheral clock enabled"
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bitfld.long 0x18 1. "TIM3EN,TIM3 peripheral clock enable" "0: TIM3 peripheral clock disabled (default after..,1: TIM3 peripheral clock enabled"
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bitfld.long 0x18 0. "TIM2EN,TIM2 peripheral clock enable" "0: TIM2 peripheral clock disabled (default after..,1: TIM2 peripheral clock enabled"
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line.long 0x1C "RCC_APB1ENR2,RCC APB1 clock enable register 2"
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bitfld.long 0x1C 27. "UCPDEN,UCPD peripheral clock enable" "0: UCPD peripheral clock disabled (default after..,1: UCPD peripheral clock enabled"
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bitfld.long 0x1C 8. "FDCANEN,FDCAN peripheral clock enable" "0: FDCAN peripheral clock disabled (default after..,1: FDCAN peripheral clock enabled"
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bitfld.long 0x1C 5. "MDIOSEN,MDIOS peripheral clock enable" "0: MDIOS peripheral clock disabled (default after..,1: MDIOS peripheral clock enabled"
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bitfld.long 0x1C 1. "CRSEN,clock recovery system peripheral clock enable" "0: CRS peripheral clock disabled (default after..,1: CRS peripheral clock enabled"
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line.long 0x20 "RCC_APB2ENR,RCC APB2 clock enable register"
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bitfld.long 0x20 23. "SAI2EN,SAI2 peripheral clocks enable" "0: SAI2 peripheral clocks disabled (default after..,1: SAI2 peripheral clocks enabled:"
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bitfld.long 0x20 22. "SAI1EN,SAI1 peripheral clocks enable" "0: SAI1 peripheral clocks disabled (default after..,1: SAI1 peripheral clocks enabled:"
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bitfld.long 0x20 20. "SPI5EN,SPI5 peripheral clocks enable" "0: SPI5 peripheral clocks disabled (default after..,1: SPI5 peripheral clocks enabled:"
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bitfld.long 0x20 19. "TIM9EN,TIM9 peripheral clock enable" "0: TIM9 peripheral clock disabled (default after..,1: TIM9 peripheral clock enabled"
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bitfld.long 0x20 18. "TIM17EN,TIM17 peripheral clock enable" "0: TIM17 peripheral clock disabled (default after..,1: TIM17 peripheral clock enabled"
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bitfld.long 0x20 17. "TIM16EN,TIM16 peripheral clock enable" "0: TIM16 peripheral clock disabled (default after..,1: TIM16 peripheral clock enabled"
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bitfld.long 0x20 16. "TIM15EN,TIM15 peripheral clock enable" "0: TIM15 peripheral clock disabled (default after..,1: TIM15 peripheral clock enabled"
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bitfld.long 0x20 13. "SPI4EN,SPI4 Peripheral Clocks Enable" "0: SPI4 peripheral clocks disabled (default after..,1: SPI4 peripheral clocks enabled:"
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bitfld.long 0x20 12. "SPI1EN,SPI2S1 Peripheral Clocks Enable" "0: SPI2S1 peripheral clocks disabled (default after..,1: SPI2S1 peripheral clocks enabled:"
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bitfld.long 0x20 4. "USART1EN,USART1 peripheral clocks enable" "0: USART1 peripheral clocks disabled (default after..,1: USART1 peripheral clocks enabled:"
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bitfld.long 0x20 0. "TIM1EN,TIM1 peripheral clock enable" "0: TIM1 peripheral clock disabled (default after..,1: TIM1 peripheral clock enabled"
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line.long 0x24 "RCC_APB4ENR,RCC APB4 clock enable register"
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bitfld.long 0x24 26. "TMPSENSEN,Temperature Sensor peripheral clock enable" "0: TMPSENS peripheral clock disabled (default after..,1: TMPSENS peripheral clock enabled"
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bitfld.long 0x24 16. "RTCAPBEN,RTC APB clock enable" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.."
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bitfld.long 0x24 15. "VREFEN,VREF peripheral clock enable" "0: VREF peripheral clock disabled (default after..,1: VREF peripheral clock enabled"
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bitfld.long 0x24 12. "LPTIM5EN,LPTIM5 peripheral clocks enable" "0: LPTIM5 peripheral clocks disabled (default after..,1: LPTIM5 peripheral clocks enabled"
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bitfld.long 0x24 11. "LPTIM4EN,LPTIM4 peripheral clocks enable" "0: LPTIM4 peripheral clocks disabled (default after..,1: LPTIM4 peripheral clocks enabled"
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bitfld.long 0x24 10. "LPTIM3EN,LPTIM3 peripheral clocks enable" "0: LPTIM3 peripheral clocks disabled (default after..,1: LPTIM3 peripheral clocks enabled"
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bitfld.long 0x24 9. "LPTIM2EN,LPTIM2 peripheral clocks enable" "0: LPTIM2 peripheral clocks disabled (default after..,1: LPTIM2 peripheral clocks enabled"
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bitfld.long 0x24 5. "SPI6EN,SPI/I2S6 peripheral clocks enable" "0: SPI/I2S6 peripheral clocks disabled (default..,1: SPI/I2S6 peripheral clocks enabled"
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bitfld.long 0x24 3. "LPUART1EN,LPUART1 peripheral clocks enable" "0: LPUART1 peripheral clocks disabled (default..,1: LPUART1 peripheral clocks enabled"
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bitfld.long 0x24 1. "SBSEN,SBS peripheral clock enable" "0: SBS peripheral clock disabled (default after..,1: SBS peripheral clock enabled"
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line.long 0x28 "RCC_AHB3ENR,RCC AHB3 clock enable register"
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bitfld.long 0x28 6. "PKAEN,PKA peripheral clock enable" "0: PKA peripheral clock disabled (default after..,1: PKA peripheral clock enabled"
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bitfld.long 0x28 4. "SAESEN,SAES peripheral clock enable" "0: The SAES peripheral clocks are disabled (default..,1: The SAES peripheral clocks are enabled"
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bitfld.long 0x28 2. "CRYPEN,CRYP peripheral clock enable" "0: CRYP peripheral clock disabled (default after..,1: CRYP peripheral clock enabled"
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bitfld.long 0x28 1. "HASHEN,HASH peripheral clock enable" "0: HASH peripheral clock disabled (default after..,1: HASH peripheral clock enabled"
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bitfld.long 0x28 0. "RNGEN,RNG peripheral clocks enable" "0: RNG peripheral clocks disabled (default after..,1: RNG peripheral clocks enabled."
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line.long 0x2C "RCC_AHB5LPENR,RCC AHB5 low-power clock enable register"
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bitfld.long 0x2C 31. "AXISRAMLPEN,AXISRAM[4:1] low-power peripheral clock enable" "0: AXISRAM[4:1] interface peripheral clock disabled..,1: AXISRAM[4:1] interface peripheral clock enabled.."
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bitfld.long 0x2C 30. "ITCMLPEN,ITCM low-power peripheral clock enable" "0: ITCM interface peripheral clock disabled during..,1: ITCM interface peripheral clock enabled during.."
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bitfld.long 0x2C 29. "DTCM2LPEN,DTCM2 low-power peripheral clock enable" "0: DTCM2 interface peripheral clock disabled during..,1: DTCM2 interface peripheral clock enabled during.."
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bitfld.long 0x2C 28. "DTCM1LPEN,DTCM1 low-power peripheral clock enable" "0: DTCM1 interface peripheral clock disabled during..,1: DTCM1 interface peripheral clock enabled during.."
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bitfld.long 0x2C 20. "GPULPEN,GPU low-power peripheral clock enable" "0: GPU interface clock peripheral disabled during..,1: GPU interface clock peripheral enabled during.."
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bitfld.long 0x2C 19. "GFXMMULPEN,GFXMMU low-power peripheral clock enable" "0: GFXMMU interface peripheral clock disabled..,1: GFXMMU interface peripheral clock enabled during.."
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bitfld.long 0x2C 14. "XSPIMLPEN,XSPIM low-power peripheral clock enable" "0: XSPIM interface peripheral clock disabled during..,1: XSPIM interface peripheral clock enabled during.."
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bitfld.long 0x2C 12. "XSPI2LPEN,XSPI2 and MCE2 low-power peripheral clock enable" "0: XSPI2 and MCE2 peripheral clock disabled during..,1: XSPI2 and MCE2 peripheral clock enabled during.."
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bitfld.long 0x2C 8. "SDMMC1LPEN,SDMMC1 and SDMMC1 delay low-power peripheral clock enable" "0: SDMMC1 and SDMMC1 delay peripheral clock..,1: SDMMC1 and SDMMC1 delay peripheral clock enabled.."
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bitfld.long 0x2C 5. "XSPI1LPEN,XSPI1 and MCE1 low-power peripheral clock enable" "0: XSPI1 and MCE1 peripheral clock disabled during..,1: XSPI1 and MCE1 peripheral clock enabled during.."
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bitfld.long 0x2C 4. "FMCLPEN,FMC and MCE3 peripheral clocks enable during Sleep mode" "0: FMC and MCE3 peripheral clocks disabled during..,1: FMC and MCE3 peripheral clocks enabled during.."
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bitfld.long 0x2C 3. "JPEGLPEN,JPEG clock enable during Sleep mode" "0: JPEG peripheral clock disabled during Sleep mode,1: JPEG peripheral clock enabled during Sleep mode.."
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bitfld.long 0x2C 2. "FLITFLPEN,FLITF low-power peripheral clock enable" "0: FLITF peripheral clock disabled during Sleep mode,1: FLITF peripheral clock enabled during Sleep mode.."
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bitfld.long 0x2C 1. "DMA2DLPEN,DMA2D low-power peripheral clock enable" "0: DMA2D peripheral clock disabled during Sleep mode,1: DMA2D peripheral clock enabled during Sleep mode.."
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bitfld.long 0x2C 0. "HPDMA1LPEN,HPDMA1 low-power peripheral clock enable" "0: HPDMA1 peripheral clock disabled during Sleep mode,1: HPDMA1 peripheral clock enabled during Sleep.."
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line.long 0x30 "RCC_AHB1LPENR,RCC AHB1 low-power clock enable register"
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bitfld.long 0x30 31. "ADFLPEN,ADF clock enable in low-power mode" "0: ADF peripheral clock disabled in low-power mode,1: ADF peripheral clock enabled in low-power mode.."
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bitfld.long 0x30 27. "OTGFSLPEN,OTGFS clock enable in low-power mode" "0: OTGFS peripheral clock disabled in low-power mode,1: OTGFS peripheral clock enabled in low-power mode.."
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bitfld.long 0x30 26. "USBPHYCLPEN,USBPHYC peripheral clock enable in low-power mode" "0: USBPHYC peripheral clock disabled in low-power..,1: USBPHYC peripheral clock enabled in low-power.."
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bitfld.long 0x30 25. "OTGHSLPEN,OTGHS peripheral clock enable in low-power mode" "0: OTGHS peripheral clock disabled in low-power mode,1: OTGHS peripheral clock enabled in low-power mode.."
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bitfld.long 0x30 24. "USBPDCTRL,USBPHYC common block power-down control" "0: In SUSPEND PHY state machine bias and USBPHYC..,1: In SUSPEND PHY state machine bias and USBPHYC.."
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bitfld.long 0x30 17. "ETH1RXLPEN,ETH1 reception peripheral clock enable in low-power mode" "0: ETH1 reception peripheral clock disabled in..,1: ETH1 reception peripheral clock enabled in.."
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bitfld.long 0x30 16. "ETH1TXLPEN,ETH1 transmission peripheral clock enable in low-power mode" "0: ETH1 transmission peripheral clock disabled in..,1: ETH1 transmission peripheral clock enabled in.."
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bitfld.long 0x30 15. "ETH1MACLPEN,ETH1 MAC peripheral clock enable in low-power mode" "0: ETH1 MAC peripheral clock disabled in low-power..,1: ETH1 MAC peripheral clock enabled in low-power.."
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bitfld.long 0x30 5. "ADC12LPEN,ADC1 and 2 peripheral clocks enable in low-power mode" "0: ADC1 and 2 peripheral clocks disabled in..,1: ADC1 and 2 peripheral clocks enabled in.."
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bitfld.long 0x30 4. "GPDMA1LPEN,GPDMA1 clock enable in low-power mode" "0: GPDMA1 clock disabled in low-power mode,1: GPDMA1 clock enabled in low-power mode (default.."
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line.long 0x34 "RCC_AHB2LPENR,RCC AHB2 low-power clock enable register"
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bitfld.long 0x34 30. "SRAM2LPEN,SRAM2 clock enable in low-power mode" "0: SRAM2 clock disabled in low-power mode,1: SRAM2 clock enabled in low-power mode (default.."
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bitfld.long 0x34 29. "SRAM1LPEN,SRAM1 clock enable in low-power mode" "0: SRAM1 clock disabled in low-power mode,1: SRAM1 clock enabled in low-power mode (default.."
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bitfld.long 0x34 14. "CORDICLPEN,CORDIC clock enable in low-power mode" "0: CORDIC clock disabled in low-power mode,1: CORDIC clock enabled in low-power mode (default.."
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bitfld.long 0x34 9. "SDMMC2LPEN,SDMMC2 and SDMMC2 delay clock enable in low-power mode" "0: SDMMC2 and SDMMC2 delay clock disabled in..,1: SDMMC2 and SDMMC2 delay clock enabled in.."
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bitfld.long 0x34 1. "PSSILPEN,PSSI peripheral clock enable in low-power mode" "0: PSSI peripheral clock disabled in low-power mode,1: PSSI peripheral clock enabled in low-power mode.."
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line.long 0x38 "RCC_AHB4LPENR,RCC AHB4 low-power clock enable register"
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bitfld.long 0x38 28. "BKPRAMLPEN,Backup RAM clock enable in low-power mode" "0: Backup RAM clock disabled in low-power mode,1: Backup RAM clock enabled in low-power mode.."
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bitfld.long 0x38 19. "CRCLPEN,CRC clock enable in low-power mode" "0: CRC clock disabled in low-power mode,1: CRC clock enabled in low-power mode (default.."
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bitfld.long 0x38 15. "GPIOPLPEN,GPIOP peripheral clock enable in low-power mode" "0: GPIOP peripheral clock disabled in low-power mode,1: GPIOP peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 14. "GPIOOLPEN,GPIOO peripheral clock enable in low-power mode" "0: GPIOO peripheral clock disabled in low-power mode,1: GPIOO peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 13. "GPIONLPEN,GPION peripheral clock enable in low-power mode" "0: GPION peripheral clock disabled in low-power mode,1: GPION peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 12. "GPIOMLPEN,GPIOM peripheral clock enable in low-power mode" "0: GPIOM peripheral clock disabled in low-power mode,1: GPIOM peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 7. "GPIOHLPEN,GPIOH peripheral clock enable in low-power mode" "0: GPIOH peripheral clock disabled in low-power mode,1: GPIOH peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 6. "GPIOGLPEN,GPIOG peripheral clock enable in low-power mode" "0: GPIOG peripheral clock disabled in low-power mode,1: GPIOG peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 5. "GPIOFLPEN,GPIOF peripheral clock enable in low-power mode" "0: GPIOF peripheral clock disabled in low-power mode,1: GPIOF peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 4. "GPIOELPEN,GPIOE peripheral clock enable in low-power mode" "0: GPIOE peripheral clock disabled in low-power mode,1: GPIOE peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 3. "GPIODLPEN,GPIOD peripheral clock enable in low-power mode" "0: GPIOD peripheral clock disabled in low-power mode,1: GPIOD peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 2. "GPIOCLPEN,GPIOC peripheral clock enable in low-power mode" "0: GPIOC peripheral clock disabled in low-power mode,1: GPIOC peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 1. "GPIOBLPEN,GPIOB peripheral clock enable in low-power mode" "0: GPIOB peripheral clock disabled in low-power mode,1: GPIOB peripheral clock enabled in low-power mode.."
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bitfld.long 0x38 0. "GPIOALPEN,GPIOA peripheral clock enable in low-power mode" "0: GPIOA peripheral clock disabled in low-power mode,1: GPIOA peripheral clock enabled in low-power mode.."
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|
line.long 0x3C "RCC_AHB3LPENR,RCC AHB3 low-power clock enable register"
|
|
bitfld.long 0x3C 6. "PKALPEN,PKA peripheral clock enable in low-power mode" "0: PKA peripheral clock disabled in low-power mode,1: PKA peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x3C 4. "SAESLPEN,SAES peripheral clock enable in low-power mode" "0: SAES peripheral clock disabled in low-power mode,1: SAES peripheral clock enabled in low-power mode.."
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bitfld.long 0x3C 2. "CRYPLPEN,CRYP peripheral clock enable in low-power mode" "0: CRYP peripheral clock disabled in low-power mode,1: CRYP peripheral clock enabled in low-power mode.."
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bitfld.long 0x3C 1. "HASHLPEN,HASH peripheral clock enable in low-power mode" "0: HASH peripheral clock disabled in low-power mode,1: HASH peripheral clock enabled in low-power mode.."
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bitfld.long 0x3C 0. "RNGLPEN,RNG peripheral clock enable in low-power mode" "0: RNG peripheral clocks disabled in low-power mode,1: RNG peripheral clock enabled in low-power mode.."
|
|
line.long 0x40 "RCC_APB1LPENR1,RCC APB1 low-power clock enable register 1"
|
|
bitfld.long 0x40 31. "UART8LPEN,UART8 peripheral clocks enable in low-power mode" "0: UART8 peripheral clocks disabled in low-power mode,1: UART8 peripheral clocks enabled in low-power.."
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|
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bitfld.long 0x40 30. "UART7LPEN,UART7 peripheral clocks enable in low-power mode" "0: UART7 peripheral clocks disabled in low-power mode,1: UART7 peripheral clocks enabled in low-power.."
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|
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bitfld.long 0x40 27. "HDMICECLPEN,HDMI-CEC peripheral clocks enable in low-power mode" "0: HDMI-CEC peripheral clocks disabled in low-power..,1: HDMI-CEC peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x40 23. "I2C3LPEN,I2C3 peripheral clocks enable in low-power mode" "0: I2C3 peripheral clocks disabled in low-power mode,1: I2C3 peripheral clocks enabled in low-power mode.."
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bitfld.long 0x40 22. "I2C2LPEN,I2C2 peripheral clocks enable in low-power mode" "0: I2C2 peripheral clocks disabled in low-power mode,1: I2C2 peripheral clocks enabled in low-power mode.."
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|
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bitfld.long 0x40 21. "I2C1_I3C1LPEN,I2C1/I3C1 peripheral clocks enable in low-power mode" "0: I2C1/I3C1 peripheral clocks disabled in..,1: I2C1/I3C1 peripheral clocks enabled in low-power.."
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|
newline
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bitfld.long 0x40 20. "UART5LPEN,UART5 peripheral clocks enable in low-power mode" "0: UART5 peripheral clocks disabled in low-power mode,1: UART5 peripheral clocks enabled in low-power.."
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|
newline
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bitfld.long 0x40 19. "UART4LPEN,UART4 peripheral clocks enable in low-power mode" "0: UART4 peripheral clocks disabled in low-power mode,1: UART4 peripheral clocks enabled in low-power.."
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|
newline
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bitfld.long 0x40 18. "USART3LPEN,USART3 peripheral clocks enable in low-power mode" "0: USART3 peripheral clocks disabled in low-power..,1: USART3 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x40 17. "USART2LPEN,USART2 peripheral clocks enable in low-power mode" "0: USART2 peripheral clocks disabled in low-power..,1: USART2 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x40 16. "SPDIFRXLPEN,SPDIFRX peripheral clocks enable in low-power mode" "0: SPDIFRX peripheral clocks disabled in low-power..,1: SPDIFRX peripheral clocks enabled in low-power.."
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|
newline
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bitfld.long 0x40 15. "SPI3LPEN,SPI3 peripheral clocks enable in low-power mode" "0: SPI3 peripheral clocks disabled in low-power mode,1: SPI3 peripheral clocks enabled in low-power mode.."
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bitfld.long 0x40 14. "SPI2LPEN,SPI2 peripheral clocks enable in low-power mode" "0: SPI2 peripheral clocks disabled in low-power mode,1: SPI2 peripheral clocks enabled in low-power mode.."
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newline
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bitfld.long 0x40 11. "WWDGLPEN,WWDG clock enable in low-power mode" "0: WWDG clock disable in low-power mode,1: WWDG clock enabled in low-power mode (default.."
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|
newline
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bitfld.long 0x40 9. "LPTIM1LPEN,LPTIM1 peripheral clocks enable in low-power mode" "0: LPTIM1 peripheral clocks disabled in low-power..,1: LPTIM1 peripheral clocks enabled in low-power.."
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bitfld.long 0x40 8. "TIM14LPEN,TIM14 peripheral clock enable in low-power mode" "0: TIM14 peripheral clock disabled in low-power mode,1: TIM14 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 7. "TIM13LPEN,TIM13 peripheral clock enable in low-power mode" "0: TIM13 peripheral clock disabled in low-power mode,1: TIM13 peripheral clock enabled in low-power mode.."
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bitfld.long 0x40 6. "TIM12LPEN,TIM12 peripheral clock enable in low-power mode" "0: TIM12 peripheral clock disabled in low-power mode,1: TIM12 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 5. "TIM7LPEN,TIM7 peripheral clock enable in low-power mode" "0: TIM7 peripheral clock disabled in low-power mode,1: TIM7 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 4. "TIM6LPEN,TIM6 peripheral clock enable in low-power mode" "0: TIM6 peripheral clock disabled in low-power mode,1: TIM6 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 3. "TIM5LPEN,TIM5 peripheral clock enable in low-power mode" "0: TIM5 peripheral clock disabled in low-power mode,1: TIM5 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 2. "TIM4LPEN,TIM4 peripheral clock enable in low-power mode" "0: TIM4 peripheral clock disabled in low-power mode,1: TIM4 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 1. "TIM3LPEN,TIM3 peripheral clock enable in low-power mode" "0: TIM3 peripheral clock disabled in low-power mode,1: TIM3 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x40 0. "TIM2LPEN,TIM2 peripheral clock enable in low-power mode" "0: TIM2 peripheral clock disabled in low-power mode,1: TIM2 peripheral clock enabled in low-power mode.."
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|
line.long 0x44 "RCC_APB1LPENR2,RCC APB1 low-power clock enable register 2"
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|
bitfld.long 0x44 27. "UCPDLPEN,UCPD peripheral clock enable in low-power mode" "0: UCPD peripheral clock disabled in low-power mode,1: UCPD peripheral clock enabled in low-power mode.."
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bitfld.long 0x44 8. "FDCANLPEN,FDCAN peripheral clock enable in low-power mode" "0: FDCAN peripheral clock disabled in low-power mode,1: FDCAN peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x44 5. "MDIOSLPEN,MDIOS peripheral clock enable in low-power mode" "0: MDIOS peripheral clock disabled in low-power mode,1: MDIOS peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x44 1. "CRSLPEN,clock recovery system peripheral clock enable in low-power mode" "0: CRS peripheral clock disabled in low-power mode,1: CRS peripheral clock enabled in low-power mode.."
|
|
line.long 0x48 "RCC_APB2LPENR,RCC APB2 low-power clock enable register"
|
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bitfld.long 0x48 23. "SAI2LPEN,SAI2 peripheral clocks enable in low-power mode" "0: SAI2 peripheral clocks disabled in low-power mode,1: SAI2 peripheral clocks enabled in low-power mode.."
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newline
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bitfld.long 0x48 22. "SAI1LPEN,SAI1 peripheral clocks enable in low-power mode" "0: SAI1 peripheral clocks disabled in low-power mode,1: SAI1 peripheral clocks enabled in low-power mode.."
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newline
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bitfld.long 0x48 20. "SPI5LPEN,SPI5 peripheral clocks enable in low-power mode" "0: SPI5 peripheral clocks disabled in low-power mode,1: SPI5 peripheral clocks enabled in low-power mode.."
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newline
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bitfld.long 0x48 19. "TIM9LPEN,TIM9 peripheral clock enable in low-power mode" "0: TIM9 peripheral clock disabled in low-power mode,1: TIM9 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x48 18. "TIM17LPEN,TIM17 peripheral clock enable in low-power mode" "0: TIM17 peripheral clock disabled in low-power mode,1: TIM17 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x48 17. "TIM16LPEN,TIM16 peripheral clock enable in low-power mode" "0: TIM16 peripheral clock disabled in low-power mode,1: TIM16 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x48 16. "TIM15LPEN,TIM15 peripheral clock enable in low-power mode" "0: TIM15 peripheral clock disabled in low-power mode,1: TIM15 peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x48 13. "SPI4LPEN,SPI4 peripheral clock enable in low-power mode" "0: SPI4 peripheral clocks disabled in low-power mode,1: SPI4 peripheral clocks enabled in low-power mode.."
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newline
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bitfld.long 0x48 12. "SPI1LPEN,SPI2S1 peripheral clock enable in low-power mode" "0: SPI2S1 peripheral clocks disabled in low-power..,1: SPI2S1 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x48 4. "USART1LPEN,USART1 peripheral clock enable in low-power mode" "0: USART1 peripheral clocks disabled in low-power..,1: USART1 peripheral clocks enabled in low-power.."
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|
newline
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bitfld.long 0x48 0. "TIM1LPEN,TIM1 peripheral clock enable in low-power mode" "0: TIM1 peripheral clock disabled in low-power mode,1: TIM1 peripheral clock enabled in low-power mode.."
|
|
line.long 0x4C "RCC_APB4LPENR,RCC APB4 low-power clock enable register"
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|
bitfld.long 0x4C 26. "TMPSENSLPEN,temperature sensor peripheral clock enable in low-power mode" "0: TMPSENS peripheral clock disabled in low-power..,1: TMPSENS peripheral clock enabled in low-power.."
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newline
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bitfld.long 0x4C 16. "RTCAPBLPEN,RTC APB clock enable in low-power mode" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.."
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newline
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bitfld.long 0x4C 15. "VREFLPEN,VREF peripheral clock enable in low-power mode" "0: VREF peripheral clock disabled in low-power mode,1: VREF peripheral clock enabled in low-power mode.."
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newline
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bitfld.long 0x4C 12. "LPTIM5LPEN,LPTIM5 peripheral clocks enable in low-power mode" "0: LPTIM5 peripheral clocks disabled in low-power..,1: LPTIM5 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x4C 11. "LPTIM4LPEN,LPTIM4 peripheral clocks enable in low-power mode" "0: LPTIM4 peripheral clocks disabled in low-power..,1: LPTIM4 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x4C 10. "LPTIM3LPEN,LPTIM3 peripheral clocks enable in low-power mode" "0: LPTIM3 peripheral clocks disabled in low-power..,1: LPTIM3 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x4C 9. "LPTIM2LPEN,LPTIM2 peripheral clocks enable in low-power mode" "0: LPTIM2 peripheral clocks disabled in low-power..,1: LPTIM2 peripheral clocks enabled in low-power.."
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|
newline
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bitfld.long 0x4C 5. "SPI6LPEN,SPI/I2S6 peripheral clocks enable in low-power mode" "0: SPI/I2S6 peripheral clocks disabled in low-power..,1: SPI/I2S6 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x4C 3. "LPUART1LPEN,LPUART1 peripheral clocks enable in low-power mode" "0: LPUART1 peripheral clocks disabled in low-power..,1: LPUART1 peripheral clocks enabled in low-power.."
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newline
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bitfld.long 0x4C 1. "SBSLPEN,SBS peripheral clock enable in low-power mode" "0: SBS peripheral clock disabled in low-power mode,1: SBS peripheral clock enabled in low-power mode.."
|
|
line.long 0x50 "RCC_APB5LPENR,RCC APB5 sleep clock register"
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bitfld.long 0x50 4. "GFXTIMLPEN,GFXTIM peripheral clock enable in low-power mode" "0: GFXTIM peripheral clock disabled in low-power mode,1: GFXTIM peripheral clock enabled in low-power.."
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|
newline
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bitfld.long 0x50 2. "DCMIPPLPEN,DCMIPP peripheral clock enable in low-power mode" "0: DCMIPP peripheral clock disabled in low-power mode,1: DCMIPP peripheral clock enabled in low-power.."
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newline
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bitfld.long 0x50 1. "LTDCLPEN,LTDC peripheral clock enable in low-power mode" "0: LTDC peripheral clock disabled in low-power mode,1: LTDC peripheral clock enabled in low-power mode.."
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tree.end
|
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tree "RNG (Random Number Generator)"
|
|
base ad:0x48020000
|
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group.long 0x0++0x7
|
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line.long 0x0 "RNG_CR,RNG control register"
|
|
bitfld.long 0x0 31. "CONFIGLOCK,RNG Config lock" "0: Writes to the RNG_HTCR and RNG_CR configuration..,1: Writes to the RNG_HTCR and RNG_CR configuration.."
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|
bitfld.long 0x0 30. "CONDRST,Conditioning soft reset" "0,1"
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|
newline
|
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hexmask.long.byte 0x0 20.--25. 1. "RNG_CONFIG1,RNG configuration 1"
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|
hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,Clock divider factor"
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|
newline
|
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bitfld.long 0x0 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12. "NISTC,NIST custom" "0: Hardware default values for NIST compliant RNG.,1: Custom values for NIST compliant RNG. See.."
|
|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "RNG_CONFIG3,RNG configuration 3"
|
|
bitfld.long 0x0 7. "ARDIS,Auto reset disable" "0: When a noise source error occurs RNG performs an..,1: When a noise source error occurs application.."
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|
newline
|
|
bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection is enable,1: Clock error detection is disable"
|
|
bitfld.long 0x0 3. "IE,Interrupt Enable" "0: RNG Interrupt is disabled,1: RNG Interrupt is enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled."
|
|
line.long 0x4 "RNG_SR,RNG status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence is detected. See.."
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (fRNGCLK> fHCLK/32),1: The RNG clock before internal divider is.."
|
|
newline
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequence.."
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (fRNGCLK> fHCLK/32). If..,1: The RNG clock is too slow (fRNGCLK< fHCLK/32)."
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|
newline
|
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rbitfld.long 0x4 0. "DRDY,Data Ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RNG_DR,RNG data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "RNG_HTCR,RNG health test control register"
|
|
hexmask.long 0x0 0.--31. 1. "HTCFG,health test configuration"
|
|
tree.end
|
|
tree "RTC (Real-Time Counter)"
|
|
base ad:0x58004000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC subsecond register"
|
|
hexmask.long 0x0 0.--31. 1. "SS,Synchronous binary counter"
|
|
group.long 0xC++0x13
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 10.--12. "BCDU,BCD update (BIN = 10 or 11)" "0: 1s calendar increment is generated each time..,1: 1s calendar increment is generated each time..,2: 1s calendar increment is generated each time..,3: 1s calendar increment is generated each time..,4: 1s calendar increment is generated each time..,5: 1s calendar increment is generated each time..,6: 1s calendar increment is generated each time..,7: 1s calendar increment is generated each time.."
|
|
newline
|
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bitfld.long 0x0 8.--9. "BIN,Binary mode" "0: Free running BCD calendar mode (Binary mode..,1: Free running Binary mode (BCD mode disabled),2: Free running BCD calendar and Binary modes,3: Free running BCD calendar and Binary modes"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 16.--31. 1. "WUTOCLR,Wakeup auto-reload output clear value"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,RTC control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 28. "ALRBFCLR,Alarm B flag automatic clear" "0: Alarm B event generates a trigger event and..,1: Alarm B event generates a trigger event. ALRBF.."
|
|
newline
|
|
bitfld.long 0xC 27. "ALRAFCLR,Alarm A flag automatic clear" "0: Alarm A event generates a trigger event and..,1: Alarm A event generates a trigger event. ALRAF.."
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 7. "SSRUIE,SSR underflow interrupt enable" "0: SSR underflow interrupt disabled,1: SSR underflow interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
newline
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
newline
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
line.long 0x10 "RTC_PRIVCFGR,RTC privilege mode control register"
|
|
bitfld.long 0x10 15. "PRIV,RTC privilege protection" "0: All RTC registers can be written when the APB..,1: All RTC registers can be written only when the.."
|
|
bitfld.long 0x10 14. "INITPRIV,Initialization privilege protection" "0: RTC Initialization mode calendar and prescalers..,1: RTC Initialization mode calendar and prescalers.."
|
|
newline
|
|
bitfld.long 0x10 13. "CALPRIV,Shift register Delight saving calibration and reference clock privilege protection" "0: Shift register Delight saving calibration and..,1: Shift register Delight saving calibration and.."
|
|
bitfld.long 0x10 3. "TSPRIV,Timestamp privilege protection" "0: RTC Timestamp configuration and interrupt clear..,1: RTC Timestamp configuration and interrupt clear.."
|
|
newline
|
|
bitfld.long 0x10 2. "WUTPRIV,Wakeup timer privilege protection" "0: RTC Wakeup timer configuration and interrupt..,1: RTC Wakeup timer configuration and interrupt.."
|
|
bitfld.long 0x10 1. "ALRBPRIV,Alarm B privilege protection" "0: RTC Alarm B configuration and interrupt clear..,1: RTC Alarm B configuration and interrupt clear.."
|
|
newline
|
|
bitfld.long 0x10 0. "ALRAPRIV,Alarm A and SSR underflow privilege protection" "0: RTC Alarm A and SSR underflow configuration and..,1: RTC Alarm A and SSR underflow configuration and.."
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
bitfld.long 0x0 12. "LPCAL,RTC low-power mode" "0: Calibration window is 2<sup>20</sup> RTCCLK..,1: Calibration window is 2<sup>20</sup> ck_apre.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp subsecond register"
|
|
hexmask.long 0x8 0.--31. 1. "SS,Subsecond value/synchronous binary counter values"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day dont care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is dont.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours dont care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes dont care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds dont care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A subsecond register"
|
|
bitfld.long 0x4 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.."
|
|
hexmask.long.byte 0x4 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
newline
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Subseconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day dont care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is dont.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours dont care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes dont care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds dont care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B subsecond register"
|
|
bitfld.long 0xC 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.."
|
|
hexmask.long.byte 0xC 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
newline
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Subseconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 6. "SSRUF,SSR underflow flag" "0,1"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 6. "SSRUMF,SSR underflow masked flag" "0,1"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 6. "CSSRUF,Clear SSR underflow flag" "0,1"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "RTC_ALRABINR,RTC alarm A binary mode register"
|
|
hexmask.long 0x0 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode"
|
|
line.long 0x4 "RTC_ALRBBINR,RTC alarm B binary mode register"
|
|
hexmask.long 0x4 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode"
|
|
tree.end
|
|
tree "SAES (Secure AES)"
|
|
base ad:0x48021000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SAES_CR,SAES control register"
|
|
bitfld.long 0x0 31. "IPRST,SAES peripheral software reset" "0,1"
|
|
bitfld.long 0x0 28.--30. "KEYSEL,Key selection" "0: Software key loaded in key registers SAES_KEYx,1: Derived hardware unique key (DHUK),2: Boot hardware key (BHK),3: Application hardware key (AHK),4: XOR of DHUK and BHK,5: XOR of DHUK and AHK,?,7: Test mode key (256-bit hardware constant.."
|
|
newline
|
|
bitfld.long 0x0 26.--27. "KSHAREID,Key share identification" "0: CRYP peripheral,?,?,?"
|
|
bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal key,1: Wrapped key,2: Shared key,?"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128,1: 256"
|
|
newline
|
|
bitfld.long 0x0 16. "CHMOD_1,CHMOD[2]" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Init phase,1: Header phase,2: Payload phase,3: Final phase"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "CHMOD,CHMOD[1:0]: Chaining mode selection" "0: Electronic codebook (ECB),1: Cipher-block chaining (CBC),2: Counter mode (CTR),3: Galois counter mode (GCM) and Galois message.."
|
|
bitfld.long 0x0 3.--4. "MODE,SAES operating mode" "0: Mode 1: encryption,1: Mode 2: key derivation (or key preparation for..,2: Mode 3: decryption,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection" "0: None,1: Half-word (16-bit),2: Byte (8-bit),3: Bit"
|
|
bitfld.long 0x0 0. "EN,SAES enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SAES_SR,SAES status register"
|
|
bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0: No valid key information is available in key..,1: Valid key information defined by KEYSIZE in.."
|
|
bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy"
|
|
newline
|
|
bitfld.long 0x0 2. "WRERR,Write error" "0: Not detected,1: Detected"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0: Not detected,1: Detected"
|
|
newline
|
|
bitfld.long 0x0 0. "CCF,Computation completed flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "SAES_DINR,SAES data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DIN,Input data word"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SAES_DOUTR,SAES data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DOUT,Output data word"
|
|
wgroup.long 0x10++0xF
|
|
line.long 0x0 "SAES_KEYR0,SAES key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]"
|
|
line.long 0x4 "SAES_KEYR1,SAES key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]"
|
|
line.long 0x8 "SAES_KEYR2,SAES key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]"
|
|
line.long 0xC "SAES_KEYR3,SAES key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "SAES_IVR0,SAES initialization vector register 0"
|
|
hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]"
|
|
line.long 0x4 "SAES_IVR1,SAES initialization vector register 1"
|
|
hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]"
|
|
line.long 0x8 "SAES_IVR2,SAES initialization vector register 2"
|
|
hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]"
|
|
line.long 0xC "SAES_IVR3,SAES initialization vector register 3"
|
|
hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]"
|
|
wgroup.long 0x30++0xF
|
|
line.long 0x0 "SAES_KEYR4,SAES key register 4"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]"
|
|
line.long 0x4 "SAES_KEYR5,SAES key register 5"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]"
|
|
line.long 0x8 "SAES_KEYR6,SAES key register 6"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]"
|
|
line.long 0xC "SAES_KEYR7,SAES key register 7"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]"
|
|
group.long 0x40++0x1F
|
|
line.long 0x0 "SAES_SUSP0R,SAES suspend registers"
|
|
hexmask.long 0x0 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0x4 "SAES_SUSP1R,SAES suspend registers"
|
|
hexmask.long 0x4 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0x8 "SAES_SUSP2R,SAES suspend registers"
|
|
hexmask.long 0x8 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0xC "SAES_SUSP3R,SAES suspend registers"
|
|
hexmask.long 0xC 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0x10 "SAES_SUSP4R,SAES suspend registers"
|
|
hexmask.long 0x10 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0x14 "SAES_SUSP5R,SAES suspend registers"
|
|
hexmask.long 0x14 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0x18 "SAES_SUSP6R,SAES suspend registers"
|
|
hexmask.long 0x18 0.--31. 1. "SUSP,SAES suspend"
|
|
line.long 0x1C "SAES_SUSP7R,SAES suspend registers"
|
|
hexmask.long 0x1C 0.--31. 1. "SUSP,SAES suspend"
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "SAES_IER,SAES interrupt enable register"
|
|
bitfld.long 0x0 3. "RNGEIE,RNG error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
|
|
bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
|
|
newline
|
|
bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
|
|
bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
|
|
rgroup.long 0x304++0x3
|
|
line.long 0x0 "SAES_ISR,SAES interrupt status register"
|
|
bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag" "0: RNG bus is functional,1: Error detected on RNG bus interface (random seed.."
|
|
bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0: No key error detected,1: Key information failed to load into key.."
|
|
newline
|
|
bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0: No read or write error detected,1: Read or write error detected (see SAES_SR.."
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0: Not completed,1: Completed"
|
|
wgroup.long 0x308++0x3
|
|
line.long 0x0 "SAES_ICR,SAES interrupt clear register"
|
|
bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1"
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bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1"
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tree.end
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tree "SAI (Serial Audio Interface)"
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base ad:0x0
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tree "SAI1"
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base ad:0x42005C00
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group.long 0x0++0x17
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line.long 0x0 "SAI_GCR,SAI global configuration register"
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bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0: No synchronization output signals. SYNCOUT[1:0]..,1: Block A used for further synchronization for..,2: Block B used for further synchronization for..,3: Reserved. These bits must be set when both audio.."
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bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3"
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line.long 0x4 "SAI_ACR1,SAI configuration register 1"
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bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.."
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bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F<sub>FS</sub> x 256,1: Master clock frequency = F<sub>FS</sub> x 512"
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newline
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hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider"
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bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.."
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newline
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bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled"
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bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled."
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newline
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bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.."
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bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode."
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newline
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bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,3: FIELD Reserved"
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bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.."
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newline
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bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first"
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bitfld.long 0x4 5.--7. "DS,Data size" "0: FIELD Reserved,1: FIELD Reserved,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits"
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newline
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bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC97 protocol,3: FIELD Reserved"
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bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver"
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line.long 0x8 "SAI_ACR2,SAI configuration register 2"
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bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,1: Reserved.,2: -Law algorithm,3: A-Law algorithm"
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bitfld.long 0x8 13. "CPL,Complement bit." "0: 1s complement representation.,1: 2s complement representation."
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newline
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hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter."
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bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode."
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newline
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bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled."
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bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.."
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newline
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bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.."
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bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,5: FIELD Reserved,6: FIELD Reserved,7: FIELD Reserved"
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line.long 0xC "SAI_AFRCR,SAI frame configuration register"
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bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.."
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bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)"
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newline
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rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.."
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hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length."
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newline
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hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length."
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line.long 0x10 "SAI_ASLOTR,SAI slot register"
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hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable."
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hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame."
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newline
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bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,3: FIELD Reserved"
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hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset"
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line.long 0x14 "SAI_AIM,SAI interrupt mask register"
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bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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newline
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bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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newline
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bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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newline
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bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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rgroup.long 0x18++0x3
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line.long 0x0 "SAI_ASR,SAI status register"
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bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO UNDER OR EQUAL 1/4 but not empty..,2: 1/4 < FIFO UNDER OR EQUAL 1/2 (transmitter mode)..,3: 1/2 < FIFO UNDER OR EQUAL 3/4 (transmitter mode)..,4: 3/4 < FIFO but not full (transmitter mode) 3/4..,5: FIFO full (transmitter and receiver modes),?,?"
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bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.."
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newline
|
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bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.."
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bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC97 Codec is ready,1: External AC97 Codec is not ready"
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newline
|
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bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR."
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|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.."
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newline
|
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bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.."
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bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection."
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|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "SAI_ACLRFR,SAI clear flag register"
|
|
bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1"
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|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1"
|
|
bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1"
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|
bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1"
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|
group.long 0x20++0x17
|
|
line.long 0x0 "SAI_ADR,SAI data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
line.long 0x4 "SAI_BCR1,SAI configuration register 1"
|
|
bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.."
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|
bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F<sub>FS</sub> x 256,1: Master clock frequency = F<sub>FS</sub> x 512"
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|
newline
|
|
hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider"
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|
bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.."
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|
newline
|
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bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled"
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|
bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled."
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newline
|
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bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.."
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bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode."
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newline
|
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bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,3: FIELD Reserved"
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bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.."
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|
newline
|
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bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first"
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|
bitfld.long 0x4 5.--7. "DS,Data size" "0: FIELD Reserved,1: FIELD Reserved,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits"
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newline
|
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bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC97 protocol,3: FIELD Reserved"
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bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver"
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line.long 0x8 "SAI_BCR2,SAI configuration register 2"
|
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bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,1: Reserved.,2: -Law algorithm,3: A-Law algorithm"
|
|
bitfld.long 0x8 13. "CPL,Complement bit." "0: 1s complement representation.,1: 2s complement representation."
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|
newline
|
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hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter."
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|
bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode."
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newline
|
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bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled."
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bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.."
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|
newline
|
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bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.."
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|
bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,5: FIELD Reserved,6: FIELD Reserved,7: FIELD Reserved"
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line.long 0xC "SAI_BFRCR,SAI frame configuration register"
|
|
bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.."
|
|
bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)"
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newline
|
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rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.."
|
|
hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length."
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length."
|
|
line.long 0x10 "SAI_BSLOTR,SAI slot register"
|
|
hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable."
|
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hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame."
|
|
newline
|
|
bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,3: FIELD Reserved"
|
|
hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset"
|
|
line.long 0x14 "SAI_BIM,SAI interrupt mask register"
|
|
bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
rgroup.long 0x38++0x3
|
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line.long 0x0 "SAI_BSR,SAI status register"
|
|
bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO UNDER OR EQUAL 1/4 but not empty..,2: 1/4 < FIFO UNDER OR EQUAL 1/2 (transmitter mode)..,3: 1/2 < FIFO UNDER OR EQUAL 3/4 (transmitter mode)..,4: 3/4 < FIFO but not full (transmitter mode) 3/4..,5: FIFO full (transmitter and receiver modes),?,?"
|
|
bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.."
|
|
newline
|
|
bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.."
|
|
bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC97 Codec is ready,1: External AC97 Codec is not ready"
|
|
newline
|
|
bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR."
|
|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.."
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|
newline
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.."
|
|
bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection."
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "SAI_BCLRFR,SAI clear flag register"
|
|
bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1"
|
|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1"
|
|
bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1"
|
|
bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "SAI_BDR,SAI data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
line.long 0x4 "SAI_PDMCR,SAI PDM control register"
|
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bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number 2" "0: SAI_CK2 clock disabled,1: SAI_CK2 clock enabled"
|
|
bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number 1" "0: SAI_CK1 clock disabled,1: SAI_CK1 clock enabled"
|
|
newline
|
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bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0: Configuration with 2 microphones,1: Configuration with 4 microphones,2: Configuration with 6 microphones,3: SAI implementation for details"
|
|
bitfld.long 0x4 0. "PDMEN,PDM enable" "0: PDM interface disabled,1: PDM interface enabled"
|
|
line.long 0x8 "SAI_PDMDLY,SAI PDM delay register"
|
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bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
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bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 of T<sub>SAI_CK </sub>periods"
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|
newline
|
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bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
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|
bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
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newline
|
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bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
newline
|
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bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
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bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
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|
tree.end
|
|
tree "SAI2"
|
|
base ad:0x42005800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "SAI_GCR,SAI global configuration register"
|
|
bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs" "0: No synchronization output signals. SYNCOUT[1:0]..,1: Block A used for further synchronization for..,2: Block B used for further synchronization for..,3: Reserved. These bits must be set when both audio.."
|
|
bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3"
|
|
line.long 0x4 "SAI_ACR1,SAI configuration register 1"
|
|
bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.."
|
|
bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F<sub>FS</sub> x 256,1: Master clock frequency = F<sub>FS</sub> x 512"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider"
|
|
bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.."
|
|
newline
|
|
bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled"
|
|
bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled."
|
|
newline
|
|
bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.."
|
|
bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode."
|
|
newline
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|
bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,3: FIELD Reserved"
|
|
bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.."
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|
newline
|
|
bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first"
|
|
bitfld.long 0x4 5.--7. "DS,Data size" "0: FIELD Reserved,1: FIELD Reserved,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits"
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|
newline
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bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC97 protocol,3: FIELD Reserved"
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|
bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver"
|
|
line.long 0x8 "SAI_ACR2,SAI configuration register 2"
|
|
bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,1: Reserved.,2: -Law algorithm,3: A-Law algorithm"
|
|
bitfld.long 0x8 13. "CPL,Complement bit." "0: 1s complement representation.,1: 2s complement representation."
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|
newline
|
|
hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter."
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|
bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode."
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|
newline
|
|
bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled."
|
|
bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.."
|
|
newline
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|
bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.."
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|
bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,5: FIELD Reserved,6: FIELD Reserved,7: FIELD Reserved"
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|
line.long 0xC "SAI_AFRCR,SAI frame configuration register"
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|
bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.."
|
|
bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)"
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|
newline
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|
rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.."
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|
hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length."
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|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length."
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|
line.long 0x10 "SAI_ASLOTR,SAI slot register"
|
|
hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable."
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|
hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame."
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|
newline
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bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,3: FIELD Reserved"
|
|
hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset"
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|
line.long 0x14 "SAI_AIM,SAI interrupt mask register"
|
|
bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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|
bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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newline
|
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bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0: Interrupt is disabled,1: Interrupt is enabled"
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|
bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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|
newline
|
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bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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|
bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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newline
|
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bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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|
rgroup.long 0x18++0x3
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|
line.long 0x0 "SAI_ASR,SAI status register"
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|
bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO UNDER OR EQUAL 1/4 but not empty..,2: 1/4 < FIFO UNDER OR EQUAL 1/2 (transmitter mode)..,3: 1/2 < FIFO UNDER OR EQUAL 3/4 (transmitter mode)..,4: 3/4 < FIFO but not full (transmitter mode) 3/4..,5: FIFO full (transmitter and receiver modes),?,?"
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|
bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.."
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newline
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bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.."
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|
bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC97 Codec is ready,1: External AC97 Codec is not ready"
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|
newline
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bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR."
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|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.."
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newline
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bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.."
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|
bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection."
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|
wgroup.long 0x1C++0x3
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|
line.long 0x0 "SAI_ACLRFR,SAI clear flag register"
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|
bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1"
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|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1"
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|
bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1"
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|
bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1"
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|
group.long 0x20++0x17
|
|
line.long 0x0 "SAI_ADR,SAI data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
line.long 0x4 "SAI_BCR1,SAI configuration register 1"
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|
bitfld.long 0x4 27. "MCKEN,Master clock generation enable" "0: The master clock is not generated,1: The master clock is generated independently of.."
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|
bitfld.long 0x4 26. "OSR,Oversampling ratio for master clock" "0: Master clock frequency = F<sub>FS</sub> x 256,1: Master clock frequency = F<sub>FS</sub> x 512"
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newline
|
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hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,Master clock divider"
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|
bitfld.long 0x4 19. "NODIV,No divider" "0: the ratio between the Master clock generator and..,1: the ratio between the Master clock generator and.."
|
|
newline
|
|
bitfld.long 0x4 17. "DMAEN,DMA enable" "0: DMA disabled,1: DMA enabled"
|
|
bitfld.long 0x4 16. "SAIEN,Audio block enable" "0: SAI audio block disabled,1: SAI audio block enabled."
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|
newline
|
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bitfld.long 0x4 13. "OUTDRIV,Output drive" "0: Audio block output driven when SAIEN is set,1: Audio block output driven immediately after the.."
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|
bitfld.long 0x4 12. "MONO,Mono mode" "0: Stereo mode,1: Mono mode."
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|
newline
|
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bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable" "0: audio subblock in asynchronous mode.,1: audio subblock is synchronous with the other..,2: audio subblock is synchronous with an external..,3: FIELD Reserved"
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|
bitfld.long 0x4 9. "CKSTR,Clock strobing edge" "0: Signals generated by the SAI change on SCK..,1: Signals generated by the SAI change on SCK.."
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newline
|
|
bitfld.long 0x4 8. "LSBFIRST,Least significant bit first" "0: Data are transferred with MSB first,1: Data are transferred with LSB first"
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|
bitfld.long 0x4 5.--7. "DS,Data size" "0: FIELD Reserved,1: FIELD Reserved,2: 8 bits,3: 10 bits,4: 16 bits,5: 20 bits,6: 24 bits,7: 32 bits"
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|
newline
|
|
bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration" "0: Free protocol. Free protocol enables to use the..,1: SPDIF protocol,2: AC97 protocol,3: FIELD Reserved"
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|
bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0: Master transmitter,1: Master receiver,2: Slave transmitter,3: Slave receiver"
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|
line.long 0x8 "SAI_BCR2,SAI configuration register 2"
|
|
bitfld.long 0x8 14.--15. "COMP,Companding mode." "0: No companding algorithm,1: Reserved.,2: -Law algorithm,3: A-Law algorithm"
|
|
bitfld.long 0x8 13. "CPL,Complement bit." "0: 1s complement representation.,1: 2s complement representation."
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newline
|
|
hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter."
|
|
bitfld.long 0x8 6. "MUTEVAL,Mute value." "0: Bit value 0 is sent during the mute mode.,1: Last values are sent during the mute mode."
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|
newline
|
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bitfld.long 0x8 5. "MUTE,Mute." "0: No mute mode.,1: Mute mode enabled."
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|
bitfld.long 0x8 4. "TRIS,Tristate management on data line." "0: SD output line is still driven by the SAI when a..,1: SD output line is released (HI-Z) at the end of.."
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|
newline
|
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bitfld.long 0x8 3. "FFLUSH,FIFO flush." "0: No FIFO flush.,1: FIFO flush. Programming this bit to 1 triggers.."
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|
bitfld.long 0x8 0.--2. "FTH,FIFO threshold." "0: FIFO empty,1: FIFO,2: FIFO,3: FIFO,4: FIFO full,5: FIELD Reserved,6: FIELD Reserved,7: FIELD Reserved"
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|
line.long 0xC "SAI_BFRCR,SAI frame configuration register"
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bitfld.long 0xC 18. "FSOFF,Frame synchronization offset." "0: FS is asserted on the first bit of the slot 0.,1: FS is asserted one bit before the first bit of.."
|
|
bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity." "0: FS is active low (falling edge),1: FS is active high (rising edge)"
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|
newline
|
|
rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition." "0: FS signal is a start frame signal,1: FS signal is a start of frame signal + channel.."
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|
hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level length."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length."
|
|
line.long 0x10 "SAI_BSLOTR,SAI slot register"
|
|
hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable."
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|
hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame."
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|
newline
|
|
bitfld.long 0x10 6.--7. "SLOTSZ,Slot size" "0: The slot size is equivalent to the data size..,1: 16-bit,2: 32-bit,3: FIELD Reserved"
|
|
hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset"
|
|
line.long 0x14 "SAI_BIM,SAI interrupt mask register"
|
|
bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
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|
newline
|
|
bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable." "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "SAI_BSR,SAI status register"
|
|
bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold." "0: FIFO empty (transmitter and receiver modes),1: FIFO UNDER OR EQUAL 1/4 but not empty..,2: 1/4 < FIFO UNDER OR EQUAL 1/2 (transmitter mode)..,3: 1/2 < FIFO UNDER OR EQUAL 3/4 (transmitter mode)..,4: 3/4 < FIFO but not full (transmitter mode) 3/4..,5: FIFO full (transmitter and receiver modes),?,?"
|
|
bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0: No error.,1: Frame synchronization signal is not present at.."
|
|
newline
|
|
bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection." "0: No error.,1: Frame synchronization signal is detected earlier.."
|
|
bitfld.long 0x0 4. "CNRDY,Codec not ready." "0: External AC97 Codec is ready,1: External AC97 Codec is not ready"
|
|
newline
|
|
bitfld.long 0x0 3. "FREQ,FIFO request." "0: No FIFO request.,1: FIFO request to read or to write the SAI_xDR."
|
|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag." "0: Clock configuration is correct,1: Clock configuration does not respect the rule.."
|
|
newline
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection." "0: No MUTE detection on the SD input line,1: MUTE value detected on the SD input line (0.."
|
|
bitfld.long 0x0 0. "OVRUDR,Overrun / underrun." "0: No overrun/underrun error.,1: Overrun/underrun error detection."
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "SAI_BCLRFR,SAI clear flag register"
|
|
bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization detection flag." "0,1"
|
|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag." "0,1"
|
|
bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMUTEDET,Mute detection flag." "0,1"
|
|
bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "SAI_BDR,SAI data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
line.long 0x4 "SAI_PDMCR,SAI PDM control register"
|
|
bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number 2" "0: SAI_CK2 clock disabled,1: SAI_CK2 clock enabled"
|
|
bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number 1" "0: SAI_CK1 clock disabled,1: SAI_CK1 clock enabled"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0: Configuration with 2 microphones,1: Configuration with 4 microphones,2: Configuration with 6 microphones,3: SAI implementation for details"
|
|
bitfld.long 0x4 0. "PDMEN,PDM enable" "0: PDM interface disabled,1: PDM interface enabled"
|
|
line.long 0x8 "SAI_PDMDLY,SAI PDM delay register"
|
|
bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair 4" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair 4" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 of T<sub>SAI_CK </sub>periods"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair 3" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair 3" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
newline
|
|
bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0: No delay,1: Delay of 1 T<sub>SAI_CK </sub>period,2: Delay of 2 T<sub>SAI_CK </sub>periods,3: SAI implementation to check if it is available,?,?,?,7: Delay of 7 T<sub>SAI_CK </sub>periods"
|
|
tree.end
|
|
tree.end
|
|
tree "SBS (System Configuration/Boot/Security)"
|
|
base ad:0x58000400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SBS_BOOTSR,SBS boot status register"
|
|
hexmask.long 0x0 0.--31. 1. "INITVTOR,initial vector for Cortex-M7"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SBS_HDPLCR,SBS hide protection control register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INCR_HDPL,increment HDPL"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SBS_HDPLSR,SBS hide protection status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "HDPL,hide protection level"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SBS_DBGCR,SBS debug control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DBG_AUTH_HDPL,authenticated debug hide protection level"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DBG_UNLOCK,debug unlock"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "AP_UNLOCK,access port unlock"
|
|
line.long 0x4 "SBS_DBGLOCKR,SBS debug lock register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DBGCFG_LOCK,debug configuration lock"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "SBS_RSSCMDR,SBS RSS command register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSSCMD,RSS command"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "SBS_PMCR,SBS product mode and configuration register"
|
|
bitfld.long 0x0 28. "AXIRAM_WS,AXIRAM wait state" "0: No wait state added when accessing any AXIRAM..,1: One wait state added when accessing any AXIRAM.."
|
|
newline
|
|
bitfld.long 0x0 21.--23. "ETH_PHYSEL,Ethernet PHY interface selection" "0: GMII or MII,?,?,?,4: RMII,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 9. "BOOSTVDDSEL,booster V<sub>DD</sub> selection" "0: V<sub>DDA</sub> selected as analog switch..,1: V<sub>DD</sub> selected as analog switch booster.."
|
|
newline
|
|
bitfld.long 0x0 8. "BOOSTEN,booster enable" "0: Booster disabled,1: Booster enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "FMPLUS_PB9,Fast-mode Plus on PB(9)" "0: I2C Fast-mode Plus mode disabled on PB(9),1: Fast-mode Plus mode enabled on PB(9)"
|
|
newline
|
|
bitfld.long 0x0 6. "FMPLUS_PB8,Fast-mode Plus on PB(8)" "0: Fast-mode Plus mode disabled on PB(8),1: Fast-mode Plus mode enabled on PB(8)"
|
|
newline
|
|
bitfld.long 0x0 5. "FMPLUS_PB7,Fast-mode Plus on PB(7)" "0: Fast-mode Plus mode disabled on PB(7),1: Fast mode plus mode enabled on PB(7)"
|
|
newline
|
|
bitfld.long 0x0 4. "FMPLUS_PB6,Fast-mode Plus on PB(6)" "0: Fast-mode Plus mode disabled on PB(6),1: Fast-mode Plus mode enabled on PB(6)"
|
|
line.long 0x4 "SBS_FPUIMR,SBS FPU interrupt mask register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "FPU_IE,FPU interrupt enable"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x0 "SBS_MESR,SBS memory erase status register"
|
|
bitfld.long 0x0 0. "MEF,memory erase flag" "0: Automatic erase of BKPRAM and PKA RAM memories..,1: Automatic erase of BKPRAM and PKA RAM memories.."
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "SBS_CCCSR,SBS I/O compensation cell control and status register"
|
|
bitfld.long 0x0 18. "OCTO2_IOHSLV,XSPIM_P2 I/O high speed at low voltage" "0: No XSPIM_P2 I/O speed optimization when device..,1: XSPIM_P2 I/O speed optimized when device voltage.."
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|
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|
|
bitfld.long 0x0 17. "OCTO1_IOHSLV,XSPIM_P1 I/O high speed at low voltage" "0: No XSPIM_P1 I/O speed optimization when device..,1: XSPIM_P1 I/O speed optimized when device voltage.."
|
|
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|
|
bitfld.long 0x0 16. "IOHSLV,I/O high speed at low voltage" "0: No I/O speed optimization when device voltage is..,1: I/O speed optimized when device voltage is low.."
|
|
newline
|
|
rbitfld.long 0x0 10. "OCTO2_COMP_RDY,XSPIM_P2 compensation cell ready" "0: XSPIM_P2 I/O compensation cell not ready,1: XSPIM_P2 I/O compensation cell ready. The code.."
|
|
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|
|
rbitfld.long 0x0 9. "OCTO1_COMP_RDY,XSPIM_P1 compensation cell ready" "0: XSPIM_P1 I/O compensation cell not ready,1: XSPIM_P1 I/O compensation cell ready. The code.."
|
|
newline
|
|
rbitfld.long 0x0 8. "COMP_RDY,Compensation cell ready" "0: I/O compensation cell not ready,1: I/O compensation cell ready. The code value.."
|
|
newline
|
|
rbitfld.long 0x0 5. "OCTO2_COMP_CODESEL,XSPIM_P2 compensation cell code selection" "0: Code from the cell (available in the SBS_CCVALR),1: Code from the SBS software value register.."
|
|
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|
|
rbitfld.long 0x0 4. "OCTO2_COMP_EN,XSPIM_P2 compensation cell enable" "0: XSPIM_P2 compensation cell disabled,1: XSPIM_P2 compensation cell enabled"
|
|
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bitfld.long 0x0 3. "OCTO1_COMP_CODESEL,XSPIM_P1 compensation cell code selection" "0: Code from the cell (available in the SBS_CCVALR),1: Code from the SBS software value register.."
|
|
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bitfld.long 0x0 2. "OCTO1_COMP_EN,XSPIM_P1 compensation cell enable" "0: XSPIM_P1 compensation cell disabled,1: XSPIM_P1 compensation cell enabled"
|
|
newline
|
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bitfld.long 0x0 1. "COMP_CODESEL,Compensation cell code selection" "0: Code from the cell (available in the SBS_CCVALR),1: Code from the SBS software value register.."
|
|
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|
|
bitfld.long 0x0 0. "COMP_EN,Compensation cell enable" "0: Compensation cell disabled,1: Compensation cell enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x0 "SBS_CCVALR,SBS compensation cell for I/Os value register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "OCTO2_PSRC,XSPIM_P2 PMOS transistors slew-rate compensation"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "OCTO2_NSRC,XSPIM_P2 NMOS transistors slew-rate compensation"
|
|
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|
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hexmask.long.byte 0x0 12.--15. 1. "OCTO1_PSRC,XSPIM_P1 PMOS transistors slew-rate compensation"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "OCTO1_NSRC,XSPIM_P1 NMOS transistors slew-rate compensation"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PSRC,PMOS transistors slew-rate compensation"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "NSRC,NMOS transistors slew-rate compensation"
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "SBS_CCSWVALR,SBS compensation cell for I/Os software value register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "OCTO2_SW_PSRC,XSPIM_P2 software PMOS transistors slew-rate compensation"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "OCTO2_SW_NSRC,XSPIM_P2 software NMOS transistors slew-rate compensation"
|
|
newline
|
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hexmask.long.byte 0x0 12.--15. 1. "OCTO1_SW_PSRC,XSPIM_P1 software PMOS transistors slew-rate compensation"
|
|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "OCTO1_SW_NSRC,XSPIM_P1 software NMOS transistors slew-rate compensation"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "SW_PSRC,Software PMOS transistors slew-rate compensation"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "SW_NSRC,Software NMOS transistors slew-rate compensation"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "SBS_BKLOCKR,SBS break lockup register"
|
|
bitfld.long 0x0 23. "ARAM1ECC_BL,AXIRAM1 ECC error break lock" "0: AXIRAM1 ECC double error detection flag..,1: AXIRAM1 ECC double error detection flag.."
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|
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|
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bitfld.long 0x0 21. "ARAM3ECC_BL,AXIRAM3 ECC error break lock" "0: AXIRAM3 ECC double error detection flag..,1: AXIRAM3 ECC double error detection flag.."
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bitfld.long 0x0 14. "ITCMECC_BL,ITCM ECC error break lock" "0: ITCM ECC double error detection flag..,1: ITCM ECC double error detection flag connected.."
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|
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|
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bitfld.long 0x0 13. "DTCMECC_BL,DTCM ECC error break lock" "0: DTCM ECC double error detection flag..,1: DTCM ECC double error detection flag connected.."
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|
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|
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bitfld.long 0x0 7. "BKRAMECC_BL,Backup RAM ECC error break lock" "0: Backup RAM ECC double error detection flag..,1: Backup RAM ECC double error detection flag.."
|
|
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|
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bitfld.long 0x0 6. "CM7LCKUP_BL,Cortex-M7 lockup break lock" "0: Cortex-M7 lockup output disconnected from..,1: Cortex-M7 lockup output connected to.."
|
|
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|
|
bitfld.long 0x0 3. "FLASHECC_BL,Flash ECC error break lock" "0: FLASH ECC double error detection flag..,1: FLASH ECC double error detection flag connected.."
|
|
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|
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bitfld.long 0x0 2. "PVD_BL,PVD break lock" "0: PVD interrupt disconnected from TIM1/8/15/16/17..,1: PVD output connected to TIM1/8/15/16/17 break.."
|
|
rgroup.long 0x130++0xF
|
|
line.long 0x0 "SBS_EXTICR0,SBS external interrupt configuration register 0"
|
|
hexmask.long.byte 0x0 12.--15. 1. "PC_EXTI3,Port configuration EXTI {0 * 4 + i}"
|
|
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hexmask.long.byte 0x0 8.--11. 1. "PC_EXTI2,Port configuration EXTI {0 * 4 + i}"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "PC_EXTI1,Port configuration EXTI {0 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC_EXTI0,Port configuration EXTI {0 * 4 + i}"
|
|
line.long 0x4 "SBS_EXTICR1,SBS external interrupt configuration register 1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "PC_EXTI7,Port configuration EXTI {1 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "PC_EXTI6,Port configuration EXTI {1 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "PC_EXTI5,Port configuration EXTI {1 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "PC_EXTI4,Port configuration EXTI {1 * 4 + i}"
|
|
line.long 0x8 "SBS_EXTICR2,SBS external interrupt configuration register 2"
|
|
hexmask.long.byte 0x8 12.--15. 1. "PC_EXTI11,Port configuration EXTI {2 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "PC_EXTI10,Port configuration EXTI {2 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "PC_EXTI9,Port configuration EXTI {2 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "PC_EXTI8,Port configuration EXTI {2 * 4 + i}"
|
|
line.long 0xC "SBS_EXTICR3,SBS external interrupt configuration register 3"
|
|
hexmask.long.byte 0xC 12.--15. 1. "PC_EXTI15,Port configuration EXTI {3 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "PC_EXTI14,Port configuration EXTI {3 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "PC_EXTI13,Port configuration EXTI {3 * 4 + i}"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "PC_EXTI12,Port configuration EXTI {3 * 4 + i}"
|
|
tree.end
|
|
tree "SDMMC (Secure Digital Input/Output and MultiMediaCard Interface)"
|
|
base ad:0x0
|
|
tree "SDMMC1"
|
|
base ad:0x52007000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "SDMMC_POWER,SDMMC power control register"
|
|
bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0: Voltage transceiver IOs driven as output when..,1: Voltage transceiver IOs driven as output when.."
|
|
bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0: SDMMC_CK clock kept unchanged after successfully..,1: SDMMC_CK clock stopped after successfully.."
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|
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|
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bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0: Voltage switch sequence not started and not..,1: Voltage switch sequence started or active."
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|
bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0: After reset Reset: the SDMMC is disabled and the..,1: Reserved. (When written 01 PWRCTRL value does..,2: Power-cycle the SDMMC is disabled and the clock..,3: Power-on: the card is clocked The first 74.."
|
|
line.long 0x4 "SDMMC_CLKCR,SDMMC clock control register"
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|
bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0: sdmmc_io_in_ck selected as receive clock,1: SDMMC_CKIN feedback clock selected as receive..,2: sdmmc_fb_ck tuned feedback clock selected as..,3: Reserved (select sdmmc_io_in_ck)"
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|
bitfld.long 0x4 19. "BUSSPEED,Bus speed for selection of SDMMC operating modes" "0: DS HS SDR12 SDR25 Legacy compatible High speed..,1: SDR50 DDR50 SDR104 HS200 bus speed mode selected."
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|
newline
|
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bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0: SDR Single data rate signaling,1: DDR double data rate signaling"
|
|
bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable" "0: Hardware flow control is disabled,1: Hardware flow control is enabled"
|
|
newline
|
|
bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and command" "0: When clock division >1 (CLKDIV > 0) & DDR = 0:,1: Command changed on the same sdmmc_ker_ck rising.."
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|
bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0: Default 1-bit wide bus mode: SDMMC_D0 used (Does..,1: 4-bit wide bus mode: SDMMC_D[3:0] used,2: 8-bit wide bus mode: SDMMC_D[7:0] used,?"
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|
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|
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bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0: SDMMC_CK clock is always enabled,1: SDMMC_CK is only enabled when the bus is active"
|
|
hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor"
|
|
line.long 0x8 "SDMMC_ARGR,SDMMC argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument"
|
|
line.long 0xC "SDMMC_CMDR,SDMMC command register"
|
|
bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1"
|
|
bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0: Boot mode procedure disabled,1: Boot mode procedure enabled"
|
|
newline
|
|
bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0: Normal boot mode procedure selected,1: Alternative boot mode procedure selected."
|
|
bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) enable bit" "0,1"
|
|
bitfld.long 0xC 11. "WAITPEND,CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1"
|
|
bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0: No response expect CMDSENT flag,1: Short response expect CMDREND or CCRCFAIL flag,2: Short response expect CMDREND flag (No CRC),3: Long response expect CMDREND or CCRCFAIL flag"
|
|
newline
|
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bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" "0,1"
|
|
bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index"
|
|
rgroup.long 0x10++0x13
|
|
line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index"
|
|
line.long 0x4 "SDMMC_RESP1R,SDMMC response 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
line.long 0x8 "SDMMC_RESP2R,SDMMC response 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
line.long 0xC "SDMMC_RESP3R,SDMMC response 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
line.long 0x10 "SDMMC_RESP4R,SDMMC response 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "SDMMC_DTIMER,SDMMC data timer register"
|
|
hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period"
|
|
line.long 0x4 "SDMMC_DLENR,SDMMC data length register"
|
|
hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value"
|
|
line.long 0x8 "SDMMC_DCTRL,SDMMC data control register"
|
|
bitfld.long 0x8 13. "FIFORST,FIFO reset flushes any remaining data" "0: FIFO not affected.,1: Flush any remaining data and reset the FIFO.."
|
|
bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0: Boot acknowledgment disabled not expected to be..,1: Boot acknowledgment enabled expected to be.."
|
|
newline
|
|
bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions" "0,1"
|
|
bitfld.long 0x8 10. "RWMOD,Read Wait mode" "0: Read Wait control using SDMMC_D2,1: Read Wait control stopping SDMMC_CK"
|
|
newline
|
|
bitfld.long 0x8 9. "RWSTOP,Read Wait stop" "0: No Read Wait stop.,1: Enable for Read Wait stop when DPSM is in the.."
|
|
bitfld.long 0x8 8. "RWSTART,Read Wait start" "0,1"
|
|
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|
|
hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size"
|
|
bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0: Block data transfer ending on block count.,1: SDIO multibyte data transfer.,2: e.MMC Stream data transfer. (WIDBUS must select..,3: Block data transfer ending with.."
|
|
newline
|
|
bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0: From host to card.,1: From card to host."
|
|
bitfld.long 0x8 0. "DTEN,Data transfer enable bit" "0: Do not start data transfer without CPSM data..,1: Start data transfer without CPSM data transfer.."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SDMMC_DCNTR,SDMMC data counter register"
|
|
hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value"
|
|
line.long 0x4 "SDMMC_STAR,SDMMC status register"
|
|
bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1"
|
|
bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1"
|
|
bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1"
|
|
bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1"
|
|
bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0: card SDMMC_D0 signal does NOT signal change from..,1: card SDMMC_D0 signal changed from busy to NOT.."
|
|
newline
|
|
bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0: card signals not busy on SDMMC_D0.,1: card signals busy on SDMMC_D0."
|
|
bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1"
|
|
bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1"
|
|
bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1"
|
|
bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1"
|
|
bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1"
|
|
bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1"
|
|
bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1"
|
|
bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1"
|
|
bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1"
|
|
group.long 0x38++0xB
|
|
line.long 0x0 "SDMMC_ICR,SDMMC interrupt clear register"
|
|
bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0: IDMABTC not cleared,1: IDMABTC cleared"
|
|
bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0: IDMATE not cleared,1: IDMATE cleared"
|
|
newline
|
|
bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0: CKSTOP not cleared,1: CKSTOP cleared"
|
|
bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0: VSWEND not cleared,1: VSWEND cleared"
|
|
newline
|
|
bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0: ACKTIMEOUT not cleared,1: ACKTIMEOUT cleared"
|
|
bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0: ACKFAIL not cleared,1: ACKFAIL cleared"
|
|
newline
|
|
bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0: SDIOIT not cleared,1: SDIOIT cleared"
|
|
bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0: BUSYD0END not cleared,1: BUSYD0END cleared"
|
|
newline
|
|
bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0: DABORT not cleared,1: DABORT cleared"
|
|
bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0: DBCKEND not cleared,1: DBCKEND cleared"
|
|
newline
|
|
bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0: DHOLD not cleared,1: DHOLD cleared"
|
|
bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0: DATAEND not cleared,1: DATAEND cleared"
|
|
newline
|
|
bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0: CMDSENT not cleared,1: CMDSENT cleared"
|
|
bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0: CMDREND not cleared,1: CMDREND cleared"
|
|
newline
|
|
bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0: RXOVERR not cleared,1: RXOVERR cleared"
|
|
bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0: TXUNDERR not cleared,1: TXUNDERR cleared"
|
|
newline
|
|
bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0: DTIMEOUT not cleared,1: DTIMEOUT cleared"
|
|
bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0: CTIMEOUT not cleared,1: CTIMEOUT cleared"
|
|
newline
|
|
bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0: DCRCFAIL not cleared,1: DCRCFAIL cleared"
|
|
bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0: CCRCFAIL not cleared,1: CCRCFAIL cleared"
|
|
line.long 0x4 "SDMMC_MASKR,SDMMC mask register"
|
|
bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0: IDMA buffer transfer complete interrupt disabled,1: IDMA buffer transfer complete interrupt enabled"
|
|
bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0: Voltage Switch clock stopped interrupt disabled,1: Voltage Switch clock stopped interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0: Voltage switch critical timing section..,1: Voltage switch critical timing section.."
|
|
bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0: Acknowledgment timeout interrupt disabled,1: Acknowledgment timeout interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0: Acknowledgment Fail interrupt disabled,1: Acknowledgment Fail interrupt enabled"
|
|
bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0: SDIO Mode interrupt received interrupt disabled,1: SDIO Mode interrupt received interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0: BUSYD0END interrupt disabled,1: BUSYD0END interrupt enabled"
|
|
bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0: Tx FIFO empty interrupt disabled,1: Tx FIFO empty interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0: Rx FIFO full interrupt disabled,1: Rx FIFO full interrupt enabled"
|
|
bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0: Rx FIFO half full interrupt disabled,1: Rx FIFO half full interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0: Tx FIFO half empty interrupt disabled,1: Tx FIFO half empty interrupt enabled"
|
|
bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0: Data transfer abort interrupt disabled,1: Data transfer abort interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0: Data block end interrupt disabled,1: Data block end interrupt enabled"
|
|
bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0: Data hold interrupt disabled,1: Data hold interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0: Data end interrupt disabled,1: Data end interrupt enabled"
|
|
bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0: Command sent interrupt disabled,1: Command sent interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0: Command response received interrupt disabled,1: command Response received interrupt enabled"
|
|
bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0: Rx FIFO overrun error interrupt disabled,1: Rx FIFO overrun error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0: Tx FIFO underrun error interrupt disabled,1: Tx FIFO underrun error interrupt enabled"
|
|
bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0: Data timeout interrupt disabled,1: Data timeout interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0: Command timeout interrupt disabled,1: Command timeout interrupt enabled"
|
|
bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0: Data CRC fail interrupt disabled,1: Data CRC fail interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0: Command CRC fail interrupt disabled,1: Command CRC fail interrupt enabled"
|
|
line.long 0x8 "SDMMC_ACKTIMER,SDMMC acknowledgment timer register"
|
|
hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "SDMMC_IDMACTRLR,SDMMC DMA control register"
|
|
bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection" "0: Single buffer mode.,1: Linked list mode."
|
|
bitfld.long 0x0 0. "IDMAEN,IDMA enable" "0: IDMA disabled,1: IDMA enabled"
|
|
line.long 0x4 "SDMMC_IDMABSIZER,SDMMC IDMA buffer size register"
|
|
hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer"
|
|
line.long 0x8 "SDMMC_IDMABASER,SDMMC IDMA buffer base address register"
|
|
hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] must be word aligned (bit [1:0] are always 0 and read only)"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register"
|
|
bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0: SDMMC_IDMALAR is not to be updated last linked..,1: SDMMC_IDMALAR is to be updated from linked list.."
|
|
bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0: SDMMC_IDMABSIZER is not to be updated from next..,1: SDMMC_IDMABSIZER is to be updated from next.."
|
|
newline
|
|
bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0: Loaded linked list buffer is not ready (this..,1: Loaded linked list buffer ready acknowledge."
|
|
hexmask.long.word 0x0 2.--15. 1. "IDMALA,Word aligned linked list item address offset"
|
|
line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register"
|
|
hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address"
|
|
group.long 0x80++0x3F
|
|
line.long 0x0 "SDMMC_FIFOR0,SDMMC data FIFO registers 0"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x4 "SDMMC_FIFOR1,SDMMC data FIFO registers 1"
|
|
hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x8 "SDMMC_FIFOR2,SDMMC data FIFO registers 2"
|
|
hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0xC "SDMMC_FIFOR3,SDMMC data FIFO registers 3"
|
|
hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x10 "SDMMC_FIFOR4,SDMMC data FIFO registers 4"
|
|
hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x14 "SDMMC_FIFOR5,SDMMC data FIFO registers 5"
|
|
hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x18 "SDMMC_FIFOR6,SDMMC data FIFO registers 6"
|
|
hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x1C "SDMMC_FIFOR7,SDMMC data FIFO registers 7"
|
|
hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x20 "SDMMC_FIFOR8,SDMMC data FIFO registers 8"
|
|
hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x24 "SDMMC_FIFOR9,SDMMC data FIFO registers 9"
|
|
hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x28 "SDMMC_FIFOR10,SDMMC data FIFO registers 10"
|
|
hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x2C "SDMMC_FIFOR11,SDMMC data FIFO registers 11"
|
|
hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x30 "SDMMC_FIFOR12,SDMMC data FIFO registers 12"
|
|
hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x34 "SDMMC_FIFOR13,SDMMC data FIFO registers 13"
|
|
hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x38 "SDMMC_FIFOR14,SDMMC data FIFO registers 14"
|
|
hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x3C "SDMMC_FIFOR15,SDMMC data FIFO registers 15"
|
|
hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
tree.end
|
|
tree "SDMMC2"
|
|
base ad:0x48002400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "SDMMC_POWER,SDMMC power control register"
|
|
bitfld.long 0x0 4. "DIRPOL,Data and command direction signals polarity selection" "0: Voltage transceiver IOs driven as output when..,1: Voltage transceiver IOs driven as output when.."
|
|
bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable" "0: SDMMC_CK clock kept unchanged after successfully..,1: SDMMC_CK clock stopped after successfully.."
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|
newline
|
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bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start" "0: Voltage switch sequence not started and not..,1: Voltage switch sequence started or active."
|
|
bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits" "0: After reset Reset: the SDMMC is disabled and the..,1: Reserved. (When written 01 PWRCTRL value does..,2: Power-cycle the SDMMC is disabled and the clock..,3: Power-on: the card is clocked The first 74.."
|
|
line.long 0x4 "SDMMC_CLKCR,SDMMC clock control register"
|
|
bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection" "0: sdmmc_io_in_ck selected as receive clock,1: SDMMC_CKIN feedback clock selected as receive..,2: sdmmc_fb_ck tuned feedback clock selected as..,3: Reserved (select sdmmc_io_in_ck)"
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|
bitfld.long 0x4 19. "BUSSPEED,Bus speed for selection of SDMMC operating modes" "0: DS HS SDR12 SDR25 Legacy compatible High speed..,1: SDR50 DDR50 SDR104 HS200 bus speed mode selected."
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|
newline
|
|
bitfld.long 0x4 18. "DDR,Data rate signaling selection" "0: SDR Single data rate signaling,1: DDR double data rate signaling"
|
|
bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable" "0: Hardware flow control is disabled,1: Hardware flow control is enabled"
|
|
newline
|
|
bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and command" "0: When clock division >1 (CLKDIV > 0) & DDR = 0:,1: Command changed on the same sdmmc_ker_ck rising.."
|
|
bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit" "0: Default 1-bit wide bus mode: SDMMC_D0 used (Does..,1: 4-bit wide bus mode: SDMMC_D[3:0] used,2: 8-bit wide bus mode: SDMMC_D[7:0] used,?"
|
|
newline
|
|
bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit" "0: SDMMC_CK clock is always enabled,1: SDMMC_CK is only enabled when the bus is active"
|
|
hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor"
|
|
line.long 0x8 "SDMMC_ARGR,SDMMC argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument"
|
|
line.long 0xC "SDMMC_CMDR,SDMMC command register"
|
|
bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1"
|
|
bitfld.long 0xC 15. "BOOTEN,Enable boot mode procedure" "0: Boot mode procedure disabled,1: Boot mode procedure enabled"
|
|
newline
|
|
bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be used" "0: Normal boot mode procedure selected,1: Alternative boot mode procedure selected."
|
|
bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) enable bit" "0,1"
|
|
bitfld.long 0xC 11. "WAITPEND,CPSM waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request" "0,1"
|
|
bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits" "0: No response expect CMDSENT flag,1: Short response expect CMDREND or CCRCFAIL flag,2: Short response expect CMDREND flag (No CRC),3: Long response expect CMDREND or CCRCFAIL flag"
|
|
newline
|
|
bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM" "0,1"
|
|
bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index"
|
|
rgroup.long 0x10++0x13
|
|
line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index"
|
|
line.long 0x4 "SDMMC_RESP1R,SDMMC response 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
line.long 0x8 "SDMMC_RESP2R,SDMMC response 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
line.long 0xC "SDMMC_RESP3R,SDMMC response 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
line.long 0x10 "SDMMC_RESP4R,SDMMC response 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "CARDSTATUS,Card status according table below"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "SDMMC_DTIMER,SDMMC data timer register"
|
|
hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period"
|
|
line.long 0x4 "SDMMC_DLENR,SDMMC data length register"
|
|
hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value"
|
|
line.long 0x8 "SDMMC_DCTRL,SDMMC data control register"
|
|
bitfld.long 0x8 13. "FIFORST,FIFO reset flushes any remaining data" "0: FIFO not affected.,1: Flush any remaining data and reset the FIFO.."
|
|
bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0: Boot acknowledgment disabled not expected to be..,1: Boot acknowledgment enabled expected to be.."
|
|
newline
|
|
bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions" "0,1"
|
|
bitfld.long 0x8 10. "RWMOD,Read Wait mode" "0: Read Wait control using SDMMC_D2,1: Read Wait control stopping SDMMC_CK"
|
|
newline
|
|
bitfld.long 0x8 9. "RWSTOP,Read Wait stop" "0: No Read Wait stop.,1: Enable for Read Wait stop when DPSM is in the.."
|
|
bitfld.long 0x8 8. "RWSTART,Read Wait start" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size"
|
|
bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection" "0: Block data transfer ending on block count.,1: SDIO multibyte data transfer.,2: e.MMC Stream data transfer. (WIDBUS must select..,3: Block data transfer ending with.."
|
|
newline
|
|
bitfld.long 0x8 1. "DTDIR,Data transfer direction selection" "0: From host to card.,1: From card to host."
|
|
bitfld.long 0x8 0. "DTEN,Data transfer enable bit" "0: Do not start data transfer without CPSM data..,1: Start data transfer without CPSM data transfer.."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SDMMC_DCNTR,SDMMC data counter register"
|
|
hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value"
|
|
line.long 0x4 "SDMMC_STAR,SDMMC status register"
|
|
bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete" "0,1"
|
|
bitfld.long 0x4 27. "IDMATE,IDMA transfer error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1"
|
|
bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section completion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1"
|
|
bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received" "0,1"
|
|
bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0: card SDMMC_D0 signal does NOT signal change from..,1: card SDMMC_D0 signal changed from busy to NOT.."
|
|
newline
|
|
bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0: card signals not busy on SDMMC_D0.,1: card signals busy on SDMMC_D0."
|
|
bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty" "0,1"
|
|
bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full" "0,1"
|
|
bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty" "0,1"
|
|
bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e. not in Idle state" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not in Idle state" "0,1"
|
|
bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DBCKEND,Data block sent/received" "0,1"
|
|
bitfld.long 0x4 9. "DHOLD,Data transfer Hold" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly" "0,1"
|
|
bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1"
|
|
bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error (masked by hardware when IDMA is enabled)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error (masked by hardware when IDMA is enabled)" "0,1"
|
|
bitfld.long 0x4 3. "DTIMEOUT,Data timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CTIMEOUT,Command response timeout" "0,1"
|
|
bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1"
|
|
group.long 0x38++0xB
|
|
line.long 0x0 "SDMMC_ICR,SDMMC interrupt clear register"
|
|
bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0: IDMABTC not cleared,1: IDMABTC cleared"
|
|
bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit" "0: IDMATE not cleared,1: IDMATE cleared"
|
|
newline
|
|
bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit" "0: CKSTOP not cleared,1: CKSTOP cleared"
|
|
bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit" "0: VSWEND not cleared,1: VSWEND cleared"
|
|
newline
|
|
bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit" "0: ACKTIMEOUT not cleared,1: ACKTIMEOUT cleared"
|
|
bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit" "0: ACKFAIL not cleared,1: ACKFAIL cleared"
|
|
newline
|
|
bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit" "0: SDIOIT not cleared,1: SDIOIT cleared"
|
|
bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit" "0: BUSYD0END not cleared,1: BUSYD0END cleared"
|
|
newline
|
|
bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit" "0: DABORT not cleared,1: DABORT cleared"
|
|
bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit" "0: DBCKEND not cleared,1: DBCKEND cleared"
|
|
newline
|
|
bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit" "0: DHOLD not cleared,1: DHOLD cleared"
|
|
bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit" "0: DATAEND not cleared,1: DATAEND cleared"
|
|
newline
|
|
bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit" "0: CMDSENT not cleared,1: CMDSENT cleared"
|
|
bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit" "0: CMDREND not cleared,1: CMDREND cleared"
|
|
newline
|
|
bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit" "0: RXOVERR not cleared,1: RXOVERR cleared"
|
|
bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit" "0: TXUNDERR not cleared,1: TXUNDERR cleared"
|
|
newline
|
|
bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit" "0: DTIMEOUT not cleared,1: DTIMEOUT cleared"
|
|
bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit" "0: CTIMEOUT not cleared,1: CTIMEOUT cleared"
|
|
newline
|
|
bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit" "0: DCRCFAIL not cleared,1: DCRCFAIL cleared"
|
|
bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit" "0: CCRCFAIL not cleared,1: CCRCFAIL cleared"
|
|
line.long 0x4 "SDMMC_MASKR,SDMMC mask register"
|
|
bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable" "0: IDMA buffer transfer complete interrupt disabled,1: IDMA buffer transfer complete interrupt enabled"
|
|
bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable" "0: Voltage Switch clock stopped interrupt disabled,1: Voltage Switch clock stopped interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable" "0: Voltage switch critical timing section..,1: Voltage switch critical timing section.."
|
|
bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0: Acknowledgment timeout interrupt disabled,1: Acknowledgment timeout interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable" "0: Acknowledgment Fail interrupt disabled,1: Acknowledgment Fail interrupt enabled"
|
|
bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt enable" "0: SDIO Mode interrupt received interrupt disabled,1: SDIO Mode interrupt received interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable" "0: BUSYD0END interrupt disabled,1: BUSYD0END interrupt enabled"
|
|
bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable" "0: Tx FIFO empty interrupt disabled,1: Tx FIFO empty interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable" "0: Rx FIFO full interrupt disabled,1: Rx FIFO full interrupt enabled"
|
|
bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable" "0: Rx FIFO half full interrupt disabled,1: Rx FIFO half full interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable" "0: Tx FIFO half empty interrupt disabled,1: Tx FIFO half empty interrupt enabled"
|
|
bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0: Data transfer abort interrupt disabled,1: Data transfer abort interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable" "0: Data block end interrupt disabled,1: Data block end interrupt enabled"
|
|
bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable" "0: Data hold interrupt disabled,1: Data hold interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable" "0: Data end interrupt disabled,1: Data end interrupt enabled"
|
|
bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable" "0: Command sent interrupt disabled,1: Command sent interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt enable" "0: Command response received interrupt disabled,1: command Response received interrupt enabled"
|
|
bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0: Rx FIFO overrun error interrupt disabled,1: Rx FIFO overrun error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0: Tx FIFO underrun error interrupt disabled,1: Tx FIFO underrun error interrupt enabled"
|
|
bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable" "0: Data timeout interrupt disabled,1: Data timeout interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable" "0: Command timeout interrupt disabled,1: Command timeout interrupt enabled"
|
|
bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable" "0: Data CRC fail interrupt disabled,1: Data CRC fail interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable" "0: Command CRC fail interrupt disabled,1: Command CRC fail interrupt enabled"
|
|
line.long 0x8 "SDMMC_ACKTIMER,SDMMC acknowledgment timer register"
|
|
hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "SDMMC_IDMACTRLR,SDMMC DMA control register"
|
|
bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection" "0: Single buffer mode.,1: Linked list mode."
|
|
bitfld.long 0x0 0. "IDMAEN,IDMA enable" "0: IDMA disabled,1: IDMA enabled"
|
|
line.long 0x4 "SDMMC_IDMABSIZER,SDMMC IDMA buffer size register"
|
|
hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,Number of bytes per buffer"
|
|
line.long 0x8 "SDMMC_IDMABASER,SDMMC IDMA buffer base address register"
|
|
hexmask.long 0x8 0.--31. 1. "IDMABASE,Buffer memory base address bits [31:2] must be word aligned (bit [1:0] are always 0 and read only)"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register"
|
|
bitfld.long 0x0 31. "ULA,Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)" "0: SDMMC_IDMALAR is not to be updated last linked..,1: SDMMC_IDMALAR is to be updated from linked list.."
|
|
bitfld.long 0x0 30. "ULS,Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)" "0: SDMMC_IDMABSIZER is not to be updated from next..,1: SDMMC_IDMABSIZER is to be updated from next.."
|
|
newline
|
|
bitfld.long 0x0 29. "ABR,Acknowledge linked list buffer ready" "0: Loaded linked list buffer is not ready (this..,1: Loaded linked list buffer ready acknowledge."
|
|
hexmask.long.word 0x0 2.--15. 1. "IDMALA,Word aligned linked list item address offset"
|
|
line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register"
|
|
hexmask.long 0x4 2.--31. 1. "IDMABA,Word aligned Linked list memory base address"
|
|
group.long 0x80++0x3F
|
|
line.long 0x0 "SDMMC_FIFOR0,SDMMC data FIFO registers 0"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x4 "SDMMC_FIFOR1,SDMMC data FIFO registers 1"
|
|
hexmask.long 0x4 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x8 "SDMMC_FIFOR2,SDMMC data FIFO registers 2"
|
|
hexmask.long 0x8 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0xC "SDMMC_FIFOR3,SDMMC data FIFO registers 3"
|
|
hexmask.long 0xC 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x10 "SDMMC_FIFOR4,SDMMC data FIFO registers 4"
|
|
hexmask.long 0x10 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x14 "SDMMC_FIFOR5,SDMMC data FIFO registers 5"
|
|
hexmask.long 0x14 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x18 "SDMMC_FIFOR6,SDMMC data FIFO registers 6"
|
|
hexmask.long 0x18 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x1C "SDMMC_FIFOR7,SDMMC data FIFO registers 7"
|
|
hexmask.long 0x1C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x20 "SDMMC_FIFOR8,SDMMC data FIFO registers 8"
|
|
hexmask.long 0x20 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x24 "SDMMC_FIFOR9,SDMMC data FIFO registers 9"
|
|
hexmask.long 0x24 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x28 "SDMMC_FIFOR10,SDMMC data FIFO registers 10"
|
|
hexmask.long 0x28 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x2C "SDMMC_FIFOR11,SDMMC data FIFO registers 11"
|
|
hexmask.long 0x2C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x30 "SDMMC_FIFOR12,SDMMC data FIFO registers 12"
|
|
hexmask.long 0x30 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x34 "SDMMC_FIFOR13,SDMMC data FIFO registers 13"
|
|
hexmask.long 0x34 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x38 "SDMMC_FIFOR14,SDMMC data FIFO registers 14"
|
|
hexmask.long 0x38 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
line.long 0x3C "SDMMC_FIFOR15,SDMMC data FIFO registers 15"
|
|
hexmask.long 0x3C 0.--31. 1. "FIFODATA,Receive and transmit FIFO data"
|
|
tree.end
|
|
tree.end
|
|
tree "SPDIFRX (SPDIF receiver interface)"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "SPDIFRX_CR,SPDIFRX control register"
|
|
bitfld.long 0x0 21. "CKSBKPEN,Backup symbol clock enable" "0: The SPDIFRX does not generate a backup symbol..,1: The SPDIFRX generates a backup symbol clock if.."
|
|
bitfld.long 0x0 20. "CKSEN,Symbol clock enable" "0: The SPDIFRX does not generate a symbol clock.,1: The SPDIFRX generates a symbol clock."
|
|
newline
|
|
bitfld.long 0x0 16.--18. "INSEL,SPDIFRX input selection" "0: SPDIFRX_IN1 selected,1: SPDIFRX_IN2 selected,2: SPDIFRX_IN3 selected,3: SPDIFRX_IN4 selected,?,?,?,?"
|
|
bitfld.long 0x0 14. "WFA,Wait for activity<sup>(1)</sup>" "0: The SPDIFRX does not wait for activity on..,1: The SPDIFRX waits for activity on SPDIFRX_IN.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBTR,Maximum allowed re-tries during synchronization phase<sup>(1)</sup>" "0: No re-try is allowed (only one attempt),1: 3 re-tries allowed,2: 15 re-tries allowed,3: 63 re-tries allowed"
|
|
bitfld.long 0x0 11. "CHSEL,Channel selection<sup>(1)</sup>" "0: The control flow takes the channel status from..,1: The control flow takes the channel status from.."
|
|
newline
|
|
bitfld.long 0x0 10. "CBDMAEN,Control buffer DMA enable for control flow<sup>(1)</sup>" "0: DMA mode is disabled for reception of channel..,1: DMA mode is enabled for reception of channel.."
|
|
bitfld.long 0x0 9. "PTMSK,Mask of preamble type bits<sup>(1)</sup>" "0: The preamble type bits are copied into the..,1: The preamble type bits are not copied into the.."
|
|
newline
|
|
bitfld.long 0x0 8. "CUMSK,Mask of channel status and user bits<sup>(1)</sup>" "0: The channel status and user bits are copied into..,1: The channel status and user bits are not copied.."
|
|
bitfld.long 0x0 7. "VMSK,Mask of validity bit<sup>(1)</sup>" "0: The validity bit is copied into the..,1: The validity bit is not copied into the.."
|
|
newline
|
|
bitfld.long 0x0 6. "PMSK,Mask parity error bit<sup>(1)</sup>" "0: The parity error bit is copied into the..,1: The parity error bit is not copied into the.."
|
|
bitfld.long 0x0 4.--5. "DRFMT,RX data format<sup>(1)</sup>" "0: Data samples are aligned in the right (LSB).,1: Data samples are aligned in the left (MSB),2: Data sample are packed by setting two 16-bit..,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 3. "RXSTEO,Stereo mode<sup>(1)</sup>" "0: The peripheral is in mono mode.,1: The peripheral is in stereo mode."
|
|
bitfld.long 0x0 2. "RXDMAEN,Receiver DMA enable for data flow<sup>(1)</sup>" "0: DMA mode is disabled for reception.,1: DMA mode is enabled for reception."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SPDIFRXEN,Peripheral block enable<sup>(1)</sup>" "0: Disable SPDIFRX (STATE_IDLE).,1: Enable SPDIFRX synchronization only.,2: FIELD Reserved,3: Enable SPDIF receiver."
|
|
line.long 0x4 "SPDIFRX_IMR,SPDIFRX interrupt mask register"
|
|
bitfld.long 0x4 6. "IFEIE,Serial interface error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
bitfld.long 0x4 5. "SYNCDIE,Synchronization done" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 4. "SBLKIE,Synchronization block detected interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
bitfld.long 0x4 3. "OVRIE,Overrun error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 2. "PERRIE,Parity error interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
bitfld.long 0x4 1. "CSRNEIE,Control buffer ready interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 0. "RXNEIE,RXNE interrupt enable" "0: Interrupt is inhibited.,1: A SPDIFRX interface interrupt is generated.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SPDIFRX_SR,SPDIFRX status register"
|
|
hexmask.long.word 0x0 16.--30. 1. "WIDTH5,duration of 5 symbols counted with spdifrx_ker_ck"
|
|
bitfld.long 0x0 8. "TERR,Time-out error" "0: No sequence error is detected.,1: Sequence error is detected."
|
|
newline
|
|
bitfld.long 0x0 7. "SERR,Synchronization error" "0: No synchronization error is detected.,1: Synchronization error is detected."
|
|
bitfld.long 0x0 6. "FERR,Framing error" "0: No Manchester violation detected,1: Manchester violation detected"
|
|
newline
|
|
bitfld.long 0x0 5. "SYNCD,Synchronization done" "0: Synchronization is pending.,1: Synchronization is completed."
|
|
bitfld.long 0x0 4. "SBD,Synchronization block detected" "0: No B preamble is detected.,1: B preamble is detected."
|
|
newline
|
|
bitfld.long 0x0 3. "OVR,Overrun error" "0: No overrun error,1: Overrun error is detected."
|
|
bitfld.long 0x0 2. "PERR,Parity error" "0: No parity error,1: Parity error"
|
|
newline
|
|
bitfld.long 0x0 1. "CSRNE,Control buffer register not empty" "0: No control word available on SPDIFRX_CSR register,1: A control word is available on SPDIFRX_CSR.."
|
|
bitfld.long 0x0 0. "RXNE,Read data register not empty" "0: Data is not received.,1: Received data is ready to be read."
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "SPDIFRX_IFCR,SPDIFRX interrupt flag clear register"
|
|
bitfld.long 0x0 5. "SYNCDCF,clears the synchronization done flag" "0,1"
|
|
bitfld.long 0x0 4. "SBDCF,clears the synchronization block detected flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRCF,clears the overrun error flag" "0,1"
|
|
bitfld.long 0x0 2. "PERRCF,clears the parity error flag" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SPDIFRX_FMT0_DR,SPDIFRX data input register"
|
|
bitfld.long 0x0 28.--29. "PT,preamble type" "0: not used,1: Preamble B received,2: Preamble M received,3: Preamble W received"
|
|
bitfld.long 0x0 27. "C,channel status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "U,user bit" "0,1"
|
|
bitfld.long 0x0 25. "V,validity bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PE,parity error bit" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DR,data value"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SPDIFRX_FMT0_DR_alternate1,SPDIFRX data input register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "DR,data value"
|
|
bitfld.long 0x0 4.--5. "PT,preamble type" "0: not used,1: preamble B received,2: preamble M received,3: preamble W received"
|
|
newline
|
|
bitfld.long 0x0 3. "C,channel Status bit" "0,1"
|
|
bitfld.long 0x0 2. "U,user bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "V,validity bit" "0,1"
|
|
bitfld.long 0x0 0. "PE,parity error bit" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "SPDIFRX_FMT0_DR_alternate2,SPDIFRX data input register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DRNL2,data value"
|
|
hexmask.long.word 0x0 0.--15. 1. "DRNL1,data value"
|
|
line.long 0x4 "SPDIFRX_CSR,SPDIFRX channel status register"
|
|
bitfld.long 0x4 24. "SOB,start of block" "0: CS[0] is not the first bit of a new block,1: CS[0] is the first bit of a new block"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CS,channel A status information"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "USR,user data information"
|
|
line.long 0x8 "SPDIFRX_DIR,SPDIFRX debug information register"
|
|
hexmask.long.word 0x8 16.--28. 1. "TLO,threshold LOW (TLO = 1.5 x UI / T<sub>spdifrx_ker_ck</sub>)"
|
|
hexmask.long.word 0x8 0.--12. 1. "THI,threshold HIGH (THI = 2.5 x UI / T<sub>spdifrx_ker_ck</sub>)"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI1"
|
|
base ad:0x42003000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CR1,SPI/I2S control register 1"
|
|
bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked"
|
|
bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied"
|
|
newline
|
|
bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied"
|
|
bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.."
|
|
newline
|
|
bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1"
|
|
bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter"
|
|
newline
|
|
bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1"
|
|
bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.."
|
|
newline
|
|
bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.."
|
|
bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled"
|
|
line.long 0x4 "SPI_CR2,SPI/I2S control register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer"
|
|
line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1"
|
|
bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled"
|
|
bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: TI mode,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256"
|
|
newline
|
|
bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared"
|
|
newline
|
|
bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled"
|
|
bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master."
|
|
hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame"
|
|
line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2"
|
|
bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.."
|
|
bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.."
|
|
newline
|
|
bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.."
|
|
bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal"
|
|
newline
|
|
bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit"
|
|
bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle"
|
|
newline
|
|
bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.."
|
|
bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first"
|
|
newline
|
|
bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master"
|
|
bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?"
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|
newline
|
|
bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex"
|
|
bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped"
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|
newline
|
|
bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.."
|
|
bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.."
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness"
|
|
line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register"
|
|
bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled"
|
|
bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled"
|
|
bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled"
|
|
bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled"
|
|
bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled"
|
|
bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_SR,SPI/I2S status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session"
|
|
bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.."
|
|
newline
|
|
bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*"
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|
bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete"
|
|
newline
|
|
bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.."
|
|
bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected."
|
|
newline
|
|
bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected"
|
|
bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected"
|
|
bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected"
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|
newline
|
|
bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished"
|
|
bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete"
|
|
newline
|
|
bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.."
|
|
bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.."
|
|
newline
|
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bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet"
|
|
wgroup.long 0x18++0x3
|
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line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register"
|
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bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1"
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|
bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1"
|
|
bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1"
|
|
bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1"
|
|
bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register"
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hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register"
|
|
rgroup.long 0x30++0x3
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line.long 0x0 "SPI_RXDR,SPI/I2S receive data register"
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hexmask.long 0x0 0.--31. 1. "RXDR,receive data register"
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group.long 0x40++0x3
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line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register"
|
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hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
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rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter"
|
|
line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register"
|
|
hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition"
|
|
line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register"
|
|
bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
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|
bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
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hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I<sup>2</sup>S linear prescaler"
|
|
bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.."
|
|
newline
|
|
bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.."
|
|
bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.."
|
|
newline
|
|
bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.."
|
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bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
newline
|
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bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 80.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.."
|
|
bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I<sup>2</sup>S standard selection" "0: I<sup>2</sup>S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
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|
bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?"
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|
newline
|
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bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected"
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|
tree.end
|
|
tree "SPI2"
|
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base ad:0x40003800
|
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group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CR1,SPI/I2S control register 1"
|
|
bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked"
|
|
bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied"
|
|
newline
|
|
bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied"
|
|
bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.."
|
|
newline
|
|
bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1"
|
|
bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter"
|
|
newline
|
|
bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1"
|
|
bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.."
|
|
newline
|
|
bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.."
|
|
bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled"
|
|
line.long 0x4 "SPI_CR2,SPI/I2S control register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer"
|
|
line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1"
|
|
bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled"
|
|
bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: TI mode,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256"
|
|
newline
|
|
bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared"
|
|
newline
|
|
bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled"
|
|
bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master."
|
|
hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame"
|
|
line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2"
|
|
bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.."
|
|
bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.."
|
|
newline
|
|
bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.."
|
|
bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal"
|
|
newline
|
|
bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit"
|
|
bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle"
|
|
newline
|
|
bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.."
|
|
bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first"
|
|
newline
|
|
bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master"
|
|
bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex"
|
|
bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped"
|
|
newline
|
|
bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.."
|
|
bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.."
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness"
|
|
line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register"
|
|
bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled"
|
|
bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled"
|
|
bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled"
|
|
bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled"
|
|
bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled"
|
|
bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_SR,SPI/I2S status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session"
|
|
bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.."
|
|
newline
|
|
bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*"
|
|
bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete"
|
|
newline
|
|
bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.."
|
|
bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected."
|
|
newline
|
|
bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected"
|
|
bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected"
|
|
bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished"
|
|
bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete"
|
|
newline
|
|
bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.."
|
|
bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register"
|
|
bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1"
|
|
bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1"
|
|
bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1"
|
|
bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1"
|
|
bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register"
|
|
hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RXDR,SPI/I2S receive data register"
|
|
hexmask.long 0x0 0.--31. 1. "RXDR,receive data register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter"
|
|
line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register"
|
|
hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition"
|
|
line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register"
|
|
bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I<sup>2</sup>S linear prescaler"
|
|
bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.."
|
|
newline
|
|
bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.."
|
|
bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.."
|
|
newline
|
|
bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.."
|
|
bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 80.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.."
|
|
bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I<sup>2</sup>S standard selection" "0: I<sup>2</sup>S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
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|
bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?"
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|
newline
|
|
bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected"
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40003C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CR1,SPI/I2S control register 1"
|
|
bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked"
|
|
bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied"
|
|
newline
|
|
bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied"
|
|
bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.."
|
|
newline
|
|
bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1"
|
|
bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter"
|
|
newline
|
|
bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1"
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|
bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.."
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|
newline
|
|
bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.."
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|
bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled"
|
|
line.long 0x4 "SPI_CR2,SPI/I2S control register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer"
|
|
line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1"
|
|
bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled"
|
|
bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: TI mode,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256"
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|
newline
|
|
bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared"
|
|
newline
|
|
bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled"
|
|
bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master."
|
|
hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame"
|
|
line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2"
|
|
bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.."
|
|
bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.."
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|
newline
|
|
bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.."
|
|
bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal"
|
|
newline
|
|
bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit"
|
|
bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle"
|
|
newline
|
|
bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.."
|
|
bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first"
|
|
newline
|
|
bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master"
|
|
bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex"
|
|
bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped"
|
|
newline
|
|
bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.."
|
|
bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.."
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness"
|
|
line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register"
|
|
bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled"
|
|
bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled"
|
|
bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled"
|
|
bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled"
|
|
bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled"
|
|
bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_SR,SPI/I2S status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session"
|
|
bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.."
|
|
newline
|
|
bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*"
|
|
bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete"
|
|
newline
|
|
bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.."
|
|
bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected."
|
|
newline
|
|
bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected"
|
|
bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected"
|
|
bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished"
|
|
bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete"
|
|
newline
|
|
bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.."
|
|
bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register"
|
|
bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1"
|
|
bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1"
|
|
bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1"
|
|
bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1"
|
|
bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register"
|
|
hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RXDR,SPI/I2S receive data register"
|
|
hexmask.long 0x0 0.--31. 1. "RXDR,receive data register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter"
|
|
line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register"
|
|
hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition"
|
|
line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register"
|
|
bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I<sup>2</sup>S linear prescaler"
|
|
bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.."
|
|
newline
|
|
bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.."
|
|
bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.."
|
|
newline
|
|
bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.."
|
|
bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 80.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.."
|
|
bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I<sup>2</sup>S standard selection" "0: I<sup>2</sup>S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?"
|
|
newline
|
|
bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected"
|
|
tree.end
|
|
tree "SPI4"
|
|
base ad:0x42003400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CR1,SPI/I2S control register 1"
|
|
bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked"
|
|
bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied"
|
|
newline
|
|
bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied"
|
|
bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.."
|
|
newline
|
|
bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1"
|
|
bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter"
|
|
newline
|
|
bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1"
|
|
bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.."
|
|
newline
|
|
bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.."
|
|
bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled"
|
|
line.long 0x4 "SPI_CR2,SPI/I2S control register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer"
|
|
line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1"
|
|
bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled"
|
|
bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: TI mode,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256"
|
|
newline
|
|
bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared"
|
|
newline
|
|
bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled"
|
|
bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master."
|
|
hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame"
|
|
line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2"
|
|
bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.."
|
|
bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.."
|
|
newline
|
|
bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.."
|
|
bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal"
|
|
newline
|
|
bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit"
|
|
bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle"
|
|
newline
|
|
bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.."
|
|
bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first"
|
|
newline
|
|
bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master"
|
|
bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex"
|
|
bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped"
|
|
newline
|
|
bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.."
|
|
bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.."
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness"
|
|
line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register"
|
|
bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled"
|
|
bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled"
|
|
bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled"
|
|
bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled"
|
|
bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled"
|
|
bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_SR,SPI/I2S status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session"
|
|
bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.."
|
|
newline
|
|
bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*"
|
|
bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete"
|
|
newline
|
|
bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.."
|
|
bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected."
|
|
newline
|
|
bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected"
|
|
bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected"
|
|
bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished"
|
|
bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete"
|
|
newline
|
|
bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.."
|
|
bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register"
|
|
bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1"
|
|
bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1"
|
|
bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1"
|
|
bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1"
|
|
bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register"
|
|
hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RXDR,SPI/I2S receive data register"
|
|
hexmask.long 0x0 0.--31. 1. "RXDR,receive data register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter"
|
|
line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register"
|
|
hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition"
|
|
line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register"
|
|
bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I<sup>2</sup>S linear prescaler"
|
|
bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.."
|
|
newline
|
|
bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.."
|
|
bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.."
|
|
newline
|
|
bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.."
|
|
bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 80.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.."
|
|
bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I<sup>2</sup>S standard selection" "0: I<sup>2</sup>S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?"
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|
newline
|
|
bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected"
|
|
tree.end
|
|
tree "SPI5"
|
|
base ad:0x42005000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CR1,SPI/I2S control register 1"
|
|
bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked"
|
|
bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied"
|
|
newline
|
|
bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied"
|
|
bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.."
|
|
newline
|
|
bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1"
|
|
bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter"
|
|
newline
|
|
bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1"
|
|
bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.."
|
|
newline
|
|
bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.."
|
|
bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled"
|
|
line.long 0x4 "SPI_CR2,SPI/I2S control register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer"
|
|
line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1"
|
|
bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled"
|
|
bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: TI mode,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256"
|
|
newline
|
|
bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared"
|
|
newline
|
|
bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled"
|
|
bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master."
|
|
hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame"
|
|
line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2"
|
|
bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.."
|
|
bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.."
|
|
newline
|
|
bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.."
|
|
bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal"
|
|
newline
|
|
bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit"
|
|
bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle"
|
|
newline
|
|
bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.."
|
|
bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first"
|
|
newline
|
|
bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master"
|
|
bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex"
|
|
bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped"
|
|
newline
|
|
bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.."
|
|
bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.."
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness"
|
|
line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register"
|
|
bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled"
|
|
bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled"
|
|
bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled"
|
|
bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled"
|
|
bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled"
|
|
bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SPI_SR,SPI/I2S status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session"
|
|
bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.."
|
|
newline
|
|
bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*"
|
|
bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete"
|
|
newline
|
|
bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.."
|
|
bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected."
|
|
newline
|
|
bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected"
|
|
bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected"
|
|
bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished"
|
|
bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete"
|
|
newline
|
|
bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.."
|
|
bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register"
|
|
bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1"
|
|
bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1"
|
|
bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1"
|
|
bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1"
|
|
bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register"
|
|
hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SPI_RXDR,SPI/I2S receive data register"
|
|
hexmask.long 0x0 0.--31. 1. "RXDR,receive data register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register"
|
|
hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter"
|
|
line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register"
|
|
hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register"
|
|
hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition"
|
|
line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register"
|
|
bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I<sup>2</sup>S linear prescaler"
|
|
bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.."
|
|
newline
|
|
bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.."
|
|
bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.."
|
|
newline
|
|
bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.."
|
|
bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 80.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.."
|
|
bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "I2SSTD,I<sup>2</sup>S standard selection" "0: I<sup>2</sup>S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?"
|
|
newline
|
|
bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected"
|
|
tree.end
|
|
tree "SPI6"
|
|
base ad:0x58001400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SPI_CR1,SPI/I2S control register 1"
|
|
bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated I/Os" "0: AF configuration is not locked,1: AF configuration is locked"
|
|
bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: all zero pattern is applied,1: all ones pattern is applied"
|
|
newline
|
|
bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: All zero pattern is applied,1: All ones pattern is applied"
|
|
bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: Full size (33-bit or 17-bit) CRC polynomial is..,1: Full size (33-bit or 17-bit) CRC polynomial is.."
|
|
newline
|
|
bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1"
|
|
bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is receiver,1: SPI is transmitter"
|
|
newline
|
|
bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1"
|
|
bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is ongoing or temporary.."
|
|
newline
|
|
bitfld.long 0x0 8. "MASRX,master automatic suspension in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.."
|
|
bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: Serial peripheral disabled.,1: Serial peripheral enabled"
|
|
line.long 0x4 "SPI_CR2,SPI/I2S control register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TSIZE,number of data at current transfer"
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|
line.long 0x8 "SPI_CFG1,SPI/I2S configuration register 1"
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|
bitfld.long 0x8 31. "BPASS,bypass of the prescaler at master baud rate clock generator" "0: bypass is disabled,1: bypass is enabled"
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|
bitfld.long 0x8 28.--30. "MBR,master baud rate prescaler setting" "0: SPI master clock/2,1: TI mode,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256"
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newline
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bitfld.long 0x8 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
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|
hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared"
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newline
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bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled"
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|
bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled"
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newline
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bitfld.long 0x8 9. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: Slave repeats lastly received data from master."
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|
hexmask.long.byte 0x8 5.--8. 1. "FTHLV,FIFO threshold level"
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newline
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hexmask.long.byte 0x8 0.--4. 1. "DSIZE,number of bits in at single SPI data frame"
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|
line.long 0xC "SPI_CFG2,SPI/I2S configuration register 2"
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bitfld.long 0xC 31. "AFCNTR,alternate function GPIOs control" "0: The peripheral takes no control of GPIOs while..,1: The peripheral keeps always control of all.."
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bitfld.long 0xC 30. "SSOM,SS output management in Master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.."
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newline
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bitfld.long 0xC 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.."
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bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal"
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newline
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bitfld.long 0xC 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit"
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bitfld.long 0xC 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle"
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newline
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bitfld.long 0xC 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.."
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bitfld.long 0xC 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first"
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newline
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bitfld.long 0xC 22. "MASTER,SPI Master" "0: SPI Slave,1: SPI Master"
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bitfld.long 0xC 19.--21. "SP,serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex"
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bitfld.long 0xC 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped"
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newline
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bitfld.long 0xC 14. "RDIOP,RDY signal input/output polarity" "0: high level of the signal means the slave is..,1: low level of the signal means the slave is ready.."
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bitfld.long 0xC 13. "RDIOM,RDY signal input/output management" "0: RDY signal is defined internally fixed as..,1: RDY signal is overtaken from alternate function.."
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|
newline
|
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hexmask.long.byte 0xC 4.--7. 1. "MIDI,master Inter-Data Idleness"
|
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hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness"
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line.long 0x10 "SPI_IER,SPI/I2S interrupt enable register"
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bitfld.long 0x10 9. "MODFIE,mode Fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled"
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bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled"
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newline
|
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bitfld.long 0x10 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled"
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|
bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled"
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newline
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bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled"
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|
bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled"
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|
newline
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bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled"
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bitfld.long 0x10 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled"
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newline
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bitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled"
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|
bitfld.long 0x10 0. "RXPIE,RXP interrupt enable" "0: RXP interrupt disabled,1: RXP interrupt enabled"
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rgroup.long 0x14++0x3
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|
line.long 0x0 "SPI_SR,SPI/I2S status register"
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hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session"
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bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.."
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newline
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bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing level" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*"
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bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: current data transaction is still ongoing data..,1: last TxFIFO frame transmission complete"
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|
newline
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bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (Master mode active or other..,1: Master mode is suspended (current frame.."
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|
bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected."
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newline
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|
bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI frame error detected"
|
|
bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected"
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|
newline
|
|
bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected"
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|
bitfld.long 0x0 5. "UDR,underrun" "0: no underrun,1: underrun detected"
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|
newline
|
|
bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is ongoing or not started,1: TxFIFO upload is finished"
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|
bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is ongoing or not started,1: transfer complete"
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|
newline
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bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: both TxFIFO has space for write and RxFIFO.."
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|
bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: not enough free space at TxFIFO to host next..,1: enough free space at TxFIFO to host at least one.."
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newline
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bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or an incomplete data packet is..,1: RxFIFO contains at least one data packet"
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|
wgroup.long 0x18++0x3
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line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register"
|
|
bitfld.long 0x0 11. "SUSPC,Suspend flag clear" "0,1"
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|
bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1"
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|
bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1"
|
|
bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1"
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newline
|
|
bitfld.long 0x0 4. "TXTFC,transmission transfer filled flag clear" "0,1"
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|
bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1"
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wgroup.long 0x20++0x3
|
|
line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register"
|
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hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register"
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rgroup.long 0x30++0x3
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|
line.long 0x0 "SPI_RXDR,SPI/I2S receive data register"
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|
hexmask.long 0x0 0.--31. 1. "RXDR,receive data register"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SPI_CRCPOLY,SPI/I2S polynomial register"
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hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x44++0x7
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line.long 0x0 "SPI_TXCRC,SPI/I2S transmitter CRC register"
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hexmask.long 0x0 0.--31. 1. "TXCRC,CRC register for transmitter"
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line.long 0x4 "SPI_RXCRC,SPI/I2S receiver CRC register"
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hexmask.long 0x4 0.--31. 1. "RXCRC,CRC register for receiver"
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group.long 0x4C++0x7
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line.long 0x0 "SPI_UDRDR,SPI/I2S underrun data register"
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hexmask.long 0x0 0.--31. 1. "UDRDR,data at slave underrun condition"
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line.long 0x4 "SPI_I2SCFGR,SPI/I2S configuration register"
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bitfld.long 0x4 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
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bitfld.long 0x4 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
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newline
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hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I<sup>2</sup>S linear prescaler"
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bitfld.long 0x4 14. "DATFMT,data format" "0: The data inside the SPI_RXDR or SPI_TXDR are..,1: The data inside the SPI_RXDR or SPI_TXDR are.."
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newline
|
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bitfld.long 0x4 13. "WSINV,word select inversion" "0: In I2S Philips standard the left channel..,1: In I2S Philips standard the left channel.."
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bitfld.long 0x4 12. "FIXCH,fixed channel length in slave" "0: the channel length in Slave mode is different..,1: the channel length in Slave mode is supposed to.."
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newline
|
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bitfld.long 0x4 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.."
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bitfld.long 0x4 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
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newline
|
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bitfld.long 0x4 8.--9. "DATLEN,data length to be transferred. Data width of 24 and 32 bits are not always supported (DATLEN = 01 or 10) refer to Section 80.3: SPI implementation to check the supported data size." "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: SPI implementation to check the supported data.."
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bitfld.long 0x4 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization"
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newline
|
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bitfld.long 0x4 4.--5. "I2SSTD,I<sup>2</sup>S standard selection" "0: I<sup>2</sup>S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
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bitfld.long 0x4 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - Full Duplex,5: master - Full Duplex,?,?"
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newline
|
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bitfld.long 0x4 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected"
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tree.end
|
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tree.end
|
|
tree "TAMP (Tamper and Backup Registers)"
|
|
base ad:0x58004400
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group.long 0x0++0x13
|
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line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
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bitfld.long 0x0 30. "ITAMP15E,Internal tamper 15 enable" "0: Internal tamper 15 disabled.,1: Internal tamper 15 enabled."
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bitfld.long 0x0 26. "ITAMP11E,Internal tamper 11 enable" "0: Internal tamper 11 disabled.,1: Internal tamper 11 enabled."
|
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newline
|
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bitfld.long 0x0 24. "ITAMP9E,Internal tamper 9 enable" "0: Internal tamper 9 disabled.,1: Internal tamper 9 enabled."
|
|
bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled."
|
|
newline
|
|
bitfld.long 0x0 22. "ITAMP7E,Internal tamper 7 enable" "0: Internal tamper 7 disabled.,1: Internal tamper 7 enabled"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled."
|
|
newline
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled."
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled."
|
|
newline
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled."
|
|
bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled."
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled."
|
|
bitfld.long 0x0 7. "TAMP8E,Tamper detection on TAMP_IN8 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN8 is disabled.,1: Tamper detection on TAMP_IN8 is enabled."
|
|
newline
|
|
bitfld.long 0x0 6. "TAMP7E,Tamper detection on TAMP_IN7 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN7 is disabled.,1: Tamper detection on TAMP_IN7 is enabled."
|
|
bitfld.long 0x0 5. "TAMP6E,Tamper detection on TAMP_IN6 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN6 is disabled.,1: Tamper detection on TAMP_IN6 is enabled."
|
|
newline
|
|
bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled."
|
|
bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled."
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 31. "TAMP8TRG,Active level for tamper 8 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 8 input..,1: If TAMPFLT different from 00 Tamper 8 input.."
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|
bitfld.long 0x4 30. "TAMP7TRG,Active level for tamper 7 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 7 input..,1: If TAMPFLT different from 00 Tamper 7 input.."
|
|
newline
|
|
bitfld.long 0x4 29. "TAMP6TRG,Active level for tamper 6 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 6 input..,1: If TAMPFLT different from 00 Tamper 6 input.."
|
|
bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 5 input..,1: If TAMPFLT different from 00 Tamper 5 input.."
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|
newline
|
|
bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 4 input..,1: If TAMPFLT different from 00 Tamper 4 input.."
|
|
bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT different from 00 Tamper 3 input..,1: If TAMPFLT different from 00 Tamper 3 input.."
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|
newline
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT different from 00 Tamper 2 input..,1: If TAMPFLT different from 00 Tamper 2 input.."
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|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT different from 00 Tamper 1 input..,1: If TAMPFLT different from 00 Tamper 1 input.."
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|
newline
|
|
bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets<sup>(1)</sup> erase" "0,1"
|
|
bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets<sup>(1)</sup> access blocked" "0: backup registers and device..,1: backup registers and device.."
|
|
newline
|
|
bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.."
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
newline
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
bitfld.long 0x4 7. "TAMP8NOER,Tamper 8 no erase" "0: Tamper 8 event erases the backup registers and..,1: Tamper 8 event does not erase the backup.."
|
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newline
|
|
bitfld.long 0x4 6. "TAMP7NOER,Tamper 7 no erase" "0: Tamper 7 event erases the backup registers and..,1: Tamper 7 event does not erase the backup.."
|
|
bitfld.long 0x4 5. "TAMP6NOER,Tamper 6 no erase" "0: Tamper 6 event erases the backup registers and..,1: Tamper 6 event does not erase the backup.."
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|
newline
|
|
bitfld.long 0x4 4. "TAMP5NOER,Tamper 5 no erase" "0: Tamper 5 event erases the backup registers and..,1: Tamper 5 event does not erase the backup.."
|
|
bitfld.long 0x4 3. "TAMP4NOER,Tamper 4 no erase" "0: Tamper 4 event erases the backup registers and..,1: Tamper 4 event does not erase the backup.."
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newline
|
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bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers and..,1: Tamper 3 event does not erase the backup.."
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers and..,1: Tamper 2 event does not erase the backup.."
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers and..,1: Tamper 1 event does not erase the backup.."
|
|
line.long 0x8 "TAMP_CR3,TAMP control register 3"
|
|
bitfld.long 0x8 14. "ITAMP15NOER,Internal Tamper 15 no erase" "0: Internal Tamper 15 event erases the backup..,1: Internal Tamper 15 event does not erase the.."
|
|
bitfld.long 0x8 10. "ITAMP11NOER,Internal Tamper 11 no erase" "0: Internal Tamper 11 event erases the backup..,1: Internal Tamper 11 event does not erase the.."
|
|
newline
|
|
bitfld.long 0x8 8. "ITAMP9NOER,Internal Tamper 9 no erase" "0: Internal Tamper 9 event erases the backup..,1: Internal Tamper 9 event does not erase the.."
|
|
bitfld.long 0x8 7. "ITAMP8NOER,Internal Tamper 8 no erase" "0: Internal Tamper 8 event erases the backup..,1: Internal Tamper 8 event does not erase the.."
|
|
newline
|
|
bitfld.long 0x8 6. "ITAMP7NOER,Internal Tamper 7 no erase" "0: Internal Tamper 7 event erases the backup..,1: Internal Tamper 7 event does not erase the.."
|
|
bitfld.long 0x8 5. "ITAMP6NOER,Internal Tamper 6 no erase" "0: Internal Tamper 6 event erases the backup..,1: Internal Tamper 6 event does not erase the.."
|
|
newline
|
|
bitfld.long 0x8 4. "ITAMP5NOER,Internal Tamper 5 no erase" "0: Internal Tamper 5 event erases the backup..,1: Internal Tamper 5 event does not erase the.."
|
|
bitfld.long 0x8 3. "ITAMP4NOER,Internal Tamper 4 no erase" "0: Internal Tamper 4 event erases the backup..,1: Internal Tamper 4 event does not erase the.."
|
|
newline
|
|
bitfld.long 0x8 2. "ITAMP3NOER,Internal Tamper 3 no erase" "0: Internal Tamper 3 event erases the backup..,1: Internal Tamper 3 event does not erase the.."
|
|
bitfld.long 0x8 1. "ITAMP2NOER,Internal Tamper 2 no erase" "0: Internal Tamper 2 event erases the backup..,1: Internal Tamper 2 event does not erase the.."
|
|
newline
|
|
bitfld.long 0x8 0. "ITAMP1NOER,Internal Tamper 1 no erase" "0: Internal Tamper 1 event erases the backup..,1: Internal Tamper 1 event does not erase the.."
|
|
line.long 0xC "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"
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line.long 0x10 "TAMP_ATCR1,TAMP active tamper control register 1"
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bitfld.long 0x10 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.."
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bitfld.long 0x10 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.."
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newline
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bitfld.long 0x10 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 16.--18. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" "0: RTCCLK is selected,1: RTCCLK/2 is selected,2: RTCCLK/4 is selected,?,?,?,?,7: RTCCLK/128 is selected"
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newline
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bitfld.long 0x10 14.--15. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4"
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bitfld.long 0x10 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4"
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newline
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bitfld.long 0x10 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4"
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bitfld.long 0x10 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4"
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newline
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bitfld.long 0x10 7. "TAMP8AM,Tamper 8 active mode" "0: Tamper 8 detection mode is passive.,1: Tamper 8 detection mode is active."
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bitfld.long 0x10 6. "TAMP7AM,Tamper 7 active mode" "0: Tamper 7 detection mode is passive.,1: Tamper 7 detection mode is active."
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newline
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bitfld.long 0x10 5. "TAMP6AM,Tamper 6 active mode" "0: Tamper 6 detection mode is passive.,1: Tamper 6 detection mode is active."
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bitfld.long 0x10 4. "TAMP5AM,Tamper 5 active mode" "0: Tamper 5 detection mode is passive.,1: Tamper 5 detection mode is active."
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newline
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bitfld.long 0x10 3. "TAMP4AM,Tamper 4 active mode" "0: Tamper 4 detection mode is passive.,1: Tamper 4 detection mode is active."
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bitfld.long 0x10 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active."
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newline
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bitfld.long 0x10 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active."
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bitfld.long 0x10 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active."
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wgroup.long 0x14++0x3
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line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register"
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hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value"
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rgroup.long 0x18++0x3
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line.long 0x0 "TAMP_ATOR,TAMP active tamper output register"
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bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1"
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bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value"
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group.long 0x1C++0xB
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line.long 0x0 "TAMP_ATCR2,TAMP active tamper control register 2"
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bitfld.long 0x0 29.--31. "ATOSEL8,Active tamper shared output 8 selection" "0: TAMPOUTSEL8 = TAMP_OUT1,1: TAMPOUTSEL8 = TAMP_OUT2,2: TAMPOUTSEL8 = TAMP_OUT3,3: TAMPOUTSEL8 = TAMP_OUT4,4: TAMPOUTSEL8 = TAMP_OUT5,5: TAMPOUTSEL8 = TAMP_OUT6,6: TAMPOUTSEL8 = TAMP_OUT7,7: TAMPOUTSEL8 = TAMP_OUT8"
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bitfld.long 0x0 26.--28. "ATOSEL7,Active tamper shared output 7 selection" "0: TAMPOUTSEL7 = TAMP_OUT1,1: TAMPOUTSEL7 = TAMP_OUT2,2: TAMPOUTSEL7 = TAMP_OUT3,3: TAMPOUTSEL7 = TAMP_OUT4,4: TAMPOUTSEL7 = TAMP_OUT5,5: TAMPOUTSEL7 = TAMP_OUT6,6: TAMPOUTSEL7 = TAMP_OUT7,7: TAMPOUTSEL7 = TAMP_OUT8"
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newline
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bitfld.long 0x0 23.--25. "ATOSEL6,Active tamper shared output 6 selection" "0: TAMPOUTSEL6 = TAMP_OUT1,1: TAMPOUTSEL6 = TAMP_OUT2,2: TAMPOUTSEL6 = TAMP_OUT3,3: TAMPOUTSEL6 = TAMP_OUT4,4: TAMPOUTSEL6 = TAMP_OUT5,5: TAMPOUTSEL6 = TAMP_OUT6,6: TAMPOUTSEL6 = TAMP_OUT7,7: TAMPOUTSEL6 = TAMP_OUT8"
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bitfld.long 0x0 20.--22. "ATOSEL5,Active tamper shared output 5 selection" "0: TAMPOUTSEL5 = TAMP_OUT1,1: TAMPOUTSEL5 = TAMP_OUT2,2: TAMPOUTSEL5 = TAMP_OUT3,3: TAMPOUTSEL5 = TAMP_OUT4,4: TAMPOUTSEL5 = TAMP_OUT5,5: TAMPOUTSEL5 = TAMP_OUT6,6: TAMPOUTSEL5 = TAMP_OUT7,7: TAMPOUTSEL5 = TAMP_OUT8"
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newline
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bitfld.long 0x0 17.--19. "ATOSEL4,Active tamper shared output 4 selection" "0: TAMPOUTSEL4 = TAMP_OUT1,1: TAMPOUTSEL4 = TAMP_OUT2,2: TAMPOUTSEL4 = TAMP_OUT3,3: TAMPOUTSEL4 = TAMP_OUT4,4: TAMPOUTSEL4 = TAMP_OUT5,5: TAMPOUTSEL4 = TAMP_OUT6,6: TAMPOUTSEL4 = TAMP_OUT7,7: TAMPOUTSEL4 = TAMP_OUT8"
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bitfld.long 0x0 14.--16. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,3: TAMPOUTSEL3 = TAMP_OUT4,4: TAMPOUTSEL3 = TAMP_OUT5,5: TAMPOUTSEL3 = TAMP_OUT6,6: TAMPOUTSEL3 = TAMP_OUT7,7: TAMPOUTSEL3 = TAMP_OUT8"
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newline
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bitfld.long 0x0 11.--13. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,3: TAMPOUTSEL2 = TAMP_OUT4,4: TAMPOUTSEL2 = TAMP_OUT5,5: TAMPOUTSEL2 = TAMP_OUT6,6: TAMPOUTSEL2 = TAMP_OUT7,7: TAMPOUTSEL2 = TAMP_OUT8"
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bitfld.long 0x0 8.--10. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,3: TAMPOUTSEL1 = TAMP_OUT4,4: TAMPOUTSEL1 = TAMP_OUT5,5: TAMPOUTSEL1 = TAMP_OUT6,6: TAMPOUTSEL1 = TAMP_OUT7,7: TAMPOUTSEL1 = TAMP_OUT8"
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line.long 0x4 "TAMP_CFGR,TAMP configuration register"
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bitfld.long 0x4 30. "BHKLOCK,Boot hardware key lock" "0: The Backup registers from TAMP_BKP0R to..,1: The backup registers from TAMP_BKP0R to.."
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hexmask.long.byte 0x4 16.--23. 1. "BKPW,Backup registers write protection offset"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "BKPRW,Backup registers read/write protection offset"
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line.long 0x8 "TAMP_PRIVCFGR,TAMP privilege configuration register"
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bitfld.long 0x8 31. "TAMPPRIV,Tamper privilege protection (excluding backup registers)" "0: Tamper configuration and interrupt can be..,1: Tamper configuration and interrupt can be.."
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bitfld.long 0x8 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0: Backup registers zone 2 can be written with..,1: Backup registers zone 2 can be written only with.."
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newline
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bitfld.long 0x8 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0: Backup registers zone 1 can be read and written..,1: Backup registers zone 1 can be read and written.."
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bitfld.long 0x8 15. "CNT1PRIV,Monotonic counter 1 privilege protection" "0: Monotonic counter 1 (TAMP_COUNT1R) can be read..,1: Monotonic counter 1 (TAMP_COUNT1R) can be read.."
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group.long 0x2C++0x7
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line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
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bitfld.long 0x0 30. "ITAMP15IE,Internal tamper 15 interrupt enable" "0: Internal tamper 15 interrupt disabled.,1: Internal tamper 15 interrupt enabled."
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bitfld.long 0x0 26. "ITAMP11IE,Internal tamper 11 interrupt enable" "0: Internal tamper 11 interrupt disabled.,1: Internal tamper 11 interrupt enabled."
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newline
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bitfld.long 0x0 24. "ITAMP9IE,Internal tamper 9 interrupt enable" "0: Internal tamper 9 interrupt disabled.,1: Internal tamper 9 interrupt enabled."
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bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled."
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newline
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bitfld.long 0x0 22. "ITAMP7IE,Internal tamper 7 interrupt enable" "0: Internal tamper 7 interrupt disabled.,1: Internal tamper 7 interrupt enabled."
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bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
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newline
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bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
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bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
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newline
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bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
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bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled."
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newline
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bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled"
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bitfld.long 0x0 7. "TAMP8IE,Tamper 8 interrupt enable" "0: Tamper 8 interrupt disabled.,1: Tamper 8 interrupt enabled."
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newline
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bitfld.long 0x0 6. "TAMP7IE,Tamper 7interrupt enable" "0: Tamper 7 interrupt disabled.,1: Tamper 7interrupt enabled."
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bitfld.long 0x0 5. "TAMP6IE,Tamper 6 interrupt enable" "0: Tamper 6 interrupt disabled.,1: Tamper 6 interrupt enabled."
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newline
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bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled."
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bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled."
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newline
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bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.."
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bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
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newline
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bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
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line.long 0x4 "TAMP_SR,TAMP status register"
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bitfld.long 0x4 30. "ITAMP15F,Internal tamper 15 flag" "0,1"
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rbitfld.long 0x4 26. "ITAMP11F,Internal tamper 11 flag" "0,1"
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newline
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rbitfld.long 0x4 24. "ITAMP9F,Internal tamper 9 flag" "0,1"
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rbitfld.long 0x4 23. "ITAMP8F,Internal tamper 8 flag" "0,1"
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newline
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rbitfld.long 0x4 22. "ITAMP7F,Internal tamper 7 flag" "0,1"
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rbitfld.long 0x4 21. "ITAMP6F,Internal tamper 6 flag" "0,1"
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newline
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rbitfld.long 0x4 20. "ITAMP5F,Internal tamper 5 flag" "0,1"
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rbitfld.long 0x4 19. "ITAMP4F,Internal tamper 4 flag" "0,1"
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newline
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rbitfld.long 0x4 18. "ITAMP3F,Internal tamper 3 flag" "0,1"
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rbitfld.long 0x4 17. "ITAMP2F,Internal tamper 2 flag" "0,1"
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newline
|
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rbitfld.long 0x4 16. "ITAMP1F,Internal tamper 1 flag" "0,1"
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rbitfld.long 0x4 7. "TAMP8F,TAMP8 detection flag" "0,1"
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newline
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rbitfld.long 0x4 6. "TAMP7F,TAMP7 detection flag" "0,1"
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rbitfld.long 0x4 5. "TAMP6F,TAMP6 detection flag" "0,1"
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newline
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rbitfld.long 0x4 4. "TAMP5F,TAMP5 detection flag" "0,1"
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rbitfld.long 0x4 3. "TAMP4F,TAMP4 detection flag" "0,1"
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newline
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rbitfld.long 0x4 2. "TAMP3F,TAMP3 detection flag" "0,1"
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rbitfld.long 0x4 1. "TAMP2F,TAMP2 detection flag" "0,1"
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newline
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rbitfld.long 0x4 0. "TAMP1F,TAMP1 detection flag" "0,1"
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rgroup.long 0x34++0x3
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line.long 0x0 "TAMP_MISR,TAMP masked interrupt status register"
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bitfld.long 0x0 30. "ITAMP15MF,internal tamper 15 interrupt masked flag" "0,1"
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bitfld.long 0x0 26. "ITAMP11MF,internal tamper 11 interrupt masked flag" "0,1"
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newline
|
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bitfld.long 0x0 24. "ITAMP9MF,internal tamper 9 interrupt masked flag" "0,1"
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|
bitfld.long 0x0 23. "ITAMP8MF,Internal tamper 8 interrupt masked flag" "0,1"
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newline
|
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bitfld.long 0x0 22. "ITAMP7MF,Internal tamper 7 tamper interrupt masked flag" "0,1"
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bitfld.long 0x0 21. "ITAMP6MF,Internal tamper 6 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 20. "ITAMP5MF,Internal tamper 5 interrupt masked flag" "0,1"
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bitfld.long 0x0 19. "ITAMP4MF,Internal tamper 4 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 18. "ITAMP3MF,Internal tamper 3 interrupt masked flag" "0,1"
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bitfld.long 0x0 17. "ITAMP2MF,Internal tamper 2 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 16. "ITAMP1MF,Internal tamper 1 interrupt masked flag" "0,1"
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bitfld.long 0x0 7. "TAMP8MF,TAMP8 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 6. "TAMP7MF,TAMP7 interrupt masked flag" "0,1"
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bitfld.long 0x0 5. "TAMP6MF,TAMP6 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 4. "TAMP5MF,TAMP5 interrupt masked flag" "0,1"
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bitfld.long 0x0 3. "TAMP4MF,TAMP4 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1"
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bitfld.long 0x0 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
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newline
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bitfld.long 0x0 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
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wgroup.long 0x3C++0x3
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line.long 0x0 "TAMP_SCR,TAMP status clear register"
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bitfld.long 0x0 30. "CITAMP15F,Clear ITAMP15 detection flag" "0,1"
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|
bitfld.long 0x0 26. "CITAMP11F,Clear ITAMP11 detection flag" "0,1"
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|
newline
|
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bitfld.long 0x0 24. "CITAMP9F,Clear ITAMP9 detection flag" "0,1"
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bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1"
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newline
|
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bitfld.long 0x0 22. "CITAMP7F,Clear ITAMP7 detection flag" "0,1"
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bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
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newline
|
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bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
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bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
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newline
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bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
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bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1"
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newline
|
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bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1"
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bitfld.long 0x0 7. "CTAMP8F,Clear TAMP8 detection flag" "0,1"
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|
newline
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bitfld.long 0x0 6. "CTAMP7F,Clear TAMP7 detection flag" "0,1"
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bitfld.long 0x0 5. "CTAMP6F,Clear TAMP6 detection flag" "0,1"
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newline
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bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1"
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bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1"
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newline
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bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1"
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bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
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newline
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bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
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|
rgroup.long 0x40++0x3
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|
line.long 0x0 "TAMP_COUNT1R,TAMP monotonic counter 1 register"
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|
hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value."
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|
group.long 0x100++0x7F
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line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
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hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
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hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
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hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
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|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
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|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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|
line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register"
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|
hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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|
line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register"
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|
hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register"
|
|
hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register"
|
|
hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register"
|
|
hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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|
line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register"
|
|
hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register"
|
|
hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register"
|
|
hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register"
|
|
hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register"
|
|
hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register"
|
|
hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register"
|
|
hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register"
|
|
hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register"
|
|
hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register"
|
|
hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register"
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hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register"
|
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hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers."
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line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register"
|
|
hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register"
|
|
hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register"
|
|
hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register"
|
|
hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register"
|
|
hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register"
|
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hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register"
|
|
hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register"
|
|
hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register"
|
|
hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register"
|
|
hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
tree.end
|
|
tree "TIM (Timers)"
|
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base ad:0x0
|
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tree "TIM1"
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base ad:0x42000000
|
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group.word 0x0++0x1
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line.word 0x0 "TIM1_CR1,TIM1 control register 1"
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bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
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|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub>=t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub>=2*t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub>=4*t<sub>tim_ker_ck</sub>,3: Reserved do not program this value"
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|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
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newline
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
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|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
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bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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|
group.long 0x4++0xF
|
|
line.long 0x0 "TIM1_CR2,TIM1 control register 2"
|
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bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2"
|
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newline
|
|
bitfld.long 0x0 18. "OIS6,Output idle state 6 (tim_oc6 output)" "0,1"
|
|
bitfld.long 0x0 16. "OIS5,Output idle state 5 (tim_oc5 output)" "0,1"
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|
newline
|
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bitfld.long 0x0 15. "OIS4N,Output idle state 4 (tim_oc4n output)" "0,1"
|
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bitfld.long 0x0 14. "OIS4,Output idle state 4 (tim_oc4 output)" "0,1"
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newline
|
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bitfld.long 0x0 13. "OIS3N,Output idle state 3 (tim_oc3n output)" "0,1"
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|
bitfld.long 0x0 12. "OIS3,Output idle state 3 (tim_oc3n output)" "0,1"
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newline
|
|
bitfld.long 0x0 11. "OIS2N,Output idle state 2 (tim_oc2n output)" "0,1"
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|
bitfld.long 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "OIS1N,Output idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0"
|
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bitfld.long 0x0 8. "OIS1,Output idle state 1 (tim_oc1 output)" "0: tim_oc1=0 (after a dead-time) when MOE=0,1: tim_oc1=1 (after a dead-time) when MOE=0"
|
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newline
|
|
bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: tim_ti1_in[15:0] tim_ti2_in[15:0] and.."
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bitfld.long 0x0 4.--6. "MMS,MMS[2:0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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newline
|
|
bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register"
|
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bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timers Update..,1: The transfer is triggered by the Index event"
|
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bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etr_in frequency divided by 2,2: tim_etr_in frequency divided by 4,3: tim_etr_in frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
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newline
|
|
bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x4 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),7: External Trigger input (tim_etrf)"
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newline
|
|
bitfld.long 0x4 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Quadrature encoder mode 1 x2 mode- Counter..,2: Quadrature encoder mode 2 x2 mode - Counter..,3: Quadrature encoder mode 3 x4 mode - Counter..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0x8 "TIM1_DIER,TIM1 DMA/interrupt enable register"
|
|
bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled"
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|
bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled"
|
|
newline
|
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bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction Change interrupt disabled,1: Direction Change interrupt enabled"
|
|
bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index Change interrupt enabled"
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|
newline
|
|
bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0x8 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0x8 12. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.long 0x8 11. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.long 0x8 10. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0x8 9. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0x8 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0x8 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "CC4IE,Capture/compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.long 0x8 3. "CC3IE,Capture/compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x8 2. "CC2IE,Capture/compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0x8 1. "CC1IE,Capture/compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0xC "TIM1_SR,TIM1 status register"
|
|
bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected"
|
|
bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected"
|
|
newline
|
|
bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change"
|
|
bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred"
|
|
newline
|
|
bitfld.long 0xC 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0xC 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "SBIF,System break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0xC 12. "CC4OF,Capture/compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3OF,Capture/compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CC1OF,Capture/compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0xC 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0xC 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0xC 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0xC 4. "CC4IF,Capture/compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IF,Capture/compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0xC 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM1_EGR,TIM1 event generation register"
|
|
bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 5. "COMG,Capture/compare control update generation" "0: No action,1: CCxE CCxNE and OCxM bits update (providing CCPC.."
|
|
newline
|
|
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM1_CCMR1_INPUT,TIM1 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM1_CCMR1_OUTPUT,TIM1 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
line.long 0x4 "TIM1_CCMR2_INPUT,TIM1 capture/compare mode register 2"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "TIM1_CCMR2_OUTPUT,TIM1 capture/compare mode register 2"
|
|
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0: Frozen - The comparison between the output..,1: Set channel 3 to active level on match.,2: Set channel 3 to inactive level on match.,3: Toggle - tim_oc3ref toggles when..,4: Force inactive level - tim_oc3ref is forced low.,5: Force active level - tim_oc3ref is forced high.,6: PWM mode 1 - In upcounting channel 3 is active..,7: PWM mode 2 - In upcounting channel 3 is inactive.."
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register"
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bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity" "0,1"
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bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable" "0,1"
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bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity" "0,1"
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bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable" "0,1"
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bitfld.long 0x4 15. "CC4NP,Capture/compare 4 complementary output polarity" "0,1"
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bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable" "0,1"
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bitfld.long 0x4 13. "CC4P,Capture/compare 4 output polarity" "0,1"
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bitfld.long 0x4 12. "CC4E,Capture/compare 4 output enable" "0,1"
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bitfld.long 0x4 11. "CC3NP,Capture/compare 3 complementary output polarity" "0,1"
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bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable" "0,1"
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bitfld.long 0x4 9. "CC3P,Capture/compare 3 output polarity" "0,1"
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bitfld.long 0x4 8. "CC3E,Capture/compare 3 output enable" "0,1"
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bitfld.long 0x4 7. "CC2NP,Capture/compare 2 complementary output polarity" "0,1"
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bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable" "0,1"
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bitfld.long 0x4 5. "CC2P,Capture/compare 2 output polarity" "0,1"
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bitfld.long 0x4 4. "CC2E,Capture/compare 2 output enable" "0,1"
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bitfld.long 0x4 3. "CC1NP,Capture/compare 1 complementary output polarity" "0: tim_oc1n active high.,1: tim_oc1n active low."
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bitfld.long 0x4 2. "CC1NE,Capture/compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.."
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newline
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bitfld.long 0x4 1. "CC1P,Capture/compare 1 output polarity" "0: the configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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bitfld.long 0x4 0. "CC1E,Capture/compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x8 "TIM1_CNT,TIM1 counter"
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rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
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hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
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group.word 0x28++0x1
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line.word 0x0 "TIM1_PSC,TIM1 prescaler"
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hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
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group.long 0x2C++0x3
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line.long 0x0 "TIM1_ARR,TIM1 auto-reload register"
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hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
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group.word 0x30++0x1
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line.word 0x0 "TIM1_RCR,TIM1 repetition counter register"
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hexmask.word 0x0 0.--15. 1. "REP,Repetition counter reload value"
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group.long 0x34++0x33
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line.long 0x0 "TIM1_CCR1,TIM1 capture/compare register 1"
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hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value"
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line.long 0x4 "TIM1_CCR2,TIM1 capture/compare register 2"
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hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value"
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line.long 0x8 "TIM1_CCR3,TIM1 capture/compare register 3"
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hexmask.long.tbyte 0x8 0.--19. 1. "CCR3,Capture/compare value"
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line.long 0xC "TIM1_CCR4,TIM1 capture/compare register 4"
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hexmask.long.tbyte 0xC 0.--19. 1. "CCR4,Capture/compare value"
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line.long 0x10 "TIM1_BDTR,TIM1 break and dead-time register"
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bitfld.long 0x10 29. "BK2BID,Break2 bidirectional" "0,1"
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bitfld.long 0x10 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode"
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bitfld.long 0x10 27. "BK2DSRM,Break2 disarm" "0,1"
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bitfld.long 0x10 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed"
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bitfld.long 0x10 25. "BK2P,Break 2 polarity" "0: Break input tim_brk2 is active low,1: Break input tim_brk2 is active high"
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bitfld.long 0x10 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled"
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hexmask.long.byte 0x10 20.--23. 1. "BK2F,Break 2 filter"
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hexmask.long.byte 0x10 16.--19. 1. "BKF,Break filter"
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newline
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bitfld.long 0x10 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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bitfld.long 0x10 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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newline
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bitfld.long 0x10 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high"
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bitfld.long 0x10 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
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newline
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bitfld.long 0x10 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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bitfld.long 0x10 10. "OSSI,Off-state selection for idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
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newline
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bitfld.long 0x10 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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hexmask.long.byte 0x10 0.--7. 1. "DTG,Dead-time generator setup"
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line.long 0x14 "TIM1_CCR5,TIM1 capture/compare register 5"
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bitfld.long 0x14 31. "GC5C3,Group channel 5 and channel 3" "0: No effect of tim_oc5ref on tim_oc3refc,1: tim_oc3refc is the logical AND of tim_oc3ref and.."
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bitfld.long 0x14 30. "GC5C2,Group channel 5 and channel 2" "0: No effect of tim_oc5ref on tim_oc2refc,1: tim_oc2refc is the logical AND of tim_oc2ref and.."
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newline
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bitfld.long 0x14 29. "GC5C1,Group channel 5 and channel 1" "0: No effect of oc5ref on oc1refc,1: oc1refc is the logical AND of oc1ref and oc5ref"
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hexmask.long.tbyte 0x14 0.--19. 1. "CCR5,Capture/compare 5 value"
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line.long 0x18 "TIM1_CCR6,TIM1 capture/compare register 6"
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hexmask.long.tbyte 0x18 0.--19. 1. "CCR6,Capture/compare 6 value"
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line.long 0x1C "TIM1_CCMR3,TIM1 capture/compare mode register 3"
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bitfld.long 0x1C 24. "OC6M_1,OC6M[3]" "0,1"
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bitfld.long 0x1C 16. "OC5M_1,OC5M[3]" "0,1"
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newline
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bitfld.long 0x1C 15. "OC6CE,Output compare 6 clear enable" "0,1"
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bitfld.long 0x1C 12.--14. "OC6M,OC6M[2:0]: Output compare 6 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x1C 11. "OC6PE,Output compare 6 preload enable" "0,1"
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bitfld.long 0x1C 10. "OC6FE,Output compare 6 fast enable" "0,1"
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newline
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bitfld.long 0x1C 7. "OC5CE,Output compare 5 clear enable" "0,1"
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bitfld.long 0x1C 4.--6. "OC5M,OC5M[2:0]: Output compare 5 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x1C 3. "OC5PE,Output compare 5 preload enable" "0,1"
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bitfld.long 0x1C 2. "OC5FE,Output compare 5 fast enable" "0,1"
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line.long 0x20 "TIM1_DTR2,TIM1 timer deadtime register 2"
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bitfld.long 0x20 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled"
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bitfld.long 0x20 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].."
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newline
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hexmask.long.byte 0x20 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
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line.long 0x24 "TIM1_ECR,TIM1 timer encoder control register"
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bitfld.long 0x24 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x24 16.--23. 1. "PW,Pulse width"
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newline
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bitfld.long 0x24 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11"
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bitfld.long 0x24 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter"
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newline
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bitfld.long 0x24 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled when tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,3: FIELD Reserved"
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bitfld.long 0x24 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,3: FIELD Reserved"
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newline
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bitfld.long 0x24 0. "IE,Index enable" "0: Index disabled,1: Index enabled"
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line.long 0x28 "TIM1_TISEL,TIM1 timer input selection register"
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hexmask.long.byte 0x28 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input"
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hexmask.long.byte 0x28 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input"
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newline
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hexmask.long.byte 0x28 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input"
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hexmask.long.byte 0x28 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input"
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line.long 0x2C "TIM1_AF1,TIM1 alternate function option register 1"
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hexmask.long.byte 0x2C 14.--17. 1. "ETRSEL,etr_in source selection"
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bitfld.long 0x2C 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input polarity is not inverted..,1: tim_brk_cmp4 input polarity is inverted (active.."
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newline
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bitfld.long 0x2C 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input polarity is not inverted..,1: tim_brk_cmp3 input polarity is inverted (active.."
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bitfld.long 0x2C 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input polarity is not inverted..,1: tim_brk_cmp2 input polarity is inverted (active.."
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newline
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bitfld.long 0x2C 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input polarity is not inverted..,1: tim_brk_cmp1 input polarity is inverted (active.."
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bitfld.long 0x2C 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input polarity is not inverted (active..,1: TIMx_BKIN input polarity is inverted (active.."
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newline
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bitfld.long 0x2C 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled"
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bitfld.long 0x2C 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled"
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newline
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bitfld.long 0x2C 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled"
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bitfld.long 0x2C 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled"
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newline
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bitfld.long 0x2C 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled"
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bitfld.long 0x2C 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled"
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newline
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bitfld.long 0x2C 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled"
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bitfld.long 0x2C 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled"
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newline
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bitfld.long 0x2C 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled"
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line.long 0x30 "TIM1_AF2,TIM1 alternate function register 2"
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bitfld.long 0x30 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM1 pins and internal signals for product..,?,?,?,?,7: tim_ocref_clr7"
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bitfld.long 0x30 13. "BK2CMP4P,tim_brk2_cmp4 input polarity" "0: tim_brk2_cmp4 input polarity is not inverted..,1: tim_brk2_cmp4 input polarity is inverted (active.."
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newline
|
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bitfld.long 0x30 12. "BK2CMP3P,tim_brk2_cmp3 input polarity" "0: tim_brk2_cmp3 input polarity is not inverted..,1: tim_brk2_cmp3 input polarity is inverted (active.."
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bitfld.long 0x30 11. "BK2CMP2P,tim_brk2_cmp2 input polarity" "0: tim_brk2_cmp2 input polarity is not inverted..,1: tim_brk2_cmp2 input polarity is inverted (active.."
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newline
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bitfld.long 0x30 10. "BK2CMP1P,tim_brk2_cmp1 input polarity" "0: tim_brk2_cmp1 input polarity is not inverted..,1: tim_brk2_cmp1 input polarity is inverted (active.."
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bitfld.long 0x30 9. "BK2INP,TIMx_BKIN2 input polarity" "0: TIMx_BKIN2 input polarity is not inverted..,1: TIMx_BKIN2 input polarity is inverted (active.."
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newline
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bitfld.long 0x30 8. "BK2CMP8E,tim_brk2_cmp8 enable" "0: tim_brk2_cmp8 input disabled,1: tim_brk2_cmp8 input enabled"
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bitfld.long 0x30 7. "BK2CMP7E,tim_brk2_cmp7 enable" "0: tim_brk2_cmp7 input disabled,1: tim_brk2_cmp7 input enabled"
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newline
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bitfld.long 0x30 6. "BK2CMP6E,tim_brk2_cmp6 enable" "0: tim_brk2_cmp6 input disabled,1: tim_brk2_cmp6 input enabled"
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bitfld.long 0x30 5. "BK2CMP5E,tim_brk2_cmp5 enable" "0: tim_brk2_cmp5 input disabled,1: tim_brk2_cmp5 input enabled"
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newline
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bitfld.long 0x30 4. "BK2CMP4E,tim_brk2_cmp4 enable" "0: tim_brk2_cmp4 input disabled,1: tim_brk2_cmp4 input enabled"
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bitfld.long 0x30 3. "BK2CMP3E,tim_brk2_cmp3 enable" "0: tim_brk2_cmp3 input disabled,1: tim_brk2_cmp3 input enabled"
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newline
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bitfld.long 0x30 2. "BK2CMP2E,tim_brk2_cmp2 enable" "0: tim_brk2_cmp2 input disabled,1: tim_brk2_cmp2 input enabled"
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bitfld.long 0x30 1. "BK2CMP1E,tim_brk2_cmp1 enable" "0: tim_brk2_cmp1 input disabled,1: tim_brk2_cmp1 input enabled"
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newline
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bitfld.long 0x30 0. "BK2INE,TIMx_BKIN2 input enable" "0: TIMx_BKIN2 input disabled,1: TIMx_BKIN2 input enabled"
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group.long 0x3DC++0x7
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line.long 0x0 "TIM1_DCR,TIM1 DMA control register"
|
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hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
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|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
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|
line.long 0x4 "TIM1_DMAR,TIM1 DMA address for full transfer"
|
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hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
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tree.end
|
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tree "TIM2"
|
|
base ad:0x40000000
|
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group.word 0x0++0x1
|
|
line.word 0x0 "TIM2_CR1,TIM2 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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newline
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bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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|
newline
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
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|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
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|
newline
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bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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|
newline
|
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bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "TIM2_CR2,TIM2 control register 2"
|
|
bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1"
|
|
bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.."
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newline
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bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.."
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|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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|
line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register"
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bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timers Update..,1: The transfer is triggered by the Index event"
|
|
bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled"
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|
newline
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bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
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|
newline
|
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bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
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|
newline
|
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bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
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bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
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bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)"
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newline
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bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf"
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bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0x8 "TIM2_DIER,TIM2 DMA/Interrupt enable register"
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bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled"
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bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled"
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newline
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bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled"
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bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled"
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newline
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bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
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bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
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bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
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bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
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newline
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bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
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bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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newline
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bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
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bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
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newline
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bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
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bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
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newline
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bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
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bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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line.long 0xC "TIM2_SR,TIM2 status register"
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bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected"
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bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected"
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newline
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bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change"
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bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred"
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newline
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bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
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bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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newline
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bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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newline
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bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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newline
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bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
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wgroup.word 0x14++0x1
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line.word 0x0 "TIM2_EGR,TIM2 event generation register"
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bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
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bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
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bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
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newline
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bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
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group.long 0x18++0x3
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line.long 0x0 "TIM2_CCMR1_INPUT,TIM2 capture/compare mode register 1"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
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group.long 0x18++0x7
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line.long 0x0 "TIM2_CCMR1_OUTPUT,TIM2 capture/compare mode register 1"
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bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
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bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
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newline
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bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
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newline
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bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
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line.long 0x4 "TIM2_CCMR2_INPUT,TIM2 capture/compare mode register 2"
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hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
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hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
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bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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group.long 0x1C++0x3
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line.long 0x0 "TIM2_CCMR2_OUTPUT,TIM2 capture/compare mode register 2"
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bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
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bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
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newline
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bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
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newline
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bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
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bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
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bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
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newline
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bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
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bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
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newline
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bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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group.word 0x20++0x1
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line.word 0x0 "TIM2_CCER,TIM2 capture/compare enable register"
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bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
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bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
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newline
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bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
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bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
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newline
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bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
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bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
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newline
|
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bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
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bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
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bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
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newline
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bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: this configuration is reserved,1: non-inverted/both edges"
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bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
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group.long 0x24++0x3
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line.long 0x0 "TIM2_CNT,TIM2 counter"
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bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1"
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hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
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group.word 0x28++0x1
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line.word 0x0 "TIM2_PSC,TIM2 prescaler"
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hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
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group.long 0x2C++0x3
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line.long 0x0 "TIM2_ARR,TIM2 auto-reload register"
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hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value"
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group.long 0x34++0xF
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line.long 0x0 "TIM2_CCR1,TIM2 capture/compare register 1"
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hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value"
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line.long 0x4 "TIM2_CCR2,TIM2 capture/compare register 2"
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hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value"
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line.long 0x8 "TIM2_CCR3,TIM2 capture/compare register 3"
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hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value"
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line.long 0xC "TIM2_CCR4,TIM2 capture/compare register 4"
|
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hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value"
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group.long 0x58++0xF
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line.long 0x0 "TIM2_ECR,TIM2 timer encoder control register"
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bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width"
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newline
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bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11"
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bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter"
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newline
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bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,3: FIELD Reserved"
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bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,3: FIELD Reserved"
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newline
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bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled"
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line.long 0x4 "TIM2_TISEL,TIM2 timer input selection register"
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hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input"
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hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input"
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newline
|
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hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input"
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hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input"
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line.long 0x8 "TIM2_AF1,TIM2 alternate function register 1"
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hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection"
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line.long 0xC "TIM2_AF2,TIM2 alternate function register 2"
|
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bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,?,?,?,?,7: tim_ocref_clr7"
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|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM2_DCR,TIM2 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
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|
newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM2_DMAR,TIM2 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
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|
tree.end
|
|
tree "TIM3"
|
|
base ad:0x40000400
|
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group.word 0x0++0x1
|
|
line.word 0x0 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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|
newline
|
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bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
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|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
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bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
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|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
newline
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bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "TIM3_CR2,TIM3 control register 2"
|
|
bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1"
|
|
bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.."
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|
newline
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bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.."
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|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x4 "TIM3_SMCR,TIM3 slave mode control register"
|
|
bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timers Update..,1: The transfer is triggered by the Index event"
|
|
bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled"
|
|
newline
|
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bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
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bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)"
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newline
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bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf"
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bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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|
line.long 0x8 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
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|
bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled"
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|
bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled"
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|
newline
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bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled"
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|
bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled"
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|
newline
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bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
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bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
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|
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bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
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|
bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
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|
newline
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bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
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|
bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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newline
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bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
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bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
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newline
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bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
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bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
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newline
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bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
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bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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|
line.long 0xC "TIM3_SR,TIM3 status register"
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|
bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected"
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bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected"
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|
newline
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bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change"
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bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred"
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newline
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bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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|
bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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newline
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bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
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|
bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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newline
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bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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newline
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bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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newline
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bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
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wgroup.word 0x14++0x1
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line.word 0x0 "TIM3_EGR,TIM3 event generation register"
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bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
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newline
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bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
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bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
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newline
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bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
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group.long 0x18++0x3
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line.long 0x0 "TIM3_CCMR1_INPUT,TIM3 capture/compare mode register 1"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
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group.long 0x18++0x7
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line.long 0x0 "TIM3_CCMR1_OUTPUT,TIM3 capture/compare mode register 1"
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bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
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bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
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newline
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bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
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newline
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bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
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line.long 0x4 "TIM3_CCMR2_INPUT,TIM3 capture/compare mode register 2"
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hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
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hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
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bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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group.long 0x1C++0x3
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line.long 0x0 "TIM2_CCMR3_OUTPUT,TIM3 capture/compare mode register 2"
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bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
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bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
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newline
|
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bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
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newline
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bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
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bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
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bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
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newline
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bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
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bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
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newline
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bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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group.word 0x20++0x1
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line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register"
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bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
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bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
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bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
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bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
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bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
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|
newline
|
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bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
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bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: this configuration is reserved,1: non-inverted/both edges"
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bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
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group.long 0x24++0x3
|
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line.long 0x0 "TIM3_CNT,TIM3 counter"
|
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bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1"
|
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hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
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group.word 0x28++0x1
|
|
line.word 0x0 "TIM3_PSC,TIM3 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
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group.long 0x2C++0x3
|
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line.long 0x0 "TIM3_ARR,TIM3 auto-reload register"
|
|
hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0xF
|
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line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1"
|
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hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value"
|
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line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2"
|
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hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value"
|
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line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value"
|
|
line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4"
|
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hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "TIM3_ECR,TIM3 timer encoder control register"
|
|
bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width"
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newline
|
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bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11"
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bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter"
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|
newline
|
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bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,3: FIELD Reserved"
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|
bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,3: FIELD Reserved"
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|
newline
|
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bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled"
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line.long 0x4 "TIM3_TISEL,TIM3 timer input selection register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input"
|
|
hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input"
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|
newline
|
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hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input"
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hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input"
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line.long 0x8 "TIM3_AF1,TIM3 alternate function register 1"
|
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hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection"
|
|
line.long 0xC "TIM3_AF2,TIM3 alternate function register 2"
|
|
bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,?,?,?,?,7: tim_ocref_clr7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM3_DCR,TIM3 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM3_DMAR,TIM3 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM4"
|
|
base ad:0x40000800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM4_CR1,TIM4 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "TIM4_CR2,TIM4 control register 2"
|
|
bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1"
|
|
bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.."
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|
newline
|
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bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.."
|
|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x4 "TIM4_SMCR,TIM4 slave mode control register"
|
|
bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timers Update..,1: The transfer is triggered by the Index event"
|
|
bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
|
|
newline
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bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)"
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newline
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bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf"
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bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0x8 "TIM4_DIER,TIM4 DMA/Interrupt enable register"
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|
bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled"
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|
bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled"
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|
newline
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bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled"
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|
bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled"
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|
newline
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bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
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bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
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|
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bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
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|
bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
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|
newline
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bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
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bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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newline
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bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
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bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
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newline
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bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
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bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
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newline
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bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
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bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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line.long 0xC "TIM4_SR,TIM4 status register"
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|
bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected"
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bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected"
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|
newline
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bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change"
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bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred"
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newline
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bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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newline
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bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
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|
bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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|
newline
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bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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|
bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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newline
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bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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newline
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bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
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wgroup.word 0x14++0x1
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|
line.word 0x0 "TIM4_EGR,TIM4 event generation register"
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bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
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newline
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bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
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bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
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|
newline
|
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bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
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group.long 0x18++0x3
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line.long 0x0 "TIM4_CCMR1_INPUT,TIM4 capture/compare mode register 1"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
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|
group.long 0x18++0x7
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line.long 0x0 "TIM4_CCMR1_OUTPUT,TIM4 capture/compare mode register 1"
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bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
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bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
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newline
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bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
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|
newline
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bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
|
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
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line.long 0x4 "TIM4_CCMR2_INPUT,TIM4 capture/compare mode register 2"
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hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
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hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
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bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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group.long 0x1C++0x3
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line.long 0x0 "TIM4_CCMR2_OUTPUT,TIM4 capture/compare mode register 2"
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bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
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bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
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newline
|
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bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
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newline
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bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
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bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
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bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
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newline
|
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bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
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bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
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newline
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bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
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group.word 0x20++0x1
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line.word 0x0 "TIM4_CCER,TIM4 capture/compare enable register"
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bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
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bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
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bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
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bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
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bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
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bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
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bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
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newline
|
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bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: this configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
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group.long 0x24++0x3
|
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line.long 0x0 "TIM4_CNT,TIM4 counter"
|
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bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1"
|
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hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
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group.word 0x28++0x1
|
|
line.word 0x0 "TIM4_PSC,TIM4 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
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group.long 0x2C++0x3
|
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line.long 0x0 "TIM4_ARR,TIM4 auto-reload register"
|
|
hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0xF
|
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line.long 0x0 "TIM4_CCR1,TIM4 capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value"
|
|
line.long 0x4 "TIM4_CCR2,TIM4 capture/compare register 2"
|
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hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value"
|
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line.long 0x8 "TIM4_CCR3,TIM4 capture/compare register 3"
|
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hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value"
|
|
line.long 0xC "TIM4_CCR4,TIM4 capture/compare register 4"
|
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hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "TIM4_ECR,TIM4 timer encoder control register"
|
|
bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width"
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newline
|
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bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11"
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bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter"
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newline
|
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bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,3: FIELD Reserved"
|
|
bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,3: FIELD Reserved"
|
|
newline
|
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bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled"
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line.long 0x4 "TIM4_TISEL,TIM4 timer input selection register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input"
|
|
hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input"
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|
newline
|
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hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input"
|
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hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input"
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line.long 0x8 "TIM4_AF1,TIM4 alternate function register 1"
|
|
hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection"
|
|
line.long 0xC "TIM4_AF2,TIM4 alternate function register 2"
|
|
bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,?,?,?,?,7: tim_ocref_clr7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM4_DCR,TIM4 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM4_DMAR,TIM4 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM5_CR1,TIM5 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering Enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "TIM5_CR2,TIM5 control register 2"
|
|
bitfld.long 0x0 25. "MMS_1,MMS[3]" "0,1"
|
|
bitfld.long 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is to..,1: The tim_ti1_in[15:0] tim_ti2_in[15:0] and.."
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|
newline
|
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bitfld.long 0x0 4.--6. "MMS,MMS[0]: Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,6: Compare - tim_oc3refc signal is used as trigger..,7: Compare - tim_oc4refc signal is used as trigger.."
|
|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x4 "TIM5_SMCR,TIM5 slave mode control register"
|
|
bitfld.long 0x4 25. "SMSPS,SMS preload source" "0: The transfer is triggered by the Timers Update..,1: The transfer is triggered by the Index event"
|
|
bitfld.long 0x4 24. "SMSPE,SMS preload enable" "0: SMS[3:0] bitfield is not preloaded,1: SMS[3:0] preload is enabled"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: tim_etr_in is non-inverted active at high level..,1: tim_etr_in is inverted active at low level or.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: tim_etrp frequency divided by 2,2: tim_etrp frequency divided by 4,3: tim_etrp frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x4 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal trigger 0 (tim_itr0),1: Internal trigger 1 (tim_itr1),2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,3: Internal trigger 3 (tim_itr3),4: tim_ti1 edge detector (tim_ti1f_ed),5: Filtered timer input 1 (tim_ti1fp1),6: Filtered timer input 2 (tim_ti2fp2),7: External trigger input (tim_etrf)"
|
|
newline
|
|
bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: tim_ocref_clr_int is connected to the..,1: tim_ocref_clr_int is connected to tim_etrf"
|
|
bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0x8 "TIM5_DIER,TIM5 DMA/Interrupt enable register"
|
|
bitfld.long 0x8 23. "TERRIE,Transition error interrupt enable" "0: Transition error interrupt disabled,1: Transition error interrupt enabled"
|
|
bitfld.long 0x8 22. "IERRIE,Index error interrupt enable" "0: Index error interrupt disabled,1: Index error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x8 21. "DIRIE,Direction change interrupt enable" "0: Direction change interrupt disabled,1: Direction change interrupt enabled"
|
|
bitfld.long 0x8 20. "IDXIE,Index interrupt enable" "0: Index interrupt disabled,1: Index interrupt enabled"
|
|
newline
|
|
bitfld.long 0x8 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0x8 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0x8 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0x8 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0x8 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0x8 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0x8 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x8 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0x8 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x8 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0x8 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0xC "TIM5_SR,TIM5 status register"
|
|
bitfld.long 0xC 23. "TERRF,Transition error interrupt flag" "0: No encoder transition error has been detected.,1: An encoder transition error has been detected"
|
|
bitfld.long 0xC 22. "IERRF,Index error interrupt flag" "0: No index error has been detected.,1: An index error has been detected"
|
|
newline
|
|
bitfld.long 0xC 21. "DIRF,Direction change interrupt flag" "0: No direction change,1: Direction change"
|
|
bitfld.long 0xC 20. "IDXF,Index interrupt flag" "0: No index event occurred.,1: An index event has occurred"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0xC 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0xC 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0xC 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0xC 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0xC 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0xC 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM5_EGR,TIM5 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM5_CCMR1_INPUT,TIM5 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM5_CCMR1_OUTPUT,TIM5 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
line.long 0x4 "TIM5_CCMR2_INPUT,TIM5 capture/compare mode register 2"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "TIM5_CCMR2_OUTPUT,TIM5 capture/compare mode register 2"
|
|
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input tim_ic4 is..,2: CC4 channel is configured as input tim_ic4 is..,3: CC4 channel is configured as input tim_ic4 is.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input tim_ic3 is..,2: CC3 channel is configured as input tim_ic3 is..,3: CC3 channel is configured as input tim_ic3 is.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM5_CCER,TIM5 capture/compare enable register"
|
|
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: this configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM5_CNT,TIM5 counter"
|
|
bitfld.long 0x0 31. "UIFCPY_CNT,Value depends on IUFREMAP in TIMx_CR1." "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM5_PSC,TIM5 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM5_ARR,TIM5 auto-reload register"
|
|
hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "TIM5_CCR1,TIM5 capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,Capture/compare 1 value"
|
|
line.long 0x4 "TIM5_CCR2,TIM5 capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,Capture/compare 2 value"
|
|
line.long 0x8 "TIM5_CCR3,TIM5 capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,Capture/compare 3 value"
|
|
line.long 0xC "TIM5_CCR4,TIM5 capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,Capture/compare 4 value"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "TIM5_ECR,TIM5 timer encoder control register"
|
|
bitfld.long 0x0 24.--26. "PWPRSC,Pulse width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PW,Pulse width"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IPOS,Index positioning" "0: Index resets the counter when AB = 00,1: Index resets the counter when AB = 01,2: Index resets the counter when AB = 10,3: Index resets the counter when AB = 11"
|
|
bitfld.long 0x0 5. "FIDX,First index" "0: Index is always active,1: the first Index only resets the counter"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "IBLK,Index blanking" "0: Index always active,1: Index disabled hen tim_ti3 input is active as..,2: Index disabled when tim_ti4 input is active as..,3: FIELD Reserved"
|
|
bitfld.long 0x0 1.--2. "IDIR,Index direction" "0: Index resets the counter whatever the direction,1: Index resets the counter when up-counting only,2: Index resets the counter when down-counting only,3: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 0. "IE,Index enable" "0: Index disabled,1: Index enabled"
|
|
line.long 0x4 "TIM5_TISEL,TIM5 timer input selection register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "TI4SEL,Selects tim_ti4[15:0] input"
|
|
hexmask.long.byte 0x4 16.--19. 1. "TI3SEL,Selects tim_ti3[15:0] input"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "TI2SEL,Selects tim_ti2[15:0] input"
|
|
hexmask.long.byte 0x4 0.--3. 1. "TI1SEL,Selects tim_ti1[15:0] input"
|
|
line.long 0x8 "TIM5_AF1,TIM5 alternate function register 1"
|
|
hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,etr_in source selection"
|
|
line.long 0xC "TIM5_AF2,TIM5 alternate function register 2"
|
|
bitfld.long 0xC 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM2/TIM3/TIM4/TIM5 pins and internal signals..,?,?,?,?,7: tim_ocref_clr7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM5_DCR,TIM5 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM5_DMAR,TIM5 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM6"
|
|
base ad:0x40001000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM6_CR1,TIM6 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM6_CR2,TIM6 control register 2"
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM6_DIER,TIM6 DMA/Interrupt enable register"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM6_SR,TIM6 status register"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM6_EGR,TIM6 event generation register"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM6_CNT,TIM6 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM6_PSC,TIM6 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM6_ARR,TIM6 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
tree.end
|
|
tree "TIM7"
|
|
base ad:0x40001400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM7_CR1,TIM7 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM7_CR2,TIM7 control register 2"
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal tim_cnt_en is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM7_DIER,TIM7 DMA/Interrupt enable register"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM7_SR,TIM7 status register"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM7_EGR,TIM7 event generation register"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM7_CNT,TIM7 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM7_PSC,TIM7 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM7_ARR,TIM7 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
tree.end
|
|
tree "TIM9"
|
|
base ad:0x42004C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM9_CR1,TIM9 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM9_CR2,TIM12 control register 2"
|
|
bitfld.word 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].."
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM9_SMCR,TIM9 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM9_DIER,TIM9 Interrupt enable register"
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM9_SR,TIM9 status register"
|
|
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM9_EGR,TIM9 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register."
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM9_CCMR1_INPUT,TIM9 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM9_CCMR1_OUTPUT,TIM9 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low,5: Force active level - tim_oc1ref is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM9_CCER,TIM9 capture/compare enable register"
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM9_CNT,TIM9 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM9_PSC,TIM9 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM9_ARR,TIM9 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "TIM9_CCR1,TIM9 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value"
|
|
line.long 0x4 "TIM9_CCR2,TIM9 capture/compare register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM9_TISEL,TIM9 timer input selection register"
|
|
hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
tree.end
|
|
tree "TIM12"
|
|
base ad:0x40001800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM12_CR1,TIM12 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM12_CR2,TIM12 control register 2"
|
|
bitfld.word 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].."
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM12_SMCR,TIM12 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: Internal Trigger 2 (tim_itr2),3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM12_DIER,TIM12 Interrupt enable register"
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM12_SR,TIM12 status register"
|
|
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM12_EGR,TIM12 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register."
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM12_CCMR1_INPUT,TIM12 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM12_CCMR1_OUTPUT,TIM12 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low,5: Force active level - tim_oc1ref is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM12_CCER,TIM12 capture/compare enable register"
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM12_CNT,TIM12 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM12_PSC,TIM12 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM12_ARR,TIM12 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "TIM12_CCR1,TIM12 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value"
|
|
line.long 0x4 "TIM12_CCR2,TIM12 capture/compare register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM12_TISEL,TIM12 timer input selection register"
|
|
hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
tree.end
|
|
tree "TIM13"
|
|
base ad:0x40001C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM13_CR1,TIM13 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM13_DIER,TIM13 Interrupt enable register"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM13_SR,TIM13 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM13_EGR,TIM13 event generation register"
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM13_CCMR1_INPUT,TIM13 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: FIELD Reserved,3: FIELD Reserved"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM13_CCMR1_OUTPUT,TIM13 capture/compare mode register 1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: Reserved.,3: Reserved."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM13_CCER,TIM13 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM13_CNT,TIM13 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM13_PSC,TIM13 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM13_ARR,TIM13 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "TIM13_CCR1,TIM13 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM13_TISEL,TIM13 timer input selection register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
tree.end
|
|
tree "TIM14"
|
|
base ad:0x40002000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM14_CR1,TIM14 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2 t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4 t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM14_DIER,TIM14 Interrupt enable register"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM14_SR,TIM14 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM14_EGR,TIM14 event generation register"
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM14_CCMR1_INPUT,TIM14 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: FIELD Reserved,3: FIELD Reserved"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM14_CCMR1_OUTPUT,TIM14 capture/compare mode register 1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when TIMx_CNT =..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: Reserved.,3: Reserved."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM14_CCER,TIM14 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / tim_oc1 is not active,1: Capture mode enabled / tim_oc1 signal is output.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM14_CNT,TIM14 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM14_PSC,TIM14 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM14_ARR,TIM14 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "TIM14_CCR1,TIM14 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM14_TISEL,TIM14 timer input selection register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
tree.end
|
|
tree "TIM15"
|
|
base ad:0x42004000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM15_CR1,TIM15 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS </sub>= t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub> = 2*t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub> = 4*t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIM15_ARR register is not buffered,1: TIM15_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM15_CR2,TIM15 control register 2"
|
|
bitfld.word 0x0 10. "OIS2,Output idle state 2 (tim_oc2 output)" "0: tim_oc2=0 when MOE=0,1: tim_oc2=1 when MOE=0"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 7. "TI1S,tim_ti1 selection" "0: The tim_ti1_in[15:0] multiplexer output is..,1: The tim_ti1_in[15:0] and tim_ti2_in[15:0].."
|
|
newline
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIM15_EGR register..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - tim_oc1refc signal is used as trigger..,5: Compare - tim_oc2refc signal is used as trigger..,?,?"
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM15_SMCR,TIM15 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (tim_itr0),1: Internal Trigger 1 (tim_itr1),2: TIM15/TIM16/TIM17 pins and internal signals for..,3: Internal Trigger 3 (tim_itr3),4: tim_ti1 Edge Detector (tim_ti1f_ed),5: Filtered Timer Input 1 (tim_ti1fp1),6: Filtered Timer Input 2 (tim_ti2fp2),7: FIELD Reserved"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: FIELD Reserved,2: FIELD Reserved,3: FIELD Reserved,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM15_SR,TIM15 status register"
|
|
bitfld.word 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in.."
|
|
newline
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "TIM15_EGR,TIM15 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIM15_SR register."
|
|
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|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
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|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: If channel CC1 is configured as output:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM15_CCMR1_INPUT,TIM15 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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|
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|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input tim_ic2 is..,2: CC2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
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|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM15_CCMR1_OUTPUT,TIM15 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
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|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
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|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: C2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
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|
newline
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|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIM15_CCR1 disabled.,1: Preload register on TIM15_CCR1 enabled."
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|
newline
|
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable register"
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low"
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|
newline
|
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bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.."
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM15_CNT,TIM15 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM15_PSC,TIM15 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM15_ARR,TIM15 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
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|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM15_RCR,TIM15 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value"
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|
group.long 0x34++0x7
|
|
line.long 0x0 "TIM15_CCR1,TIM15 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/compare 1 value"
|
|
line.long 0x4 "TIM15_CCR2,TIM15 capture/compare register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CCR2,Capture/compare 2 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM15_BDTR,TIM15 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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|
bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_ocx and tim_ocxn outputs are disabled or..,1: tim_ocx and tim_ocxn outputs are enabled if.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high"
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|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk clock..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_ocx/tim_ocxn outputs are..,1: When inactive tim_ocx/tim_ocxn outputs are.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_ocx/tim_ocxn outputs are..,1: When inactive tim_ocx/tim_ocxn outputs are.."
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|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIM15_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: OCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "TIM15_DTR2,TIM15 timer deadtime register 2"
|
|
bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled"
|
|
bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "TIM15_TISEL,TIM15 input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects tim_ti2_in[15:0] input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
line.long 0x4 "TIM15_AF1,TIM15 alternate function register 1"
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|
bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low"
|
|
bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low"
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|
newline
|
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bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low"
|
|
bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low"
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|
newline
|
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bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low"
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|
bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled"
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|
newline
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bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled"
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|
bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled"
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newline
|
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bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled"
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|
bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled"
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newline
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bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled"
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|
bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled"
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|
newline
|
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bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled"
|
|
bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled"
|
|
line.long 0x8 "TIM15_AF2,TIM15 alternate function register 2"
|
|
bitfld.long 0x8 16.--18. "OCRSEL,ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM15/TIM16/TIM17 pins and internal signals for..,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM15_DCR,TIM15 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM15_DMAR,TIM15 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM16"
|
|
base ad:0x42004400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM16_CR1,TIM16 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub>=t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub>=2*t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub>=4*t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: nly counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM16_CR2,TIM16 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM16_SR,TIM16 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM16_EGR,TIM16 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_INPUT,TIM16 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_OUTPUT,TIM16 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: C2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIM15_CCR1 disabled.,1: Preload register on TIM15_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM16_CNT,TIM16 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM16_PSC,TIM16 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM16_ARR,TIM16 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM16_RCR,TIM16 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "TIM16_CCR1,TIM16 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_oc1 and tim_oc1n outputs are disabled or..,1: tim_oc1 and tim_oc1n outputs are enabled if.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "TIM16_DTR2,TIM16 timer deadtime register 2"
|
|
bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled"
|
|
bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "TIM16_TISEL,TIM16 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
line.long 0x4 "TIM16_AF1,TIM16 alternate function register 1"
|
|
bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low"
|
|
bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low"
|
|
newline
|
|
bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low"
|
|
bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low"
|
|
newline
|
|
bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low"
|
|
bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled"
|
|
bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled"
|
|
bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled"
|
|
bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled"
|
|
bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled"
|
|
line.long 0x8 "TIM16_AF2,TIM16 alternate function register 2"
|
|
bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM15/TIM16/TIM17 pins and internal signals for..,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM16_DCR,TIM16 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM16_DMAR,TIM16/TIM17 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM17"
|
|
base ad:0x42004800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM17_CR1,TIM17 control register 1"
|
|
bitfld.word 0x0 12. "DITHEN,Dithering enable" "0: Dithering disabled,1: Dithering enabled"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub>=t<sub>tim_ker_ck</sub>,1: t<sub>DTS</sub>=2*t<sub>tim_ker_ck</sub>,2: t<sub>DTS</sub>=4*t<sub>tim_ker_ck</sub>,3: FIELD Reserved"
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: nly counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM17_CR2,TIM17 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (tim_oc1n output)" "0: tim_oc1n=0 after a dead-time when MOE=0,1: tim_oc1n=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (tim_oc1 output)" "0: tim_oc1=0 after a dead-time when MOE=0,1: tim_oc1=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM17_DIER,TIM17 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM17_SR,TIM17 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM17_EGR,TIM17 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM17_CCMR1_INPUT,TIM17 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input tim_ic1 is..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM17_CCMR1_OUTPUT,TIM17 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input tim_ic2 is..,2: C2 channel is configured as input tim_ic2 is..,3: CC2 channel is configured as input tim_ic2 is.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: tim_oc1ref is not affected by the..,1: tim_oc1ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - tim_oc1ref toggles when..,4: Force inactive level - tim_oc1ref is forced low.,5: Force active level - tim_oc1ref is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIM15_CCR1 disabled.,1: Preload register on TIM15_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input tim_ic1 is..,2: CC1 channel is configured as input tim_ic1 is..,3: CC1 channel is configured as input tim_ic1 is.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM17_CCER,TIM17 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: tim_oc1n active high,1: tim_oc1n active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - tim_oc1n is not active. tim_oc1n level is..,1: On - tim_oc1n signal is output on the.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM17_CNT,TIM17 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM17_PSC,TIM17 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM17_ARR,TIM17 auto-reload register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM17_RCR,TIM17 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "TIM17_CCR1,TIM17 capture/compare register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM17_BDTR,TIM17 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input tim_brk in input mode,1: Break input tim_brk in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input tim_brk is armed,1: Break input tim_brk is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: tim_oc1 and tim_oc1n outputs are disabled or..,1: tim_oc1 and tim_oc1n outputs are enabled if.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input tim_brk is active low,1: Break input tim_brk is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (tim_brk and tim_sys_brk event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive tim_oc1/tim_oc1n outputs are..,1: When inactive tim_oc1/tim_oc1n outputs are.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "TIM17_DTR2,TIM17 timer deadtime register 2"
|
|
bitfld.long 0x0 17. "DTPE,Deadtime preload enable" "0: Deadtime value is not preloaded,1: Deadtime value preload is enabled"
|
|
bitfld.long 0x0 16. "DTAE,Deadtime asymmetric enable" "0: Deadtime on rising and falling edges are..,1: Deadtime on rising edge is defined with DTG[7:0].."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "TIM17_TISEL,TIM17 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects tim_ti1_in[15:0] input"
|
|
line.long 0x4 "TIM17_AF1,TIM17 alternate function register 1"
|
|
bitfld.long 0x4 13. "BKCMP4P,tim_brk_cmp4 input polarity" "0: tim_brk_cmp4 input is active high,1: tim_brk_cmp4 input is active low"
|
|
bitfld.long 0x4 12. "BKCMP3P,tim_brk_cmp3 input polarity" "0: tim_brk_cmp3 input is active high,1: tim_brk_cmp3 input is active low"
|
|
newline
|
|
bitfld.long 0x4 11. "BKCMP2P,tim_brk_cmp2 input polarity" "0: tim_brk_cmp2 input is active high,1: tim_brk_cmp2 input is active low"
|
|
bitfld.long 0x4 10. "BKCMP1P,tim_brk_cmp1 input polarity" "0: tim_brk_cmp1 input is active high,1: tim_brk_cmp1 input is active low"
|
|
newline
|
|
bitfld.long 0x4 9. "BKINP,TIMx_BKIN input polarity" "0: TIMx_BKIN input is active high,1: TIMx_BKIN input is active low"
|
|
bitfld.long 0x4 8. "BKCMP8E,tim_brk_cmp8 enable" "0: tim_brk_cmp8 input disabled,1: tim_brk_cmp8 input enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "BKCMP7E,tim_brk_cmp7 enable" "0: tim_brk_cmp7 input disabled,1: tim_brk_cmp7 input enabled"
|
|
bitfld.long 0x4 6. "BKCMP6E,tim_brk_cmp6 enable" "0: tim_brk_cmp6 input disabled,1: tim_brk_cmp6 input enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "BKCMP5E,tim_brk_cmp5 enable" "0: tim_brk_cmp5 input disabled,1: tim_brk_cmp5 input enabled"
|
|
bitfld.long 0x4 4. "BKCMP4E,tim_brk_cmp4 enable" "0: tim_brk_cmp4 input disabled,1: tim_brk_cmp4 input enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "BKCMP3E,tim_brk_cmp3 enable" "0: tim_brk_cmp3 input disabled,1: tim_brk_cmp3 input enabled"
|
|
bitfld.long 0x4 2. "BKCMP2E,tim_brk_cmp2 enable" "0: tim_brk_cmp2 input disabled,1: tim_brk_cmp2 input enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "BKCMP1E,tim_brk_cmp1 enable" "0: tim_brk_cmp1 input disabled,1: tim_brk_cmp1 input enabled"
|
|
bitfld.long 0x4 0. "BKINE,TIMx_BKIN input enable" "0: TIMx_BKIN input disabled,1: TIMx_BKIN input enabled"
|
|
line.long 0x8 "TIM17_AF2,TIM17 alternate function register 2"
|
|
bitfld.long 0x8 16.--18. "OCRSEL,tim_ocref_clr source selection" "0: tim_ocref_clr0,1: tim_ocref_clr1,2: TIM15/TIM16/TIM17 pins and internal signals for..,3: tim_ocref_clr3,4: tim_ocref_clr4,5: tim_ocref_clr5,6: tim_ocref_clr6,7: tim_ocref_clr7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "TIM17_DCR,TIM17 DMA control register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DBSS,DMA burst source selection"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "TIM17_DMAR,TIM16/TIM17 DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree.end
|
|
tree "UCPD (USB Type-C/USB Power Delivery Interface)"
|
|
base ad:0x4000EC00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock"
|
|
line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2"
|
|
bitfld.long 0x4 8. "RXAFILTEN,Rx analog filter enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request"
|
|
bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples"
|
|
newline
|
|
bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "UCPD_CR,UCPD control register"
|
|
bitfld.long 0x0 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable"
|
|
bitfld.long 0x0 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x0 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive"
|
|
bitfld.long 0x0 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY"
|
|
newline
|
|
bitfld.long 0x0 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink"
|
|
bitfld.long 0x0 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication"
|
|
bitfld.long 0x0 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)"
|
|
bitfld.long 0x0 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message"
|
|
newline
|
|
bitfld.long 0x0 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission"
|
|
bitfld.long 0x0 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?"
|
|
line.long 0x4 "UCPD_IMR,UCPD interrupt mask register"
|
|
rbitfld.long 0x4 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1"
|
|
bitfld.long 0x4 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "UCPD_SR,UCPD status register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest"
|
|
bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event"
|
|
bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received"
|
|
bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received"
|
|
bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty"
|
|
bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent"
|
|
bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort"
|
|
bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded"
|
|
bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "UCPD_ICR,UCPD interrupt clear register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit"
|
|
line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit"
|
|
line.long 0x8 "UCPD_TXDR,UCPD Tx data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No code corrupted,1: First code corrupted,2: Second code corrupted,3: Third code corrupted,4: Fourth code corrupted,?,?,?"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct codes. For debug purposes only." "0: 4 correct codes out of 4,1: 3 correct codes out of 4"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver"
|
|
line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received"
|
|
line.long 0x8 "UCPD_RXDR,UCPD receive data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received"
|
|
line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received"
|
|
tree.end
|
|
tree "USART (Universal Synchronous Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
tree "UART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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newline
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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newline
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "UART5"
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base ad:0x40005000
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
|
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
|
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
|
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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|
line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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newline
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
|
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tree "UART7"
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base ad:0x40007800
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
|
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
|
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tree "UART8"
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base ad:0x40007C00
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART1"
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base ad:0x42001000
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
|
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART2"
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base ad:0x40004400
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
|
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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newline
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|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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newline
|
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
|
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
|
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
|
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newline
|
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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newline
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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newline
|
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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newline
|
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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newline
|
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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newline
|
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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newline
|
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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newline
|
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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newline
|
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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newline
|
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
|
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
|
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line.long 0x0 "USART_RQR,USART request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
|
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
|
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
|
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
|
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
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rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
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newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART3"
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base ad:0x40004800
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1_ENABLED,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_DISABLED,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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|
newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
|
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
|
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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newline
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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newline
|
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
|
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
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newline
|
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
|
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
|
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
|
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
|
|
newline
|
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bitfld.long 0x8 21. "WUS1,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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|
bitfld.long 0x8 20. "WUS0,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
|
|
newline
|
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 4549,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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newline
|
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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newline
|
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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newline
|
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
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|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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newline
|
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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newline
|
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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newline
|
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
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newline
|
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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newline
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
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line.long 0xC "USART_BRR,USART baud rate register"
|
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
|
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line.long 0x0 "USART_RQR,USART request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
|
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
|
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ENABLED,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
|
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
|
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_DISABLED,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree.end
|
|
tree "VREFBUF (Voltage Reference Buffer)"
|
|
base ad:0x58003C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register"
|
|
bitfld.long 0x0 4.--6. "VRS,Voltage reference scale" "0: VREFBUF0 voltage selected,1: VREFBUF1 voltage selected,?,?,?,?,?,?"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: V<sub>REF+</sub> pin is internally connected to..,1: V<sub>REF+</sub> pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
tree.end
|
|
tree "WWDG (Window Watchdog)"
|
|
base ad:0x40002C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base The time base of the" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1"
|
|
tree.end
|
|
tree "XSPI (Extended-SPI Interface)"
|
|
base ad:0x0
|
|
tree "XSPI1"
|
|
base ad:0x52005000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "XSPI_CR,XSPI control register"
|
|
bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]"
|
|
bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode"
|
|
newline
|
|
bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active"
|
|
bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.."
|
|
newline
|
|
bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.."
|
|
bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level"
|
|
bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.."
|
|
bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode"
|
|
newline
|
|
bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested"
|
|
bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1"
|
|
bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time"
|
|
bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)."
|
|
newline
|
|
bitfld.long 0x0 0. "CKMODE,clock mode 0/mode 3" "0: CLK must stay low while NCS is high (chip-select..,1: CLK must stay high while NCS is high.."
|
|
line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2"
|
|
bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler"
|
|
line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer"
|
|
line.long 0xC "XSPI_DCR4,XSPI device configuration register 4"
|
|
hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "XSPI_SR,XSPI status register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level"
|
|
bitfld.long 0x0 5. "BUSY,Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TOF,Timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "SMF,Status match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "XSPI_FCR,XSPI flag clear register"
|
|
bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "XSPI_DLR,XSPI data length register"
|
|
hexmask.long 0x0 0.--31. 1. "DL,Data length"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "XSPI_AR,XSPIaddress register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDRESS,Address"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "XSPI_DR,XSPI data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Status mask"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "XSPI_PSMAR,XSPI polling status match register"
|
|
hexmask.long 0x0 0.--31. 1. "MATCH,Status match"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XSPI_PIR,XSPI polling interval register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "XSPI_CCR,XSPI communication configuration register"
|
|
bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?"
|
|
bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes"
|
|
newline
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase"
|
|
bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address"
|
|
bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?"
|
|
bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction"
|
|
newline
|
|
bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase"
|
|
bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "XSPI_TCR,XSPI timing configuration register"
|
|
bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift"
|
|
bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "XSPI_IR,XSPI instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "XSPI_ABR,XSPI alternate bytes register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register"
|
|
bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?"
|
|
bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes"
|
|
newline
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase"
|
|
bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,7: DATA reserved"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address"
|
|
bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?"
|
|
bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction"
|
|
newline
|
|
bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase"
|
|
bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register"
|
|
bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift"
|
|
bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register"
|
|
bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,7: DATA reserved"
|
|
bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes"
|
|
newline
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase"
|
|
bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address"
|
|
bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?"
|
|
bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction"
|
|
newline
|
|
bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase"
|
|
bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "XSPI_WIR,XSPI write instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "XSPI_WABR,XSPI write alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time"
|
|
newline
|
|
bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses"
|
|
bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration"
|
|
bitfld.long 0x0 31. "CALMAX,Max value" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
tree.end
|
|
tree "XSPI2"
|
|
base ad:0x5200A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "XSPI_CR,XSPI control register"
|
|
bitfld.long 0x0 30.--31. "MSEL,Flash select" "0: data exchanged over IO[3:0],1: data exchanged over IO[7:4],2: data exchanged over IO[11:8],3: data exchanged over IO[15:12]"
|
|
bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0: indirect-write mode,1: indirect-read mode,2: automatic status-polling mode,3: memory-mapped mode"
|
|
newline
|
|
bitfld.long 0x0 24. "CSSEL,chip select selection" "0: NCS1 active,1: NCS2 active"
|
|
bitfld.long 0x0 23. "PMM,Polling match mode" "0: AND-match mode SMF is set if all the unmasked..,1: OR-match mode SMF is set if any of the unmasked.."
|
|
newline
|
|
bitfld.long 0x0 22. "APMS,Automatic status-polling mode stop" "0: Automatic status-polling mode is stopped only by..,1: Automatic status-polling mode stops as soon as.."
|
|
bitfld.long 0x0 20. "TOIE,Timeout interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "FTHRES,FIFO threshold level"
|
|
bitfld.long 0x0 6. "DMM,Dual-memory configuration" "0: dual-memory configuration disabled,1: dual-memory configuration enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0: timeout counter is disabled and thus the..,1: timeout counter is enabled and thus the.."
|
|
bitfld.long 0x0 2. "DMAEN,DMA enable" "0: DMA disabled for indirect mode,1: DMA enabled for indirect mode"
|
|
newline
|
|
bitfld.long 0x0 1. "ABORT,Abort request" "0: no abort requested,1: abort requested"
|
|
bitfld.long 0x0 0. "EN,Enable" "0: XSPI disabled,1: XSPI enabled"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "XSPI_DCR1,XSPI device configuration register 1"
|
|
bitfld.long 0x0 24.--26. "MTYP,Memory type" "0: Micron mode D0/D1 ordering in DTR 8-data-bit..,1: Macronix mode D1/D0 ordering in DTR 8-data-bit..,2: Standard mode,3: Macronix RAM mode D1/D0 ordering in DTR..,4: HyperBus memory mode the protocol follows the..,5: HyperBus register mode addressing register..,?,?"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time"
|
|
bitfld.long 0x0 1. "FRCK,Free running clock" "0: CLK is not free running.,1: CLK is free running (always provided)."
|
|
newline
|
|
bitfld.long 0x0 0. "CKMODE,clock mode 0/mode 3" "0: CLK must stay low while NCS is high (chip-select..,1: CLK must stay high while NCS is high.."
|
|
line.long 0x4 "XSPI_DCR2,XSPI device configuration register 2"
|
|
bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0: wrapped reads are not supported by the memory.,?,2: external memory supports wrap size of 16 bytes.,3: external memory supports wrap size of 32 bytes.,4: external memory supports wrap size of 64 bytes.,5: external memory supports wrap size of 128 bytes.,?,?"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler"
|
|
line.long 0x8 "XSPI_DCR3,XSPI device configuration register 3"
|
|
hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,NCS boundary"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer"
|
|
line.long 0xC "XSPI_DCR4,XSPI device configuration register 4"
|
|
hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "XSPI_SR,XSPI status register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FLEVEL,FIFO level"
|
|
bitfld.long 0x0 5. "BUSY,Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TOF,Timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "SMF,Status match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "XSPI_FCR,XSPI flag clear register"
|
|
bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "XSPI_DLR,XSPI data length register"
|
|
hexmask.long 0x0 0.--31. 1. "DL,Data length"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "XSPI_AR,XSPIaddress register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDRESS,Address"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "XSPI_DR,XSPI data register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "XSPI_PSMKR,XSPI polling status mask register"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Status mask"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "XSPI_PSMAR,XSPI polling status match register"
|
|
hexmask.long 0x0 0.--31. 1. "MATCH,Status match"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XSPI_PIR,XSPI polling interval register"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "XSPI_CCR,XSPI communication configuration register"
|
|
bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: data on 16 lines,?,?"
|
|
bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes"
|
|
newline
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase"
|
|
bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address"
|
|
bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?"
|
|
bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction"
|
|
newline
|
|
bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase"
|
|
bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "XSPI_TCR,XSPI timing configuration register"
|
|
bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift"
|
|
bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no delay hold,1: 1/4 cycle hold"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "XSPI_IR,XSPI instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "XSPI_ABR,XSPI alternate bytes register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "XSPI_LPTR,XSPI low-power timeout register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "XSPI_WPCCR,XSPI wrap communication configuration register"
|
|
bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
bitfld.long 0x0 27. "DDTR,Data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,?,?,?"
|
|
bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes"
|
|
newline
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer rate" "0: DTR mode disabled for alternate bytes phase,1: DTR mode enabled for alternate bytes phase"
|
|
bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,5: alternate bytes on 16 lines,?,7: DATA reserved"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address"
|
|
bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?"
|
|
bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction"
|
|
newline
|
|
bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase"
|
|
bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?"
|
|
group.long 0x148++0x3
|
|
line.long 0x0 "XSPI_WPTCR,XSPI wrap timing configuration register"
|
|
bitfld.long 0x0 30. "SSHIFT,Sample shift" "0: no shift,1: 1/2 cycle shift"
|
|
bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0: no quarter cycle delay,1: quarter cycle delay inserted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "XSPI_WPIR,XSPI wrap instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "XSPI_WPABR,XSPI wrap alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "XSPI_WCCR,XSPI write communication configuration register"
|
|
bitfld.long 0x0 29. "DQSE,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
bitfld.long 0x0 27. "DDTR,data double transfer rate" "0: DTR mode disabled for data phase,1: DTR mode enabled for data phase"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "DMODE,Data mode" "0: no data,1: data on a single line,2: data on two lines,3: data on four lines,4: data on eight lines,5: Data on 16 lines,?,7: DATA reserved"
|
|
bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0: 8-bit alternate bytes,1: 16-bit alternate bytes,2: 24-bit alternate bytes,3: 32-bit alternate bytes"
|
|
newline
|
|
bitfld.long 0x0 19. "ABDTR,Alternate bytes double-transfer rate" "0: DTR mode disabled for alternate-bytes phase,1: DTR mode enabled for alternate-bytes phase"
|
|
bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0: no alternate bytes,1: alternate bytes on a single line,2: alternate bytes on two lines,3: alternate bytes on four lines,4: alternate bytes on eight lines,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0: 8-bit address,1: 16-bit address,2: 24-bit address,3: 32-bit address"
|
|
bitfld.long 0x0 11. "ADDTR,Address double transfer rate" "0: DTR mode disabled for address phase,1: DTR mode enabled for address phase"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0: no address,1: address on a single line,2: address on two lines,3: address on four lines,4: address on eight lines,?,?,?"
|
|
bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0: 8-bit instruction,1: 16-bit instruction,2: 24-bit instruction,3: 32-bit instruction"
|
|
newline
|
|
bitfld.long 0x0 3. "IDTR,Instruction double transfer rate" "0: DTR mode disabled for instruction phase,1: DTR mode enabled for instruction phase"
|
|
bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0: no instruction,1: instruction on a single line,2: instruction on two lines,3: instruction on four lines,4: instruction on eight lines,?,?,?"
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "XSPI_WTCR,XSPI write timing configuration register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles"
|
|
group.long 0x190++0x3
|
|
line.long 0x0 "XSPI_WIR,XSPI write instruction register"
|
|
hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "XSPI_WABR,XSPI write alternate byte register"
|
|
hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "XSPI_HLCR,XSPI HyperBus latency configuration register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time"
|
|
newline
|
|
bitfld.long 0x0 1. "WZL,Write zero latency" "0: latency on write accesses,1: no latency on write accesses"
|
|
bitfld.long 0x0 0. "LM,Latency mode" "0: Variable initial latency,1: Fixed latency"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "XSPI_CALFCR,XSPI full-cycle calibration configuration"
|
|
bitfld.long 0x0 31. "CALMAX,Max value" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "XSPI_CALMR,XSPI DLL master calibration configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "XSPI_CALSOR,XSPI DLL slave output calibration configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "XSPI_CALSIR,XSPI DLL slave input calibration configuration"
|
|
hexmask.long.byte 0x0 16.--20. 1. "COARSE,Coarse calibration"
|
|
hexmask.long.byte 0x0 0.--6. 1. "FINE,Fine calibration"
|
|
tree.end
|
|
tree "XSPIM1"
|
|
base ad:0x5200B400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "XSPIM_CR,XSPIM control register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK time"
|
|
bitfld.long 0x0 6. "CSSEL_OVR_O2,Chip select selector override setting for XSPI2" "0,1"
|
|
bitfld.long 0x0 5. "CSSEL_OVR_O1,Chip select selector override setting for XSPI1" "0,1"
|
|
bitfld.long 0x0 4. "CSSEL_OVR_EN,Chip select selector override enable" "0,1"
|
|
bitfld.long 0x0 1. "MODE,XSPI multiplexing mode" "0,1"
|
|
bitfld.long 0x0 0. "MUXEN,Multiplexed mode enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.OFF
|